/*
 * Copyright 2018-2025 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

/***********************************************************************************************************************
 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
 **********************************************************************************************************************/

#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_

/*!
 * @addtogroup pin_mux
 * @{
 */

/***********************************************************************************************************************
 * API
 **********************************************************************************************************************/

#if defined(__cplusplus)
extern "C" {
#endif

/*!
 * @brief Calls initialization functions.
 *
 */
void BOARD_InitBootPins(void);

#define IOPCTL_PIO_ANAMUX_DI 0x00u        /*!<@brief Analog mux is disabled */
#define IOPCTL_PIO_FULLDRIVE_DI 0x00u     /*!<@brief Normal drive */
#define IOPCTL_PIO_FULLDRIVE_EN 0x0100u   /*!<@brief Full drive enable */
#define IOPCTL_PIO_FUNC0 0x00u            /*!<@brief Selects pin function 0 */
#define IOPCTL_PIO_FUNC1 0x01u            /*!<@brief Selects pin function 1 */
#define IOPCTL_PIO_INBUF_DI 0x00u         /*!<@brief Disable input buffer function */
#define IOPCTL_PIO_INBUF_EN 0x40u         /*!<@brief Enables input buffer function */
#define IOPCTL_PIO_INV_DI 0x00u           /*!<@brief Input function is not inverted */
#define IOPCTL_PIO_PSEDRAIN_DI 0x00u      /*!<@brief Pseudo Output Drain is disabled */
#define IOPCTL_PIO_PULLDOWN_EN 0x00u      /*!<@brief Enable pull-down function */
#define IOPCTL_PIO_PULLUP_EN 0x20u        /*!<@brief Enable pull-up function */
#define IOPCTL_PIO_PUPD_DI 0x00u          /*!<@brief Disable pull-up / pull-down function */
#define IOPCTL_PIO_PUPD_EN 0x10u          /*!<@brief Enable pull-up / pull-down function */
#define IOPCTL_PIO_SLEW_RATE_NORMAL 0x00u /*!<@brief Normal mode */

/*! @name FC1_SCK (coord J2), U34[3]/I2S_BCLK_CODEC
  @{ */
/* Routed pin properties */
#define BOARD_INITPINS_Fc1_BICK_PERIPHERAL FLEXCOMM1               /*!<@brief Peripheral name */
#define BOARD_INITPINS_Fc1_BICK_SIGNAL SCK                         /*!<@brief Signal name */
#define BOARD_INITPINS_Fc1_BICK_PORT 0U                            /*!<@brief PORT peripheral base pointer */
#define BOARD_INITPINS_Fc1_BICK_PIN 7U                             /*!<@brief PORT pin number */
#define BOARD_INITPINS_Fc1_BICK_PIN_MASK (1U << 7U)                /*!<@brief PORT pin mask */
                                                                   /* @} */

/*! @name FC1_TXD_SCL_MISO_WS (coord K4), U34[2]/I2S_WS_CODEC
  @{ */
/* Routed pin properties */
#define BOARD_INITPINS_Fc1_LRCK_PERIPHERAL FLEXCOMM1               /*!<@brief Peripheral name */
#define BOARD_INITPINS_Fc1_LRCK_SIGNAL TXD_SCL_MISO_WS             /*!<@brief Signal name */
#define BOARD_INITPINS_Fc1_LRCK_PORT 0U                            /*!<@brief PORT peripheral base pointer */
#define BOARD_INITPINS_Fc1_LRCK_PIN 8U                             /*!<@brief PORT pin number */
#define BOARD_INITPINS_Fc1_LRCK_PIN_MASK (1U << 8U)                /*!<@brief PORT pin mask */
                                                                   /* @} */

/*! @name FC1_RXD_SDA_MOSI_DATA (coord L3), JP8[2]/J47[3]/I2S_DAI_CODEC
  @{ */
/* Routed pin properties */
#define BOARD_INITPINS_Fc1_TxData_PERIPHERAL FLEXCOMM1                /*!<@brief Peripheral name */
#define BOARD_INITPINS_Fc1_TxData_SIGNAL RXD_SDA_MOSI_DATA            /*!<@brief Signal name */
#define BOARD_INITPINS_Fc1_TxData_PORT 0U                             /*!<@brief PORT peripheral base pointer */
#define BOARD_INITPINS_Fc1_TxData_PIN 9U                              /*!<@brief PORT pin number */
#define BOARD_INITPINS_Fc1_TxData_PIN_MASK (1U << 9U)                 /*!<@brief PORT pin mask */
                                                                      /* @} */

/*! @name FC3_RXD_SDA_MOSI_DATA (coord C9), JP7[2]/J19[16]/J38[28]/I2S_DAO_CODEC
  @{ */
/* Routed pin properties */
/*!
 * @brief Peripheral name */
#define BOARD_INITPINS_Fc3_TxData_PERIPHERAL FLEXCOMM3
/*!
 * @brief Signal name */
#define BOARD_INITPINS_Fc3_TxData_SIGNAL RXD_SDA_MOSI_DATA
/*!
 * @brief PORT peripheral base pointer */
#define BOARD_INITPINS_Fc3_TxData_PORT 0U
/*!
 * @brief PORT pin number */
#define BOARD_INITPINS_Fc3_TxData_PIN 23U
/*!
 * @brief PORT pin mask */
#define BOARD_INITPINS_Fc3_TxData_PIN_MASK (1U << 23U)
/* @} */

/*! @name MCLK (coord K16), J27[6]/U35[8]/MCLK_CODEC
  @{ */
/* Routed pin properties */
#define BOARD_INITPINS_MCLK_PERIPHERAL SYSCON                  /*!<@brief Peripheral name */
#define BOARD_INITPINS_MCLK_SIGNAL MCLK                        /*!<@brief Signal name */
#define BOARD_INITPINS_MCLK_PORT 1U                            /*!<@brief PORT peripheral base pointer */
#define BOARD_INITPINS_MCLK_PIN 10U                            /*!<@brief PORT pin number */
#define BOARD_INITPINS_MCLK_PIN_MASK (1U << 10U)               /*!<@brief PORT pin mask */
                                                               /* @} */

/*! @name I3C0_PUR (coord B6), J18[3]
  @{ */
/* Routed pin properties */
#define BOARD_INITPINS_I3C0_PUR_PERIPHERAL I3C            /*!<@brief Peripheral name */
#define BOARD_INITPINS_I3C0_PUR_SIGNAL PUR                /*!<@brief Signal name */
#define BOARD_INITPINS_I3C0_PUR_PORT 2U                   /*!<@brief PORT peripheral base pointer */
#define BOARD_INITPINS_I3C0_PUR_PIN 31U                   /*!<@brief PORT pin number */
#define BOARD_INITPINS_I3C0_PUR_PIN_MASK (1U << 31U)      /*!<@brief PORT pin mask */
                                                          /* @} */

/*! @name I3C0_SCL (coord N17), J18[1]/U8[2]/U17[A6]/SCL_CODEC
  @{ */
/* Routed pin properties */
#define BOARD_INITPINS_I3C0_SCL_PERIPHERAL I3C                         /*!<@brief Peripheral name */
#define BOARD_INITPINS_I3C0_SCL_SIGNAL SCL                             /*!<@brief Signal name */
#define BOARD_INITPINS_I3C0_SCL_PORT 2U                                /*!<@brief PORT peripheral base pointer */
#define BOARD_INITPINS_I3C0_SCL_PIN 29U                                /*!<@brief PORT pin number */
#define BOARD_INITPINS_I3C0_SCL_PIN_MASK (1U << 29U)                   /*!<@brief PORT pin mask */
                                                                       /* @} */

/*! @name I3C0_SDA (coord P16), J18[2]/U8[3]/U17[B6]/SDA_CODEC
  @{ */
/* Routed pin properties */
#define BOARD_INITPINS_I3C0_SDA_PERIPHERAL I3C                         /*!<@brief Peripheral name */
#define BOARD_INITPINS_I3C0_SDA_SIGNAL SDA                             /*!<@brief Signal name */
#define BOARD_INITPINS_I3C0_SDA_PORT 2U                                /*!<@brief PORT peripheral base pointer */
#define BOARD_INITPINS_I3C0_SDA_PIN 30U                                /*!<@brief PORT pin number */
#define BOARD_INITPINS_I3C0_SDA_PIN_MASK (1U << 30U)                   /*!<@brief PORT pin mask */
                                                                       /* @} */

/*! @name FC0_RXD_SDA_MOSI_DATA (coord G4), JP21[2]/U28[3]/U9[13]
  @{ */
/* Routed pin properties */
#define BOARD_INITPINS_DEBUG_UART_RXD_PERIPHERAL FLEXCOMM0           /*!<@brief Peripheral name */
#define BOARD_INITPINS_DEBUG_UART_RXD_SIGNAL RXD_SDA_MOSI_DATA       /*!<@brief Signal name */
#define BOARD_INITPINS_DEBUG_UART_RXD_PORT 0U                        /*!<@brief PORT peripheral base pointer */
#define BOARD_INITPINS_DEBUG_UART_RXD_PIN 2U                         /*!<@brief PORT pin number */
#define BOARD_INITPINS_DEBUG_UART_RXD_PIN_MASK (1U << 2U)            /*!<@brief PORT pin mask */
                                                                     /* @} */

/*! @name FC0_TXD_SCL_MISO_WS (coord G2), J16[1]/U27[3]/U9[12]
  @{ */
/* Routed pin properties */
#define BOARD_INITPINS_DEBUG_UART_TXD_PERIPHERAL FLEXCOMM0         /*!<@brief Peripheral name */
#define BOARD_INITPINS_DEBUG_UART_TXD_SIGNAL TXD_SCL_MISO_WS       /*!<@brief Signal name */
#define BOARD_INITPINS_DEBUG_UART_TXD_PORT 0U                      /*!<@brief PORT peripheral base pointer */
#define BOARD_INITPINS_DEBUG_UART_TXD_PIN 1U                       /*!<@brief PORT pin number */
#define BOARD_INITPINS_DEBUG_UART_TXD_PIN_MASK (1U << 1U)          /*!<@brief PORT pin mask */
                                                                   /* @} */

/*! @name FC2_RXD_SDA_MOSI_DATA (coord D6), J36[8]/J47[7]
  @{ */
/* Routed pin properties */
#define BOARD_INITPINS_Fc2_RxData_PERIPHERAL FLEXCOMM2              /*!<@brief Peripheral name */
#define BOARD_INITPINS_Fc2_RxData_SIGNAL RXD_SDA_MOSI_DATA          /*!<@brief Signal name */
#define BOARD_INITPINS_Fc2_RxData_PORT 0U                           /*!<@brief PORT peripheral base pointer */
#define BOARD_INITPINS_Fc2_RxData_PIN 16U                           /*!<@brief PORT pin number */
#define BOARD_INITPINS_Fc2_RxData_PIN_MASK (1U << 16U)              /*!<@brief PORT pin mask */
                                                                    /* @} */

/*! @name FC2_SCK (coord A3), Q4[5]
  @{ */
/* Routed pin properties */
#define BOARD_INITPINS_Fc2_BICK_PERIPHERAL FLEXCOMM2              /*!<@brief Peripheral name */
#define BOARD_INITPINS_Fc2_BICK_SIGNAL SCK                        /*!<@brief Signal name */
#define BOARD_INITPINS_Fc2_BICK_PORT 0U                           /*!<@brief PORT peripheral base pointer */
#define BOARD_INITPINS_Fc2_BICK_PIN 14U                           /*!<@brief PORT pin number */
#define BOARD_INITPINS_Fc2_BICK_PIN_MASK (1U << 14U)              /*!<@brief PORT pin mask */
                                                                  /* @} */

/*! @name FC2_TXD_SCL_MISO_WS (coord A5), J36[6]/J47[6]
  @{ */
/* Routed pin properties */
#define BOARD_INITPINS_Fc2_LRCK_PERIPHERAL FLEXCOMM2              /*!<@brief Peripheral name */
#define BOARD_INITPINS_Fc2_LRCK_SIGNAL TXD_SCL_MISO_WS            /*!<@brief Signal name */
#define BOARD_INITPINS_Fc2_LRCK_PORT 0U                           /*!<@brief PORT peripheral base pointer */
#define BOARD_INITPINS_Fc2_LRCK_PIN 15U                           /*!<@brief PORT pin number */
#define BOARD_INITPINS_Fc2_LRCK_PIN_MASK (1U << 15U)              /*!<@brief PORT pin mask */
                                                                  /* @} */

/*! @name PIO0_3 (coord H2), J1[3]/J36[4]/J45[58]
  @{ */
/* Routed pin properties */
#define BOARD_INITPINS_DbgPin1_PERIPHERAL GPIO                    /*!<@brief Peripheral name */
#define BOARD_INITPINS_DbgPin1_SIGNAL PIO0                        /*!<@brief Signal name */
#define BOARD_INITPINS_DbgPin1_CHANNEL 3                          /*!<@brief Signal channel */

/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_DbgPin1_GPIO GPIO                          /*!<@brief GPIO peripheral base pointer */
#define BOARD_INITPINS_DbgPin1_INIT_GPIO_VALUE 0U                 /*!<@brief GPIO output initial state */
#define BOARD_INITPINS_DbgPin1_GPIO_PIN_MASK (1U << 3U)           /*!<@brief GPIO pin mask */
#define BOARD_INITPINS_DbgPin1_PORT 0U                            /*!<@brief PORT peripheral base pointer */
#define BOARD_INITPINS_DbgPin1_PIN 3U                             /*!<@brief PORT pin number */
#define BOARD_INITPINS_DbgPin1_PIN_MASK (1U << 3U)                /*!<@brief PORT pin mask */
                                                                  /* @} */

/*! @name PIO0_4 (coord J1), J1[5]/J45[60]
  @{ */
/* Routed pin properties */
#define BOARD_INITPINS_DbgPin2_PERIPHERAL GPIO                    /*!<@brief Peripheral name */
#define BOARD_INITPINS_DbgPin2_SIGNAL PIO0                        /*!<@brief Signal name */
#define BOARD_INITPINS_DbgPin2_CHANNEL 4                          /*!<@brief Signal channel */

/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_DbgPin2_GPIO GPIO                          /*!<@brief GPIO peripheral base pointer */
#define BOARD_INITPINS_DbgPin2_INIT_GPIO_VALUE 0U                 /*!<@brief GPIO output initial state */
#define BOARD_INITPINS_DbgPin2_GPIO_PIN_MASK (1U << 4U)           /*!<@brief GPIO pin mask */
#define BOARD_INITPINS_DbgPin2_PORT 0U                            /*!<@brief PORT peripheral base pointer */
#define BOARD_INITPINS_DbgPin2_PIN 4U                             /*!<@brief PORT pin number */
#define BOARD_INITPINS_DbgPin2_PIN_MASK (1U << 4U)                /*!<@brief PORT pin mask */
                                                                  /* @} */

/*! @name PIO0_19 (coord A1), J30[3]
  @{ */
/* Routed pin properties */
#define BOARD_INITPINS_DbgPin3_PERIPHERAL GPIO                    /*!<@brief Peripheral name */
#define BOARD_INITPINS_DbgPin3_SIGNAL PIO0                        /*!<@brief Signal name */
#define BOARD_INITPINS_DbgPin3_CHANNEL 19                         /*!<@brief Signal channel */

/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_DbgPin3_GPIO GPIO                          /*!<@brief GPIO peripheral base pointer */
#define BOARD_INITPINS_DbgPin3_INIT_GPIO_VALUE 0U                 /*!<@brief GPIO output initial state */
#define BOARD_INITPINS_DbgPin3_GPIO_PIN_MASK (1U << 19U)          /*!<@brief GPIO pin mask */
#define BOARD_INITPINS_DbgPin3_PORT 0U                            /*!<@brief PORT peripheral base pointer */
#define BOARD_INITPINS_DbgPin3_PIN 19U                            /*!<@brief PORT pin number */
#define BOARD_INITPINS_DbgPin3_PIN_MASK (1U << 19U)               /*!<@brief PORT pin mask */
                                                                  /* @} */

/*! @name PIO0_20 (coord B2), J30[4]
  @{ */
/* Routed pin properties */
#define BOARD_INITPINS_DbgPin4_PERIPHERAL GPIO                    /*!<@brief Peripheral name */
#define BOARD_INITPINS_DbgPin4_SIGNAL PIO0                        /*!<@brief Signal name */
#define BOARD_INITPINS_DbgPin4_CHANNEL 20                         /*!<@brief Signal channel */

/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_DbgPin4_GPIO GPIO                          /*!<@brief GPIO peripheral base pointer */
#define BOARD_INITPINS_DbgPin4_INIT_GPIO_VALUE 0U                 /*!<@brief GPIO output initial state */
#define BOARD_INITPINS_DbgPin4_GPIO_PIN_MASK (1U << 20U)          /*!<@brief GPIO pin mask */
#define BOARD_INITPINS_DbgPin4_PORT 0U                            /*!<@brief PORT peripheral base pointer */
#define BOARD_INITPINS_DbgPin4_PIN 20U                            /*!<@brief PORT pin number */
#define BOARD_INITPINS_DbgPin4_PIN_MASK (1U << 20U)               /*!<@brief PORT pin mask */
                                                                  /* @} */

/*! @name PIO0_31 (coord A11), Q4[2]
  @{ */
/* Routed pin properties */
#define BOARD_INITPINS_LED_RED_PERIPHERAL GPIO                    /*!<@brief Peripheral name */
#define BOARD_INITPINS_LED_RED_SIGNAL PIO0                        /*!<@brief Signal name */
#define BOARD_INITPINS_LED_RED_CHANNEL 31                         /*!<@brief Signal channel */

/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_LED_RED_GPIO GPIO                          /*!<@brief GPIO peripheral base pointer */
#define BOARD_INITPINS_LED_RED_INIT_GPIO_VALUE 0U                 /*!<@brief GPIO output initial state */
#define BOARD_INITPINS_LED_RED_GPIO_PIN_MASK (1U << 31U)          /*!<@brief GPIO pin mask */
#define BOARD_INITPINS_LED_RED_PORT 0U                            /*!<@brief PORT peripheral base pointer */
#define BOARD_INITPINS_LED_RED_PIN 31U                            /*!<@brief PORT pin number */
#define BOARD_INITPINS_LED_RED_PIN_MASK (1U << 31U)               /*!<@brief PORT pin mask */
                                                                  /* @} */

/*! @name PIO0_26 (coord A2), Q3[2]
  @{ */
/* Routed pin properties */
#define BOARD_INITPINS_LED_BLUE_PERIPHERAL GPIO                    /*!<@brief Peripheral name */
#define BOARD_INITPINS_LED_BLUE_SIGNAL PIO0                        /*!<@brief Signal name */
#define BOARD_INITPINS_LED_BLUE_CHANNEL 26                         /*!<@brief Signal channel */

/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_LED_BLUE_GPIO GPIO                          /*!<@brief GPIO peripheral base pointer */
#define BOARD_INITPINS_LED_BLUE_INIT_GPIO_VALUE 0U                 /*!<@brief GPIO output initial state */
#define BOARD_INITPINS_LED_BLUE_GPIO_PIN_MASK (1U << 26U)          /*!<@brief GPIO pin mask */
#define BOARD_INITPINS_LED_BLUE_PORT 0U                            /*!<@brief PORT peripheral base pointer */
#define BOARD_INITPINS_LED_BLUE_PIN 26U                            /*!<@brief PORT pin number */
#define BOARD_INITPINS_LED_BLUE_PIN_MASK (1U << 26U)               /*!<@brief PORT pin mask */
                                                                   /* @} */

/*!
 * @brief Configures pin routing and optionally pin electrical features.
 *
 */
void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */

#if defined(__cplusplus)
}
#endif

/*!
 * @}
 */
#endif /* _PIN_MUX_H_ */

/***********************************************************************************************************************
 * EOF
 **********************************************************************************************************************/
