/******************************************************************************
                                                  COPYRIGHT (c) FREESCALE 20005  
 File Name          :    $RCSfile: S12SPIV5.h,v $                          
                                                                           
 Current Revision :      $Revision: 1.0 $                                  
                                                                           
 PURPOSE: header file for HCS12 SPI register block                         
                                                                           
 DESCRIPTION:  Defines the SPI register block as a datastructure of type tSPI.          
                                                                           
 UPDATE HISTORY                                                            
 REV  AUTHOR     DATE       DESCRIPTION OF CHANGE                          
 ---  ------    --------    ---------------------                          
 1.0  r32151    01/09/05    Intial coding based on S12SPIV4.               


      *****************************************************************
      *File created by: Freescale East Kilbride MCD Applications Group*
      *****************************************************************

                                                                          
******************************************************************************/
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#ifndef S12SPIV5_H         /*prevent duplicated includes */
#define S12SPIV5_H

#include "S12_COMMON.h"

typedef union uSPICR1
  {
  tU08   byte;
  struct
    {
    tU08 lsbfe :1;      /*lsb first enable */
    tU08 ssoe  :1;      /*slave select output enable */
    tU08 cpha  :1;      /*clock phase */
    tU08 cpol  :1;      /*clock polarity */
    tU08 mstr  :1;      /*master/slave mode select */
    tU08 sptie :1;      /*transmit interrupt enable */
    tU08 spe   :1;      /*spi enable */
    tU08 spie  :1;      /*spi interrupt enable */
    }bit;
  }tSPICR1;

/*bit masks for SPICR1 */
#define LSBFE  0x01  
#define SSOE   0x02
#define CPHA   0x04
#define CPOL   0x08
#define MSTR   0x10
#define SPTIE  0x20
#define SPE    0x40
#define SPIE   0x80

typedef union uSPICR2
  {
  tU08   byte;
  struct
    {
    tU08 spc0    :1; /*serial pin control 0 */
    tU08 spiswai :1; /*stop in wait mode  */
    tU08         :1; /*not used */
    tU08 bidiroe :1; /*bi-directional mode output enable */
    tU08 modfen  :1; /*mode fault enable  */
    tU08         :1; /*not used */
    tU08 xfrw    :1; /*transfer data width */
    tU08         :1; /*not used */
    }bit;
  }tSPICR2;

/*bit masks for SPICR1 */
#define SPC0      0x01  
#define SPISWAI   0x02
#define BIDIROE   0x08
#define MODFEN    0x10
#define XFRW      0x40


typedef union uSPIBR
  {
  tU08   byte;
  struct
    {
    tU08 spr   :3;      /*baud rate selection */
    tU08       :1;      /*not used*/                           
    tU08 sppr  :3;      /*baud rate pre-selection */
    tU08       :1;      /*not used */                             
    }bit;
  }tSPIBR;

/*bit masks for SPIBR */
#define SPR0   0x01  /*bit masks */
#define SPR1   0x02
#define SPR2   0x04
#define SPR    0x07  /*baud rate selection mask */
#define SPPR0  0x10
#define SPPR1  0x20
#define SPPR2  0x40  
#define SPPR   0x70  /*baud rate pre-selection mask */

typedef union uSPISR
  {
  tU08   byte;
  struct
    {
    tU08       :4;      /*not used */
    tU08 modf  :1;      /*mode error interrupt status flag */
    tU08 sptef :1;      /*transmit empty interrupt flag */
    tU08       :1;      /*not used */
    tU08 spif  :1;      /*spi interrupt request */
    }bit;
  }tSPISR;

/*bit masks for SPISR */
#define MODF   0x10  /*bit masks */
#define SPTEF  0x20
#define SPIF   0x80

  typedef union uSPIDR    /*16 bit register with word and byte access*/
  {
  tU16  word;           /*access whole word    */
  struct                /*access byte at a time or individual bits in the bytes */
    {
    tU08  h;
    tU08  l;
    }byte;
  }tSPIDR;
  
  typedef struct          /*spi datastructure  */
  {
  volatile tSPICR1   spicr1;  /*spi control register 1 */
  volatile tSPICR2   spicr2;  /*spi control register 2 */
  volatile tSPIBR    spibr;   /*spi baud rate register */
  volatile tSPISR    spisr;   /*spi status register */
  volatile tSPIDR    spidr;
           tU16      sv2;     /*reserved (maintaining module memory map) */
  }tSPI;

#endif /*S12SPIV5_H */