/*******************************************************************************
*
* Freescale Semiconductor Inc.
* (c) Copyright 2004-2005 Freescale Semiconductor, Inc.
* (c) Copyright 2001-2004 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
********************************************************************************
*
* $File Name: compat.h$
*
* $Date:      Mar-9-2005$
*
* $Version:   2.1.9.0$
*
* Description: Backward compatibility header file for 56F800 (HawkV1) release.
*              Any macro obsolete in previous release is redefined here
*              according to new naming convention.
*
*              Include this file at the end of your appconfig.h file		  
*
*****************************************************************************/

/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!! DO NOT EDIT!! - This file is generated from compat.h.templ file !!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/

#ifndef __COMPAT_H
#define __COMPAT_H

/* adc */

#if defined(ADC_A_CONTROL_REG1) && !defined(ADC_A_ADCR1_INIT)
#define ADC_A_ADCR1_INIT	ADC_A_CONTROL_REG1
#endif
#if defined(ADC_A_CONTROL_REG2) && !defined(ADC_A_ADCR2_INIT)
#define ADC_A_ADCR2_INIT	ADC_A_CONTROL_REG2
#endif
#if defined(ADC_A_ZERO_CROSS_CONTROL_REG) && !defined(ADC_A_ADZCC_INIT)
#define ADC_A_ADZCC_INIT	ADC_A_ZERO_CROSS_CONTROL_REG
#endif
#if defined(ADC_A_CHANNEL_LIST_REG1) && !defined(ADC_A_ADLST1_INIT)
#define ADC_A_ADLST1_INIT	ADC_A_CHANNEL_LIST_REG1
#endif
#if defined(ADC_A_CHANNEL_LIST_REG2) && !defined(ADC_A_ADLST2_INIT)
#define ADC_A_ADLST2_INIT	ADC_A_CHANNEL_LIST_REG2
#endif
#if defined(ADC_A_SAMPLE_DISABLE_REG) && !defined(ADC_A_ADSDIS_INIT)
#define ADC_A_ADSDIS_INIT	ADC_A_SAMPLE_DISABLE_REG
#endif
#if defined(ADC_A_STATUS_REG) && !defined(ADC_A_ADSTAT_INIT)
#define ADC_A_ADSTAT_INIT	ADC_A_STATUS_REG
#endif
#if defined(ADC_A_LIMIT_STATUS_REG) && !defined(ADC_A_ADLSTAT_INIT)
#define ADC_A_ADLSTAT_INIT	ADC_A_LIMIT_STATUS_REG
#endif
#if defined(ADC_A_ZERO_CROSS_STATUS_REG) && !defined(ADC_A_ADZCSTAT_INIT)
#define ADC_A_ADZCSTAT_INIT	ADC_A_ZERO_CROSS_STATUS_REG
#endif

#if defined(ADC_A_LOW_LIMIT_REG0) && !defined(ADC_A_ADLLMT0_INIT)
#define ADC_A_ADLLMT0_INIT	ADC_A_LOW_LIMIT_REG0
#endif
#if defined(ADC_A_LOW_LIMIT_REG1) && !defined(ADC_A_ADLLMT1_INIT)
#define ADC_A_ADLLMT1_INIT	ADC_A_LOW_LIMIT_REG1
#endif
#if defined(ADC_A_LOW_LIMIT_REG2) && !defined(ADC_A_ADLLMT2_INIT)
#define ADC_A_ADLLMT2_INIT	ADC_A_LOW_LIMIT_REG2
#endif
#if defined(ADC_A_LOW_LIMIT_REG3) && !defined(ADC_A_ADLLMT3_INIT)
#define ADC_A_ADLLMT3_INIT	ADC_A_LOW_LIMIT_REG3
#endif
#if defined(ADC_A_LOW_LIMIT_REG4) && !defined(ADC_A_ADLLMT4_INIT)
#define ADC_A_ADLLMT4_INIT	ADC_A_LOW_LIMIT_REG4
#endif
#if defined(ADC_A_LOW_LIMIT_REG5) && !defined(ADC_A_ADLLMT5_INIT)
#define ADC_A_ADLLMT5_INIT	ADC_A_LOW_LIMIT_REG5
#endif
#if defined(ADC_A_LOW_LIMIT_REG6) && !defined(ADC_A_ADLLMT6_INIT)
#define ADC_A_ADLLMT6_INIT	ADC_A_LOW_LIMIT_REG6
#endif
#if defined(ADC_A_LOW_LIMIT_REG7) && !defined(ADC_A_ADLLMT7_INIT)
#define ADC_A_ADLLMT7_INIT	ADC_A_LOW_LIMIT_REG7
#endif

#if defined(ADC_A_HIGH_LIMIT_REG0) && !defined(ADC_A_ADHLMT0_INIT)
#define ADC_A_ADHLMT0_INIT	ADC_A_HIGH_LIMIT_REG0
#endif
#if defined(ADC_A_HIGH_LIMIT_REG1) && !defined(ADC_A_ADHLMT1_INIT)
#define ADC_A_ADHLMT1_INIT	ADC_A_HIGH_LIMIT_REG1
#endif
#if defined(ADC_A_HIGH_LIMIT_REG2) && !defined(ADC_A_ADHLMT2_INIT)
#define ADC_A_ADHLMT2_INIT	ADC_A_HIGH_LIMIT_REG2
#endif
#if defined(ADC_A_HIGH_LIMIT_REG3) && !defined(ADC_A_ADHLMT3_INIT)
#define ADC_A_ADHLMT3_INIT	ADC_A_HIGH_LIMIT_REG3
#endif
#if defined(ADC_A_HIGH_LIMIT_REG4) && !defined(ADC_A_ADHLMT4_INIT)
#define ADC_A_ADHLMT4_INIT	ADC_A_HIGH_LIMIT_REG4
#endif
#if defined(ADC_A_HIGH_LIMIT_REG5) && !defined(ADC_A_ADHLMT5_INIT)
#define ADC_A_ADHLMT5_INIT	ADC_A_HIGH_LIMIT_REG5
#endif
#if defined(ADC_A_HIGH_LIMIT_REG6) && !defined(ADC_A_ADHLMT6_INIT)
#define ADC_A_ADHLMT6_INIT	ADC_A_HIGH_LIMIT_REG6
#endif
#if defined(ADC_A_HIGH_LIMIT_REG7) && !defined(ADC_A_ADHLMT7_INIT)
#define ADC_A_ADHLMT7_INIT	ADC_A_HIGH_LIMIT_REG7
#endif

#if defined(ADC_A_OFFSET_REG0) && !defined(ADC_A_ADOFS0_INIT)
#define ADC_A_ADOFS0_INIT	ADC_A_OFFSET_REG0
#endif
#if defined(ADC_A_OFFSET_REG1) && !defined(ADC_A_ADOFS1_INIT)
#define ADC_A_ADOFS1_INIT	ADC_A_OFFSET_REG1
#endif
#if defined(ADC_A_OFFSET_REG2) && !defined(ADC_A_ADOFS2_INIT)
#define ADC_A_ADOFS2_INIT	ADC_A_OFFSET_REG2
#endif
#if defined(ADC_A_OFFSET_REG3) && !defined(ADC_A_ADOFS3_INIT)
#define ADC_A_ADOFS3_INIT	ADC_A_OFFSET_REG3
#endif
#if defined(ADC_A_OFFSET_REG4) && !defined(ADC_A_ADOFS4_INIT)
#define ADC_A_ADOFS4_INIT	ADC_A_OFFSET_REG4
#endif
#if defined(ADC_A_OFFSET_REG5) && !defined(ADC_A_ADOFS5_INIT)
#define ADC_A_ADOFS5_INIT	ADC_A_OFFSET_REG5
#endif
#if defined(ADC_A_OFFSET_REG6) && !defined(ADC_A_ADOFS6_INIT)
#define ADC_A_ADOFS6_INIT	ADC_A_OFFSET_REG6
#endif
#if defined(ADC_A_OFFSET_REG7) && !defined(ADC_A_ADOFS7_INIT)
#define ADC_A_ADOFS7_INIT	ADC_A_OFFSET_REG7
#endif

#if defined(ADC_B_CONTROL_REG1) && !defined(ADC_B_ADCR1_INIT)
#define ADC_B_ADCR1_INIT	ADC_B_CONTROL_REG1
#endif
#if defined(ADC_B_CONTROL_REG2) && !defined(ADC_B_ADCR2_INIT)
#define ADC_B_ADCR2_INIT	ADC_B_CONTROL_REG2
#endif
#if defined(ADC_B_ZERO_CROSS_CONTROL_REG) && !defined(ADC_B_ADZCC_INIT)
#define ADC_B_ADZCC_INIT	ADC_B_ZERO_CROSS_CONTROL_REG
#endif
#if defined(ADC_B_CHANNEL_LIST_REG1) && !defined(ADC_B_ADLST1_INIT)
#define ADC_B_ADLST1_INIT	ADC_B_CHANNEL_LIST_REG1
#endif
#if defined(ADC_B_CHANNEL_LIST_REG2) && !defined(ADC_B_ADLST2_INIT)
#define ADC_B_ADLST2_INIT	ADC_B_CHANNEL_LIST_REG2
#endif
#if defined(ADC_B_SAMPLE_DISABLE_REG) && !defined(ADC_B_ADSDIS_INIT)
#define ADC_B_ADSDIS_INIT	ADC_B_SAMPLE_DISABLE_REG
#endif
#if defined(ADC_B_STATUS_REG) && !defined(ADC_B_ADSTAT_INIT)
#define ADC_B_ADSTAT_INIT	ADC_B_STATUS_REG
#endif
#if defined(ADC_B_LIMIT_STATUS_REG) && !defined(ADC_B_ADLSTAT_INIT)
#define ADC_B_ADLSTAT_INIT	ADC_B_LIMIT_STATUS_REG
#endif
#if defined(ADC_B_ZERO_CROSS_STATUS_REG) && !defined(ADC_B_ADZCSTAT_INIT)
#define ADC_B_ADZCSTAT_INIT	ADC_B_ZERO_CROSS_STATUS_REG
#endif

#if defined(ADC_B_LOW_LIMIT_REG0) && !defined(ADC_B_ADLLMT0_INIT)
#define ADC_B_ADLLMT0_INIT	ADC_B_LOW_LIMIT_REG0
#endif
#if defined(ADC_B_LOW_LIMIT_REG1) && !defined(ADC_B_ADLLMT1_INIT)
#define ADC_B_ADLLMT1_INIT	ADC_B_LOW_LIMIT_REG1
#endif
#if defined(ADC_B_LOW_LIMIT_REG2) && !defined(ADC_B_ADLLMT2_INIT)
#define ADC_B_ADLLMT2_INIT	ADC_B_LOW_LIMIT_REG2
#endif
#if defined(ADC_B_LOW_LIMIT_REG3) && !defined(ADC_B_ADLLMT3_INIT)
#define ADC_B_ADLLMT3_INIT	ADC_B_LOW_LIMIT_REG3
#endif
#if defined(ADC_B_LOW_LIMIT_REG4) && !defined(ADC_B_ADLLMT4_INIT)
#define ADC_B_ADLLMT4_INIT	ADC_B_LOW_LIMIT_REG4
#endif
#if defined(ADC_B_LOW_LIMIT_REG5) && !defined(ADC_B_ADLLMT5_INIT)
#define ADC_B_ADLLMT5_INIT	ADC_B_LOW_LIMIT_REG5
#endif
#if defined(ADC_B_LOW_LIMIT_REG6) && !defined(ADC_B_ADLLMT6_INIT)
#define ADC_B_ADLLMT6_INIT	ADC_B_LOW_LIMIT_REG6
#endif
#if defined(ADC_B_LOW_LIMIT_REG7) && !defined(ADC_B_ADLLMT7_INIT)
#define ADC_B_ADLLMT7_INIT	ADC_B_LOW_LIMIT_REG7
#endif

#if defined(ADC_B_HIGH_LIMIT_REG0) && !defined(ADC_B_ADHLMT0_INIT)
#define ADC_B_ADHLMT0_INIT	ADC_B_HIGH_LIMIT_REG0
#endif
#if defined(ADC_B_HIGH_LIMIT_REG1) && !defined(ADC_B_ADHLMT1_INIT)
#define ADC_B_ADHLMT1_INIT	ADC_B_HIGH_LIMIT_REG1
#endif
#if defined(ADC_B_HIGH_LIMIT_REG2) && !defined(ADC_B_ADHLMT2_INIT)
#define ADC_B_ADHLMT2_INIT	ADC_B_HIGH_LIMIT_REG2
#endif
#if defined(ADC_B_HIGH_LIMIT_REG3) && !defined(ADC_B_ADHLMT3_INIT)
#define ADC_B_ADHLMT3_INIT	ADC_B_HIGH_LIMIT_REG3
#endif
#if defined(ADC_B_HIGH_LIMIT_REG4) && !defined(ADC_B_ADHLMT4_INIT)
#define ADC_B_ADHLMT4_INIT	ADC_B_HIGH_LIMIT_REG4
#endif
#if defined(ADC_B_HIGH_LIMIT_REG5) && !defined(ADC_B_ADHLMT5_INIT)
#define ADC_B_ADHLMT5_INIT	ADC_B_HIGH_LIMIT_REG5
#endif
#if defined(ADC_B_HIGH_LIMIT_REG6) && !defined(ADC_B_ADHLMT6_INIT)
#define ADC_B_ADHLMT6_INIT	ADC_B_HIGH_LIMIT_REG6
#endif
#if defined(ADC_B_HIGH_LIMIT_REG7) && !defined(ADC_B_ADHLMT7_INIT)
#define ADC_B_ADHLMT7_INIT	ADC_B_HIGH_LIMIT_REG7
#endif

#if defined(ADC_B_OFFSET_REG0) && !defined(ADC_B_ADOFS0_INIT)
#define ADC_B_ADOFS0_INIT	ADC_B_OFFSET_REG0
#endif
#if defined(ADC_B_OFFSET_REG1) && !defined(ADC_B_ADOFS1_INIT)
#define ADC_B_ADOFS1_INIT	ADC_B_OFFSET_REG1
#endif
#if defined(ADC_B_OFFSET_REG2) && !defined(ADC_B_ADOFS2_INIT)
#define ADC_B_ADOFS2_INIT	ADC_B_OFFSET_REG2
#endif
#if defined(ADC_B_OFFSET_REG3) && !defined(ADC_B_ADOFS3_INIT)
#define ADC_B_ADOFS3_INIT	ADC_B_OFFSET_REG3
#endif
#if defined(ADC_B_OFFSET_REG4) && !defined(ADC_B_ADOFS4_INIT)
#define ADC_B_ADOFS4_INIT	ADC_B_OFFSET_REG4
#endif
#if defined(ADC_B_OFFSET_REG5) && !defined(ADC_B_ADOFS5_INIT)
#define ADC_B_ADOFS5_INIT	ADC_B_OFFSET_REG5
#endif
#if defined(ADC_B_OFFSET_REG6) && !defined(ADC_B_ADOFS6_INIT)
#define ADC_B_ADOFS6_INIT	ADC_B_OFFSET_REG6
#endif
#if defined(ADC_B_OFFSET_REG7) && !defined(ADC_B_ADOFS7_INIT)
#define ADC_B_ADOFS7_INIT	ADC_B_OFFSET_REG7
#endif

/* cop */

#if defined(COP_CONTROL_REG) && !defined(COP_COPCTL_INIT)
#define COP_COPCTL_INIT	COP_CONTROL_REG
#endif
#if defined(COP_TIMEOUT_REG) && !defined(COP_COPTO_INIT)
#define COP_COPTO_INIT	COP_TIMEOUT_REG
#endif

/* decoder */

#if defined(DEC_0_CONTROL_REG) && !defined(DEC_0_DECCR_INIT)
#define DEC_0_DECCR_INIT	DEC_0_CONTROL_REG
#endif
#if defined(DEC_0_WATCHDOG_TIMEOUT_REG) && !defined(DEC_0_WTR_INIT)
#define DEC_0_WTR_INIT	DEC_0_WATCHDOG_TIMEOUT_REG
#endif
#if defined(DEC_0_FILTER_INTERVAL_REG) && !defined(DEC_0_FIR_INIT)
#define DEC_0_FIR_INIT	DEC_0_FILTER_INTERVAL_REG
#endif
#if defined(DEC_0_UPPER_INIT_REG) && !defined(DEC_0_UIR_INIT)
#define DEC_0_UIR_INIT	DEC_0_UPPER_INIT_REG
#endif
#if defined(DEC_0_LOWER_INIT_REG) && !defined(DEC_0_LIR_INIT)
#define DEC_0_LIR_INIT	DEC_0_LOWER_INIT_REG
#endif

#if defined(DEC_1_CONTROL_REG) && !defined(DEC_1_DECCR_INIT)
#define DEC_1_DECCR_INIT	DEC_1_CONTROL_REG
#endif
#if defined(DEC_1_WATCHDOG_TIMEOUT_REG) && !defined(DEC_1_WTR_INIT)
#define DEC_1_WTR_INIT	DEC_1_WATCHDOG_TIMEOUT_REG
#endif
#if defined(DEC_1_FILTER_INTERVAL_REG) && !defined(DEC_1_FIR_INIT)
#define DEC_1_FIR_INIT	DEC_1_FILTER_INTERVAL_REG
#endif
#if defined(DEC_1_UPPER_INIT_REG) && !defined(DEC_1_UIR_INIT)
#define DEC_1_UIR_INIT	DEC_1_UPPER_INIT_REG
#endif
#if defined(DEC_1_LOWER_INIT_REG) && !defined(DEC_1_LIR_INIT)
#define DEC_1_LIR_INIT	DEC_1_LOWER_INIT_REG
#endif

/* gpio */

#if defined(GPIO_A_PULLUP_ENABLE_REG) && !defined(GPIO_A_PUR_INIT)
#define GPIO_A_PUR_INIT	GPIO_A_PULLUP_ENABLE_REG
#endif
#if defined(GPIO_A_DATA_DIRECTION_REG) && !defined(GPIO_A_DDR_INIT)
#define GPIO_A_DDR_INIT	GPIO_A_DATA_DIRECTION_REG
#endif
#if defined(GPIO_A_PERIPHERAL_ENABLE_REG) && !defined(GPIO_A_PER_INIT)
#define GPIO_A_PER_INIT	GPIO_A_PERIPHERAL_ENABLE_REG
#endif
#if defined(GPIO_A_INTERRUPT_ENABLE_REG) && !defined(GPIO_A_IENR_INIT)
#define GPIO_A_IENR_INIT	GPIO_A_INTERRUPT_ENABLE_REG
#endif
#if defined(GPIO_A_INTERRUPT_POLARITY_REG) && !defined(GPIO_A_IPOLR_INIT)
#define GPIO_A_IPOLR_INIT	GPIO_A_INTERRUPT_POLARITY_REG
#endif
#if defined(GPIO_A_PUSHPULL_MODE_REG) && !defined(GPIO_A_PPMODE_INIT)
#define GPIO_A_PPMODE_INIT	GPIO_A_PUSHPULL_MODE_REG
#endif

#if defined(GPIO_B_PULLUP_ENABLE_REG) && !defined(GPIO_B_PUR_INIT)
#define GPIO_B_PUR_INIT	GPIO_B_PULLUP_ENABLE_REG
#endif
#if defined(GPIO_B_DATA_DIRECTION_REG) && !defined(GPIO_B_DDR_INIT)
#define GPIO_B_DDR_INIT	GPIO_B_DATA_DIRECTION_REG
#endif
#if defined(GPIO_B_PERIPHERAL_ENABLE_REG) && !defined(GPIO_B_PER_INIT)
#define GPIO_B_PER_INIT	GPIO_B_PERIPHERAL_ENABLE_REG
#endif
#if defined(GPIO_B_INTERRUPT_ENABLE_REG) && !defined(GPIO_B_IENR_INIT)
#define GPIO_B_IENR_INIT	GPIO_B_INTERRUPT_ENABLE_REG
#endif
#if defined(GPIO_B_INTERRUPT_POLARITY_REG) && !defined(GPIO_B_IPOLR_INIT)
#define GPIO_B_IPOLR_INIT	GPIO_B_INTERRUPT_POLARITY_REG
#endif
#if defined(GPIO_B_PUSHPULL_MODE_REG) && !defined(GPIO_B_PPMODE_INIT)
#define GPIO_B_PPMODE_INIT	GPIO_B_PUSHPULL_MODE_REG
#endif

#if defined(GPIO_C_PULLUP_ENABLE_REG) && !defined(GPIO_C_PUR_INIT)
#define GPIO_C_PUR_INIT	GPIO_C_PULLUP_ENABLE_REG
#endif
#if defined(GPIO_C_DATA_DIRECTION_REG) && !defined(GPIO_C_DDR_INIT)
#define GPIO_C_DDR_INIT	GPIO_C_DATA_DIRECTION_REG
#endif
#if defined(GPIO_C_PERIPHERAL_ENABLE_REG) && !defined(GPIO_C_PER_INIT)
#define GPIO_C_PER_INIT	GPIO_C_PERIPHERAL_ENABLE_REG
#endif
#if defined(GPIO_C_INTERRUPT_ENABLE_REG) && !defined(GPIO_C_IENR_INIT)
#define GPIO_C_IENR_INIT	GPIO_C_INTERRUPT_ENABLE_REG
#endif
#if defined(GPIO_C_INTERRUPT_POLARITY_REG) && !defined(GPIO_C_IPOLR_INIT)
#define GPIO_C_IPOLR_INIT	GPIO_C_INTERRUPT_POLARITY_REG
#endif
#if defined(GPIO_C_PUSHPULL_MODE_REG) && !defined(GPIO_C_PPMODE_INIT)
#define GPIO_C_PPMODE_INIT	GPIO_C_PUSHPULL_MODE_REG
#endif

#if defined(GPIO_D_PULLUP_ENABLE_REG) && !defined(GPIO_D_PUR_INIT)
#define GPIO_D_PUR_INIT	GPIO_D_PULLUP_ENABLE_REG
#endif
#if defined(GPIO_D_DATA_DIRECTION_REG) && !defined(GPIO_D_DDR_INIT)
#define GPIO_D_DDR_INIT	GPIO_D_DATA_DIRECTION_REG
#endif
#if defined(GPIO_D_PERIPHERAL_ENABLE_REG) && !defined(GPIO_D_PER_INIT)
#define GPIO_D_PER_INIT	GPIO_D_PERIPHERAL_ENABLE_REG
#endif
#if defined(GPIO_D_INTERRUPT_ENABLE_REG) && !defined(GPIO_D_IENR_INIT)
#define GPIO_D_IENR_INIT	GPIO_D_INTERRUPT_ENABLE_REG
#endif
#if defined(GPIO_D_INTERRUPT_POLARITY_REG) && !defined(GPIO_D_IPOLR_INIT)
#define GPIO_D_IPOLR_INIT	GPIO_D_INTERRUPT_POLARITY_REG
#endif
#if defined(GPIO_D_PUSHPULL_MODE_REG) && !defined(GPIO_D_PPMODE_INIT)
#define GPIO_D_PPMODE_INIT	GPIO_D_PUSHPULL_MODE_REG
#endif

#if defined(GPIO_E_PULLUP_ENABLE_REG) && !defined(GPIO_E_PUR_INIT)
#define GPIO_E_PUR_INIT	GPIO_E_PULLUP_ENABLE_REG
#endif
#if defined(GPIO_E_DATA_DIRECTION_REG) && !defined(GPIO_E_DDR_INIT)
#define GPIO_E_DDR_INIT	GPIO_E_DATA_DIRECTION_REG
#endif
#if defined(GPIO_E_PERIPHERAL_ENABLE_REG) && !defined(GPIO_E_PER_INIT)
#define GPIO_E_PER_INIT	GPIO_E_PERIPHERAL_ENABLE_REG
#endif
#if defined(GPIO_E_INTERRUPT_ENABLE_REG) && !defined(GPIO_E_IENR_INIT)
#define GPIO_E_IENR_INIT	GPIO_E_INTERRUPT_ENABLE_REG
#endif
#if defined(GPIO_E_INTERRUPT_POLARITY_REG) && !defined(GPIO_E_IPOLR_INIT)
#define GPIO_E_IPOLR_INIT	GPIO_E_INTERRUPT_POLARITY_REG
#endif
#if defined(GPIO_E_PUSHPULL_MODE_REG) && !defined(GPIO_E_PPMODE_INIT)
#define GPIO_E_PPMODE_INIT	GPIO_E_PUSHPULL_MODE_REG
#endif

/* occs */

#if defined(OCCS_CONTROL_REG) && !defined(OCCS_PLLCR_INIT)
#define OCCS_PLLCR_INIT	OCCS_CONTROL_REG
#endif
#if defined(OCCS_DIVIDE_BY_REG) && !defined(OCCS_PLLDB_INIT)
#define OCCS_PLLDB_INIT	OCCS_DIVIDE_BY_REG
#endif

/* qtimer */

#if defined(QT_A0_CONTROL_REG) && !defined(QT_A0_CTRL_INIT)
#define QT_A0_CTRL_INIT	QT_A0_CONTROL_REG
#endif
#if defined(QT_A0_STATUS_CONTROL_REG) && !defined(QT_A0_SCR_INIT)
#define QT_A0_SCR_INIT	QT_A0_STATUS_CONTROL_REG
#endif
#if defined(QT_A0_COMPARE_REG1) && !defined(QT_A0_CMP1_INIT)
#define QT_A0_CMP1_INIT	QT_A0_COMPARE_REG1
#endif
#if defined(QT_A0_COMPARE_REG2) && !defined(QT_A0_CMP2_INIT)
#define QT_A0_CMP2_INIT	QT_A0_COMPARE_REG2
#endif
#if defined(QT_A0_LOAD_REG) && !defined(QT_A0_LOAD_INIT)
#define QT_A0_LOAD_INIT	QT_A0_LOAD_REG
#endif
#if defined(QT_A0_COUNTER_REG) && !defined(QT_A0_CNTR_INIT)
#define QT_A0_CNTR_INIT	QT_A0_COUNTER_REG
#endif

#if defined(QT_A1_CONTROL_REG) && !defined(QT_A1_CTRL_INIT)
#define QT_A1_CTRL_INIT	QT_A1_CONTROL_REG
#endif
#if defined(QT_A1_STATUS_CONTROL_REG) && !defined(QT_A1_SCR_INIT)
#define QT_A1_SCR_INIT	QT_A1_STATUS_CONTROL_REG
#endif
#if defined(QT_A1_COMPARE_REG1) && !defined(QT_A1_CMP1_INIT)
#define QT_A1_CMP1_INIT	QT_A1_COMPARE_REG1
#endif
#if defined(QT_A1_COMPARE_REG2) && !defined(QT_A1_CMP2_INIT)
#define QT_A1_CMP2_INIT	QT_A1_COMPARE_REG2
#endif
#if defined(QT_A1_LOAD_REG) && !defined(QT_A1_LOAD_INIT)
#define QT_A1_LOAD_INIT	QT_A1_LOAD_REG
#endif
#if defined(QT_A1_COUNTER_REG) && !defined(QT_A1_CNTR_INIT)
#define QT_A1_CNTR_INIT	QT_A1_COUNTER_REG
#endif

#if defined(QT_A2_CONTROL_REG) && !defined(QT_A2_CTRL_INIT)
#define QT_A2_CTRL_INIT	QT_A2_CONTROL_REG
#endif
#if defined(QT_A2_STATUS_CONTROL_REG) && !defined(QT_A2_SCR_INIT)
#define QT_A2_SCR_INIT	QT_A2_STATUS_CONTROL_REG
#endif
#if defined(QT_A2_COMPARE_REG1) && !defined(QT_A2_CMP1_INIT)
#define QT_A2_CMP1_INIT	QT_A2_COMPARE_REG1
#endif
#if defined(QT_A2_COMPARE_REG2) && !defined(QT_A2_CMP2_INIT)
#define QT_A2_CMP2_INIT	QT_A2_COMPARE_REG2
#endif
#if defined(QT_A2_LOAD_REG) && !defined(QT_A2_LOAD_INIT)
#define QT_A2_LOAD_INIT	QT_A2_LOAD_REG
#endif
#if defined(QT_A2_COUNTER_REG) && !defined(QT_A2_CNTR_INIT)
#define QT_A2_CNTR_INIT	QT_A2_COUNTER_REG
#endif

#if defined(QT_A3_CONTROL_REG) && !defined(QT_A3_CTRL_INIT)
#define QT_A3_CTRL_INIT	QT_A3_CONTROL_REG
#endif
#if defined(QT_A3_STATUS_CONTROL_REG) && !defined(QT_A3_SCR_INIT)
#define QT_A3_SCR_INIT	QT_A3_STATUS_CONTROL_REG
#endif
#if defined(QT_A3_COMPARE_REG1) && !defined(QT_A3_CMP1_INIT)
#define QT_A3_CMP1_INIT	QT_A3_COMPARE_REG1
#endif
#if defined(QT_A3_COMPARE_REG2) && !defined(QT_A3_CMP2_INIT)
#define QT_A3_CMP2_INIT	QT_A3_COMPARE_REG2
#endif
#if defined(QT_A3_LOAD_REG) && !defined(QT_A3_LOAD_INIT)
#define QT_A3_LOAD_INIT	QT_A3_LOAD_REG
#endif
#if defined(QT_A3_COUNTER_REG) && !defined(QT_A3_CNTR_INIT)
#define QT_A3_CNTR_INIT	QT_A3_COUNTER_REG
#endif

#if defined(QT_B0_CONTROL_REG) && !defined(QT_B0_CTRL_INIT)
#define QT_B0_CTRL_INIT	QT_B0_CONTROL_REG
#endif
#if defined(QT_B0_STATUS_CONTROL_REG) && !defined(QT_B0_SCR_INIT)
#define QT_B0_SCR_INIT	QT_B0_STATUS_CONTROL_REG
#endif
#if defined(QT_B0_COMPARE_REG1) && !defined(QT_B0_CMP1_INIT)
#define QT_B0_CMP1_INIT	QT_B0_COMPARE_REG1
#endif
#if defined(QT_B0_COMPARE_REG2) && !defined(QT_B0_CMP2_INIT)
#define QT_B0_CMP2_INIT	QT_B0_COMPARE_REG2
#endif
#if defined(QT_B0_LOAD_REG) && !defined(QT_B0_LOAD_INIT)
#define QT_B0_LOAD_INIT	QT_B0_LOAD_REG
#endif
#if defined(QT_B0_COUNTER_REG) && !defined(QT_B0_CNTR_INIT)
#define QT_B0_CNTR_INIT	QT_B0_COUNTER_REG
#endif

#if defined(QT_B1_CONTROL_REG) && !defined(QT_B1_CTRL_INIT)
#define QT_B1_CTRL_INIT	QT_B1_CONTROL_REG
#endif
#if defined(QT_B1_STATUS_CONTROL_REG) && !defined(QT_B1_SCR_INIT)
#define QT_B1_SCR_INIT	QT_B1_STATUS_CONTROL_REG
#endif
#if defined(QT_B1_COMPARE_REG1) && !defined(QT_B1_CMP1_INIT)
#define QT_B1_CMP1_INIT	QT_B1_COMPARE_REG1
#endif
#if defined(QT_B1_COMPARE_REG2) && !defined(QT_B1_CMP2_INIT)
#define QT_B1_CMP2_INIT	QT_B1_COMPARE_REG2
#endif
#if defined(QT_B1_LOAD_REG) && !defined(QT_B1_LOAD_INIT)
#define QT_B1_LOAD_INIT	QT_B1_LOAD_REG
#endif
#if defined(QT_B1_COUNTER_REG) && !defined(QT_B1_CNTR_INIT)
#define QT_B1_CNTR_INIT	QT_B1_COUNTER_REG
#endif

#if defined(QT_B2_CONTROL_REG) && !defined(QT_B2_CTRL_INIT)
#define QT_B2_CTRL_INIT	QT_B2_CONTROL_REG
#endif
#if defined(QT_B2_STATUS_CONTROL_REG) && !defined(QT_B2_SCR_INIT)
#define QT_B2_SCR_INIT	QT_B2_STATUS_CONTROL_REG
#endif
#if defined(QT_B2_COMPARE_REG1) && !defined(QT_B2_CMP1_INIT)
#define QT_B2_CMP1_INIT	QT_B2_COMPARE_REG1
#endif
#if defined(QT_B2_COMPARE_REG2) && !defined(QT_B2_CMP2_INIT)
#define QT_B2_CMP2_INIT	QT_B2_COMPARE_REG2
#endif
#if defined(QT_B2_LOAD_REG) && !defined(QT_B2_LOAD_INIT)
#define QT_B2_LOAD_INIT	QT_B2_LOAD_REG
#endif
#if defined(QT_B2_COUNTER_REG) && !defined(QT_B2_CNTR_INIT)
#define QT_B2_CNTR_INIT	QT_B2_COUNTER_REG
#endif

#if defined(QT_B3_CONTROL_REG) && !defined(QT_B3_CTRL_INIT)
#define QT_B3_CTRL_INIT	QT_B3_CONTROL_REG
#endif
#if defined(QT_B3_STATUS_CONTROL_REG) && !defined(QT_B3_SCR_INIT)
#define QT_B3_SCR_INIT	QT_B3_STATUS_CONTROL_REG
#endif
#if defined(QT_B3_COMPARE_REG1) && !defined(QT_B3_CMP1_INIT)
#define QT_B3_CMP1_INIT	QT_B3_COMPARE_REG1
#endif
#if defined(QT_B3_COMPARE_REG2) && !defined(QT_B3_CMP2_INIT)
#define QT_B3_CMP2_INIT	QT_B3_COMPARE_REG2
#endif
#if defined(QT_B3_LOAD_REG) && !defined(QT_B3_LOAD_INIT)
#define QT_B3_LOAD_INIT	QT_B3_LOAD_REG
#endif
#if defined(QT_B3_COUNTER_REG) && !defined(QT_B3_CNTR_INIT)
#define QT_B3_CNTR_INIT	QT_B3_COUNTER_REG
#endif

#if defined(QT_C0_CONTROL_REG) && !defined(QT_C0_CTRL_INIT)
#define QT_C0_CTRL_INIT	QT_C0_CONTROL_REG
#endif
#if defined(QT_C0_STATUS_CONTROL_REG) && !defined(QT_C0_SCR_INIT)
#define QT_C0_SCR_INIT	QT_C0_STATUS_CONTROL_REG
#endif
#if defined(QT_C0_COMPARE_REG1) && !defined(QT_C0_CMP1_INIT)
#define QT_C0_CMP1_INIT	QT_C0_COMPARE_REG1
#endif
#if defined(QT_C0_COMPARE_REG2) && !defined(QT_C0_CMP2_INIT)
#define QT_C0_CMP2_INIT	QT_C0_COMPARE_REG2
#endif
#if defined(QT_C0_LOAD_REG) && !defined(QT_C0_LOAD_INIT)
#define QT_C0_LOAD_INIT	QT_C0_LOAD_REG
#endif
#if defined(QT_C0_COUNTER_REG) && !defined(QT_C0_CNTR_INIT)
#define QT_C0_CNTR_INIT	QT_C0_COUNTER_REG
#endif

#if defined(QT_C1_CONTROL_REG) && !defined(QT_C1_CTRL_INIT)
#define QT_C1_CTRL_INIT	QT_C1_CONTROL_REG
#endif
#if defined(QT_C1_STATUS_CONTROL_REG) && !defined(QT_C1_SCR_INIT)
#define QT_C1_SCR_INIT	QT_C1_STATUS_CONTROL_REG
#endif
#if defined(QT_C1_COMPARE_REG1) && !defined(QT_C1_CMP1_INIT)
#define QT_C1_CMP1_INIT	QT_C1_COMPARE_REG1
#endif
#if defined(QT_C1_COMPARE_REG2) && !defined(QT_C1_CMP2_INIT)
#define QT_C1_CMP2_INIT	QT_C1_COMPARE_REG2
#endif
#if defined(QT_C1_LOAD_REG) && !defined(QT_C1_LOAD_INIT)
#define QT_C1_LOAD_INIT	QT_C1_LOAD_REG
#endif
#if defined(QT_C1_COUNTER_REG) && !defined(QT_C1_CNTR_INIT)
#define QT_C1_CNTR_INIT	QT_C1_COUNTER_REG
#endif

#if defined(QT_C2_CONTROL_REG) && !defined(QT_C2_CTRL_INIT)
#define QT_C2_CTRL_INIT	QT_C2_CONTROL_REG
#endif
#if defined(QT_C2_STATUS_CONTROL_REG) && !defined(QT_C2_SCR_INIT)
#define QT_C2_SCR_INIT	QT_C2_STATUS_CONTROL_REG
#endif
#if defined(QT_C2_COMPARE_REG1) && !defined(QT_C2_CMP1_INIT)
#define QT_C2_CMP1_INIT	QT_C2_COMPARE_REG1
#endif
#if defined(QT_C2_COMPARE_REG2) && !defined(QT_C2_CMP2_INIT)
#define QT_C2_CMP2_INIT	QT_C2_COMPARE_REG2
#endif
#if defined(QT_C2_LOAD_REG) && !defined(QT_C2_LOAD_INIT)
#define QT_C2_LOAD_INIT	QT_C2_LOAD_REG
#endif
#if defined(QT_C2_COUNTER_REG) && !defined(QT_C2_CNTR_INIT)
#define QT_C2_CNTR_INIT	QT_C2_COUNTER_REG
#endif

#if defined(QT_C3_CONTROL_REG) && !defined(QT_C3_CTRL_INIT)
#define QT_C3_CTRL_INIT	QT_C3_CONTROL_REG
#endif
#if defined(QT_C3_STATUS_CONTROL_REG) && !defined(QT_C3_SCR_INIT)
#define QT_C3_SCR_INIT	QT_C3_STATUS_CONTROL_REG
#endif
#if defined(QT_C3_COMPARE_REG1) && !defined(QT_C3_CMP1_INIT)
#define QT_C3_CMP1_INIT	QT_C3_COMPARE_REG1
#endif
#if defined(QT_C3_COMPARE_REG2) && !defined(QT_C3_CMP2_INIT)
#define QT_C3_CMP2_INIT	QT_C3_COMPARE_REG2
#endif
#if defined(QT_C3_LOAD_REG) && !defined(QT_C3_LOAD_INIT)
#define QT_C3_LOAD_INIT	QT_C3_LOAD_REG
#endif
#if defined(QT_C3_COUNTER_REG) && !defined(QT_C3_CNTR_INIT)
#define QT_C3_CNTR_INIT	QT_C3_COUNTER_REG
#endif

#if defined(QT_D0_CONTROL_REG) && !defined(QT_D0_CTRL_INIT)
#define QT_D0_CTRL_INIT	QT_D0_CONTROL_REG
#endif
#if defined(QT_D0_STATUS_CONTROL_REG) && !defined(QT_D0_SCR_INIT)
#define QT_D0_SCR_INIT	QT_D0_STATUS_CONTROL_REG
#endif
#if defined(QT_D0_COMPARE_REG1) && !defined(QT_D0_CMP1_INIT)
#define QT_D0_CMP1_INIT	QT_D0_COMPARE_REG1
#endif
#if defined(QT_D0_COMPARE_REG2) && !defined(QT_D0_CMP2_INIT)
#define QT_D0_CMP2_INIT	QT_D0_COMPARE_REG2
#endif
#if defined(QT_D0_LOAD_REG) && !defined(QT_D0_LOAD_INIT)
#define QT_D0_LOAD_INIT	QT_D0_LOAD_REG
#endif
#if defined(QT_D0_COUNTER_REG) && !defined(QT_D0_CNTR_INIT)
#define QT_D0_CNTR_INIT	QT_D0_COUNTER_REG
#endif

#if defined(QT_D1_CONTROL_REG) && !defined(QT_D1_CTRL_INIT)
#define QT_D1_CTRL_INIT	QT_D1_CONTROL_REG
#endif
#if defined(QT_D1_STATUS_CONTROL_REG) && !defined(QT_D1_SCR_INIT)
#define QT_D1_SCR_INIT	QT_D1_STATUS_CONTROL_REG
#endif
#if defined(QT_D1_COMPARE_REG1) && !defined(QT_D1_CMP1_INIT)
#define QT_D1_CMP1_INIT	QT_D1_COMPARE_REG1
#endif
#if defined(QT_D1_COMPARE_REG2) && !defined(QT_D1_CMP2_INIT)
#define QT_D1_CMP2_INIT	QT_D1_COMPARE_REG2
#endif
#if defined(QT_D1_LOAD_REG) && !defined(QT_D1_LOAD_INIT)
#define QT_D1_LOAD_INIT	QT_D1_LOAD_REG
#endif
#if defined(QT_D1_COUNTER_REG) && !defined(QT_D1_CNTR_INIT)
#define QT_D1_CNTR_INIT	QT_D1_COUNTER_REG
#endif

#if defined(QT_D2_CONTROL_REG) && !defined(QT_D2_CTRL_INIT)
#define QT_D2_CTRL_INIT	QT_D2_CONTROL_REG
#endif
#if defined(QT_D2_STATUS_CONTROL_REG) && !defined(QT_D2_SCR_INIT)
#define QT_D2_SCR_INIT	QT_D2_STATUS_CONTROL_REG
#endif
#if defined(QT_D2_COMPARE_REG1) && !defined(QT_D2_CMP1_INIT)
#define QT_D2_CMP1_INIT	QT_D2_COMPARE_REG1
#endif
#if defined(QT_D2_COMPARE_REG2) && !defined(QT_D2_CMP2_INIT)
#define QT_D2_CMP2_INIT	QT_D2_COMPARE_REG2
#endif
#if defined(QT_D2_LOAD_REG) && !defined(QT_D2_LOAD_INIT)
#define QT_D2_LOAD_INIT	QT_D2_LOAD_REG
#endif
#if defined(QT_D2_COUNTER_REG) && !defined(QT_D2_CNTR_INIT)
#define QT_D2_CNTR_INIT	QT_D2_COUNTER_REG
#endif

#if defined(QT_D3_CONTROL_REG) && !defined(QT_D3_CTRL_INIT)
#define QT_D3_CTRL_INIT	QT_D3_CONTROL_REG
#endif
#if defined(QT_D3_STATUS_CONTROL_REG) && !defined(QT_D3_SCR_INIT)
#define QT_D3_SCR_INIT	QT_D3_STATUS_CONTROL_REG
#endif
#if defined(QT_D3_COMPARE_REG1) && !defined(QT_D3_CMP1_INIT)
#define QT_D3_CMP1_INIT	QT_D3_COMPARE_REG1
#endif
#if defined(QT_D3_COMPARE_REG2) && !defined(QT_D3_CMP2_INIT)
#define QT_D3_CMP2_INIT	QT_D3_COMPARE_REG2
#endif
#if defined(QT_D3_LOAD_REG) && !defined(QT_D3_LOAD_INIT)
#define QT_D3_LOAD_INIT	QT_D3_LOAD_REG
#endif
#if defined(QT_D3_COUNTER_REG) && !defined(QT_D3_CNTR_INIT)
#define QT_D3_CNTR_INIT	QT_D3_COUNTER_REG
#endif

/* sci */

#if defined(SCI_0_BAUD_RATE_REG) && !defined(SCI_0_SCIBR_INIT)
#define SCI_0_SCIBR_INIT	SCI_0_BAUD_RATE_REG
#endif
#if defined(SCI_0_CONTROL_REG) && !defined(SCI_0_SCICR_INIT)
#define SCI_0_SCICR_INIT	SCI_0_CONTROL_REG
#endif

#if defined(SCI_1_BAUD_RATE_REG) && !defined(SCI_1_SCIBR_INIT)
#define SCI_1_SCIBR_INIT	SCI_1_BAUD_RATE_REG
#endif
#if defined(SCI_1_CONTROL_REG) && !defined(SCI_1_SCICR_INIT)
#define SCI_1_SCICR_INIT	SCI_1_CONTROL_REG
#endif

/* spi */

#if defined(SPI_0_STATUS_CONTROL_REG) && !defined(SPI_0_SPSCR_INIT)
#define SPI_0_SPSCR_INIT	SPI_0_STATUS_CONTROL_REG
#endif
#if defined(SPI_0_DATA_SIZE_REG) && !defined(SPI_0_SPDSCR_INIT)
#define SPI_0_SPDSCR_INIT	SPI_0_DATA_SIZE_REG
#endif

#if defined(SPI_1_STATUS_CONTROL_REG) && !defined(SPI_1_SPSCR_INIT)
#define SPI_1_SPSCR_INIT	SPI_1_STATUS_CONTROL_REG
#endif
#if defined(SPI_1_DATA_SIZE_REG) && !defined(SPI_1_SPDSCR_INIT)
#define SPI_1_SPDSCR_INIT	SPI_1_DATA_SIZE_REG
#endif

/* sys */

#if defined(SYS_CONTROL_REG) && !defined(SIM_CONROL_INIT)
#define SIM_CONROL_INIT	SYS_CONTROL_REG
#endif

/* semi */

#if defined(SYS_BASEREG_0) && !defined(SEMI_CSBAR0_INIT)
#define SEMI_CSBAR0_INIT	SYS_BASEREG_0
#endif
#if defined(SYS_BASEREG_1) && !defined(SEMI_CSBAR1_INIT)
#define SEMI_CSBAR1_INIT	SYS_BASEREG_1
#endif
#if defined(SYS_BASEREG_2) && !defined(SEMI_CSBAR2_INIT)
#define SEMI_CSBAR2_INIT	SYS_BASEREG_2
#endif
#if defined(SYS_BASEREG_3) && !defined(SEMI_CSBAR3_INIT)
#define SEMI_CSBAR3_INIT	SYS_BASEREG_3
#endif
#if defined(SYS_BASEREG_4) && !defined(SEMI_CSBAR4_INIT)
#define SEMI_CSBAR4_INIT	SYS_BASEREG_4
#endif
#if defined(SYS_BASEREG_5) && !defined(SEMI_CSBAR5_INIT)
#define SEMI_CSBAR5_INIT	SYS_BASEREG_5
#endif
#if defined(SYS_BASEREG_6) && !defined(SEMI_CSBAR6_INIT)
#define SEMI_CSBAR6_INIT	SYS_BASEREG_6
#endif
#if defined(SYS_BASEREG_7) && !defined(SEMI_CSBAR7_INIT)
#define SEMI_CSBAR7_INIT	SYS_BASEREG_7
#endif

#if defined(SYS_OPTIONREG_0) && !defined(SEMI_CSOR0_INIT)
#define SEMI_CSOR0_INIT	SYS_OPTIONREG_0
#endif
#if defined(SYS_OPTIONREG_1) && !defined(SEMI_CSOR1_INIT)
#define SEMI_CSOR1_INIT	SYS_OPTIONREG_1
#endif
#if defined(SYS_OPTIONREG_2) && !defined(SEMI_CSOR2_INIT)
#define SEMI_CSOR2_INIT	SYS_OPTIONREG_2
#endif
#if defined(SYS_OPTIONREG_3) && !defined(SEMI_CSOR3_INIT)
#define SEMI_CSOR3_INIT	SYS_OPTIONREG_3
#endif
#if defined(SYS_OPTIONREG_4) && !defined(SEMI_CSOR4_INIT)
#define SEMI_CSOR4_INIT	SYS_OPTIONREG_4
#endif
#if defined(SYS_OPTIONREG_5) && !defined(SEMI_CSOR5_INIT)
#define SEMI_CSOR5_INIT	SYS_OPTIONREG_5
#endif
#if defined(SYS_OPTIONREG_6) && !defined(SEMI_CSOR6_INIT)
#define SEMI_CSOR6_INIT	SYS_OPTIONREG_6
#endif
#if defined(SYS_OPTIONREG_7) && !defined(SEMI_CSOR7_INIT)
#define SEMI_CSOR7_INIT	SYS_OPTIONREG_7
#endif

#endif /* __COMPAT_H */

