
/****************************************************************
* WARNING this file is automatically generated DO NOT EDIT IT!   
*                                                                
* This file provides an interface between eTPU code and CPU      
* code. All references to the ASAC function should be made with
* information in this file. This allows only symbolic            
* information to be referenced which allows the eTPU code to be  
* optimized without effecting the CPU code.                      
*****************************************************************/
#ifndef _FS_ETPU_ASAC_AUTO_H_
#define _FS_ETPU_ASAC_AUTO_H_

/****************************************************************
* Function Configuration Information.
****************************************************************/
#define FS_ETPU_ASAC_FUNCTION_NUMBER                  6 
#define FS_ETPU_ASAC_TABLE_SELECT                    1 
#define FS_ETPU_ASAC_NUM_PARMS                       0x0098 

/****************************************************************
* Host Service Request Definitions.
****************************************************************/
#define FS_ASAC_HSR_INIT_PERIOD_MODE            7 
#define FS_ASAC_HSR_INIT_SYNC_MODE              5   
#define FS_ASAC_HSR_MEASURE_DC_OFFSETS          2

/****************************************************************
* Parameter Definitions.
****************************************************************/
#define FS_ETPU_ASAC_MEASURE_TIME_OFFSET             0x000D
#define FS_ETPU_ASAC_PERIOD_OFFSET                   0x0001
#define FS_ETPU_ASAC_P_EDGE_TIME_OFFSET              0x0009
#define FS_ETPU_ASAC_START_OFFSET_OFFSET             0x0005
#define FS_ETPU_ASAC_PERIODS_PER_OUTERLOOP_OFFSET    0x0011
#define FS_ETPU_ASAC_OUTERLOOP_CHAN_OFFSET           0x0000
#define FS_ETPU_ASAC_INNERLOOP_CHAN_OFFSET           0x0004
#define FS_ETPU_ASAC_RESULT_QUEUE_OFFSET             0x0015
#define FS_ETPU_ASAC_BIT_SHIFT_OFFSET                0x0019
#define FS_ETPU_ASAC_MEASURE_DC_OFFSET_MASK_OFFSET   0x0018
#define FS_ETPU_ASAC_QUEUE_OFFSET_A_OFFSET           0x0008
#define FS_ETPU_ASAC_QUEUE_OFFSET_B_OFFSET           0x000C
#define FS_ETPU_ASAC_QUEUE_OFFSET_C_OFFSET           0x0010
#define FS_ETPU_ASAC_QUEUE_OFFSET_D_OFFSET           0x0014
#define FS_ETPU_ASAC_DC_OFFSET_A_OFFSET              0x001D
#define FS_ETPU_ASAC_DC_OFFSET_B_OFFSET              0x0021
#define FS_ETPU_ASAC_DC_OFFSET_C_OFFSET              0x0025
#define FS_ETPU_ASAC_DC_OFFSET_D_OFFSET              0x0029
#define FS_ETPU_ASAC_FORGET_FACTOR_A_OFFSET          0x002D
#define FS_ETPU_ASAC_FORGET_FACTOR_B_OFFSET          0x0031
#define FS_ETPU_ASAC_FORGET_FACTOR_C_OFFSET          0x0035
#define FS_ETPU_ASAC_FORGET_FACTOR_D_OFFSET          0x0039
#define FS_ETPU_ASAC_OUTPUT_A_OFFSET                 0x003D
#define FS_ETPU_ASAC_OUTPUT_B_OFFSET                 0x0041
#define FS_ETPU_ASAC_OUTPUT_C_OFFSET                 0x0045
#define FS_ETPU_ASAC_OUTPUT_D_OFFSET                 0x0049
#define FS_ETPU_ASAC_P_OUTPUT_A_OFFSET               0x004D
#define FS_ETPU_ASAC_P_OUTPUT_B_OFFSET               0x0051
#define FS_ETPU_ASAC_P_OUTPUT_C_OFFSET               0x0055
#define FS_ETPU_ASAC_P_OUTPUT_D1_OFFSET              0x0059
#define FS_ETPU_ASAC_P_OUTPUT_D2_OFFSET              0x005D
#define FS_ETPU_ASAC_MEASURE_SAMPLES_MASK_OFFSET     0x001C
#define FS_ETPU_ASAC_P_PWMMAC_SECTOR_OFFSET          0x0061
#define FS_ETPU_ASAC_SECTOR_OFFSET                   0x0020
#define FS_ETPU_ASAC_DTC_THRESHOLD_OFFSET            0x0065
#define FS_ETPU_ASAC_P_DTC_A_OFFSET                  0x0069
#define FS_ETPU_ASAC_P_DTC_B_OFFSET                  0x006D
#define FS_ETPU_ASAC_P_DTC_C_OFFSET                  0x0071
#define FS_ETPU_ASAC_OPTIONS_OFFSET                  0x0024
#define FS_ETPU_ASAC_ADC0_I_A_CMD_OFFSET             0x0074
#define FS_ETPU_ASAC_ADC1_I_A_CMD_OFFSET             0x0078
#define FS_ETPU_ASAC_ADC0_I_B_CMD_OFFSET             0x007C
#define FS_ETPU_ASAC_ADC1_I_B_CMD_OFFSET             0x0080
#define FS_ETPU_ASAC_ADC0_I_C_CMD_OFFSET             0x0084
#define FS_ETPU_ASAC_ADC1_I_C_CMD_OFFSET             0x0088
#define FS_ETPU_ASAC_P_APPLIED_EQADC_CMDS_OFFSET     0x008D
#define FS_ETPU_ASAC_SECTOR_PLACE_HOLDER_OFFSET    0x0030

/****************************************************************
* Value Definitions.
****************************************************************/
#define FS_ETPU_ASAC_FM_PHASE_CURRENTS_OFF 0
#define FS_ETPU_ASAC_FM_PHASE_CURRENTS_ON  1
#define FS_ETPU_ASAC_FM_DTC_OFF            0
#define FS_ETPU_ASAC_FM_DTC_ON             2

#define FS_ETPU_ASAC_OPTION_DMA_INTR_1ST_EDGE     1 
#define FS_ETPU_ASAC_OPTION_DMA_INTR_2ND_EDGE     2 
#define FS_ETPU_ASAC_OPTION_UPDATE_COMMAND_QUEUE  4 
#define FS_ETPU_ASAC_OPTION_POLARITY_1ST_LOW_2ND_HIGH  8 
#define FS_ETPU_ASAC_OPTION_INVERT_CURRENTS       16 

#endif
