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etpu_util.h

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00001 /*******************************************************************************
00002 *
00003 * Freescale Semiconductor Inc.
00004 * (c) Copyright 2004-2012 Freescale Semiconductor, Inc.
00005 * ALL RIGHTS RESERVED.
00006 *
00007 ****************************************************************************//*!
00008 *
00009 * @file    etpu_util.h
00010 *
00011 * @author  Milan Brejl [r54529]
00012 * 
00013 * @version 3.2
00014 * 
00015 * @date    21-Mar-2014
00016 *
00017 * @brief   This file contains useful macros and prototypes for using the eTPU
00018 *          and eTPU2.
00019 *
00020 *******************************************************************************/
00021 #ifndef _ETPU_UTIL_H_
00022 #define _ETPU_UTIL_H_
00023 
00024 /*******************************************************************************
00025 * Includes
00026 *******************************************************************************/
00027 #include "typedefs.h"     /* standard types */
00028 #include "etpu_struct.h"  /* eTPU module structure definition */
00029 
00030 /*******************************************************************************
00031 * Macros
00032 *******************************************************************************/
00033 /***************************************************************************//*!
00034 * @brief   Channel number expressed by (engine, channel)
00035 * @note    All channel numbers for both eTPUs are absolute.
00036 *          eTPU_A has channels 0-31 and eTPU_B has channels 64-95.
00037 *******************************************************************************/
00038 #define FS_ETPU_ENGINE_CHANNEL(x,y) (((x)-1)*64 + y)
00039 
00040 /***************************************************************************//*!
00041 * @brief   Transformation from absolute channel number to link register encoding
00042 *******************************************************************************/
00043 #define FS_ETPU_CHANNEL_TO_LINK(x)  ((x)+64)
00044 
00045 #ifndef TRUE
00046 #define TRUE  1
00047 #endif
00048 
00049 #ifndef FALSE
00050 #define FALSE 0
00051 #endif
00052 
00053 /*******************************************************************************
00054 * Global variables
00055 *******************************************************************************/
00056 /** @brief   Pointer to the first free parameter in eTPU DATA RAM */
00057 extern uint32_t *fs_free_param;
00058 
00059 /** @brief   Access to eTPU registers' structure */
00060 extern struct eTPU_struct *eTPU;
00061 
00062 /*******************************************************************************
00063 * Type Definitions
00064 *******************************************************************************/
00065 typedef uint32_t ufract24_t;
00066 typedef int32_t fract24_t;
00067 
00068 typedef uint32_t uint24_t;
00069 typedef int32_t int24_t;
00070 
00071 /* Configuration structure */
00072 struct etpu_config_t{
00073   uint32_t mcr;
00074   uint32_t misc;
00075   uint32_t ecr_a;
00076   uint32_t tbcr_a;
00077   uint32_t stacr_a;
00078   uint32_t ecr_b;
00079   uint32_t tbcr_b;
00080   uint32_t stacr_b;
00081   uint32_t wdtr_a;
00082   uint32_t wdtr_b;
00083 };
00084 
00085 /*******************************************************************************
00086 * Function prototypes
00087 *******************************************************************************/
00088 /* eTPU Module Initialization */
00089 uint32_t fs_etpu_init(
00090   struct etpu_config_t p_etpu_config,
00091   uint32_t *code,
00092   uint32_t code_size,
00093   uint32_t *globals,
00094   uint32_t globals_size);
00095 
00096 uint32_t fs_etpu2_init(
00097   struct etpu_config_t p_etpu_config,
00098   uint32_t engine_mem_size);
00099 
00100 /* eTPU Channel Initialization */
00101 uint32_t *fs_etpu_chan_init(
00102   uint8_t channel,
00103   uint8_t function,
00104   uint8_t mode,
00105   uint8_t hsr,
00106   uint8_t num_param,
00107   uint32_t config,
00108   uint32_t *func_frame);
00109 
00110 uint32_t *fs_etpu_malloc(
00111   uint16_t num_bytes);
00112 uint32_t *fs_etpu_malloc2(
00113   uint8_t channel,
00114   uint16_t num_bytes);
00115 
00116 /* Run-Time eTPU Module Control */
00117 void fs_timer_start(void);
00118 uint32_t fs_etpu_get_global_exceptions(void);
00119 void fs_etpu_clear_global_exceptions(void);
00120 uint32_t fs_etpu_get_global_error(void);
00121 void fs_etpu_set_interrupt_mask_a(
00122   uint32_t mask);
00123 void fs_etpu_set_interrupt_mask_b(
00124   uint32_t mask);
00125 void fs_etpu_set_dma_mask_a(
00126   uint32_t mask);
00127 void fs_etpu_set_dma_mask_b(
00128   uint32_t mask);
00129 void fs_etpu_set_output_disable_mask_a(
00130   uint32_t mask,
00131   uint32_t polarity);
00132 void fs_etpu_set_output_disable_mask_b(
00133   uint32_t mask,
00134   uint32_t polarity);
00135 
00136 /* Run-Time eTPU Channel Control */
00137 uint8_t fs_etpu_get_hsr(
00138   uint8_t channel);
00139 void fs_etpu_set_hsr(
00140   uint8_t channel,
00141   uint8_t hsr);
00142 
00143 void fs_etpu_enable(
00144   uint8_t channel,
00145   uint8_t priority);
00146 void fs_etpu_disable(
00147   uint8_t channel);
00148 
00149 void fs_etpu_interrupt_enable(
00150   uint8_t channel);
00151 void fs_etpu_interrupt_disable(
00152   uint8_t channel);
00153 
00154 uint8_t fs_etpu_get_chan_interrupt_flag(
00155   uint8_t channel);
00156 void fs_etpu_clear_chan_interrupt_flag(
00157   uint8_t channel);
00158 
00159 uint8_t fs_etpu_get_chan_interrupt_overflow_flag(
00160   uint8_t channel);
00161 void fs_etpu_clear_chan_interrupt_overflow_flag(
00162   uint8_t channel);
00163 
00164 void fs_etpu_dma_enable(
00165   uint8_t channel);
00166 void fs_etpu_dma_disable(
00167   uint8_t channel);
00168 
00169 uint8_t fs_etpu_get_chan_dma_flag(
00170   uint8_t channel);
00171 void fs_etpu_clear_chan_dma_flag(
00172   uint8_t channel);
00173 
00174 uint8_t fs_etpu_get_chan_dma_overflow_flag(
00175   uint8_t channel);
00176 void fs_etpu_clear_chan_dma_overflow_flag(
00177   uint8_t channel);
00178 
00179 /* eTPU DATA RAM Access */
00180 uint32_t *fs_etpu_data_ram(
00181   uint8_t channel);
00182 
00183 uint32_t fs_etpu_get_chan_local_32(
00184   uint8_t channel,
00185   uint32_t offset);
00186 uint24_t fs_etpu_get_chan_local_24(
00187   uint8_t channel,
00188   uint32_t offset);
00189 int24_t fs_etpu_get_chan_local_24s(
00190   uint8_t channel,
00191   uint32_t offset);
00192 uint16_t fs_etpu_get_chan_local_16(
00193   uint8_t channel,
00194   uint32_t offset);
00195 uint8_t  fs_etpu_get_chan_local_8(
00196   uint8_t channel,
00197   uint32_t offset);
00198 
00199 void fs_etpu_set_chan_local_32(
00200   uint8_t channel,
00201   uint32_t offset,
00202   uint32_t value);
00203 void fs_etpu_set_chan_local_24(
00204   uint8_t channel,
00205   uint32_t offset,
00206   uint24_t value);
00207 void fs_etpu_set_chan_local_16(
00208   uint8_t channel,
00209   uint32_t offset,
00210   uint16_t value);
00211 void fs_etpu_set_chan_local_8(
00212   uint8_t channel,
00213   uint32_t offset,
00214   uint8_t value);
00215 
00216 uint32_t fs_etpu_get_global_32(
00217   uint32_t offset);
00218 int24_t fs_etpu_get_global_24s(
00219   uint32_t offset);
00220 uint24_t fs_etpu_get_global_24(
00221   uint32_t offset);
00222 uint16_t fs_etpu_get_global_16(
00223   uint32_t offset);
00224 uint8_t  fs_etpu_get_global_8(
00225   uint32_t offset);
00226 
00227 void fs_etpu_set_global_32(
00228   uint32_t offset,
00229   uint32_t value);
00230 void fs_etpu_set_global_24(
00231   uint32_t offset,
00232   uint24_t value);
00233 void fs_etpu_set_global_16(
00234   uint32_t offset,
00235   uint16_t value);
00236 void fs_etpu_set_global_8(
00237   uint32_t offset,
00238   uint8_t value);
00239 
00240 uint32_t fs_etpu_coherent_read_24(
00241   uint8_t channel,
00242   uint32_t offset1,
00243   uint32_t offset2,
00244   int32_t *value1,
00245   int32_t *value2);
00246 uint32_t fs_etpu_coherent_read_32(
00247   uint8_t channel,
00248   uint32_t offset1,
00249   uint32_t offset2,
00250   uint32_t *value1,
00251   uint32_t *value2);
00252 uint32_t fs_etpu_coherent_write_24(
00253   uint8_t channel,
00254   uint32_t offset1,
00255   uint32_t offset2,
00256   int32_t value1,
00257   int32_t value2);
00258 uint32_t fs_etpu_coherent_write_32(
00259   uint8_t channel,
00260   uint32_t offset1,
00261   uint32_t offset2,
00262   uint32_t value1,
00263   uint32_t value2);
00264 
00265 /* eTPU Load Evaluation */
00266 uint24_t fs_etpu_get_idle_cnt_a(void);
00267 uint24_t fs_etpu_get_idle_cnt_b(void);
00268 void fs_etpu_clear_idle_cnt_a(void);
00269 void fs_etpu_clear_idle_cnt_b(void);
00270 
00271 /* Others */
00272 uint32_t *fs_memcpy32(
00273   uint32_t *dest,
00274   uint32_t *source,
00275   uint32_t size);
00276 void fs_memset32(
00277   uint32_t *start,
00278   uint32_t value,
00279   int32_t size);
00280 
00281 
00282 /*******************************************************************************
00283 * Definition of Terms
00284 *******************************************************************************/
00285 /* Channel Priority values used by several function APIs */
00286 #define FS_ETPU_PRIORITY_HIGH         0x3
00287 #define FS_ETPU_PRIORITY_MIDDLE       0x2
00288 #define FS_ETPU_PRIORITY_LOW          0x1
00289 #define FS_ETPU_PRIORITY_DISABLE      0x0
00290 
00291 #define FS_ETPU_PIN_HIGH 1
00292 #define FS_ETPU_PIN_LOW  0
00293 
00294 /* eTPU timebases */
00295 #define FS_ETPU_TCR1   0
00296 #define FS_ETPU_TCR2   1
00297 #define FS_ETPU_TCR1_A 0
00298 #define FS_ETPU_TCR2_A 1
00299 #define FS_ETPU_TCR1_B 0
00300 #define FS_ETPU_TCR2_B 1
00301 
00302 /* MCR - Module Configuration Register */
00303 #define FS_ETPU_MISC_ENABLE            0x00000200 /* Code RAM MISC Enable */
00304 #define FS_ETPU_MISC_DISABLE           0x00000000
00305 
00306 #define FS_ETPU_VIS_ON                 0x00000040 /* Code RAM Visibility */
00307 #define FS_ETPU_VIS_OFF                0x00000000
00308 
00309 #define FS_ETPU_GLOBAL_TIMEBASE_ENABLE  0x00000001 /* Global Time Base Enable */
00310 #define FS_ETPU_GLOBAL_TIMEBASE_DISABLE 0x00000000
00311 
00312 #define FS_ETPU_SDM_READ_ERROR         0x40000000  /* eTPU2 only */
00313 #define FS_ETPU_WATCHDOG_TIMEOUT_A     0x20000000  /* eTPU2 only */
00314 #define FS_ETPU_WATCHDOG_TIMEOUT_B     0x10000000  /* eTPU2 only */
00315 #define FS_ETPU_MICROCODE_GLOBAL_EX_A  0x08000000
00316 #define FS_ETPU_MICROCODE_GLOBAL_EX_B  0x04000000
00317 #define FS_ETPU_ILLEGAL_INSTRUCTION_A  0x02000000
00318 #define FS_ETPU_ILLEGAL_INSTRUCTION_B  0x01000000
00319 #define FS_ETPU_SHARED_SUBSYS_ACC_ERR  0x00800000  /* eTPU2 only */
00320 #define FS_ETPU_SCM_MISC_FLAG          0x00000400
00321 #define FS_ETPU_SCM_READ_ERROR         0x00000100  /* eTPU2 only */
00322 
00323 /* ECR - Engine Configuration Register */
00324 #define FS_ETPU_FILTER_CLOCK_DIV2      0x00000000 /* Filter Prescaler Clock */
00325 #define FS_ETPU_FILTER_CLOCK_DIV4      0x00010000 /* Control                */
00326 #define FS_ETPU_FILTER_CLOCK_DIV8      0x00020000
00327 #define FS_ETPU_FILTER_CLOCK_DIV16     0x00030000
00328 #define FS_ETPU_FILTER_CLOCK_DIV32     0x00040000
00329 #define FS_ETPU_FILTER_CLOCK_DIV64     0x00050000
00330 #define FS_ETPU_FILTER_CLOCK_DIV128    0x00060000
00331 #define FS_ETPU_FILTER_CLOCK_DIV256    0x00070000
00332 
00333 #define FS_ETPU_FCSS_DIV2              0x00000000 /* Filter Clock Source Selection */
00334 #define FS_ETPU_FCSS_DIV1              0x00080000 /* eTPU2 only */
00335 
00336 #define FS_ETPU_CHAN_FILTER_2SAMPLE    0x00000000 /* Channel filter mode */
00337 #define FS_ETPU_CHAN_FILTER_3SAMPLE    0x00008000
00338 #define FS_ETPU_CHAN_FILTER_CONT       0x0000C000
00339 #define FS_ETPU_CHAN_FILTER_BYPASS     0x00004000 /* eTPU2 only */
00340 
00341 #define FS_ETPU_ENGINE_ENABLE          0x00000000  /* Low Power Stop Bit */
00342 #define FS_ETPU_ENGINE_DISABLE         0x40000000
00343 
00344 #define FS_ETPU_PRIORITY_PASSING_ENABLE   0x00000000 /* Scheduler Priority Passing */
00345 #define FS_ETPU_PRIORITY_PASSING_DISABLE  0x00000080 /* eTPU2 only */
00346 
00347 /* TBCR - Time Base Configuration Register */
00348 #define FS_ETPU_TCRCLK_MODE_2SAMPLE     0x00000000 /* TCRCLK Signal Filter Control*/
00349 #define FS_ETPU_TCRCLK_MODE_INTEGRATION 0x10000000
00350 #define FS_ETPU_TCRCLK_INPUT_DIV2CLOCK  0x00000000
00351 #define FS_ETPU_TCRCLK_INPUT_CHANCLOCK  0x08000000
00352 
00353 #define FS_ETPU_TCR1CTL_TCRCLK         0x00000000  /* TCR1 Clock/Gate Control */
00354 #define FS_ETPU_TCR1CTL_DIV2           0x00008000
00355 
00356 #define FS_ETPU_TCR1CS_DIV2            0x00000000  /* TCR1 Clock Source */
00357 #define FS_ETPU_TCR1CS_DIV1            0x00002000  /* eTPU2 only */
00358 
00359 #define FS_ETPU_ANGLE_MODE_ENABLE      0x02000000   /* Angle Mode */
00360 #define FS_ETPU_ANGLE_MODE_DISABLE     0x00000000
00361 #define FS_ETPU_ANGLE_MODE_ENABLE_CH1  0x04000000   /* eTPU2 only */
00362 #define FS_ETPU_ANGLE_MODE_ENABLE_CH2  0x06000000   /* eTPU2 only */
00363 
00364 #define FS_ETPU_TCR2CTL_GATEDDIV8      0x00000000   /* TCR2 Clock/Gate Control */
00365 #define FS_ETPU_TCR2CTL_RISE           0x20000000
00366 #define FS_ETPU_TCR2CTL_FALL           0x40000000
00367 #define FS_ETPU_TCR2CTL_RISEFALL       0x60000000
00368 #define FS_ETPU_TCR2CTL_DIV8           0x80000000
00369 
00370 #define FS_ETPU_TCR1_PRESCALER(x)      (((x)-1) & 0xFF) /* TCR1 Prescaler, x = 1 to 256 */
00371 #define FS_ETPU_TCR2_PRESCALER(x)      ((((x)-1) & 0x3F)<<16) /* TCR2 Prescaler, x = 1 to 64 */
00372 
00373 /* STACR - Shared Time And Angle Count Register */
00374 #define FS_ETPU_TCR1_STAC_ENABLE       0x80000000   /* TCR1 Resource Enable */
00375 #define FS_ETPU_TCR1_STAC_DISABLE      0x00000000
00376 
00377 #define FS_ETPU_TCR1_STAC_CLIENT       0x00000000   /* TCR1 Resource Control */
00378 #define FS_ETPU_TCR1_STAC_SERVER       0x40000000
00379 
00380 #define FS_ETPU_TCR1_STAC_SRVSLOT(x)   (((x) & 0xF)<<16) /* TCR1 Server Slot, x = 0 to 3 */
00381 
00382 #define FS_ETPU_TCR2_STAC_ENABLE       0x00008000   /* TCR2 Resource Enable */
00383 #define FS_ETPU_TCR2_STAC_DISABLE      0x00000000
00384 
00385 #define FS_ETPU_TCR2_STAC_CLIENT       0x00000000   /* TCR2 Resource Control */
00386 #define FS_ETPU_TCR2_STAC_SERVER       0x00004000
00387 
00388 #define FS_ETPU_TCR2_STAC_SRVSLOT(x)   ((x) & 0xF)  /* TCR2 Server Slot, x = 0 to 3 */
00389 
00390 /* WDTR - Watchdog Timer Register - eTPU2 only */
00391 #define FS_ETPU_WDM_DISABLED           0x00000000 /* Watchdog Mode */
00392 #define FS_ETPU_WDM_THREAD_LEN         0x80000000 /* eTPU2 only */
00393 #define FS_ETPU_WDM_BUSY_LEN           0xC0000000 /* eTPU2 only */
00394 
00395 #define FS_ETPU_WDTR_WDCNT(x)      ((x) & 0xFFFF) /* Watchdog Count - eTPU2 only */
00396 
00397 /* CxCR - Channel x Configuration Register */
00398 #define FS_ETPU_INTERRUPT_ENABLE       0x80000000  /* Channel Interrupt Enable */
00399 #define FS_ETPU_INTERRUPT_DISABLE      0x00000000
00400 
00401 #define FS_ETPU_DMA_ENABLE             0x40000000  /* Data Transfer Request Enable*/
00402 #define FS_ETPU_DMA_DISABLE            0x00000000
00403 
00404 #define FS_ETPU_ENTRY_TABLE_STANDARD   0x00000000  /* Entry Table Condition Select*/
00405 #define FS_ETPU_ENTRY_TABLE_ALTERNATE  0x01000000
00406 
00407 #define FS_ETPU_ENTRY_TABLE_PIN_INPUT  0x00000000  /* Entry Table Pin Direction*/
00408 #define FS_ETPU_ENTRY_TABLE_PIN_OUTPUT 0x02000000
00409 
00410 #define FS_ETPU_OUTPUT_DISABLE_OFF     0x00000000  /* Output Disable */
00411 #define FS_ETPU_OUTPUT_DISABLE_LOW     0x0000C000
00412 #define FS_ETPU_OUTPUT_DISABLE_HIGH    0x00008000
00413 
00414 /* eTPU error return codes */
00415 #define FS_ETPU_ERROR_NONE             0
00416 #define FS_ETPU_ERROR_MALLOC           1
00417 #define FS_ETPU_ERROR_FREQ             2
00418 #define FS_ETPU_ERROR_VALUE            3
00419 #define FS_ETPU_ERROR_CODESIZE         4
00420 #define FS_ETPU_ERROR_VIS_BIT_NOT_SET  5
00421 #define FS_ETPU_ERROR_ADDRESS          6
00422 #define FS_ETPU_ERROR_TIMING           7
00423 
00424 #endif /* _ETPU_UTIL_H_ */
00425 /*******************************************************************************
00426  *
00427  * Copyright:
00428  *  Freescale Semiconductor, INC. All Rights Reserved.
00429  *  You are hereby granted a copyright license to use, modify, and
00430  *  distribute the SOFTWARE so long as this entire notice is
00431  *  retained without alteration in any modified and/or redistributed
00432  *  versions, and that such modified versions are clearly identified
00433  *  as such. No licenses are granted by implication, estoppel or
00434  *  otherwise under any patents or trademarks of Freescale
00435  *  Semiconductor, Inc. This software is provided on an "AS IS"
00436  *  basis and without warranty.
00437  *
00438  *  To the maximum extent permitted by applicable law, Freescale
00439  *  Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
00440  *  INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
00441  *  PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
00442  *  REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
00443  *  AND ANY ACCOMPANYING WRITTEN MATERIALS.
00444  *
00445  *  To the maximum extent permitted by applicable law, IN NO EVENT
00446  *  SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
00447  *  (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
00448  *  BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
00449  *  PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
00450  *
00451  *  Freescale Semiconductor assumes no responsibility for the
00452  *  maintenance and support of this software
00453  ******************************************************************************/
00454 /*******************************************************************************
00455  *
00456  * REVISION HISTORY:
00457  *
00458  * FILE OWNER: Milan Brejl [r54529]
00459  *
00460  * Revision 3.2  2014/03/21  r54529
00461  * fs_etpu_clear_chan_interrupt_flag and fs_etpu_clear_chan_dma_flag bug fix
00462  * - the overflow flag was cleared as well.
00463  * fs_etpu_get/clear_chan_interrupt_oveflow_flag and 
00464  * fs_etpu_get/clear_chan_dma_overflow_flag added.
00465  *
00466  * Revision 3.01  2013/07/26  r54529
00467  * FS_ETPU_ERROR_TIMING added.
00468  *  
00469  * Revision 3.0  2012/05/17  r54529
00470  * fs_etpu2_init bug fix - engine-relative memory granularity is 512 bytes.
00471  *
00472  * Revision 2.9  2012/05/12  r54529
00473  * fs_etpu2_init bug fix
00474  *  
00475  * Revision 2.8  2012/04/10  r54529
00476  * fs_etpu2_init reworked - engine memory allocated but not initialized, becuase
00477  * the compiler never generated staticly allocated engine variables.   
00478  *  
00479  * Revision 2.7  2012/03/13  r54529
00480  * New macros added:
00481  *  - FS_ETPU_ENTRY_TABLE_PIN_INPUT, FS_ETPU_ENTRY_TABLE_PIN_OUTPUT
00482  *
00483  * Revision 2.6  2012/02/22  r54529
00484  * New functions added:
00485  *  - fs_etpu_set_interrupt_mask_a/b
00486  *  - fs_etpu_set_dma_mask_a/b
00487  *  - fs_etpu_set_output_disable_mask_a/b 
00488  * New macros added:
00489  *  - FS_ETPU_TCR1_PRESCALER(x), FS_ETPU_TCR2_PRESCALER(x)
00490  *  - FS_ETPU_TCR1_STAC_SRVSLOT(x), FS_ETPU_TCR2_STAC_SRVSLOT(x)
00491  *
00492  * Revision 2.5  2012/02/10 13:52:15  r54529
00493  * Spelling and format edits.
00494  *
00495  * Revision 2.4  2012/02/10 08:27:49  r54529
00496  * New functions added:
00497  *  - get_global_error
00498  *  - fs_etpu_get/clear_idle_count_a/b
00499  * Modified (optimized) functions:
00500  *  - fs_etpu_coherent_read/write_24/32
00501  * Code formating cleared.
00502  * All code comments reformated for DoxyGen support.
00503  *
00504  * Revision 2.3  2011/07/11 13:22:15  r54529
00505  * New functions added:
00506  *  - fs_etpu_get/clear_chan_interrupt_flag
00507  *  - fs_etpu_get/clear_chan_dma_flag
00508  *  - fs_etpu_get/clear_global_exceptions
00509  *  - fs_etpu_coherent_read/write_24/32
00510  * Engine TBCR registers written only when ECR.MDIS = 0.
00511  * The eTPU2 supported by adding etpu watchdog initialization into etpu_config_t structure, fs_etpu2_init function and definitions of new eTPU2 register bits.
00512  *
00513  * Revision 2.2  2009/12/17 20:31:07  r54529
00514  * function fs_etpu_chan_init added (restored) - because used by eTPU GCT
00515  *
00516  * Revision 2.1  2009/10/28 14:55:10  r47354
00517  * Added FS_ETPU_ERROR_VIS_BIT_NOT_SET
00518  *
00519  * Revision 2.0  2004/11/30 16:11:34  r12110
00520  * -Updated functions to remove requirement for etpu_config.h file.
00521  *
00522  * Revision 1.1  2004/11/12 10:39:10  r12110
00523  * Initial version checked into CVS.
00524  *..............................................................................
00525  * 0.01  J. Loeliger  13/Jun/03    Initial version of file.
00526  * 0.02  M. Brejl     12/Nov/03    etpu routines elaborated
00527  * 0.03  J. Loeliger  17/Nov/03    Merged several versions of file
00528  *                                  together.
00529  * 0.04  J. Loeliger  19/Mar/04    Change function prefix to fs_ for
00530  *                                  Freescale semiconductor.
00531  * 0.05  J. Loeliger  26/May/04    Added 24 bit data types.
00532  *       M. Brejl                  Added FS_ to macros
00533  *                                 Changed filename to fs_etpu_util
00534  *                                 Added pin high/low macros.
00535  * 0.06 J. Loeliger  20/Jul/04    Change include to just typedefs.h
00536  * 0.07 J. Loeliger  16/Aug/04    Removed typedef from etpu_config_t
00537  * 0.1  J. Loeliger  01/Sep/04    Added fs_etpu_malloc2 function.
00538  ******************************************************************************/