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etpu_inj.h

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00001 /*******************************************************************************
00002 *
00003 * Freescale Semiconductor Inc.
00004 * (c) Copyright 2004-2014 Freescale Semiconductor, Inc.
00005 * ALL RIGHTS RESERVED.
00006 *
00007 ****************************************************************************//*!
00008 *
00009 * @file    etpu_inj.h
00010 *
00011 * @author  Milan Brejl [r54529]
00012 *
00013 * @version 1.0
00014 *
00015 * @date    17-Mar-2014
00016 *
00017 * @brief   This file contains useful macros and prototypes for INJ API.
00018 *
00019 *******************************************************************************/
00020 #ifndef _ETPU_INJ_H_
00021 #define _ETPU_INJ_H_
00022 
00023 /*******************************************************************************
00024 * Includes
00025 *******************************************************************************/
00026 #include "etpu_util.h"        /* 24-bit types */
00027 #include "etpu_inj_auto.h"    /* auto generated header file */
00028 
00029 /*******************************************************************************
00030 * Definitions
00031 *******************************************************************************/
00032 /** Unused BANK channel number */
00033 #define FS_ETPU_INJ_BANK_CHAN_NOT_USED    0xFF
00034 
00035 /** Injection phase configuration */
00036 #define FS_ETPU_INJ_PHASE_DURATION_MASK   0x00FFFFFF
00037 #define FS_ETPU_INJ_PHASE_OUT_LOW         0x00000000
00038 #define FS_ETPU_INJ_PHASE_OUT_HIGH_INJ    0x01000000
00039 #define FS_ETPU_INJ_PHASE_OUT_HIGH_BANK_1 0x02000000
00040 #define FS_ETPU_INJ_PHASE_OUT_HIGH_BANK_2 0x04000000
00041 #define FS_ETPU_INJ_PHASE_OUT_HIGH_BANK_3 0x08000000
00042 #define FS_ETPU_INJ_PHASE_DMA_INJ         0x10000000
00043 #define FS_ETPU_INJ_PHASE_DMA_IRQ_BANK_1  0x20000000  /* eTPU2 only */
00044 #define FS_ETPU_INJ_PHASE_DMA_IRQ_BANK_2  0x40000000  /* eTPU2 only */
00045 #define FS_ETPU_INJ_PHASE_DMA_IRQ_BANK_3  0x80000000  /* eTPU2 only */
00046 
00047 
00048 /*******************************************************************************
00049 * Type Definitions
00050 *******************************************************************************/
00051 /** A structure to represent an instance of INJ.
00052  *  It includes static INJ initialization items. */
00053 struct inj_instance_t
00054 {
00055   const uint8_t  chan_num_inj;  /**< Channel number of the INJ channel. */
00056   const uint8_t  chan_num_bank_1;  /**< Channel number of the 1st BANK channel.
00057     Assign a chanel number or FS_ETPU_INJ_BANK_CHAN_NOT_USED */
00058   const uint8_t  chan_num_bank_2;  /**< Channel number of the 2nd BANK channel.
00059     Assign a chanel number or FS_ETPU_INJ_BANK_CHAN_NOT_USED */
00060   const uint8_t  chan_num_bank_3;  /**< Channel number of the 3rd BANK channel.
00061     Assign a chanel number or FS_ETPU_INJ_BANK_CHAN_NOT_USED */
00062   const uint8_t  priority;  /**< Channel priority for the INJ channel. */
00063   const uint8_t  polarity_inj;  /**< INJ polarity, applies to INJ channel.
00064     It can one any of:
00065     - @ref FS_ETPU_INJ_FM0_ACTIVE_HIGH - active output signal state is high
00066     - @ref FS_ETPU_INJ_FM0_ACTIVE_LOW - active output signal state is low */
00067   const uint8_t  polarity_bank;  /**< INJ polarity, applies to all BANK
00068     channels. It can one any of:
00069     - @ref FS_ETPU_INJ_FM0_ACTIVE_HIGH - active output signal state is high
00070     - @ref FS_ETPU_INJ_FM0_ACTIVE_LOW - active output signal state is low */
00071   const uint24_t  tdc_angle; /**< The cylinder Top Dead Center as a number
00072     of TCR2 angle ticks relative to zero engine angle, in a range corresponding
00073     to 0-720 degrees. */
00074         uint32_t *cpba;     /**< Channel parameter base address.
00075     Set cpba = 0 to use automatic allocation of eTPU DATA RAM for INJ channel
00076     parameters using the eTPU utility function fs_etpu_malloc (recommanded),
00077     or assign the cpba manually by an address where the INJ channel parameter
00078     space will start from, e.g. 0xC3FC8100. */
00079         uint32_t *cpba_injections; /**< Base address of the injections array in
00080     eTPU DATA RAM. Set cpba_injections = 0 to use automatic allocation of the
00081     eTPU DATA RAM space corresponding to the injection_count value,
00082     using the eTPU utility function fs_etpu_malloc (recommanded),
00083     or assign the cpba_injections manually by an address, e.g. 0xC3FC8100. */
00084         uint32_t *cpba_phases; /**< Base address of the injection phase array in
00085     eTPU DATA RAM. Set cpba_phase = 0 to use automatic allocation of eTPU DATA
00086     RAM space corresponding to the phase_count value, using the eTPU utility
00087     function fs_etpu_malloc (recommanded),
00088     or assign the cpba_phases manually by an address, e.g. 0xC3FC8100. */
00089 };
00090 
00091 
00092 /** A structure to represent a configuration of INJ.
00093  *  It includes INJ configuration items which can mostly be changed in
00094  *  run-time. */
00095 struct inj_config_t
00096 {
00097    int24_t angle_irq;  /**< The tdc_angle-relative IRQ angle as a
00098     number of TCR2 ticks. Positive values precede the TDC, negative go after.
00099     The INJ channel interrupt is generated in order to enable the CPU to
00100     update the injection parameters before the first injection start-angle. */
00101    int24_t angle_stop;  /**< The tdc_angle-relative injection stop angle as a
00102     number of TCR2 ticks. Positive values precede the TDC, negative go after.
00103     In case the whole injection sequence has not finieshed, it is stopped
00104     at this angle by setting the INJ and BANK channels to inactive state. */
00105   uint8_t  injection_count;  /**< The count of injections. */
00106   struct inj_injection_config_t *p_injection_config; /**< Pointer to the first
00107     item of an array of the injection configuration structures. */
00108 };
00109 
00110 
00111 /** A structure to represent a single injection configuration. */
00112 struct inj_injection_config_t
00113 {
00114    int24_t angle_start;  /**< The tdc_angle-relative injection start angle as a
00115     number of TCR2 ticks. Positive values precede the TDC, negative go after. */
00116   uint8_t  phase_count;  /**< The count of injection phases. */
00117   uint32_t *p_phase_config; /**< Pointer to the first item of in an array
00118     of injection phase configuration 32-bit words.
00119     Use the following definitions to set a single phase configuration word:
00120       FS_ETPU_INJ_PHASE_DURATION_MASK    - 24-bit mask for phase duration set
00121                                            as a number of TCR1 ticks.
00122       FS_ETPU_INJ_PHASE_OUT_LOW          - output low on an INJ or BANK channel
00123       FS_ETPU_INJ_PHASE_OUT_HIGH_INJ     - output high on the INJ channel
00124       FS_ETPU_INJ_PHASE_OUT_HIGH_BANK_1  - output high on the BANK 1 channel
00125       FS_ETPU_INJ_PHASE_OUT_HIGH_BANK_2  - output high on the BANK 2 channel
00126       FS_ETPU_INJ_PHASE_OUT_HIGH_BANK_3  - output high on the BANK 3 channel
00127       FS_ETPU_INJ_PHASE_DMA_INJ          - generate DMA request on the INJ
00128                                            channel at the phase start
00129       The following applie to eTPU2 only:
00130       FS_ETPU_INJ_PHASE_DMA_IRQ_BANK_1   - generate DMA and IRQ request on the
00131                                            BANK 1 channel at the phase start
00132       FS_ETPU_INJ_PHASE_DMA_IRQ_BANK_2   - generate DMA and IRQ request on the
00133                                            BANK 2 channel at the phase start
00134       FS_ETPU_INJ_PHASE_DMA_IRQ_BANK_3   - generate DMA and IRQ request on the
00135                                            BANK 3 channel at the phase start */
00136 };
00137 
00138 
00139 /** A structure to represent states of INJ. */
00140 struct inj_states_t
00141 {
00142   uint8_t error;      /**< This is the error status of CRANK. It includes
00143     the following error flags:
00144     - @ref FS_ETPU_INJ_ERROR_PREV_INJ_NOT_FINISHED
00145     - @ref FS_ETPU_INJ_ERROR_LATE_START_ANGLE_1ST
00146     - @ref FS_ETPU_INJ_ERROR_LATE_START_ANGLE_NTH
00147     - @ref FS_ETPU_INJ_ERROR_STOPPED_BY_STOP_ANGLE
00148     The eTPU sets the error flags, the CPU clears them after reading. */
00149   uint8_t injection_idx;  /**< This is the index of the actual injection.
00150     It can be 1 to num_injections in case an injection is active, or 0 in case
00151     no injection is active. */
00152   uint8_t phase_idx; /**< This is the index of the actual injection phase.
00153     It can be 1 to num_phases in case an injection phase is active, or 0 in case
00154     no injection phase is active. */
00155 };
00156 
00157 
00158 /*******************************************************************************
00159 * Function prototypes
00160 *******************************************************************************/
00161 /* Initialize */
00162 uint32_t fs_etpu_inj_init(
00163   struct inj_instance_t   *p_inj_instance,
00164   struct inj_config_t     *p_inj_config);
00165 
00166 /* Change configuration */
00167 uint32_t fs_etpu_inj_config(
00168   struct inj_instance_t *p_inj_instance,
00169   struct inj_config_t   *p_inj_config);
00170 
00171 /* Get states */
00172 uint32_t fs_etpu_inj_get_states(
00173   struct inj_instance_t *p_inj_instance,
00174   struct inj_states_t   *p_inj_states);
00175 
00176 #endif /* _ETPU_INJ_H_ */
00177 /*******************************************************************************
00178  *
00179  * Copyright:
00180  *  Freescale Semiconductor, INC. All Rights Reserved.
00181  *  You are hereby granted a copyright license to use, modify, and
00182  *  distribute the SOFTWARE so long as this entire notice is
00183  *  retained without alteration in any modified and/or redistributed
00184  *  versions, and that such modified versions are clearly identified
00185  *  as such. No licenses are granted by implication, estoppel or
00186  *  otherwise under any patents or trademarks of Freescale
00187  *  Semiconductor, Inc. This software is provided on an "AS IS"
00188  *  basis and without warranty.
00189  *
00190  *  To the maximum extent permitted by applicable law, Freescale
00191  *  Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
00192  *  INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
00193  *  PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
00194  *  REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
00195  *  AND ANY ACCOMPANYING WRITTEN MATERIALS.
00196  *
00197  *  To the maximum extent permitted by applicable law, IN NO EVENT
00198  *  SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
00199  *  (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
00200  *  BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
00201  *  PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
00202  *
00203  *  Freescale Semiconductor assumes no responsibility for the
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00205  ******************************************************************************/
00206 /*******************************************************************************
00207  *
00208  * REVISION HISTORY:
00209  *
00210  * FILE OWNER: Milan Brejl [r54529]
00211  *
00212  * Revision 1.0  2014/03/17  r54529
00213  * Minor comment and formating improvements.
00214  * Ready for eTPU Engine Control Library release 1.0.
00215  *
00216  * Revision 0.2  2013/08/02  r54529
00217  * fs_etpu_inj_update() removed.
00218  * Separate polarity for Inj and Bank channels.
00219  *
00220  * Revision 0.1  2012/11/28  r54529
00221  * Initial version of file.
00222  ******************************************************************************/