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etpu_as_auto.h

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00001 
00002 /**************************************************************** 
00003 * WARNING: This file is automatically generated. DO NOT EDIT IT!
00004 *
00005 * COPYRIGHT (c) Freescale 2004-2012, All Rights Reserved
00006 *
00007 * FILE NAME: etpu_as_auto.h
00008 * ARCHITECTURE: eTPU
00009 *
00010 * This file was generated by: etpuc_as.c at Oct 18 2012 18:15:58
00011 *
00012 * This file provides an interface between eTPU code and CPU
00013 * code. All references to the eTPU function should be made with
00014 * information in this file. This allows only symbolic
00015 * information to be referenced which allows the eTPU code to be
00016 * optimized without effecting the CPU code.
00017 *****************************************************************/
00018 #ifndef _ETPU_AS_AUTO_H_
00019 #define _ETPU_AS_AUTO_H_
00020 
00021 /* Function Configuration Information */
00022 #define FS_ETPU_AS_FUNCTION_NUMBER 0
00023 #define FS_ETPU_AS_TABLE_SELECT 1
00024 #define FS_ETPU_AS_NUM_PARMS 0x60
00025 
00026 
00027 /* Host Service Request Definitions */
00028 #define FS_ETPU_AS_HSR_INIT_MODE_PERIODIC 7
00029 #define FS_ETPU_AS_HSR_INIT_MODE_SYNC 5
00030 #define FS_ETPU_AS_HSR_MEASURE_DC_OFFSETS 2
00031 
00032 /* Function Mode Bit Definitions - phases */
00033 #define FS_ETPU_AS_FM0_FRAME_PULSE_ON 1
00034 #define FS_ETPU_AS_FM0_FRAME_PULSE_OFF 0
00035 #define FS_ETPU_AS_FM1_CENTER_PULSE_ON (1 << 1)
00036 #define FS_ETPU_AS_FM1_CENTER_PULSE_OFF (0 << 1)
00037 
00038 /* Parameter Definitions */
00039 #define FS_ETPU_AS_OFFSET_OPTIONS_POLARITY  0x0
00040 #define FS_ETPU_AS_OFFSET_START_OFFSET  0x1
00041 #define FS_ETPU_AS_OFFSET_OPTIONS_LINK  0x4
00042 #define FS_ETPU_AS_OFFSET_PERIOD  0x5
00043 #define FS_ETPU_AS_OFFSET_OPTIONS_IRQ  0x8
00044 #define FS_ETPU_AS_OFFSET_PULSE_ADJUSTMENT_FRAME  0x9
00045 #define FS_ETPU_AS_OFFSET_OPTIONS_CFIFO  0xc
00046 #define FS_ETPU_AS_OFFSET_PULSE_ADJUSTMENT_CENTER 0xd
00047 #define FS_ETPU_AS_OFFSET_SIGNAL_MASK_FRAME  0x10
00048 #define FS_ETPU_AS_OFFSET_PULSE_WIDTH  0x11
00049 #define FS_ETPU_AS_OFFSET_SIGNAL_MASK_CENTER  0x14
00050 #define FS_ETPU_AS_OFFSET_FRAME_TIME  0x15
00051 #define FS_ETPU_AS_OFFSET_SIGNAL_MASK_DC_OFFSET  0x18
00052 #define FS_ETPU_AS_OFFSET_CENTER_TIME  0x19
00053 #define FS_ETPU_AS_OFFSET_SECTOR  0x1c
00054 #define FS_ETPU_AS_OFFSET_PWMM_SECTOR  0x1d
00055 #define FS_ETPU_AS_OFFSET_PHASE_CURRENT_A_IDX  0x20
00056 #define FS_ETPU_AS_OFFSET_PWMM_FRAME_TIME  0x21
00057 #define FS_ETPU_AS_OFFSET_PHASE_CURRENT_B_IDX  0x24
00058 #define FS_ETPU_AS_OFFSET_PWMM_CENTER_TIME  0x25
00059 #define FS_ETPU_AS_OFFSET_PHASE_CURRENT_C_IDX  0x28
00060 #define FS_ETPU_AS_OFFSET_RESULT_QUEUE  0x29
00061 #define FS_ETPU_AS_OFFSET_SIGNAL_COUNT  0x2c
00062 #define FS_ETPU_AS_OFFSET_COMMAND_QUEUE  0x2d
00063 #define FS_ETPU_AS_OFFSET_OPTIONS_PHASE_CURRENTS  0x30
00064 #define FS_ETPU_AS_OFFSET_SIGNAL  0x31
00065 #define FS_ETPU_AS_OFFSET_LINK_CHANS_FRAME_START  0x34
00066 #define FS_ETPU_AS_OFFSET_LINK_CHANS_FRAME_END  0x38
00067 #define FS_ETPU_AS_OFFSET_LINK_CHANS_CENTER_START 0x3c
00068 #define FS_ETPU_AS_OFFSET_LINK_CHANS_CENTER_END  0x40
00069 #define FS_ETPU_AS_OFFSET_CMD_IA_ADC0  0x44
00070 #define FS_ETPU_AS_OFFSET_CMD_IA_ADC1  0x48
00071 #define FS_ETPU_AS_OFFSET_CMD_IB_ADC0  0x4c
00072 #define FS_ETPU_AS_OFFSET_CMD_IB_ADC1  0x50
00073 #define FS_ETPU_AS_OFFSET_CMD_IC_ADC0  0x54
00074 #define FS_ETPU_AS_OFFSET_CMD_IC_ADC1  0x58
00075 
00076 /* Signal Structure Definitions */
00077 #define FS_ETPU_AS_OFFSET_QUEUE_OFFSET  0x00
00078 #define FS_ETPU_AS_OFFSET_GAIN  0x01
00079 #define FS_ETPU_AS_OFFSET_DC_OFFSET  0x05
00080 #define FS_ETPU_AS_OFFSET_FORGET_FACTOR 0x09
00081 #define FS_ETPU_AS_OFFSET_VALUE  0x0D
00082 
00083 /* Value Definitions */
00084 #define FS_ETPU_AS_SIGNALS_MAX  8
00085 #define FS_ETPU_AS_SIGNAL_STRUCT_SIZE  0x10
00086 
00087 /* Polarity Options */
00088 #define FS_ETPU_AS_POLARITY_PULSE_LOW  0
00089 #define FS_ETPU_AS_POLARITY_PULSE_HIGH  1
00090 
00091 /* Phase Currents Options */
00092 #define FS_ETPU_AS_PHASE_CURRENTS_OFF  1
00093 #define FS_ETPU_AS_PHASE_CURRENTS_ON  0
00094 
00095 /* IRQ&DMA Options */
00096 #define FS_ETPU_AS_IRQ_FRAME_PULSE_START  0x01
00097 #define FS_ETPU_AS_IRQ_FRAME_PULSE_END  0x02
00098 #define FS_ETPU_AS_IRQ_CENTER_PULSE_START 0x04
00099 #define FS_ETPU_AS_IRQ_CENTER_PULSE_END  0x08
00100 
00101 /* Link Options */
00102 #define FS_ETPU_AS_LINK_FRAME_PULSE_START  0x01
00103 #define FS_ETPU_AS_LINK_FRAME_PULSE_END  0x02
00104 #define FS_ETPU_AS_LINK_CENTER_PULSE_START 0x04
00105 #define FS_ETPU_AS_LINK_CENTER_PULSE_END  0x08
00106 
00107 /* CFIFO Options */
00108 #define FS_ETPU_AS_CFIFO_FRAME_PULSE_START  0x01
00109 #define FS_ETPU_AS_CFIFO_FRAME_PULSE_END  0x02
00110 #define FS_ETPU_AS_CFIFO_CENTER_PULSE_START 0x04
00111 #define FS_ETPU_AS_CFIFO_CENTER_PULSE_END  0x08
00112 
00113 #endif