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etpu_spark.c

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00001 /*******************************************************************************
00002 *
00003 * Freescale Semiconductor Inc.
00004 * (c) Copyright 2004-2014 Freescale Semiconductor, Inc.
00005 * ALL RIGHTS RESERVED.
00006 *
00007 ****************************************************************************//*!
00008 *
00009 * @file    etpu_spark.c
00010 *
00011 * @author  Milan Brejl [r54529]
00012 *
00013 * @version 1.0
00014 *
00015 * @date    17-Mar-2014
00016 *
00017 * @brief   This file contains API for using the eTPU function
00018 *          Spark (SPARK).
00019 *
00020 ****************************************************************************//*!
00021 *
00022 * @mainpage
00023 *
00024 * The eTPU SPARK APIs @ref etpu_spark.c/.h includes API functions for eTPU
00025 * function Spark.
00026 *
00027 * Each instance of the SPARK eTPU function controls a single SPARK channel.
00028 *
00029 * There is a SPARK parameter tdc_angle, relative to which all angles are
00030 * defined. Positive angles precede the tdc_angle, negative angles come after.
00031 *
00032 * Each instance of the SPARK eTPU function controls a single SPARK channel.
00033 *
00034 * The SPARK eTPU function enables to generate one or more spark output pulses.
00035 * Each spark output includes the main pulse, defined by end_angle and dwell_time
00036 * and limited by min_dwell_time and max_dwell_time. The main pulse is optionaly
00037 * followed by a sequence of multi-pulses, defined by multi_on_time,
00038 * multi_off_time and pulse_count.
00039 *
00040 * The CPU can monitor the SPARK operation using SPARK state variables
00041 * dwell_time_applied and error.
00042 * The reported error flags are:
00043 *   @ref FS_ETPU_SPARK_ERROR_MIN_DWELL_APPLIED - the spark main pulse has
00044 *     been limited by min_dwell_time and the pulse ended at a later angle than
00045 *     the eng_angle. Hence, the commanded dwell_time and the dwell_time_applie 
00046 *     may differ.
00047 *   @ref FS_ETPU_SPARK_ERROR_MAX_DWELL_APPLIED - the spark main pulse has
00048 *     been limited by max_dwell_time and the pulse ended sooner than at the
00049 *     eng_angle. Hence, the commanded dwell_time and the dwell_time_applie 
00050 *     may differ.
00051 *
00052 * Channel interrupt is generated before each single spark, on the recalc_angle.
00053 *
00054 *******************************************************************************/
00055 /*******************************************************************************
00056 * Includes
00057 *******************************************************************************/
00058 #include "etpu_spark.h"   /* private header file */
00059 #include "etpu_util.h"    /* utility routines for working with the eTPU */
00060 
00061 /*******************************************************************************
00062 * Global variables
00063 *******************************************************************************/
00064 extern uint32_t fs_etpu_data_ram_start;
00065 extern uint32_t fs_etpu_data_ram_ext;
00066 
00067 /*******************************************************************************
00068 * FUNCTION: fs_etpu_spark_init
00069 ****************************************************************************//*!
00070 * @brief   This function initializes eTPU channels to run SPARK function.
00071 *
00072 * @note    The following actions are performed in order:
00073 *          -# Use user-defined CPBA or allocate new eTPU DATA RAM
00074 *          -# Write chan config registers and FM bits
00075 *          -# Write channel parameters
00076 *          -# Write HSR
00077 *          -# Set channel priority
00078 *
00079 * @param   *p_spark_instance - This is a pointer to the instance structure
00080 *            @ref spark_instance_t.
00081 * @param   *p_spark_config - This is a pointer to the structure of configuration
00082 *            parameters @ref spark_config_t.
00083 *
00084 * @return  Error codes that can be returned are:
00085 *          - @ref FS_ETPU_ERROR_MALLOC - eTPU DATA RAM memory allocation error
00086 *          - @ref FS_ETPU_ERROR_NONE - No error
00087 *
00088 * @warning This function does not configure the pins, only the eTPU channels.
00089 *******************************************************************************/
00090 uint32_t fs_etpu_spark_init(
00091   struct spark_instance_t   *p_spark_instance,
00092   struct spark_config_t     *p_spark_config)
00093 {
00094   uint8_t  chan_num;
00095   uint8_t  priority;
00096   uint32_t *cpba;
00097   uint32_t *cpba_single_spark;
00098   uint8_t  spark_count;
00099   struct single_spark_config_t *p_single_spark_config;
00100   uint32_t cr;
00101   uint8_t  i;
00102 
00103   chan_num          = p_spark_instance->chan_num;
00104   priority          = p_spark_instance->priority;
00105   cpba              = p_spark_instance->cpba;
00106   cpba_single_spark = p_spark_instance->cpba_single_spark;
00107 
00108   /* Use user-defined CPBA or allocate new eTPU DATA RAM for chan. parameters */
00109   if(cpba == 0)
00110   {
00111     cpba = fs_etpu_malloc(FS_ETPU_SPARK_NUM_PARMS);
00112     if(cpba == 0)
00113     {
00114       return(FS_ETPU_ERROR_MALLOC);
00115     }
00116     else
00117     {
00118       p_spark_instance->cpba = cpba;
00119     }
00120   }
00121   /* Use user-defined CPBA or allocate new eTPU DATA RAM for single spark */
00122   spark_count = p_spark_config->spark_count;
00123   if(cpba_single_spark == 0)
00124   {
00125     cpba_single_spark = fs_etpu_malloc(FS_ETPU_SINGLE_SPARK_STRUCT_SIZE * spark_count);
00126     if(cpba_single_spark == 0)
00127     {
00128       return(FS_ETPU_ERROR_MALLOC);
00129     }
00130     else
00131     {
00132       p_spark_instance->cpba_single_spark = cpba_single_spark;
00133     }
00134   }
00135 
00136   /* Write chan config registers and FM bits */
00137   cr = (FS_ETPU_SPARK_TABLE_SELECT << 24) +
00138        (FS_ETPU_SPARK_FUNCTION_NUMBER << 16) +
00139        (((uint32_t)cpba - fs_etpu_data_ram_start) >> 3);
00140   eTPU->CHAN[chan_num].CR.R = cr;
00141   eTPU->CHAN[chan_num].SCR.R = (uint32_t)p_spark_instance->polarity;
00142 
00143   /* Write channel parameters */
00144   /* 24-bit */
00145   *(cpba + ((FS_ETPU_SPARK_OFFSET_TDC_ANGLE            - 1)>>2)) = p_spark_instance->tdc_angle;
00146   *(cpba + ((FS_ETPU_SPARK_OFFSET_TDC_ANGLE_ACTUAL     - 1)>>2)) = 0;
00147   *(cpba + ((FS_ETPU_SPARK_OFFSET_ANGLE_OFFSET_RECALC  - 1)>>2)) = p_spark_config->angle_offset_recalc;
00148   *(cpba + ((FS_ETPU_SPARK_OFFSET_DWELL_TIME_MIN       - 1)>>2)) = p_spark_config->dwell_time_min;
00149   *(cpba + ((FS_ETPU_SPARK_OFFSET_DWELL_TIME_MAX       - 1)>>2)) = p_spark_config->dwell_time_max;
00150   *(cpba + ((FS_ETPU_SPARK_OFFSET_MULTI_ON_TIME        - 1)>>2)) = p_spark_config->multi_on_time;
00151   *(cpba + ((FS_ETPU_SPARK_OFFSET_MULTI_OFF_TIME       - 1)>>2)) = p_spark_config->multi_off_time;
00152   *(cpba + ((FS_ETPU_SPARK_OFFSET_P_SINGLE_SPARK_FIRST - 1)>>2)) = (uint32_t)cpba_single_spark - fs_etpu_data_ram_start;
00153   *(cpba + ((FS_ETPU_SPARK_OFFSET_P_SINGLE_SPARK       - 1)>>2)) = 0;
00154   *(cpba + ((FS_ETPU_SPARK_OFFSET_PULSE_START_TIME     - 1)>>2)) = 0;
00155   *(cpba + ((FS_ETPU_SPARK_OFFSET_DWELL_TIME_APPLIED   - 1)>>2)) = 0;
00156   *(cpba + ((FS_ETPU_SPARK_OFFSET_DWELL_TIME           - 1)>>2)) = 0;
00157   *(cpba + ((FS_ETPU_SPARK_OFFSET_END_ANGLE            - 1)>>2)) = 0;
00158   /* 8-bit */
00159   *((uint8_t*)cpba + FS_ETPU_SPARK_OFFSET_SPARK_COUNT        ) = spark_count;
00160   *((uint8_t*)cpba + FS_ETPU_SPARK_OFFSET_SPARK_COUNTER      ) = 0;
00161   *((uint8_t*)cpba + FS_ETPU_SPARK_OFFSET_MULTI_PULSE_COUNT  ) = 0;
00162   *((uint8_t*)cpba + FS_ETPU_SPARK_OFFSET_MULTI_PULSE_COUNTER) = 0;
00163   *((uint8_t*)cpba + FS_ETPU_SPARK_OFFSET_STATE              ) = 0;
00164   *((uint8_t*)cpba + FS_ETPU_SPARK_OFFSET_ERROR              ) = 0;
00165   *((uint8_t*)cpba + FS_ETPU_SPARK_OFFSET_GENERATION_DISABLE ) = p_spark_config->generation_disable;
00166 
00167   /* Write array of single sparke array parameters */
00168   p_single_spark_config = p_spark_config->p_single_spark_config;
00169   for(i=0; i<spark_count; i++)
00170   {
00171     /* 24-bit */
00172     *(cpba_single_spark + ((FS_ETPU_SINGLE_SPARK_OFFSET_END_ANGLE  - 1)>>2)) = p_single_spark_config->end_angle;
00173     *(cpba_single_spark + ((FS_ETPU_SINGLE_SPARK_OFFSET_DWELL_TIME - 1)>>2)) = p_single_spark_config->dwell_time;
00174     /* 8-bit */
00175     *((uint8_t*)cpba_single_spark + FS_ETPU_SINGLE_SPARK_OFFSET_MULTI_PULSE_COUNT) = p_single_spark_config->multi_pulse_count;
00176 
00177     p_single_spark_config++;
00178     cpba_single_spark += FS_ETPU_SINGLE_SPARK_STRUCT_SIZE >> 2;
00179   }
00180 
00181   /* Write HSR and Set channel priority*/
00182   eTPU->CHAN[chan_num].HSRR.R = FS_ETPU_SPARK_HSR_INIT;
00183   fs_etpu_enable(chan_num, priority);
00184 
00185   return(FS_ETPU_ERROR_NONE);
00186 }
00187 
00188 /*******************************************************************************
00189 * FUNCTION: fs_etpu_spark_config
00190 ****************************************************************************//*!
00191 * @brief   This function changes the SPARK configuration.
00192 *
00193 * @note    The following actions are performed in order:
00194 *          -# Write configuration parameter values to eTPU DATA RAM
00195 *          -# Write HSR
00196 *
00197 * @warning The new single spark configurations (array of single spark structures)
00198 *          must fit into the eTPU DATA RAM already allocated. It means the
00199 *          spark_count can only be lower or the same as the value provided
00200 *          on initialization.
00201 *
00202 * @param   *p_spark_instance - This is a pointer to the instance structure
00203 *            @ref spark_instance_t.
00204 * @param   *p_spark_config - This is a pointer to the structure of configuration
00205 *            parameters @ref spark_config_t.
00206 *
00207 * @return  Error codes that can be returned are:
00208 *          - @ref FS_ETPU_ERROR_NONE - No error
00209 *          - @ref FS_ETPU_ERROR_TIMING - The mode was not set because there is
00210 *              a HSR pending on the eTPU channel.
00211 *              It can be caused by a call of an API function which writes
00212 *              the HSR to the same channel shortly before this function call.
00213 *              Try to repeat the function call several microseconds later.
00214 *
00215 *******************************************************************************/
00216 uint32_t fs_etpu_spark_config(
00217   struct spark_instance_t *p_spark_instance,
00218   struct spark_config_t   *p_spark_config)
00219 {
00220   uint32_t *cpba;
00221   uint32_t *cpba_single_spark;
00222   uint32_t *cpbae;
00223   uint8_t  spark_count;
00224   struct single_spark_config_t *p_single_spark_config;
00225   uint8_t  i;
00226 
00227   /* Check there is no pending HSR */
00228   if(eTPU->CHAN[p_spark_instance->chan_num].HSRR.R != 0)
00229   {
00230     return(FS_ETPU_ERROR_TIMING);
00231   }
00232   else
00233   {
00234     cpba              = p_spark_instance->cpba;
00235     cpba_single_spark = p_spark_instance->cpba_single_spark;
00236     spark_count       = p_spark_config->spark_count;
00237     cpbae = cpba + (0x4000 >> 2); /* sign-extended memory area */
00238 
00239     /* Write channel parameters */
00240     /* 24-bit */
00241     *(cpbae + ((FS_ETPU_SPARK_OFFSET_ANGLE_OFFSET_RECALC - 1)>>2)) = p_spark_config->angle_offset_recalc;
00242     *(cpbae + ((FS_ETPU_SPARK_OFFSET_DWELL_TIME_MIN      - 1)>>2)) = p_spark_config->dwell_time_min;
00243     *(cpbae + ((FS_ETPU_SPARK_OFFSET_DWELL_TIME_MAX      - 1)>>2)) = p_spark_config->dwell_time_max;
00244     *(cpbae + ((FS_ETPU_SPARK_OFFSET_MULTI_ON_TIME       - 1)>>2)) = p_spark_config->multi_on_time;
00245     *(cpbae + ((FS_ETPU_SPARK_OFFSET_MULTI_OFF_TIME      - 1)>>2)) = p_spark_config->multi_off_time;
00246     /* 8-bit */
00247     *((uint8_t*)cpba + FS_ETPU_SPARK_OFFSET_SPARK_COUNT       ) = spark_count;
00248     *((uint8_t*)cpba + FS_ETPU_SPARK_OFFSET_GENERATION_DISABLE) = p_spark_config->generation_disable;
00249 
00250     /* Write array of sparkection parameters */
00251     p_single_spark_config = p_spark_config->p_single_spark_config;
00252     for(i=0; i<spark_count; i++)
00253     {
00254       /* 24-bit */
00255       *(cpba_single_spark + ((FS_ETPU_SINGLE_SPARK_OFFSET_END_ANGLE  - 1)>>2)) = p_single_spark_config->end_angle;
00256       *(cpba_single_spark + ((FS_ETPU_SINGLE_SPARK_OFFSET_DWELL_TIME - 1)>>2)) = p_single_spark_config->dwell_time;
00257       /* 8-bit */
00258       *((uint8_t*)cpba_single_spark + FS_ETPU_SINGLE_SPARK_OFFSET_MULTI_PULSE_COUNT) = p_single_spark_config->multi_pulse_count;
00259 
00260       p_single_spark_config++;
00261       cpba_single_spark += FS_ETPU_SINGLE_SPARK_STRUCT_SIZE >> 2;
00262     }
00263 
00264     /* Write HSR and Set channel priority*/
00265     eTPU->CHAN[p_spark_instance->chan_num].HSRR.R = FS_ETPU_SPARK_HSR_UPDATE;
00266 
00267     return(FS_ETPU_ERROR_NONE);
00268   }
00269 }
00270 
00271 /*******************************************************************************
00272 * FUNCTION: fs_etpu_spark_get_states
00273 ****************************************************************************//*!
00274 * @brief   This function reads SPARK state variables, including error flags,
00275 *          and clears the eTPU error after reading.
00276 *
00277 * @note    The following actions are performed in order:
00278 *          -# Read state parameter values from eTPU DATA RAM
00279 *          -# Clear SPARK error
00280 *
00281 * @param   *p_spark_instance - This is a pointer to the instance structure
00282 *            @ref inj_instance_t.
00283 * @param   *p_spark_states - This is a pointer to the return structure of states
00284 *            @ref inj_states_t.
00285 *
00286 * @return  Error codes that can be returned are:
00287 *          - @ref FS_ETPU_ERROR_NONE - No error
00288 *
00289 *******************************************************************************/
00290 uint32_t fs_etpu_spark_get_states(
00291   struct spark_instance_t *p_spark_instance,
00292   struct spark_states_t   *p_spark_states)
00293 {
00294   uint32_t *cpba;
00295   uint32_t *cpbae;
00296 
00297   cpba  = p_spark_instance->cpba;
00298   cpbae = cpba + (0x4000 >> 2); /* sign-extended memory area */
00299 
00300   /* Read SPARK channel parameters */
00301   p_spark_states->dwell_time_applied = *(cpbae + ((FS_ETPU_SPARK_OFFSET_DWELL_TIME_APPLIED - 1)>>2));
00302   p_spark_states->error             |= *((uint8_t*)cpba + FS_ETPU_SPARK_OFFSET_ERROR);
00303   /* Clear SPARK error */
00304   *((uint8_t*)cpba + FS_ETPU_SPARK_OFFSET_ERROR) = 0;
00305 
00306   return(FS_ETPU_ERROR_NONE);
00307 }
00308 
00309 /*******************************************************************************
00310  *
00311  * Copyright:
00312  *  Freescale Semiconductor, INC. All Rights Reserved.
00313  *  You are hereby granted a copyright license to use, modify, and
00314  *  distribute the SOFTWARE so long as this entire notice is
00315  *  retained without alteration in any modified and/or redistributed
00316  *  versions, and that such modified versions are clearly identified
00317  *  as such. No licenses are granted by implication, estoppel or
00318  *  otherwise under any patents or trademarks of Freescale
00319  *  Semiconductor, Inc. This software is provided on an "AS IS"
00320  *  basis and without warranty.
00321  *
00322  *  To the maximum extent permitted by applicable law, Freescale
00323  *  Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
00324  *  INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
00325  *  PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
00326  *  REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
00327  *  AND ANY ACCOMPANYING WRITTEN MATERIALS.
00328  *
00329  *  To the maximum extent permitted by applicable law, IN NO EVENT
00330  *  SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
00331  *  (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
00332  *  BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
00333  *  PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
00334  *
00335  *  Freescale Semiconductor assumes no responsibility for the
00336  *  maintenance and support of this software
00337  ******************************************************************************/
00338 /*******************************************************************************
00339  *
00340  * REVISION HISTORY:
00341  *
00342  * FILE OWNER: Milan Brejl [r54529]
00343  *
00344  * Revision 1.0  2014/03/17  r54529
00345  * Minor comment and formating improvements.
00346  * Ready for eTPU Engine Control Library release 1.0.
00347  *
00348  * Revision 0.1  2013/09/17  r54529
00349  * Initial version of file.
00350  ******************************************************************************/