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00021 #ifndef _ETPU_UTIL_H_
00022 #define _ETPU_UTIL_H_
00023
00024
00025
00026
00027 #include "typedefs.h"
00028 #include "etpu_struct.h"
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038 #define FS_ETPU_ENGINE_CHANNEL(x,y) (((x)-1)*64 + y)
00039
00040
00041
00042
00043 #define FS_ETPU_CHANNEL_TO_LINK(x) ((x)+64)
00044
00045 #ifndef TRUE
00046 #define TRUE 1
00047 #endif
00048
00049 #ifndef FALSE
00050 #define FALSE 0
00051 #endif
00052
00053
00054
00055
00056
00057 extern uint32_t *fs_free_param;
00058
00059
00060 extern struct eTPU_struct *eTPU;
00061
00062
00063
00064
00065 typedef uint32_t ufract24_t;
00066 typedef int32_t fract24_t;
00067
00068 typedef uint32_t uint24_t;
00069 typedef int32_t int24_t;
00070
00071
00072 struct etpu_config_t{
00073 uint32_t mcr;
00074 uint32_t misc;
00075 uint32_t ecr_a;
00076 uint32_t tbcr_a;
00077 uint32_t stacr_a;
00078 uint32_t ecr_b;
00079 uint32_t tbcr_b;
00080 uint32_t stacr_b;
00081 uint32_t wdtr_a;
00082 uint32_t wdtr_b;
00083 };
00084
00085
00086
00087
00088
00089 uint32_t fs_etpu_init(
00090 struct etpu_config_t p_etpu_config,
00091 uint32_t *code,
00092 uint32_t code_size,
00093 uint32_t *globals,
00094 uint32_t globals_size);
00095
00096 uint32_t fs_etpu2_init(
00097 struct etpu_config_t p_etpu_config,
00098 uint32_t engine_mem_size);
00099
00100
00101 uint32_t *fs_etpu_chan_init(
00102 uint8_t channel,
00103 uint8_t function,
00104 uint8_t mode,
00105 uint8_t hsr,
00106 uint8_t num_param,
00107 uint32_t config,
00108 uint32_t *func_frame);
00109
00110 uint32_t *fs_etpu_malloc(
00111 uint16_t num_bytes);
00112 uint32_t *fs_etpu_malloc2(
00113 uint8_t channel,
00114 uint16_t num_bytes);
00115
00116
00117 void fs_timer_start(void);
00118 uint32_t fs_etpu_get_global_exceptions(void);
00119 void fs_etpu_clear_global_exceptions(void);
00120 uint32_t fs_etpu_get_global_error(void);
00121 void fs_etpu_set_interrupt_mask_a(
00122 uint32_t mask);
00123 void fs_etpu_set_interrupt_mask_b(
00124 uint32_t mask);
00125 void fs_etpu_set_dma_mask_a(
00126 uint32_t mask);
00127 void fs_etpu_set_dma_mask_b(
00128 uint32_t mask);
00129 void fs_etpu_set_output_disable_mask_a(
00130 uint32_t mask,
00131 uint32_t polarity);
00132 void fs_etpu_set_output_disable_mask_b(
00133 uint32_t mask,
00134 uint32_t polarity);
00135
00136
00137 uint8_t fs_etpu_get_hsr(
00138 uint8_t channel);
00139 void fs_etpu_set_hsr(
00140 uint8_t channel,
00141 uint8_t hsr);
00142
00143 void fs_etpu_enable(
00144 uint8_t channel,
00145 uint8_t priority);
00146 void fs_etpu_disable(
00147 uint8_t channel);
00148
00149 void fs_etpu_interrupt_enable(
00150 uint8_t channel);
00151 void fs_etpu_interrupt_disable(
00152 uint8_t channel);
00153
00154 uint8_t fs_etpu_get_chan_interrupt_flag(
00155 uint8_t channel);
00156 void fs_etpu_clear_chan_interrupt_flag(
00157 uint8_t channel);
00158
00159 uint8_t fs_etpu_get_chan_interrupt_overflow_flag(
00160 uint8_t channel);
00161 void fs_etpu_clear_chan_interrupt_overflow_flag(
00162 uint8_t channel);
00163
00164 void fs_etpu_dma_enable(
00165 uint8_t channel);
00166 void fs_etpu_dma_disable(
00167 uint8_t channel);
00168
00169 uint8_t fs_etpu_get_chan_dma_flag(
00170 uint8_t channel);
00171 void fs_etpu_clear_chan_dma_flag(
00172 uint8_t channel);
00173
00174 uint8_t fs_etpu_get_chan_dma_overflow_flag(
00175 uint8_t channel);
00176 void fs_etpu_clear_chan_dma_overflow_flag(
00177 uint8_t channel);
00178
00179
00180 uint32_t *fs_etpu_data_ram(
00181 uint8_t channel);
00182
00183 uint32_t fs_etpu_get_chan_local_32(
00184 uint8_t channel,
00185 uint32_t offset);
00186 uint24_t fs_etpu_get_chan_local_24(
00187 uint8_t channel,
00188 uint32_t offset);
00189 int24_t fs_etpu_get_chan_local_24s(
00190 uint8_t channel,
00191 uint32_t offset);
00192 uint16_t fs_etpu_get_chan_local_16(
00193 uint8_t channel,
00194 uint32_t offset);
00195 uint8_t fs_etpu_get_chan_local_8(
00196 uint8_t channel,
00197 uint32_t offset);
00198
00199 void fs_etpu_set_chan_local_32(
00200 uint8_t channel,
00201 uint32_t offset,
00202 uint32_t value);
00203 void fs_etpu_set_chan_local_24(
00204 uint8_t channel,
00205 uint32_t offset,
00206 uint24_t value);
00207 void fs_etpu_set_chan_local_16(
00208 uint8_t channel,
00209 uint32_t offset,
00210 uint16_t value);
00211 void fs_etpu_set_chan_local_8(
00212 uint8_t channel,
00213 uint32_t offset,
00214 uint8_t value);
00215
00216 uint32_t fs_etpu_get_global_32(
00217 uint32_t offset);
00218 int24_t fs_etpu_get_global_24s(
00219 uint32_t offset);
00220 uint24_t fs_etpu_get_global_24(
00221 uint32_t offset);
00222 uint16_t fs_etpu_get_global_16(
00223 uint32_t offset);
00224 uint8_t fs_etpu_get_global_8(
00225 uint32_t offset);
00226
00227 void fs_etpu_set_global_32(
00228 uint32_t offset,
00229 uint32_t value);
00230 void fs_etpu_set_global_24(
00231 uint32_t offset,
00232 uint24_t value);
00233 void fs_etpu_set_global_16(
00234 uint32_t offset,
00235 uint16_t value);
00236 void fs_etpu_set_global_8(
00237 uint32_t offset,
00238 uint8_t value);
00239
00240 uint32_t fs_etpu_coherent_read_24(
00241 uint8_t channel,
00242 uint32_t offset1,
00243 uint32_t offset2,
00244 int32_t *value1,
00245 int32_t *value2);
00246 uint32_t fs_etpu_coherent_read_32(
00247 uint8_t channel,
00248 uint32_t offset1,
00249 uint32_t offset2,
00250 uint32_t *value1,
00251 uint32_t *value2);
00252 uint32_t fs_etpu_coherent_write_24(
00253 uint8_t channel,
00254 uint32_t offset1,
00255 uint32_t offset2,
00256 int32_t value1,
00257 int32_t value2);
00258 uint32_t fs_etpu_coherent_write_32(
00259 uint8_t channel,
00260 uint32_t offset1,
00261 uint32_t offset2,
00262 uint32_t value1,
00263 uint32_t value2);
00264
00265
00266 uint24_t fs_etpu_get_idle_cnt_a(void);
00267 uint24_t fs_etpu_get_idle_cnt_b(void);
00268 void fs_etpu_clear_idle_cnt_a(void);
00269 void fs_etpu_clear_idle_cnt_b(void);
00270
00271
00272 uint32_t *fs_memcpy32(
00273 uint32_t *dest,
00274 uint32_t *source,
00275 uint32_t size);
00276 void fs_memset32(
00277 uint32_t *start,
00278 uint32_t value,
00279 int32_t size);
00280
00281
00282
00283
00284
00285
00286 #define FS_ETPU_PRIORITY_HIGH 0x3
00287 #define FS_ETPU_PRIORITY_MIDDLE 0x2
00288 #define FS_ETPU_PRIORITY_LOW 0x1
00289 #define FS_ETPU_PRIORITY_DISABLE 0x0
00290
00291 #define FS_ETPU_PIN_HIGH 1
00292 #define FS_ETPU_PIN_LOW 0
00293
00294
00295 #define FS_ETPU_TCR1 0
00296 #define FS_ETPU_TCR2 1
00297 #define FS_ETPU_TCR1_A 0
00298 #define FS_ETPU_TCR2_A 1
00299 #define FS_ETPU_TCR1_B 0
00300 #define FS_ETPU_TCR2_B 1
00301
00302
00303 #define FS_ETPU_MISC_ENABLE 0x00000200
00304 #define FS_ETPU_MISC_DISABLE 0x00000000
00305
00306 #define FS_ETPU_VIS_ON 0x00000040
00307 #define FS_ETPU_VIS_OFF 0x00000000
00308
00309 #define FS_ETPU_GLOBAL_TIMEBASE_ENABLE 0x00000001
00310 #define FS_ETPU_GLOBAL_TIMEBASE_DISABLE 0x00000000
00311
00312 #define FS_ETPU_SDM_READ_ERROR 0x40000000
00313 #define FS_ETPU_WATCHDOG_TIMEOUT_A 0x20000000
00314 #define FS_ETPU_WATCHDOG_TIMEOUT_B 0x10000000
00315 #define FS_ETPU_MICROCODE_GLOBAL_EX_A 0x08000000
00316 #define FS_ETPU_MICROCODE_GLOBAL_EX_B 0x04000000
00317 #define FS_ETPU_ILLEGAL_INSTRUCTION_A 0x02000000
00318 #define FS_ETPU_ILLEGAL_INSTRUCTION_B 0x01000000
00319 #define FS_ETPU_SHARED_SUBSYS_ACC_ERR 0x00800000
00320 #define FS_ETPU_SCM_MISC_FLAG 0x00000400
00321 #define FS_ETPU_SCM_READ_ERROR 0x00000100
00322
00323
00324 #define FS_ETPU_FILTER_CLOCK_DIV2 0x00000000
00325 #define FS_ETPU_FILTER_CLOCK_DIV4 0x00010000
00326 #define FS_ETPU_FILTER_CLOCK_DIV8 0x00020000
00327 #define FS_ETPU_FILTER_CLOCK_DIV16 0x00030000
00328 #define FS_ETPU_FILTER_CLOCK_DIV32 0x00040000
00329 #define FS_ETPU_FILTER_CLOCK_DIV64 0x00050000
00330 #define FS_ETPU_FILTER_CLOCK_DIV128 0x00060000
00331 #define FS_ETPU_FILTER_CLOCK_DIV256 0x00070000
00332
00333 #define FS_ETPU_FCSS_DIV2 0x00000000
00334 #define FS_ETPU_FCSS_DIV1 0x00080000
00335
00336 #define FS_ETPU_CHAN_FILTER_2SAMPLE 0x00000000
00337 #define FS_ETPU_CHAN_FILTER_3SAMPLE 0x00008000
00338 #define FS_ETPU_CHAN_FILTER_CONT 0x0000C000
00339 #define FS_ETPU_CHAN_FILTER_BYPASS 0x00004000
00340
00341 #define FS_ETPU_ENGINE_ENABLE 0x00000000
00342 #define FS_ETPU_ENGINE_DISABLE 0x40000000
00343
00344 #define FS_ETPU_PRIORITY_PASSING_ENABLE 0x00000000
00345 #define FS_ETPU_PRIORITY_PASSING_DISABLE 0x00000080
00346
00347
00348 #define FS_ETPU_TCRCLK_MODE_2SAMPLE 0x00000000
00349 #define FS_ETPU_TCRCLK_MODE_INTEGRATION 0x10000000
00350 #define FS_ETPU_TCRCLK_INPUT_DIV2CLOCK 0x00000000
00351 #define FS_ETPU_TCRCLK_INPUT_CHANCLOCK 0x08000000
00352
00353 #define FS_ETPU_TCR1CTL_TCRCLK 0x00000000
00354 #define FS_ETPU_TCR1CTL_DIV2 0x00008000
00355
00356 #define FS_ETPU_TCR1CS_DIV2 0x00000000
00357 #define FS_ETPU_TCR1CS_DIV1 0x00002000
00358
00359 #define FS_ETPU_ANGLE_MODE_ENABLE 0x02000000
00360 #define FS_ETPU_ANGLE_MODE_DISABLE 0x00000000
00361 #define FS_ETPU_ANGLE_MODE_ENABLE_CH1 0x04000000
00362 #define FS_ETPU_ANGLE_MODE_ENABLE_CH2 0x06000000
00363
00364 #define FS_ETPU_TCR2CTL_GATEDDIV8 0x00000000
00365 #define FS_ETPU_TCR2CTL_RISE 0x20000000
00366 #define FS_ETPU_TCR2CTL_FALL 0x40000000
00367 #define FS_ETPU_TCR2CTL_RISEFALL 0x60000000
00368 #define FS_ETPU_TCR2CTL_DIV8 0x80000000
00369
00370 #define FS_ETPU_TCR1_PRESCALER(x) (((x)-1) & 0xFF)
00371 #define FS_ETPU_TCR2_PRESCALER(x) ((((x)-1) & 0x3F)<<16)
00372
00373
00374 #define FS_ETPU_TCR1_STAC_ENABLE 0x80000000
00375 #define FS_ETPU_TCR1_STAC_DISABLE 0x00000000
00376
00377 #define FS_ETPU_TCR1_STAC_CLIENT 0x00000000
00378 #define FS_ETPU_TCR1_STAC_SERVER 0x40000000
00379
00380 #define FS_ETPU_TCR1_STAC_SRVSLOT(x) (((x) & 0xF)<<16)
00381
00382 #define FS_ETPU_TCR2_STAC_ENABLE 0x00008000
00383 #define FS_ETPU_TCR2_STAC_DISABLE 0x00000000
00384
00385 #define FS_ETPU_TCR2_STAC_CLIENT 0x00000000
00386 #define FS_ETPU_TCR2_STAC_SERVER 0x00004000
00387
00388 #define FS_ETPU_TCR2_STAC_SRVSLOT(x) ((x) & 0xF)
00389
00390
00391 #define FS_ETPU_WDM_DISABLED 0x00000000
00392 #define FS_ETPU_WDM_THREAD_LEN 0x80000000
00393 #define FS_ETPU_WDM_BUSY_LEN 0xC0000000
00394
00395 #define FS_ETPU_WDTR_WDCNT(x) ((x) & 0xFFFF)
00396
00397
00398 #define FS_ETPU_INTERRUPT_ENABLE 0x80000000
00399 #define FS_ETPU_INTERRUPT_DISABLE 0x00000000
00400
00401 #define FS_ETPU_DMA_ENABLE 0x40000000
00402 #define FS_ETPU_DMA_DISABLE 0x00000000
00403
00404 #define FS_ETPU_ENTRY_TABLE_STANDARD 0x00000000
00405 #define FS_ETPU_ENTRY_TABLE_ALTERNATE 0x01000000
00406
00407 #define FS_ETPU_ENTRY_TABLE_PIN_INPUT 0x00000000
00408 #define FS_ETPU_ENTRY_TABLE_PIN_OUTPUT 0x02000000
00409
00410 #define FS_ETPU_OUTPUT_DISABLE_OFF 0x00000000
00411 #define FS_ETPU_OUTPUT_DISABLE_LOW 0x0000C000
00412 #define FS_ETPU_OUTPUT_DISABLE_HIGH 0x00008000
00413
00414
00415 #define FS_ETPU_ERROR_NONE 0
00416 #define FS_ETPU_ERROR_MALLOC 1
00417 #define FS_ETPU_ERROR_FREQ 2
00418 #define FS_ETPU_ERROR_VALUE 3
00419 #define FS_ETPU_ERROR_CODESIZE 4
00420 #define FS_ETPU_ERROR_VIS_BIT_NOT_SET 5
00421 #define FS_ETPU_ERROR_ADDRESS 6
00422 #define FS_ETPU_ERROR_TIMING 7
00423
00424 #endif
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