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00001 /**************************************************************************/ 00002 /* FILE NAME: etpu_struct.h COPYRIGHT (c) Freescale 2010 */ 00003 /* VERSION: 1.3 All Rights Reserved */ 00004 /* */ 00005 /* DESCRIPTION: */ 00006 /* This file contain all of the register and bit field definitions for */ 00007 /* the eTPU module. */ 00008 /*========================================================================*/ 00009 /* UPDATE HISTORY */ 00010 /* REV AUTHOR DATE DESCRIPTION OF CHANGE */ 00011 /* --- ----------- --------- --------------------- */ 00012 /* 1.0 J. Loeliger 26/Nov/04 Initial version of file. */ 00013 /* 1.1 R. Moran 18/Jan/10 Updated with eTPU2 registers */ 00014 /* 1.2 G. Emerson 19/Jan/10 name structure as ETPU_struct */ 00015 /* 1.2 G. Emerson 20/Jan/10 fix typo */ 00016 /* 1.3 M. Brejl 10/Aug/11 Correction in IDLE register */ 00017 /**************************************************************************/ 00018 /*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ 00019 00020 #ifndef _ETPU_STRUCT_H_ 00021 #define _ETPU_STRUCT_H_ 00022 00023 #include "typedefs.h" 00024 00025 #ifdef __cplusplus 00026 extern "C" { 00027 #endif 00028 00029 #ifdef __MWERKS__ 00030 #pragma push 00031 #pragma ANSI_strict off 00032 #endif 00033 00034 /****************************************************************************/ 00035 /* MODULE :ETPU */ 00036 /****************************************************************************/ 00037 00038 /***************************Configuration Registers**************************/ 00039 00040 struct eTPU_struct { 00041 union { /* MODULE CONFIGURATION REGISTER */ 00042 vuint32_t R; 00043 struct { 00044 vuint32_t GEC:1; /* Global Exception Clear */ 00045 vuint32_t SDMERR:1; /* SDM Read Error */ 00046 vuint32_t WDTOA:1; /* Watchdog Timeout-eTPU_A */ 00047 vuint32_t WDTOB:1; /* Watchdog Timeout-eTPU_B */ 00048 vuint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */ 00049 vuint32_t MGE2:1; /* Microcode Global Exception-ETPU_B */ 00050 vuint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */ 00051 vuint32_t ILF2:1; /* Illegal Instruction Flag-ETPU_B */ 00052 vuint32_t:3; 00053 vuint32_t SCMSIZE:5; /* Shared Code Memory size */ 00054 vuint32_t:4; 00055 vuint32_t SCMMISC:1; /* SCM MISC Complete/Clear */ 00056 vuint32_t SCMMISF:1; /* SCM MISC Flag */ 00057 vuint32_t SCMMISEN:1; /* SCM MISC Enable */ 00058 vuint32_t SCMERR:1; /* SCM Read Error */ 00059 vuint32_t:1; 00060 vuint32_t VIS:1; /* SCM Visability */ 00061 vuint32_t:5; 00062 vuint32_t GTBE:1; /* Global Time Base Enable */ 00063 } B; 00064 } MCR; 00065 00066 union { /* COHERENT DUAL-PARAMETER CONTROL */ 00067 vuint32_t R; 00068 struct { 00069 vuint32_t STS:1; /* Start Status bit */ 00070 vuint32_t CTBASE:5; /* Channel Transfer Base */ 00071 vuint32_t PBASE:10; /* Parameter Buffer Base Address */ 00072 vuint32_t PWIDTH:1; /* Parameter Width */ 00073 vuint32_t PARAM0:7; /* Channel Parameter 0 */ 00074 vuint32_t WR:1; /* Read/Write selection */ 00075 vuint32_t PARAM1:7; /* Channel Parameter 1 */ 00076 } B; 00077 } CDCR; 00078 00079 uint32_t eTPU_reserved0008; /* 0x0008-0x000B */ 00080 00081 union { /* MISC Compare Register */ 00082 uint32_t R; 00083 struct { 00084 vuint32_t ETPUMISCCMP:32; 00085 } B; 00086 } MISCCMPR; 00087 00088 union { /* SCM off-range Date Register */ 00089 uint32_t R; 00090 struct { 00091 vuint32_t ETPUSCMOFFDATA:32; 00092 } B; 00093 } SCMOFFDATAR; 00094 00095 union { /* ETPU_A Configuration Register */ 00096 vuint32_t R; 00097 struct { 00098 vuint32_t FEND:1; /* Force END */ 00099 vuint32_t MDIS:1; /* Low power Stop */ 00100 vuint32_t:1; 00101 vuint32_t STF:1; /* Stop Flag */ 00102 vuint32_t:4; 00103 vuint32_t HLTF:1; /* Halt Mode Flag */ 00104 vuint32_t:3; 00105 vuint32_t FCSS:1; /* Filter Clock Source Select */ 00106 vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */ 00107 vuint32_t CDFC:2; 00108 vuint32_t:1; 00109 vuint32_t ERBA:5; /* Engine Relative Base Address */ 00110 vuint32_t SPPDIS:1; /* Schedule Priority Passing Disable */ 00111 vuint32_t:2; 00112 vuint32_t ETB:5; /* Entry Table Base */ 00113 } B; 00114 } ECR_A; 00115 00116 union { /* ETPU_B Configuration Register */ 00117 vuint32_t R; 00118 struct { 00119 vuint32_t FEND:1; /* Force END */ 00120 vuint32_t MDIS:1; /* Low power Stop */ 00121 vuint32_t:1; 00122 vuint32_t STF:1; /* Stop Flag */ 00123 vuint32_t:4; 00124 vuint32_t HLTF:1; /* Halt Mode Flag */ 00125 vuint32_t:3; 00126 vuint32_t FCSS:1; /* Filter Clock Source Select */ 00127 vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */ 00128 vuint32_t CDFC:2; 00129 vuint32_t:1; 00130 vuint32_t ERBA:5; /* Engine Relative Base Address */ 00131 vuint32_t SPPDIS:1; /* Schedule Priority Passing Disable */ 00132 vuint32_t:2; 00133 vuint32_t ETB:5; /* Entry Table Base */ 00134 } B; 00135 } ECR_B; 00136 00137 uint32_t eTPU_reserved001C; /* 0x001C-0x001F */ 00138 00139 union { /* ETPU_A Timebase Configuration Register */ 00140 uint32_t R; 00141 struct { 00142 vuint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ 00143 vuint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ 00144 vuint32_t AM:2; /* Angle Mode */ 00145 vuint32_t:3; 00146 vuint32_t TCR2P:6; /* TCR2 Prescaler Control */ 00147 vuint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ 00148 vuint32_t TCR1CS:1; /* TCR1 Clock Source */ 00149 vuint32_t:5; 00150 vuint32_t TCR1P:8; /* TCR1 Prescaler Control */ 00151 } B; 00152 } TBCR_A; 00153 00154 union { /* ETPU_A TCR1 Visibility Register */ 00155 vuint32_t R; 00156 struct { 00157 vuint32_t:8; 00158 vuint32_t TCR1:24; 00159 } B; 00160 } TB1R_A; 00161 00162 union { /* ETPU_A TCR2 Visibility Register */ 00163 vuint32_t R; 00164 struct { 00165 vuint32_t:8; 00166 vuint32_t TCR2:24; 00167 } B; 00168 } TB2R_A; 00169 00170 union { /* ETPU_A STAC Configuration Register */ 00171 vuint32_t R; 00172 struct { 00173 vuint32_t REN1:1; /* Resource Enable TCR1 */ 00174 vuint32_t RSC1:1; /* Resource Control TCR1 */ 00175 vuint32_t:2; 00176 vuint32_t SERVER_ID1:4; /* TCR1 Server ID */ 00177 vuint32_t:4; 00178 vuint32_t SRV1:4; /* Resource Server Slot */ 00179 vuint32_t REN2:1; /* Resource Enable TCR2 */ 00180 vuint32_t RSC2:1; /* Resource Control TCR2 */ 00181 vuint32_t:2; 00182 vuint32_t SERVER_ID2:4; /* TCR2 Server ID */ 00183 vuint32_t:4; 00184 vuint32_t SRV2:4; /* Resource Server Slot */ 00185 } B; 00186 } REDCR_A; 00187 00188 uint32_t eTPU_reserved0030[4]; /* 0x0030-0x003F */ 00189 00190 union { /* ETPU_B Timebase Configuration Register */ 00191 uint32_t R; 00192 struct { 00193 vuint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ 00194 vuint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ 00195 vuint32_t AM:2; /* Angle Mode */ 00196 vuint32_t:3; 00197 vuint32_t TCR2P:6; /* TCR2 Prescaler Control */ 00198 vuint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ 00199 vuint32_t TCR1CS:1; /* TCR1 Clock Source */ 00200 vuint32_t:5; 00201 vuint32_t TCR1P:8; /* TCR1 Prescaler Control */ 00202 } B; 00203 } TBCR_B; 00204 00205 union { /* ETPU_B TCR1 Visibility Register */ 00206 vuint32_t R; 00207 struct { 00208 vuint32_t:8; 00209 vuint32_t TCR1:24; 00210 } B; 00211 } TB1R_B; 00212 00213 union { /* ETPU_B TCR2 Visibility Register */ 00214 vuint32_t R; 00215 struct { 00216 vuint32_t:8; 00217 vuint32_t TCR2:24; 00218 } B; 00219 } TB2R_B; 00220 00221 union { /* ETPU_B STAC Configuration Register */ 00222 vuint32_t R; 00223 struct { 00224 vuint32_t REN1:1; /* Resource Enable TCR1 */ 00225 vuint32_t RSC1:1; /* Resource Control TCR1 */ 00226 vuint32_t:2; 00227 vuint32_t SERVER_ID1:4; /* TCR1 Server ID */ 00228 vuint32_t:4; 00229 vuint32_t SRV1:4; /* Resource Server Slot */ 00230 vuint32_t REN2:1; /* Resource Enable TCR2 */ 00231 vuint32_t RSC2:1; /* Resource Control TCR2 */ 00232 vuint32_t:2; 00233 vuint32_t SERVER_ID2:4; /* TCR2 Server ID */ 00234 vuint32_t:4; 00235 vuint32_t SRV2:4; /* Resource Server Slot */ 00236 } B; 00237 } REDCR_B; 00238 00239 uint32_t eTPU_reserved0050[4]; /* 0x0050-0x005F */ 00240 00241 union { /* Watchdog Timer Register A */ 00242 vuint32_t R; 00243 struct { 00244 vuint32_t WDM:2; /* Watchdog Mode */ 00245 vuint32_t:14; 00246 vuint32_t WDCNT:16; /* Watchdog Count */ 00247 } B; 00248 } WDTR_A; 00249 00250 uint32_t eTPU_reserved0064; /* 0x0064-0x0067 */ 00251 00252 union { /* Idle Counter Register A*/ 00253 vuint32_t R; 00254 struct { 00255 vuint32_t:31; 00256 vuint32_t ICLR:1; /* Idle Clear */ 00257 } B; 00258 00259 } IDLE_A; 00260 00261 uint32_t eTPU_reserved006C; /* 0x006C-0x006F */ 00262 00263 union { /* Watchdog Timer Register B */ 00264 vuint32_t R; 00265 struct { 00266 vuint32_t WDM:2; /* Watchdog Mode */ 00267 vuint32_t:14; 00268 vuint32_t WDCNT:16; /* Watchdog Count */ 00269 } B; 00270 } WDTR_B; 00271 00272 uint32_t eTPU_reserved0074; /* 0x0074-0x0077 */ 00273 00274 union { /* Idle Counter Register B*/ 00275 vuint32_t R; 00276 struct { 00277 vuint32_t:31; 00278 vuint32_t ICLR:1; /* Idle Clear */ 00279 } B; 00280 } IDLE_B; 00281 00282 uint32_t eTPU_reserved007C; /* 0x007C-0x007F */ 00283 00284 uint32_t eTPU_reserved0080[96]; /* 0x0080-0x01FF */ 00285 00286 /*****************************Status and Control Registers**************************/ 00287 00288 union { /* ETPU_A Channel Interrut Status */ 00289 vuint32_t R; 00290 struct { 00291 vuint32_t CIS31:1; /* Channel 31 Interrut Status */ 00292 vuint32_t CIS30:1; /* Channel 30 Interrut Status */ 00293 vuint32_t CIS29:1; /* Channel 29 Interrut Status */ 00294 vuint32_t CIS28:1; /* Channel 28 Interrut Status */ 00295 vuint32_t CIS27:1; /* Channel 27 Interrut Status */ 00296 vuint32_t CIS26:1; /* Channel 26 Interrut Status */ 00297 vuint32_t CIS25:1; /* Channel 25 Interrut Status */ 00298 vuint32_t CIS24:1; /* Channel 24 Interrut Status */ 00299 vuint32_t CIS23:1; /* Channel 23 Interrut Status */ 00300 vuint32_t CIS22:1; /* Channel 22 Interrut Status */ 00301 vuint32_t CIS21:1; /* Channel 21 Interrut Status */ 00302 vuint32_t CIS20:1; /* Channel 20 Interrut Status */ 00303 vuint32_t CIS19:1; /* Channel 19 Interrut Status */ 00304 vuint32_t CIS18:1; /* Channel 18 Interrut Status */ 00305 vuint32_t CIS17:1; /* Channel 17 Interrut Status */ 00306 vuint32_t CIS16:1; /* Channel 16 Interrut Status */ 00307 vuint32_t CIS15:1; /* Channel 15 Interrut Status */ 00308 vuint32_t CIS14:1; /* Channel 14 Interrut Status */ 00309 vuint32_t CIS13:1; /* Channel 13 Interrut Status */ 00310 vuint32_t CIS12:1; /* Channel 12 Interrut Status */ 00311 vuint32_t CIS11:1; /* Channel 11 Interrut Status */ 00312 vuint32_t CIS10:1; /* Channel 10 Interrut Status */ 00313 vuint32_t CIS9:1; /* Channel 9 Interrut Status */ 00314 vuint32_t CIS8:1; /* Channel 8 Interrut Status */ 00315 vuint32_t CIS7:1; /* Channel 7 Interrut Status */ 00316 vuint32_t CIS6:1; /* Channel 6 Interrut Status */ 00317 vuint32_t CIS5:1; /* Channel 5 Interrut Status */ 00318 vuint32_t CIS4:1; /* Channel 4 Interrut Status */ 00319 vuint32_t CIS3:1; /* Channel 3 Interrut Status */ 00320 vuint32_t CIS2:1; /* Channel 2 Interrut Status */ 00321 vuint32_t CIS1:1; /* Channel 1 Interrut Status */ 00322 vuint32_t CIS0:1; /* Channel 0 Interrut Status */ 00323 } B; 00324 } CISR_A; 00325 00326 union { /* ETPU_B Channel Interruput Status */ 00327 vuint32_t R; 00328 struct { 00329 vuint32_t CIS31:1; /* Channel 31 Interrut Status */ 00330 vuint32_t CIS30:1; /* Channel 30 Interrut Status */ 00331 vuint32_t CIS29:1; /* Channel 29 Interrut Status */ 00332 vuint32_t CIS28:1; /* Channel 28 Interrut Status */ 00333 vuint32_t CIS27:1; /* Channel 27 Interrut Status */ 00334 vuint32_t CIS26:1; /* Channel 26 Interrut Status */ 00335 vuint32_t CIS25:1; /* Channel 25 Interrut Status */ 00336 vuint32_t CIS24:1; /* Channel 24 Interrut Status */ 00337 vuint32_t CIS23:1; /* Channel 23 Interrut Status */ 00338 vuint32_t CIS22:1; /* Channel 22 Interrut Status */ 00339 vuint32_t CIS21:1; /* Channel 21 Interrut Status */ 00340 vuint32_t CIS20:1; /* Channel 20 Interrut Status */ 00341 vuint32_t CIS19:1; /* Channel 19 Interrut Status */ 00342 vuint32_t CIS18:1; /* Channel 18 Interrut Status */ 00343 vuint32_t CIS17:1; /* Channel 17 Interrut Status */ 00344 vuint32_t CIS16:1; /* Channel 16 Interrut Status */ 00345 vuint32_t CIS15:1; /* Channel 15 Interrut Status */ 00346 vuint32_t CIS14:1; /* Channel 14 Interrut Status */ 00347 vuint32_t CIS13:1; /* Channel 13 Interrut Status */ 00348 vuint32_t CIS12:1; /* Channel 12 Interrut Status */ 00349 vuint32_t CIS11:1; /* Channel 11 Interrut Status */ 00350 vuint32_t CIS10:1; /* Channel 10 Interrut Status */ 00351 vuint32_t CIS9:1; /* Channel 9 Interrut Status */ 00352 vuint32_t CIS8:1; /* Channel 8 Interrut Status */ 00353 vuint32_t CIS7:1; /* Channel 7 Interrut Status */ 00354 vuint32_t CIS6:1; /* Channel 6 Interrut Status */ 00355 vuint32_t CIS5:1; /* Channel 5 Interrut Status */ 00356 vuint32_t CIS4:1; /* Channel 4 Interrut Status */ 00357 vuint32_t CIS3:1; /* Channel 3 Interrut Status */ 00358 vuint32_t CIS2:1; /* Channel 2 Interrut Status */ 00359 vuint32_t CIS1:1; /* Channel 1 Interrupt Status */ 00360 vuint32_t CIS0:1; /* Channel 0 Interrupt Status */ 00361 } B; 00362 } CISR_B; 00363 00364 uint32_t eTPU_reserved0208[2]; /* 0x0208-0x020F */ 00365 00366 union { /* ETPU_A Data Transfer Request Status */ 00367 vuint32_t R; 00368 struct { 00369 vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ 00370 vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ 00371 vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ 00372 vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ 00373 vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ 00374 vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ 00375 vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ 00376 vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ 00377 vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ 00378 vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ 00379 vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ 00380 vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ 00381 vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ 00382 vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ 00383 vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ 00384 vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ 00385 vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ 00386 vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ 00387 vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ 00388 vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ 00389 vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ 00390 vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ 00391 vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ 00392 vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ 00393 vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ 00394 vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ 00395 vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ 00396 vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ 00397 vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ 00398 vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ 00399 vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ 00400 vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ 00401 } B; 00402 } CDTRSR_A; 00403 00404 union { /* ETPU_B Data Transfer Request Status */ 00405 vuint32_t R; 00406 struct { 00407 vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ 00408 vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ 00409 vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ 00410 vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ 00411 vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ 00412 vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ 00413 vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ 00414 vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ 00415 vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ 00416 vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ 00417 vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ 00418 vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ 00419 vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ 00420 vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ 00421 vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ 00422 vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ 00423 vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ 00424 vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ 00425 vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ 00426 vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ 00427 vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ 00428 vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ 00429 vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ 00430 vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ 00431 vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ 00432 vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ 00433 vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ 00434 vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ 00435 vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ 00436 vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ 00437 vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ 00438 vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ 00439 } B; 00440 } CDTRSR_B; 00441 00442 uint32_t eTPU_reserved0218[2]; /* 0x0218-0x021F */ 00443 00444 union { /* ETPU_A Interruput Overflow Status */ 00445 vuint32_t R; 00446 struct { 00447 vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ 00448 vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ 00449 vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ 00450 vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ 00451 vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ 00452 vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ 00453 vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ 00454 vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ 00455 vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ 00456 vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ 00457 vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ 00458 vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ 00459 vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ 00460 vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ 00461 vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ 00462 vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ 00463 vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ 00464 vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ 00465 vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ 00466 vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ 00467 vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ 00468 vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ 00469 vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ 00470 vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ 00471 vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ 00472 vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ 00473 vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ 00474 vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ 00475 vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ 00476 vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ 00477 vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ 00478 vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ 00479 } B; 00480 } CIOSR_A; 00481 00482 union { /* ETPU_B Interruput Overflow Status */ 00483 vuint32_t R; 00484 struct { 00485 vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ 00486 vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ 00487 vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ 00488 vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ 00489 vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ 00490 vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ 00491 vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ 00492 vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ 00493 vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ 00494 vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ 00495 vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ 00496 vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ 00497 vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ 00498 vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ 00499 vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ 00500 vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ 00501 vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ 00502 vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ 00503 vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ 00504 vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ 00505 vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ 00506 vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ 00507 vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ 00508 vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ 00509 vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ 00510 vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ 00511 vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ 00512 vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ 00513 vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ 00514 vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ 00515 vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ 00516 vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ 00517 } B; 00518 } CIOSR_B; 00519 00520 uint32_t eTPU_reserved0228[2]; /* 0x0228-0x022F */ 00521 00522 union { /* ETPU_A Data Transfer Overflow Status */ 00523 vuint32_t R; 00524 struct { 00525 vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ 00526 vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ 00527 vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ 00528 vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ 00529 vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ 00530 vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ 00531 vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ 00532 vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ 00533 vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ 00534 vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ 00535 vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ 00536 vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ 00537 vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ 00538 vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ 00539 vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ 00540 vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ 00541 vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ 00542 vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ 00543 vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ 00544 vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ 00545 vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ 00546 vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ 00547 vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ 00548 vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ 00549 vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ 00550 vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ 00551 vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ 00552 vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ 00553 vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ 00554 vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ 00555 vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ 00556 vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ 00557 } B; 00558 } CDTROSR_A; 00559 00560 union { /* ETPU_B Data Transfer Overflow Status */ 00561 vuint32_t R; 00562 struct { 00563 vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ 00564 vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ 00565 vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ 00566 vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ 00567 vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ 00568 vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ 00569 vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ 00570 vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ 00571 vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ 00572 vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ 00573 vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ 00574 vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ 00575 vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ 00576 vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ 00577 vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ 00578 vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ 00579 vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ 00580 vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ 00581 vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ 00582 vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ 00583 vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ 00584 vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ 00585 vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ 00586 vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ 00587 vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ 00588 vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ 00589 vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ 00590 vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ 00591 vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ 00592 vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ 00593 vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ 00594 vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ 00595 } B; 00596 } CDTROSR_B; 00597 00598 uint32_t eTPU_reserved0238[2]; /* 0x0238-0x023F */ 00599 00600 union { /* ETPU_A Channel Interruput Enable */ 00601 vuint32_t R; 00602 struct { 00603 vuint32_t CIE31:1; /* Channel 31 Interruput Enable */ 00604 vuint32_t CIE30:1; /* Channel 30 Interruput Enable */ 00605 vuint32_t CIE29:1; /* Channel 29 Interruput Enable */ 00606 vuint32_t CIE28:1; /* Channel 28 Interruput Enable */ 00607 vuint32_t CIE27:1; /* Channel 27 Interruput Enable */ 00608 vuint32_t CIE26:1; /* Channel 26 Interruput Enable */ 00609 vuint32_t CIE25:1; /* Channel 25 Interruput Enable */ 00610 vuint32_t CIE24:1; /* Channel 24 Interruput Enable */ 00611 vuint32_t CIE23:1; /* Channel 23 Interruput Enable */ 00612 vuint32_t CIE22:1; /* Channel 22 Interruput Enable */ 00613 vuint32_t CIE21:1; /* Channel 21 Interruput Enable */ 00614 vuint32_t CIE20:1; /* Channel 20 Interruput Enable */ 00615 vuint32_t CIE19:1; /* Channel 19 Interruput Enable */ 00616 vuint32_t CIE18:1; /* Channel 18 Interruput Enable */ 00617 vuint32_t CIE17:1; /* Channel 17 Interruput Enable */ 00618 vuint32_t CIE16:1; /* Channel 16 Interruput Enable */ 00619 vuint32_t CIE15:1; /* Channel 15 Interruput Enable */ 00620 vuint32_t CIE14:1; /* Channel 14 Interruput Enable */ 00621 vuint32_t CIE13:1; /* Channel 13 Interruput Enable */ 00622 vuint32_t CIE12:1; /* Channel 12 Interruput Enable */ 00623 vuint32_t CIE11:1; /* Channel 11 Interruput Enable */ 00624 vuint32_t CIE10:1; /* Channel 10 Interruput Enable */ 00625 vuint32_t CIE9:1; /* Channel 9 Interruput Enable */ 00626 vuint32_t CIE8:1; /* Channel 8 Interruput Enable */ 00627 vuint32_t CIE7:1; /* Channel 7 Interruput Enable */ 00628 vuint32_t CIE6:1; /* Channel 6 Interruput Enable */ 00629 vuint32_t CIE5:1; /* Channel 5 Interruput Enable */ 00630 vuint32_t CIE4:1; /* Channel 4 Interruput Enable */ 00631 vuint32_t CIE3:1; /* Channel 3 Interruput Enable */ 00632 vuint32_t CIE2:1; /* Channel 2 Interruput Enable */ 00633 vuint32_t CIE1:1; /* Channel 1 Interruput Enable */ 00634 vuint32_t CIE0:1; /* Channel 0 Interruput Enable */ 00635 } B; 00636 } CIER_A; 00637 00638 union { /* ETPU_B Channel Interruput Enable */ 00639 vuint32_t R; 00640 struct { 00641 vuint32_t CIE31:1; /* Channel 31 Interruput Enable */ 00642 vuint32_t CIE30:1; /* Channel 30 Interruput Enable */ 00643 vuint32_t CIE29:1; /* Channel 29 Interruput Enable */ 00644 vuint32_t CIE28:1; /* Channel 28 Interruput Enable */ 00645 vuint32_t CIE27:1; /* Channel 27 Interruput Enable */ 00646 vuint32_t CIE26:1; /* Channel 26 Interruput Enable */ 00647 vuint32_t CIE25:1; /* Channel 25 Interruput Enable */ 00648 vuint32_t CIE24:1; /* Channel 24 Interruput Enable */ 00649 vuint32_t CIE23:1; /* Channel 23 Interruput Enable */ 00650 vuint32_t CIE22:1; /* Channel 22 Interruput Enable */ 00651 vuint32_t CIE21:1; /* Channel 21 Interruput Enable */ 00652 vuint32_t CIE20:1; /* Channel 20 Interruput Enable */ 00653 vuint32_t CIE19:1; /* Channel 19 Interruput Enable */ 00654 vuint32_t CIE18:1; /* Channel 18 Interruput Enable */ 00655 vuint32_t CIE17:1; /* Channel 17 Interruput Enable */ 00656 vuint32_t CIE16:1; /* Channel 16 Interruput Enable */ 00657 vuint32_t CIE15:1; /* Channel 15 Interruput Enable */ 00658 vuint32_t CIE14:1; /* Channel 14 Interruput Enable */ 00659 vuint32_t CIE13:1; /* Channel 13 Interruput Enable */ 00660 vuint32_t CIE12:1; /* Channel 12 Interruput Enable */ 00661 vuint32_t CIE11:1; /* Channel 11 Interruput Enable */ 00662 vuint32_t CIE10:1; /* Channel 10 Interruput Enable */ 00663 vuint32_t CIE9:1; /* Channel 9 Interruput Enable */ 00664 vuint32_t CIE8:1; /* Channel 8 Interruput Enable */ 00665 vuint32_t CIE7:1; /* Channel 7 Interruput Enable */ 00666 vuint32_t CIE6:1; /* Channel 6 Interruput Enable */ 00667 vuint32_t CIE5:1; /* Channel 5 Interruput Enable */ 00668 vuint32_t CIE4:1; /* Channel 4 Interruput Enable */ 00669 vuint32_t CIE3:1; /* Channel 3 Interruput Enable */ 00670 vuint32_t CIE2:1; /* Channel 2 Interruput Enable */ 00671 vuint32_t CIE1:1; /* Channel 1 Interruput Enable */ 00672 vuint32_t CIE0:1; /* Channel 0 Interruput Enable */ 00673 } B; 00674 } CIER_B; 00675 00676 uint32_t eTPU_reserved0248[2]; /* 0x0248-0x024F */ 00677 00678 union { /* ETPU_A Channel Data Transfer Request Enable */ 00679 vuint32_t R; 00680 struct { 00681 vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ 00682 vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ 00683 vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ 00684 vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ 00685 vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ 00686 vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ 00687 vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ 00688 vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ 00689 vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ 00690 vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ 00691 vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ 00692 vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ 00693 vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ 00694 vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ 00695 vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ 00696 vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ 00697 vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ 00698 vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ 00699 vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ 00700 vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ 00701 vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ 00702 vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ 00703 vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ 00704 vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ 00705 vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ 00706 vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ 00707 vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ 00708 vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ 00709 vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ 00710 vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ 00711 vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ 00712 vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ 00713 } B; 00714 } CDTRER_A; 00715 00716 union { /* ETPU_B Channel Data Transfer Request Enable */ 00717 vuint32_t R; 00718 struct { 00719 vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ 00720 vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ 00721 vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ 00722 vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ 00723 vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ 00724 vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ 00725 vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ 00726 vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ 00727 vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ 00728 vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ 00729 vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ 00730 vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ 00731 vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ 00732 vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ 00733 vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ 00734 vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ 00735 vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ 00736 vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ 00737 vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ 00738 vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ 00739 vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ 00740 vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ 00741 vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ 00742 vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ 00743 vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ 00744 vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ 00745 vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ 00746 vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ 00747 vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ 00748 vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ 00749 vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ 00750 vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ 00751 } B; 00752 } CDTRER_B; 00753 00754 uint32_t eTPU_reserved0258[2]; /* 0x0258-0x025F */ 00755 00756 union { /* Watchdog Status Register A */ 00757 vuint32_t R; 00758 struct { 00759 vuint32_t WDS31:1; 00760 vuint32_t WDS30:1; 00761 vuint32_t WDS29:1; 00762 vuint32_t WDS28:1; 00763 vuint32_t WDS27:1; 00764 vuint32_t WDS26:1; 00765 vuint32_t WDS25:1; 00766 vuint32_t WDS24:1; 00767 vuint32_t WDS23:1; 00768 vuint32_t WDS22:1; 00769 vuint32_t WDS21:1; 00770 vuint32_t WDS20:1; 00771 vuint32_t WDS19:1; 00772 vuint32_t WDS18:1; 00773 vuint32_t WDS17:1; 00774 vuint32_t WDS16:1; 00775 vuint32_t WDS15:1; 00776 vuint32_t WDS14:1; 00777 vuint32_t WDS13:1; 00778 vuint32_t WDS12:1; 00779 vuint32_t WDS11:1; 00780 vuint32_t WDS10:1; 00781 vuint32_t WDS9:1; 00782 vuint32_t WDS8:1; 00783 vuint32_t WDS7:1; 00784 vuint32_t WDS6:1; 00785 vuint32_t WDS5:1; 00786 vuint32_t WDS4:1; 00787 vuint32_t WDS3:1; 00788 vuint32_t WDS2:1; 00789 vuint32_t WDS1:1; 00790 vuint32_t WDS0:1; 00791 } B; 00792 } WDSR_A; 00793 00794 union { /* Watchdog Status Register B */ 00795 vuint32_t R; 00796 struct { 00797 vuint32_t WDS31:1; 00798 vuint32_t WDS30:1; 00799 vuint32_t WDS29:1; 00800 vuint32_t WDS28:1; 00801 vuint32_t WDS27:1; 00802 vuint32_t WDS26:1; 00803 vuint32_t WDS25:1; 00804 vuint32_t WDS24:1; 00805 vuint32_t WDS23:1; 00806 vuint32_t WDS22:1; 00807 vuint32_t WDS21:1; 00808 vuint32_t WDS20:1; 00809 vuint32_t WDS19:1; 00810 vuint32_t WDS18:1; 00811 vuint32_t WDS17:1; 00812 vuint32_t WDS16:1; 00813 vuint32_t WDS15:1; 00814 vuint32_t WDS14:1; 00815 vuint32_t WDS13:1; 00816 vuint32_t WDS12:1; 00817 vuint32_t WDS11:1; 00818 vuint32_t WDS10:1; 00819 vuint32_t WDS9:1; 00820 vuint32_t WDS8:1; 00821 vuint32_t WDS7:1; 00822 vuint32_t WDS6:1; 00823 vuint32_t WDS5:1; 00824 vuint32_t WDS4:1; 00825 vuint32_t WDS3:1; 00826 vuint32_t WDS2:1; 00827 vuint32_t WDS1:1; 00828 vuint32_t WDS0:1; 00829 } B; 00830 } WDSR_B; 00831 00832 uint32_t eTPU_reserved0268[6]; /* 0x0268-0x027F */ 00833 00834 union { /* ETPU_A Channel Pending Service Status */ 00835 vuint32_t R; 00836 struct { 00837 vuint32_t SR31:1; /* Channel 31 Pending Service Status */ 00838 vuint32_t SR30:1; /* Channel 30 Pending Service Status */ 00839 vuint32_t SR29:1; /* Channel 29 Pending Service Status */ 00840 vuint32_t SR28:1; /* Channel 28 Pending Service Status */ 00841 vuint32_t SR27:1; /* Channel 27 Pending Service Status */ 00842 vuint32_t SR26:1; /* Channel 26 Pending Service Status */ 00843 vuint32_t SR25:1; /* Channel 25 Pending Service Status */ 00844 vuint32_t SR24:1; /* Channel 24 Pending Service Status */ 00845 vuint32_t SR23:1; /* Channel 23 Pending Service Status */ 00846 vuint32_t SR22:1; /* Channel 22 Pending Service Status */ 00847 vuint32_t SR21:1; /* Channel 21 Pending Service Status */ 00848 vuint32_t SR20:1; /* Channel 20 Pending Service Status */ 00849 vuint32_t SR19:1; /* Channel 19 Pending Service Status */ 00850 vuint32_t SR18:1; /* Channel 18 Pending Service Status */ 00851 vuint32_t SR17:1; /* Channel 17 Pending Service Status */ 00852 vuint32_t SR16:1; /* Channel 16 Pending Service Status */ 00853 vuint32_t SR15:1; /* Channel 15 Pending Service Status */ 00854 vuint32_t SR14:1; /* Channel 14 Pending Service Status */ 00855 vuint32_t SR13:1; /* Channel 13 Pending Service Status */ 00856 vuint32_t SR12:1; /* Channel 12 Pending Service Status */ 00857 vuint32_t SR11:1; /* Channel 11 Pending Service Status */ 00858 vuint32_t SR10:1; /* Channel 10 Pending Service Status */ 00859 vuint32_t SR9:1; /* Channel 9 Pending Service Status */ 00860 vuint32_t SR8:1; /* Channel 8 Pending Service Status */ 00861 vuint32_t SR7:1; /* Channel 7 Pending Service Status */ 00862 vuint32_t SR6:1; /* Channel 6 Pending Service Status */ 00863 vuint32_t SR5:1; /* Channel 5 Pending Service Status */ 00864 vuint32_t SR4:1; /* Channel 4 Pending Service Status */ 00865 vuint32_t SR3:1; /* Channel 3 Pending Service Status */ 00866 vuint32_t SR2:1; /* Channel 2 Pending Service Status */ 00867 vuint32_t SR1:1; /* Channel 1 Pending Service Status */ 00868 vuint32_t SR0:1; /* Channel 0 Pending Service Status */ 00869 } B; 00870 } CPSSR_A; 00871 00872 union { /* ETPU_B Channel Pending Service Status */ 00873 vuint32_t R; 00874 struct { 00875 vuint32_t SR31:1; /* Channel 31 Pending Service Status */ 00876 vuint32_t SR30:1; /* Channel 30 Pending Service Status */ 00877 vuint32_t SR29:1; /* Channel 29 Pending Service Status */ 00878 vuint32_t SR28:1; /* Channel 28 Pending Service Status */ 00879 vuint32_t SR27:1; /* Channel 27 Pending Service Status */ 00880 vuint32_t SR26:1; /* Channel 26 Pending Service Status */ 00881 vuint32_t SR25:1; /* Channel 25 Pending Service Status */ 00882 vuint32_t SR24:1; /* Channel 24 Pending Service Status */ 00883 vuint32_t SR23:1; /* Channel 23 Pending Service Status */ 00884 vuint32_t SR22:1; /* Channel 22 Pending Service Status */ 00885 vuint32_t SR21:1; /* Channel 21 Pending Service Status */ 00886 vuint32_t SR20:1; /* Channel 20 Pending Service Status */ 00887 vuint32_t SR19:1; /* Channel 19 Pending Service Status */ 00888 vuint32_t SR18:1; /* Channel 18 Pending Service Status */ 00889 vuint32_t SR17:1; /* Channel 17 Pending Service Status */ 00890 vuint32_t SR16:1; /* Channel 16 Pending Service Status */ 00891 vuint32_t SR15:1; /* Channel 15 Pending Service Status */ 00892 vuint32_t SR14:1; /* Channel 14 Pending Service Status */ 00893 vuint32_t SR13:1; /* Channel 13 Pending Service Status */ 00894 vuint32_t SR12:1; /* Channel 12 Pending Service Status */ 00895 vuint32_t SR11:1; /* Channel 11 Pending Service Status */ 00896 vuint32_t SR10:1; /* Channel 10 Pending Service Status */ 00897 vuint32_t SR9:1; /* Channel 9 Pending Service Status */ 00898 vuint32_t SR8:1; /* Channel 8 Pending Service Status */ 00899 vuint32_t SR7:1; /* Channel 7 Pending Service Status */ 00900 vuint32_t SR6:1; /* Channel 6 Pending Service Status */ 00901 vuint32_t SR5:1; /* Channel 5 Pending Service Status */ 00902 vuint32_t SR4:1; /* Channel 4 Pending Service Status */ 00903 vuint32_t SR3:1; /* Channel 3 Pending Service Status */ 00904 vuint32_t SR2:1; /* Channel 2 Pending Service Status */ 00905 vuint32_t SR1:1; /* Channel 1 Pending Service Status */ 00906 vuint32_t SR0:1; /* Channel 0 Pending Service Status */ 00907 } B; 00908 } CPSSR_B; 00909 00910 uint32_t eTPU_reserved0288[2]; /* 0x0288-0x028F */ 00911 00912 union { /* ETPU_A Channel Service Status */ 00913 vuint32_t R; 00914 struct { 00915 vuint32_t SS31:1; /* Channel 31 Service Status */ 00916 vuint32_t SS30:1; /* Channel 30 Service Status */ 00917 vuint32_t SS29:1; /* Channel 29 Service Status */ 00918 vuint32_t SS28:1; /* Channel 28 Service Status */ 00919 vuint32_t SS27:1; /* Channel 27 Service Status */ 00920 vuint32_t SS26:1; /* Channel 26 Service Status */ 00921 vuint32_t SS25:1; /* Channel 25 Service Status */ 00922 vuint32_t SS24:1; /* Channel 24 Service Status */ 00923 vuint32_t SS23:1; /* Channel 23 Service Status */ 00924 vuint32_t SS22:1; /* Channel 22 Service Status */ 00925 vuint32_t SS21:1; /* Channel 21 Service Status */ 00926 vuint32_t SS20:1; /* Channel 20 Service Status */ 00927 vuint32_t SS19:1; /* Channel 19 Service Status */ 00928 vuint32_t SS18:1; /* Channel 18 Service Status */ 00929 vuint32_t SS17:1; /* Channel 17 Service Status */ 00930 vuint32_t SS16:1; /* Channel 16 Service Status */ 00931 vuint32_t SS15:1; /* Channel 15 Service Status */ 00932 vuint32_t SS14:1; /* Channel 14 Service Status */ 00933 vuint32_t SS13:1; /* Channel 13 Service Status */ 00934 vuint32_t SS12:1; /* Channel 12 Service Status */ 00935 vuint32_t SS11:1; /* Channel 11 Service Status */ 00936 vuint32_t SS10:1; /* Channel 10 Service Status */ 00937 vuint32_t SS9:1; /* Channel 9 Service Status */ 00938 vuint32_t SS8:1; /* Channel 8 Service Status */ 00939 vuint32_t SS7:1; /* Channel 7 Service Status */ 00940 vuint32_t SS6:1; /* Channel 6 Service Status */ 00941 vuint32_t SS5:1; /* Channel 5 Service Status */ 00942 vuint32_t SS4:1; /* Channel 4 Service Status */ 00943 vuint32_t SS3:1; /* Channel 3 Service Status */ 00944 vuint32_t SS2:1; /* Channel 2 Service Status */ 00945 vuint32_t SS1:1; /* Channel 1 Service Status */ 00946 vuint32_t SS0:1; /* Channel 0 Service Status */ 00947 } B; 00948 } CSSR_A; 00949 00950 union { /* ETPU_B Channel Service Status */ 00951 vuint32_t R; 00952 struct { 00953 vuint32_t SS31:1; /* Channel 31 Service Status */ 00954 vuint32_t SS30:1; /* Channel 30 Service Status */ 00955 vuint32_t SS29:1; /* Channel 29 Service Status */ 00956 vuint32_t SS28:1; /* Channel 28 Service Status */ 00957 vuint32_t SS27:1; /* Channel 27 Service Status */ 00958 vuint32_t SS26:1; /* Channel 26 Service Status */ 00959 vuint32_t SS25:1; /* Channel 25 Service Status */ 00960 vuint32_t SS24:1; /* Channel 24 Service Status */ 00961 vuint32_t SS23:1; /* Channel 23 Service Status */ 00962 vuint32_t SS22:1; /* Channel 22 Service Status */ 00963 vuint32_t SS21:1; /* Channel 21 Service Status */ 00964 vuint32_t SS20:1; /* Channel 20 Service Status */ 00965 vuint32_t SS19:1; /* Channel 19 Service Status */ 00966 vuint32_t SS18:1; /* Channel 18 Service Status */ 00967 vuint32_t SS17:1; /* Channel 17 Service Status */ 00968 vuint32_t SS16:1; /* Channel 16 Service Status */ 00969 vuint32_t SS15:1; /* Channel 15 Service Status */ 00970 vuint32_t SS14:1; /* Channel 14 Service Status */ 00971 vuint32_t SS13:1; /* Channel 13 Service Status */ 00972 vuint32_t SS12:1; /* Channel 12 Service Status */ 00973 vuint32_t SS11:1; /* Channel 11 Service Status */ 00974 vuint32_t SS10:1; /* Channel 10 Service Status */ 00975 vuint32_t SS9:1; /* Channel 9 Service Status */ 00976 vuint32_t SS8:1; /* Channel 8 Service Status */ 00977 vuint32_t SS7:1; /* Channel 7 Service Status */ 00978 vuint32_t SS6:1; /* Channel 6 Service Status */ 00979 vuint32_t SS5:1; /* Channel 5 Service Status */ 00980 vuint32_t SS4:1; /* Channel 4 Service Status */ 00981 vuint32_t SS3:1; /* Channel 3 Service Status */ 00982 vuint32_t SS2:1; /* Channel 2 Service Status */ 00983 vuint32_t SS1:1; /* Channel 1 Service Status */ 00984 vuint32_t SS0:1; /* Channel 0 Service Status */ 00985 } B; 00986 } CSSR_B; 00987 00988 uint32_t eTPU_reserved0298[2]; /* 0x0298-0x029F */ 00989 00990 uint32_t eTPU_reserved02A0[88]; /* 0x02A0-0x03FF */ 00991 00992 /*****************************Channels********************************/ 00993 00994 struct { 00995 union { /* Channel Configuration Register */ 00996 vuint32_t R; 00997 struct { 00998 vuint32_t CIE:1; /* Channel Interruput Enable */ 00999 vuint32_t DTRE:1; /* Data Transfer Request Enable */ 01000 vuint32_t CPR:2; /* Channel Priority */ 01001 vuint32_t:2; 01002 vuint32_t ETPD:1; 01003 vuint32_t ETCS:1; /* Entry Table Condition Select */ 01004 vuint32_t:3; 01005 vuint32_t CFS:5; /* Channel Function Select */ 01006 vuint32_t ODIS:1; /* Output disable */ 01007 vuint32_t OPOL:1; /* output polarity */ 01008 vuint32_t:3; 01009 vuint32_t CPBA:11; /* Channel Parameter Base Address */ 01010 } B; 01011 } CR; 01012 01013 union { /* Channel Status Control Register */ 01014 vuint32_t R; 01015 struct { 01016 vuint32_t CIS:1; /* Channel Interruput Status */ 01017 vuint32_t CIOS:1; /* Channel Interruput Overflow Status */ 01018 vuint32_t:6; 01019 vuint32_t DTRS:1; /* Data Transfer Status */ 01020 vuint32_t DTROS:1; /* Data Transfer Overflow Status */ 01021 vuint32_t:6; 01022 vuint32_t IPS:1; /* Input Pin State */ 01023 vuint32_t OPS:1; /* Output Pin State */ 01024 vuint32_t OBE:1; /* Output Buffer Enable */ 01025 vuint32_t:11; 01026 vuint32_t FM1:1; /* Function mode */ 01027 vuint32_t FM0:1; /* Function mode */ 01028 } B; 01029 } SCR; 01030 01031 union { /* Channel Host Service Request Register */ 01032 vuint32_t R; 01033 struct { 01034 vuint32_t:29; /* Host Service Request */ 01035 vuint32_t HSR:3; 01036 } B; 01037 } HSRR; 01038 01039 uint32_t eTPU_ch_reserved00C; /* channel offset 0x00C-0x00F */ 01040 01041 } CHAN[127]; 01042 01043 uint32_t eTPU_reserved1000[7168]; /* 0x1000-0x7FFF */ 01044 01045 }; 01046 01047 01048 01049 #ifdef __MWERKS__ 01050 #pragma pop 01051 #endif 01052 01053 #ifdef __cplusplus 01054 } 01055 #endif 01056 #endif /* ifdef _ETPU_STRUCT_H_ */ 01057 /********************************************************************* 01058 * 01059 * Copyright: 01060 * Freescale Semiconductor, INC. All Rights Reserved. 01061 * You are hereby granted a copyright license to use, modify, and 01062 * distribute the SOFTWARE so long as this entire notice is 01063 * retained without alteration in any modified and/or redistributed 01064 * versions, and that such modified versions are clearly identified 01065 * as such. No licenses are granted by implication, estoppel or 01066 * otherwise under any patents or trademarks of Freescale 01067 * Semiconductor, Inc. This software is provided on an "AS IS" 01068 * basis and without warranty. 01069 * 01070 * To the maximum extent permitted by applicable law, Freescale 01071 * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, 01072 * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A 01073 * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH 01074 * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) 01075 * AND ANY ACCOMPANYING WRITTEN MATERIALS. 01076 * 01077 * To the maximum extent permitted by applicable law, IN NO EVENT 01078 * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER 01079 * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, 01080 * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER 01081 * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. 01082 * 01083 * Freescale Semiconductor assumes no responsibility for the 01084 * maintenance and support of this software 01085 * 01086 ********************************************************************/
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