/**************************************************************************
 * FILE NAME: MPC5777M.h                     COPYRIGHT (c) Freescale 2014 * 
 * REVISION:  1.8                                     All Rights Reserved *
 *                                                                        *
 * DESCRIPTION:                                                           *
 * This file contains all of the register and bit field definitions for   *
 * the MPC5777M.                                                          *
 *========================================================================*
 * UPDATE HISTORY                                                         *
 * REV      AUTHOR      DATE       	DESCRIPTION OF CHANGE                 *
 * ---   -----------  ---------    	---------------------                 *
 * 0.2      P.A.      21-Mar-12     Adding register array style           *
 *                                                                        *
 * 0.3      P.A.      05-Apr-12     Adding new modules sent by Curt       *
 *                                  Hillier                               *
 *                                                                        *
 * 0.4      P.A.      25-Jul-12     Adding latest modules.                *
 * 0.4A     C.H.      13-Aug-12     Corrected errors in memory map.       *
 *                                                                        ******
 * CGM was incorrectly generated at 0UL.  Corrected to 0xFFFB0700UL            *
 * FR_0 was incorrectly generated at 0xFC250000UL.  Corrected to 0xFFE50000UL  *
 * LFAST was incorrectly generated at 0x1UL.  Corrected to 0xFFFD8000UL        *
 * PRAMC was incorrectly generated at 0UL.  Correct to 0xFC020000UL.           *
 *                                                                             *
 * 0.4b to                                                                     *
 *  0.5b    C.H.      22-Oct-12     Interim builds for debugging.              *
 * 0.5c     C.H.      23-Oct-12     replace autogenerated SARADC               *
 *                                  block with McKinley.  Too many mis-        *
 *                                  matches present.                           *
 *                                  Collapse DSPI CTARs to array               *
 * 0.5d     C.H.      24-Oct-12     Incorporate feedback from PE.              *
 *                                    add #ifdef support for SARADC arrays     *
 *                                    add array support for MC_ME_RUN_MC       *
 * 0.6      C.H.      26-Oct-12     MC_CGM uses base address of 0xFFFB_0700    *
 *                                  and registers offsets starting at 0x0700.  *
 *                                  This results in incorrect absolute         *
 *                                  addresses starting at 0xFFFB_0E000.        *
 *                                  To fix this, commented out the reserved    *
 *                                  space "//  uint8_t MC_CGM_reserved0[1792];" *
 *                                  and keep module base address = 0xFFFB_0700. *
 *                                  This matches McKinley implementation.      *
 *                                                                             *
 * 0.7      M.D.      05-Mar-13     Updated to RDP from Jan 2013 as follows:   *
 *                                  Module INTC: Added register MPROT          *
 *                                  And updated structure of PSR register      * 
 *                                  Module MCAN: Updated registers NDAT1,      *
 *                                  NDAT2, RXFOS, RXF1S, TXFQS, TXEFS          *
 *                                  Also added some comments to Module MCAN    *
 *                                                                             *
 * 0.8      M.D.      13-Mar-13     Updated PRAMC & CRC from new XML drop      *
 *                                  Expanded AC0_DC[5] register                *
 *                                  Change to PRAMC was manually inserted as   *
 *                                  code generated from XML was not correct    *  
 *                                  MC_ME: Inserted hand coded PCTL11 & 15     *
 *                                  due to missing from XML                    *
 *                                                                        *   
 * 0.9      M.D.      25-Jul-13     Updated from new XML drop             *
 *                                                                        *
 * 1.0      M.D.      17-Oct-13     Updated from RDP rev3                 *
 *                                                                        *
 * 1.1      M.D.      31-Jan-14     Added GTM104 modules                  *
 *                                                                        *     
 * 1.2      M.D.      26-Feb-14     Compressed GTM_ATOM modules           *
 *                                                                        *     
 * 1.3      M.D.      27-Feb-14     Compressed GTM modules: MCSs, AFDs,   *
 *                                  F2As, FIFOs, SPEs, TIMs and TOM       *
 *                                                                        *     
 * 1.4      M.D.      27-Feb-14     Removed a module                      *
 *                                                                        *
 * 1.5      M.D.      13-Mar-14     Updated with new GTM RDP              *
 *                                                                        *
 * 1.6      M.D.      02-Apr-14     Updated with RDP Rev 3                *
 *                                                                        *
 * 1.7      M.D.      03-Apr-14     Corrected some GTM macros             *
 *                                                                        *
 * 1.8      M.D.      07-Apr-14     Corrected MC_CGM base address         *
 *                                                                        *
 *========================================================================*
 * COPYRIGHT:                                                             *
 *  Freescale Semiconductor, INC. All Rights Reserved. You are hereby     *
 *  granted a copyright license to use, modify, and distribute the        *
 *  SOFTWARE so long as this entire notice is retained without alteration *
 *  in any modified and/or redistributed versions, and that such modified *
 *  versions are clearly identified as such. No licenses are granted by   *
 *  implication, estoppel or otherwise under any patentsor trademarks     *
 *  of Freescale Semiconductor, Inc. This software is provided on an      *
 *  "AS IS" basis and without warranty.                                   *
 *                                                                        *
 *  To the maximum extent permitted by applicable law, Freescale          *
 *  Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,    *
 *  INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A      *
 *  PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD  *
 *  TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY     *
 *  ACCOMPANYING WRITTEN MATERIALS.                                       *
 *                                                                        *
 *  To the maximum extent permitted by applicable law, IN NO EVENT        *
 *  SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER    *
 *  (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,  *
 *  BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER         *
 *  PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.  *
 *                                                                        *
 *  Freescale Semiconductor assumes no responsibility for the             *
 *  maintenance and support of this software                              *
 *                                                                        *
 **************************************************************************/
/*>>>>>>> NOTE! this file is auto-generated please do not edit it! <<<<<<<*/

/**************************************************************************
 * Example register & bit field write:                                    *
 *                                                                        *
 *  <MODULE>.<REGISTER>.B.<BIT> = 1;                                      *
 *  <MODULE>.<REGISTER>.R       = 0x10000000;                             *
 *                                                                        *
 **************************************************************************/

#ifndef _MPC5777M_H_
#define _MPC5777M_H_
#include "typedefs.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __MWERKS__
#pragma push
#pragma ANSI_strict off
#endif
#ifdef __ghs__
#pragma ghs nowarning 618
#endif


/* ============================================================================
   =============================== Module: C55FMC =============================
   ============================================================================ */

struct C55FMC_tag {
  union {                              /* Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t RVE:1;                 /* Read Voltage Error */
      vuint32_t RRE:1;                 /* Read Reference Error */
      vuint32_t AEE:1;                 /* Address Encode Error */
      vuint32_t EEE:1;                 /* ECC after ECC Error */
      vuint32_t  :12;
      vuint32_t EER:1;                 /* ECC Event Error */
      vuint32_t RWE:1;                 /* Read-While-Write Event Error */
      vuint32_t SBC:1;                 /* Single Bit Correction */
      vuint32_t  :1;
      vuint32_t PEAS:1;                /* Program Access Space */
      vuint32_t DONE:1;                /* State Machine Status */
      vuint32_t PEG:1;                 /* Program/Erase Good */
      vuint32_t PECIE:1;               /* Program/Erase Complete Interrupt Enable */
      vuint32_t FERS:1;                /* Factory Erase and Program */
      vuint32_t  :2;
      vuint32_t PGM:1;                 /* Program */
      vuint32_t PSUS:1;                /* Program Suspend */
      vuint32_t ERS:1;                 /* Erase */
      vuint32_t ESUS:1;                /* Erase Suspend */
      vuint32_t EHV:1;                 /* Enable High Voltage */
    } B;
  } MCR;

  union {                              /* Alternate Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t PEASa:1;               /* Program Access Space */
      vuint32_t DONEa:1;               /* State Machine Status */
      vuint32_t PEGa:1;                /* Program/Erase Good */
      vuint32_t  :4;
      vuint32_t PGMa:1;                /* Program */
      vuint32_t PSUSa:1;               /* Program Suspend */
      vuint32_t ERSa:1;                /* Erase Suspend */
      vuint32_t ESUSa:1;               /* Erase Suspend */
      vuint32_t EHVa:1;                /* Enable High Voltage */
    } B;
  } MCRA;

  union {                              /* Extended Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t HT:1;                  /* High Temperature Enabled. */
      vuint32_t  :2;
      vuint32_t n256K:5;
      vuint32_t n64Kh:3;
      vuint32_t n32Kh:2;
      vuint32_t n16Kh:3;
      vuint32_t n64Km:3;
      vuint32_t n32Km:2;
      vuint32_t n16Km:3;
      vuint32_t n64Kl:3;
      vuint32_t n32Kl:2;
      vuint32_t n16Kl:3;
    } B;
  } MCRE;

  uint8_t C55FMC_reserved0[4];
  union {                              /* Lock 0 register */
    vuint32_t R;
    struct {
      vuint32_t TSLOCK:1;              /* UTest NVM Lock. */
      vuint32_t  :1;
      vuint32_t LOWLOCK:14;            /* Low Block Lock */
      vuint32_t MIDLOCK:16;            /* Mid Block Lock */
    } B;
  } LOCK0;

  union {                              /* Lock 1 register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t HIGHLOCK:16;           /* High Block Lock */
    } B;
  } LOCK1;

  union {                              /* Lock 2 register */
    vuint32_t R;
    struct {
      vuint32_t A256KLOCK:32;          /* 256 KB Block Lock */
    } B;
  } LOCK2;

  union {                              /* Lock 3 register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t A256KLOCK:16;          /* 256 KB Block Lock */
    } B;
  } LOCK3;

  uint8_t C55FMC_reserved1[8];
  union {                              /* Alternate Lock 0 register */
    vuint32_t R;
    struct {
      vuint32_t TSLOCKa:1;             /* Alternate UTest NVM Lock. */
      vuint32_t  :1;
      vuint32_t LOWLOCKa:14;           /* Alternate Low Block Lock */
      vuint32_t MIDLOCKa:16;           /* Alternate Mid Block Lock */
    } B;
  } LOCK0A;

  union {                              /* Alternate Lock 1 register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t HIGHLOCKa:16;          /* Alternate High Block Lock */
    } B;
  } LOCK1A;

  uint8_t C55FMC_reserved2[8];
  union {                              /* Select 0 register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t LOWSEL:14;             /* LOW Block Select. */
      vuint32_t MIDSEL:16;             /* Mid Block Select. */
    } B;
  } SEL0;

  union {                              /* Select 1 register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t HIGHSEL:16;            /* High Block Select. */
    } B;
  } SEL1;

  union {                              /* Select 2 register */
    vuint32_t R;
    struct {
      vuint32_t A256KSEL:32;           /* 256 KB Block Select. */
    } B;
  } SEL2;

  union {                              /* Select 3 register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t A256KSEL:16;           /* 256 KB Block Select. */
    } B;
  } SEL3;

  uint8_t C55FMC_reserved3[8];
  union {                              /* Address register */
    vuint32_t R;
    struct {
      vuint32_t SAD:1;
      vuint32_t aH:1;
      vuint32_t aM:1;
      vuint32_t aL:1;
      vuint32_t a256k:1;
      vuint32_t a64k:1;
      vuint32_t a32k:1;
      vuint32_t a16k:1;
      vuint32_t ADDR:21;
      vuint32_t  :3;
    } B;
  } ADR;

  union {                              /* UTest 0 register */
    vuint32_t R;
    struct {
      vuint32_t UTE:1;
      vuint32_t SBCE:1;
      vuint32_t  :11;
      vuint32_t CPR:1;
      vuint32_t CPA:1;
      vuint32_t CPE:1;
      vuint32_t  :6;
      vuint32_t NAIBP:1;
      vuint32_t AIBPE:1;
      vuint32_t  :1;
      vuint32_t AISUS:1;
      vuint32_t MRE:1;
      vuint32_t MRV:1;
      vuint32_t  :1;
      vuint32_t AIS:1;
      vuint32_t AIE:1;
      vuint32_t AID:1;
    } B;
  } UT0;

  union {                              /* UMISR register */
    vuint32_t R;
    struct {
      vuint32_t MISR:32;
    } B;
  } UM[9];

  union {                              /* UMISR register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t MISR:1;                /* MISR[288]. */
    } B;
  } UM9;

  union {                              /* Over-Program Protection 0 register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t LOWOPP:14;             /* Low Block Over-Program Protection[13:0]. */
      vuint32_t MIDOPP:16;             /* Mid Block Over-Program Protection[15:0]. */
    } B;
  } OPP0;

  union {                              /* Over-Program Protection 1 register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t HIGHOPP:16;            /* High Block Over-Program Protection[15:0]. */
    } B;
  } OPP1;

  union {                              /* Over-Program Protection 2 register */
    vuint32_t R;
    struct {
      vuint32_t A256KOPP:32;           /* 256K Block Over-Program Protection[31:0]. */
    } B;
  } OPP2;

  union {                              /* Over-Program Protection 3 register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t A256KOPP:16;           /* 256K Block Over-Program Protection[47:32]. */
    } B;
  } OPP3;

  union {                              /* Test Mode Disable Password Check register */
    vuint32_t R;
    struct {
      vuint32_t PWD:32;                /* Password challenge */
    } B;
  } TMD;
};


/* ============================================================================
   =============================== Module: CMU ================================
   ============================================================================ */

struct CMU_tag {
  union {                              /* CMU Control Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SFM:1;                 /* Start frequency measure. */
      vuint32_t  :13;
      vuint32_t CKSEL1:2;              /* Frequency measure clock selection bit. */
      vuint32_t  :5;
      vuint32_t RCDIV:2;               /* CLKMT0_RMN division factor. */
      vuint32_t CME:1;                 /* CLKMN1 monitor enable. */
    } B;
  } CSR;

  union {                              /* CMU Frequency Display Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t FD:20;                 /* Measured frequency bits. */
    } B;
  } FDR;

  union {                              /* CMU High Frequency Reference Register CLKMN1 */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t HFREF:12;              /* High Frequency reference value. */
    } B;
  } HFREFR;

  union {                              /* CMU Low Frequency Reference Register CLKMN1 */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t LFREF:12;              /* Low Frequency reference value. */
    } B;
  } LFREFR;

  union {                              /* CMU Interrupt Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t  :1;
      vuint32_t FHHI:1;                /* CLKMN1 frequency higher than high reference event status. */
      vuint32_t FLLI:1;                /* CLKMN1 frequency less than low reference event status. */
      vuint32_t OLRI:1;                /* Oscillator frequency less than f CLKMT0_RMN * 2RCDIVevent status. */
    } B;
  } ISR;

  uint8_t CMU_reserved0[4];
  union {                              /* CMU Measurement Duration Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t MD:20;                 /* Measurement duration bits */
    } B;
  } MDR;
};


/* ============================================================================
   =============================== Module: CRC ================================
   ============================================================================ */

struct CRC_tag {
  union {                              /* Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t  :18;
      vuint32_t SWAP_BYTEWISE:1;       /* Swap CRC_INP byte-wise */
      vuint32_t SWAP_BITWISE:1;        /* Swap CRC_INP bit-wise */
      vuint32_t POLYG:2;               /* Polynomial selection */
      vuint32_t SWAP:1;                /* Swap selection */
      vuint32_t INV:1;                 /* Inversion selection */
    } B;
  } CFG;

  union {                              /* Input Register */
    vuint32_t R;
    struct {
      vuint32_t INP:32;                /* Input data for the CRC computation */
    } B;
  } INP;

  union {                              /* Current Status Register */
    vuint32_t R;
    struct {
      vuint32_t CSTAT:32;              /* CRC signature status */
    } B;
  } CSTAT;

  union {                              /* Output Register */
    vuint32_t R;
    struct {
      vuint32_t OUTP:32;               /* Final CRC signature */
    } B;
  } OUTP;
};


/* ============================================================================
   =============================== Module: DMAMUX =============================
   ============================================================================ */

struct DMAMUX_tag {
  union {                              /* Channel Configuration register */
    vuint8_t R;
    struct {
      vuint8_t ENBL:1;                 /* DMA Channel Enable */
      vuint8_t TRIG:1;                 /* DMA Channel Trigger Enable */
      vuint8_t SOURCE:6;               /* DMA Channel Source (Slot) */
    } B;
  } CHCFG[16];
};


/* ============================================================================
   =============================== Module: DSPI ===============================
   ============================================================================ */

struct DSPI_tag {
  union {                              /* DSPI Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t MSTR:1;
      vuint32_t CONT_SCKE:1;
      vuint32_t DCONF:2;
      vuint32_t FRZ:1;
      vuint32_t MTFE:1;
      vuint32_t PCSSE:1;
      vuint32_t ROOE:1;
      vuint32_t PCSIS:8;
      vuint32_t  :1;
      vuint32_t MDIS:1;
      vuint32_t DIS_TXF:1;
      vuint32_t DIS_RXF:1;
      vuint32_t CLR_TXF:1;
      vuint32_t CLR_RXF:1;
      vuint32_t SMPL_PT:2;
      vuint32_t  :4;
      vuint32_t XSPI:1;
      vuint32_t FCPCS:1;
      vuint32_t PES:1;
      vuint32_t HALT:1;
    } B;
  } MCR;

  uint8_t DSPI_reserved0[4];
  union {                              /* DSPI Transfer Count Register */
    vuint32_t R;
    struct {
      vuint32_t SPI_TCNT:16;
      vuint32_t  :16;
    } B;
  } TCR;

  union {
    union {                            /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
      vuint32_t R;
      struct {
        vuint32_t DBR:1;
        vuint32_t FMSZ:4;
        vuint32_t CPOL:1;
        vuint32_t CPHA:1;
        vuint32_t LSBFE:1;
        vuint32_t PCSSCK:2;
        vuint32_t PASC:2;
        vuint32_t PDT:2;
        vuint32_t PBR:2;
        vuint32_t CSSCK:4;
        vuint32_t ASC:4;
        vuint32_t DT:4;
        vuint32_t BR:4;
      } B;
    } CTAR[8];
    union {                            /* DSPI Clock and Transfer Attributes Register (In Slave Mode) */
      vuint32_t R;
      struct {
        vuint32_t FMSZ:5;
        vuint32_t CPOL:1;
        vuint32_t CPHA:1;
        vuint32_t PE:1;
        vuint32_t PP:1;
        vuint32_t FMSZ5:1;
        vuint32_t  :22;
      } B;
    } CTAR_SLAVE[2];
  } MODE;

  union {                              /* DSPI Status Register */
    vuint32_t R;
    struct {
      vuint32_t TCF:1;
      vuint32_t TXRXS:1;
      vuint32_t SPITCF:1;
      vuint32_t EOQF:1;
      vuint32_t TFUF:1;
      vuint32_t DSITCF:1;
      vuint32_t TFFF:1;
      vuint32_t BSYF:1;
      vuint32_t CMDTCF:1;
      vuint32_t DPEF:1;
      vuint32_t SPEF:1;
      vuint32_t DDIF:1;
      vuint32_t RFOF:1;
      vuint32_t TFIWF:1;
      vuint32_t RFDF:1;
      vuint32_t CMDFFF:1;
      vuint32_t TXCTR:4;
      vuint32_t TXNXTPTR:4;
      vuint32_t RXCTR:4;
      vuint32_t POPNXTPTR:4;
    } B;
  } SR;

  union {                              /* DSPI DMA/Interrupt Request Select and Enable Register */
    vuint32_t R;
    struct {
      vuint32_t TCF_RE:1;
      vuint32_t CMDFFF_RE:1;
      vuint32_t SPITCF_RE:1;
      vuint32_t EOQF_RE:1;
      vuint32_t TFUF_RE:1;
      vuint32_t DSITCF_RE:1;
      vuint32_t TFFF_RE:1;
      vuint32_t TFFF_DIRS:1;
      vuint32_t CMDTCF_RE:1;
      vuint32_t DPEF_RE:1;
      vuint32_t SPEF_RE:1;
      vuint32_t DDIF_RE:1;
      vuint32_t RFOF_RE:1;
      vuint32_t TFIWF_RE:1;
      vuint32_t RFDF_RE:1;
      vuint32_t RFDF_DIRS:1;
      vuint32_t CMDFFF_DIRS:1;
      vuint32_t DDIF_DIRS:1;
      vuint32_t  :14;
    } B;
  } RSER;

  union {
    union {                            /* DSPI PUSH FIFO Register In Master Mode */
      vuint32_t R;
      struct {
        vuint32_t CONT:1;
        vuint32_t CTAS:3;
        vuint32_t EOQ:1;
        vuint32_t CTCNT:1;
        vuint32_t PE_MASC:1;
        vuint32_t PP_MCSC:1;
        vuint32_t PCS:8;
        vuint32_t TXDATA:16;
      } B;
    } PUSHR;
    union {                            /* DSPI PUSH FIFO Register In Slave Mode */
      vuint32_t R;
      struct {
        vuint32_t  :16;
        vuint32_t TXDATA:16;
      } B;
    } PUSHR_SLAVE;
  } PUSHR;

  union {                              /* DSPI POP FIFO Register */
    vuint32_t R;
    struct {
      vuint32_t RXDATA:32;
    } B;
  } POPR;

  union {                              /* DSPI Transmit FIFO Registers */
    vuint32_t R;
    struct {
      vuint32_t TXCMD_TXDATA:16;
      vuint32_t TXDATA:16;
    } B;
  } TXFR[4];

  uint8_t DSPI_reserved1[48];
  union {                              /* DSPI Receive FIFO Registers */
    vuint32_t R;
    struct {
      vuint32_t RXDATA:32;
    } B;
  } RXFR[4];

  uint8_t DSPI_reserved2[48];
  union {                              /* DSPI DSI Configuration Register 0 */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t FMSZ4:1;
      vuint32_t  :6;
      vuint32_t FMSZ5:1;
      vuint32_t  :1;
      vuint32_t ITSB:1;
      vuint32_t TSBC:1;
      vuint32_t TXSS:1;
      vuint32_t TPOL:1;
      vuint32_t  :1;
      vuint32_t CID:1;
      vuint32_t DCONT:1;
      vuint32_t DSICTAS:3;
      vuint32_t DMS:1;
      vuint32_t PES:1;
      vuint32_t PE:1;
      vuint32_t PP:1;
      vuint32_t DPCSx:8;
    } B;
  } DSICR0;

  union {                              /* DSPI DSI Serialization Data Register 0 */
    vuint32_t R;
    struct {
      vuint32_t SER_DATA:32;
    } B;
  } SDR0;

  union {                              /* DSPI DSI Alternate Serialization Data Register 0 */
    vuint32_t R;
    struct {
      vuint32_t ASER_DATA:32;
    } B;
  } ASDR0;

  union {                              /* DSPI DSI Transmit Comparison Register 0 */
    vuint32_t R;
    struct {
      vuint32_t COMP_DATA:32;
    } B;
  } COMPR0;

  union {                              /* DSPI DSI Deserialization Data Register 0 */
    vuint32_t R;
    struct {
      vuint32_t DESER_DATA:32;
    } B;
  } DDR0;

  union {                              /* DSPI DSI Configuration Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t TSBCNT:6;
      vuint32_t  :5;
      vuint32_t DSI64E:1;
      vuint32_t DSE1:1;
      vuint32_t DSE0:1;
      vuint32_t TRGPRD:8;
      vuint32_t DPCS1_x:8;
    } B;
  } DSICR1;

  union {                              /* DSPI DSI Serialization Source Select Register 0 */
    vuint32_t R;
    struct {
      vuint32_t SS:32;
    } B;
  } SSR0;

  union {                              /* DSPI DSI Parallel Input Select Register 0 */
    vuint32_t R;
    struct {
      vuint32_t IPS7:4;
      vuint32_t IPS6:4;
      vuint32_t IPS5:4;
      vuint32_t IPS4:4;
      vuint32_t IPS3:4;
      vuint32_t IPS2:4;
      vuint32_t IPS1:4;
      vuint32_t IPS0:4;
    } B;
  } PISR0;

  union {                              /* DSPI DSI Parallel Input Select Register 1 */
    vuint32_t R;
    struct {
      vuint32_t IPS15:4;
      vuint32_t IPS14:4;
      vuint32_t IPS13:4;
      vuint32_t IPS12:4;
      vuint32_t IPS11:4;
      vuint32_t IPS10:4;
      vuint32_t IPS9:4;
      vuint32_t IPS8:4;
    } B;
  } PISR1;

  union {                              /* DSPI DSI Parallel Input Select Register 2 */
    vuint32_t R;
    struct {
      vuint32_t IPS23:4;
      vuint32_t IPS22:4;
      vuint32_t IPS21:4;
      vuint32_t IPS20:4;
      vuint32_t IPS19:4;
      vuint32_t IPS18:4;
      vuint32_t IPS17:4;
      vuint32_t IPS16:4;
    } B;
  } PISR2;

  union {                              /* DSPI DSI Parallel Input Select Register 3 */
    vuint32_t R;
    struct {
      vuint32_t IPS31:4;
      vuint32_t IPS30:4;
      vuint32_t IPS29:4;
      vuint32_t IPS28:4;
      vuint32_t IPS27:4;
      vuint32_t IPS26:4;
      vuint32_t IPS25:4;
      vuint32_t IPS24:4;
    } B;
  } PISR3;

  union {                              /* DSPI DSI Deserialized Data Interrupt Mask Register 0 */
    vuint32_t R;
    struct {
      vuint32_t MASK:32;
    } B;
  } DIMR0;

  union {                              /* DSPI DSI Deserialized Data Polarity Interrupt Register 0 */
    vuint32_t R;
    struct {
      vuint32_t DP:32;
    } B;
  } DPIR0;

  union {                              /* DSPI DSI Serialization Data Register 1 */
    vuint32_t R;
    struct {
      vuint32_t SER_DATA:32;
    } B;
  } SDR1;

  union {                              /* DSPI DSI Alternate Serialization Data Register 1 */
    vuint32_t R;
    struct {
      vuint32_t ASER_DATA:32;
    } B;
  } ASDR1;

  union {                              /* DSPI DSI Transmit Comparison Register 1 */
    vuint32_t R;
    struct {
      vuint32_t COMP_DATA:32;
    } B;
  } COMPR1;

  union {                              /* DSPI DSI Deserialization Data Register 1 */
    vuint32_t R;
    struct {
      vuint32_t DESER_DATA:32;
    } B;
  } DDR1;

  union {                              /* DSPI DSI Serialization Source Select Register 1 */
    vuint32_t R;
    struct {
      vuint32_t SS:32;
    } B;
  } SSR1;

  union {                              /* DSPI DSI Parallel Input Select Register 4 */
    vuint32_t R;
    struct {
      vuint32_t IPS39:4;
      vuint32_t IPS38:4;
      vuint32_t IPS37:4;
      vuint32_t IPS36:4;
      vuint32_t IPS35:4;
      vuint32_t IPS34:4;
      vuint32_t IPS33:4;
      vuint32_t IPS32:4;
    } B;
  } PISR4;

  union {                              /* DSPI DSI Parallel Input Select Register 5 */
    vuint32_t R;
    struct {
      vuint32_t IPS47:4;
      vuint32_t IPS46:4;
      vuint32_t IPS45:4;
      vuint32_t IPS44:4;
      vuint32_t IPS43:4;
      vuint32_t IPS42:4;
      vuint32_t IPS41:4;
      vuint32_t IPS40:4;
    } B;
  } PISR5;

  union {                              /* DSPI DSI Parallel Input Select Register 6 */
    vuint32_t R;
    struct {
      vuint32_t IPS55:4;
      vuint32_t IPS54:4;
      vuint32_t IPS53:4;
      vuint32_t IPS52:4;
      vuint32_t IPS51:4;
      vuint32_t IPS50:4;
      vuint32_t IPS49:4;
      vuint32_t IPS48:4;
    } B;
  } PISR6;

  union {                              /* DSPI DSI Parallel Input Select Register 7 */
    vuint32_t R;
    struct {
      vuint32_t IPS63:4;
      vuint32_t IPS62:4;
      vuint32_t IPS61:4;
      vuint32_t IPS60:4;
      vuint32_t IPS59:4;
      vuint32_t IPS58:4;
      vuint32_t IPS57:4;
      vuint32_t IPS56:4;
    } B;
  } PISR7;

  union {                              /* DSPI DSI Deserialized Data Interrupt Mask Register 1 */
    vuint32_t R;
    struct {
      vuint32_t MASK:32;
    } B;
  } DIMR1;

  union {                              /* DSPI DSI Deserialized Data Polarity Interrupt Register 1 */
    vuint32_t R;
    struct {
      vuint32_t DP:32;
    } B;
  } DPIR1;

  union {                              /* DSPI Clock and Transfer Attributes Register Extended */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t FMSZE:1;
      vuint32_t  :5;
      vuint32_t DTCP:11;
    } B;
  } CTARE[8];

  union {                              /* DSPI Status Register Extended */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t CMDCTR:4;
      vuint32_t CMDNXTPTR:4;
    } B;
  } SREX;
};


/* ============================================================================
   =============================== Module: DTS ================================
   ============================================================================ */

struct DTS_tag {
  union {                              /* Output Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t DTS_EN_B:1;
      vuint32_t DTS_EN:1;
    } B;
  } ENABLE;

  union {                              /* Startup Register */
    vuint32_t R;
    struct {
      vuint32_t AD:32;
    } B;
  } STARTUP;

  union {                              /* Semaphore Register */
    vuint32_t R;
    struct {
      vuint32_t ST:32;
    } B;
  } SEMAPHORE;

  union {                              /* Semaphore Extension */
    vuint32_t R;
    struct {
      vuint32_t ST_B:32;
    } B;
  } SEMAPHORE_B;
};


/* ============================================================================
   =============================== Module: EBI ================================
   ============================================================================ */

struct EBI_tag {
  union {                              /* Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t ACGE:1;
      vuint32_t  :8;
      vuint32_t MDIS:1;
      vuint32_t  :3;
      vuint32_t D16_31:1;
      vuint32_t  :1;
      vuint32_t DBM:1;
    } B;
  } MCR;

  uint8_t EBI_reserved0[12];
  union {                              /* Base Register Bank */
    vuint32_t R;
    struct {
      vuint32_t BA:17;
      vuint32_t  :2;
      vuint32_t LWRN:1;
      vuint32_t PS:1;
      vuint32_t EOE:2;
      vuint32_t SBL:1;
      vuint32_t AD_MUX:1;
      vuint32_t BL:1;
      vuint32_t WEBS:1;
      vuint32_t TBDIP:1;
      vuint32_t GCSN:1;
      vuint32_t  :1;
      vuint32_t BI:1;
      vuint32_t V:1;
    } B;
  } BR0;

  union {                              /* Option Register Bank */
    vuint32_t R;
    struct {
      vuint32_t AM:17;
      vuint32_t  :2;
      vuint32_t APS:1;                 /* Address by Port Size */
      vuint32_t  :1;
      vuint32_t AWE:1;                 /* Address / Write Enable Select */
      vuint32_t  :2;
      vuint32_t SCY:4;
      vuint32_t  :1;
      vuint32_t BSCY:2;
      vuint32_t  :1;
    } B;
  } OR0;

  union {                              /* Base Register Bank */
    vuint32_t R;
    struct {
      vuint32_t BA:17;
      vuint32_t  :2;
      vuint32_t LWRN:1;
      vuint32_t PS:1;
      vuint32_t EOE:2;
      vuint32_t SBL:1;
      vuint32_t AD_MUX:1;
      vuint32_t BL:1;
      vuint32_t WEBS:1;
      vuint32_t TBDIP:1;
      vuint32_t GCSN:1;
      vuint32_t  :1;
      vuint32_t BI:1;
      vuint32_t V:1;
    } B;
  } BR1;

  union {                              /* Option Register Bank */
    vuint32_t R;
    struct {
      vuint32_t AM:17;
      vuint32_t  :2;
      vuint32_t APS:1;                 /* Address by Port Size */
      vuint32_t  :1;
      vuint32_t AWE:1;                 /* Address / Write Enable Select */
      vuint32_t  :2;
      vuint32_t SCY:4;
      vuint32_t  :1;
      vuint32_t BSCY:2;
      vuint32_t  :1;
    } B;
  } OR1;

  union {                              /* Base Register Bank */
    vuint32_t R;
    struct {
      vuint32_t BA:17;
      vuint32_t  :2;
      vuint32_t LWRN:1;
      vuint32_t PS:1;
      vuint32_t EOE:2;
      vuint32_t SBL:1;
      vuint32_t AD_MUX:1;
      vuint32_t BL:1;
      vuint32_t WEBS:1;
      vuint32_t TBDIP:1;
      vuint32_t GCSN:1;
      vuint32_t  :1;
      vuint32_t BI:1;
      vuint32_t V:1;
    } B;
  } BR2;

  union {                              /* Option Register Bank */
    vuint32_t R;
    struct {
      vuint32_t AM:17;
      vuint32_t  :2;
      vuint32_t APS:1;                 /* Address by Port Size */
      vuint32_t  :1;
      vuint32_t AWE:1;                 /* Address / Write Enable Select */
      vuint32_t  :2;
      vuint32_t SCY:4;
      vuint32_t  :1;
      vuint32_t BSCY:2;
      vuint32_t  :1;
    } B;
  } OR2;

  union {                              /* Base Register Bank */
    vuint32_t R;
    struct {
      vuint32_t BA:17;
      vuint32_t  :2;
      vuint32_t LWRN:1;
      vuint32_t PS:1;
      vuint32_t EOE:2;
      vuint32_t SBL:1;
      vuint32_t AD_MUX:1;
      vuint32_t BL:1;
      vuint32_t WEBS:1;
      vuint32_t TBDIP:1;
      vuint32_t GCSN:1;
      vuint32_t  :1;
      vuint32_t BI:1;
      vuint32_t V:1;
    } B;
  } BR3;

  union {                              /* Option Register Bank */
    vuint32_t R;
    struct {
      vuint32_t AM:17;
      vuint32_t  :2;
      vuint32_t APS:1;                 /* Address by Port Size */
      vuint32_t  :1;
      vuint32_t AWE:1;                 /* Address / Write Enable Select */
      vuint32_t  :2;
      vuint32_t SCY:4;
      vuint32_t  :1;
      vuint32_t BSCY:2;
      vuint32_t  :1;
    } B;
  } OR3;
};


/* ============================================================================
   =============================== Module: FCCU ===============================
   ============================================================================ */

struct FCCU_tag {
  union {                              /* Control Register */
    vuint32_t R;
    struct {
      vuint32_t FILTER_BYPASS:1;
      vuint32_t FILTER_WIDTH:2;
      vuint32_t  :19;
      vuint32_t DEBUG:1;
      vuint32_t  :1;
      vuint32_t OPS:2;
      vuint32_t  :1;
      vuint32_t OPR:5;
    } B;
  } CTRL;

  union {                              /* CTRL Key Register */
    vuint32_t R;
    struct {
      vuint32_t CTRLK:32;
    } B;
  } CTRLK;

  union {                              /* Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t FCCU_SET_AFTER_RESET:1;
      vuint32_t FCCU_SET_CLEAR:2;
      vuint32_t  :2;
      vuint32_t  :4;
      vuint32_t  :1;
      vuint32_t  :2;
      vuint32_t OD:1;
      vuint32_t  :1;
      vuint32_t SM:1;
      vuint32_t PS:1;
      vuint32_t FOM:3;
      vuint32_t  :6;
    } B;
  } CFG;

  uint8_t FCCU_reserved0[16];
  union {                              /* RF Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t RFC31:1;
      vuint32_t RFC30:1;
      vuint32_t RFC29:1;
      vuint32_t RFC28:1;
      vuint32_t RFC27:1;
      vuint32_t RFC26:1;
      vuint32_t RFC25:1;
      vuint32_t RFC24:1;
      vuint32_t RFC23:1;
      vuint32_t RFC22:1;
      vuint32_t RFC21:1;
      vuint32_t RFC20:1;
      vuint32_t RFC19:1;
      vuint32_t RFC18:1;
      vuint32_t RFC17:1;
      vuint32_t RFC16:1;
      vuint32_t RFC15:1;
      vuint32_t RFC14:1;
      vuint32_t RFC13:1;
      vuint32_t RFC12:1;
      vuint32_t RFC11:1;
      vuint32_t RFC10:1;
      vuint32_t RFC9:1;
      vuint32_t RFC8:1;
      vuint32_t RFC7:1;
      vuint32_t RFC6:1;
      vuint32_t RFC5:1;
      vuint32_t RFC4:1;
      vuint32_t RFC3:1;
      vuint32_t RFC2:1;
      vuint32_t RFC1:1;
      vuint32_t RFC0:1;
    } B;
  } RF_CFG[4];

  uint8_t FCCU_reserved1[32];
  union {                              /* RFS Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t RFSC31:1;
      vuint32_t RFSC30:1;
      vuint32_t RFSC29:1;
      vuint32_t RFSC28:1;
      vuint32_t RFSC27:1;
      vuint32_t RFSC26:1;
      vuint32_t RFSC25:1;
      vuint32_t RFSC24:1;
      vuint32_t RFSC23:1;
      vuint32_t RFSC22:1;
      vuint32_t RFSC21:1;
      vuint32_t RFSC20:1;
      vuint32_t RFSC19:1;
      vuint32_t RFSC18:1;
      vuint32_t RFSC17:1;
      vuint32_t RFSC16:1;
      vuint32_t RFSC15:1;
      vuint32_t RFSC14:1;
      vuint32_t RFSC13:1;
      vuint32_t RFSC12:1;
      vuint32_t RFSC11:1;
      vuint32_t RFSC10:1;
      vuint32_t RFSC9:1;
      vuint32_t RFSC8:1;
      vuint32_t RFSC7:1;
      vuint32_t RFSC6:1;
      vuint32_t RFSC5:1;
      vuint32_t RFSC4:1;
      vuint32_t RFSC3:1;
      vuint32_t RFSC2:1;
      vuint32_t RFSC1:1;
      vuint32_t RFSC0:1;
    } B;
  } RFS_CFG[8];

  uint8_t FCCU_reserved2[20];
  union {                              /* UF Status Register */
    vuint32_t R;
    struct {
      vuint32_t RFS31:1;
      vuint32_t RFS30:1;
      vuint32_t RFS29:1;
      vuint32_t RFS28:1;
      vuint32_t RFS27:1;
      vuint32_t RFS26:1;
      vuint32_t RFS25:1;
      vuint32_t RFS24:1;
      vuint32_t RFS23:1;
      vuint32_t RFS22:1;
      vuint32_t RFS21:1;
      vuint32_t RFS20:1;
      vuint32_t RFS19:1;
      vuint32_t RFS18:1;
      vuint32_t RFS17:1;
      vuint32_t RFS16:1;
      vuint32_t RFS15:1;
      vuint32_t RFS14:1;
      vuint32_t RFS13:1;
      vuint32_t RFS12:1;
      vuint32_t RFS11:1;
      vuint32_t RFS10:1;
      vuint32_t RFS9:1;
      vuint32_t RFS8:1;
      vuint32_t RFS7:1;
      vuint32_t RFS6:1;
      vuint32_t RFS5:1;
      vuint32_t RFS4:1;
      vuint32_t RFS3:1;
      vuint32_t RFS2:1;
      vuint32_t RFS1:1;
      vuint32_t RFS0:1;
    } B;
  } RF_S[4];

  union {                              /* RF Key Register */
    vuint32_t R;
    struct {
      vuint32_t RFK:32;
    } B;
  } RFK;

  union {                              /* RF Enable Register */
    vuint32_t R;
    struct {
      vuint32_t RFE31:1;
      vuint32_t RFE30:1;
      vuint32_t RFE29:1;
      vuint32_t RFE28:1;
      vuint32_t RFE27:1;
      vuint32_t RFE26:1;
      vuint32_t RFE25:1;
      vuint32_t RFE24:1;
      vuint32_t RFE23:1;
      vuint32_t RFE22:1;
      vuint32_t RFE21:1;
      vuint32_t RFE20:1;
      vuint32_t RFE19:1;
      vuint32_t RFE18:1;
      vuint32_t RFE17:1;
      vuint32_t RFE16:1;
      vuint32_t RFE15:1;
      vuint32_t RFE14:1;
      vuint32_t RFE13:1;
      vuint32_t RFE12:1;
      vuint32_t RFE11:1;
      vuint32_t RFE10:1;
      vuint32_t RFE9:1;
      vuint32_t RFE8:1;
      vuint32_t RFE7:1;
      vuint32_t RFE6:1;
      vuint32_t RFE5:1;
      vuint32_t RFE4:1;
      vuint32_t RFE3:1;
      vuint32_t RFE2:1;
      vuint32_t RFE1:1;
      vuint32_t RFE0:1;
    } B;
  } RF_E[4];

  union {                              /* RF Time-out Enable Register */
    vuint32_t R;
    struct {
      vuint32_t RFTOE31:1;
      vuint32_t RFTOE30:1;
      vuint32_t RFTOE29:1;
      vuint32_t RFTOE28:1;
      vuint32_t RFTOE27:1;
      vuint32_t RFTOE26:1;
      vuint32_t RFTOE25:1;
      vuint32_t RFTOE24:1;
      vuint32_t RFTOE23:1;
      vuint32_t RFTOE22:1;
      vuint32_t RFTOE21:1;
      vuint32_t RFTOE20:1;
      vuint32_t RFTOE19:1;
      vuint32_t RFTOE18:1;
      vuint32_t RFTOE17:1;
      vuint32_t RFTOE16:1;
      vuint32_t RFTOE15:1;
      vuint32_t RFTOE14:1;
      vuint32_t RFTOE13:1;
      vuint32_t RFTOE12:1;
      vuint32_t RFTOE11:1;
      vuint32_t RFTOE10:1;
      vuint32_t RFTOE9:1;
      vuint32_t RFTOE8:1;
      vuint32_t RFTOE7:1;
      vuint32_t RFTOE6:1;
      vuint32_t RFTOE5:1;
      vuint32_t RFTOE4:1;
      vuint32_t RFTOE3:1;
      vuint32_t RFTOE2:1;
      vuint32_t RFTOE1:1;
      vuint32_t RFTOE0:1;
    } B;
  } RF_TOE[4];

  union {                              /* RF Time-out Register */
    vuint32_t R;
    struct {
      vuint32_t TO:32;
    } B;
  } RF_TO;

  union {                              /* CFG Timeout Register */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t TO:3;
    } B;
  } CFG_TO;

  union {                              /* IO Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t EIN1:1;
      vuint32_t EIN0:1;
      vuint32_t  :2;
      vuint32_t EOUT1:1;
      vuint32_t EOUT0:1;
    } B;
  } EINOUT;

  union {                              /* Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t PhysicErrorPin:2;
      vuint32_t ESTAT:1;
      vuint32_t STATUS:3;
    } B;
  } STAT;

  union {                              /* NA Freeze Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t NAFS:8;
    } B;
  } N2AF_STATUS;

  union {                              /* AF Freeze Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t AF_SRC:2;
      vuint32_t AFFS:8;
    } B;
  } A2FF_STATUS;

  union {                              /* NF Freeze Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t NF_SRC:2;
      vuint32_t NFFS:8;
    } B;
  } N2FF_STATUS;

  union {                              /* FA Freeze Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t FAFS:9;
    } B;
  } F2A_STATUS;

  uint8_t FCCU_reserved3[8];
  union {                              /* RF Fake Register */
    vuint32_t R;
    struct {
      vuint32_t  :25;
      vuint32_t FRFC:7;
    } B;
  } RFF;

  union {                              /* IRQ Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t NMI_STAT:1;
      vuint32_t ALRM_STAT:1;
      vuint32_t CFG_TO_STAT:1;
    } B;
  } IRQ_STAT;

  union {                              /* IRQ Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t  :1;
      vuint32_t  :2;
      vuint32_t CFG_TO_IEN:1;
    } B;
  } IRQ_EN;

  union {                              /* XTMR Register */
    vuint32_t R;
    struct {
      vuint32_t XTMR:32;
    } B;
  } XTMR;

  union {                              /* MCS Register */
    vuint32_t R;
    struct {
      vuint32_t VL3:1;
      vuint32_t FS3:1;
      vuint32_t  :2;
      vuint32_t MCS3:4;
      vuint32_t VL2:1;
      vuint32_t FS2:1;
      vuint32_t  :2;
      vuint32_t MCS2:4;
      vuint32_t VL1:1;
      vuint32_t FS1:1;
      vuint32_t  :2;
      vuint32_t MCS1:4;
      vuint32_t VL0:1;
      vuint32_t FS0:1;
      vuint32_t  :2;
      vuint32_t MCS0:4;
    } B;
  } MCS;

  union {                              /* Transient Lock Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t TRANSKEY:9;
    } B;
  } TRANS_LOCK;

  union {                              /* Permanent Lock Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t PERMNTKEY:9;
    } B;
  } PERMNT_LOCK;

  union {                              /* Delta T Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t  :14;
      vuint32_t  :2;
      vuint32_t DELTA_T:14;
    } B;
  } DELTA_T;

  union {                              /* IRQ Alarm Enable Register */
    vuint32_t R;
    struct {
      vuint32_t IRQEN31:1;
      vuint32_t IRQEN30:1;
      vuint32_t IRQEN29:1;
      vuint32_t IRQEN28:1;
      vuint32_t IRQEN27:1;
      vuint32_t IRQEN26:1;
      vuint32_t IRQEN25:1;
      vuint32_t IRQEN24:1;
      vuint32_t IRQEN23:1;
      vuint32_t IRQEN22:1;
      vuint32_t IRQEN21:1;
      vuint32_t IRQEN20:1;
      vuint32_t IRQEN19:1;
      vuint32_t IRQEN18:1;
      vuint32_t IRQEN17:1;
      vuint32_t IRQEN16:1;
      vuint32_t IRQEN15:1;
      vuint32_t IRQEN14:1;
      vuint32_t IRQEN13:1;
      vuint32_t IRQEN12:1;
      vuint32_t IRQEN11:1;
      vuint32_t IRQEN10:1;
      vuint32_t IRQEN9:1;
      vuint32_t IRQEN8:1;
      vuint32_t IRQEN7:1;
      vuint32_t IRQEN6:1;
      vuint32_t IRQEN5:1;
      vuint32_t IRQEN4:1;
      vuint32_t IRQEN3:1;
      vuint32_t IRQEN2:1;
      vuint32_t IRQEN1:1;
      vuint32_t IRQEN0:1;
    } B;
  } IRQ_ALARM_EN[4];

  union {                              /* NMI Enable Register */
    vuint32_t R;
    struct {
      vuint32_t NMIEN31:1;
      vuint32_t NMIEN30:1;
      vuint32_t NMIEN29:1;
      vuint32_t NMIEN28:1;
      vuint32_t NMIEN27:1;
      vuint32_t NMIEN26:1;
      vuint32_t NMIEN25:1;
      vuint32_t NMIEN24:1;
      vuint32_t NMIEN23:1;
      vuint32_t NMIEN22:1;
      vuint32_t NMIEN21:1;
      vuint32_t NMIEN20:1;
      vuint32_t NMIEN19:1;
      vuint32_t NMIEN18:1;
      vuint32_t NMIEN17:1;
      vuint32_t NMIEN16:1;
      vuint32_t NMIEN15:1;
      vuint32_t NMIEN14:1;
      vuint32_t NMIEN13:1;
      vuint32_t NMIEN12:1;
      vuint32_t NMIEN11:1;
      vuint32_t NMIEN10:1;
      vuint32_t NMIEN9:1;
      vuint32_t NMIEN8:1;
      vuint32_t NMIEN7:1;
      vuint32_t NMIEN6:1;
      vuint32_t NMIEN5:1;
      vuint32_t NMIEN4:1;
      vuint32_t NMIEN3:1;
      vuint32_t NMIEN2:1;
      vuint32_t NMIEN1:1;
      vuint32_t NMIEN0:1;
    } B;
  } NMI_EN[4];

  union {                              /* EOUT Signaling Enable Register */
    vuint32_t R;
    struct {
      vuint32_t EOUTEN31:1;
      vuint32_t EOUTEN30:1;
      vuint32_t EOUTEN29:1;
      vuint32_t EOUTEN28:1;
      vuint32_t EOUTEN27:1;
      vuint32_t EOUTEN26:1;
      vuint32_t EOUTEN25:1;
      vuint32_t EOUTEN24:1;
      vuint32_t EOUTEN23:1;
      vuint32_t EOUTEN22:1;
      vuint32_t EOUTEN21:1;
      vuint32_t EOUTEN20:1;
      vuint32_t EOUTEN19:1;
      vuint32_t EOUTEN18:1;
      vuint32_t EOUTEN17:1;
      vuint32_t EOUTEN16:1;
      vuint32_t EOUTEN15:1;
      vuint32_t EOUTEN14:1;
      vuint32_t EOUTEN13:1;
      vuint32_t EOUTEN12:1;
      vuint32_t EOUTEN11:1;
      vuint32_t EOUTEN10:1;
      vuint32_t EOUTEN9:1;
      vuint32_t EOUTEN8:1;
      vuint32_t EOUTEN7:1;
      vuint32_t EOUTEN6:1;
      vuint32_t EOUTEN5:1;
      vuint32_t EOUTEN4:1;
      vuint32_t EOUTEN3:1;
      vuint32_t EOUTEN2:1;
      vuint32_t EOUTEN1:1;
      vuint32_t EOUTEN0:1;
    } B;
  } EOUT_SIG_EN[4];
};


/* ============================================================================
   =============================== Module: FEC ================================
   ============================================================================ */

struct FEC_tag {
  uint8_t FEC_reserved0[4];
  union {                              /* Interrupt Event Register */
    vuint32_t R;
    struct {
      vuint32_t HBERR:1;
      vuint32_t BABR:1;
      vuint32_t BABT:1;
      vuint32_t GRA:1;
      vuint32_t TXF:1;
      vuint32_t TXB:1;
      vuint32_t RXF:1;
      vuint32_t RXB:1;
      vuint32_t MII:1;
      vuint32_t EBERR:1;
      vuint32_t LC:1;
      vuint32_t RL:1;
      vuint32_t UN:1;
      vuint32_t  :19;
    } B;
  } EIR;

  union {                              /* Interrupt Mask Register */
    vuint32_t R;
    struct {
      vuint32_t HBERR:1;
      vuint32_t BABR:1;
      vuint32_t BABT:1;
      vuint32_t GRA:1;
      vuint32_t TXF:1;
      vuint32_t TXB:1;
      vuint32_t RXF:1;
      vuint32_t RXB:1;
      vuint32_t MII:1;
      vuint32_t EBERR:1;
      vuint32_t LC:1;
      vuint32_t RL:1;
      vuint32_t UN:1;
      vuint32_t  :19;
    } B;
  } EIMR;

  uint8_t FEC_reserved1[4];
  union {                              /* Receive Descriptor Active Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t RDAR:1;
      vuint32_t  :24;
    } B;
  } RDAR;

  union {                              /* Transmit Descriptor Active Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t TDAR:1;
      vuint32_t  :24;
    } B;
  } TDAR;

  uint8_t FEC_reserved2[12];
  union {                              /* Ethernet Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t  :23;
      vuint32_t  :1;
      vuint32_t ETHER_EN:1;
      vuint32_t RESET:1;
    } B;
  } ECR;

  uint8_t FEC_reserved3[24];
  union {                              /* MII Management Frame Register */
    vuint32_t R;
    struct {
      vuint32_t ST:2;
      vuint32_t OP:2;
      vuint32_t PA:5;
      vuint32_t RA:5;
      vuint32_t TA:2;
      vuint32_t DATA:16;
    } B;
  } MMFR;

  union {                              /* MII Speed Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t DIS_PRE:1;
      vuint32_t MII_SPEED:6;
      vuint32_t  :1;
    } B;
  } MSCR;

  uint8_t FEC_reserved4[28];
  union {                              /* MIB Control Register */
    vuint32_t R;
    struct {
      vuint32_t MIB_DIS:1;
      vuint32_t MIB_IDLE:1;
      vuint32_t  :30;
    } B;
  } MIBC;

  uint8_t FEC_reserved5[28];
  union {                              /* Receive Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t MAX_FL:11;
      vuint32_t  :4;
      vuint32_t RMII_ECHO:1;
      vuint32_t RMII_LOOP:1;
      vuint32_t RMII_10T:1;
      vuint32_t RMII_MODE:1;
      vuint32_t  :2;
      vuint32_t FCE:1;
      vuint32_t BC_REJ:1;
      vuint32_t PROM:1;
      vuint32_t MII_MODE:1;
      vuint32_t DRT:1;
      vuint32_t LOOP:1;
    } B;
  } RCR;

  uint8_t FEC_reserved6[60];
  union {                              /* Transmit Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t RFC_PAUSE:1;
      vuint32_t TFC_PAUSE:1;
      vuint32_t FDEN:1;
      vuint32_t HBC:1;
      vuint32_t GTS:1;
    } B;
  } TCR;

  uint8_t FEC_reserved7[28];
  union {                              /* Physical Address Low Register */
    vuint32_t R;
    struct {
      vuint32_t PADDR1:32;
    } B;
  } PALR;

  union {                              /* Physical Address High Register and Type Field */
    vuint32_t R;
    struct {
      vuint32_t PADDR2:16;
      vuint32_t TYPE:16;
    } B;
  } PAUR;

  union {                              /* Opcode/Pause Duration */
    vuint32_t R;
    struct {
      vuint32_t OPCODE:16;
      vuint32_t PAUSE_DUR:16;
    } B;
  } OPD;

  uint8_t FEC_reserved8[40];
  union {                              /* Descriptor Individual Upper Address Register */
    vuint32_t R;
    struct {
      vuint32_t IADDR1:32;
    } B;
  } IAUR;

  union {                              /* Descriptor Individual Lower Address Register */
    vuint32_t R;
    struct {
      vuint32_t IADDR2:32;
    } B;
  } IALR;

  union {                              /* Descriptor Group Upper Address Register */
    vuint32_t R;
    struct {
      vuint32_t GADDR1:32;
    } B;
  } GAUR;

  union {                              /* Descriptor Group Lower Address Register */
    vuint32_t R;
    struct {
      vuint32_t GADDR2:32;
    } B;
  } GALR;

  uint8_t FEC_reserved9[28];
  union {                              /* Transmit FIFO Watermark */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t TFWR:2;
    } B;
  } TFWR;

  uint8_t FEC_reserved10[4];
  union {                              /* FIFO Receive Bound Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t  :1;
      vuint32_t R_BOUND:8;
      vuint32_t  :2;
    } B;
  } FRBR;

  union {                              /* FIFO Receive Start Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t  :1;
      vuint32_t R_FSTART:8;
      vuint32_t  :2;
    } B;
  } FRSR;

  uint8_t FEC_reserved11[44];
  union {                              /* Receive Descriptor Ring Start Register */
    vuint32_t R;
    struct {
      vuint32_t R_DES_START:30;
      vuint32_t  :2;
    } B;
  } ERDSR;

  union {                              /* Transmit Buffer Descriptor Ring Start Register */
    vuint32_t R;
    struct {
      vuint32_t X_DES_START:30;
      vuint32_t  :2;
    } B;
  } ETDSR;

  union {                              /* Receive Buffer Size Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t R_BUF_SIZE:7;
      vuint32_t  :4;
    } B;
  } EMRBR;

  uint8_t FEC_reserved12[116];
  union {                              /* Count of frames not counted correctly */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_DROP:32;
    } B;
  } RMON_T_DROP;

  union {                              /* RMON Tx packet count */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_PACKETS:32;
    } B;
  } RMON_T_PACKETS;

  union {                              /* RMON Tx broadcast packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_BC_PKT:32;
    } B;
  } RMON_T_BC_PKT;

  union {                              /* RMON Tx multicast packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_MC_PKT:32;
    } B;
  } RMON_T_MC_PKT;

  union {                              /* RMON Tx packets with CRC/align error */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_CRC_ALIGN:32;
    } B;
  } RMON_T_CRC_ALIGN;

  union {                              /* RMON Tx packets < 64 bytes, good CRC */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_UNDERSIZE:32;
    } B;
  } RMON_T_UNDERSIZE;

  union {                              /* RMON Tx packets > MAX_FL bytes, good CRC */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_OVERSIZE:32;
    } B;
  } RMON_T_OVERSIZE;

  union {                              /* RMON Tx packets < 64 bytes, bad CRC */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_FRAG:32;
    } B;
  } RMON_T_FRAG;

  union {                              /* RMON Tx packets > MAX_FL bytes, bad CRC */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_JAB:32;
    } B;
  } RMON_T_JAB;

  union {                              /* RMON Tx collision count */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_COL:32;
    } B;
  } RMON_T_COL;

  union {                              /* RMON Tx 64 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_P64:32;
    } B;
  } RMON_T_P64;

  union {                              /* RMON Tx 65 to 127 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_P65TO127:32;
    } B;
  } RMON_T_P65TO127;

  union {                              /* RMON Tx 128 to 255 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_P128TO255:32;
    } B;
  } RMON_T_P128TO255;

  union {                              /* RMON Tx 256 to 511 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_P256TO511:32;
    } B;
  } RMON_T_P256TO511;

  union {                              /* RMON Tx 512 to 1023 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_P512TO1023:32;
    } B;
  } RMON_T_P512TO1023;

  union {                              /* RMON Tx 1024 to 2047 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_P1024TO2047:32;
    } B;
  } RMON_T_P1024TO2047;

  union {                              /* RMON Tx packets with > 2048 bytes */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_P_GTE2048:32;
    } B;
  } RMON_T_P_GTE2048;

  union {                              /* RMON Tx Octets */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_OCTETS:32;
    } B;
  } RMON_T_OCTETS;

  union {                              /* Count of transmitted frames not counted correctly */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_DROP:32;
    } B;
  } IEEE_T_DROP;

  union {                              /* Frames transmitted OK */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_FRAME_OK:32;
    } B;
  } IEEE_T_FRAME_OK;

  union {                              /* Frames transmitted with single collision */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_1COL:32;
    } B;
  } IEEE_T_1COL;

  union {                              /* Frames transmitted with multiple collisions */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_MCOL:32;
    } B;
  } IEEE_T_MCOL;

  union {                              /* Frames transmitted after deferral delay */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_DEF:32;
    } B;
  } IEEE_T_DEF;

  union {                              /* Frames transmitted with late collision */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_LCOL:32;
    } B;
  } IEEE_T_LCOL;

  union {                              /* Frames transmitted with excessive collisions */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_EXCOL:32;
    } B;
  } IEEE_T_EXCOL;

  union {                              /* Frames transmitted with Tx FIFO underrun */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_MACERR:32;
    } B;
  } IEEE_T_MACERR;

  union {                              /* Frames transmitted with carrier sense error */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_CSERR:32;
    } B;
  } IEEE_T_CSERR;

  union {                              /* Frames transmitted with SQE error */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_SQE:32;
    } B;
  } IEEE_T_SQE;

  union {                              /* Flow control pause frames transmitted */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_FDXFC:32;
    } B;
  } IEEE_T_FDXFC;

  union {                              /* Octet count for frames transmitted without error */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_OCTETS_OK:32;
    } B;
  } IEEE_T_OCTETS_OK;

  uint8_t FEC_reserved13[8];
  union {                              /* Count of received frames not counted correctly */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_DROP:32;
    } B;
  } RMON_R_DROP;

  union {                              /* RMON Rx packet count */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_PACKETS:32;
    } B;
  } RMON_R_PACKETS;

  union {                              /* RMON Rx broadcast packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_BC_PKT:32;
    } B;
  } RMON_R_BC_PKT;

  union {                              /* RMON Rx multicast packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_MC_PKT:32;
    } B;
  } RMON_R_MC_PKT;

  union {                              /* RMON Rx packets with CRC/Align error */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_CRC_ALIGN:32;
    } B;
  } RMON_R_CRC_ALIGN;

  union {                              /* RMON Rx packets < 64 bytes, good CRC */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_UNDERSIZE:32;
    } B;
  } RMON_R_UNDERSIZE;

  union {                              /* RMON Rx packets > MAX_FL bytes, good CRC */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_OVERSIZE:32;
    } B;
  } RMON_R_OVERSIZE;

  union {                              /* RMON Rx packets < 64 bytes, bad CRC */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_FRAG:32;
    } B;
  } RMON_R_FRAG;

  union {                              /* RMON Rx packets > MAX_FL bytes, bad CRC */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_JAB:32;
    } B;
  } RMON_R_JAB;

  union {                              /* Reserved */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_RESVD_0:32;
    } B;
  } RMON_R_RESVD_0;

  union {                              /* RMON Rx 64 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_P64:32;
    } B;
  } RMON_R_P64;

  union {                              /* RMON Rx 65 to 127 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_P65TO127:32;
    } B;
  } RMON_R_P65TO127;

  union {                              /* RMON Rx 128 to 255 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_P128TO255:32;
    } B;
  } RMON_R_P128TO255;

  union {                              /* RMON Rx 256 to 511 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_P256TO511:32;
    } B;
  } RMON_R_P256TO511;

  union {                              /* RMON Rx 512 to 1023 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_P512TO1023:32;
    } B;
  } RMON_R_P512TO1023;

  union {                              /* RMON Rx 1024 to 2047 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_P1024TO2047:32;
    } B;
  } RMON_R_P1024TO2047;

  union {                              /* RMON Rx packets with > 2048 bytes */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_P_GTE2048:32;
    } B;
  } RMON_R_P_GTE2048;

  union {                              /* RMON Rx octets */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_OCTETS:32;
    } B;
  } RMON_R_OCTETS;

  union {                              /* Count of received frames not counted correctly */
    vuint32_t R;
    struct {
      vuint32_t IEEE_R_DROP:32;
    } B;
  } IEEE_R_DROP;

  union {                              /* Frames received OK */
    vuint32_t R;
    struct {
      vuint32_t IEEE_R_FRAME_OK:32;
    } B;
  } IEEE_R_FRAME_OK;

  union {                              /* Frames received with CRC error */
    vuint32_t R;
    struct {
      vuint32_t IEEE_R_CRC:32;
    } B;
  } IEEE_R_CRC;

  union {                              /* Frames received with alignment error */
    vuint32_t R;
    struct {
      vuint32_t IEEE_R_ALIGN:32;
    } B;
  } IEEE_R_ALIGN;

  union {                              /* Receive FIFO overflow count */
    vuint32_t R;
    struct {
      vuint32_t IEEE_R_MACERR:32;
    } B;
  } IEEE_R_MACERR;

  union {                              /* Flow control pause frames received */
    vuint32_t R;
    struct {
      vuint32_t IEEE_R_FDXFC:32;
    } B;
  } IEEE_R_FDXFC;

  union {                              /* Octet count for frames received without error */
    vuint32_t R;
    struct {
      vuint32_t IEEE_R_OCTETS_OK:32;
    } B;
  } IEEE_R_OCTETS_OK;
};


/* ============================================================================
   =============================== Module: FR =================================
   ============================================================================ */

struct FR_tag {
  union {                              /* Module Version Register */
    vuint16_t R;
    struct {
      vuint16_t CHIVER:8;
      vuint16_t PEVER:8;
    } B;
  } MVR;

  union {                              /* Module Configuration Register */
    vuint16_t R;
    struct {
      vuint16_t MEN:1;
      vuint16_t SBFF:1;                /* System Bus Failure Freeze */
      vuint16_t SCM:1;
      vuint16_t CHB:1;
      vuint16_t CHA:1;
      vuint16_t SFFE:1;
      vuint16_t ECCE:1;
      vuint16_t  :1;                   /* Reserved bit, will not be changed. Application must not write any value different from the reset value. */
      vuint16_t FUM:1;
      vuint16_t FAM:1;
      vuint16_t  :1;
      vuint16_t CLKSEL:1;
      vuint16_t BITRATE:3;
      vuint16_t  :1;
    } B;
  } MCR;

  union {                              /* System Memory Base Address High Register */
    vuint16_t R;
    struct {
      vuint16_t SMBA:16;               /* System Memory Base Address high. This is the value of the system memory base address for the individual message buffers and sync frame table. This is the value of the system memory base address for the receive FIFO if the FIFO address mode bit FR_MCR[FAM] is set to 1. It is defines as a byte address. */
    } B;
  } SYMBADHR;

  union {                              /* System Memory Base Address Low Register */
    vuint16_t R;
    struct {
      vuint16_t SMBA:12;
      vuint16_t  :4;
    } B;
  } SYMBADLR;

  union {                              /* Strobe Signal Control Register */
    vuint16_t R;
    struct {
      vuint16_t WMD:1;
      vuint16_t  :3;
      vuint16_t SEL:4;
      vuint16_t  :3;
      vuint16_t ENB:1;
      vuint16_t  :2;
      vuint16_t STBPSEL:2;
    } B;
  } STBSCR;

  uint8_t FR_reserved0[2];
  union {                              /* Message Buffer Data Size Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t MBSEG2DS:7;
      vuint16_t  :1;
      vuint16_t MBSEG1DS:7;
    } B;
  } MBDSR;

  union {                              /* Message Buffer Segment Size and Utilization Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t LAST_MB_SEG1:7;
      vuint16_t  :1;
      vuint16_t LAST_MB_UTIL:7;
    } B;
  } MBSSUTR;

  union {                              /* PE DRAM Access Register */
    vuint16_t R;
    struct {
      vuint16_t INST:4;
      vuint16_t ADDR:11;
      vuint16_t DAD:1;
    } B;
  } PEDRAR;

  union {                              /* PE DRAM Data Register */
    vuint16_t R;
    struct {
      vuint16_t DATA:16;
    } B;
  } PEDRDR;

  union {                              /* Protocol Operation Control Register */
    vuint16_t R;
    struct {
      vuint16_t WME:1;
      vuint16_t  :3;
      vuint16_t EOC_AP:2;
      vuint16_t ERC_AP:2;
      vuint16_t BSY_WMC:1;
      vuint16_t  :3;
      vuint16_t POCCMD:4;
    } B;
  } POCR;

  union {                              /* Global Interrupt Flag and Enable Register */
    vuint16_t R;
    struct {
      vuint16_t MIF:1;
      vuint16_t PRIF:1;
      vuint16_t CHIF:1;
      vuint16_t WUPIF:1;
      vuint16_t FAFBIF:1;
      vuint16_t FAFAIF:1;
      vuint16_t RBIF:1;
      vuint16_t TBIF:1;
      vuint16_t MIE:1;
      vuint16_t PRIE:1;
      vuint16_t CHIE:1;
      vuint16_t WUPIE:1;
      vuint16_t FAFBIE:1;
      vuint16_t FAFAIE:1;
      vuint16_t RBIE:1;
      vuint16_t TBIE:1;
    } B;
  } GIFER;

  union {                              /* Protocol Interrupt Flag Register 0 */
    vuint16_t R;
    struct {
      vuint16_t FATL_IF:1;
      vuint16_t INTL_IF:1;
      vuint16_t ILCF_IF:1;
      vuint16_t CSA_IF:1;
      vuint16_t MRC_IF:1;
      vuint16_t MOC_IF:1;
      vuint16_t CCL_IF:1;
      vuint16_t MXS_IF:1;
      vuint16_t MTX_IF:1;
      vuint16_t LTXB_IF:1;
      vuint16_t LTXA_IF:1;
      vuint16_t TBVB_IF:1;
      vuint16_t TBVA_IF:1;
      vuint16_t TI2_IF:1;
      vuint16_t TI1_IF:1;
      vuint16_t CYS_IF:1;
    } B;
  } PIFR0;

  union {                              /* Protocol Interrupt Flag Register 1 */
    vuint16_t R;
    struct {
      vuint16_t EMC_IF:1;
      vuint16_t IPC_IF:1;
      vuint16_t PECF_IF:1;
      vuint16_t PSC_IF:1;
      vuint16_t SSI3_IF:1;
      vuint16_t SSI2_IF:1;
      vuint16_t SSI1_IF:1;
      vuint16_t SSI0_IF:1;
      vuint16_t  :2;
      vuint16_t EVT_IF:1;
      vuint16_t ODT_IF:1;
      vuint16_t  :4;
    } B;
  } PIFR1;

  union {                              /* Protocol Interrupt Enable Register 0 */
    vuint16_t R;
    struct {
      vuint16_t FATL_IE:1;
      vuint16_t INTL_IE:1;
      vuint16_t ILCF_IE:1;
      vuint16_t CSA_IE:1;
      vuint16_t MRC_IE:1;
      vuint16_t MOC_IE:1;
      vuint16_t CCL_IE:1;
      vuint16_t MXS_IE:1;
      vuint16_t MTX_IE:1;
      vuint16_t LTXB_IE:1;
      vuint16_t LTXA_IE:1;
      vuint16_t TBVB_IE:1;
      vuint16_t TBVA_IE:1;
      vuint16_t TI2_IE:1;
      vuint16_t TI1_IE:1;
      vuint16_t CYS_IE:1;
    } B;
  } PIER0;

  union {                              /* Protocol Interrupt Enable Register 1 */
    vuint16_t R;
    struct {
      vuint16_t EMC_IE:1;
      vuint16_t IPC_IE:1;
      vuint16_t PECF_IE:1;
      vuint16_t PSC_IE:1;
      vuint16_t SSI3_IE:1;
      vuint16_t SSI2_IE:1;
      vuint16_t SSI1_IE:1;
      vuint16_t SSI0_IE:1;
      vuint16_t  :2;
      vuint16_t EVT_IE:1;
      vuint16_t ODT_IE:1;
      vuint16_t  :4;
    } B;
  } PIER1;

  union {                              /* CHI Error Flag Register */
    vuint16_t R;
    struct {
      vuint16_t FRLB_EF:1;
      vuint16_t FRLA_EF:1;
      vuint16_t PCMI_EF:1;
      vuint16_t FOVB_EF:1;
      vuint16_t FOVA_EF:1;
      vuint16_t MBS_EF:1;
      vuint16_t MBU_EF:1;
      vuint16_t LCK_EF:1;
      vuint16_t  :1;
      vuint16_t SBCF_EF:1;
      vuint16_t FID_EF:1;
      vuint16_t DPL_EF:1;
      vuint16_t SPL_EF:1;
      vuint16_t NML_EF:1;
      vuint16_t NMF_EF:1;
      vuint16_t ILSA_EF:1;
    } B;
  } CHIERFR;

  union {                              /* Message Buffer Interrupt Vector Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t TBIVEC:7;
      vuint16_t  :1;
      vuint16_t RBIVEC:7;
    } B;
  } MBIVEC;

  union {                              /* Channel A Status Error Counter Register */
    vuint16_t R;
    struct {
      vuint16_t CHAERSCNT:16;
    } B;
  } CASERCR;

  union {                              /* Channel B Status Error Counter Register */
    vuint16_t R;
    struct {
      vuint16_t CHBERSCNT:16;
    } B;
  } CBSERCR;

  union {                              /* Protocol Status Register 0 */
    vuint16_t R;
    struct {
      vuint16_t ERRMODE:2;
      vuint16_t SLOTMODE:2;
      vuint16_t  :1;
      vuint16_t PROTSTATE:3;
      vuint16_t STARTUPSTATE:4;
      vuint16_t  :1;
      vuint16_t WAKEUPSTATUS:3;
    } B;
  } PSR0;

  union {                              /* Protocol Status Register 1 */
    vuint16_t R;
    struct {
      vuint16_t CSAA:1;
      vuint16_t CSP:1;
      vuint16_t  :1;
      vuint16_t REMCSAT:5;
      vuint16_t CPN:1;
      vuint16_t HHR:1;
      vuint16_t FRZ:1;
      vuint16_t APTAC:5;
    } B;
  } PSR1;

  union {                              /* Protocol Status Register 2 */
    vuint16_t R;
    struct {
      vuint16_t NBVB:1;
      vuint16_t NSEB:1;
      vuint16_t STCB:1;
      vuint16_t SBVB:1;
      vuint16_t SSEB:1;
      vuint16_t MTB:1;
      vuint16_t NBVA:1;
      vuint16_t NSEA:1;
      vuint16_t STCA:1;
      vuint16_t SBVA:1;
      vuint16_t SSEA:1;
      vuint16_t MTA:1;
      vuint16_t CKCORFCNT:4;
    } B;
  } PSR2;

  union {                              /* Protocol Status Register 3 */
    vuint16_t R;
    struct {
      vuint16_t  :2;
      vuint16_t WUB:1;
      vuint16_t ABVB:1;
      vuint16_t AACB:1;
      vuint16_t ACEB:1;
      vuint16_t ASEB:1;
      vuint16_t AVFB:1;
      vuint16_t  :2;
      vuint16_t WUA:1;
      vuint16_t ABVA:1;
      vuint16_t AACA:1;
      vuint16_t ACEA:1;
      vuint16_t ASEA:1;
      vuint16_t AVFA:1;
    } B;
  } PSR3;

  union {                              /* Macrotick Counter Register */
    vuint16_t R;
    struct {
      vuint16_t  :2;
      vuint16_t MTCT:14;
    } B;
  } MTCTR;

  union {                              /* Cycle Counter Register */
    vuint16_t R;
    struct {
      vuint16_t  :10;
      vuint16_t CYCCNT:6;
    } B;
  } CYCTR;

  union {                              /* Slot Counter Channel A Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t SLOTCNTA:11;
    } B;
  } SLTCTAR;

  union {                              /* Slot Counter Channel B Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t SLOTCNTB:11;
    } B;
  } SLTCTBR;

  union {                              /* Rate Correction Value Register */
    vuint16_t R;
    struct {
      vuint16_t RATECORR:16;
    } B;
  } RTCORVR;

  union {                              /* Offset Correction Value Register */
    vuint16_t R;
    struct {
      vuint16_t OFFSETCORR:16;
    } B;
  } OFCORVR;

  union {                              /* Combined Interrupt Flag Register */
    vuint16_t R;
    struct {
      vuint16_t  :8;
      vuint16_t MIF:1;
      vuint16_t PRIF:1;
      vuint16_t CHIF:1;
      vuint16_t WUPIF:1;
      vuint16_t FAFBIF:1;
      vuint16_t FAFAIF:1;
      vuint16_t RBIF:1;
      vuint16_t TBIF:1;
    } B;
  } CIFR;

  union {                              /* System Memory Access Time-Out Register */
    vuint16_t R;
    struct {
      vuint16_t  :8;
      vuint16_t TIMEOUT:8;
    } B;
  } SYMATOR;

  union {                              /* Sync Frame Counter Register */
    vuint16_t R;
    struct {
      vuint16_t SFEVB:4;
      vuint16_t SFEVA:4;
      vuint16_t SFODB:4;
      vuint16_t SFODA:4;
    } B;
  } SFCNTR;

  union {                              /* Sync Frame Table Offset Register */
    vuint16_t R;
    struct {
      vuint16_t SFT_OFFSET:15;
      vuint16_t  :1;
    } B;
  } SFTOR;

  union {                              /* Sync Frame Table Configuration, Control, Status Register */
    vuint16_t R;
    struct {
      vuint16_t ELKT:1;
      vuint16_t OLKT:1;
      vuint16_t CYCNUM:6;
      vuint16_t ELKS:1;
      vuint16_t OLKS:1;
      vuint16_t EVAL:1;
      vuint16_t OVAL:1;
      vuint16_t  :1;
      vuint16_t OPT:1;
      vuint16_t SDVEN:1;
      vuint16_t SIDEN:1;
    } B;
  } SFTCCSR;

  union {                              /* Sync Frame ID Rejection Filter Register */
    vuint16_t R;
    struct {
      vuint16_t  :6;
      vuint16_t SYNFRID:10;
    } B;
  } SFIDRFR;

  union {                              /* Sync Frame ID Acceptance Filter Value Register */
    vuint16_t R;
    struct {
      vuint16_t  :6;
      vuint16_t FVAL:10;
    } B;
  } SFIDAFVR;

  union {                              /* Sync Frame ID Acceptance Filter Mask Register */
    vuint16_t R;
    struct {
      vuint16_t  :6;
      vuint16_t FMSK:10;
    } B;
  } SFIDAFMR;

  union {                              /* Network Management Vector Register */
    vuint16_t R;
    struct {
      vuint16_t NMVP:16;
    } B;
  } NMVR[6];

  union {                              /* Network Management Vector Length Register */
    vuint16_t R;
    struct {
      vuint16_t  :12;
      vuint16_t NMVL:4;
    } B;
  } NMVLR;

  union {                              /* Timer Configuration and Control Register */
    vuint16_t R;
    struct {
      vuint16_t  :2;
      vuint16_t T2_CFG:1;
      vuint16_t T2_REP:1;
      vuint16_t  :1;
      vuint16_t T2SP:1;
      vuint16_t T2TR:1;
      vuint16_t T2ST:1;
      vuint16_t  :3;
      vuint16_t T1_REP:1;
      vuint16_t  :1;
      vuint16_t T1SP:1;
      vuint16_t T1TR:1;
      vuint16_t T1ST:1;
    } B;
  } TICCR;

  union {                              /* Timer 1 Cycle Set Register */
    vuint16_t R;
    struct {
      vuint16_t  :2;
      vuint16_t T1_CYC_VAL:6;
      vuint16_t  :2;
      vuint16_t T1_CYC_MSK:6;
    } B;
  } TI1CYSR;

  union {                              /* Timer 1 Macrotick Offset Register */
    vuint16_t R;
    struct {
      vuint16_t  :2;
      vuint16_t T1_MTOFFSET:14;
    } B;
  } TI1MTOR;

  union {
    union {                            /* Timer 2 Configuration Register 0 (Absolute Timer Configuration) */
      vuint16_t R;
      struct {
        vuint16_t  :2;
        vuint16_t T2CYCVAL:6;          /* Timer T2 Cycle Filter Mask */
        vuint16_t  :2;
        vuint16_t T2CYCMSK:6;          /* Timer T2 Cycle Filter Mask */
      } B;
    } ABS;
    union {                            /* Timer 2 Configuration Register 0 (Relative Timer Configuration) */
      vuint16_t R;
      struct {
        vuint16_t T2MTCNT:16;          /* Timer T2 Macrotick High Word */
      } B;
    } REL;
  } TI2CR0;

  union {
    union {                            /* Timer 2 Configuration Register 1 (Absolute Timer Configuration) */
      vuint16_t R;
      struct {
        vuint16_t  :2;
        vuint16_t T2MOFF:14;           /* Timer T2 Macrotick Offset */
      } B;
    } ABS;
    union {                            /* Timer 2 Configuration Register 1 (Relative Timer Configuration) */
      vuint16_t R;
      struct {
        vuint16_t T2MTCNT:16;
      } B;
    } REL;
  } TI2CR1;

  union {                              /* Slot Status Selection Register */
    vuint16_t R;
    struct {
      vuint16_t WMD:1;
      vuint16_t  :1;
      vuint16_t SEL:2;
      vuint16_t  :1;
      vuint16_t SLOTNUMBER:11;
    } B;
  } SSSR;

  union {                              /* Slot Status Counter Condition Register */
    vuint16_t R;
    struct {
      vuint16_t WMD:1;
      vuint16_t  :1;
      vuint16_t SEL:2;
      vuint16_t  :1;
      vuint16_t CNTCFG:2;
      vuint16_t MCY:1;
      vuint16_t VFR:1;
      vuint16_t SYF:1;
      vuint16_t NUF:1;
      vuint16_t SUF:1;
      vuint16_t STATUSMASK:4;
    } B;
  } SSCCR;

  union {                              /* Slot Status Register */
    vuint16_t R;
    struct {
      vuint16_t VFB:1;
      vuint16_t SYB:1;
      vuint16_t NFB:1;
      vuint16_t SUB:1;
      vuint16_t SEB:1;
      vuint16_t CEB:1;
      vuint16_t BVB:1;
      vuint16_t TCB:1;
      vuint16_t VFA:1;
      vuint16_t SYA:1;
      vuint16_t NFA:1;
      vuint16_t SUA:1;
      vuint16_t SEA:1;
      vuint16_t CEA:1;
      vuint16_t BVA:1;
      vuint16_t TCA:1;
    } B;
  } SSR[8];

  union {                              /* Slot Status Counter Register */
    vuint16_t R;
    struct {
      vuint16_t SLOTSTATUSCNT:16;
    } B;
  } SSCR[4];

  union {                              /* MTS A Configuration Register */
    vuint16_t R;
    struct {
      vuint16_t MTE:1;
      vuint16_t  :1;
      vuint16_t CYCCNTMSK:6;
      vuint16_t  :2;
      vuint16_t CYCCNTVAL:6;
    } B;
  } MTSACFR;

  union {                              /* MTS B Configuration Register */
    vuint16_t R;
    struct {
      vuint16_t MTE:1;
      vuint16_t  :1;
      vuint16_t CYCCNTMSK:6;
      vuint16_t  :2;
      vuint16_t CYCCNTVAL:6;
    } B;
  } MTSBCFR;

  union {                              /* Receive Shadow Buffer Index Register */
    vuint16_t R;
    struct {
      vuint16_t WMD:1;
      vuint16_t  :1;
      vuint16_t SEL:2;
      vuint16_t  :4;
      vuint16_t RSBIDX:8;              /* RSBIDXA1/RSBIDXA2/RSBIDXB1/RSBIDXB2- Receive Shadow Buffer Index */
    } B;
  } RSBIR;

  union {                              /* Receive FIFO Watermark and Selection Register */
    vuint16_t R;
    struct {
      vuint16_t WM:8;                  /* WMA/WMB - Watermark */
      vuint16_t  :7;
      vuint16_t SEL:1;
    } B;
  } RFWMSR;

  union {                              /* Receive FIFO Start Index Register */
    vuint16_t R;
    struct {
      vuint16_t  :6;
      vuint16_t SIDX:10;               /* SIDXA/SIDXB - Start Index */
    } B;
  } RFSIR;

  union {                              /* Receive FIFO Depth and Size Register */
    vuint16_t R;
    struct {
      vuint16_t FIFO_DEPTH:8;          /* FIFO_DEPTHA/FIFO_DEPTHB - FIFO Depth */
      vuint16_t  :1;
      vuint16_t ENTRY_SIZE:7;          /* ENTRY_SIZEA/ENTRY_SIZEB - Entry Size */
    } B;
  } RFDSR;

  union {                              /* Receive FIFO A Read Index Register */
    vuint16_t R;
    struct {
      vuint16_t  :6;
      vuint16_t RDIDX:10;
    } B;
  } RFARIR;

  union {                              /* Receive FIFO B Read Index Register */
    vuint16_t R;
    struct {
      vuint16_t  :6;
      vuint16_t RDIDX:10;
    } B;
  } RFBRIR;

  union {                              /* Receive FIFO Message ID Acceptance Filter Value Register */
    vuint16_t R;
    struct {
      vuint16_t MIDAFVAL:16;           /* MIDAFVALA/MIDAFVALB - Message ID Acceptance Filter Value */
    } B;
  } RFMIDAFVR;

  union {                              /* Receive FIFO Message ID Acceptance Filter Mask Register */
    vuint16_t R;
    struct {
      vuint16_t MIDAFMSK:16;           /* MIDAFMSKA/MIDAFMSKB - Message ID Acceptance Filter Mask */
    } B;
  } RFMIDAFMR;

  union {                              /* Receive FIFO Frame ID Rejection Filter Value Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t FIDRFVAL:11;           /* FIDRFVALA/FIDRFVALB - Frame ID Rejection Filter Value */
    } B;
  } RFFIDRFVR;

  union {                              /* Receive FIFO Frame ID Rejection Filter Mask Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t FIDRFMSK:11;
    } B;
  } RFFIDRFMR;

  union {                              /* Receive FIFO Range Filter Configuration Register */
    vuint16_t R;
    struct {
      vuint16_t WMD:1;
      vuint16_t IBD:1;
      vuint16_t SEL:2;
      vuint16_t  :1;
      vuint16_t SID:11;                /* Slot ID */
    } B;
  } RFRFCFR;

  union {                              /* Receive FIFO Range Filter Control Register */
    vuint16_t R;
    struct {
      vuint16_t  :4;
      vuint16_t F3MD:1;
      vuint16_t F2MD:1;
      vuint16_t F1MD:1;
      vuint16_t F0MD:1;
      vuint16_t  :4;
      vuint16_t F3EN:1;
      vuint16_t F2EN:1;
      vuint16_t F1EN:1;
      vuint16_t F0EN:1;
    } B;
  } RFRFCTR;

  union {                              /* Last Dynamic Transmit Slot Channel A Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t LDYNTXSLOTA:11;
    } B;
  } LDTXSLAR;

  union {                              /* Last Dynamic Transmit Slot Channel B Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t LDYNTXSLOTB:11;
    } B;
  } LDTXSLBR;

  union {                              /* Protocol Configuration Register 0 */
    vuint16_t R;
    struct {
      vuint16_t action_point_offset:6;
      vuint16_t static_slot_length:10;
    } B;
  } PCR0;

  union {                              /* Protocol Configuration Register 1 */
    vuint16_t R;
    struct {
      vuint16_t  :2;
      vuint16_t macro_after_first_static_slot:14;
    } B;
  } PCR1;

  union {                              /* Protocol Configuration Register 2 */
    vuint16_t R;
    struct {
      vuint16_t minislot_after_action_point:6;
      vuint16_t number_of_static_slots:10; /* gNumberOfStaticSlots */
    } B;
  } PCR2;

  union {                              /* Protocol Configuration Register 3 */
    vuint16_t R;
    struct {
      vuint16_t wakeup_symbol_rx_low:6;
      vuint16_t minislot_action_point_offset:5;
      vuint16_t coldstart_attempts:5;
    } B;
  } PCR3;

  union {                              /* Protocol Configuration Register 4 */
    vuint16_t R;
    struct {
      vuint16_t cas_rx_low_max:7;
      vuint16_t wakeup_symbol_rx_window:9;
    } B;
  } PCR4;

  union {                              /* Protocol Configuration Register 5 */
    vuint16_t R;
    struct {
      vuint16_t tss_transmitter:4;
      vuint16_t wakeup_symbol_tx_low:6;
      vuint16_t wakeup_symbol_rx_idle:6;
    } B;
  } PCR5;

  union {                              /* Protocol Configuration Register 6 */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t symbol_window_after_action_point:8;
      vuint16_t macro_initial_offset_a:7;
    } B;
  } PCR6;

  union {                              /* Protocol Configuration Register 7 */
    vuint16_t R;
    struct {
      vuint16_t decoding_correction_b:9;
      vuint16_t micro_per_macro_nom_half:7;
    } B;
  } PCR7;

  union {                              /* Protocol Configuration Register 8 */
    vuint16_t R;
    struct {
      vuint16_t max_without_clock_correction_fatal:4;
      vuint16_t max_without_clock_correction_passive:4;
      vuint16_t wakeup_symbol_tx_idle:8;
    } B;
  } PCR8;

  union {                              /* Protocol Configuration Register 9 */
    vuint16_t R;
    struct {
      vuint16_t minislot_exists:1;
      vuint16_t symbol_window_exists:1;
      vuint16_t offset_correction_out:14;
    } B;
  } PCR9;

  union {                              /* Protocol Configuration Register 10 */
    vuint16_t R;
    struct {
      vuint16_t single_slot_enabled:1;
      vuint16_t wakeup_channel:1;
      vuint16_t macro_per_cycle:14;
    } B;
  } PCR10;

  union {                              /* Protocol Configuration Register 11 */
    vuint16_t R;
    struct {
      vuint16_t key_slot_used_for_startup:1;
      vuint16_t key_slot_used_for_sync:1;
      vuint16_t offset_correction_start:14;
    } B;
  } PCR11;

  union {                              /* Protocol Configuration Register 12 */
    vuint16_t R;
    struct {
      vuint16_t allow_passive_to_active:5;
      vuint16_t key_slot_header_crc:11;
    } B;
  } PCR12;

  union {                              /* Protocol Configuration Register 13 */
    vuint16_t R;
    struct {
      vuint16_t first_minislot_action_point_offset:6;
      vuint16_t static_slot_after_action_point:10;
    } B;
  } PCR13;

  union {                              /* Protocol Configuration Register 14 */
    vuint16_t R;
    struct {
      vuint16_t rate_correction_out:11;
      vuint16_t listen_timeout:5;
    } B;
  } PCR14;

  union {                              /* Protocol Configuration Register 15 */
    vuint16_t R;
    struct {
      vuint16_t listen_timeout:16;
    } B;
  } PCR15;

  union {                              /* Protocol Configuration Register 16 */
    vuint16_t R;
    struct {
      vuint16_t macro_initial_offset_b:7;
      vuint16_t noise_listen_timeout:9;
    } B;
  } PCR16;

  union {                              /* Protocol Configuration Register 17 */
    vuint16_t R;
    struct {
      vuint16_t noise_listen_timeout:16;
    } B;
  } PCR17;

  union {                              /* Protocol Configuration Register 18 */
    vuint16_t R;
    struct {
      vuint16_t wakeup_pattern:6;
      vuint16_t key_slot_id:10;
    } B;
  } PCR18;

  union {                              /* Protocol Configuration Register 19 */
    vuint16_t R;
    struct {
      vuint16_t decoding_correction_a:9;
      vuint16_t payload_length_static:7;
    } B;
  } PCR19;

  union {                              /* Protocol Configuration Register 20 */
    vuint16_t R;
    struct {
      vuint16_t micro_initial_offset_b:8;
      vuint16_t micro_initial_offset_a:8;
    } B;
  } PCR20;

  union {                              /* Protocol Configuration Register 21 */
    vuint16_t R;
    struct {
      vuint16_t extern_rate_correction:3;
      vuint16_t latest_tx:13;
    } B;
  } PCR21;

  union {                              /* Protocol Configuration Register 22 */
    vuint16_t R;
    struct {
      vuint16_t  :1;                   /* Reserved bit, will not be changed. Application must not write any value different from the reset value. */
      vuint16_t comp_accepted_startup_range_a:11;
      vuint16_t micro_per_cycle:4;
    } B;
  } PCR22;

  union {                              /* Protocol Configuration Register 23 */
    vuint16_t R;
    struct {
      vuint16_t micro_per_cycle:16;
    } B;
  } PCR23;

  union {                              /* Protocol Configuration Register 24 */
    vuint16_t R;
    struct {
      vuint16_t cluster_drift_damping:5;
      vuint16_t max_payload_length_dynamic:7;
      vuint16_t micro_per_cycle_min:4;
    } B;
  } PCR24;

  union {                              /* Protocol Configuration Register 25 */
    vuint16_t R;
    struct {
      vuint16_t micro_per_cycle_min:16;
    } B;
  } PCR25;

  union {                              /* Protocol Configuration Register 26 */
    vuint16_t R;
    struct {
      vuint16_t allow_halt_due_to_clock:1;
      vuint16_t comp_accepted_startup_range_b:11;
      vuint16_t micro_per_cycle_max:4;
    } B;
  } PCR26;

  union {                              /* Protocol Configuration Register 27 */
    vuint16_t R;
    struct {
      vuint16_t micro_per_cycle_max:16;
    } B;
  } PCR27;

  union {                              /* Protocol Configuration Register 28 */
    vuint16_t R;
    struct {
      vuint16_t dynamic_slot_idle_phase:2;
      vuint16_t macro_after_offset_correction:14;
    } B;
  } PCR28;

  union {                              /* Protocol Configuration Register 29 */
    vuint16_t R;
    struct {
      vuint16_t extern_offset_correction:3;
      vuint16_t minislots_max:13;
    } B;
  } PCR29;

  union {                              /* Protocol Configuration Register 30 */
    vuint16_t R;
    struct {
      vuint16_t  :12;
      vuint16_t sync_node_max:4;
    } B;
  } PCR30;

  union {                              /* StopWatch Count Register */
    vuint16_t R;
    struct {
      vuint16_t STPW:16;               /* StopWatch Count Register */
    } B;
  } STPWR;

  uint8_t FR_reserved1[2];
  union {                              /* Protocol Event Output Enable and StopWatch Control Register */
    vuint16_t R;
    struct {
      vuint16_t  :7;
      vuint16_t STPW_EN:1;             /* Stopwatch count Enable */
      vuint16_t  :5;
      vuint16_t TIM2_EE:1;
      vuint16_t TIM1_EE:1;
      vuint16_t CYC_EE:1;
    } B;
  } PEOER;

  uint8_t FR_reserved2[2];
  union {                              /* Receive FIFO Start Data Offset Register */
    vuint16_t R;
    struct {
      vuint16_t SDO:16;                /* SDOA/SDOB - Start Data Field Offset */
    } B;
  } RFSDOR;

  union {                              /* Receive FIFO System Memory Base Address High Register */
    vuint16_t R;
    struct {
      vuint16_t SMBA:16;
    } B;
  } RFSYMBADHR;

  union {                              /* Receive FIFO System Memory Base Address Low Register */
    vuint16_t R;
    struct {
      vuint16_t SMBA:12;
      vuint16_t  :4;
    } B;
  } RFSYMBADLR;

  union {                              /* Receive FIFO Periodic Timer Register */
    vuint16_t R;
    struct {
      vuint16_t  :2;
      vuint16_t PTD:14;
    } B;
  } RFPTR;

  union {                              /* Receive FIFO Fill Level and POP Count Register */
    vuint16_t R;
    struct {
      vuint16_t FLB_or_PCB:8;
      vuint16_t FLA_or_PCA:8;
    } B;
  } RFFLPCR;

  union {                              /* ECC Error Interrupt Flag and Enable Register */
    vuint16_t R;
    struct {
      vuint16_t LRNE_OF:1;
      vuint16_t LRCE_OF:1;
      vuint16_t DRNE_OF:1;
      vuint16_t DRCE_OF:1;
      vuint16_t LRNE_IF:1;
      vuint16_t LRCE_IF:1;
      vuint16_t DRNE_IF:1;
      vuint16_t DRCE_IF:1;
      vuint16_t  :4;
      vuint16_t LRNE_IE:1;
      vuint16_t LRCE_IE:1;
      vuint16_t DRNE_IE:1;
      vuint16_t DRCE_IE:1;
    } B;
  } EEIFER;

  union {                              /* ECC Error Report and Injection Control Register */
    vuint16_t R;
    struct {
      vuint16_t BSY:1;
      vuint16_t  :5;
      vuint16_t ERS:2;
      vuint16_t  :3;
      vuint16_t ERM:1;
      vuint16_t  :2;
      vuint16_t EIM:1;
      vuint16_t EIE:1;
    } B;
  } EERICR;

  union {                              /* ECC Error Report Address Register */
    vuint16_t R;
    struct {
      vuint16_t MID:1;
      vuint16_t BANK:3;
      vuint16_t ADDR:12;
    } B;
  } EERAR;

  union {                              /* ECC Error Report Data Register */
    vuint16_t R;
    struct {
      vuint16_t DATA:16;
    } B;
  } EERDR;

  union {                              /* ECC Error Report Code Register */
    vuint16_t R;
    struct {
      vuint16_t  :11;
      vuint16_t CODE:5;
    } B;
  } EERCR;

  union {                              /* ECC Error Injection Address Register */
    vuint16_t R;
    struct {
      vuint16_t MID:1;
      vuint16_t BANK:3;
      vuint16_t ADDR:12;
    } B;
  } EEIAR;

  union {                              /* ECC Error Injection Data Register */
    vuint16_t R;
    struct {
      vuint16_t DATA:16;
    } B;
  } EEIDR;

  union {                              /* ECC Error Injection Code Register */
    vuint16_t R;
    struct {
      vuint16_t  :11;
      vuint16_t CODE:5;
    } B;
  } EEICR;

  uint8_t FR_reserved3[1792];
  struct {
    union {                            /* Message Buffer Configuration, Control, Status Register */
      vuint16_t R;
      struct {
        vuint16_t  :3;
        vuint16_t MTD:1;
        vuint16_t CMT:1;
        vuint16_t EDT:1;
        vuint16_t LCKT:1;
        vuint16_t MBIE:1;
        vuint16_t  :3;
        vuint16_t DUP:1;
        vuint16_t DVAL:1;
        vuint16_t EDS:1;
        vuint16_t LCKS:1;
        vuint16_t MBIF:1;
      } B;
    } CCSR;
    union {                            /* Message Buffer Cycle Counter Filter Register */
      vuint16_t R;
      struct {
        vuint16_t MTM:1;
        vuint16_t CHA:1;
        vuint16_t CHB:1;
        vuint16_t CCFE:1;
        vuint16_t CCFMSK:6;
        vuint16_t CCFVAL:6;
      } B;
    } CCFR;
    union {                            /* Message Buffer Frame ID Register */
      vuint16_t R;
      struct {
        vuint16_t  :5;
        vuint16_t FID:11;
      } B;
    } FIDR;
    union {                            /* Message Buffer Index Register */
      vuint16_t R;
      struct {
        vuint16_t  :8;
        vuint16_t MBIDX:8;
      } B;
    } IDXR;
  } MB[128];

  uint8_t FR_reserved4[1024];
  union {                              /* Message Buffer Data Field Offset Register */
    vuint16_t R;
    struct {
      vuint16_t MBDO:16;
    } B;
  } MBDOR[132];

  union {                              /* LRAM ECC Error Test Register */
    vuint16_t R;
    struct {
      vuint16_t LEETD:16;
    } B;
  } LEETR[6];
};


/* ============================================================================
   =============================== Module: GTM ================================
   ============================================================================ */

struct GTM_tag {
  union {                              /* GTM Revision Register */
    vuint32_t R;
    struct {
      vuint32_t DEV_CODE2:4;           /* Device encoding digit 2. */
      vuint32_t DEV_CODE1:4;           /* Device encoding digit 1. */
      vuint32_t DEV_CODE0:4;           /* Device encoding digit 0. */
      vuint32_t MAJOR:4;               /* Major version number */
      vuint32_t MINOR:4;               /* Minor version number */
      vuint32_t NO:4;                  /* Delivery number. */
      vuint32_t STEP:8;                /* Release step. */
    } B;
  } REV;

  union {                              /* GTM Reset Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t RST:1;                 /* GTM Reset. */
    } B;
  } RST;

  union {                              /* GTM Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;                  /* Read as zero, should be written as zero. */
      vuint32_t TO_VAL:5;              /* AEI Timeout value. */
      vuint32_t  :2;                   /* Read as zero, should be written as zero. */
      vuint32_t TO_MODE:1;             /* AEI Timeout mode. */
      vuint32_t RF_PROT:1;             /* RST and FORCINT protection. */
    } B;
  } CTRL;

  union {                              /* GTM AEI Address Pointer Register */
    vuint32_t R;
    struct {
      vuint32_t  :11;
      vuint32_t TO_W1R0:1;             /* AEI Timeout Read/Write flag. */
      vuint32_t TO_ADDR:20;            /* AEI Timeout address. */
    } B;
  } AEI_ADDR_XPT;

  union {                              /* GTM Interrupt Request Notification Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t AEI_USP_BE:1;          /* AEI Unsupported byte enable interrupt. */
      vuint32_t AEI_IM_ADDR:1;         /* AEI Illegal Module address interrupt. */
      vuint32_t AEI_USP_ADDR:1;        /* AEI Unsupported address interrupt. */
      vuint32_t AEI_TO_XPT:1;          /* AEI Timeout exception occurred. */
    } B;
  } IRQ_NOTIFY;

  union {                              /* GTM Interrupt Request Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t AEI_USP_BE_IRQ_EN:1;   /* AEI Unsupported Byte Enable Interrupt Enable. */
      vuint32_t AEI_IM_ADDR_IRQ_EN:1;  /* AEI Illegal Module Address Interrupt Enable. */
      vuint32_t AEI_USP_ADDR_IRQ_EN:1; /* AEI Unsupported Address Interrupt Enable. */
      vuint32_t AEI_TO_XPT_IRQ_EN:1;   /* AEI Timeout Exception Interrupt Enable. */
    } B;
  } IRQ_EN;

  union {                              /* GTM Force Interrupt Request Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t TRG_AEI_USP_BE:1;      /* Trigger AEI_USP_BE_IRQ interrupt by software. */
      vuint32_t TRG_AEI_IM_ADDR:1;     /* Trigger AEI_IM_ADDR_IRQ interrupt by software. */
      vuint32_t TRG_AEI_USP_ADDR:1;    /* Trigger AEI_USP_ADDR_IRQ interrupt by software. */
      vuint32_t TRG_AEI_TO_XPT:1;      /* Trigger AEI_TO_XPT_IRQ interrupt by software. */
    } B;
  } IRQ_FORCINT;

  union {                              /* GTM Interrupt Request Mode Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Read as zero, should be written as zero. */
      vuint32_t IRQ_MODE:2;            /* Interrupt strategy mode selection for the AEI timeout and address monitoring interrupts. */
    } B;
  } IRQ_MODE;

  union {                              /* GTM Error Interrupt Request Enable register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t AEI_USP_BE_EIRQ_EN:1;  /* AEI_USP_BE_EIRQ error interrupt enable. */
      vuint32_t AEI_IM_ADDR_EIRQ_EN:1; /* AEI_IM_ADDR_EIRQ error interrupt enable. */
      vuint32_t AEI_USP_ADDR_EIRQ_EN:1; /* AEI_USP_ADDR_EIRQ error interrupt enable. */
      vuint32_t AEI_TO_XPT_EIRQ_EN:1;  /* AEI_TO_XPT_EIRQ error interrupt enable. */
    } B;
  } EIRQ_EN;

  uint8_t GTM_reserved0[12];
  union {                              /* GTM Bridge Mode Register */
    vuint32_t R;
    struct {
      vuint32_t BUFF_DPT:8;            /* Buffer depth of AEI bridge. */
      vuint32_t  :7;
      vuint32_t BRG_RST:1;             /* Bridge software reset. */
      vuint32_t  :3;
      vuint32_t SYNC_INPUT_REG:1;      /* Additional pipelined stage in synchronous bridge mode. */
      vuint32_t  :2;
      vuint32_t BUFF_OVL:1;            /* Buffer overflow register. */
      vuint32_t MODE_UP_PGR:1;         /* Mode update in progress. */
      vuint32_t  :6;
      vuint32_t MSK_WR_RSP:1;          /* Mask write response. */
      vuint32_t BRG_MODE:1;            /* Defines the operation mode for the AEI bridge. */
    } B;
  } BRIDGE_MODE;

  union {                              /* GTM Bridge Pointer 1 Register */
    vuint32_t R;
    struct {
      vuint32_t RSP_TRAN_RDY:6;        /* Response transactions ready. */
      vuint32_t FBC:6;                 /* Free buffer count. */
      vuint32_t ABT_TRAN_PGR:5;        /* Aborted transaction in progress pointer. */
      vuint32_t TRAN_IN_PGR:5;         /* Transaction in progress pointer (acquire). */
      vuint32_t FIRST_RSP_PTR:5;       /* First response pointer. */
      vuint32_t NEW_TRAN_PTR:5;        /* New transaction pointer. */
    } B;
  } BRIDGE_PTR1;

  union {                              /* GTM Bridge Pointer 2 Register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t TRAN_IN_PGR2:5;        /* Transaction in progress pointer (aquire2). */
    } B;
  } BRIDGE_PTR2;

  uint8_t GTM_reserved1[4];
  union {                              /* GTM TIM0 Auxiliary Input Source register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t SRC_CH7:1;             /* Defines AUX_IN source of TIM[i] channel 7. */
      vuint32_t SRC_CH6:1;             /* Defines AUX_IN source of TIM[i] channel 6. */
      vuint32_t SRC_CH5:1;             /* Defines AUX_IN source of TIM[i] channel 5. */
      vuint32_t SRC_CH4:1;             /* Defines AUX_IN source of TIM[i] channel 4. */
      vuint32_t SRC_CH3:1;             /* Defines AUX_IN source of TIM[i] channel 3. */
      vuint32_t SRC_CH2:1;             /* Defines AUX_IN source of TIM[i] channel 2. */
      vuint32_t SRC_CH1:1;             /* Defines AUX_IN source of TIM[i] channel 1. */
      vuint32_t SRC_CH0:1;             /* Defines AUX_IN source of TIM[i] channel 0. */
    } B;
  } TIM0_AUX_IN_SRC;

  union {                              /* GTM TIM1 Auxiliary Input Source register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t SRC_CH7:1;             /* Defines AUX_IN source of TIM[i] channel 7. */
      vuint32_t SRC_CH6:1;             /* Defines AUX_IN source of TIM[i] channel 6. */
      vuint32_t SRC_CH5:1;             /* Defines AUX_IN source of TIM[i] channel 5. */
      vuint32_t SRC_CH4:1;             /* Defines AUX_IN source of TIM[i] channel 4. */
      vuint32_t SRC_CH3:1;             /* Defines AUX_IN source of TIM[i] channel 3. */
      vuint32_t SRC_CH2:1;             /* Defines AUX_IN source of TIM[i] channel 2. */
      vuint32_t SRC_CH1:1;             /* Defines AUX_IN source of TIM[i] channel 1. */
      vuint32_t SRC_CH0:1;             /* Defines AUX_IN source of TIM[i] channel 0. */
    } B;
  } TIM1_AUX_IN_SRC;

  union {                              /* GTM TIM2 Auxiliary Input Source register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t SRC_CH7:1;             /* Defines AUX_IN source of TIM[i] channel 7. */
      vuint32_t SRC_CH6:1;             /* Defines AUX_IN source of TIM[i] channel 6. */
      vuint32_t SRC_CH5:1;             /* Defines AUX_IN source of TIM[i] channel 5. */
      vuint32_t SRC_CH4:1;             /* Defines AUX_IN source of TIM[i] channel 4. */
      vuint32_t SRC_CH3:1;             /* Defines AUX_IN source of TIM[i] channel 3. */
      vuint32_t SRC_CH2:1;             /* Defines AUX_IN source of TIM[i] channel 2. */
      vuint32_t SRC_CH1:1;             /* Defines AUX_IN source of TIM[i] channel 1. */
      vuint32_t SRC_CH0:1;             /* Defines AUX_IN source of TIM[i] channel 0. */
    } B;
  } TIM2_AUX_IN_SRC;

  union {                              /* GTM TIM3 Auxiliary Input Source register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t SRC_CH7:1;             /* Defines AUX_IN source of TIM[i] channel 7. */
      vuint32_t SRC_CH6:1;             /* Defines AUX_IN source of TIM[i] channel 6. */
      vuint32_t SRC_CH5:1;             /* Defines AUX_IN source of TIM[i] channel 5. */
      vuint32_t SRC_CH4:1;             /* Defines AUX_IN source of TIM[i] channel 4. */
      vuint32_t SRC_CH3:1;             /* Defines AUX_IN source of TIM[i] channel 3. */
      vuint32_t SRC_CH2:1;             /* Defines AUX_IN source of TIM[i] channel 2. */
      vuint32_t SRC_CH1:1;             /* Defines AUX_IN source of TIM[i] channel 1. */
      vuint32_t SRC_CH0:1;             /* Defines AUX_IN source of TIM[i] channel 0. */
    } B;
  } TIM3_AUX_IN_SRC;

  union {                              /* GTM TIM4 Auxiliary Input Source register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t SRC_CH7:1;             /* Defines AUX_IN source of TIM[i] channel 7. */
      vuint32_t SRC_CH6:1;             /* Defines AUX_IN source of TIM[i] channel 6. */
      vuint32_t SRC_CH5:1;             /* Defines AUX_IN source of TIM[i] channel 5. */
      vuint32_t SRC_CH4:1;             /* Defines AUX_IN source of TIM[i] channel 4. */
      vuint32_t SRC_CH3:1;             /* Defines AUX_IN source of TIM[i] channel 3. */
      vuint32_t SRC_CH2:1;             /* Defines AUX_IN source of TIM[i] channel 2. */
      vuint32_t SRC_CH1:1;             /* Defines AUX_IN source of TIM[i] channel 1. */
      vuint32_t SRC_CH0:1;             /* Defines AUX_IN source of TIM[i] channel 0. */
    } B;
  } TIM4_AUX_IN_SRC;

  union {                              /* GTM TIM5 Auxiliary Input Source register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t SRC_CH7:1;             /* Defines AUX_IN source of TIM[i] channel 7. */
      vuint32_t SRC_CH6:1;             /* Defines AUX_IN source of TIM[i] channel 6. */
      vuint32_t SRC_CH5:1;             /* Defines AUX_IN source of TIM[i] channel 5. */
      vuint32_t SRC_CH4:1;             /* Defines AUX_IN source of TIM[i] channel 4. */
      vuint32_t SRC_CH3:1;             /* Defines AUX_IN source of TIM[i] channel 3. */
      vuint32_t SRC_CH2:1;             /* Defines AUX_IN source of TIM[i] channel 2. */
      vuint32_t SRC_CH1:1;             /* Defines AUX_IN source of TIM[i] channel 1. */
      vuint32_t SRC_CH0:1;             /* Defines AUX_IN source of TIM[i] channel 0. */
    } B;
  } TIM5_AUX_IN_SRC;
};


/* ============================================================================
   =============================== Module: GTMINT =============================
   ============================================================================ */

struct GTMINT_tag {
  uint8_t GTMINT_reserved0[192];
  union {                              /* GTM Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t MDIS:1;                /* [BLG_GTMW_007] [Covers: Saf1461] MDIS [end] Module Disable. */
      vuint32_t  :13;
      vuint32_t AEISREN:1;             /* [BLG_GTMW_007] [Covers: Saf1461] Saf1276 - Safety-critical AEISREN [end] AEI interface soft-reset control enable. */
      vuint32_t  :1;
      vuint32_t STPS:1;                /* [BLG_GTMW_007] [Covers: Saf1461] STPS [end] Stop Mode Status. */
      vuint32_t  :14;
    } B;
  } GTMMCR;

  uint8_t GTMINT_reserved1[4];
  union {                              /* GTM Interrupts Clear Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t INTCLR_PTR:10;         /* [BLG_GTMW_007] [Covers: Saf1461] INTCLR_PTR [end] Interrupt Clear Pointer. */
    } B;
  } GTMINTCLR;

  union {                              /* GTM AEI Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t AEISRST:1;             /* [BLG_GTMW_007] [Covers: Saf1461] AEISRST [end] AEI interface soft-reset control. */
    } B;
  } GTMAEICR;
};


/* ============================================================================
   =============================== Module: GTM_AFD ============================
   ============================================================================ */

struct GTM_AFD_tag {
  struct {
    union {                            /* AFD FIFO Channel n Buffer Access Register, n=0:7 */
      vuint32_t R;
      struct {
        vuint32_t  :3;
        vuint32_t DATA:29;             /* Read/write data from/to FIFO. */
      } B;
    } BUF_ACC;
    uint8_t CH_reserved0[12];
  } CH[8];
};


/* ============================================================================
   =============================== Module: GTM_ARU ============================
   ============================================================================ */

struct GTM_ARU_tag {
  union {                              /* ARU Access Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t WREQ:1;                /* Initiate write request. */
      vuint32_t RREQ:1;                /* Initiate read request. */
      vuint32_t  :3;
      vuint32_t ADDR:9;                /* ARU address. */
    } B;
  } ACCESS;

  union {                              /* ARU Data High Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t DATA:29;               /* Upper ARU data word. */
    } B;
  } DATA_H;

  union {                              /* ARU Data Low Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t DATA:29;               /* Lower ARU data word. */
    } B;
  } DATA_L;

  union {                              /* ARU Debug Access 0 Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t ADDR:9;                /* ARU debugging address. */
    } B;
  } DBG_ACCESS0;

  union {                              /* ARU Debug Data 0 High Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t DATA:29;               /* Upper debug data word. */
    } B;
  } DBG_DATA0_H;

  union {                              /* ARU Debug Data 0 Low Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t DATA:29;               /* Lower debug data word. */
    } B;
  } DBG_DATA0_L;

  union {                              /* ARU Debug Access 1 Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t ADDR:9;                /* ARU debugging address. */
    } B;
  } DBG_ACCESS1;

  union {                              /* ARU Debug Data 1 High */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t DATA:29;               /* Upper debug data word */
    } B;
  } DBG_DATA1_H;

  union {                              /* ARU Debug Data 1 Low Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t DATA:29;               /* Lower debug data word. */
    } B;
  } DBG_DATA1_L;

  union {                              /* ARU Interrupt Request Notification Register */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t ACC_ACK:1;             /* On read access data valid, AEI to ARU access is complete. */
      vuint32_t NEW_DATA1:1;           /* Data was transferred for address ARU_DBG_ACCESS1. */
      vuint32_t NEW_DATA0:1;           /* Data was transferred for address ARU_DBG_ACCESS0. */
    } B;
  } IRQ_NOTIFY;

  union {                              /* ARU Interrupt Request Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t ACC_ACK_IRQ_EN:1;      /* ACC_ACK_IRQ interrupt enable. */
      vuint32_t NEW_DATA1_IRQ_EN:1;    /* ARU_NEW_DATA1_IRQ interrupt enable. */
      vuint32_t NEW_DATA0_IRQ_EN:1;    /* ARU_NEW_DATA0_IRQ interrupt enable. */
    } B;
  } IRQ_EN;

  union {                              /* ARU Force Interrupt Request Register */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t TRG_ACC_ACK:1;         /* Trigger ACC_ACK interrupt. */
      vuint32_t TRG_NEW_DATA1:1;       /* Trigger new data 1 interrupt. */
      vuint32_t TRG_NEW_DATA0:1;       /* Trigger new data 0 interrupt. */
    } B;
  } IRQ_FORCINT;

  union {                              /* ARU Interrupt Request Mode Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t IRQ_MODE:2;            /* IRQ mode select. */
    } B;
  } IRQ_MODE;
};


/* ============================================================================
   =============================== Module: GTM_ATOM ===========================
   ============================================================================ */

struct GTM_ATOM_tag {
  union {                              /* ATOM Channel n Read Address Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t RDADDR1:9;             /* ARU Read address 1. */
      vuint32_t  :7;
      vuint32_t RDADDR0:9;             /* ARU Read address 0. */
    } B;
  } CH0_RDADDR;

  union {                              /* ATOM Channel n Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t ABM:1;                 /* ARU blocking mode. */
      vuint32_t OSM:1;                 /* One-shot mode. */
      vuint32_t SLA:1;                 /* Serve last ARU communication strategy */
      vuint32_t TRIGOUT:1;             /* NTrigger output selection (output signal TRIG_CHn) of module ATOM_CHn. */
      vuint32_t  :3;                   /* Reads as zero, should be written as zero. */
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :3;
      vuint32_t WR_REQ:1;              /* CPU Write request bit for late compare register update. */
      vuint32_t  :1;
      vuint32_t CLK_SRC_SR:3;          /* Actual CMU clock source (SOMS) / shadow register for CMU clock source (SOMP). */
      vuint32_t SL:1;                  /* Initial signal level after channel enable. */
      vuint32_t  :1;
      vuint32_t CMP_CTRL:1;            /* CCUn compare strategy select.. */
      vuint32_t ACB:5;                 /* ATOM Mode control bits. */
      vuint32_t ARU_EN:1;              /* ARU Input stream enable. */
      vuint32_t TB12_SEL:1;            /* Select time base value TBU_TS1 or TBU_TS2. */
      vuint32_t MODE:2;                /* ATOM channel mode select. */
    } B;
  } CH0_CTRL;

  union {                              /* ATOM Channel n Shadow 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SR0:24;                /* ATOM channel n shadow register SR0. */
    } B;
  } CH0_SR0;

  union {                              /* ATOM Channel n Shadow 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SR1:24;                /* ATOM channel n shadow register SR1. */
    } B;
  } CH0_SR1;

  union {                              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CM0:24;                /* ATOM CCU0 compare register. */
    } B;
  } CH0_CM0;

  union {                              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CM1:24;                /* ATOM CCU1 compare register. */
    } B;
  } CH0_CM1;

  union {                              /* ATOM Channel n Counter 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CN0:24;                /* ATOM CCU0 counter register. */
    } B;
  } CH0_CN0;

  union {                              /* ATOM Channel n Status Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t ACBO:5;                /* ATOM Internal status bits. */
      vuint32_t  :1;
      vuint32_t WRF:1;                 /* Write request of CPU failed for late update. */
      vuint32_t DV:1;                  /* Valid ARU Data stored in compare registers. */
      vuint32_t ACBI:5;                /* ATOM Mode control bits received through ARU. */
      vuint32_t  :15;
      vuint32_t OL:1;                  /* Actual output signal level of ATOM_CHn_OUT. */
    } B;
  } CH0_STAT;

  union {                              /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH0_IRQ_NOTIFY;

  union {                              /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t CCU1TC_IRQ_EN:1;       /* ATOM_CCU1TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* ATOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH0_IRQ_EN;

  union {                              /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t TRG_CCU1TC:1;          /* Trigger ATOM_CCU1TC_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC:1;          /* Trigger ATOM_CCU0TC_IRQ interrupt by software. */
    } B;
  } CH0_IRQ_FORCINT;

  union {                              /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH0_IRQ_MODE;

  uint8_t ATOM_reserved0[16];
  union {                              /* ATOM AGC Global Control Register */
    vuint32_t R;
    struct {
      vuint32_t UPEN_CTRL7:2;          /* For channel 7, ATOM channel enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL6:2;          /* For channel 6, ATOM channel enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL5:2;          /* For channel 5, ATOM channel enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL4:2;          /* For channel 4, ATOM channel enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL3:2;          /* For channel 3, ATOM channel enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL2:2;          /* For channel 2, ATOM channel enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL1:2;          /* For channel 1, ATOM channel enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL0:2;          /* For channel 0, ATOM channel enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t RST_CH7:1;             /* See RST_CH0 */
      vuint32_t RST_CH6:1;             /* See RST_CH0 */
      vuint32_t RST_CH5:1;             /* See RST_CH0 */
      vuint32_t RST_CH4:1;             /* See RST_CH0 */
      vuint32_t RST_CH3:1;             /* See RST_CH0 */
      vuint32_t RST_CH2:1;             /* See RST_CH0 */
      vuint32_t RST_CH1:1;             /* See RST_CH0 */
      vuint32_t RST_CH0:1;             /* Software reset of corresponding channel 0. */
      vuint32_t  :7;
      vuint32_t HOST_TRIG:1;           /* Trigger request signal (see AGC) to update the register ENDIS_STAT and OUTEN_STAT. */
    } B;
  } AGC_GLB_CTRL;

  union {                              /* ATOM TGC0 Enable/Disable Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t ENDIS_CTRL7:2;         /* Channel 7 enable/disable update value. */
      vuint32_t ENDIS_CTRL6:2;         /* Channel 6 enable/disable update value. */
      vuint32_t ENDIS_CTRL5:2;         /* Channel 5 enable/disable update value. */
      vuint32_t ENDIS_CTRL4:2;         /* TOM channel 4 enable/disable update value. */
      vuint32_t ENDIS_CTRL3:2;         /* TOM channel 3 enable/disable update value. */
      vuint32_t ENDIS_CTRL2:2;         /* TOM channel 2 enable/disable update value. */
      vuint32_t ENDIS_CTRL1:2;         /* TOM channel 1 enable/disable update value. */
      vuint32_t ENDIS_CTRL0:2;         /* TOM channel 0 enable/disable update value. */
    } B;
  } AGC_ENDIS_CTRL;

  union {                              /* ATOM TGC0 Enable/Disable Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t ENDIS_STAT7:2;         /* TOM channel 7 enable/disable. */
      vuint32_t ENDIS_STAT6:2;         /* TOM channel 6 enable/disable. */
      vuint32_t ENDIS_STAT5:2;         /* TOM channel 5 enable/disable. */
      vuint32_t ENDIS_STAT4:2;         /* TOM channel 4 enable/disable. */
      vuint32_t ENDIS_STAT3:2;         /* TOM channel 3 enable/disable. */
      vuint32_t ENDIS_STAT2:2;         /* TOM channel 2 enable/disable. */
      vuint32_t ENDIS_STAT1:2;         /* TOM channel 1 enable/disable. */
      vuint32_t ENDIS_STAT0:2;         /* TOM channel 0 enable/disable. */
    } B;
  } AGC_ENDIS_STAT;

  union {                              /* ATOM TGC0 Action Time Base Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t TBU_SEL:2;             /* Selection of time base used for comparison. */
      vuint32_t TB_TRIG:1;             /* Set trigger request. */
      vuint32_t ACT_TB:24;             /* Specifies the signed compare value with selected signal TBU_TS[n], x=0..2. */
    } B;
  } AGC_ACT_TB;

  union {                              /* ATOM TGC0 Out Enable Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t OUTEN_CTRL7:2;         /* Output TOM_OUT(7) enable/disable update value. */
      vuint32_t OUTEN_CTRL6:2;         /* Output TOM_OUT(6) enable/disable update value. */
      vuint32_t OUTEN_CTRL5:2;         /* Output TOM_OUT(5) enable/disable update value. */
      vuint32_t OUTEN_CTRL4:2;         /* Output TOM_OUT(4) enable/disable update value. */
      vuint32_t OUTEN_CTRL3:2;         /* Output TOM_OUT(3) enable/disable update value. */
      vuint32_t OUTEN_CTRL2:2;         /* Output TOM_OUT(2) enable/disable update value. */
      vuint32_t OUTEN_CTRL1:2;         /* Output TOM_OUT(1) enable/disable update value. */
      vuint32_t OUTEN_CTRL0:2;         /* Output TOM_OUT(0) enable/disable update value. */
    } B;
  } AGC_OUTEN_CTRL;

  union {                              /* ATOM TGC0 Out Enable Control/Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t OUTEN_STAT7:2;         /* Control/status of output TOM_OUT(7). */
      vuint32_t OUTEN_STAT6:2;         /* Control/status of output TOM_OUT(6). */
      vuint32_t OUTEN_STAT5:2;         /* Control/status of output TOM_OUT(5). */
      vuint32_t OUTEN_STAT4:2;         /* Control/status of output TOM_OUT(4) */
      vuint32_t OUTEN_STAT3:2;         /* Control/status of output TOM_OUT(3). */
      vuint32_t OUTEN_STAT2:2;         /* Control/status of output TOM_OUT(2). */
      vuint32_t OUTEN_STAT1:2;         /* Control/status of output TOM_OUT(1). */
      vuint32_t OUTEN_STAT0:2;         /* Control/status of output TOM_OUT(0). */
    } B;
  } AGC_OUTEN_STAT;

  union {                              /* ATOM TGC0 Force Update Control Register */
    vuint32_t R;
    struct {
      vuint32_t RSTCN0_CH7:2;          /* Reset CN0 of channel 7 on force update event. */
      vuint32_t RSTCN0_CH6:2;          /* Reset CN0 of channel 6 on force update event. */
      vuint32_t RSTCN0_CH5:2;          /* Reset CN0 of channel 5 on force update event. */
      vuint32_t RSTCN0_CH4:2;          /* Reset CN0 of channel 4 on force update event. */
      vuint32_t RSTCN0_CH3:2;          /* Reset CN0 of channel 3 on force update event. */
      vuint32_t RSTCN0_CH2:2;          /* Reset CN0 of channel 2 on force update event. */
      vuint32_t RSTCN0_CH1:2;          /* Reset CN0 of channel 1 on force update event. */
      vuint32_t RSTCN0_CH0:2;          /* Reset CN0 of channel 0 on force update event. */
      vuint32_t FUPD_CTRL7:2;          /* Force update of TOM channel 7 operation registers. */
      vuint32_t FUPD_CTRL6:2;          /* Force update of TOM channel 6 operation registers, */
      vuint32_t FUPD_CTRL5:2;          /* Force update of TOM channel 5 operation registers. */
      vuint32_t FUPD_CTRL4:2;          /* Force update of TOM channel 4 operation registers. */
      vuint32_t FUPD_CTRL3:2;          /* Force update of TOM channel 3 operation registers. */
      vuint32_t FUPD_CTRL2:2;          /* ce update of TOM channel 2 operation registers. */
      vuint32_t FUPD_CTRL1:2;          /* Force update of TOM channel 1 operation registers. */
      vuint32_t FUPD_CTRL0:2;          /* Force update of TOM channel 0 operation registers. */
    } B;
  } AGC_FUPD_CTRL;

  union {                              /* ATOM TGC0 Interrupt Trigger Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t INT_TRIG7:2;           /* Select input signal TRIG_7 as a trigger source. */
      vuint32_t INT_TRIG6:2;           /* Select input signal TRIG_6 as a trigger source. */
      vuint32_t INT_TRIG5:2;           /* Select input signal TRIG_5 as a trigger source. */
      vuint32_t INT_TRIG4:2;           /* Select input signal TRIG_4 as a trigger source. */
      vuint32_t INT_TRIG3:2;           /* Select input signal TRIG_3 as a trigger source. */
      vuint32_t INT_TRIG2:2;           /* Select input signal TRIG_2 as a trigger source. */
      vuint32_t INT_TRIG1:2;           /* Select input signal TRIG_1 as a trigger source. */
      vuint32_t INT_TRIG0:2;           /* Select input signal TRIG_0 as a trigger source. */
    } B;
  } AGC_INT_TRIG;

  uint8_t ATOM_reserved1[32];
  union {                              /* ATOM Channel n Read Address Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t RDADDR1:9;             /* ARU Read address 1. */
      vuint32_t  :7;
      vuint32_t RDADDR0:9;             /* ARU Read address 0. */
    } B;
  } CH1_RDADDR;

  union {                              /* ATOM Channel n Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t ABM:1;                 /* ARU blocking mode. */
      vuint32_t OSM:1;                 /* One-shot mode. */
      vuint32_t SLA:1;                 /* Serve last ARU communication strategy */
      vuint32_t TRIGOUT:1;             /* NTrigger output selection (output signal TRIG_CHn) of module ATOM_CHn. */
      vuint32_t  :3;                   /* Reads as zero, should be written as zero. */
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :3;
      vuint32_t WR_REQ:1;              /* CPU Write request bit for late compare register update. */
      vuint32_t  :1;
      vuint32_t CLK_SRC_SR:3;          /* Actual CMU clock source (SOMS) / shadow register for CMU clock source (SOMP). */
      vuint32_t SL:1;                  /* Initial signal level after channel enable. */
      vuint32_t  :1;
      vuint32_t CMP_CTRL:1;            /* CCUn compare strategy select.. */
      vuint32_t ACB:5;                 /* ATOM Mode control bits. */
      vuint32_t ARU_EN:1;              /* ARU Input stream enable. */
      vuint32_t TB12_SEL:1;            /* Select time base value TBU_TS1 or TBU_TS2. */
      vuint32_t MODE:2;                /* ATOM channel mode select. */
    } B;
  } CH1_CTRL;

  union {                              /* ATOM Channel n Shadow 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SR0:24;                /* ATOM channel n shadow register SR0. */
    } B;
  } CH1_SR0;

  union {                              /* ATOM Channel n Shadow 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SR1:24;                /* ATOM channel n shadow register SR1. */
    } B;
  } CH1_SR1;

  union {                              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CM0:24;                /* ATOM CCU0 compare register. */
    } B;
  } CH1_CM0;

  union {                              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CM1:24;                /* ATOM CCU1 compare register. */
    } B;
  } CH1_CM1;

  union {                              /* ATOM Channel n Counter 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CN0:24;                /* ATOM CCU0 counter register. */
    } B;
  } CH1_CN0;

  union {                              /* ATOM Channel n Status Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t ACBO:5;                /* ATOM Internal status bits. */
      vuint32_t  :1;
      vuint32_t WRF:1;                 /* Write request of CPU failed for late update. */
      vuint32_t DV:1;                  /* Valid ARU Data stored in compare registers. */
      vuint32_t ACBI:5;                /* ATOM Mode control bits received through ARU. */
      vuint32_t  :15;
      vuint32_t OL:1;                  /* Actual output signal level of ATOM_CHn_OUT. */
    } B;
  } CH1_STAT;

  union {                              /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH1_IRQ_NOTIFY;

  union {                              /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t CCU1TC_IRQ_EN:1;       /* ATOM_CCU1TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* ATOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH1_IRQ_EN;

  union {                              /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t TRG_CCU1TC:1;          /* Trigger ATOM_CCU1TC_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC:1;          /* Trigger ATOM_CCU0TC_IRQ interrupt by software. */
    } B;
  } CH1_IRQ_FORCINT;

  union {                              /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH1_IRQ_MODE;

  uint8_t ATOM_reserved2[80];
  union {                              /* ATOM Channel n Read Address Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t RDADDR1:9;             /* ARU Read address 1. */
      vuint32_t  :7;
      vuint32_t RDADDR0:9;             /* ARU Read address 0. */
    } B;
  } CH2_RDADDR;

  union {                              /* ATOM Channel n Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t ABM:1;                 /* ARU blocking mode. */
      vuint32_t OSM:1;                 /* One-shot mode. */
      vuint32_t SLA:1;                 /* Serve last ARU communication strategy */
      vuint32_t TRIGOUT:1;             /* NTrigger output selection (output signal TRIG_CHn) of module ATOM_CHn. */
      vuint32_t  :3;                   /* Reads as zero, should be written as zero. */
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :3;
      vuint32_t WR_REQ:1;              /* CPU Write request bit for late compare register update. */
      vuint32_t  :1;
      vuint32_t CLK_SRC_SR:3;          /* Actual CMU clock source (SOMS) / shadow register for CMU clock source (SOMP). */
      vuint32_t SL:1;                  /* Initial signal level after channel enable. */
      vuint32_t  :1;
      vuint32_t CMP_CTRL:1;            /* CCUn compare strategy select.. */
      vuint32_t ACB:5;                 /* ATOM Mode control bits. */
      vuint32_t ARU_EN:1;              /* ARU Input stream enable. */
      vuint32_t TB12_SEL:1;            /* Select time base value TBU_TS1 or TBU_TS2. */
      vuint32_t MODE:2;                /* ATOM channel mode select. */
    } B;
  } CH2_CTRL;

  union {                              /* ATOM Channel n Shadow 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SR0:24;                /* ATOM channel n shadow register SR0. */
    } B;
  } CH2_SR0;

  union {                              /* ATOM Channel n Shadow 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SR1:24;                /* ATOM channel n shadow register SR1. */
    } B;
  } CH2_SR1;

  union {                              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CM0:24;                /* ATOM CCU0 compare register. */
    } B;
  } CH2_CM0;

  union {                              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CM1:24;                /* ATOM CCU1 compare register. */
    } B;
  } CH2_CM1;

  union {                              /* ATOM Channel n Counter 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CN0:24;                /* ATOM CCU0 counter register. */
    } B;
  } CH2_CN0;

  union {                              /* ATOM Channel n Status Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t ACBO:5;                /* ATOM Internal status bits. */
      vuint32_t  :1;
      vuint32_t WRF:1;                 /* Write request of CPU failed for late update. */
      vuint32_t DV:1;                  /* Valid ARU Data stored in compare registers. */
      vuint32_t ACBI:5;                /* ATOM Mode control bits received through ARU. */
      vuint32_t  :15;
      vuint32_t OL:1;                  /* Actual output signal level of ATOM_CHn_OUT. */
    } B;
  } CH2_STAT;

  union {                              /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH2_IRQ_NOTIFY;

  union {                              /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t CCU1TC_IRQ_EN:1;       /* ATOM_CCU1TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* ATOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH2_IRQ_EN;

  union {                              /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t TRG_CCU1TC:1;          /* Trigger ATOM_CCU1TC_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC:1;          /* Trigger ATOM_CCU0TC_IRQ interrupt by software. */
    } B;
  } CH2_IRQ_FORCINT;

  union {                              /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH2_IRQ_MODE;

  uint8_t ATOM_reserved3[80];
  union {                              /* ATOM Channel n Read Address Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t RDADDR1:9;             /* ARU Read address 1. */
      vuint32_t  :7;
      vuint32_t RDADDR0:9;             /* ARU Read address 0. */
    } B;
  } CH3_RDADDR;

  union {                              /* ATOM Channel n Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t ABM:1;                 /* ARU blocking mode. */
      vuint32_t OSM:1;                 /* One-shot mode. */
      vuint32_t SLA:1;                 /* Serve last ARU communication strategy */
      vuint32_t TRIGOUT:1;             /* NTrigger output selection (output signal TRIG_CHn) of module ATOM_CHn. */
      vuint32_t  :3;                   /* Reads as zero, should be written as zero. */
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :3;
      vuint32_t WR_REQ:1;              /* CPU Write request bit for late compare register update. */
      vuint32_t  :1;
      vuint32_t CLK_SRC_SR:3;          /* Actual CMU clock source (SOMS) / shadow register for CMU clock source (SOMP). */
      vuint32_t SL:1;                  /* Initial signal level after channel enable. */
      vuint32_t  :1;
      vuint32_t CMP_CTRL:1;            /* CCUn compare strategy select.. */
      vuint32_t ACB:5;                 /* ATOM Mode control bits. */
      vuint32_t ARU_EN:1;              /* ARU Input stream enable. */
      vuint32_t TB12_SEL:1;            /* Select time base value TBU_TS1 or TBU_TS2. */
      vuint32_t MODE:2;                /* ATOM channel mode select. */
    } B;
  } CH3_CTRL;

  union {                              /* ATOM Channel n Shadow 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SR0:24;                /* ATOM channel n shadow register SR0. */
    } B;
  } CH3_SR0;

  union {                              /* ATOM Channel n Shadow 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SR1:24;                /* ATOM channel n shadow register SR1. */
    } B;
  } CH3_SR1;

  union {                              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CM0:24;                /* ATOM CCU0 compare register. */
    } B;
  } CH3_CM0;

  union {                              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CM1:24;                /* ATOM CCU1 compare register. */
    } B;
  } CH3_CM1;

  union {                              /* ATOM Channel n Counter 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CN0:24;                /* ATOM CCU0 counter register. */
    } B;
  } CH3_CN0;

  union {                              /* ATOM Channel n Status Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t ACBO:5;                /* ATOM Internal status bits. */
      vuint32_t  :1;
      vuint32_t WRF:1;                 /* Write request of CPU failed for late update. */
      vuint32_t DV:1;                  /* Valid ARU Data stored in compare registers. */
      vuint32_t ACBI:5;                /* ATOM Mode control bits received through ARU. */
      vuint32_t  :15;
      vuint32_t OL:1;                  /* Actual output signal level of ATOM_CHn_OUT. */
    } B;
  } CH3_STAT;

  union {                              /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH3_IRQ_NOTIFY;

  union {                              /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t CCU1TC_IRQ_EN:1;       /* ATOM_CCU1TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* ATOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH3_IRQ_EN;

  union {                              /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t TRG_CCU1TC:1;          /* Trigger ATOM_CCU1TC_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC:1;          /* Trigger ATOM_CCU0TC_IRQ interrupt by software. */
    } B;
  } CH3_IRQ_FORCINT;

  union {                              /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH3_IRQ_MODE;

  uint8_t ATOM_reserved4[80];
  union {                              /* ATOM Channel n Read Address Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t RDADDR1:9;             /* ARU Read address 1. */
      vuint32_t  :7;
      vuint32_t RDADDR0:9;             /* ARU Read address 0. */
    } B;
  } CH4_RDADDR;

  union {                              /* ATOM Channel n Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t ABM:1;                 /* ARU blocking mode. */
      vuint32_t OSM:1;                 /* One-shot mode. */
      vuint32_t SLA:1;                 /* Serve last ARU communication strategy */
      vuint32_t TRIGOUT:1;             /* NTrigger output selection (output signal TRIG_CHn) of module ATOM_CHn. */
      vuint32_t  :3;                   /* Reads as zero, should be written as zero. */
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :3;
      vuint32_t WR_REQ:1;              /* CPU Write request bit for late compare register update. */
      vuint32_t  :1;
      vuint32_t CLK_SRC_SR:3;          /* Actual CMU clock source (SOMS) / shadow register for CMU clock source (SOMP). */
      vuint32_t SL:1;                  /* Initial signal level after channel enable. */
      vuint32_t  :1;
      vuint32_t CMP_CTRL:1;            /* CCUn compare strategy select.. */
      vuint32_t ACB:5;                 /* ATOM Mode control bits. */
      vuint32_t ARU_EN:1;              /* ARU Input stream enable. */
      vuint32_t TB12_SEL:1;            /* Select time base value TBU_TS1 or TBU_TS2. */
      vuint32_t MODE:2;                /* ATOM channel mode select. */
    } B;
  } CH4_CTRL;

  union {                              /* ATOM Channel n Shadow 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SR0:24;                /* ATOM channel n shadow register SR0. */
    } B;
  } CH4_SR0;

  union {                              /* ATOM Channel n Shadow 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SR1:24;                /* ATOM channel n shadow register SR1. */
    } B;
  } CH4_SR1;

  union {                              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CM0:24;                /* ATOM CCU0 compare register. */
    } B;
  } CH4_CM0;

  union {                              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CM1:24;                /* ATOM CCU1 compare register. */
    } B;
  } CH4_CM1;

  union {                              /* ATOM Channel n Counter 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CN0:24;                /* ATOM CCU0 counter register. */
    } B;
  } CH4_CN0;

  union {                              /* ATOM Channel n Status Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t ACBO:5;                /* ATOM Internal status bits. */
      vuint32_t  :1;
      vuint32_t WRF:1;                 /* Write request of CPU failed for late update. */
      vuint32_t DV:1;                  /* Valid ARU Data stored in compare registers. */
      vuint32_t ACBI:5;                /* ATOM Mode control bits received through ARU. */
      vuint32_t  :15;
      vuint32_t OL:1;                  /* Actual output signal level of ATOM_CHn_OUT. */
    } B;
  } CH4_STAT;

  union {                              /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH4_IRQ_NOTIFY;

  union {                              /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t CCU1TC_IRQ_EN:1;       /* ATOM_CCU1TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* ATOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH4_IRQ_EN;

  union {                              /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t TRG_CCU1TC:1;          /* Trigger ATOM_CCU1TC_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC:1;          /* Trigger ATOM_CCU0TC_IRQ interrupt by software. */
    } B;
  } CH4_IRQ_FORCINT;

  union {                              /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH4_IRQ_MODE;

  uint8_t ATOM_reserved5[80];
  union {                              /* ATOM Channel n Read Address Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t RDADDR1:9;             /* ARU Read address 1. */
      vuint32_t  :7;
      vuint32_t RDADDR0:9;             /* ARU Read address 0. */
    } B;
  } CH5_RDADDR;

  union {                              /* ATOM Channel n Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t ABM:1;                 /* ARU blocking mode. */
      vuint32_t OSM:1;                 /* One-shot mode. */
      vuint32_t SLA:1;                 /* Serve last ARU communication strategy */
      vuint32_t TRIGOUT:1;             /* NTrigger output selection (output signal TRIG_CHn) of module ATOM_CHn. */
      vuint32_t  :3;                   /* Reads as zero, should be written as zero. */
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :3;
      vuint32_t WR_REQ:1;              /* CPU Write request bit for late compare register update. */
      vuint32_t  :1;
      vuint32_t CLK_SRC_SR:3;          /* Actual CMU clock source (SOMS) / shadow register for CMU clock source (SOMP). */
      vuint32_t SL:1;                  /* Initial signal level after channel enable. */
      vuint32_t  :1;
      vuint32_t CMP_CTRL:1;            /* CCUn compare strategy select.. */
      vuint32_t ACB:5;                 /* ATOM Mode control bits. */
      vuint32_t ARU_EN:1;              /* ARU Input stream enable. */
      vuint32_t TB12_SEL:1;            /* Select time base value TBU_TS1 or TBU_TS2. */
      vuint32_t MODE:2;                /* ATOM channel mode select. */
    } B;
  } CH5_CTRL;

  union {                              /* ATOM Channel n Shadow 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SR0:24;                /* ATOM channel n shadow register SR0. */
    } B;
  } CH5_SR0;

  union {                              /* ATOM Channel n Shadow 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SR1:24;                /* ATOM channel n shadow register SR1. */
    } B;
  } CH5_SR1;

  union {                              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CM0:24;                /* ATOM CCU0 compare register. */
    } B;
  } CH5_CM0;

  union {                              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CM1:24;                /* ATOM CCU1 compare register. */
    } B;
  } CH5_CM1;

  union {                              /* ATOM Channel n Counter 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CN0:24;                /* ATOM CCU0 counter register. */
    } B;
  } CH5_CN0;

  union {                              /* ATOM Channel n Status Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t ACBO:5;                /* ATOM Internal status bits. */
      vuint32_t  :1;
      vuint32_t WRF:1;                 /* Write request of CPU failed for late update. */
      vuint32_t DV:1;                  /* Valid ARU Data stored in compare registers. */
      vuint32_t ACBI:5;                /* ATOM Mode control bits received through ARU. */
      vuint32_t  :15;
      vuint32_t OL:1;                  /* Actual output signal level of ATOM_CHn_OUT. */
    } B;
  } CH5_STAT;

  union {                              /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH5_IRQ_NOTIFY;

  union {                              /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t CCU1TC_IRQ_EN:1;       /* ATOM_CCU1TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* ATOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH5_IRQ_EN;

  union {                              /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t TRG_CCU1TC:1;          /* Trigger ATOM_CCU1TC_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC:1;          /* Trigger ATOM_CCU0TC_IRQ interrupt by software. */
    } B;
  } CH5_IRQ_FORCINT;

  union {                              /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH5_IRQ_MODE;

  uint8_t ATOM_reserved6[80];
  union {                              /* ATOM Channel n Read Address Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t RDADDR1:9;             /* ARU Read address 1. */
      vuint32_t  :7;
      vuint32_t RDADDR0:9;             /* ARU Read address 0. */
    } B;
  } CH6_RDADDR;

  union {                              /* ATOM Channel n Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t ABM:1;                 /* ARU blocking mode. */
      vuint32_t OSM:1;                 /* One-shot mode. */
      vuint32_t SLA:1;                 /* Serve last ARU communication strategy */
      vuint32_t TRIGOUT:1;             /* NTrigger output selection (output signal TRIG_CHn) of module ATOM_CHn. */
      vuint32_t  :3;                   /* Reads as zero, should be written as zero. */
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :3;
      vuint32_t WR_REQ:1;              /* CPU Write request bit for late compare register update. */
      vuint32_t  :1;
      vuint32_t CLK_SRC_SR:3;          /* Actual CMU clock source (SOMS) / shadow register for CMU clock source (SOMP). */
      vuint32_t SL:1;                  /* Initial signal level after channel enable. */
      vuint32_t  :1;
      vuint32_t CMP_CTRL:1;            /* CCUn compare strategy select.. */
      vuint32_t ACB:5;                 /* ATOM Mode control bits. */
      vuint32_t ARU_EN:1;              /* ARU Input stream enable. */
      vuint32_t TB12_SEL:1;            /* Select time base value TBU_TS1 or TBU_TS2. */
      vuint32_t MODE:2;                /* ATOM channel mode select. */
    } B;
  } CH6_CTRL;

  union {                              /* ATOM Channel n Shadow 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SR0:24;                /* ATOM channel n shadow register SR0. */
    } B;
  } CH6_SR0;

  union {                              /* ATOM Channel n Shadow 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SR1:24;                /* ATOM channel n shadow register SR1. */
    } B;
  } CH6_SR1;

  union {                              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CM0:24;                /* ATOM CCU0 compare register. */
    } B;
  } CH6_CM0;

  union {                              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CM1:24;                /* ATOM CCU1 compare register. */
    } B;
  } CH6_CM1;

  union {                              /* ATOM Channel n Counter 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CN0:24;                /* ATOM CCU0 counter register. */
    } B;
  } CH6_CN0;

  union {                              /* ATOM Channel n Status Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t ACBO:5;                /* ATOM Internal status bits. */
      vuint32_t  :1;
      vuint32_t WRF:1;                 /* Write request of CPU failed for late update. */
      vuint32_t DV:1;                  /* Valid ARU Data stored in compare registers. */
      vuint32_t ACBI:5;                /* ATOM Mode control bits received through ARU. */
      vuint32_t  :15;
      vuint32_t OL:1;                  /* Actual output signal level of ATOM_CHn_OUT. */
    } B;
  } CH6_STAT;

  union {                              /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH6_IRQ_NOTIFY;

  union {                              /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t CCU1TC_IRQ_EN:1;       /* ATOM_CCU1TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* ATOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH6_IRQ_EN;

  union {                              /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t TRG_CCU1TC:1;          /* Trigger ATOM_CCU1TC_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC:1;          /* Trigger ATOM_CCU0TC_IRQ interrupt by software. */
    } B;
  } CH6_IRQ_FORCINT;

  union {                              /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH6_IRQ_MODE;

  uint8_t ATOM_reserved7[80];
  union {                              /* ATOM Channel n Read Address Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t RDADDR1:9;             /* ARU Read address 1. */
      vuint32_t  :7;
      vuint32_t RDADDR0:9;             /* ARU Read address 0. */
    } B;
  } CH7_RDADDR;

  union {                              /* ATOM Channel n Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t ABM:1;                 /* ARU blocking mode. */
      vuint32_t OSM:1;                 /* One-shot mode. */
      vuint32_t SLA:1;                 /* Serve last ARU communication strategy */
      vuint32_t TRIGOUT:1;             /* NTrigger output selection (output signal TRIG_CHn) of module ATOM_CHn. */
      vuint32_t  :3;                   /* Reads as zero, should be written as zero. */
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :3;
      vuint32_t WR_REQ:1;              /* CPU Write request bit for late compare register update. */
      vuint32_t  :1;
      vuint32_t CLK_SRC_SR:3;          /* Actual CMU clock source (SOMS) / shadow register for CMU clock source (SOMP). */
      vuint32_t SL:1;                  /* Initial signal level after channel enable. */
      vuint32_t  :1;
      vuint32_t CMP_CTRL:1;            /* CCUn compare strategy select.. */
      vuint32_t ACB:5;                 /* ATOM Mode control bits. */
      vuint32_t ARU_EN:1;              /* ARU Input stream enable. */
      vuint32_t TB12_SEL:1;            /* Select time base value TBU_TS1 or TBU_TS2. */
      vuint32_t MODE:2;                /* ATOM channel mode select. */
    } B;
  } CH7_CTRL;

  union {                              /* ATOM Channel n Shadow 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SR0:24;                /* ATOM channel n shadow register SR0. */
    } B;
  } CH7_SR0;

  union {                              /* ATOM Channel n Shadow 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SR1:24;                /* ATOM channel n shadow register SR1. */
    } B;
  } CH7_SR1;

  union {                              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CM0:24;                /* ATOM CCU0 compare register. */
    } B;
  } CH7_CM0;

  union {                              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CM1:24;                /* ATOM CCU1 compare register. */
    } B;
  } CH7_CM1;

  union {                              /* ATOM Channel n Counter 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CN0:24;                /* ATOM CCU0 counter register. */
    } B;
  } CH7_CN0;

  union {                              /* ATOM Channel n Status Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t ACBO:5;                /* ATOM Internal status bits. */
      vuint32_t  :1;
      vuint32_t WRF:1;                 /* Write request of CPU failed for late update. */
      vuint32_t DV:1;                  /* Valid ARU Data stored in compare registers. */
      vuint32_t ACBI:5;                /* ATOM Mode control bits received through ARU. */
      vuint32_t  :15;
      vuint32_t OL:1;                  /* Actual output signal level of ATOM_CHn_OUT. */
    } B;
  } CH7_STAT;

  union {                              /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH7_IRQ_NOTIFY;

  union {                              /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t CCU1TC_IRQ_EN:1;       /* ATOM_CCU1TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* ATOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH7_IRQ_EN;

  union {                              /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t TRG_CCU1TC:1;          /* Trigger ATOM_CCU1TC_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC:1;          /* Trigger ATOM_CCU0TC_IRQ interrupt by software. */
    } B;
  } CH7_IRQ_FORCINT;

  union {                              /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH7_IRQ_MODE;
};


/* ============================================================================
   =============================== Module: GTM_BRC ============================
   ============================================================================ */

struct GTM_BRC_tag {
  struct {
    union {                            /* BRC Source n Address Register, n[0:11] */
      vuint32_t R;
      struct {
        vuint32_t  :19;
        vuint32_t BRC_MODE:1;          /* BRC Operation mode select. */
        vuint32_t  :3;
        vuint32_t ADDR:9;              /* Source ARU address. */
      } B;
    } ADDR;
    union {                            /* BRC Source n to Destination Register, n[0:11] */
      vuint32_t R;
      struct {
        vuint32_t  :9;
        vuint32_t EN_TRASHBIN:1;       /* Control trash bin functionality. */
        vuint32_t EN_DEST21:1;         /* See EN_DEST0. */
        vuint32_t EN_DEST20:1;         /* See EN_DEST0. */
        vuint32_t EN_DEST19:1;         /* See EN_DEST0. */
        vuint32_t EN_DEST18:1;         /* See EN_DEST0. */
        vuint32_t EN_DEST17:1;         /* See EN_DEST0. */
        vuint32_t EN_DEST16:1;         /* See EN_DEST0. */
        vuint32_t EN_DEST15:1;         /* See EN_DEST0. */
        vuint32_t EN_DEST14:1;         /* See EN_DEST0. */
        vuint32_t EN_DEST13:1;         /* See EN_DEST0. */
        vuint32_t EN_DEST12:1;         /* See EN_DEST0. */
        vuint32_t EN_DEST11:1;         /* See EN_DEST0. */
        vuint32_t EN_DEST10:1;         /* See EN_DEST0. */
        vuint32_t EN_DEST9:1;          /* See EN_DEST0. */
        vuint32_t EN_DEST8:1;          /* See EN_DEST0. */
        vuint32_t EN_DEST7:1;          /* See EN_DEST0. */
        vuint32_t EN_DEST6:1;          /* See EN_DEST0. */
        vuint32_t EN_DEST5:1;          /* See EN_DEST0. */
        vuint32_t EN_DEST4:1;          /* See EN_DEST0. */
        vuint32_t EN_DEST3:1;          /* See EN_DEST0. */
        vuint32_t EN_DEST2:1;          /* See EN_DEST0. */
        vuint32_t EN_DEST1:1;          /* See EN_DEST0. */
        vuint32_t EN_DEST0:1;          /* Enable BRC destination address. */
      } B;
    } DEST;
  } SRC[12];

  union {                              /* BRC Interrupt Request Notification Register */
    vuint32_t R;
    struct {
      vuint32_t  :19;
      vuint32_t DID0:1;                /* Data inconsistency occurred in MTM mode. */
      vuint32_t DID1:1;                /* Data inconsistency occurred in MTM mode. */
      vuint32_t DID2:1;                /* Data inconsistency occurred in MTM mode. */
      vuint32_t DID3:1;                /* Data inconsistency occurred in MTM mode. */
      vuint32_t DID4:1;                /* Data inconsistency occurred in MTM mode. */
      vuint32_t DID5:1;                /* Data inconsistency occurred in MTM mode. */
      vuint32_t DID6:1;                /* Data inconsistency occurred in MTM mode. */
      vuint32_t DID7:1;                /* Data inconsistency occurred in MTM mode. */
      vuint32_t DID8:1;                /* Data inconsistency occurred in MTM mode. */
      vuint32_t DID9:1;                /* Data inconsistency occurred in MTM mode. */
      vuint32_t DID10:1;               /* Data inconsistency occurred in MTM mode. */
      vuint32_t DID11:1;               /* Data inconsistency occurred in MTM mode. */
      vuint32_t DEST_ERR:1;            /* Configuration error interrupt for BRC submodule. */
    } B;
  } IRQ_NOTIFY;

  union {                              /* BRC Interrupt Request Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :19;
      vuint32_t DID_IRQ_EN0:1;         /* BRC_DID_IRQ interrupt enable. */
      vuint32_t DID_IRQ_EN1:1;         /* BRC_DID_IRQ interrupt enable. */
      vuint32_t DID_IRQ_EN2:1;         /* BRC_DID_IRQ interrupt enable. */
      vuint32_t DID_IRQ_EN3:1;         /* BRC_DID_IRQ interrupt enable. */
      vuint32_t DID_IRQ_EN4:1;         /* BRC_DID_IRQ interrupt enable. */
      vuint32_t DID_IRQ_EN5:1;         /* BRC_DID_IRQ interrupt enable. */
      vuint32_t DID_IRQ_EN6:1;         /* BRC_DID_IRQ interrupt enable. */
      vuint32_t DID_IRQ_EN7:1;         /* BRC_DID_IRQ interrupt enable. */
      vuint32_t DID_IRQ_EN8:1;         /* BRC_DID_IRQ interrupt enable. */
      vuint32_t DID_IRQ_EN9:1;         /* BRC_DID_IRQ interrupt enable. */
      vuint32_t DID_IRQ_EN10:1;        /* BRC_DID_IRQ interrupt enable. */
      vuint32_t DID_IRQ_EN11:1;        /* BRC_DID_IRQ interrupt enable. */
      vuint32_t DEST_ERR_EN:1;         /* BRC_DEST_ERR_IRQ interrupt enable. */
    } B;
  } IRQ_EN;

  union {                              /* BRC Force Interrupt Request Register */
    vuint32_t R;
    struct {
      vuint32_t  :19;
      vuint32_t TRG_DID0:1;            /* Trigger data inconsistency error interrupt. */
      vuint32_t TRG_DID1:1;            /* Trigger data inconsistency error interrupt. */
      vuint32_t TRG_DID2:1;            /* Trigger data inconsistency error interrupt. */
      vuint32_t TRG_DID3:1;            /* Trigger data inconsistency error interrupt. */
      vuint32_t TRG_DID4:1;            /* Trigger data inconsistency error interrupt. */
      vuint32_t TRG_DID5:1;            /* Trigger data inconsistency error interrupt. */
      vuint32_t TRG_DID6:1;            /* Trigger data inconsistency error interrupt. */
      vuint32_t TRG_DID7:1;            /* Trigger data inconsistency error interrupt. */
      vuint32_t TRG_DID8:1;            /* Trigger data inconsistency error interrupt. */
      vuint32_t TRG_DID9:1;            /* Trigger data inconsistency error interrupt. */
      vuint32_t TRG_DID10:1;           /* Trigger data inconsistency error interrupt. */
      vuint32_t TRG_DID11:1;           /* Trigger data inconsistency error interrupt. */
      vuint32_t TRG_DEST_ERR:1;        /* Trigger destination error interrupt. */
    } B;
  } IRQ_FORCINT;

  union {                              /* BRC Interrupt Request Mode Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode select */
    } B;
  } IRQ_MODE;

  union {                              /* BRC Software Reset Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t RST:1;                 /* Software reset. */
    } B;
  } RST;

  union {                              /* BRC Error Interrupt Request Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :19;
      vuint32_t DID_EIRQ_EN0:1;        /* BRC_DID_EIRQ error interrupt enable. */
      vuint32_t DID_EIRQ_EN1:1;        /* BRC_DID_EIRQ error interrupt enable. */
      vuint32_t DID_EIRQ_EN2:1;        /* BRC_DID_EIRQ error interrupt enable. */
      vuint32_t DID_EIRQ_EN3:1;        /* BRC_DID_EIRQ error interrupt enable. */
      vuint32_t DID_EIRQ_EN4:1;        /* BRC_DID_EIRQ error interrupt enable. */
      vuint32_t DID_EIRQ_EN5:1;        /* BRC_DID_EIRQ error interrupt enable. */
      vuint32_t DID_EIRQ_EN6:1;        /* BRC_DID_EIRQ error interrupt enable. */
      vuint32_t DID_EIRQ_EN7:1;        /* BRC_DID_EIRQ error interrupt enable. */
      vuint32_t DID_EIRQ_EN8:1;        /* BRC_DID_EIRQ error interrupt enable. */
      vuint32_t DID_EIRQ_EN9:1;        /* BRC_DID_EIRQ error interrupt enable. */
      vuint32_t DID_EIRQ_EN10:1;       /* BRC_DID_EIRQ error interrupt enable. */
      vuint32_t DID_EIRQ_EN11:1;       /* BRC_DID_EIRQ error interrupt enable. */
      vuint32_t DEST_ERR_EIRQ_EN:1;    /* BRC_DEST_ERR_EIRQ error interrupt enable. */
    } B;
  } EIRQ_EN;
};


/* ============================================================================
   =============================== Module: GTM_CMP ============================
   ============================================================================ */

struct GTM_CMP_tag {
  union {                              /* Compare Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t TBWC11_EN:1;           /* See TBWC0_EN. */
      vuint32_t TBWC10_EN:1;           /* See TBWC0_EN. */
      vuint32_t TBWC9_EN:1;            /* See TBWC0_EN. */
      vuint32_t TBWC8_EN:1;            /* See TBWC0_EN. */
      vuint32_t TBWC7_EN:1;            /* See TBWC0_EN. */
      vuint32_t TBWC6_EN:1;            /* See TBWC0_EN. */
      vuint32_t TBWC5_EN:1;            /* See TBWC0_EN. */
      vuint32_t TBWC4_EN:1;            /* See TBWC0_EN. */
      vuint32_t TBWC3_EN:1;            /* See TBWC0_EN. */
      vuint32_t TBWC2_EN:1;            /* See TBWC0_EN. */
      vuint32_t TBWC1_EN:1;            /* See TBWC0_EN. */
      vuint32_t TBWC0_EN:1;            /* Enable corresponding comparator in TBWC. */
      vuint32_t ABWC11_EN:1;           /* See ABWC0_EN. */
      vuint32_t ABWC10_EN:1;           /* See ABWC0_EN. */
      vuint32_t ABWC9_EN:1;            /* See ABWC0_EN. */
      vuint32_t ABWC8_EN:1;            /* See ABWC0_EN. */
      vuint32_t ABWC7_EN:1;            /* See ABWC0_EN. */
      vuint32_t ABWC6_EN:1;            /* See ABWC0_EN. */
      vuint32_t ABWC5_EN:1;            /* See ABWC0_EN. */
      vuint32_t ABWC4_EN:1;            /* See ABWC0_EN. */
      vuint32_t ABWC3_EN:1;            /* See ABWC0_EN. */
      vuint32_t ABWC2_EN:1;            /* See ABWC0_EN. */
      vuint32_t ABWC1_EN:1;            /* See ABWC0_EN. */
      vuint32_t ABWC0_EN:1;            /* Enable corresponding comparator in ABWC. */
    } B;
  } EN;

  union {                              /* Compare Interrupt Request Notification Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t TBWC11:1;              /* See TBWC0. */
      vuint32_t TBWC10:1;              /* See TBWC0. */
      vuint32_t TBWC9:1;               /* See TBWC0. */
      vuint32_t TBWC8:1;               /* See TBWC0. */
      vuint32_t TBCW7:1;               /* See TBWC0. */
      vuint32_t TBWC6:1;               /* See TBWC0. */
      vuint32_t TBWC5:1;               /* See TBWC0. */
      vuint32_t TBWC4:1;               /* See TBWC0. */
      vuint32_t TBWC3:1;               /* See TBWC0. */
      vuint32_t TBWC2:1;               /* See TBWC0. */
      vuint32_t TBWC1:1;               /* See TBWC0. */
      vuint32_t TBWC0:1;               /* TOM sub modules outputs bitwise comparator 0 error indication. */
      vuint32_t ABWC11:1;              /* See ABWC0. */
      vuint32_t ABWC10:1;              /* See ABWC0. */
      vuint32_t ABWC9:1;               /* See ABWC0. */
      vuint32_t ABWC8:1;               /* See ABWC0. */
      vuint32_t ABWC7:1;               /* See ABWC0. */
      vuint32_t ABWC6:1;               /* See ABWC0. */
      vuint32_t ABWC5:1;               /* See ABWC0. */
      vuint32_t ABWC4:1;               /* See ABWC0. */
      vuint32_t ABWC3:1;               /* See ABWC0. */
      vuint32_t ABWC2:1;               /* See ABWC0. */
      vuint32_t ABWC1:1;               /* See ABWC0. */
      vuint32_t ABWC0:1;               /* ATOM sub modules outputs bitwise comparator error indication. */
    } B;
  } IRQ_NOTIFY;

  union {                              /* Compare Interrupt Request Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t TBWC11_EN_IRQ:1;       /* See TBWC0_EN_IRQ. */
      vuint32_t TBWC10_EN_IRQ:1;       /* See TBWC0_EN_IRQ. */
      vuint32_t TBWC9_EN_IRQ:1;        /* See TBWC0_EN_IRQ. */
      vuint32_t TBWC8_EN_IRQ:1;        /* See TBWC0_EN_IRQ. */
      vuint32_t TBWC7_EN_IRQ:1;        /* See TBWC0_EN_IRQ. */
      vuint32_t TBWC6_EN_IRQ:1;        /* See TBWC0_EN_IRQ. */
      vuint32_t TBWC5_EN_IRQ:1;        /* See TBWC0_EN_IRQ. */
      vuint32_t TBWC4_EN_IRQ:1;        /* See TBWC0_EN_IRQ. */
      vuint32_t TBWC3_EN_IRQ:1;        /* See TBWC0_EN_IRQ. */
      vuint32_t TBWC2_EN_IRQ:1;        /* See TBWC0_EN_IRQ. */
      vuint32_t TBWC1_EN_IRQ:1;        /* See TBWC0_EN_IRQ. */
      vuint32_t TBWC0_EN_IRQ:1;        /* Enable corresponding TBWC interrupt source for CMP_IRQ line. */
      vuint32_t ABWC11_EN_IRQ:1;       /* See ABWC0_EN_IRQ. */
      vuint32_t ABWC10_EN_IRQ:1;       /* See ABWC0_EN_IRQ. */
      vuint32_t ABWC9_EN_IRQ:1;        /* See ABWC0_EN_IRQ. */
      vuint32_t ABWC8_EN_IRQ:1;        /* See ABWC0_EN_IRQ. */
      vuint32_t ABWC7_EN_IRQ:1;        /* See ABWC0_EN_IRQ. */
      vuint32_t ABWC6_EN_IRQ:1;        /* See ABWC0_EN_IRQ. */
      vuint32_t ABWC5_EN_IRQ:1;        /* See ABWC0_EN_IRQ. */
      vuint32_t ABWC4_EN_IRQ:1;        /* See ABWC0_EN_IRQ. */
      vuint32_t ABWC3_EN_IRQ:1;        /* See ABWC0_EN_IRQ. */
      vuint32_t ABWC2_EN_IRQ:1;        /* See ABWC0_EN_IRQ. */
      vuint32_t ABWC1_EN_IRQ:1;        /* See ABWC0_EN_IRQ. */
      vuint32_t ABWC0_EN_IRQ:1;        /* Enable corresponding ABWC interrupt source for CMP_IRQ line. */
    } B;
  } IRQ_EN;

  union {                              /* Compare Force Interrupt Request Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t TRG_TBWC11:1;          /* See TRG_TBWC0. */
      vuint32_t TRG_TBWC10:1;          /* See TRG_TBWC0. */
      vuint32_t TRG_TBWC9:1;           /* See TRG_TBWC0. */
      vuint32_t TRG_TBWC8:1;           /* See TRG_TBWC0. */
      vuint32_t TRG_TBWC7:1;           /* See TRG_TBWC0. */
      vuint32_t TRG_TBWC6:1;           /* See TRG_TBWC0. */
      vuint32_t TRG_TBWC5:1;           /* See TRG_TBWC0. */
      vuint32_t TRG_TBWC4:1;           /* See TRG_TBWC0. */
      vuint32_t TRG_TBWC3:1;           /* See TRG_TBWC0. */
      vuint32_t TRG_TBWC2:1;           /* See TRG_TBWC0. */
      vuint32_t TRG_TBWC1:1;           /* See TRG_TBWC0. */
      vuint32_t TRG_TBWC0:1;           /* Trigger corresponding TBWC bit in CMP_IRQ_NOTIFY register by software. */
      vuint32_t TRG_ABWC11:1;          /* See TRG_ABWC0. */
      vuint32_t TRG_ABWC10:1;          /* See TRG_ABWC0. */
      vuint32_t TRG_ABWC9:1;           /* See TRG_ABWC0. */
      vuint32_t TRG_ABWC8:1;           /* See TRG_ABWC0. */
      vuint32_t TRG_ABWC7:1;           /* See TRG_ABWC0. */
      vuint32_t TRG_ABWC6:1;           /* See TRG_ABWC0. */
      vuint32_t TRG_ABWC5:1;           /* See TRG_ABWC0. */
      vuint32_t TRG_ABWC4:1;           /* See TRG_ABWC0. */
      vuint32_t TRG_ABWC3:1;           /* See TRG_ABWC0. */
      vuint32_t TRG_ABWC2:1;           /* See TRG_ABWC0. */
      vuint32_t TRG_ABWC1:1;           /* See TRG_ABWC0. */
      vuint32_t TRG_ABWC0:1;           /* Trigger corresponding ABWC bit in CMP_IRQ_NOTIFY register by software. */
    } B;
  } IRQ_FORCINT;

  union {                              /* Compare Interrupt Request Mode Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } IRQ_MODE;

  union {                              /* Compare Error Interrupt Request Enable register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t TBWC11_EN_EIRQ:1;      /* See TBWC0_EN_EIRQ. */
      vuint32_t TBWC10_EN_EIRQ:1;      /* See TBWC0_EN_EIRQ. */
      vuint32_t TBWC9_EN_EIRQ:1;       /* See TBWC0_EN_EIRQ. */
      vuint32_t TBWC8_EN_EIRQ:1;       /* See TBWC0_EN_EIRQ. */
      vuint32_t TBWC7_EN_EIRQ:1;       /* See TBWC0_EN_EIRQ. */
      vuint32_t TBWC6_EN_EIRQ:1;       /* See TBWC0_EN_EIRQ. */
      vuint32_t TBWC5_EN_EIRQ:1;       /* See TBWC0_EN_EIRQ. */
      vuint32_t TBWC4_EN_EIRQ:1;       /* See TBWC0_EN_EIRQ. */
      vuint32_t TBWC3_EN_EIRQ:1;       /* See TBWC0_EN_EIRQ. */
      vuint32_t TBWC2_EN_EIRQ:1;       /* See TBWC0_EN_EIRQ. */
      vuint32_t TBWC1_EN_EIRQ:1;       /* See TBWC0_EN_EIRQ. */
      vuint32_t TBWC0_EN_EIRQ:1;       /* Enable comparator 0-11 in TBWC. */
      vuint32_t ABWC11_EN_EIRQ:1;      /* ABWC0_EN_EIRQ */
      vuint32_t ABWC10_EN_EIRQ:1;      /* ABWC0_EN_EIRQ */
      vuint32_t ABWC9_EN_EIRQ:1;       /* ABWC0_EN_EIRQ */
      vuint32_t ABWC8_EN_EIRQ:1;       /* ABWC0_EN_EIRQ */
      vuint32_t ABWC7_EN_EIRQ:1;       /* ABWC0_EN_EIRQ */
      vuint32_t ABWC6_EN_EIRQ:1;       /* ABWC0_EN_EIRQ */
      vuint32_t ABWC5_EN_EIRQ:1;       /* ABWC0_EN_EIRQ */
      vuint32_t ABWC4_EN_EIRQ:1;       /* ABWC0_EN_EIRQ */
      vuint32_t ABWC3_EN_EIRQ:1;       /* ABWC0_EN_EIRQ */
      vuint32_t ABWC2_EN_EIRQ:1;       /* ABWC0_EN_EIRQ */
      vuint32_t ABWC1_EN_EIRQ:1;       /* ABWC0_EN_EIRQ */
      vuint32_t ABWC0_EN_EIRQ:1;       /* Enable comparator 0-11 in ABWC. */
    } B;
  } EIRQ_EN;
};


/* ============================================================================
   =============================== Module: GTM_CMU ============================
   ============================================================================ */

struct GTM_CMU_tag {
  union {                              /* CMU Clock Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t EN_FXCLK:2;            /* Enable all CMU_FXCLK. */
      vuint32_t EN_ECLK2:2;            /* Enable ECLK 2 generation subunit. */
      vuint32_t EN_ECLK1:2;            /* Enable ECLK 1 generation subunit */
      vuint32_t EN_ECLK0:2;            /* Enable ECLK 0 generation subunit. */
      vuint32_t EN_CLK7:2;             /* Enable clock source 7. */
      vuint32_t EN_CLK6:2;             /* Enable clock source 6. */
      vuint32_t EN_CLK5:2;             /* Enable clock source 5. */
      vuint32_t EN_CLK4:2;             /* Enable clock source 4. */
      vuint32_t EN_CLK3:2;             /* Enable clock source 3 */
      vuint32_t EN_CLK2:2;             /* Enable clock source 2. */
      vuint32_t EN_CLK1:2;             /* Enable clock source 1 */
      vuint32_t EN_CLK0:2;             /* Enable clock source 0. */
    } B;
  } CLK_EN;

  union {                              /* Global Clock Control Numerator Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t GCLK_NUM:24;           /* Numerator for global clock divider. */
    } B;
  } GCLK_NUM;

  union {                              /* Global Clock Control Denominator Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t GCLK_DEN:24;           /* Denominator for global clock divider. */
    } B;
  } GCLK_DEN;

  union {                              /* Control for Clock Source n register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CLK_CNT:24;            /* Clock count. */
    } B;
  } CLK_CTRL[6];

  union {                              /* Control for Clock Source 6 register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t CLK6_SEL:1;            /* Clock source selection for CMU_CLK6. */
      vuint32_t CLK_CNT:24;            /* Clock count. */
    } B;
  } CLK_6_CTRL;

  union {                              /* Control for Clock Source 7 register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t CLK7_SEL:1;            /* Clock source selection for CMU_CLK7. */
      vuint32_t CLK_CNT:24;            /* Clock count. */
    } B;
  } CLK_7_CTRL;

  struct {
    union {                            /* CMU External Clock n Numerator Register */
      vuint32_t R;
      struct {
        vuint32_t  :8;
        vuint32_t ECLK_NUM:24;         /* Numerator for external clock divider. */
      } B;
    } NUM;
    union {                            /* CMU External Clock n Denominator Register */
      vuint32_t R;
      struct {
        vuint32_t  :8;
        vuint32_t ECLK_DEN:24;         /* Denominator for external clock divider. */
      } B;
    } DEN;
  } ECLK[3];

  union {                              /* CMU FX Clock Control register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t FXCLK_SEL:4;           /* Input clock selection for EN_FXCLK line. */
    } B;
  } FXCLK_CTRL;
};


/* ============================================================================
   =============================== Module: GTM_DPLL ===========================
   ============================================================================ */

struct GTM_DPLL_tag {
  union {                              /* Control Register 0 */
    vuint32_t R;
    struct {
      vuint32_t RMO:1;                 /* Reference mode. */
      vuint32_t TEN:1;                 /* TRIGGER enable. */
      vuint32_t SEN:1;                 /* STATE enable. */
      vuint32_t IDT:1;                 /* Input delay TRIGGER. */
      vuint32_t IDS:1;                 /* Input delay STATE. */
      vuint32_t AMT:1;                 /* Adapt mode TRIGGER */
      vuint32_t AMS:1;                 /* Addapt mode STATE. */
      vuint32_t TNU:9;                 /* TRIGGER number. */
      vuint32_t SNU:5;                 /* STATE number. */
      vuint32_t IFP:1;                 /* Input filter position. */
      vuint32_t MLT:10;                /* Multiplier for TRIGGER. */
    } B;
  } CTRL_0;

  union {                              /* Control Register 1 */
    vuint32_t R;
    struct {
      vuint32_t TSL:2;                 /* TRIGGER slope select. */
      vuint32_t SSL:2;                 /* STATE slope select. */
      vuint32_t SMC:1;                 /* Synchronous Motor Control */
      vuint32_t TS0_HRT:1;             /* Time stamp high resolution TRIGGER */
      vuint32_t TS0_HRS:1;             /* Time stamp high resolution STATE. */
      vuint32_t SYSF:1;                /* SYN_NS for FULL_SCALE. */
      vuint32_t SWR:1;                 /* Software reset */
      vuint32_t LCD:1;                 /* Locking Condition Definition. */
      vuint32_t SYN_NT:6;              /* Synchronization number of TRIGGER. */
      vuint32_t SYN_NS:5;              /* Synchronization number of STATE. */
      vuint32_t PCM2:1;                /* Pulse Correction Mode. */
      vuint32_t DLM2:1;                /* Direct Load Mode. */
      vuint32_t SGE2:1;                /* SUB_INC2 generator enable. */
      vuint32_t PCM1:1;                /* Pulse Correction Mode. */
      vuint32_t DLM1:1;                /* Direct Load Mode. */
      vuint32_t SGE1:1;                /* SUB_INC1 generator enable. */
      vuint32_t PIT:1;                 /* Plausibility. */
      vuint32_t COA:1;                 /* Correction strategy in automatic end mode (DMO=0). */
      vuint32_t IDDS:1;                /* Input Direction Detection Strategy in the case of SMC=0. */
      vuint32_t DEN:1;                 /* DPLL enable. */
      vuint32_t DMO:1;                 /* DPLL mode select. */
    } B;
  } CTRL_1;

  union {                              /* Action Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t WAD7:1;                /* Write control bit of Action_7. */
      vuint32_t WAD6:1;                /* Write control bit of Action_6. */
      vuint32_t WAD5:1;                /* Write control bit of Action_5. */
      vuint32_t WAD4:1;                /* Write control bit of Action_4. */
      vuint32_t WAD3:1;                /* Write control bit of Action_3. */
      vuint32_t WAD2:1;                /* Write control bit of Action_2. */
      vuint32_t WAD1:1;                /* Write control bit of Action_1. */
      vuint32_t WAD0:1;                /* Write control bit of Action_0. */
      vuint32_t AEN7:1;                /* ACTION_7 enable. */
      vuint32_t AEN6:1;                /* ACTION_6 enable. */
      vuint32_t AEN5:1;                /* ACTION_5 enable. */
      vuint32_t AEN4:1;                /* ACTION_4 enable. */
      vuint32_t AEN3:1;                /* ACTION_3 enable. */
      vuint32_t AEN2:1;                /* ACTION_2 enable. */
      vuint32_t AEN1:1;                /* ACTION_1 enable. */
      vuint32_t AEN0:1;                /* ACTION_0 enable. */
      vuint32_t  :8;                   /* Reserved. */
    } B;
  } CTRL_2;

  union {                              /* Action Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t WAD15:1;               /* Write control bit of Action_15. */
      vuint32_t WAD14:1;               /* Write control bit of Action_14. */
      vuint32_t WAD13:1;               /* Write control bit of Action_13. */
      vuint32_t WAD12:1;               /* Write control bit of Action_12. */
      vuint32_t WAD11:1;               /* Write control bit of Action_11. */
      vuint32_t WAD10:1;               /* Write control bit of Action_10. */
      vuint32_t WAD9:1;                /* Write control bit of Action_9. */
      vuint32_t WAD8:1;                /* Write control bit of Action_8. */
      vuint32_t AEN15:1;               /* ACTION_15 enable. */
      vuint32_t AEN14:1;               /* ACTION_14 enable. */
      vuint32_t AEN13:1;               /* ACTION_13 enable. */
      vuint32_t AEN12:1;               /* ACTION_12 enable. */
      vuint32_t AEN11:1;               /* ACTION_11 enable. */
      vuint32_t AEN10:1;               /* ACTION_10 enable. */
      vuint32_t AEN9:1;                /* ACTION_9 enable. */
      vuint32_t AEN8:1;                /* ACTION_8 enable. */
      vuint32_t  :8;
    } B;
  } CTRL_3;

  union {                              /* Action Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t WAD23:1;               /* Write control bit of Action_23. */
      vuint32_t WAD22:1;               /* Write control bit of Action_22. */
      vuint32_t WAD21:1;               /* Write control bit of Action_21. */
      vuint32_t WAD20:1;               /* Write control bit of Action_20. */
      vuint32_t WAD19:1;               /* Write control bit of Action_19. */
      vuint32_t WAD18:1;               /* Write control bit of Action_18. */
      vuint32_t WAD17:1;               /* Write control bit of Action_17. */
      vuint32_t WAD16:1;               /* Write control bit of Action_16. */
      vuint32_t AEN23:1;               /* ACTION_23 enable. */
      vuint32_t AEN22:1;               /* ACTION_22 enable. */
      vuint32_t AEN21:1;               /* ACTION_21 enable. */
      vuint32_t AEN20:1;               /* ACTION_20 enable. */
      vuint32_t AEN19:1;               /* ACTION_19 enable. */
      vuint32_t AEN18:1;               /* ACTION_18 enable. */
      vuint32_t AEN17:1;               /* ACTION_17 enable. */
      vuint32_t AEN16:1;               /* ACTION_16 enable. */
      vuint32_t  :8;
    } B;
  } CTRL_4;

  union {                              /* Action Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t WAD31:1;               /* Write control bit of Action_31. */
      vuint32_t WAD30:1;               /* Write control bit of Action_30. */
      vuint32_t WAD29:1;               /* Write control bit of Action_29. */
      vuint32_t WAD28:1;               /* Write control bit of Action_28. */
      vuint32_t WAD27:1;               /* Write control bit of Action_27. */
      vuint32_t WAD26:1;               /* Write control bit of Action_26. */
      vuint32_t WAD25:1;               /* Write control bit of Action_25. */
      vuint32_t WAD24:1;               /* Write control bit of Action_24. */
      vuint32_t AEN31:1;               /* ACTION_31 enable. */
      vuint32_t AEN30:1;               /* ACTION_30 enable. */
      vuint32_t AEN29:1;               /* ACTION_29 enable. */
      vuint32_t AEN28:1;               /* ACTION_28 enable. */
      vuint32_t AEN27:1;               /* ACTION_27 enable. */
      vuint32_t AEN26:1;               /* ACTION_26 enable. */
      vuint32_t AEN25:1;               /* ACTION_25 enable. */
      vuint32_t AEN24:1;               /* ACTION_24 enable. */
      vuint32_t  :8;
    } B;
  } CTRL_5;

  union {                              /* Action Status Register including Shadow Register */
    vuint32_t R;
    struct {
      vuint32_t ACT_N:32;              /* New output data values concerning to action i provided. */
    } B;
  } ACT_STA;

  union {                              /* Offset and Switch Old/New Address Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t OSS:2;                 /* Offset size of RAM region 2. */
      vuint32_t  :6;
      vuint32_t SWON_T:1;              /* Switch of new TRIGGER. */
      vuint32_t SWON_S:1;              /* Switch of new STATE. */
    } B;
  } OSW;

  union {                              /* Address Offset Register of RAM2 Regions */
    vuint32_t R;
    struct {
      vuint32_t AOSV_2D:8;             /* Address offset value of the RAM 2d region. */
      vuint32_t AOSV_2C:8;             /* Address offset value of the RAM 2c region. */
      vuint32_t AOSV_2B:8;             /* Address offset value of the RAM 2b region. */
      vuint32_t AOSV_2A:8;             /* Address offset value of the RAM 2a region. */
    } B;
  } AOSV_2;

  union {                              /* Actual RAM Pointer Address for Trigger */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t APT_2B:10;             /* Address pointer TRIGGER for RAM region 2b. */
      vuint32_t WAPT_2B:1;             /* Write bit for address pointer APT_2b, read as zero. */
      vuint32_t  :1;
      vuint32_t APT:10;                /* Address pointer TRIGGER. */
      vuint32_t WAPT:1;                /* Write bit for address pointer APT, reads as zero. */
      vuint32_t  :1;
    } B;
  } APT;

  union {                              /* Actual RAM Pointer Address for STATE */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t APS_1C2:6;             /* Address pointer STATE for RAM regoin 1c2. */
      vuint32_t WAPS_1C2:1;            /* Write bit for address pointer APS_1c2, reads as zero. */
      vuint32_t  :5;
      vuint32_t APS:6;                 /* Address pointer STATE. */
      vuint32_t WAPS:1;                /* Write bit for address pointer APS, reads as zero. */
      vuint32_t  :1;
    } B;
  } APS;

  union {                              /* Actual RAM Pointer Address for Region 2C */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t APT_2C:10;             /* Address pointer TRIGGER for RAM region 2c. */
      vuint32_t  :2;
    } B;
  } APT_2C;

  union {                              /* Actual RAM Pointer Address for Region 1C3 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t APS_1C3:6;             /* Address pointer STATE for RAM region 1c3. */
      vuint32_t  :2;
    } B;
  } APS_1C3;

  union {                              /* Number of Recent TRIGGER Events used for Calculations */
    vuint32_t R;
    struct {
      vuint32_t WVTN:1;                /* Write control bit for VTN; reads as zero. */
      vuint32_t WSYN:1;                /* Write control bit for SYN_T and SYN_T_old; reads as zero. */
      vuint32_t WNUT:1;                /* Write control bit for NUTE and FST; reads as zero. */
      vuint32_t  :4;
      vuint32_t VTN:6;                 /* Virtual TRIGGER number. */
      vuint32_t SYN_T_old:3;           /* Number of real and virtual events to be considered for the last increment. */
      vuint32_t SYN_T:3;               /* Number of real and virtual events to be considered for the current increment. */
      vuint32_t  :2;
      vuint32_t FST:1;                 /* FULL_SCALE of TRIGGER. */
      vuint32_t NUTE:10;               /* Number of recent TRIGGER events used for SUB_INC1 and action calculations modulo 2 * (TNU max +1). */
    } B;
  } NUTC;

  union {                              /* Number of Recent STATE Events used for Calculations */
    vuint32_t R;
    struct {
      vuint32_t WVSN:1;                /* Write control bit for VSN; reads as zero. */
      vuint32_t WSYN:1;                /* Write control bit for SYN_S and SYN_S_old; reads as zero. */
      vuint32_t WNUS:1;                /* Write control bit for NUSE; reads as zero. */
      vuint32_t  :4;
      vuint32_t VSN:6;                 /* Virtual STATE number. */
      vuint32_t SYN_S_OLD:6;           /* Number of real and virtual events to be considered for the last increment. */
      vuint32_t SYN_S:6;               /* Number of real and virtual events to be considered for the current increment. */
      vuint32_t FSS:1;                 /* FULL_SCALE of STATE. */
      vuint32_t NUSE:6;                /* Number of recent STATE events used for SUB_INCx calculations modulo 2*(SNU max +1). */
    } B;
  } NUSC;

  union {                              /* Number of Active TRIGGER Events to Interrupt */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t NTI_CNT:10;            /* Number of TRIGGERs to interrupt. */
    } B;
  } NTI_CNT;

  union {                              /* Interrupt Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t DCGI:1;                /* Direction change interrupt. */
      vuint32_t SORI:1;                /* STATE out of range. */
      vuint32_t TORI:1;                /* TRIGGER out of range interrupt. */
      vuint32_t CDSI:1;                /* Calculation of STATE duration done. */
      vuint32_t CDTI:1;                /* Calculation of TRIGGER duration done, only while NTI_CNT is zero. */
      vuint32_t TE4I:1;                /* TRIGGER event interrupt 4. */
      vuint32_t TE3I:1;                /* TRIGGER event interrupt 3. */
      vuint32_t TE2I:1;                /* TRIGGER event interrupt 2. */
      vuint32_t TE1I:1;                /* TRIGGER event interrupt 1. */
      vuint32_t TE0I:1;                /* TRIGGER event interrupt 0. */
      vuint32_t LL2I:1;                /* Loss of lock interrupt for SUB_INC2. */
      vuint32_t GL2I:1;                /* Get of lock interrupt, for SUB_INC2. */
      vuint32_t EI:1;                  /* Error interrupt (see status register bit 31). */
      vuint32_t LL1I:1;                /* Loss of lock interrupt for SUB_INC1. */
      vuint32_t GL1I:1;                /* Get of lock interrupt, for SUB_INC1. */
      vuint32_t W1I:1;                 /* Write access to RAM region 1b or 1c interrupt. */
      vuint32_t W2I:1;                 /* RAM write access to RAM region 2 interrupt. */
      vuint32_t PWI:1;                 /* Plausibility window (PVT) violation interrupt of TRIGGER. */
      vuint32_t TASI:1;                /* TRIGGER active slope interrupt. */
      vuint32_t SASI:1;                /* STATE active slope interrupt. */
      vuint32_t MTI:1;                 /* Missing TRIGGER interrupt. */
      vuint32_t MSI:1;                 /* Missing STATE interrupt. */
      vuint32_t TISI:1;                /* TRIGGER inactive slope interrupt. */
      vuint32_t SISI:1;                /* STATE inactive slope interrupt. */
      vuint32_t TAXI:1;                /* TRIGGER maximum hold time violation interrupt (dt > THMA > 0). */
      vuint32_t TINI:1;
      vuint32_t PEI:1;                 /* DPLL enable interrupt; announces the switch on of the DEN bit. */
      vuint32_t PDI:1;                 /* DPLL disable interrupt; announces the switch off of the DEN bit. */
    } B;
  } IRQ_NOTIFY;

  union {                              /* Interrupt Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t DCGI_IRQ_EN:1;         /* Direction change interrupt. */
      vuint32_t SORI_IRQ_EN:1;         /* STATE out of range. */
      vuint32_t TORI_IRQ_EN:1;         /* TRIGGER out of range interrupt. */
      vuint32_t CDSI_IRQ_EN:1;         /* Enable interrupt when calculation of TRIGGER duration done. */
      vuint32_t CDTI_IRQ_EN:1;         /* Enable interrupt when calculation of TRIGGER duration done. */
      vuint32_t TE4I_IRQ_EN:1;         /* TRIGGER event interrupt 4 enable. */
      vuint32_t TE3I_IRQ_EN:1;         /* TRIGGER event interrupt 3 enable. */
      vuint32_t TE2I_IRQ_EN:1;         /* TRIGGER event interrupt 2 enable. */
      vuint32_t TE1I_IRQ_EN:1;         /* TRIGGER event interrupt 1 enable. */
      vuint32_t TE0I_IRQ_EN:1;         /* TRIGGER event interrupt 0 enable. */
      vuint32_t LL2I_IRQ_EN:1;         /* Loss of lock interrupt enable for SUB_INC2. */
      vuint32_t GL2I_IRQ_EN:1;         /* Get of lock interrupt enable for SUB_INC2. */
      vuint32_t EI_IRQ_EN:1;           /* Error interrupt enable (see status register). */
      vuint32_t LL1I_IRQ_EN:1;         /* Loss of lock interrupt enable. */
      vuint32_t GL1I_IRQ_EN:1;         /* Get of lock interrupt enable, when lock arises. */
      vuint32_t W1I_IRQ_EN:1;          /* Write access to RAM region 1b or 1c interrupt. */
      vuint32_t W2I_IRQ_EN:1;          /* RAM write access to RAM region 2 interrupt enable. */
      vuint32_t PWI_IRQ_EN:1;          /* Plausibility window (PVT) violation interrupt of TRIGGER enable. */
      vuint32_t TASI_IRQ_EN:1;         /* TRIGGER active slope interrupt enable. */
      vuint32_t SASI_IRQ_EN:1;         /* STATE active slope interrupt enable. */
      vuint32_t MTI_IRQ_EN:1;          /* Missing TRIGGER interrupt enable. */
      vuint32_t MSI_IRQ_EN:1;          /* Missing STATE interrupt enable. */
      vuint32_t TISI_IRQ_EN:1;         /* TRIGGER inactive slope interrupt enable bit. */
      vuint32_t SISI_IRQ_EN:1;         /* STATE inactive slope interrupt enable bit. */
      vuint32_t TAXI_IRQ_EN:1;         /* TRIGGER maximum hold time violation interrupt enable bit. */
      vuint32_t TINI_IRQ_EN:1;         /* TRIGGER minimum hold time violation interrupt enable bit. */
      vuint32_t PEI_IRQ_EN:1;          /* DPLL enable interrupt enable, when switch on of the DEN bit. */
      vuint32_t PDI_IRQ_EN:1;          /* DPLL disable interrupt enable, when switch off of the DEN bit. */
    } B;
  } IRQ_EN;

  union {                              /* Force Interrupt Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;                   /* Reserved. */
      vuint32_t TRG_DCGI:1;            /* Force interrupt DCGI. */
      vuint32_t TRG_SORI:1;            /* Force Interrupt SORI. */
      vuint32_t TRG_TORI:1;            /* Force Interrupt TORI. */
      vuint32_t TRG_CDSI:1;            /* Force Interrupt CDSI. */
      vuint32_t TRG_CDTI:1;            /* Force Interrupt CDTI. */
      vuint32_t TRG_TE4I:1;            /* Force Interrupt TE4I. */
      vuint32_t TRG_TE3I:1;            /* Force Interrupt TE3I. */
      vuint32_t TRG_TE2I:1;            /* Force Interrupt TE2I. */
      vuint32_t TRG_TE1I:1;            /* Force Interrupt TE1I. */
      vuint32_t TRG_TE0I:1;            /* Force Interrupt TE0I. */
      vuint32_t TRG_LL2I:1;            /* Force Interrupt LL2I. */
      vuint32_t TRG_GL2I:1;            /* Force Interrupt GL2I. */
      vuint32_t TRG_EI:1;              /* Force Interrupt EI. */
      vuint32_t TRG_LL1I:1;            /* Force Interrupt LL1I. */
      vuint32_t TRG_GL1I:1;            /* Force Interrupt GL1I. */
      vuint32_t TRG_W1I:1;             /* Force Interrupt W1I. */
      vuint32_t TRG_W2I:1;             /* Force Interrupt W2I. */
      vuint32_t TRG_PWI:1;             /* Force Interrupt PWI. */
      vuint32_t TRG_TASI:1;            /* Force Interrupt TASI. */
      vuint32_t TRG_SASI:1;            /* Force Interrupt SASI. */
      vuint32_t TRG_MTI:1;
      vuint32_t TRG_MSI:1;             /* Force Interrupt MSI. */
      vuint32_t TRG_TISI:1;            /* Force Interrupt TISI. */
      vuint32_t TRG_SISI:1;            /* Force Interrupt SISI. */
      vuint32_t TRG_TAXI:1;            /* Force Interrupt TAXI. */
      vuint32_t TRG_TINI:1;            /* Force Interrupt TINI. */
      vuint32_t TRG_PEI:1;             /* Force Interrupt PEI. */
      vuint32_t TRG_PDI:1;             /* Force Interrupt PDI. */
    } B;
  } IRQ_FORCINT;

  union {                              /* Interrupt Request Mode */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } IRQ_MODE;

  union {                              /* Error Interrupt Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t DCGI_EIRQ_EN:1;        /* Direction Change Interrupt. */
      vuint32_t SORI_EIRQ_EN:1;        /* STATE Out of Range Interrupt. */
      vuint32_t TORI_EIRQ_EN:1;        /* TRIGGER Out of Range Interrupt */
      vuint32_t CDSI_EIRQ_EN:1;        /* Enable interrupt when calculation of STATE duration done. */
      vuint32_t CDTI_EIRQ_EN:1;        /* Enable interrupt when calculation of TRIGGER duration done */
      vuint32_t TE4I_EIRQ_EN:1;        /* TRIGGER event interrupt 4 enable. */
      vuint32_t TE3I_EIRQ_EN:1;        /* TRIGGER event interrupt 3 enable. */
      vuint32_t TE2I_EIRQ_EN:1;        /* TRIGGER event interrupt 2 enable. */
      vuint32_t TE1I_EIRQ_EN:1;        /* TRIGGER event interrupt 1 enable. */
      vuint32_t TE0I_EIRQ_EN:1;        /* TRIGGER event interrupt 0 enable. */
      vuint32_t LL2I_EIRQ_EN:1;        /* Loss of lock interrupt enable for SUB_INC2. */
      vuint32_t GL2I_EIRQ_EN:1;        /* Get of lock interrupt enable for SUB_INC2. */
      vuint32_t EI_EIRQ_EN:1;          /* Error interrupt enable (see status register). */
      vuint32_t LL1I_EIRQ_EN:1;        /* Loss of lock interrupt enable. */
      vuint32_t GL1I_EIRQ_EN:1;        /* Get of lock interrupt enable, when lock arises. */
      vuint32_t W1I_EIRQ_EN:1;         /* Write access to RAM region 1b or 1c interrupt. */
      vuint32_t W2I_EIRQ_EN:1;         /* RAM write access to RAM region 2 interrupt enable. */
      vuint32_t PWI_EIRQ_EN:1;         /* Plausibility window (PVT) violation interrupt of TRIGGER enable. */
      vuint32_t TASI_EIRQ_EN:1;        /* TRIGGER active slope interrupt enable. */
      vuint32_t SASI_EIRQ_EN:1;        /* STATE active slope interrupt enable. */
      vuint32_t MTI_EIRQ_EN:1;         /* Missing TRIGGER interrupt enable. */
      vuint32_t MSI_EIRQ_EN:1;         /* Missing STATE interrupt enable. */
      vuint32_t TISI_EIRQ_EN:1;        /* TRIGGER inactive slope interrupt enable bit. */
      vuint32_t SISI_EIRQ_EN:1;        /* STATE inactive slope interrupt enable bit. */
      vuint32_t TAXI_EIRQ_EN:1;        /* TRIGGER maximum hold time violation interrupt enable bit. */
      vuint32_t TINI_EIRQ_EN:1;        /* TRIGGER minimum hold time violation interrupt enable bit. */
      vuint32_t PEI_EIRQ_EN:1;         /* DPLL enable interrupt enable, when switch on of the DEN bit. */
      vuint32_t PDI_EIRQ_EN:1;         /* DPLL disable interrupt enable, when switch off of the DEN bit. */
    } B;
  } EIRQ_EN;

  uint8_t DPLL_reserved0[92];
  union {                              /* Counter Value of Sent SUB_INC1 Pulses */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t INC_CNT1:24;           /* Actual number of pulses to be still sent out at the current increment until the next valid input signal in automatic end mode. */
    } B;
  } INC_CNT1;

  union {                              /* Counter Value of sent SUB_INC2 values (for SMC=1 and RMO=1) */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t INC_CNT2:24;           /* Actual number of pulses to be still sent out at the current increment until the next valid input signal in automatic end mode. */
    } B;
  } INC_CNT2;

  union {                              /* TRIGGER Time Stamp Field Offset at Synchronization Time */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t APT_2B_OLD:10;         /* Address pointer TRIGGER for RAM region 2B at synchronization time. */
      vuint32_t  :7;
      vuint32_t APT_2B_STATUS:1;       /* Address pointer 2B status. */
      vuint32_t APT_2B_EXT:6;          /* Address pointer 2B extension. */
    } B;
  } APT_SYNC;

  union {                              /* STATE Time Stamp Field Offset at Synchronization Time */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t APS_1C2_OLD:6;         /* Address pointer STATE for RAM regoin 1C2 at synchronization time. */
      vuint32_t  :7;
      vuint32_t APS_1C2_STATUS:1;      /* Address pointer 1C2 status. */
      vuint32_t APS_1C2_EXT:6;         /* Address pointer 1C2 extension. */
    } B;
  } APS_SYNC;

  union {                              /* Time Stamp Value for the last valid TRIGGER */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t TBU_TS0_T:24;          /* Value of TBU_TS0 at the last TRIGGER event. */
    } B;
  } TBU_TS0_T;

  union {                              /* Time Stamp Value for the last valid STATE */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t TBU_TS0_S:24;          /* Value of TBU_TS0 at the last STATE event. */
    } B;
  } TBU_TS0_S;

  union {                              /* ADD_IN Value in Direct Load Mode for TRIGGER */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t ADD_IN_LD1:24;         /* Input value for SUB_INC1 generation. */
    } B;
  } ADD_IN_LD1;

  union {                              /* ADD_IN Value in Direct Load Mode for STATE */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t ADD_IN_LD2:24;         /* Input value for SUB_INC2 generation. */
    } B;
  } ADD_IN_LD2;

  uint8_t DPLL_reserved1[44];
  union {                              /* Status Register */
    vuint32_t R;
    struct {
      vuint32_t ERR:1;                 /* Error. */
      vuint32_t LOCK1:1;               /* DPLL Lock status concerning SUB_INC1. */
      vuint32_t FTD:1;                 /* First TRIGGER detected. */
      vuint32_t FSD:1;                 /* First STATE detected. */
      vuint32_t SYT:1;                 /* Synchronization condition of TRIGGER fixed. */
      vuint32_t SYS:1;                 /* Synchronization condition of STATE fixed. */
      vuint32_t LOCK2:1;               /* DPLL Lock status concerning SUB_INC2. */
      vuint32_t  :1;
      vuint32_t BWD1:1;                /* Backwards drive of SUB_INC1. */
      vuint32_t BWD2:1;                /* Backwards drive of SUB_INC2. */
      vuint32_t ITN:1;                 /* Increment number of TRIGGER is not plausible. */
      vuint32_t ISN:1;                 /* Increment number of STATE is not plausible. */
      vuint32_t CAIP1:1;               /* Calculation of actions 0 to 11 in progress (1st part). */
      vuint32_t CAIP2:1;               /* Calculation of actions 12 to 23 in progress (2nd part). */
      vuint32_t CSVT:1;                /* Current signal value TRIGGER. */
      vuint32_t CSVS:1;                /* Current signal value STATE. */
      vuint32_t LOW_RES:1;             /* Low resolution of TBU_TS0. */
      vuint32_t  :2;
      vuint32_t RAM2_ERR:1;            /* DPLL internal access to not configured RAM2 memory space. */
      vuint32_t MT:1;                  /* Missing TRIGGER detected according to TOV. */
      vuint32_t TOR:1;                 /* TRIGGER out of range. */
      vuint32_t MS:1;                  /* Missing STATE detected according to TOV_S. */
      vuint32_t SOR:1;                 /* STATE out of range. */
      vuint32_t PSE:1;                 /* Prediction space configuration error. */
      vuint32_t RCT:1;                 /* Resolution conflict TRIGGER. */
      vuint32_t RCS:1;                 /* Resolution conflict STATE. */
      vuint32_t CRO:1;                 /* Calculated Reciprocal value overflow. */
      vuint32_t CTO:1;                 /* Calculated TRIGGER duration overflow. */
      vuint32_t  :1;
      vuint32_t CSO:1;                 /* Calculated STATE duration overflow. */
      vuint32_t  :1;
    } B;
  } STATUS;

  union {                              /* ID Information for In ut Signal PTR x (Position minus Time Request) */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t ID_PMTR_n:9;           /* ID information to the input signal PMTR_n from the ARU. */
    } B;
  } ID_PMTR[32];

  uint8_t DPLL_reserved2[96];
  union {                              /* Shadow Register of DPLL_CTRL_0 controlled by a valid TRIGGER Slope */
    vuint32_t R;
    struct {
      vuint32_t RMO:1;                 /* Reference mode. */
      vuint32_t  :3;
      vuint32_t IDT:1;                 /* Input delay TRIGGER; */
      vuint32_t  :1;
      vuint32_t AMT:1;                 /* Adapt mode TRIGGER */
      vuint32_t  :14;
      vuint32_t IFP:1;                 /* Input filter position. */
      vuint32_t MLT:10;                /* Multiplier for TRIGGER. */
    } B;
  } CTRL_0_SHADOW_TRIGGER;

  union {                              /* Shadow Register of DPLL_CTRL_0 controlled by a valid STATE Slope */
    vuint32_t R;
    struct {
      vuint32_t RMO:1;                 /* Reference mode. */
      vuint32_t  :3;
      vuint32_t IDS:1;                 /* Input delay STATE. */
      vuint32_t  :1;
      vuint32_t AMS:1;                 /* Addapt mode STATE. */
      vuint32_t  :14;
      vuint32_t IFP:1;                 /* Input filter position. */
      vuint32_t  :10;
    } B;
  } CTRL_0_SHADOW_STATE;

  union {                              /* Shadow Register of DPLL_CTRL_1 controlled by a valid TRIGGER Slope */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t PCM1:1;                /* Pulse Correction Mode. */
      vuint32_t DLM1:1;                /* Direct Load Mode. */
      vuint32_t SGE1:1;                /* SUB_INC1 generator enable. */
      vuint32_t PIT:1;                 /* Plausibility. */
      vuint32_t COA:1;                 /* Correction strategy in automatic end mode (DMO=0). */
      vuint32_t  :2;
      vuint32_t DMO:1;                 /* DPLL mode select.. */
    } B;
  } CTRL_1_SHADOW_TRIGGER;

  union {                              /* Shadow Register of DPLL_CTRL_1 controlled by a valid STATE Slope */
    vuint32_t R;
    struct {
      vuint32_t SYN_NS:21;             /* Synchronization number of STATE. */
      vuint32_t PCM2:1;                /* Pulse Correction Mode for SUB_INC2 generation. */
      vuint32_t DLM2:1;                /* Direct Load Mode for SUB_INC2 generation. */
      vuint32_t SGE2:1;                /* SUB_INC2 generator enable. */
      vuint32_t PCM1:1;                /* Pulse Correction Mode for SUB_INC1 generation. */
      vuint32_t DLM1:1;                /* Direct Load Mode for SUB_INC1 generation. */
      vuint32_t SGE1:1;                /* SUB_INC1 generator enable. */
      vuint32_t PIT:1;                 /* Plausibility value PVT to next valid TRIGGER is time related. */
      vuint32_t COA:1;                 /* Correction strategy in automatic end mode (DMO=0). */
      vuint32_t  :1;
      vuint32_t DEN:1;                 /* DPLL enable. */
      vuint32_t DMO:1;                 /* DPLL mode select. */
    } B;
  } CTRL_1_SHADOW_STATE;

  uint8_t DPLL_reserved3[12];
  union {                              /* Register to control the RAM Initialization */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t INIT_RAM:1;            /* RAM regions 1A, 1B and 2 are to be initialized. */
      vuint32_t  :1;
      vuint32_t INIT_2:1;              /* RAM region 2 initialization in progress. */
      vuint32_t INIT_1B:1;             /* RAM region 1B initialization in progress. */
      vuint32_t INIT_1A:1;             /* RAM region 1A initialization in progress. */
    } B;
  } RAM_INI;

  uint8_t DPLL_reserved4[3072];
  union {                              /* Calculated Time Value to start Action i */
    vuint32_t R;
    struct {
      vuint32_t TSAC:32;               /* Calculated time stamp for ACTION_i. */
    } B;
  } TSAC[32];

  union {                              /* DPLL Calculated Position Value ACTION i */
    vuint32_t R;
    struct {
      vuint32_t PSAC:32;               /* Calculated position value for the start of ACTION_i . */
    } B;
  } PSAC[32];

  union {                              /* Control Bits for up to 32 Actions */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t ACB_3:5;               /* Action Control Bits of ACTION_(i + 3), reflects ACT_D[i+3](52:48), i=4*j. */
      vuint32_t  :3;
      vuint32_t ACB_2:5;               /* Action Control Bits of ACTION_(i + 2), reflects ACT_D[i+2](52:48), i=4*j. */
      vuint32_t  :3;
      vuint32_t ACB_1:5;               /* Action Control Bits of ACTION_(i + 1) , reflects ACT_D[i+1](52:48), i=4*j. */
      vuint32_t  :3;
      vuint32_t ACB_0:5;               /* Control Bits of ACTION_i, reflects ACT_D[i](52:48), i=4*j. */
    } B;
  } ACB[8];
};


/* ============================================================================
   =============================== Module: GTM_F2A ============================
   ============================================================================ */

struct GTM_F2A_tag {
  union {                              /* F2A Read Channel n Address Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t ADDR:9;                /* ARU Read address. */
    } B;
  } CH_ARU_RD_FIFO[8];

  union {                              /* F2A Channel n Stream Configuration Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t DIR:1;                 /* Data transfer direction. */
      vuint32_t TMODE:2;               /* Transfer mode for 53 bit ARU data from/to FIFO. */
      vuint32_t  :16;
    } B;
  } CH_STR_CFG[8];

  union {                              /* F2A Stream Activation Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t STR7_EN:2;             /* Enable/disable stream 7. */
      vuint32_t STR6_EN:2;             /* Enable/disable stream 6. */
      vuint32_t STR5_EN:2;             /* Enable/disable stream 5. */
      vuint32_t STR4_EN:2;             /* Enable/disable stream 4. */
      vuint32_t STR3_EN:2;             /* Enable/disable stream 3. */
      vuint32_t STR2_EN:2;             /* Enable/disable stream 2. */
      vuint32_t STR1_EN:2;             /* Enable/disable stream 1. */
      vuint32_t STR0_EN:2;             /* STR0_EN */
    } B;
  } ENABLE;
};


/* ============================================================================
   =============================== Module: GTM_FIFO ===========================
   ============================================================================ */

struct GTM_FIFO_tag {
  struct {
    union {                            /* FIFO Channel Control Register */
      vuint32_t R;
      struct {
        vuint32_t  :28;                /* Reserved. */
        vuint32_t WULOCK:1;            /* RAM write unlock. */
        vuint32_t FLUSH:1;             /* FIFO Flush control. */
        vuint32_t RAP:1;               /* RAM access priority. */
        vuint32_t RBM:1;               /* Ring buffer mode enable. */
      } B;
    } CTRL;
    union {                            /* FIFO Channel End Address Register */
      vuint32_t R;
      struct {
        vuint32_t  :22;                /* Reserved. */
        vuint32_t ADDR:10;             /* End address for FIFO channel n. */
      } B;
    } END_ADDR;
    union {                            /* FIFO Channel Start Address Register */
      vuint32_t R;
      struct {
        vuint32_t  :22;                /* Reserved. */
        vuint32_t ADDR:10;             /* Start address for FIFO channel n. */
      } B;
    } START_ADDR;
    union {                            /* FIFO Channel Upper Watermark Register */
      vuint32_t R;
      struct {
        vuint32_t  :22;                /* Reserved. */
        vuint32_t ADDR:10;             /* Upper watermark. */
      } B;
    } UPPER_WM;
    union {                            /* FIFO Channel Lower Watermark Register */
      vuint32_t R;
      struct {
        vuint32_t  :22;                /* Reserved. */
        vuint32_t ADDR:10;             /* Normal Operation mode: Lower watermark. Ring buffer operation mode: Gate pointer from LWU to UWE. */
      } B;
    } LOWER_WM;
    union {                            /* FIFO Channel Status Register */
      vuint32_t R;
      struct {
        vuint32_t  :28;                /* Reserved. */
        vuint32_t UP_WM:1;             /* Upper watermark reached. */
        vuint32_t LOW_WM:1;            /* Lower watermark reached. */
        vuint32_t FULL:1;              /* FIFO fill level status. */
        vuint32_t EMPTY:1;             /* FIFO fill level status. */
      } B;
    } STATUS;
    union {                            /* FIFO Channel Fill Level Register */
      vuint32_t R;
      struct {
        vuint32_t  :21;                /* Reserved. */
        vuint32_t LEVEL:11;            /* Fill level of the current FIFO. */
      } B;
    } FILL_LEVEL;
    union {                            /* FIFO Channel Write Pointer Register */
      vuint32_t R;
      struct {
        vuint32_t  :22;                /* Reserved. */
        vuint32_t ADDR:10;             /* Position of the write pointer. */
      } B;
    } WR_PTR;
    union {                            /* FIFO Channel Read Pointer */
      vuint32_t R;
      struct {
        vuint32_t  :22;                /* Reserved. */
        vuint32_t ADDR:10;             /* Position of the read pointer. */
      } B;
    } RD_PTR;
    union {                            /* FIFO Channel IRQ Notification Register */
      vuint32_t R;
      struct {
        vuint32_t  :28;                /* Reserved. */
        vuint32_t FIFO_UWM:1;          /* FIFO Upper watermark was over-run. */
        vuint32_t FIFO_LWM:1;          /* FIFO Lower watermark was under-run. */
        vuint32_t FIFO_FULL:1;         /* FIFO is full. */
        vuint32_t FIFO_EMPTY:1;        /* FIFO is empty. */
      } B;
    } IRQ_NOTIFY;
    union {                            /* FIFO Channel IRQ Enable Register */
      vuint32_t R;
      struct {
        vuint32_t  :28;                /* Reserved. */
        vuint32_t FIFO_UWM_IRQ_EN:1;   /* FIFO Upper Water Mark Interrupt Enable. */
        vuint32_t FIFO_LWM_IRQ_EN:1;   /* FIFO Lower Watermark Interrupt Enable. */
        vuint32_t FIFO_FULL_IRQ_EN:1;  /* FIFO Full Interrupt Enable. */
        vuint32_t FIFO_EMPTY_IRQ_EN:1; /* FIFO Empty Interrupt Enable. */
      } B;
    } IRQ_EN;
    union {                            /* FIFO Channel Force Interrupt Register */
      vuint32_t R;
      struct {
        vuint32_t  :28;                /* Reserved. */
        vuint32_t TRG_FIFO_UWM:1;      /* Force interrupt of upper watermark. */
        vuint32_t TRG_FIFO_LWM:1;      /* Force interrupt of lower watermark. */
        vuint32_t TRG_FIFO_FULL:1;     /* Force interrupt of FIFO full status. */
        vuint32_t TRG_FIFO_EMPTY:1;    /* Force interrupt of FIFO empty status. */
      } B;
    } IRQ_FORCINT;
    union {                            /* FIFO Channel IRQ Mode Register */
      vuint32_t R;
      struct {
        vuint32_t  :28;                /* Reserved. */
        vuint32_t DMA_HYST_DIR:1;      /* DMA direction in hysteresis mode. */
        vuint32_t DMA_HYSTERESIS:1;    /* Enable DMA hysteresis mode. */
        vuint32_t IRQ_MODE:2;          /* IRQ mode select. */
      } B;
    } IRQ_MODE;
    union {                            /* FIFO Channel Error Interrupt Request Register */
      vuint32_t R;
      struct {
        vuint32_t  :28;
        vuint32_t FIFO_UWM_EIRQ_EN:1;  /* FIFO Upper Water Mark Error Interrupt Request Enable. */
        vuint32_t FIFO_LWM_EIRQ_EN:1;  /* FIFO Lower Water Mark Error Interrupt Request Enable. */
        vuint32_t FIFO_FULL_EIRQ_EN:1; /* FIFO Full Error Interrupt Request Enable. */
        vuint32_t FIFO_EMPTY_EIRQ_EN:1; /* FIFO Empty Error Interrupt Request Enable. */
      } B;
    } EIRQ_EN;
    uint8_t CHANNEL_reserved0[8];
  } CHANNEL[8];
};


/* ============================================================================
   =============================== Module: GTM_ICM ============================
   ============================================================================ */

struct GTM_ICM_tag {
  union {                              /* GTM Infrastructure Interrupt Group Register */
    vuint32_t R;
    struct {
      vuint32_t PSM1_CH7_IRQ:1;        /* PSM1 shared submodule channel 7 interrupt. */
      vuint32_t PSM1_CH6_IRQ:1;        /* PSM1 shared submodule channel 6 interrupt. */
      vuint32_t PSM1_CH5_IRQ:1;        /* PSM1 shared submodule channel 5 interrupt. */
      vuint32_t PSM1_CH4_IRQ:1;        /* PSM1 shared submodule channel 4 interrupt. */
      vuint32_t PSM1_CH3_IRQ:1;        /* PSM1 shared submodule channel 3 interrupt. */
      vuint32_t PSM1_CH2_IRQ:1;        /* PSM1 shared submodule channel 2 interrupt. */
      vuint32_t PSM1_CH1_IRQ:1;        /* PSM1 shared submodule channel 1 interrupt. */
      vuint32_t PSM1_CH0_IRQ:1;        /* PSM1 shared submodule channel 0 interrupt. */
      vuint32_t PSM0_CH7_IRQ:1;        /* PSM0 shared submodule channel 7 interrupt. */
      vuint32_t PSM0_CH6_IRQ:1;        /* PSM0 shared submodule channel 6 interrupt. */
      vuint32_t PSM0_CH5_IRQ:1;        /* PSM0 shared submodule channel 5 interrupt. */
      vuint32_t PSM0_CH4_IRQ:1;        /* PSM0 shared submodule channel 4 interrupt. */
      vuint32_t PSM0_CH3_IRQ:1;        /* PSM0 shared submodule channel 3 interrupt. */
      vuint32_t PSM0_CH2_IRQ:1;        /* PSM0 shared submodule channel 2 interrupt. */
      vuint32_t PSM0_CH1_IRQ:1;        /* PSM0 shared submodule channel 1 interrupt. */
      vuint32_t PSM0_CH0_IRQ:1;        /* PSM0 shared submodule channel 0 interrupt. */
      vuint32_t  :6;
      vuint32_t SPE3_IRQ:1;            /* SPE3 shared submodule interrupt. */
      vuint32_t SPE2_IRQ:1;            /* SPE2 shared submodule interrupt. */
      vuint32_t SPE1_IRQ:1;            /* SPE1 shared submodule interrupt. */
      vuint32_t SPE0_IRQ:1;            /* SPE0 shared submodule interrupt. */
      vuint32_t CMP_IRQ:1;             /* CMP shared submodule interrupt. */
      vuint32_t AEI_IRQ:1;             /* AEI_IRQ interrupt. */
      vuint32_t BRC_IRQ:1;             /* BRC shared submodule interrupt. */
      vuint32_t ARU_ACC_ACK_IRQ:1;     /* ARU_ACC_ACK interrupt. */
      vuint32_t ARU_NEW_DATA1_IRQ:1;   /* ARU_NEW_DATA1 interrupt. */
      vuint32_t ARU_NEW_DATA0_IRQ:1;   /* ARU_NEW_DATA0 interrupt. */
    } B;
  } IRQG_0;

  union {                              /* DPLL Interrupt Group Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t DPLL_SORI_IRQ:1;       /* DPLL calculated duration interrupt for STATE. */
      vuint32_t DPLL_TORI_IRQ:1;       /* DPLL calculated duration interrupt for TRIGGER. */
      vuint32_t DPLL_CDSI_IRQ:1;       /* DPLL calculated duration interrupt for STATE. */
      vuint32_t DPLL_CDTI_IRQ:1;       /* DPLL calculated duration interrupt for TRIGGER. */
      vuint32_t DPLL_TE4I_IRQ:1;       /* TRIGGER event interrupt 4. */
      vuint32_t DPLL_TE3I_IRQ:1;       /* TRIGGER event interrupt 3. */
      vuint32_t DPLL_TE2I_IRQ:1;       /* TRIGGER event interrupt 2. */
      vuint32_t DPLL_TE1I_IRQ:1;       /* TRIGGER event interrupt 1. */
      vuint32_t DPLL_TE0I_IRQ:1;       /* TRIGGER event interrupt 0. */
      vuint32_t DPLL_LL2I_IRQ:1;       /* Lost of lock interrupt for SUB_INC2. */
      vuint32_t DPLL_GL2I_IRQ:1;       /* Get of lock interrupt for SUB_INC2. */
      vuint32_t DPLL_EI_IRQ:1;         /* Error interrupt. */
      vuint32_t DPLL_LLI_IRQ:1;        /* Lost of lock interrupt for SUB_INC1. */
      vuint32_t DPLL_GLI_IRQ:1;        /* Get of lock interrupt for SUB_INC1. */
      vuint32_t DPLL_W1I_IRQ:1;        /* Write access to RAM region 1b or 1c interrupt. */
      vuint32_t DPLL_W2I_IRQ:1;        /* Write access to RAM region 2 interrupt. */
      vuint32_t DPLL_PWI_IRQ:1;        /* Plausibility window (PVT) violation interrupt of TRIGGER. */
      vuint32_t DPLL_TASI_IRQ:1;       /* TRIGGER active slope detected while NTI_CNT is zero. */
      vuint32_t DPLL_SASI_IRQ:1;       /* STATE active slope detected. */
      vuint32_t DPLL_MTI_IRQ:1;        /* Missing TRIGGER interrupt. */
      vuint32_t DPLL_MSI_IRQ:1;        /* Missing STATE interrupt. */
      vuint32_t DPLL_TISI_IRQ:1;       /* TRIGGER inactive slope detected interrupt. */
      vuint32_t DPLL_SISI_IRQ:1;       /* STATE inactive slope detected interrupt. */
      vuint32_t DPLL_TAXI_IRQ:1;       /* TRIGGER maximum hold time (THMA) violation detected interrupt. */
      vuint32_t DPLL_TINI_IRQ:1;       /* TRIGGER minimum hold time (THMI) violation detected interrupt. */
      vuint32_t DPLL_EDI_IRQ:1;        /* DPLL enable/disable interrupt. */
      vuint32_t DPLL_DCGI_IRQ:1;       /* TRIGGER direction change detected. */
    } B;
  } IRQG_1;

  union {                              /* TIM Interrupt Group 0 Register */
    vuint32_t R;
    struct {
      vuint32_t TIM3_CH7_IRQ:1;        /* TIM3 shared interrupt channel 7. */
      vuint32_t TIM3_CH6_IRQ:1;        /* TIM3 shared interrupt channel 6. */
      vuint32_t TIM3_CH5_IRQ:1;        /* TIM3 shared interrupt channel 5. */
      vuint32_t TIM3_CH4_IRQ:1;        /* TIM3 shared interrupt channel 4. */
      vuint32_t TIM3_CH3_IRQ:1;        /* TIM3 shared interrupt channel 3. */
      vuint32_t TIM3_CH2_IRQ:1;        /* TIM3 shared interrupt channel 2. */
      vuint32_t TIM3_CH1_IRQ:1;        /* TIM3 shared interrupt channel 1. */
      vuint32_t TIM3_CH0_IRQ:1;        /* TIM3 shared interrupt channel 0. */
      vuint32_t TIM2_CH7_IRQ:1;        /* TIM2 shared interrupt channel 7. */
      vuint32_t TIM2_CH6_IRQ:1;        /* TIM2 shared interrupt channel 6. */
      vuint32_t TIM2_CH5_IRQ:1;        /* TIM2 shared interrupt channel 5. */
      vuint32_t TIM2_CH4_IRQ:1;        /* TIM2 shared interrupt channel 4. */
      vuint32_t TIM2_CH3_IRQ:1;        /* TIM2 shared interrupt channel 3. */
      vuint32_t TIM2_CH2_IRQ:1;        /* TIM2 shared interrupt channel 2. */
      vuint32_t TIM2_CH1_IRQ:1;        /* TIM2 shared interrupt channel 1. */
      vuint32_t TIM2_CH0_IRQ:1;        /* TIM2 shared interrupt channel 0. */
      vuint32_t TIM1_CH7_IRQ:1;        /* TIM1 shared interrupt channel 7. */
      vuint32_t TIM1_CH6_IRQ:1;        /* TIM1 shared interrupt channel 6. */
      vuint32_t TIM1_CH5_IRQ:1;        /* TIM1 shared interrupt channel 5. */
      vuint32_t TIM1_CH4_IRQ:1;        /* TIM1 shared interrupt channel 4. */
      vuint32_t TIM1_CH3_IRQ:1;        /* TIM1 shared interrupt channel 3. */
      vuint32_t TIM1_CH2_IRQ:1;        /* TIM1 shared interrupt channel 2. */
      vuint32_t TIM1_CH1_IRQ:1;        /* TIM1 shared interrupt channel 1. */
      vuint32_t TIM1_CH0_IRQ:1;        /* TIM1 shared interrupt channel 0. */
      vuint32_t TIM0_CH7_IRQ:1;        /* TIM0 shared interrupt channel 7. */
      vuint32_t TIM0_CH6_IRQ:1;        /* TIM0 shared interrupt channel 6. */
      vuint32_t TIM0_CH5_IRQ:1;        /* TIM0 shared interrupt channel 5. */
      vuint32_t TIM0_CH4_IRQ:1;        /* TIM0 shared interrupt channel 4. */
      vuint32_t TIM0_CH3_IRQ:1;        /* TIM0 shared interrupt channel 3. */
      vuint32_t TIM0_CH2_IRQ:1;        /* TIM0 shared interrupt channel 2. */
      vuint32_t TIM0_CH1_IRQ:1;        /* TIM0 shared interrupt channel 1. */
      vuint32_t TIM0_CH0_IRQ:1;        /* TIM0 shared interrupt channel 0. */
    } B;
  } IRQG_2;

  union {                              /* TIM Interrupt Group 1 Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t TIM6_CH7_IRQ:1;        /* TIM6 shared interrupt channel 7. */
      vuint32_t TIM6_CH6_IRQ:1;        /* TIM6 shared interrupt channel 6. */
      vuint32_t TIM6_CH5_IRQ:1;        /* TIM6 shared interrupt channel 5. */
      vuint32_t TIM6_CH4_IRQ:1;        /* TIM6 shared interrupt channel 4. */
      vuint32_t TIM6_CH3_IRQ:1;        /* TIM6 shared interrupt channel 3. */
      vuint32_t TIM6_CH2_IRQ:1;        /* TIM6 shared interrupt channel 2. */
      vuint32_t TIM6_CH1_IRQ:1;        /* TIM6 shared interrupt channel 1. */
      vuint32_t TIM6_CH0_IRQ:1;        /* TIM6 shared interrupt channel 0. */
      vuint32_t TIM5_CH7_IRQ:1;        /* TIM5 shared interrupt channel 7. */
      vuint32_t TIM5_CH6_IRQ:1;        /* TIM5 shared interrupt channel 6. */
      vuint32_t TIM5_CH5_IRQ:1;        /* TIM5 shared interrupt channel 5. */
      vuint32_t TIM5_CH4_IRQ:1;        /* TIM5 shared interrupt channel 4. */
      vuint32_t TIM5_CH3_IRQ:1;        /* TIM5 shared interrupt channel 3. */
      vuint32_t TIM5_CH2_IRQ:1;        /* TIM5 shared interrupt channel 2. */
      vuint32_t TIM5_CH1_IRQ:1;        /* TIM5 shared interrupt channel 1. */
      vuint32_t TIM5_CH0_IRQ:1;        /* TIM5 shared interrupt channel 0. */
      vuint32_t TIM4_CH7_IRQ:1;        /* TIM4 shared interrupt channel 7. */
      vuint32_t TIM4_CH6_IRQ:1;        /* TIM4 shared interrupt channel 6. */
      vuint32_t TIM4_CH5_IRQ:1;        /* TIM4 shared interrupt channel 5. */
      vuint32_t TIM4_CH4_IRQ:1;        /* TIM4 shared interrupt channel 4. */
      vuint32_t TIM4_CH3_IRQ:1;        /* TIM4 shared interrupt channel 3. */
      vuint32_t TIM4_CH2_IRQ:1;        /* TIM4 shared interrupt channel 2. */
      vuint32_t TIM4_CH1_IRQ:1;        /* TIM4 shared interrupt channel 1. */
      vuint32_t TIM4_CH0_IRQ:1;        /* TIM4 shared interrupt channel 0. */
    } B;
  } IRQG_3;

  union {                              /* MCS Interrupt Group 0 Register */
    vuint32_t R;
    struct {
      vuint32_t MCS3_CH7_IRQ:1;        /* MCS3 channel 7 interrupt. */
      vuint32_t MCS3_CH6_IRQ:1;        /* MCS3 channel 6 interrupt. */
      vuint32_t MCS3_CH5_IRQ:1;        /* MCS3 channel 5 interrupt. */
      vuint32_t MCS3_CH4_IRQ:1;        /* MCS3 channel 4 interrupt. */
      vuint32_t MCS3_CH3_IRQ:1;        /* MCS3 channel 3 interrupt. */
      vuint32_t MCS3_CH2_IRQ:1;        /* MCS3 channel 2 interrupt. */
      vuint32_t MCS3_CH1_IRQ:1;        /* MCS3 channel 1 interrupt. */
      vuint32_t MCS3_CH0_IRQ:1;        /* MCS3 channel 0 interrupt. */
      vuint32_t MCS2_CH7_IRQ:1;        /* MCS2 channel 7 interrupt. */
      vuint32_t MCS2_CH6_IRQ:1;        /* MCS2 channel 6 interrupt. */
      vuint32_t MCS2_CH5_IRQ:1;        /* MCS2 channel 5 interrupt. */
      vuint32_t MCS2_CH4_IRQ:1;        /* MCS2 channel 4 interrupt. */
      vuint32_t MCS2_CH3_IRQ:1;        /* MCS2 channel 3 interrupt. */
      vuint32_t MCS2_CH2_IRQ:1;        /* MCS2 channel 2 interrupt. */
      vuint32_t MCS2_CH1_IRQ:1;        /* MCS2 channel 1 interrupt. */
      vuint32_t MCS2_CH0_IRQ:1;        /* MCS2 channel 0 interrupt. */
      vuint32_t MCS1_CH7_IRQ:1;        /* MCS1 channel 7 interrupt. */
      vuint32_t MCS1_CH6_IRQ:1;        /* MCS1 channel 6 interrupt. */
      vuint32_t MCS1_CH5_IRQ:1;        /* MCS1 channel 5 interrupt. */
      vuint32_t MCS1_CH4_IRQ:1;        /* MCS1 channel 4 interrupt. */
      vuint32_t MCS1_CH3_IRQ:1;        /* MCS1 channel 3 interrupt. */
      vuint32_t MCS1_CH2_IRQ:1;        /* MCS1 channel 2 interrupt. */
      vuint32_t MCS1_CH1_IRQ:1;        /* MCS1 channel 1 interrupt. */
      vuint32_t MCS1_CH0_IRQ:1;        /* MCS1 channel 0 interrupt. */
      vuint32_t MCS0_CH7_IRQ:1;        /* MCS0 channel 7 interrupt. */
      vuint32_t MCS0_CH6_IRQ:1;        /* MCS0 channel 6 interrupt. */
      vuint32_t MCS0_CH5_IRQ:1;        /* MCS0 channel 5 interrupt. */
      vuint32_t MCS0_CH4_IRQ:1;        /* MCS0 channel 4 interrupt. */
      vuint32_t MCS0_CH3_IRQ:1;        /* MCS0 channel 3 interrupt. */
      vuint32_t MCS0_CH2_IRQ:1;        /* MCS0 channel 2 interrupt. */
      vuint32_t MCS0_CH1_IRQ:1;        /* MCS0 channel 1 interrupt. */
      vuint32_t MCS0_CH0_IRQ:1;        /* MCS0 channel 0 interrupt. */
    } B;
  } IRQG_4;

  union {                              /* MCS Interrupt Group 1 Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t MCS6_CH7_IRQ:1;        /* MCS6 channel 7 interrupt. */
      vuint32_t MCS6_CH6_IRQ:1;        /* MCS6 channel 6 interrupt. */
      vuint32_t MCS6_CH5_IRQ:1;        /* MCS6 channel 5 interrupt. */
      vuint32_t MCS6_CH4_IRQ:1;        /* MCS6 channel 4 interrupt. */
      vuint32_t MCS6_CH3_IRQ:1;        /* MCS6 channel 3 interrupt. */
      vuint32_t MCS6_CH2_IRQ:1;        /* MCS6 channel 2 interrupt. */
      vuint32_t MCS6_CH1_IRQ:1;        /* MCS6 channel 1 interrupt. */
      vuint32_t MCS6_CH0_IRQ:1;        /* MCS6 channel 0 interrupt. */
      vuint32_t MCS5_CH7_IRQ:1;        /* MCS5 channel 7 interrupt. */
      vuint32_t MCS5_CH6_IRQ:1;        /* MCS5 channel 6 interrupt. */
      vuint32_t MCS5_CH5_IRQ:1;        /* MCS5 channel 5 interrupt. */
      vuint32_t MCS5_CH4_IRQ:1;        /* MCS5 channel 4 interrupt. */
      vuint32_t MCS5_CH3_IRQ:1;        /* MCS5 channel 3 interrupt. */
      vuint32_t MCS5_CH2_IRQ:1;        /* MCS5 channel 2 interrupt. */
      vuint32_t MCS5_CH1_IRQ:1;        /* MCS5 channel 1 interrupt. */
      vuint32_t MCS5_CH0_IRQ:1;        /* MCS5 channel 0 interrupt. */
      vuint32_t MCS4_CH7_IRQ:1;        /* MCS4 channel 7 interrupt. */
      vuint32_t MCS4_CH6_IRQ:1;        /* MCS4 channel 6 interrupt. */
      vuint32_t MCS4_CH5_IRQ:1;        /* MCS4 channel 5 interrupt. */
      vuint32_t MCS4_CH4_IRQ:1;        /* MCS4 channel 4 interrupt. */
      vuint32_t MCS4_CH3_IRQ:1;        /* MCS4 channel 3 interrupt. */
      vuint32_t MCS4_CH2_IRQ:1;        /* MCS4 channel 2 interrupt. */
      vuint32_t MCS4_CH1_IRQ:1;        /* MCS4 channel 1 interrupt. */
      vuint32_t MCS4_CH0_IRQ:1;        /* MCS4 channel 0 interrupt. */
    } B;
  } IRQG_5;

  union {                              /* TOM Interrupt Group 0 Register */
    vuint32_t R;
    struct {
      vuint32_t TOM1_CH15_IRQ:1;       /* TOM1 channel 15 shared interrupt. */
      vuint32_t TOM1_CH14_IRQ:1;       /* TOM1 channel 14 shared interrupt. */
      vuint32_t TOM1_CH13_IRQ:1;       /* TOM1 channel 13 shared interrupt. */
      vuint32_t TOM1_CH12_IRQ:1;       /* TOM1 channel 12 shared interrupt. */
      vuint32_t TOM1_CH11_IRQ:1;       /* TOM1 channel 11 shared interrupt. */
      vuint32_t TOM1_CH10_IRQ:1;       /* TOM1 channel 10 shared interrupt. */
      vuint32_t TOM1_CH9_IRQ:1;        /* TOM1 channel 9 shared interrupt. */
      vuint32_t TOM1_CH8_IRQ:1;        /* TOM1 channel 8 shared interrupt. */
      vuint32_t TOM1_CH7_IRQ:1;        /* TOM1 channel 7 shared interrupt. */
      vuint32_t TOM1_CH6_IRQ:1;        /* TOM1 channel 6 shared interrupt. */
      vuint32_t TOM1_CH5_IRQ:1;        /* TOM1 channel 5 shared interrupt. */
      vuint32_t TOM1_CH4_IRQ:1;        /* TOM1 channel 4 shared interrupt. */
      vuint32_t TOM1_CH3_IRQ:1;        /* TOM1 channel 3 shared interrupt. */
      vuint32_t TOM1_CH2_IRQ:1;        /* TOM1 channel 2 shared interrupt. */
      vuint32_t TOM1_CH1_IRQ:1;        /* TOM1 channel 1 shared interrupt. */
      vuint32_t TOM1_CH0_IRQ:1;        /* TOM1 channel 0 shared interrupt. */
      vuint32_t TOM0_CH15_IRQ:1;       /* TOM0 channel 15 shared interrupt. */
      vuint32_t TOM0_CH14_IRQ:1;       /* TOM0 channel 14 shared interrupt. */
      vuint32_t TOM0_CH13_IRQ:1;       /* TOM0 channel 13 shared interrupt. */
      vuint32_t TOM0_CH12_IRQ:1;       /* TOM0 channel 12 shared interrupt. */
      vuint32_t TOM0_CH11_IRQ:1;       /* TOM0 channel 11 shared interrupt. */
      vuint32_t TOM0_CH10_IRQ:1;       /* TOM0 channel 10 shared interrupt. */
      vuint32_t TOM0_CH9_IRQ:1;        /* TOM0 channel 9 shared interrupt. */
      vuint32_t TOM0_CH8_IRQ:1;        /* TOM0 channel 8 shared interrupt. */
      vuint32_t TOM0_CH7_IRQ:1;        /* TOM0 channel 7 shared interrupt. */
      vuint32_t TOM0_CH6_IRQ:1;        /* TOM0 channel 6 shared interrupt. */
      vuint32_t TOM0_CH5_IRQ:1;        /* TOM0 channel 5 shared interrupt. */
      vuint32_t TOM0_CH4_IRQ:1;        /* TOM0 channel 4 shared interrupt. */
      vuint32_t TOM0_CH3_IRQ:1;        /* TOM0 channel 3 shared interrupt. */
      vuint32_t TOM0_CH2_IRQ:1;        /* TOM0 channel 2 shared interrupt. */
      vuint32_t TOM0_CH1_IRQ:1;        /* TOM0 channel 1 shared interrupt */
      vuint32_t TOM0_CH0_IRQ:1;        /* TOM0 channel 0 shared interrupt. */
    } B;
  } IRQG_6;

  union {                              /* TOM Interrupt Group 1 Register */
    vuint32_t R;
    struct {
      vuint32_t TOM3_CH15_IRQ:1;       /* TOM3 channel 15 shared interrupt. */
      vuint32_t TOM3_CH14_IRQ:1;       /* TOM3 channel 14 shared interrupt. */
      vuint32_t TOM3_CH13_IRQ:1;       /* TOM3 channel 13 shared interrupt. */
      vuint32_t TOM3_CH12_IRQ:1;       /* TOM3 channel 12 shared interrupt. */
      vuint32_t TOM3_CH11_IRQ:1;       /* TOM3 channel 11 shared interrupt. */
      vuint32_t TOM3_CH10_IRQ:1;       /* TOM3 channel 10 shared interrupt. */
      vuint32_t TOM3_CH9_IRQ:1;        /* TOM3 channel 9 shared interrupt. */
      vuint32_t TOM3_CH8_IRQ:1;        /* TOM3 channel 8 shared interrupt. */
      vuint32_t TOM3_CH7_IRQ:1;        /* TOM3 channel 7 shared interrupt. */
      vuint32_t TOM3_CH6_IRQ:1;        /* TOM3 channel 7 shared interrupt. */
      vuint32_t TOM3_CH5_IRQ:1;        /* TOM3 channel 5 shared interrupt. */
      vuint32_t TOM3_CH4_IRQ:1;        /* TOM3 channel 4 shared interrupt. */
      vuint32_t TOM3_CH3_IRQ:1;        /* TOM3 channel 3 shared interrupt. */
      vuint32_t TOM3_CH2_IRQ:1;        /* TOM3 channel 2 shared interrupt. */
      vuint32_t TOM3_CH1_IRQ:1;        /* TOM3 channel 1 shared interrupt. */
      vuint32_t TOM3_CH0_IRQ:1;        /* TOM3 channel 0 shared interrupt. */
      vuint32_t TOM2_CH15_IRQ:1;       /* TOM2 channel 15 shared interrupt. */
      vuint32_t TOM2_CH14_IRQ:1;       /* TOM2 channel 14 shared interrupt. */
      vuint32_t TOM2_CH13_IRQ:1;       /* TOM2 channel 13 shared interrupt. */
      vuint32_t TOM2_CH12_IRQ:1;       /* TOM2 channel 12 shared interrupt. */
      vuint32_t TOM2_CH11_IRQ:1;       /* TOM2 channel 11 shared interrupt. */
      vuint32_t TOM2_CH10_IRQ:1;       /* TOM2 channel 10 shared interrupt. */
      vuint32_t TOM2_CH9_IRQ:1;        /* TOM2 channel 9 shared interrupt. */
      vuint32_t TOM2_CH8_IRQ:1;        /* TOM2 channel 8 shared interrupt. */
      vuint32_t TOM2_CH7_IRQ:1;        /* TOM2 channel 7 shared interrupt. */
      vuint32_t TOM2_CH6_IRQ:1;        /* TOM2 channel 6 shared interrupt. */
      vuint32_t TOM2_CH5_IRQ:1;        /* TOM2 channel 5 shared interrupt. */
      vuint32_t TOM2_CH4_IRQ:1;        /* TOM2 channel 4 shared interrupt. */
      vuint32_t TOM2_CH3_IRQ:1;        /* TOM2 channel 3 shared interrupt. */
      vuint32_t TOM2_CH2_IRQ:1;        /* TOM2 channel 2 shared interrupt. */
      vuint32_t TOM2_CH1_IRQ:1;        /* TOM2 channel 1 shared interrupt */
      vuint32_t TOM2_CH0_IRQ:1;        /* TOM2 channel 0 shared interrupt. */
    } B;
  } IRQG_7;

  union {                              /* TOM Interrupt Group 2 Register */
    vuint32_t R;
    struct {
      vuint32_t TOM5_CH15_IRQ:1;       /* TOM5 channel 15 shared interrupt. */
      vuint32_t TOM5_CH14_IRQ:1;       /* TOM5 channel 14 shared interrupt. */
      vuint32_t TOM5_CH13_IRQ:1;       /* TOM5 channel 13 shared interrupt. */
      vuint32_t TOM5_CH12_IRQ:1;       /* TOM5 channel 12 shared interrupt. */
      vuint32_t TOM5_CH11_IRQ:1;       /* TOM5 channel 11 shared interrupt. */
      vuint32_t TOM5_CH10_IRQ:1;       /* TOM5 channel 10 shared interrupt. */
      vuint32_t TOM5_CH9_IRQ:1;        /* TOM5 channel 9 shared interrupt. */
      vuint32_t TOM5_CH8_IRQ:1;        /* TOM5 channel 8 shared interrupt. */
      vuint32_t TOM5_CH7_IRQ:1;        /* TOM5 channel 7 shared interrupt. */
      vuint32_t TOM5_CH6_IRQ:1;        /* TOM5 channel 6 shared interrupt. */
      vuint32_t TOM5_CH5_IRQ:1;        /* TOM5 channel 5 shared interrupt. */
      vuint32_t TOM5_CH4_IRQ:1;        /* TOM5 channel 4 shared interrupt. */
      vuint32_t TOM5_CH3_IRQ:1;        /* TOM5 channel 3 shared interrupt. */
      vuint32_t TOM5_CH2_IRQ:1;        /* TOM5 channel 2 shared interrupt. */
      vuint32_t TOM5_CH1_IRQ:1;        /* TOM5 channel 1 shared interrupt. */
      vuint32_t TOM5_CH0_IRQ:1;        /* TOM5 channel 0 shared interrupt. */
      vuint32_t TOM4_CH15_IRQ:1;       /* TOM4 channel 15 shared interrupt. */
      vuint32_t TOM4_CH14_IRQ:1;       /* TOM4 channel 14 shared interrupt. */
      vuint32_t TOM4_CH13_IRQ:1;       /* TOM4 channel 13 shared interrupt. */
      vuint32_t TOM4_CH12_IRQ:1;       /* TOM4 channel 12 shared interrupt. */
      vuint32_t TOM4_CH11_IRQ:1;       /* TOM4 channel 11 shared interrupt. */
      vuint32_t TOM4_CH10_IRQ:1;       /* TOM4 channel 10 shared interrupt. */
      vuint32_t TOM4_CH9_IRQ:1;        /* TOM4 channel 9 shared interrupt. */
      vuint32_t TOM4_CH8_IRQ:1;        /* TOM4 channel 8 shared interrupt. */
      vuint32_t TOM4_CH7_IRQ:1;        /* TOM4 channel 7 shared interrupt. */
      vuint32_t TOM4_CH6_IRQ:1;        /* TOM4 channel 6 shared interrupt. */
      vuint32_t TOM4_CH5_IRQ:1;        /* TOM4 channel 5 shared interrupt. */
      vuint32_t TOM4_CH4_IRQ:1;        /* TOM4 channel 4 shared interrupt. */
      vuint32_t TOM4_CH3_IRQ:1;        /* TOM4 channel 3 shared interrupt. */
      vuint32_t TOM4_CH2_IRQ:1;        /* TOM4 channel 2 shared interrupt. */
      vuint32_t TOM4_CH1_IRQ:1;        /* TOM4 channel 1 shared interrupt */
      vuint32_t TOM4_CH0_IRQ:1;        /* TOM4 channel 0 shared interrupt. */
    } B;
  } IRQG_8;

  union {                              /* ATOM Interrupt Group 0 Register */
    vuint32_t R;
    struct {
      vuint32_t ATOM3_CH7_IRQ:1;       /* ATOM3 channel 7 interrupt. */
      vuint32_t ATOM3_CH6_IRQ:1;       /* ATOM3 channel 6 interrupt. */
      vuint32_t ATOM3_CH5_IRQ:1;       /* ATOM3 channel 5 interrupt. */
      vuint32_t ATOM3_CH4_IRQ:1;       /* ATOM3 channel 4 interrupt. */
      vuint32_t ATOM3_CH3_IRQ:1;       /* ATOM3 channel 3 interrupt. */
      vuint32_t ATOM3_CH2_IRQ:1;       /* ATOM3 channel 2 interrupt. */
      vuint32_t ATOM3_CH1_IRQ:1;       /* ATOM3 channel 1 interrupt. */
      vuint32_t ATOM3_CH0_IRQ:1;       /* ATOM3 channel 0 interrupt. */
      vuint32_t ATOM2_CH7_IRQ:1;       /* ATOM2 channel 7 interrupt. */
      vuint32_t ATOM2_CH6_IRQ:1;       /* ATOM2 channel 6 interrupt. */
      vuint32_t ATOM2_CH5_IRQ:1;       /* ATOM2 channel 5 interrupt. */
      vuint32_t ATOM2_CH4_IRQ:1;       /* ATOM2 channel 4 interrupt. */
      vuint32_t ATOM2_CH3_IRQ:1;       /* ATOM2 channel 3 interrupt. */
      vuint32_t ATOM2_CH2_IRQ:1;       /* ATOM2 channel 2 interrupt. */
      vuint32_t ATOM2_CH1_IRQ:1;       /* ATOM2 channel 1 interrupt. */
      vuint32_t ATOM2_CH0_IRQ:1;       /* ATOM2 channel 0 interrupt. */
      vuint32_t ATOM1_CH7_IRQ:1;       /* ATOM1 channel 7 interrupt. */
      vuint32_t ATOM1_CH6_IRQ:1;       /* ATOM1 channel 6 interrupt. */
      vuint32_t ATOM1_CH5_IRQ:1;       /* ATOM1 channel 5 interrupt. */
      vuint32_t ATOM1_CH4_IRQ:1;       /* ATOM1 channel 4 interrupt. */
      vuint32_t ATOM1_CH3_IRQ:1;       /* ATOM1 channel 3 interrupt. */
      vuint32_t ATOM1_CH2_IRQ:1;       /* ATOM1 channel 2 interrupt. */
      vuint32_t ATOM1_CH1_IRQ:1;       /* ATOM1 channel 1 interrupt. */
      vuint32_t ATOM1_CH0_IRQ:1;       /* ATOM1 channel 0 interrupt. */
      vuint32_t ATOM0_CH7_IRQ:1;       /* ATOM0 channel 7 interrupt. */
      vuint32_t ATOM0_CH6_IRQ:1;       /* ATOM0 channel 6 interrupt. */
      vuint32_t ATOM0_CH5_IRQ:1;       /* ATOM0 channel 5 interrupt. */
      vuint32_t ATOM0_CH4_IRQ:1;       /* ATOM0 channel 4 interrupt. */
      vuint32_t ATOM0_CH3_IRQ:1;       /* ATOM0 channel 3 interrupt. */
      vuint32_t ATOM0_CH2_IRQ:1;       /* ATOM0 channel 2 interrupt. */
      vuint32_t ATOM0_CH1_IRQ:1;       /* ATOM0 channel 1 interrupt. */
      vuint32_t ATOM0_CH0_IRQ:1;       /* ATOM0 channel 0 interrupt. */
    } B;
  } IRQG_9;

  union {                              /* ATOM Interrupt Group 1 Register */
    vuint32_t R;
    struct {
      vuint32_t ATOM7_CH7_IRQ:1;       /* ATOM7 channel 7 interrupt. */
      vuint32_t ATOM7_CH6_IRQ:1;       /* ATOM7 channel 6 interrupt. */
      vuint32_t ATOM7_CH5_IRQ:1;       /* ATOM7 channel 5 interrupt. */
      vuint32_t ATOM7_CH4_IRQ:1;       /* ATOM7 channel 4 interrupt. */
      vuint32_t ATOM7_CH3_IRQ:1;       /* ATOM7 channel 3 interrupt. */
      vuint32_t ATOM7_CH2_IRQ:1;       /* ATOM7 channel 2 interrupt. */
      vuint32_t ATOM7_CH1_IRQ:1;       /* ATOM7 channel 1 interrupt. */
      vuint32_t ATOM7_CH0_IRQ:1;       /* ATOM7 channel 0 interrupt. */
      vuint32_t ATOM6_CH7_IRQ:1;       /* ATOM6 channel 7 interrupt. */
      vuint32_t ATOM6_CH6_IRQ:1;       /* ATOM6 channel 6 interrupt. */
      vuint32_t ATOM6_CH5_IRQ:1;       /* ATOM6 channel 5 interrupt. */
      vuint32_t ATOM6_CH4_IRQ:1;       /* ATOM channel 4 interrupt. */
      vuint32_t ATOM6_CH3_IRQ:1;       /* ATOM6 channel 3 interrupt. */
      vuint32_t ATOM6_CH2_IRQ:1;       /* ATOM6 channel 2 interrupt. */
      vuint32_t ATOM6_CH1_IRQ:1;       /* ATOM6 channel 1 interrupt. */
      vuint32_t ATOM6_CH0_IRQ:1;       /* ATOM6 channel 0 interrupt. */
      vuint32_t ATOM5_CH7_IRQ:1;       /* ATOM5 channel 7 interrupt. */
      vuint32_t ATOM5_CH6_IRQ:1;       /* ATOM5 channel 6 interrupt. */
      vuint32_t ATOM5_CH5_IRQ:1;       /* ATOM5 channel 5 interrupt. */
      vuint32_t ATOM5_CH4_IRQ:1;       /* ATOM5 channel 4 interrupt. */
      vuint32_t ATOM5_CH3_IRQ:1;       /* ATOM5 channel 3 interrupt. */
      vuint32_t ATOM5_CH2_IRQ:1;       /* ATOM5 channel 2 interrupt. */
      vuint32_t ATOM5_CH1_IRQ:1;       /* ATOM5 channel 1 interrupt. */
      vuint32_t ATOM5_CH0_IRQ:1;       /* ATOM5 channel 0 interrupt. */
      vuint32_t ATOM4_CH7_IRQ:1;       /* ATOM4 channel 7 interrupt. */
      vuint32_t ATOM4_CH6_IRQ:1;       /* ATOM4 channel 6 interrupt. */
      vuint32_t ATOM4_CH5_IRQ:1;       /* ATOM4 channel 5 interrupt. */
      vuint32_t ATOM4_CH4_IRQ:1;       /* ATOM4 channel 4 interrupt. */
      vuint32_t ATOM4_CH3_IRQ:1;       /* ATOM4 channel 3 interrupt. */
      vuint32_t ATOM4_CH2_IRQ:1;       /* ATOM4 channel 2 interrupt. */
      vuint32_t ATOM4_CH1_IRQ:1;       /* ATOM4 channel 1 interrupt. */
      vuint32_t ATOM4_CH0_IRQ:1;       /* ATOM4 channel 0 interrupt. */
    } B;
  } IRQG_10;

  union {                              /* ATOM Interrupt Group 2 Register */
    vuint32_t R;
    struct {
      vuint32_t ATOM11_CH7_IRQ:1;      /* ATOM11 channel 7 interrupt. */
      vuint32_t ATOM11_CH6_IRQ:1;      /* ATOM11 channel 6 interrupt. */
      vuint32_t ATOM11_CH5_IRQ:1;      /* ATOM11 channel 5 interrupt. */
      vuint32_t ATOM11_CH4_IRQ:1;      /* ATOM11 channel 4 interrupt. */
      vuint32_t ATOM11_CH3_IRQ:1;      /* ATOM11 channel 3 interrupt. */
      vuint32_t ATOM11_CH2_IRQ:1;      /* ATOM11 channel 2 interrupt. */
      vuint32_t ATOM11_CH1_IRQ:1;      /* ATOM11 channel 1 interrupt. */
      vuint32_t ATOM11_CH0_IRQ:1;      /* ATOM11 channel 0 interrupt. */
      vuint32_t ATOM10_CH7_IRQ:1;      /* ATOM10 channel 7 interrupt. */
      vuint32_t ATOM10_CH6_IRQ:1;      /* ATOM10 channel 6 interrupt. */
      vuint32_t ATOM10_CH5_IRQ:1;      /* ATOM10 channel 5 interrupt. */
      vuint32_t ATOM10_CH4_IRQ:1;      /* ATOM10 channel 4 interrupt. */
      vuint32_t ATOM10_CH3_IRQ:1;      /* ATOM10 channel 3 interrupt. */
      vuint32_t ATOM10_CH2_IRQ:1;      /* ATOM10 channel 2 interrupt. */
      vuint32_t ATOM10_CH1_IRQ:1;      /* ATOM10 channel 1 interrupt. */
      vuint32_t ATOM10_CH0_IRQ:1;      /* ATOM10 channel 0 interrupt. */
      vuint32_t ATOM9_CH7_IRQ:1;       /* ATOM9 channel 7 interrupt. */
      vuint32_t ATOM9_CH6_IRQ:1;       /* ATOM9 channel 6 interrupt. */
      vuint32_t ATOM9_CH5_IRQ:1;       /* ATOM9 channel 5 interrupt. */
      vuint32_t ATOM9_CH4_IRQ:1;       /* ATOM9 channel 4 interrupt. */
      vuint32_t ATOM9_CH3_IRQ:1;       /* ATOM9 channel 3 interrupt. */
      vuint32_t ATOM9_CH2_IRQ:1;       /* ATOM9 channel 2 interrupt. */
      vuint32_t ATOM9_CH1_IRQ:1;       /* ATOM9 channel 1 interrupt. */
      vuint32_t ATOM9_CH0_IRQ:1;       /* ATOM9 channel 0 interrupt. */
      vuint32_t ATOM8_CH7_IRQ:1;       /* ATOM8 channel 7 interrupt. */
      vuint32_t ATOM8_CH6_IRQ:1;       /* ATOM8 channel 6 interrupt. */
      vuint32_t ATOM8_CH5_IRQ:1;       /* ATOM8 channel 5 interrupt. */
      vuint32_t ATOM8_CH4_IRQ:1;       /* ATOM8 channel 4 interrupt. */
      vuint32_t ATOM4_CH3_IR8:1;       /* ATOM8 channel 3 interrupt. */
      vuint32_t ATOM8_CH2_IRQ:1;       /* ATOM8 channel 2 interrupt. */
      vuint32_t ATOM8_CH1_IRQ:1;       /* ATOM8 channel 1 interrupt. */
      vuint32_t ATOM8_CH0_IRQ:1;       /* ATOM8 channel 0 interrupt. */
    } B;
  } IRQG_11;

  union {                              /* ICM IRQG Module Error Interrupt register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t DPLL_EIRQ:1;           /* DPLL error interrupt. */
      vuint32_t CMP_EIRQ:1;            /* CMP error interrupt. */
      vuint32_t SPE3_EIRQ:1;           /* SPE3 error interrupt. */
      vuint32_t SPE2_EIRQ:1;           /* SPE2 error interrupt. */
      vuint32_t SPE1_EIRQ:1;           /* SPE1 error interrupt. */
      vuint32_t SPE0_EIRQ:1;           /* SPE0 error interrupt. */
      vuint32_t  :1;
      vuint32_t MCS6_EIRQ:1;           /* MCS6 error interrupt. */
      vuint32_t MCS5_EIRQ:1;           /* MCS5 error interrupt. */
      vuint32_t MCS4_EIRQ:1;           /* MCS4 error interrupt. */
      vuint32_t MCS3_EIRQ:1;           /* MCS3 error interrupt. */
      vuint32_t MCS2_EIRQ:1;           /* MCS2 error interrupt. */
      vuint32_t MCS1_EIRQ:1;           /* MCS1 error interrupt */
      vuint32_t MCS0_EIRQ:1;           /* MCS0 error interrupt. */
      vuint32_t  :1;
      vuint32_t TIM6_EIRQ:1;           /* TIM6 error interrupt. */
      vuint32_t TIM5_EIRQ:1;           /* TIM5 error interrupt. */
      vuint32_t TIM4_EIRQ:1;           /* TIM4 error interrupt. */
      vuint32_t TIM3_EIRQ:1;           /* TIM3 error interrupt. */
      vuint32_t TIM2_EIRQ:1;           /* TIM2 error interrupt. */
      vuint32_t TIM1_EIRQ:1;           /* TIM1 error interrupt. */
      vuint32_t TIM0_EIRQ:1;           /* TIM0 error interrupt. */
      vuint32_t FIFO1_EIRQ:1;          /* FIFO1 error interrupt. */
      vuint32_t FIFO0_EIRQ:1;          /* FIFO0 error interrupt. */
      vuint32_t BRC_EIRQ:1;            /* BRC error interrupt. */
      vuint32_t GTM_EIRQ:1;            /* GTM Error interrupt request. */
    } B;
  } IRQG_MEI;

  union {                              /* ICM Channel Error Interrupt Request Group 0 register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t FIFO1_CH7_EIRQ:1;      /* FIFO1 channel 7 error interrupt */
      vuint32_t FIFO1_CH6_EIRQ:1;      /* FIFO1 channel 6 error interrupt */
      vuint32_t FIFO1_CH5_EIRQ:1;      /* FIFO1 channel 5 error interrupt */
      vuint32_t FIFO1_CH4_EIRQ:1;      /* FIFO1 channel 4 error interrupt */
      vuint32_t FIFO1_CH3_EIRQ:1;      /* FIFO1 channel 3 error interrupt */
      vuint32_t FIFO1_CH2_EIRQ:1;      /* FIFO1 channel 2 error interrupt */
      vuint32_t FIFO1_CH1_EIRQ:1;      /* FIFO1 channel 1 error interrupt */
      vuint32_t FIFO1_CH0_EIRQ:1;      /* FIFO1 channel 0 error interrupt */
      vuint32_t FIFO0_CH7_EIRQ:1;      /* FIFO0 channel 7 error interrupt */
      vuint32_t FIFO0_CH6_EIRQ:1;      /* FIFO0 channel 6 error interrupt */
      vuint32_t FIFO0_CH5_EIRQ:1;      /* FIFO0 channel 5 error interrupt */
      vuint32_t FIFO0_CH4_EIRQ:1;      /* FIFO0 channel 4 error interrupt */
      vuint32_t FIFO0_CH3_EIRQ:1;      /* FIFO0 channel 3 error interrupt */
      vuint32_t FIFO0_CH2_EIRQ:1;      /* FIFO0 channel 2 error interrupt */
      vuint32_t FIFO0_CH1_EIRQ:1;      /* FIFO0 channel 1 error interrupt */
      vuint32_t FIFO0_CH0_EIRQ:1;      /* FIFO0 channel 0 error interrupt */
    } B;
  } IRQG_CEI0;

  union {                              /* Channel Error Interrupt Request Group 1 register */
    vuint32_t R;
    struct {
      vuint32_t TIM3_CH7_EIRQ:1;       /* TIM3 Channel 7 Error interrupt */
      vuint32_t TIM3_CH6_EIRQ:1;       /* TIM3 Channel 6 Error interrupt */
      vuint32_t TIM3_CH5_EIRQ:1;       /* TIM3 Channel 5 Error interrupt */
      vuint32_t TIM3_CH4_EIRQ:1;       /* TIM3 Channel 4 Error interrupt */
      vuint32_t TIM3_CH3_EIRQ:1;       /* TIM3 Channel 3 Error interrupt */
      vuint32_t TIM3_CH2_EIRQ:1;       /* TIM3 Channel 2 Error interrupt */
      vuint32_t TIM3_CH1_EIRQ:1;       /* TIM3 Channel 1 Error interrupt */
      vuint32_t TIM3_CH0_EIRQ:1;       /* TIM3 Channel 0 Error interrupt */
      vuint32_t TIM2_CH7_EIRQ:1;       /* TIM2 Channel 7 Error interrupt */
      vuint32_t TIM2_CH6_EIRQ:1;       /* TIM2 Channel 6 Error interrupt */
      vuint32_t TIM2_CH5_EIRQ:1;       /* TIM2 Channel 5 Error interrupt */
      vuint32_t TIM2_CH4_EIRQ:1;       /* TIM2 Channel 4 Error interrupt */
      vuint32_t TIM2_CH3_EIRQ:1;       /* TIM2 Channel 3 Error interrupt */
      vuint32_t TIM2_CH2_EIRQ:1;       /* TIM2 Channel 2 Error interrupt */
      vuint32_t TIM2_CH1_EIRQ:1;       /* TIM2 Channel 1 Error interrupt */
      vuint32_t TIM2_CH0_EIRQ:1;       /* TIM2 Channel 0 Error interrupt */
      vuint32_t TIM1_CH7_EIRQ:1;       /* TIM1 Channel 7 Error interrupt */
      vuint32_t TIM1_CH6_EIRQ:1;       /* TIM1 Channel 6 Error interrupt */
      vuint32_t TIM1_CH5_EIRQ:1;       /* TIM1 Channel 5 Error interrupt */
      vuint32_t TIM1_CH4_EIRQ:1;       /* TIM1 Channel 4 Error interrupt */
      vuint32_t TIM1_CH3_EIRQ:1;       /* TIM1 Channel 3 Error interrupt */
      vuint32_t TIM1_CH2_EIRQ:1;       /* TIM1 Channel 2 Error interrupt */
      vuint32_t TIM1_CH1_EIRQ:1;       /* TIM1 Channel 1 Error interrupt */
      vuint32_t TIM1_CH0_EIRQ:1;       /* TIM1 Channel 0 Error interrupt */
      vuint32_t TIM0_CH7_EIRQ:1;       /* TIM0 Channel 7 Error interrupt */
      vuint32_t TIM0_CH6_EIRQ:1;       /* TIM0 Channel 6 Error interrupt */
      vuint32_t TIM0_CH5_EIRQ:1;       /* TIM0 Channel 5 Error interrupt */
      vuint32_t TIM0_CH4_EIRQ:1;       /* TIM0 Channel 4 Error interrupt */
      vuint32_t TIM0_CH3_EIRQ:1;       /* TIM0 Channel 3 Error interrupt */
      vuint32_t TIM0_CH2_EIRQ:1;       /* TIM0 Channel 2 Error interrupt */
      vuint32_t TIM0_CH1_EIRQ:1;       /* TIM0 Channel 1 Error interrupt */
      vuint32_t TIM0_CH0_EIRQ:1;       /* TIM0 Channel 0 Error interrupt */
    } B;
  } IRQG_CEI1;

  union {                              /* Channel Error Interrupt Request Group 2 register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t TIM6_CH7_EIRQ:1;       /* TIM6 Channel 7 Error interrupt */
      vuint32_t TIM6_CH6_EIRQ:1;       /* TIM6 Channel 6 Error interrupt */
      vuint32_t TIM6_CH5_EIRQ:1;       /* TIM6 Channel 5 Error interrupt */
      vuint32_t TIM6_CH4_EIRQ:1;       /* TIM6 Channel 4 Error interrupt */
      vuint32_t TIM6_CH3_EIRQ:1;       /* TIM6 Channel 3 Error interrupt */
      vuint32_t TIM6_CH2_EIRQ:1;       /* TIM6 Channel 2 Error interrupt */
      vuint32_t TIM6_CH1_EIRQ:1;       /* TIM6 Channel 1 Error interrupt */
      vuint32_t TIM6_CH0_EIRQ:1;       /* TIM6 Channel 0 Error interrupt */
      vuint32_t TIM5_CH7_EIRQ:1;       /* TIM5 Channel 7 Error interrupt */
      vuint32_t TIM5_CH6_EIRQ:1;       /* TIM5 Channel 6 Error interrupt */
      vuint32_t TIM5_CH5_EIRQ:1;       /* TIM5 Channel 5 Error interrupt */
      vuint32_t TIM5_CH4_EIRQ:1;       /* TIM5 Channel 4 Error interrupt */
      vuint32_t TIM5_CH3_EIRQ:1;       /* TIM5 Channel 3 Error interrupt */
      vuint32_t TIM5_CH2_EIRQ:1;       /* TIM5 Channel 2 Error interrupt */
      vuint32_t TIM5_CH1_EIRQ:1;       /* TIM5 Channel 1 Error interrupt */
      vuint32_t TIM5_CH0_EIRQ:1;       /* TIM5 Channel 0 Error interrupt */
      vuint32_t TIM4_CH7_EIRQ:1;       /* TIM4 Channel 7 Error interrupt */
      vuint32_t TIM4_CH6_EIRQ:1;       /* TIM4 Channel 6 Error interrupt */
      vuint32_t TIM4_CH5_EIRQ:1;       /* TIM4 Channel 5 Error interrupt */
      vuint32_t TIM4_CH4_EIRQ:1;       /* TIM4 Channel 4 Error interrupt */
      vuint32_t TIM4_CH3_EIRQ:1;       /* TIM4 Channel 3 Error interrupt */
      vuint32_t TIM4_CH2_EIRQ:1;       /* TIM4 Channel 2 Error interrupt */
      vuint32_t TIM4_CH1_EIRQ:1;       /* TIM4 Channel 1 Error interrupt */
      vuint32_t TIM4_CH0_EIRQ:1;       /* TIM4 Channel 0 Error interrupt */
    } B;
  } IRQG_CEI2;

  union {                              /* Channel Error Interrupt Request Group 3 register */
    vuint32_t R;
    struct {
      vuint32_t MCS3_CH7_EIRQ:1;       /* MCS3 Channel 7 error interrupt */
      vuint32_t MCS3_CH6_EIRQ:1;       /* MCS3 Channel 6 error interrupt */
      vuint32_t MCS3_CH5_EIRQ:1;       /* MCS3 Channel 5 error interrupt */
      vuint32_t MCS3_CH4_EIRQ:1;       /* MCS3 Channel 4 error interrupt */
      vuint32_t MCS3_CH3_EIRQ:1;       /* MCS3 Channel 3 error interrupt */
      vuint32_t MCS3_CH2_EIRQ:1;       /* MCS3 Channel 2 error interrupt */
      vuint32_t MCS3_CH1_EIRQ:1;       /* MCS3 Channel 1 error interrupt */
      vuint32_t MCS3_CH0_EIRQ:1;       /* MCS3 Channel 0 error interrupt */
      vuint32_t MCS2_CH7_EIRQ:1;       /* MCS2 Channel 7 error interrupt */
      vuint32_t MCS2_CH6_EIRQ:1;       /* MCS2 Channel 6 error interrupt */
      vuint32_t MCS2_CH5_EIRQ:1;       /* MCS2 Channel 5 error interrupt */
      vuint32_t MCS2_CH4_EIRQ:1;       /* MCS2 Channel 4 error interrupt */
      vuint32_t MCS2_CH3_EIRQ:1;       /* MCS2 Channel 3 error interrupt */
      vuint32_t MCS2_CH2_EIRQ:1;       /* MCS2 Channel 2 error interrupt */
      vuint32_t MCS2_CH1_EIRQ:1;       /* MCS2 Channel 1 error interrupt */
      vuint32_t MCS2_CH0_EIRQ:1;       /* MCS2 Channel 0 error interrupt */
      vuint32_t MCS1_CH7_EIRQ:1;       /* MCS1 Channel 7 error interrupt */
      vuint32_t MCS1_CH6_EIRQ:1;       /* MCS1 Channel 6 error interrupt */
      vuint32_t MCS1_CH5_EIRQ:1;       /* MCS1 Channel 5 error interrupt */
      vuint32_t MCS1_CH4_EIRQ:1;       /* MCS1 Channel 4 error interrupt */
      vuint32_t MCS1_CH3_EIRQ:1;       /* MCS1 Channel 3 error interrupt */
      vuint32_t MCS1_CH2_EIRQ:1;       /* MCS1 Channel 2 error interrupt */
      vuint32_t MCS1_CH1_EIRQ:1;       /* MCS1 Channel 1 error interrupt */
      vuint32_t MCS1_CH0_EIRQ:1;       /* MCS1 Channel 0 error interrupt */
      vuint32_t MCS0_CH7_EIRQ:1;       /* MCS0 Channel 7 error interrupt */
      vuint32_t MCS0_CH6_EIRQ:1;       /* MCS0 Channel 6 error interrupt */
      vuint32_t MCS0_CH5_EIRQ:1;       /* MCS0 Channel 5 error interrupt */
      vuint32_t MCS0_CH4_EIRQ:1;       /* MCS0 Channel 4 error interrupt */
      vuint32_t MCS0_CH3_EIRQ:1;       /* MCS0 Channel 3 error interrupt */
      vuint32_t MCS0_CH2_EIRQ:1;       /* MCS0 Channel 2 error interrupt */
      vuint32_t MCS0_CH1_EIRQ:1;       /* MCS0 Channel 1 error interrupt */
      vuint32_t MCS0_CH0_EIRQ:1;       /* MCS0 Channel 0 error interrupt */
    } B;
  } IRQG_CEI3;

  union {                              /* Channel Error Interrupt Request Group 4 register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t MCS6_CH7_EIRQ:1;       /* MCS6 Channel 7 error interrupt */
      vuint32_t MCS6_CH6_EIRQ:1;       /* MCS6 Channel 6 error interrupt */
      vuint32_t MCS6_CH5_EIRQ:1;       /* MCS6 Channel 5 error interrupt */
      vuint32_t MCS6_CH4_EIRQ:1;       /* MCS6 Channel 4 error interrupt */
      vuint32_t MCS6_CH3_EIRQ:1;       /* MCS6 Channel 3 error interrupt */
      vuint32_t MCS6_CH2_EIRQ:1;       /* MCS6 Channel 2 error interrupt */
      vuint32_t MCS6_CH1_EIRQ:1;       /* MCS6 Channel 1 error interrupt */
      vuint32_t MCS6_CH0_EIRQ:1;       /* MCS6 Channel 0 error interrupt */
      vuint32_t MCS5_CH7_EIRQ:1;       /* MCS5 Channel 7 error interrupt */
      vuint32_t MCS5_CH6_EIRQ:1;       /* MCS5 Channel 6 error interrupt */
      vuint32_t MCS5_CH5_EIRQ:1;       /* MCS5 Channel 5 error interrupt */
      vuint32_t MCS5_CH4_EIRQ:1;       /* MCS5 Channel 4 error interrupt */
      vuint32_t MCS5_CH3_EIRQ:1;       /* MCS5 Channel 3 error interrupt */
      vuint32_t MCS5_CH2_EIRQ:1;       /* MCS5 Channel 2 error interrupt */
      vuint32_t MCS5_CH1_EIRQ:1;       /* MCS5 Channel 1 error interrupt */
      vuint32_t MCS5_CH0_EIRQ:1;       /* MCS5 Channel 0 error interrupt */
      vuint32_t MCS4_CH7_EIRQ:1;       /* MCS4 Channel 7 error interrupt */
      vuint32_t MCS4_CH6_EIRQ:1;       /* MCS4 Channel 6 error interrupt */
      vuint32_t MCS4_CH5_EIRQ:1;       /* MCS4 Channel 5 error interrupt */
      vuint32_t MCS4_CH4_EIRQ:1;       /* MCS4 Channel 4 error interrupt */
      vuint32_t MCS4_CH3_EIRQ:1;       /* MCS4 Channel 3 error interrupt */
      vuint32_t MCS4_CH2_EIRQ:1;       /* MCS4 Channel 2 error interrupt */
      vuint32_t MCS4_CH1_EIRQ:1;       /* MCS4 Channel 1 error interrupt */
      vuint32_t MCS4_CH0_EIRQ:1;       /* MCS4 Channel 0 error interrupt */
    } B;
  } IRQG_CEI4;
};


/* ============================================================================
   =============================== Module: GTM_MAP ============================
   ============================================================================ */

struct GTM_MAP_tag {
  union {                              /* TIM0 Input MAP Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t TSPP1_I2V:1;           /* Disable of TSPP1 TIM0_CHz(48) input line. */
      vuint32_t TSPP1_I1V:1;           /* Disable of TSPP1 TIM0_CHy(48) input line. */
      vuint32_t TSPP1_I0V:1;           /* Disable of TSPP1 TIM0_CHx(48) input line. */
      vuint32_t  :2;
      vuint32_t TSPP1_DLD:1;           /* DIR level definition bit. */
      vuint32_t TSPP1_EN:1;            /* Enable of TSPP1 subunit. */
      vuint32_t  :1;
      vuint32_t TSPP0_I2V:1;           /* Disable of TSPP0 TIM0_CHz(48) input line. */
      vuint32_t TSPP0_I1V:1;           /* Disable of TSPP0 TIM0_CHy(48) input line. */
      vuint32_t TSPP0_I0V:1;           /* Disable of TSPP0 TIM0_CHx(48) input line. */
      vuint32_t  :2;
      vuint32_t TSPP0_DLD:1;           /* DIR level definition bit. */
      vuint32_t TSPP0_EN:1;            /* Enable of TSPP0 subunit. */
      vuint32_t  :11;
      vuint32_t LSEL:1;                /* TIM0_IN6 input level selection. */
      vuint32_t SSL:3;                 /* STATE signal output select. */
      vuint32_t TSEL:1;                /* TRIGGER signal output select. */
    } B;
  } CTRL;
};


/* ============================================================================
   =============================== Module: GTM_MCFG ===========================
   ============================================================================ */

struct GTM_MCFG_tag {
  union {                              /* Memory Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t MEM6:2;                /* Configure Memory pages for MCS-instance MCS6. */
      vuint32_t MEM5:2;                /* Configure Memory pages for MCS-instance MCS5. */
      vuint32_t MEM4:2;                /* Configure Memory pages for MCS-instance MCS4. */
      vuint32_t MEM3:2;                /* Configure Memory pages for MCS-instance MCS3 */
      vuint32_t MEM2:2;                /* Configure Memory pages for MCS-instance MCS2 */
      vuint32_t MEM1:2;                /* Configure Memory pages for MCS-instance MCS1. */
      vuint32_t MEM0:2;                /* Configure Memory pages for MCS-instance MCS0. */
    } B;
  } CTRL;
};


/* ============================================================================
   =============================== Module: GTM_MCS ============================
   ============================================================================ */

struct GTM_MCS_tag {
  union {                              /* MCS Channel n General Purpose 0 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R0. */
    } B;
  } CH0_R0;

  union {                              /* MCS Channel n General Purpose 1 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R1. */
    } B;
  } CH0_R1;

  union {                              /* MCS Channel n General Purpose 2 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R2. */
    } B;
  } CH0_R2;

  union {                              /* MCS Channel n General Purpose 3 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R3. */
    } B;
  } CH0_R3;

  union {                              /* MCS Channel n General Purpose 4 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R4. */
    } B;
  } CH0_R4;

  union {                              /* MCS Channel n General Purpose 5 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R5. */
    } B;
  } CH0_R5;

  union {                              /* MCS Channel n General Purpose 6 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R6. */
    } B;
  } CH0_R6;

  union {                              /* MCS Channel n General Purpose 7 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R7. */
    } B;
  } CH0_R7;

  union {                              /* MCS Channel n Control Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t SP_CNT:3;              /* Stack pointer counter value. */
      vuint32_t  :5;
      vuint32_t SAT:1;                 /* Successful ARU transfer bit. */
      vuint32_t CWT:1;                 /* Cancel WURM instruction state. */
      vuint32_t CAT:1;                 /* Cancel ARU transfer state. */
      vuint32_t N:1;                   /* Negative bit state. */
      vuint32_t V:1;                   /* Overflow bit state. */
      vuint32_t Z:1;                   /* Zero bit state. */
      vuint32_t CY:1;                  /* Carry bit state. */
      vuint32_t  :1;
      vuint32_t ERR:1;                 /* Error state. */
      vuint32_t IRQ:1;                 /* Interrupt state. */
      vuint32_t EN:1;                  /* Enable MCS-channel. */
    } B;
  } CH0_CTRL;

  union {                              /* MCS Channel n ARU Control Bit Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t ACB4:1;                /* See ACB0. */
      vuint32_t ACB3:1;                /* See ACB0. */
      vuint32_t ACB2:1;                /* See ACB0. */
      vuint32_t ACB1:1;                /* See ACB0. */
      vuint32_t ACB0:1;                /* ARU Control bit[4:0]. */
    } B;
  } CH0_ACB;

  union {                              /* MCS Clear Trigger Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t TRG15:1;               /* Trigger bit. */
      vuint32_t TRG14:1;               /* Trigger bit. */
      vuint32_t TRG13:1;               /* Trigger bit. */
      vuint32_t TRG12:1;               /* Trigger bit. */
      vuint32_t TRG11:1;               /* Trigger bit. */
      vuint32_t TRG10:1;               /* Trigger bit. */
      vuint32_t TRG9:1;                /* Trigger bit. */
      vuint32_t TRG8:1;                /* Trigger bit. */
      vuint32_t TRG7:1;                /* Trigger bit. */
      vuint32_t TRG6:1;                /* Trigger bit. */
      vuint32_t TRG5:1;                /* Trigger bit. */
      vuint32_t TRG4:1;                /* Trigger bit. */
      vuint32_t TRG3:1;                /* Trigger bit. */
      vuint32_t TRG2:1;                /* Trigger bit. */
      vuint32_t TRG1:1;                /* Trigger bit. */
      vuint32_t TRG0:1;                /* Trigger bit. */
    } B;
  } CTRG;

  union {                              /* MCS Set Trigger Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t TRG15:1;               /* Trigger bit. */
      vuint32_t TRG14:1;               /* Trigger bit. */
      vuint32_t TRG13:1;               /* Trigger bit. */
      vuint32_t TRG12:1;               /* Trigger bit. */
      vuint32_t TRG11:1;               /* Trigger bit. */
      vuint32_t TRG10:1;               /* Trigger bit. */
      vuint32_t TRG9:1;                /* Trigger bit. */
      vuint32_t TRG8:1;                /* Trigger bit. */
      vuint32_t TRG7:1;                /* Trigger bit. */
      vuint32_t TRG6:1;                /* Trigger bit. */
      vuint32_t TRG5:1;                /* Trigger bit. */
      vuint32_t TRG4:1;                /* Trigger bit. */
      vuint32_t TRG3:1;                /* Trigger bit. */
      vuint32_t TRG2:1;                /* Trigger bit. */
      vuint32_t TRG1:1;                /* Trigger bit. */
      vuint32_t TRG0:1;                /* Trigger bit. */
    } B;
  } STRG;

  uint8_t MCS_reserved0[16];
  union {                              /* MCS Channel n Program Counter Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t PC:14;                 /* Current Program Counter. */
    } B;
  } CH0_PC;

  union {                              /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_IRQ:1;         /* Memory access out of range in channel n. */
      vuint32_t STK_ERR_IRQ:1;         /* Stack counter overflow/underflow of channel n. */
      vuint32_t MCS_IRQ:1;             /* Interrupt request by MCS-channel n. */
    } B;
  } CH0_IRQ_NOTIFY;

  union {                              /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_IRQ_EN:1;      /* MCS channel n MEM_ERR_IRQ interrupt enable. */
      vuint32_t STK_ERR_IRQ_EN:1;      /* MCS channel n STK_ERR_IRQ interrupt enable. */
      vuint32_t MCS_IRQ_EN:1;          /* MCS channel n MCS_IRQ interrupt enable. */
    } B;
  } CH0_IRQ_EN;

  union {                              /* MCS Channel n Force Interrupt Request Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t TRG_MEM_ERR_IRQ:1;     /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software. */
      vuint32_t TRG_STK_ERR_IRQ:1;     /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software. */
      vuint32_t TRG_MCS_IRQ:1;         /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register */
    } B;
  } CH0_IRQ_FORCINT;

  union {                              /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH0_IRQ_MODE;

  union {                              /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_EIRQ_EN:1;     /* MCS[i] channel n MEM_ERR_EIRQ error interrupt enable. */
      vuint32_t STK_ERR_EIRQ_EN:1;     /* MCS[i] channel n STK_ERR_IRQ error interrupt enable. */
      vuint32_t MCS_EIRQ_EN:1;         /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register */
    } B;
  } CH0_EIRQ_EN;

  uint8_t MCS_reserved1[28];
  union {                              /* MCS Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t RAM_RST:1;             /* RAM reset bit. */
      vuint32_t  :14;
      vuint32_t HLT_SP_OFL:1;          /* Halt on stack pointer overflow. */
      vuint32_t SCHED:1;               /* MCS submodule scheduling scheme. */
    } B;
  } CTRL;

  union {                              /* MCS Reset Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CWT7:1;                /* Cancel WURM instruction for channel. */
      vuint32_t CWT6:1;                /* Cancel WURM instruction for channel. */
      vuint32_t CWT5:1;                /* Cancel WURM instruction for channel. */
      vuint32_t CWT4:1;                /* Cancel WURM instruction for channel. */
      vuint32_t CWT3:1;                /* Cancel WURM instruction for channel. */
      vuint32_t CWT2:1;                /* Cancel WURM instruction for channel. */
      vuint32_t CWT1:1;                /* Cancel WURM instruction for channel. */
      vuint32_t CWT0:1;                /* Cancel WURM instruction for channel. */
      vuint32_t CAT7:1;                /* Cancel ARU transfer for channel. */
      vuint32_t CAT6:1;                /* Cancel ARU transfer for channel. */
      vuint32_t CAT5:1;                /* Cancel ARU transfer for channel. */
      vuint32_t CAT4:1;                /* Cancel ARU transfer for channel. */
      vuint32_t CAT3:1;                /* Cancel ARU transfer for channel. */
      vuint32_t CAT2:1;                /* Cancel ARU transfer for channel. */
      vuint32_t CAT1:1;                /* Cancel ARU transfer for channel. */
      vuint32_t CAT0:1;                /* Cancel ARU transfer for channel. */
      vuint32_t RST7:1;                /* Software reset of channel. */
      vuint32_t RST6:1;                /* Software reset of channel. */
      vuint32_t RST5:1;                /* Software reset of channel. */
      vuint32_t RST4:1;                /* Software reset of channel. */
      vuint32_t RST3:1;                /* Software reset of channel. */
      vuint32_t RST2:1;                /* Software reset of channel. */
      vuint32_t RST1:1;                /* Software reset of channel. */
      vuint32_t RST0:1;                /* Software reset of channel. */
    } B;
  } RST;

  union {                              /* MCS Error Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t ERR7:1;                /* Error State of MCS-channel. */
      vuint32_t ERR6:1;                /* Error State of MCS-channel. */
      vuint32_t ERR5:1;                /* Error State of MCS-channel. */
      vuint32_t ERR4:1;                /* Error State of MCS-channel. */
      vuint32_t ERR3:1;                /* Error State of MCS-channel. */
      vuint32_t ERR2:1;                /* Error State of MCS-channel. */
      vuint32_t ERR1:1;                /* Error State of MCS-channel. */
      vuint32_t ERR0:1;                /* Error State of MCS-channel. */
    } B;
  } ERR;

  union {                              /* MCS Channel n General Purpose 0 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R0. */
    } B;
  } CH1_R0;

  union {                              /* MCS Channel n General Purpose 1 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R1. */
    } B;
  } CH1_R1;

  union {                              /* MCS Channel n General Purpose 2 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R2. */
    } B;
  } CH1_R2;

  union {                              /* MCS Channel n General Purpose 3 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R3. */
    } B;
  } CH1_R3;

  union {                              /* MCS Channel n General Purpose 4 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R4. */
    } B;
  } CH1_R4;

  union {                              /* MCS Channel n General Purpose 5 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R5. */
    } B;
  } CH1_R5;

  union {                              /* MCS Channel n General Purpose 6 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R6. */
    } B;
  } CH1_R6;

  union {                              /* MCS Channel n General Purpose 7 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R7. */
    } B;
  } CH1_R7;

  union {                              /* MCS Channel n Control Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t SP_CNT:3;              /* Stack pointer counter value. */
      vuint32_t  :5;
      vuint32_t SAT:1;                 /* Successful ARU transfer bit. */
      vuint32_t CWT:1;                 /* Cancel WURM instruction state. */
      vuint32_t CAT:1;                 /* Cancel ARU transfer state. */
      vuint32_t N:1;                   /* Negative bit state. */
      vuint32_t V:1;                   /* Overflow bit state. */
      vuint32_t Z:1;                   /* Zero bit state. */
      vuint32_t CY:1;                  /* Carry bit state. */
      vuint32_t  :1;
      vuint32_t ERR:1;                 /* Error state. */
      vuint32_t IRQ:1;                 /* Interrupt state. */
      vuint32_t EN:1;                  /* Enable MCS-channel. */
    } B;
  } CH1_CTRL;

  union {                              /* MCS Channel n ARU Control Bit Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t ACB4:1;                /* See ACB0. */
      vuint32_t ACB3:1;                /* See ACB0. */
      vuint32_t ACB2:1;                /* See ACB0. */
      vuint32_t ACB1:1;                /* See ACB0. */
      vuint32_t ACB0:1;                /* ARU Control bit[4:0]. */
    } B;
  } CH1_ACB;

  uint8_t MCS_reserved2[24];
  union {                              /* MCS Channel n Program Counter Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t PC:14;                 /* Current Program Counter. */
    } B;
  } CH1_PC;

  union {                              /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_IRQ:1;         /* Memory access out of range in channel n. */
      vuint32_t STK_ERR_IRQ:1;         /* Stack counter overflow/underflow of channel n. */
      vuint32_t MCS_IRQ:1;             /* Interrupt request by MCS-channel n. */
    } B;
  } CH1_IRQ_NOTIFY;

  union {                              /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_IRQ_EN:1;      /* MCS channel n MEM_ERR_IRQ interrupt enable. */
      vuint32_t STK_ERR_IRQ_EN:1;      /* MCS channel n STK_ERR_IRQ interrupt enable. */
      vuint32_t MCS_IRQ_EN:1;          /* MCS channel n MCS_IRQ interrupt enable. */
    } B;
  } CH1_IRQ_EN;

  union {                              /* MCS Channel n Force Interrupt Request Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t TRG_MEM_ERR_IRQ:1;     /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software. */
      vuint32_t TRG_STK_ERR_IRQ:1;     /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software. */
      vuint32_t TRG_MCS_IRQ:1;         /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register */
    } B;
  } CH1_IRQ_FORCINT;

  union {                              /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH1_IRQ_MODE;

  union {                              /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_EIRQ_EN:1;     /* MCS[i] channel n MEM_ERR_EIRQ error interrupt enable. */
      vuint32_t STK_ERR_EIRQ_EN:1;     /* MCS[i] channel n STK_ERR_IRQ error interrupt enable. */
      vuint32_t MCS_EIRQ_EN:1;         /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register */
    } B;
  } CH1_EIRQ_EN;

  uint8_t MCS_reserved3[40];
  union {                              /* MCS Channel n General Purpose 0 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R0. */
    } B;
  } CH2_R0;

  union {                              /* MCS Channel n General Purpose 1 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R1. */
    } B;
  } CH2_R1;

  union {                              /* MCS Channel n General Purpose 2 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R2. */
    } B;
  } CH2_R2;

  union {                              /* MCS Channel n General Purpose 3 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R3. */
    } B;
  } CH2_R3;

  union {                              /* MCS Channel n General Purpose 4 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R4. */
    } B;
  } CH2_R4;

  union {                              /* MCS Channel n General Purpose 5 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R5. */
    } B;
  } CH2_R5;

  union {                              /* MCS Channel n General Purpose 6 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R6. */
    } B;
  } CH2_R6;

  union {                              /* MCS Channel n General Purpose 7 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R7. */
    } B;
  } CH2_R7;

  union {                              /* MCS Channel n Control Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t SP_CNT:3;              /* Stack pointer counter value. */
      vuint32_t  :5;
      vuint32_t SAT:1;                 /* Successful ARU transfer bit. */
      vuint32_t CWT:1;                 /* Cancel WURM instruction state. */
      vuint32_t CAT:1;                 /* Cancel ARU transfer state. */
      vuint32_t N:1;                   /* Negative bit state. */
      vuint32_t V:1;                   /* Overflow bit state. */
      vuint32_t Z:1;                   /* Zero bit state. */
      vuint32_t CY:1;                  /* Carry bit state. */
      vuint32_t  :1;
      vuint32_t ERR:1;                 /* Error state. */
      vuint32_t IRQ:1;                 /* Interrupt state. */
      vuint32_t EN:1;                  /* Enable MCS-channel. */
    } B;
  } CH2_CTRL;

  union {                              /* MCS Channel n ARU Control Bit Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t ACB4:1;                /* See ACB0. */
      vuint32_t ACB3:1;                /* See ACB0. */
      vuint32_t ACB2:1;                /* See ACB0. */
      vuint32_t ACB1:1;                /* See ACB0. */
      vuint32_t ACB0:1;                /* ARU Control bit[4:0]. */
    } B;
  } CH2_ACB;

  uint8_t MCS_reserved4[24];
  union {                              /* MCS Channel n Program Counter Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t PC:14;                 /* Current Program Counter. */
    } B;
  } CH2_PC;

  union {                              /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_IRQ:1;         /* Memory access out of range in channel n. */
      vuint32_t STK_ERR_IRQ:1;         /* Stack counter overflow/underflow of channel n. */
      vuint32_t MCS_IRQ:1;             /* Interrupt request by MCS-channel n. */
    } B;
  } CH2_IRQ_NOTIFY;

  union {                              /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_IRQ_EN:1;      /* MCS channel n MEM_ERR_IRQ interrupt enable. */
      vuint32_t STK_ERR_IRQ_EN:1;      /* MCS channel n STK_ERR_IRQ interrupt enable. */
      vuint32_t MCS_IRQ_EN:1;          /* MCS channel n MCS_IRQ interrupt enable. */
    } B;
  } CH2_IRQ_EN;

  union {                              /* MCS Channel n Force Interrupt Request Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t TRG_MEM_ERR_IRQ:1;     /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software. */
      vuint32_t TRG_STK_ERR_IRQ:1;     /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software. */
      vuint32_t TRG_MCS_IRQ:1;         /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register */
    } B;
  } CH2_IRQ_FORCINT;

  union {                              /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH2_IRQ_MODE;

  union {                              /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_EIRQ_EN:1;     /* MCS[i] channel n MEM_ERR_EIRQ error interrupt enable. */
      vuint32_t STK_ERR_EIRQ_EN:1;     /* MCS[i] channel n STK_ERR_IRQ error interrupt enable. */
      vuint32_t MCS_EIRQ_EN:1;         /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register */
    } B;
  } CH2_EIRQ_EN;

  uint8_t MCS_reserved5[40];
  union {                              /* MCS Channel n General Purpose 0 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R0. */
    } B;
  } CH3_R0;

  union {                              /* MCS Channel n General Purpose 1 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R1. */
    } B;
  } CH3_R1;

  union {                              /* MCS Channel n General Purpose 2 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R2. */
    } B;
  } CH3_R2;

  union {                              /* MCS Channel n General Purpose 3 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R3. */
    } B;
  } CH3_R3;

  union {                              /* MCS Channel n General Purpose 4 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R4. */
    } B;
  } CH3_R4;

  union {                              /* MCS Channel n General Purpose 5 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R5. */
    } B;
  } CH3_R5;

  union {                              /* MCS Channel n General Purpose 6 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R6. */
    } B;
  } CH3_R6;

  union {                              /* MCS Channel n General Purpose 7 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R7. */
    } B;
  } CH3_R7;

  union {                              /* MCS Channel n Control Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t SP_CNT:3;              /* Stack pointer counter value. */
      vuint32_t  :5;
      vuint32_t SAT:1;                 /* Successful ARU transfer bit. */
      vuint32_t CWT:1;                 /* Cancel WURM instruction state. */
      vuint32_t CAT:1;                 /* Cancel ARU transfer state. */
      vuint32_t N:1;                   /* Negative bit state. */
      vuint32_t V:1;                   /* Overflow bit state. */
      vuint32_t Z:1;                   /* Zero bit state. */
      vuint32_t CY:1;                  /* Carry bit state. */
      vuint32_t  :1;
      vuint32_t ERR:1;                 /* Error state. */
      vuint32_t IRQ:1;                 /* Interrupt state. */
      vuint32_t EN:1;                  /* Enable MCS-channel. */
    } B;
  } CH3_CTRL;

  union {                              /* MCS Channel n ARU Control Bit Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t ACB4:1;                /* See ACB0. */
      vuint32_t ACB3:1;                /* See ACB0. */
      vuint32_t ACB2:1;                /* See ACB0. */
      vuint32_t ACB1:1;                /* See ACB0. */
      vuint32_t ACB0:1;                /* ARU Control bit[4:0]. */
    } B;
  } CH3_ACB;

  uint8_t MCS_reserved6[24];
  union {                              /* MCS Channel n Program Counter Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t PC:14;                 /* Current Program Counter. */
    } B;
  } CH3_PC;

  union {                              /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_IRQ:1;         /* Memory access out of range in channel n. */
      vuint32_t STK_ERR_IRQ:1;         /* Stack counter overflow/underflow of channel n. */
      vuint32_t MCS_IRQ:1;             /* Interrupt request by MCS-channel n. */
    } B;
  } CH3_IRQ_NOTIFY;

  union {                              /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_IRQ_EN:1;      /* MCS channel n MEM_ERR_IRQ interrupt enable. */
      vuint32_t STK_ERR_IRQ_EN:1;      /* MCS channel n STK_ERR_IRQ interrupt enable. */
      vuint32_t MCS_IRQ_EN:1;          /* MCS channel n MCS_IRQ interrupt enable. */
    } B;
  } CH3_IRQ_EN;

  union {                              /* MCS Channel n Force Interrupt Request Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t TRG_MEM_ERR_IRQ:1;     /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software. */
      vuint32_t TRG_STK_ERR_IRQ:1;     /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software. */
      vuint32_t TRG_MCS_IRQ:1;         /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register */
    } B;
  } CH3_IRQ_FORCINT;

  union {                              /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH3_IRQ_MODE;

  union {                              /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_EIRQ_EN:1;     /* MCS[i] channel n MEM_ERR_EIRQ error interrupt enable. */
      vuint32_t STK_ERR_EIRQ_EN:1;     /* MCS[i] channel n STK_ERR_IRQ error interrupt enable. */
      vuint32_t MCS_EIRQ_EN:1;         /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register */
    } B;
  } CH3_EIRQ_EN;

  uint8_t MCS_reserved7[40];
  union {                              /* MCS Channel n General Purpose 0 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R0. */
    } B;
  } CH4_R0;

  union {                              /* MCS Channel n General Purpose 1 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R1. */
    } B;
  } CH4_R1;

  union {                              /* MCS Channel n General Purpose 2 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R2. */
    } B;
  } CH4_R2;

  union {                              /* MCS Channel n General Purpose 3 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R3. */
    } B;
  } CH4_R3;

  union {                              /* MCS Channel n General Purpose 4 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R4. */
    } B;
  } CH4_R4;

  union {                              /* MCS Channel n General Purpose 5 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R5. */
    } B;
  } CH4_R5;

  union {                              /* MCS Channel n General Purpose 6 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R6. */
    } B;
  } CH4_R6;

  union {                              /* MCS Channel n General Purpose 7 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R7. */
    } B;
  } CH4_R7;

  union {                              /* MCS Channel n Control Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t SP_CNT:3;              /* Stack pointer counter value. */
      vuint32_t  :5;
      vuint32_t SAT:1;                 /* Successful ARU transfer bit. */
      vuint32_t CWT:1;                 /* Cancel WURM instruction state. */
      vuint32_t CAT:1;                 /* Cancel ARU transfer state. */
      vuint32_t N:1;                   /* Negative bit state. */
      vuint32_t V:1;                   /* Overflow bit state. */
      vuint32_t Z:1;                   /* Zero bit state. */
      vuint32_t CY:1;                  /* Carry bit state. */
      vuint32_t  :1;
      vuint32_t ERR:1;                 /* Error state. */
      vuint32_t IRQ:1;                 /* Interrupt state. */
      vuint32_t EN:1;                  /* Enable MCS-channel. */
    } B;
  } CH4_CTRL;

  union {                              /* MCS Channel n ARU Control Bit Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t ACB4:1;                /* See ACB0. */
      vuint32_t ACB3:1;                /* See ACB0. */
      vuint32_t ACB2:1;                /* See ACB0. */
      vuint32_t ACB1:1;                /* See ACB0. */
      vuint32_t ACB0:1;                /* ARU Control bit[4:0]. */
    } B;
  } CH4_ACB;

  uint8_t MCS_reserved8[24];
  union {                              /* MCS Channel n Program Counter Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t PC:14;                 /* Current Program Counter. */
    } B;
  } CH4_PC;

  union {                              /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_IRQ:1;         /* Memory access out of range in channel n. */
      vuint32_t STK_ERR_IRQ:1;         /* Stack counter overflow/underflow of channel n. */
      vuint32_t MCS_IRQ:1;             /* Interrupt request by MCS-channel n. */
    } B;
  } CH4_IRQ_NOTIFY;

  union {                              /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_IRQ_EN:1;      /* MCS channel n MEM_ERR_IRQ interrupt enable. */
      vuint32_t STK_ERR_IRQ_EN:1;      /* MCS channel n STK_ERR_IRQ interrupt enable. */
      vuint32_t MCS_IRQ_EN:1;          /* MCS channel n MCS_IRQ interrupt enable. */
    } B;
  } CH4_IRQ_EN;

  union {                              /* MCS Channel n Force Interrupt Request Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t TRG_MEM_ERR_IRQ:1;     /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software. */
      vuint32_t TRG_STK_ERR_IRQ:1;     /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software. */
      vuint32_t TRG_MCS_IRQ:1;         /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register */
    } B;
  } CH4_IRQ_FORCINT;

  union {                              /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH4_IRQ_MODE;

  union {                              /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_EIRQ_EN:1;     /* MCS[i] channel n MEM_ERR_EIRQ error interrupt enable. */
      vuint32_t STK_ERR_EIRQ_EN:1;     /* MCS[i] channel n STK_ERR_IRQ error interrupt enable. */
      vuint32_t MCS_EIRQ_EN:1;         /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register */
    } B;
  } CH4_EIRQ_EN;

  uint8_t MCS_reserved9[40];
  union {                              /* MCS Channel n General Purpose 0 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R0. */
    } B;
  } CH5_R0;

  union {                              /* MCS Channel n General Purpose 1 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R1. */
    } B;
  } CH5_R1;

  union {                              /* MCS Channel n General Purpose 2 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R2. */
    } B;
  } CH5_R2;

  union {                              /* MCS Channel n General Purpose 3 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R3. */
    } B;
  } CH5_R3;

  union {                              /* MCS Channel n General Purpose 4 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R4. */
    } B;
  } CH5_R4;

  union {                              /* MCS Channel n General Purpose 5 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R5. */
    } B;
  } CH5_R5;

  union {                              /* MCS Channel n General Purpose 6 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R6. */
    } B;
  } CH5_R6;

  union {                              /* MCS Channel n General Purpose 7 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R7. */
    } B;
  } CH5_R7;

  union {                              /* MCS Channel n Control Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t SP_CNT:3;              /* Stack pointer counter value. */
      vuint32_t  :5;
      vuint32_t SAT:1;                 /* Successful ARU transfer bit. */
      vuint32_t CWT:1;                 /* Cancel WURM instruction state. */
      vuint32_t CAT:1;                 /* Cancel ARU transfer state. */
      vuint32_t N:1;                   /* Negative bit state. */
      vuint32_t V:1;                   /* Overflow bit state. */
      vuint32_t Z:1;                   /* Zero bit state. */
      vuint32_t CY:1;                  /* Carry bit state. */
      vuint32_t  :1;
      vuint32_t ERR:1;                 /* Error state. */
      vuint32_t IRQ:1;                 /* Interrupt state. */
      vuint32_t EN:1;                  /* Enable MCS-channel. */
    } B;
  } CH5_CTRL;

  union {                              /* MCS Channel n ARU Control Bit Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t ACB4:1;                /* See ACB0. */
      vuint32_t ACB3:1;                /* See ACB0. */
      vuint32_t ACB2:1;                /* See ACB0. */
      vuint32_t ACB1:1;                /* See ACB0. */
      vuint32_t ACB0:1;                /* ARU Control bit[4:0]. */
    } B;
  } CH5_ACB;

  uint8_t MCS_reserved10[24];
  union {                              /* MCS Channel n Program Counter Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t PC:14;                 /* Current Program Counter. */
    } B;
  } CH5_PC;

  union {                              /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_IRQ:1;         /* Memory access out of range in channel n. */
      vuint32_t STK_ERR_IRQ:1;         /* Stack counter overflow/underflow of channel n. */
      vuint32_t MCS_IRQ:1;             /* Interrupt request by MCS-channel n. */
    } B;
  } CH5_IRQ_NOTIFY;

  union {                              /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_IRQ_EN:1;      /* MCS channel n MEM_ERR_IRQ interrupt enable. */
      vuint32_t STK_ERR_IRQ_EN:1;      /* MCS channel n STK_ERR_IRQ interrupt enable. */
      vuint32_t MCS_IRQ_EN:1;          /* MCS channel n MCS_IRQ interrupt enable. */
    } B;
  } CH5_IRQ_EN;

  union {                              /* MCS Channel n Force Interrupt Request Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t TRG_MEM_ERR_IRQ:1;     /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software. */
      vuint32_t TRG_STK_ERR_IRQ:1;     /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software. */
      vuint32_t TRG_MCS_IRQ:1;         /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register */
    } B;
  } CH5_IRQ_FORCINT;

  union {                              /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH5_IRQ_MODE;

  union {                              /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_EIRQ_EN:1;     /* MCS[i] channel n MEM_ERR_EIRQ error interrupt enable. */
      vuint32_t STK_ERR_EIRQ_EN:1;     /* MCS[i] channel n STK_ERR_IRQ error interrupt enable. */
      vuint32_t MCS_EIRQ_EN:1;         /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register */
    } B;
  } CH5_EIRQ_EN;

  uint8_t MCS_reserved11[40];
  union {                              /* MCS Channel n General Purpose 0 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R0. */
    } B;
  } CH6_R0;

  union {                              /* MCS Channel n General Purpose 1 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R1. */
    } B;
  } CH6_R1;

  union {                              /* MCS Channel n General Purpose 2 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R2. */
    } B;
  } CH6_R2;

  union {                              /* MCS Channel n General Purpose 3 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R3. */
    } B;
  } CH6_R3;

  union {                              /* MCS Channel n General Purpose 4 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R4. */
    } B;
  } CH6_R4;

  union {                              /* MCS Channel n General Purpose 5 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R5. */
    } B;
  } CH6_R5;

  union {                              /* MCS Channel n General Purpose 6 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R6. */
    } B;
  } CH6_R6;

  union {                              /* MCS Channel n General Purpose 7 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R7. */
    } B;
  } CH6_R7;

  union {                              /* MCS Channel n Control Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t SP_CNT:3;              /* Stack pointer counter value. */
      vuint32_t  :5;
      vuint32_t SAT:1;                 /* Successful ARU transfer bit. */
      vuint32_t CWT:1;                 /* Cancel WURM instruction state. */
      vuint32_t CAT:1;                 /* Cancel ARU transfer state. */
      vuint32_t N:1;                   /* Negative bit state. */
      vuint32_t V:1;                   /* Overflow bit state. */
      vuint32_t Z:1;                   /* Zero bit state. */
      vuint32_t CY:1;                  /* Carry bit state. */
      vuint32_t  :1;
      vuint32_t ERR:1;                 /* Error state. */
      vuint32_t IRQ:1;                 /* Interrupt state. */
      vuint32_t EN:1;                  /* Enable MCS-channel. */
    } B;
  } CH6_CTRL;

  union {                              /* MCS Channel n ARU Control Bit Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t ACB4:1;                /* See ACB0. */
      vuint32_t ACB3:1;                /* See ACB0. */
      vuint32_t ACB2:1;                /* See ACB0. */
      vuint32_t ACB1:1;                /* See ACB0. */
      vuint32_t ACB0:1;                /* ARU Control bit[4:0]. */
    } B;
  } CH6_ACB;

  uint8_t MCS_reserved12[24];
  union {                              /* MCS Channel n Program Counter Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t PC:14;                 /* Current Program Counter. */
    } B;
  } CH6_PC;

  union {                              /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_IRQ:1;         /* Memory access out of range in channel n. */
      vuint32_t STK_ERR_IRQ:1;         /* Stack counter overflow/underflow of channel n. */
      vuint32_t MCS_IRQ:1;             /* Interrupt request by MCS-channel n. */
    } B;
  } CH6_IRQ_NOTIFY;

  union {                              /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_IRQ_EN:1;      /* MCS channel n MEM_ERR_IRQ interrupt enable. */
      vuint32_t STK_ERR_IRQ_EN:1;      /* MCS channel n STK_ERR_IRQ interrupt enable. */
      vuint32_t MCS_IRQ_EN:1;          /* MCS channel n MCS_IRQ interrupt enable. */
    } B;
  } CH6_IRQ_EN;

  union {                              /* MCS Channel n Force Interrupt Request Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t TRG_MEM_ERR_IRQ:1;     /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software. */
      vuint32_t TRG_STK_ERR_IRQ:1;     /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software. */
      vuint32_t TRG_MCS_IRQ:1;         /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register */
    } B;
  } CH6_IRQ_FORCINT;

  union {                              /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH6_IRQ_MODE;

  union {                              /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_EIRQ_EN:1;     /* MCS[i] channel n MEM_ERR_EIRQ error interrupt enable. */
      vuint32_t STK_ERR_EIRQ_EN:1;     /* MCS[i] channel n STK_ERR_IRQ error interrupt enable. */
      vuint32_t MCS_EIRQ_EN:1;         /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register */
    } B;
  } CH6_EIRQ_EN;

  uint8_t MCS_reserved13[40];
  union {                              /* MCS Channel n General Purpose 0 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R0. */
    } B;
  } CH7_R0;

  union {                              /* MCS Channel n General Purpose 1 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R1. */
    } B;
  } CH7_R1;

  union {                              /* MCS Channel n General Purpose 2 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R2. */
    } B;
  } CH7_R2;

  union {                              /* MCS Channel n General Purpose 3 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R3. */
    } B;
  } CH7_R3;

  union {                              /* MCS Channel n General Purpose 4 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R4. */
    } B;
  } CH7_R4;

  union {                              /* MCS Channel n General Purpose 5 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R5. */
    } B;
  } CH7_R5;

  union {                              /* MCS Channel n General Purpose 6 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R6. */
    } B;
  } CH7_R6;

  union {                              /* MCS Channel n General Purpose 7 Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DATA:24;               /* Data of MCS general purpose register R7. */
    } B;
  } CH7_R7;

  union {                              /* MCS Channel n Control Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t SP_CNT:3;              /* Stack pointer counter value. */
      vuint32_t  :5;
      vuint32_t SAT:1;                 /* Successful ARU transfer bit. */
      vuint32_t CWT:1;                 /* Cancel WURM instruction state. */
      vuint32_t CAT:1;                 /* Cancel ARU transfer state. */
      vuint32_t N:1;                   /* Negative bit state. */
      vuint32_t V:1;                   /* Overflow bit state. */
      vuint32_t Z:1;                   /* Zero bit state. */
      vuint32_t CY:1;                  /* Carry bit state. */
      vuint32_t  :1;
      vuint32_t ERR:1;                 /* Error state. */
      vuint32_t IRQ:1;                 /* Interrupt state. */
      vuint32_t EN:1;                  /* Enable MCS-channel. */
    } B;
  } CH7_CTRL;

  union {                              /* MCS Channel n ARU Control Bit Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t ACB4:1;                /* See ACB0. */
      vuint32_t ACB3:1;                /* See ACB0. */
      vuint32_t ACB2:1;                /* See ACB0. */
      vuint32_t ACB1:1;                /* See ACB0. */
      vuint32_t ACB0:1;                /* ARU Control bit[4:0]. */
    } B;
  } CH7_ACB;

  uint8_t MCS_reserved14[24];
  union {                              /* MCS Channel n Program Counter Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t PC:14;                 /* Current Program Counter. */
    } B;
  } CH7_PC;

  union {                              /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_IRQ:1;         /* Memory access out of range in channel n. */
      vuint32_t STK_ERR_IRQ:1;         /* Stack counter overflow/underflow of channel n. */
      vuint32_t MCS_IRQ:1;             /* Interrupt request by MCS-channel n. */
    } B;
  } CH7_IRQ_NOTIFY;

  union {                              /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_IRQ_EN:1;      /* MCS channel n MEM_ERR_IRQ interrupt enable. */
      vuint32_t STK_ERR_IRQ_EN:1;      /* MCS channel n STK_ERR_IRQ interrupt enable. */
      vuint32_t MCS_IRQ_EN:1;          /* MCS channel n MCS_IRQ interrupt enable. */
    } B;
  } CH7_IRQ_EN;

  union {                              /* MCS Channel n Force Interrupt Request Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t TRG_MEM_ERR_IRQ:1;     /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software. */
      vuint32_t TRG_STK_ERR_IRQ:1;     /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software. */
      vuint32_t TRG_MCS_IRQ:1;         /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register */
    } B;
  } CH7_IRQ_FORCINT;

  union {                              /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH7_IRQ_MODE;

  union {                              /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MEM_ERR_EIRQ_EN:1;     /* MCS[i] channel n MEM_ERR_EIRQ error interrupt enable. */
      vuint32_t STK_ERR_EIRQ_EN:1;     /* MCS[i] channel n STK_ERR_IRQ error interrupt enable. */
      vuint32_t MCS_EIRQ_EN:1;         /* Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register */
    } B;
  } CH7_EIRQ_EN;
};


/* ============================================================================
   =============================== Module: GTM_MON ============================
   ============================================================================ */

struct GTM_MON_tag {
  union {                              /* Monitor Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t MCS6_ERR:1;            /* See MCS0_ERR. */
      vuint32_t MCS5_ERR:1;            /* See MCS0_ERR. */
      vuint32_t MCS4_ERR:1;            /* See MCS0_ERR. */
      vuint32_t MCS3_ERR:1;            /* See MCS0_ERR. */
      vuint32_t MCS2_ERR:1;            /* See MCS0_ERR. */
      vuint32_t MCS1_ERR:1;            /* See MCS0_ERR. */
      vuint32_t MCS0_ERR:1;            /* Error detected at corresponding MCS. */
      vuint32_t  :3;
      vuint32_t CMP_ERR:1;             /* Error detected at CMP. */
      vuint32_t  :3;
      vuint32_t ACT_CMUFX4:1;          /* See ACT_CMUFX0. */
      vuint32_t ACT_CMUFX3:1;          /* See ACT_CMUFX0. */
      vuint32_t ACT_CMUFX2:1;          /* See ACT_CMUFX0. */
      vuint32_t ACT_CMUFX1:1;          /* See ACT_CMUFX0. */
      vuint32_t ACT_CMUFX0:1;          /* Corresponding CMU_CLKFX activity. */
      vuint32_t ACT_CMU7:1;            /* See ACT_CMU0. */
      vuint32_t ACT_CMU6:1;            /* See ACT_CMU0. */
      vuint32_t ACT_CMU5:1;            /* See ACT_CMU0. */
      vuint32_t ACT_CMU4:1;            /* See ACT_CMU0. */
      vuint32_t ACT_CMU3:1;            /* See ACT_CMU0. */
      vuint32_t ACT_CMU2:1;            /* See ACT_CMU0. */
      vuint32_t ACT_CMU1:1;            /* See ACT_CMU0. */
      vuint32_t ACT_CMU0:1;            /* Corresponding CMU_CLK activity. */
    } B;
  } STATUS;

  union {                              /* Monitor Acitivity 0 */
    vuint32_t R;
    struct {
      vuint32_t MCA_3_7:1;             /* See MCA_3_0. */
      vuint32_t MCA_3_6:1;             /* See MCA_3_0. */
      vuint32_t MCA_3_5:1;             /* See MCA_3_0. */
      vuint32_t MCA_3_4:1;             /* See MCA_3_0. */
      vuint32_t MCA_3_3:1;             /* See MCA_3_0. */
      vuint32_t MCA_3_2:1;             /* See MCA_3_0. */
      vuint32_t MCA_3_1:1;             /* See MCA_3_0. */
      vuint32_t MCA_3_0:1;             /* Activity of check performed in module MCS[3] at corresponding channel. */
      vuint32_t MCA_2_7:1;             /* See MCA_2_0. */
      vuint32_t MCA_2_6:1;             /* See MCA_2_0. */
      vuint32_t MCA_2_5:1;             /* See MCA_2_0. */
      vuint32_t MCA_2_4:1;             /* See MCA_2_0. */
      vuint32_t MCA_2_3:1;             /* See MCA_2_0. */
      vuint32_t MCA_2_2:1;             /* See MCA_2_0. */
      vuint32_t MCA_2_1:1;             /* See MCA_2_0. */
      vuint32_t MCA_2_0:1;             /* Activity of check performed in module MCS[2] at corresponding channel. */
      vuint32_t MCA_1_7:1;             /* See MCA_1_0. */
      vuint32_t MCA_1_6:1;             /* See MCA_1_0. */
      vuint32_t MCA_1_5:1;             /* See MCA_1_0. */
      vuint32_t MCA_1_4:1;             /* See MCA_1_0. */
      vuint32_t MCA_1_3:1;             /* See MCA_1_0. */
      vuint32_t MCA_1_2:1;             /* See MCA_1_0. */
      vuint32_t MCA_1_1:1;             /* See MCA_1_0. */
      vuint32_t MCA_1_0:1;             /* Activity of check performed in module MCS[1] at corresponding channel. */
      vuint32_t MCA_0_7:1;             /* See MCA_0_0. */
      vuint32_t MCA_0_6:1;             /* See MCA_0_0. */
      vuint32_t MCA_0_5:1;             /* See MCA_0_0. */
      vuint32_t MCA_0_4:1;             /* See MCA_0_0. */
      vuint32_t MCA_0_3:1;             /* See MCA_0_0. */
      vuint32_t MCA_0_2:1;             /* See MCA_0_0. */
      vuint32_t MCA_0_1:1;             /* See MCA_0_0. */
      vuint32_t MCA_0_0:1;             /* Activity of check performed in module MCS[0] at corresponding channel. */
    } B;
  } ACTIVITY_0;

  union {                              /* Monitor Acitivity 1 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t MCA_6_7:1;             /* See MCA_6_0. */
      vuint32_t MCA_6_6:1;             /* See MCA_6_0. */
      vuint32_t MCA_6_5:1;             /* See MCA_6_0. */
      vuint32_t MCA_6_4:1;             /* See MCA_6_0. */
      vuint32_t MCA_6_3:1;             /* See MCA_6_0. */
      vuint32_t MCA_6_2:1;             /* See MCA_6_0. */
      vuint32_t MCA_6_1:1;             /* See MCA_6_0. */
      vuint32_t MCA_6_0:1;             /* Activity of check performed in module MCS[6] at corresponding channel. */
      vuint32_t MCA_5_7:1;             /* See MCA_5_0. */
      vuint32_t MCA_5_6:1;             /* See MCA_5_0. */
      vuint32_t MCA_5_5:1;             /* See MCA_5_0. */
      vuint32_t MCA_5_4:1;             /* See MCA_5_0. */
      vuint32_t MCA_5_3:1;             /* See MCA_5_0. */
      vuint32_t MCA_5_2:1;             /* See MCA_5_0. */
      vuint32_t MCA_5_1:1;             /* See MCA_5_0. */
      vuint32_t MCA_5_0:1;             /* Activity of check performed in module MCS[5] at corresponding channel. */
      vuint32_t MCA_4_7:1;             /* See MCA_4_0. */
      vuint32_t MCA_4_6:1;             /* See MCA_4_0. */
      vuint32_t MCA_4_5:1;             /* See MCA_4_0. */
      vuint32_t MCA_4_4:1;             /* See MCA_4_0. */
      vuint32_t MCA_4_3:1;             /* See MCA_4_0. */
      vuint32_t MCA_4_2:1;             /* See MCA_4_0. */
      vuint32_t MCA_4_1:1;             /* See MCA_4_0. */
      vuint32_t MCA_4_0:1;             /* Activity of check performed in module MCS[4] at corresponding channel. */
    } B;
  } ACTIVITY_1;
};


/* ============================================================================
   =============================== Module: GTM_SPE ============================
   ============================================================================ */

struct GTM_SPE_tag {
  union {                              /* SPE Control Status Register */
    vuint32_t R;
    struct {
      vuint32_t FSOL:8;                /* Fast Shut-Off Level for TOM[i] channel 0 to 7. */
      vuint32_t  :1;
      vuint32_t NIP:3;                 /* New input pattern that was detected. */
      vuint32_t PDIR:1;                /* Previous rotation direction. */
      vuint32_t PIP:3;                 /* Previous input pattern that was detected by a regular input pattern change. */
      vuint32_t ADIR:1;                /* Actual rotation direction. */
      vuint32_t AIP:3;                 /* Actual input pattern that was detected by a regular input pattern change. */
      vuint32_t  :1;
      vuint32_t SPE_PAT_PTR:3;         /* Pattern selector for TOM output signals. */
      vuint32_t FSOM:1;                /* Fast Shut-Off Mode. */
      vuint32_t TIM_SEL:1;             /* Select TIM input signal. */
      vuint32_t TRIG_SEL:2;            /* Select trigger input signal. */
      vuint32_t SIE2:1;                /* SPE Input enable for TIM_CHz(48). */
      vuint32_t SIE1:1;                /* SPE Input enable for TIM_CHy(48). */
      vuint32_t SIE0:1;                /* SPE Input enable for TIM_CHx(48). */
      vuint32_t EN:1;                  /* SPE Submodule enable. */
    } B;
  } CTRL_STAT;

  union {                              /* SPE Input Pattern Register */
    vuint32_t R;
    struct {
      vuint32_t IP7_PAT:3;             /* Input pattern 7. */
      vuint32_t IP7_VAL:1;             /* Input pattern 7 is a valid pattern. */
      vuint32_t IP6_PAT:3;             /* Input pattern 6. */
      vuint32_t IP6_VAL:1;             /* Input pattern 6 is a valid pattern. */
      vuint32_t IP5_PAT:3;             /* Input pattern 5. */
      vuint32_t IP5_VAL:1;             /* Input pattern 5 is a valid pattern. */
      vuint32_t IP4_PAT:3;             /* Input pattern 4. */
      vuint32_t IP4_VAL:1;             /* Input pattern 4 is a valid pattern. */
      vuint32_t IP3_PAT:3;             /* Input pattern 3. */
      vuint32_t IP3_VAL:1;             /* Input pattern 3 is a valid pattern. */
      vuint32_t IP2_PAT:3;             /* Input pattern 2. */
      vuint32_t IP2_VAL:1;             /* Input pattern 2 is a valid pattern. */
      vuint32_t IP1_PAT:3;
      vuint32_t IP1_VAL:1;             /* Input pattern 1 is a valid pattern. */
      vuint32_t IP0_PAT:3;             /* Input pattern 0. */
      vuint32_t IP0_VAL:1;             /* Input pattern 0 is a valid pattern. */
    } B;
  } PAT;

  union {                              /* SPE Output Pattern n Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SPE_OUT_PAT:16;        /* SPE output control value for TOM_CH0 to TOM_CH7 SPE_OUT_PAT[n+1:n] defines output select signal of TOM[i]_CH[n]. */
    } B;
  } OUT_PAT[8];

  union {                              /* SPE Output Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;                  /* Reserved. */
      vuint32_t SPE_OUT_CTRL:16;       /* SPE output control value for TOM_CH0 to TOM_CH7. */
    } B;
  } OUT_CTRL;

  union {                              /* SPE Interrupt Request Notify Register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t SPE_RCMP:1;            /* SPE revolution counter match event. */
      vuint32_t SPE_BIS:1;             /* Bouncing input signal detected. */
      vuint32_t SPE_PERR:1;            /* Wrong or invalid pattern detected at input. */
      vuint32_t SPE_DCHG:1;            /* SPE_DIR bit changed on behalf of new input pattern. */
      vuint32_t SPE_NIPD:1;            /* New input pattern interrupt occurred. */
    } B;
  } IRQ_NOTIFY;

  union {                              /* SPE Interrupt Request Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :27;                  /* Reserved. */
      vuint32_t SPE_RCMP_IRQ_EN:1;     /* SPE_RCMP_IRQ interrupt enable. */
      vuint32_t SPE_BIS_IRQ_EN:1;      /* SPE_BIS_IRQ interrupt enable. */
      vuint32_t SPE_PERR_IRQ_EN:1;     /* SPE_PERR_IRQ interrupt enable. */
      vuint32_t SPE_DCHG_IRQ_EN:1;     /* SPE_DCHG_IRQ interrupt enable. */
      vuint32_t SPE_NIPD_IRQ_EN:1;     /* SPE_NIPD_IRQ interrupt enable. */
    } B;
  } IRQ_EN;

  union {                              /* SPE Interrupt Request Force Interrupt Register */
    vuint32_t R;
    struct {
      vuint32_t  :27;                  /* Reserved. */
      vuint32_t TRG_SPE_RCMP:1;        /* Force interrupt of SPE_RCMP. */
      vuint32_t TRG_SPE_BIS:1;         /* Force interrupt of SPE_BIS. */
      vuint32_t TRG_SPE_PERR:1;        /* Force interrupt of SPE_PERR. */
      vuint32_t TRG_SPE_DCHG:1;        /* Force interrupt of SPE_DCHG. */
      vuint32_t TRG_SPE_NIPD:1;        /* Force interrupt of SPE_NIPD. */
    } B;
  } IRQ_FORCINT;

  union {                              /* SPE Interrupt Request Mode Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } IRQ_MODE;

  union {                              /* SPE Error Interrupt Request Enable register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t SPE_RCMP_EIRQ_EN:1;    /* SPE_BIS_EIRQ error interrupt enable. */
      vuint32_t SPE_BIS_EIRQ_EN:1;     /* SPE_BIS_EIRQ error interrupt enable. */
      vuint32_t SPE_PERR_EIRQ_EN:1;    /* SPE_PERR_EIRQ interrupt enable. */
      vuint32_t SPE_DCHG_EIRQ_EN:1;
      vuint32_t SPE_NIPD_EIRQ_EN:1;    /* SPE_NIPD_EIRQ interrupt enable. */
    } B;
  } EIRQ_EN;

  union {                              /* SPE Revolution Counter register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t REV_CNT:24;            /* Input signal revolution counter. */
    } B;
  } REV_CNT;

  union {                              /* SPE Revolution Counter Compare register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t REV_CMP:24;            /* Input signal revolution counter compare value. */
    } B;
  } REV_CMP;
};


/* ============================================================================
   =============================== Module: GTM_TBU ============================
   ============================================================================ */

struct GTM_TBU_tag {
  union {                              /* TBU Global Channel Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t ENDIS_CH2:2;           /* TBU channel 2 enable/disable control. */
      vuint32_t ENDIS_CH1:2;           /* TBU channel 1 enable/disable control. */
      vuint32_t ENDIS_CH0:2;           /* TBU channel 0 enable/disable control. */
    } B;
  } CHEN;

  union {                              /* TBU Channel 0 Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t CH_CLK_SRC:3;          /* Clock source for channel 0. */
      vuint32_t LOW_RES:1;             /* TBU_CH0_BASE register resolution. */
    } B;
  } CH0_CTRL;

  union {                              /* TBU Channel 0 Base Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t BASE:27;               /* Time base value for channel 0. */
    } B;
  } CH0_BASE;

  union {                              /* TBU Channel 1 Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t CH_CLK_SRC:3;          /* Clock source for channel time base counter. */
      vuint32_t CH_MODE:1;             /* Channel mode. */
    } B;
  } CH1_CTRL;

  union {                              /* TBU Channel 1 Base Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t BASE:24;               /* Time base value for the channel. */
    } B;
  } CH1_BASE;

  union {                              /* TBU Channel 2 Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t CH_CLK_SRC:3;          /* Clock source for channel time base counter. */
      vuint32_t CH_MODE:1;             /* Channel mode. */
    } B;
  } CH2_CTRL;

  union {                              /* TBU Channel 2 Base Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t BASE:24;               /* Time base value for the channel. */
    } B;
  } CH2_BASE;
};


/* ============================================================================
   =============================== Module: GTM_TIM ============================
   ============================================================================ */

struct GTM_TIM_tag {
  union {                              /* TIM Channel n General Purpose Register 0, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t GPR0:24;               /* Input signal characteristic parameter 0. */
    } B;
  } CH0_GPR0;

  union {                              /* TIM Channel n General Purpose Register 1, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t GPR1:24;               /* Input signal characteristic parameter 1. */
    } B;
  } CH0_GPR1;

  union {                              /* TIM Channel n Count Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CNT:24;                /* Actual SMU counter value. */
    } B;
  } CH0_CNT;

  union {                              /* TIM Channel n Edge Counter Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t ECNT:16;               /* Edge counter. */
    } B;
  } CH0_ECNT;

  union {                              /* TIM Channel n Counter Shadow Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t CNTS:24;               /* Counter shadow register. */
    } B;
  } CH0_CNTS;

  union {                              /* TIM Channel n TDUC Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t TO_CNT:8;              /* Current Timeout value for channel n (n:0...m-1). */
    } B;
  } CH0_TDUC;

  union {                              /* TIM Channel n TDUV Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t TCS:3;                 /* Timeout Clock selection. */
      vuint32_t  :20;
      vuint32_t TOV:8;                 /* Time out duration for channel n (n:0...m-1). */
    } B;
  } CH0_TDUV;

  union {                              /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t FLT_RE:24;             /* Filter parameter for rising edge. */
    } B;
  } CH0_FLT_RE;

  union {                              /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t FLT_FE:24;             /* Filter parameter for falling edge. */
    } B;
  } CH0_FLT_FE;

  union {                              /* TIM Channel n Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t TOCTRL:2;              /* Timeout control */
      vuint32_t EGPR1_SEL:1;           /* Extension of GPR1_SEL bit field. */
      vuint32_t EGPR0_SEL:1;           /* Extension of GPR0_SEL bit field. */
      vuint32_t FR_ECNT_OFL:1;         /* Extended Edge counter overflow behavior. */
      vuint32_t CLK_SEL:3;             /* CMU clock source select for channel. */
      vuint32_t FLT_CTR_FE:1;          /* Filter counter mode for falling edge. */
      vuint32_t FLT_MODE_FE:1;         /* Filter mode for falling edge. */
      vuint32_t FLT_CTR_RE:1;          /* Filter counter mode for rising edge. */
      vuint32_t FLT_MODE_RE:1;         /* Filter mode for rising edge. */
      vuint32_t EXT_CAP_EN:1;          /* Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses, the input event changes are ignored. */
      vuint32_t FLT_CNT_FRQ:2;         /* Filter counter frequency select. */
      vuint32_t FLT_EN:1;              /* Filter enable for channel n. */
      vuint32_t ECNT_RESET:1;          /* Enables resetting the ECNT counter in periodic sampling mode. */
      vuint32_t ISL:1;                 /* Ignore Signal Level. */
      vuint32_t DSL:1;                 /* Signal level control. */
      vuint32_t CNTS_SEL:1;            /* Selection for CNTS register. */
      vuint32_t GPR1_SEL:2;            /* Selection for GPR1 register. */
      vuint32_t GPR0_SEL:2;            /* Selection for GPR0 register. */
      vuint32_t TBU0_SEL:1;            /* TBU_TS0 bits input select for TIM_CHn_GPRz (z: 0, 1) */
      vuint32_t CICTRL:1;              /* Channel Input Control. */
      vuint32_t ARU_EN:1;              /* GPR0 and GPR1 register values routed to ARU. */
      vuint32_t OSM:1;                 /* One-shot mode. */
      vuint32_t TIM_MODE:3;            /* TIM channel n mode. */
      vuint32_t TIM_EN:1;              /* TIM channel n enable. */
    } B;
  } CH0_CTRL;

  union {                              /* TIM Channel n External Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t EXT_CAP_SRC:3;         /* Defines selected source for triggering the EXT_CAPTURE functionality. */
    } B;
  } CH0_ECTRL;

  union {                              /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET:1;           /* Glitch detected on channel n. */
      vuint32_t TODET:1;               /* Timeout reached for input signal of channel n. */
      vuint32_t GPROFL:1;              /* GPR0 and GPR1 data overflow, old data not read out before new data has arrived at input pin. */
      vuint32_t CNTOFL:1;              /* SMU CNT counter overflow of channel n. */
      vuint32_t ECNTOFL:1;             /* ECNT counter overflow of channel n. */
      vuint32_t NEWVAL:1;              /* New measurement value detected by in channel n */
    } B;
  } CH0_IRQ_NOTIFY;

  union {                              /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET_IRQ_EN:1;    /* TIM_GLITCHDETx_IRQ interrupt enable. */
      vuint32_t TODET_IRQ_EN:1;        /* TIM_TODETn_IRQ interrupt enable. */
      vuint32_t GPROFL_IRQ_EN:1;       /* TIM_GPROFL_IRQ interrupt enable. */
      vuint32_t CNTOFL_IRQ_EN:1;       /* TIM_CNTOFLn_IRQ interrupt enable. */
      vuint32_t ECNTOFL_IRQ_EN:1;      /* TIM_ECNTOFLn_IRQ interrupt enable. */
      vuint32_t NEWVAL_IRQ_EN:1;       /* TIM_NEWVALn_IRQ interrupt enable. */
    } B;
  } CH0_IRQ_EN;

  union {                              /* TIM Channel n Force Interrupt Request Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t TRG_GLITCHDET:1;       /* Trigger bit TIM_CHn_IRQ_NOTIFY[GLITCHDET] by software. */
      vuint32_t TRG_TODET:1;           /* Trigger bit TIM_CHn_IRQ_NOTIFY[TODET] by software. */
      vuint32_t TRG_GPROFL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[GPROFL] by software. */
      vuint32_t TRG_CNTOFL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[CNTOFL] by software. */
      vuint32_t TRG_ECNTOFL:1;         /* Trigger bit TIM_CHn_IRQ_NOTIFY[ECNTOFL] by software. */
      vuint32_t TRG_NEWVAL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[NEWVAL] by software. */
    } B;
  } CH0_IRQ_FORCINT;

  union {                              /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH0_IRQ_MODE;

  union {                              /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET_EIRQ_EN:1;   /* TIM_GLITCHDETx_IRQ interrupt enable. */
      vuint32_t TODET_EIRQ_EN:1;       /* TIM_TODETx_IRQ interrupt enable. */
      vuint32_t GPROFL_EIRQ_EN:1;      /* TIM_GPROFL_IRQ interrupt enable. */
      vuint32_t CNTOFL_EIRQ_EN:1;      /* TIM_CNTOFLx_IRQ interrupt enable. */
      vuint32_t ECNTOFL_EIRQ_EN:1;     /* TIM_ECNTOFLx_IRQ interrupt enable. */
      vuint32_t NEWVAL_EIRQ_EN:1;      /* TIM_NEWVALx_EIRQ error interrupt enable. */
    } B;
  } CH0_EIRQ_EN;

  uint8_t TIM_reserved0[56];
  union {                              /* TIM Input Source Register */
    vuint32_t R;
    struct {
      vuint32_t MODE_7:2;              /* Input source to Channel 7 */
      vuint32_t VAL_7:2;               /* Value to be fed to Channel 7 */
      vuint32_t MODE_6:2;              /* Input source to Channel 6 */
      vuint32_t VAL_6:2;               /* Value to be fed to Channel 6 */
      vuint32_t MODE_5:2;              /* Input source to Channel 5 */
      vuint32_t VAL_5:2;               /* Value to be fed to Channel 5 */
      vuint32_t MODE_4:2;              /* Input source to Channel 4 */
      vuint32_t VAL_4:2;               /* Value to be fed to Channel 4 */
      vuint32_t MODE_3:2;              /* Input source to Channel 3 */
      vuint32_t VAL_3:2;               /* Value to be fed to Channel 3 */
      vuint32_t MODE_2:2;              /* Input source to Channel 2 */
      vuint32_t VAL_2:2;               /* Value to be fed to Channel 2 */
      vuint32_t MODE_1:2;              /* Input source to Channel 1 */
      vuint32_t VAL_1:2;               /* Value to be fed to Channel 1 */
      vuint32_t MODE_0:2;              /* Input source to Channel 0 */
      vuint32_t VAL_0:2;               /* Value to be fed to Channel 0 */
    } B;
  } IN_SRC;

  union {                              /* TIM Channel Reset Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t RST_CH7:1;             /* Software reset of channel 7. */
      vuint32_t RST_CH6:1;             /* Software reset of channel 6. */
      vuint32_t RST_CH5:1;             /* Software reset of channel 5. */
      vuint32_t RST_CH4:1;             /* Software reset of channel 4. */
      vuint32_t RST_CH3:1;             /* Software reset of channel 3. */
      vuint32_t RST_CH2:1;             /* Software reset of channel 2. */
      vuint32_t RST_CH1:1;             /* Software reset of channel 1. */
      vuint32_t RST_CH0:1;             /* Software reset of channel 0. */
    } B;
  } RST;

  union {                              /* TIM Channel n General Purpose Register 0, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t GPR0:24;               /* Input signal characteristic parameter 0. */
    } B;
  } CH1_GPR0;

  union {                              /* TIM Channel n General Purpose Register 1, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t GPR1:24;               /* Input signal characteristic parameter 1. */
    } B;
  } CH1_GPR1;

  union {                              /* TIM Channel n Count Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CNT:24;                /* Actual SMU counter value. */
    } B;
  } CH1_CNT;

  union {                              /* TIM Channel n Edge Counter Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t ECNT:16;               /* Edge counter. */
    } B;
  } CH1_ECNT;

  union {                              /* TIM Channel n Counter Shadow Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t CNTS:24;               /* Counter shadow register. */
    } B;
  } CH1_CNTS;

  union {                              /* TIM Channel n TDUC Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t TO_CNT:8;              /* Current Timeout value for channel n (n:0...m-1). */
    } B;
  } CH1_TDUC;

  union {                              /* TIM Channel n TDUV Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t TCS:3;                 /* Timeout Clock selection. */
      vuint32_t  :20;
      vuint32_t TOV:8;                 /* Time out duration for channel n (n:0...m-1). */
    } B;
  } CH1_TDUV;

  union {                              /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t FLT_RE:24;             /* Filter parameter for rising edge. */
    } B;
  } CH1_FLT_RE;

  union {                              /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t FLT_FE:24;             /* Filter parameter for falling edge. */
    } B;
  } CH1_FLT_FE;

  union {                              /* TIM Channel n Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t TOCTRL:2;              /* Timeout control */
      vuint32_t EGPR1_SEL:1;           /* Extension of GPR1_SEL bit field. */
      vuint32_t EGPR0_SEL:1;           /* Extension of GPR0_SEL bit field. */
      vuint32_t FR_ECNT_OFL:1;         /* Extended Edge counter overflow behavior. */
      vuint32_t CLK_SEL:3;             /* CMU clock source select for channel. */
      vuint32_t FLT_CTR_FE:1;          /* Filter counter mode for falling edge. */
      vuint32_t FLT_MODE_FE:1;         /* Filter mode for falling edge. */
      vuint32_t FLT_CTR_RE:1;          /* Filter counter mode for rising edge. */
      vuint32_t FLT_MODE_RE:1;         /* Filter mode for rising edge. */
      vuint32_t EXT_CAP_EN:1;          /* Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses, the input event changes are ignored. */
      vuint32_t FLT_CNT_FRQ:2;         /* Filter counter frequency select. */
      vuint32_t FLT_EN:1;              /* Filter enable for channel n. */
      vuint32_t ECNT_RESET:1;          /* Enables resetting the ECNT counter in periodic sampling mode. */
      vuint32_t ISL:1;                 /* Ignore Signal Level. */
      vuint32_t DSL:1;                 /* Signal level control. */
      vuint32_t CNTS_SEL:1;            /* Selection for CNTS register. */
      vuint32_t GPR1_SEL:2;            /* Selection for GPR1 register. */
      vuint32_t GPR0_SEL:2;            /* Selection for GPR0 register. */
      vuint32_t TBU0_SEL:1;            /* TBU_TS0 bits input select for TIM_CHn_GPRz (z: 0, 1) */
      vuint32_t CICTRL:1;              /* Channel Input Control. */
      vuint32_t ARU_EN:1;              /* GPR0 and GPR1 register values routed to ARU. */
      vuint32_t OSM:1;                 /* One-shot mode. */
      vuint32_t TIM_MODE:3;            /* TIM channel n mode. */
      vuint32_t TIM_EN:1;              /* TIM channel n enable. */
    } B;
  } CH1_CTRL;

  union {                              /* TIM Channel n External Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t EXT_CAP_SRC:3;         /* Defines selected source for triggering the EXT_CAPTURE functionality. */
    } B;
  } CH1_ECTRL;

  union {                              /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET:1;           /* Glitch detected on channel n. */
      vuint32_t TODET:1;               /* Timeout reached for input signal of channel n. */
      vuint32_t GPROFL:1;              /* GPR0 and GPR1 data overflow, old data not read out before new data has arrived at input pin. */
      vuint32_t CNTOFL:1;              /* SMU CNT counter overflow of channel n. */
      vuint32_t ECNTOFL:1;             /* ECNT counter overflow of channel n. */
      vuint32_t NEWVAL:1;              /* New measurement value detected by in channel n */
    } B;
  } CH1_IRQ_NOTIFY;

  union {                              /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET_IRQ_EN:1;    /* TIM_GLITCHDETx_IRQ interrupt enable. */
      vuint32_t TODET_IRQ_EN:1;        /* TIM_TODETn_IRQ interrupt enable. */
      vuint32_t GPROFL_IRQ_EN:1;       /* TIM_GPROFL_IRQ interrupt enable. */
      vuint32_t CNTOFL_IRQ_EN:1;       /* TIM_CNTOFLn_IRQ interrupt enable. */
      vuint32_t ECNTOFL_IRQ_EN:1;      /* TIM_ECNTOFLn_IRQ interrupt enable. */
      vuint32_t NEWVAL_IRQ_EN:1;       /* TIM_NEWVALn_IRQ interrupt enable. */
    } B;
  } CH1_IRQ_EN;

  union {                              /* TIM Channel n Force Interrupt Request Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t TRG_GLITCHDET:1;       /* Trigger bit TIM_CHn_IRQ_NOTIFY[GLITCHDET] by software. */
      vuint32_t TRG_TODET:1;           /* Trigger bit TIM_CHn_IRQ_NOTIFY[TODET] by software. */
      vuint32_t TRG_GPROFL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[GPROFL] by software. */
      vuint32_t TRG_CNTOFL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[CNTOFL] by software. */
      vuint32_t TRG_ECNTOFL:1;         /* Trigger bit TIM_CHn_IRQ_NOTIFY[ECNTOFL] by software. */
      vuint32_t TRG_NEWVAL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[NEWVAL] by software. */
    } B;
  } CH1_IRQ_FORCINT;

  union {                              /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH1_IRQ_MODE;

  union {                              /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET_EIRQ_EN:1;   /* TIM_GLITCHDETx_IRQ interrupt enable. */
      vuint32_t TODET_EIRQ_EN:1;       /* TIM_TODETx_IRQ interrupt enable. */
      vuint32_t GPROFL_EIRQ_EN:1;      /* TIM_GPROFL_IRQ interrupt enable. */
      vuint32_t CNTOFL_EIRQ_EN:1;      /* TIM_CNTOFLx_IRQ interrupt enable. */
      vuint32_t ECNTOFL_EIRQ_EN:1;     /* TIM_ECNTOFLx_IRQ interrupt enable. */
      vuint32_t NEWVAL_EIRQ_EN:1;      /* TIM_NEWVALx_EIRQ error interrupt enable. */
    } B;
  } CH1_EIRQ_EN;

  uint8_t TIM_reserved1[64];
  union {                              /* TIM Channel n General Purpose Register 0, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t GPR0:24;               /* Input signal characteristic parameter 0. */
    } B;
  } CH2_GPR0;

  union {                              /* TIM Channel n General Purpose Register 1, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t GPR1:24;               /* Input signal characteristic parameter 1. */
    } B;
  } CH2_GPR1;

  union {                              /* TIM Channel n Count Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CNT:24;                /* Actual SMU counter value. */
    } B;
  } CH2_CNT;

  union {                              /* TIM Channel n Edge Counter Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t ECNT:16;               /* Edge counter. */
    } B;
  } CH2_ECNT;

  union {                              /* TIM Channel n Counter Shadow Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t CNTS:24;               /* Counter shadow register. */
    } B;
  } CH2_CNTS;

  union {                              /* TIM Channel n TDUC Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t TO_CNT:8;              /* Current Timeout value for channel n (n:0...m-1). */
    } B;
  } CH2_TDUC;

  union {                              /* TIM Channel n TDUV Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t TCS:3;                 /* Timeout Clock selection. */
      vuint32_t  :20;
      vuint32_t TOV:8;                 /* Time out duration for channel n (n:0...m-1). */
    } B;
  } CH2_TDUV;

  union {                              /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t FLT_RE:24;             /* Filter parameter for rising edge. */
    } B;
  } CH2_FLT_RE;

  union {                              /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t FLT_FE:24;             /* Filter parameter for falling edge. */
    } B;
  } CH2_FLT_FE;

  union {                              /* TIM Channel n Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t TOCTRL:2;              /* Timeout control */
      vuint32_t EGPR1_SEL:1;           /* Extension of GPR1_SEL bit field. */
      vuint32_t EGPR0_SEL:1;           /* Extension of GPR0_SEL bit field. */
      vuint32_t FR_ECNT_OFL:1;         /* Extended Edge counter overflow behavior. */
      vuint32_t CLK_SEL:3;             /* CMU clock source select for channel. */
      vuint32_t FLT_CTR_FE:1;          /* Filter counter mode for falling edge. */
      vuint32_t FLT_MODE_FE:1;         /* Filter mode for falling edge. */
      vuint32_t FLT_CTR_RE:1;          /* Filter counter mode for rising edge. */
      vuint32_t FLT_MODE_RE:1;         /* Filter mode for rising edge. */
      vuint32_t EXT_CAP_EN:1;          /* Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses, the input event changes are ignored. */
      vuint32_t FLT_CNT_FRQ:2;         /* Filter counter frequency select. */
      vuint32_t FLT_EN:1;              /* Filter enable for channel n. */
      vuint32_t ECNT_RESET:1;          /* Enables resetting the ECNT counter in periodic sampling mode. */
      vuint32_t ISL:1;                 /* Ignore Signal Level. */
      vuint32_t DSL:1;                 /* Signal level control. */
      vuint32_t CNTS_SEL:1;            /* Selection for CNTS register. */
      vuint32_t GPR1_SEL:2;            /* Selection for GPR1 register. */
      vuint32_t GPR0_SEL:2;            /* Selection for GPR0 register. */
      vuint32_t TBU0_SEL:1;            /* TBU_TS0 bits input select for TIM_CHn_GPRz (z: 0, 1) */
      vuint32_t CICTRL:1;              /* Channel Input Control. */
      vuint32_t ARU_EN:1;              /* GPR0 and GPR1 register values routed to ARU. */
      vuint32_t OSM:1;                 /* One-shot mode. */
      vuint32_t TIM_MODE:3;            /* TIM channel n mode. */
      vuint32_t TIM_EN:1;              /* TIM channel n enable. */
    } B;
  } CH2_CTRL;

  union {                              /* TIM Channel n External Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t EXT_CAP_SRC:3;         /* Defines selected source for triggering the EXT_CAPTURE functionality. */
    } B;
  } CH2_ECTRL;

  union {                              /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET:1;           /* Glitch detected on channel n. */
      vuint32_t TODET:1;               /* Timeout reached for input signal of channel n. */
      vuint32_t GPROFL:1;              /* GPR0 and GPR1 data overflow, old data not read out before new data has arrived at input pin. */
      vuint32_t CNTOFL:1;              /* SMU CNT counter overflow of channel n. */
      vuint32_t ECNTOFL:1;             /* ECNT counter overflow of channel n. */
      vuint32_t NEWVAL:1;              /* New measurement value detected by in channel n */
    } B;
  } CH2_IRQ_NOTIFY;

  union {                              /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET_IRQ_EN:1;    /* TIM_GLITCHDETx_IRQ interrupt enable. */
      vuint32_t TODET_IRQ_EN:1;        /* TIM_TODETn_IRQ interrupt enable. */
      vuint32_t GPROFL_IRQ_EN:1;       /* TIM_GPROFL_IRQ interrupt enable. */
      vuint32_t CNTOFL_IRQ_EN:1;       /* TIM_CNTOFLn_IRQ interrupt enable. */
      vuint32_t ECNTOFL_IRQ_EN:1;      /* TIM_ECNTOFLn_IRQ interrupt enable. */
      vuint32_t NEWVAL_IRQ_EN:1;       /* TIM_NEWVALn_IRQ interrupt enable. */
    } B;
  } CH2_IRQ_EN;

  union {                              /* TIM Channel n Force Interrupt Request Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t TRG_GLITCHDET:1;       /* Trigger bit TIM_CHn_IRQ_NOTIFY[GLITCHDET] by software. */
      vuint32_t TRG_TODET:1;           /* Trigger bit TIM_CHn_IRQ_NOTIFY[TODET] by software. */
      vuint32_t TRG_GPROFL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[GPROFL] by software. */
      vuint32_t TRG_CNTOFL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[CNTOFL] by software. */
      vuint32_t TRG_ECNTOFL:1;         /* Trigger bit TIM_CHn_IRQ_NOTIFY[ECNTOFL] by software. */
      vuint32_t TRG_NEWVAL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[NEWVAL] by software. */
    } B;
  } CH2_IRQ_FORCINT;

  union {                              /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH2_IRQ_MODE;

  union {                              /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET_EIRQ_EN:1;   /* TIM_GLITCHDETx_IRQ interrupt enable. */
      vuint32_t TODET_EIRQ_EN:1;       /* TIM_TODETx_IRQ interrupt enable. */
      vuint32_t GPROFL_EIRQ_EN:1;      /* TIM_GPROFL_IRQ interrupt enable. */
      vuint32_t CNTOFL_EIRQ_EN:1;      /* TIM_CNTOFLx_IRQ interrupt enable. */
      vuint32_t ECNTOFL_EIRQ_EN:1;     /* TIM_ECNTOFLx_IRQ interrupt enable. */
      vuint32_t NEWVAL_EIRQ_EN:1;      /* TIM_NEWVALx_EIRQ error interrupt enable. */
    } B;
  } CH2_EIRQ_EN;

  uint8_t TIM_reserved2[64];
  union {                              /* TIM Channel n General Purpose Register 0, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t GPR0:24;               /* Input signal characteristic parameter 0. */
    } B;
  } CH3_GPR0;

  union {                              /* TIM Channel n General Purpose Register 1, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t GPR1:24;               /* Input signal characteristic parameter 1. */
    } B;
  } CH3_GPR1;

  union {                              /* TIM Channel n Count Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CNT:24;                /* Actual SMU counter value. */
    } B;
  } CH3_CNT;

  union {                              /* TIM Channel n Edge Counter Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t ECNT:16;               /* Edge counter. */
    } B;
  } CH3_ECNT;

  union {                              /* TIM Channel n Counter Shadow Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t CNTS:24;               /* Counter shadow register. */
    } B;
  } CH3_CNTS;

  union {                              /* TIM Channel n TDUC Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t TO_CNT:8;              /* Current Timeout value for channel n (n:0...m-1). */
    } B;
  } CH3_TDUC;

  union {                              /* TIM Channel n TDUV Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t TCS:3;                 /* Timeout Clock selection. */
      vuint32_t  :20;
      vuint32_t TOV:8;                 /* Time out duration for channel n (n:0...m-1). */
    } B;
  } CH3_TDUV;

  union {                              /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t FLT_RE:24;             /* Filter parameter for rising edge. */
    } B;
  } CH3_FLT_RE;

  union {                              /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t FLT_FE:24;             /* Filter parameter for falling edge. */
    } B;
  } CH3_FLT_FE;

  union {                              /* TIM Channel n Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t TOCTRL:2;              /* Timeout control */
      vuint32_t EGPR1_SEL:1;           /* Extension of GPR1_SEL bit field. */
      vuint32_t EGPR0_SEL:1;           /* Extension of GPR0_SEL bit field. */
      vuint32_t FR_ECNT_OFL:1;         /* Extended Edge counter overflow behavior. */
      vuint32_t CLK_SEL:3;             /* CMU clock source select for channel. */
      vuint32_t FLT_CTR_FE:1;          /* Filter counter mode for falling edge. */
      vuint32_t FLT_MODE_FE:1;         /* Filter mode for falling edge. */
      vuint32_t FLT_CTR_RE:1;          /* Filter counter mode for rising edge. */
      vuint32_t FLT_MODE_RE:1;         /* Filter mode for rising edge. */
      vuint32_t EXT_CAP_EN:1;          /* Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses, the input event changes are ignored. */
      vuint32_t FLT_CNT_FRQ:2;         /* Filter counter frequency select. */
      vuint32_t FLT_EN:1;              /* Filter enable for channel n. */
      vuint32_t ECNT_RESET:1;          /* Enables resetting the ECNT counter in periodic sampling mode. */
      vuint32_t ISL:1;                 /* Ignore Signal Level. */
      vuint32_t DSL:1;                 /* Signal level control. */
      vuint32_t CNTS_SEL:1;            /* Selection for CNTS register. */
      vuint32_t GPR1_SEL:2;            /* Selection for GPR1 register. */
      vuint32_t GPR0_SEL:2;            /* Selection for GPR0 register. */
      vuint32_t TBU0_SEL:1;            /* TBU_TS0 bits input select for TIM_CHn_GPRz (z: 0, 1) */
      vuint32_t CICTRL:1;              /* Channel Input Control. */
      vuint32_t ARU_EN:1;              /* GPR0 and GPR1 register values routed to ARU. */
      vuint32_t OSM:1;                 /* One-shot mode. */
      vuint32_t TIM_MODE:3;            /* TIM channel n mode. */
      vuint32_t TIM_EN:1;              /* TIM channel n enable. */
    } B;
  } CH3_CTRL;

  union {                              /* TIM Channel n External Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t EXT_CAP_SRC:3;         /* Defines selected source for triggering the EXT_CAPTURE functionality. */
    } B;
  } CH3_ECTRL;

  union {                              /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET:1;           /* Glitch detected on channel n. */
      vuint32_t TODET:1;               /* Timeout reached for input signal of channel n. */
      vuint32_t GPROFL:1;              /* GPR0 and GPR1 data overflow, old data not read out before new data has arrived at input pin. */
      vuint32_t CNTOFL:1;              /* SMU CNT counter overflow of channel n. */
      vuint32_t ECNTOFL:1;             /* ECNT counter overflow of channel n. */
      vuint32_t NEWVAL:1;              /* New measurement value detected by in channel n */
    } B;
  } CH3_IRQ_NOTIFY;

  union {                              /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET_IRQ_EN:1;    /* TIM_GLITCHDETx_IRQ interrupt enable. */
      vuint32_t TODET_IRQ_EN:1;        /* TIM_TODETn_IRQ interrupt enable. */
      vuint32_t GPROFL_IRQ_EN:1;       /* TIM_GPROFL_IRQ interrupt enable. */
      vuint32_t CNTOFL_IRQ_EN:1;       /* TIM_CNTOFLn_IRQ interrupt enable. */
      vuint32_t ECNTOFL_IRQ_EN:1;      /* TIM_ECNTOFLn_IRQ interrupt enable. */
      vuint32_t NEWVAL_IRQ_EN:1;       /* TIM_NEWVALn_IRQ interrupt enable. */
    } B;
  } CH3_IRQ_EN;

  union {                              /* TIM Channel n Force Interrupt Request Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t TRG_GLITCHDET:1;       /* Trigger bit TIM_CHn_IRQ_NOTIFY[GLITCHDET] by software. */
      vuint32_t TRG_TODET:1;           /* Trigger bit TIM_CHn_IRQ_NOTIFY[TODET] by software. */
      vuint32_t TRG_GPROFL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[GPROFL] by software. */
      vuint32_t TRG_CNTOFL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[CNTOFL] by software. */
      vuint32_t TRG_ECNTOFL:1;         /* Trigger bit TIM_CHn_IRQ_NOTIFY[ECNTOFL] by software. */
      vuint32_t TRG_NEWVAL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[NEWVAL] by software. */
    } B;
  } CH3_IRQ_FORCINT;

  union {                              /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH3_IRQ_MODE;

  union {                              /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET_EIRQ_EN:1;   /* TIM_GLITCHDETx_IRQ interrupt enable. */
      vuint32_t TODET_EIRQ_EN:1;       /* TIM_TODETx_IRQ interrupt enable. */
      vuint32_t GPROFL_EIRQ_EN:1;      /* TIM_GPROFL_IRQ interrupt enable. */
      vuint32_t CNTOFL_EIRQ_EN:1;      /* TIM_CNTOFLx_IRQ interrupt enable. */
      vuint32_t ECNTOFL_EIRQ_EN:1;     /* TIM_ECNTOFLx_IRQ interrupt enable. */
      vuint32_t NEWVAL_EIRQ_EN:1;      /* TIM_NEWVALx_EIRQ error interrupt enable. */
    } B;
  } CH3_EIRQ_EN;

  uint8_t TIM_reserved3[64];
  union {                              /* TIM Channel n General Purpose Register 0, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t GPR0:24;               /* Input signal characteristic parameter 0. */
    } B;
  } CH4_GPR0;

  union {                              /* TIM Channel n General Purpose Register 1, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t GPR1:24;               /* Input signal characteristic parameter 1. */
    } B;
  } CH4_GPR1;

  union {                              /* TIM Channel n Count Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CNT:24;                /* Actual SMU counter value. */
    } B;
  } CH4_CNT;

  union {                              /* TIM Channel n Edge Counter Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t ECNT:16;               /* Edge counter. */
    } B;
  } CH4_ECNT;

  union {                              /* TIM Channel n Counter Shadow Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t CNTS:24;               /* Counter shadow register. */
    } B;
  } CH4_CNTS;

  union {                              /* TIM Channel n TDUC Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t TO_CNT:8;              /* Current Timeout value for channel n (n:0...m-1). */
    } B;
  } CH4_TDUC;

  union {                              /* TIM Channel n TDUV Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t TCS:3;                 /* Timeout Clock selection. */
      vuint32_t  :20;
      vuint32_t TOV:8;                 /* Time out duration for channel n (n:0...m-1). */
    } B;
  } CH4_TDUV;

  union {                              /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t FLT_RE:24;             /* Filter parameter for rising edge. */
    } B;
  } CH4_FLT_RE;

  union {                              /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t FLT_FE:24;             /* Filter parameter for falling edge. */
    } B;
  } CH4_FLT_FE;

  union {                              /* TIM Channel n Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t TOCTRL:2;              /* Timeout control */
      vuint32_t EGPR1_SEL:1;           /* Extension of GPR1_SEL bit field. */
      vuint32_t EGPR0_SEL:1;           /* Extension of GPR0_SEL bit field. */
      vuint32_t FR_ECNT_OFL:1;         /* Extended Edge counter overflow behavior. */
      vuint32_t CLK_SEL:3;             /* CMU clock source select for channel. */
      vuint32_t FLT_CTR_FE:1;          /* Filter counter mode for falling edge. */
      vuint32_t FLT_MODE_FE:1;         /* Filter mode for falling edge. */
      vuint32_t FLT_CTR_RE:1;          /* Filter counter mode for rising edge. */
      vuint32_t FLT_MODE_RE:1;         /* Filter mode for rising edge. */
      vuint32_t EXT_CAP_EN:1;          /* Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses, the input event changes are ignored. */
      vuint32_t FLT_CNT_FRQ:2;         /* Filter counter frequency select. */
      vuint32_t FLT_EN:1;              /* Filter enable for channel n. */
      vuint32_t ECNT_RESET:1;          /* Enables resetting the ECNT counter in periodic sampling mode. */
      vuint32_t ISL:1;                 /* Ignore Signal Level. */
      vuint32_t DSL:1;                 /* Signal level control. */
      vuint32_t CNTS_SEL:1;            /* Selection for CNTS register. */
      vuint32_t GPR1_SEL:2;            /* Selection for GPR1 register. */
      vuint32_t GPR0_SEL:2;            /* Selection for GPR0 register. */
      vuint32_t TBU0_SEL:1;            /* TBU_TS0 bits input select for TIM_CHn_GPRz (z: 0, 1) */
      vuint32_t CICTRL:1;              /* Channel Input Control. */
      vuint32_t ARU_EN:1;              /* GPR0 and GPR1 register values routed to ARU. */
      vuint32_t OSM:1;                 /* One-shot mode. */
      vuint32_t TIM_MODE:3;            /* TIM channel n mode. */
      vuint32_t TIM_EN:1;              /* TIM channel n enable. */
    } B;
  } CH4_CTRL;

  union {                              /* TIM Channel n External Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t EXT_CAP_SRC:3;         /* Defines selected source for triggering the EXT_CAPTURE functionality. */
    } B;
  } CH4_ECTRL;

  union {                              /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET:1;           /* Glitch detected on channel n. */
      vuint32_t TODET:1;               /* Timeout reached for input signal of channel n. */
      vuint32_t GPROFL:1;              /* GPR0 and GPR1 data overflow, old data not read out before new data has arrived at input pin. */
      vuint32_t CNTOFL:1;              /* SMU CNT counter overflow of channel n. */
      vuint32_t ECNTOFL:1;             /* ECNT counter overflow of channel n. */
      vuint32_t NEWVAL:1;              /* New measurement value detected by in channel n */
    } B;
  } CH4_IRQ_NOTIFY;

  union {                              /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET_IRQ_EN:1;    /* TIM_GLITCHDETx_IRQ interrupt enable. */
      vuint32_t TODET_IRQ_EN:1;        /* TIM_TODETn_IRQ interrupt enable. */
      vuint32_t GPROFL_IRQ_EN:1;       /* TIM_GPROFL_IRQ interrupt enable. */
      vuint32_t CNTOFL_IRQ_EN:1;       /* TIM_CNTOFLn_IRQ interrupt enable. */
      vuint32_t ECNTOFL_IRQ_EN:1;      /* TIM_ECNTOFLn_IRQ interrupt enable. */
      vuint32_t NEWVAL_IRQ_EN:1;       /* TIM_NEWVALn_IRQ interrupt enable. */
    } B;
  } CH4_IRQ_EN;

  union {                              /* TIM Channel n Force Interrupt Request Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t TRG_GLITCHDET:1;       /* Trigger bit TIM_CHn_IRQ_NOTIFY[GLITCHDET] by software. */
      vuint32_t TRG_TODET:1;           /* Trigger bit TIM_CHn_IRQ_NOTIFY[TODET] by software. */
      vuint32_t TRG_GPROFL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[GPROFL] by software. */
      vuint32_t TRG_CNTOFL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[CNTOFL] by software. */
      vuint32_t TRG_ECNTOFL:1;         /* Trigger bit TIM_CHn_IRQ_NOTIFY[ECNTOFL] by software. */
      vuint32_t TRG_NEWVAL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[NEWVAL] by software. */
    } B;
  } CH4_IRQ_FORCINT;

  union {                              /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH4_IRQ_MODE;

  union {                              /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET_EIRQ_EN:1;   /* TIM_GLITCHDETx_IRQ interrupt enable. */
      vuint32_t TODET_EIRQ_EN:1;       /* TIM_TODETx_IRQ interrupt enable. */
      vuint32_t GPROFL_EIRQ_EN:1;      /* TIM_GPROFL_IRQ interrupt enable. */
      vuint32_t CNTOFL_EIRQ_EN:1;      /* TIM_CNTOFLx_IRQ interrupt enable. */
      vuint32_t ECNTOFL_EIRQ_EN:1;     /* TIM_ECNTOFLx_IRQ interrupt enable. */
      vuint32_t NEWVAL_EIRQ_EN:1;      /* TIM_NEWVALx_EIRQ error interrupt enable. */
    } B;
  } CH4_EIRQ_EN;

  uint8_t TIM_reserved4[64];
  union {                              /* TIM Channel n General Purpose Register 0, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t GPR0:24;               /* Input signal characteristic parameter 0. */
    } B;
  } CH5_GPR0;

  union {                              /* TIM Channel n General Purpose Register 1, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t GPR1:24;               /* Input signal characteristic parameter 1. */
    } B;
  } CH5_GPR1;

  union {                              /* TIM Channel n Count Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CNT:24;                /* Actual SMU counter value. */
    } B;
  } CH5_CNT;

  union {                              /* TIM Channel n Edge Counter Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t ECNT:16;               /* Edge counter. */
    } B;
  } CH5_ECNT;

  union {                              /* TIM Channel n Counter Shadow Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t CNTS:24;               /* Counter shadow register. */
    } B;
  } CH5_CNTS;

  union {                              /* TIM Channel n TDUC Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t TO_CNT:8;              /* Current Timeout value for channel n (n:0...m-1). */
    } B;
  } CH5_TDUC;

  union {                              /* TIM Channel n TDUV Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t TCS:3;                 /* Timeout Clock selection. */
      vuint32_t  :20;
      vuint32_t TOV:8;                 /* Time out duration for channel n (n:0...m-1). */
    } B;
  } CH5_TDUV;

  union {                              /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t FLT_RE:24;             /* Filter parameter for rising edge. */
    } B;
  } CH5_FLT_RE;

  union {                              /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t FLT_FE:24;             /* Filter parameter for falling edge. */
    } B;
  } CH5_FLT_FE;

  union {                              /* TIM Channel n Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t TOCTRL:2;              /* Timeout control */
      vuint32_t EGPR1_SEL:1;           /* Extension of GPR1_SEL bit field. */
      vuint32_t EGPR0_SEL:1;           /* Extension of GPR0_SEL bit field. */
      vuint32_t FR_ECNT_OFL:1;         /* Extended Edge counter overflow behavior. */
      vuint32_t CLK_SEL:3;             /* CMU clock source select for channel. */
      vuint32_t FLT_CTR_FE:1;          /* Filter counter mode for falling edge. */
      vuint32_t FLT_MODE_FE:1;         /* Filter mode for falling edge. */
      vuint32_t FLT_CTR_RE:1;          /* Filter counter mode for rising edge. */
      vuint32_t FLT_MODE_RE:1;         /* Filter mode for rising edge. */
      vuint32_t EXT_CAP_EN:1;          /* Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses, the input event changes are ignored. */
      vuint32_t FLT_CNT_FRQ:2;         /* Filter counter frequency select. */
      vuint32_t FLT_EN:1;              /* Filter enable for channel n. */
      vuint32_t ECNT_RESET:1;          /* Enables resetting the ECNT counter in periodic sampling mode. */
      vuint32_t ISL:1;                 /* Ignore Signal Level. */
      vuint32_t DSL:1;                 /* Signal level control. */
      vuint32_t CNTS_SEL:1;            /* Selection for CNTS register. */
      vuint32_t GPR1_SEL:2;            /* Selection for GPR1 register. */
      vuint32_t GPR0_SEL:2;            /* Selection for GPR0 register. */
      vuint32_t TBU0_SEL:1;            /* TBU_TS0 bits input select for TIM_CHn_GPRz (z: 0, 1) */
      vuint32_t CICTRL:1;              /* Channel Input Control. */
      vuint32_t ARU_EN:1;              /* GPR0 and GPR1 register values routed to ARU. */
      vuint32_t OSM:1;                 /* One-shot mode. */
      vuint32_t TIM_MODE:3;            /* TIM channel n mode. */
      vuint32_t TIM_EN:1;              /* TIM channel n enable. */
    } B;
  } CH5_CTRL;

  union {                              /* TIM Channel n External Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t EXT_CAP_SRC:3;         /* Defines selected source for triggering the EXT_CAPTURE functionality. */
    } B;
  } CH5_ECTRL;

  union {                              /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET:1;           /* Glitch detected on channel n. */
      vuint32_t TODET:1;               /* Timeout reached for input signal of channel n. */
      vuint32_t GPROFL:1;              /* GPR0 and GPR1 data overflow, old data not read out before new data has arrived at input pin. */
      vuint32_t CNTOFL:1;              /* SMU CNT counter overflow of channel n. */
      vuint32_t ECNTOFL:1;             /* ECNT counter overflow of channel n. */
      vuint32_t NEWVAL:1;              /* New measurement value detected by in channel n */
    } B;
  } CH5_IRQ_NOTIFY;

  union {                              /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET_IRQ_EN:1;    /* TIM_GLITCHDETx_IRQ interrupt enable. */
      vuint32_t TODET_IRQ_EN:1;        /* TIM_TODETn_IRQ interrupt enable. */
      vuint32_t GPROFL_IRQ_EN:1;       /* TIM_GPROFL_IRQ interrupt enable. */
      vuint32_t CNTOFL_IRQ_EN:1;       /* TIM_CNTOFLn_IRQ interrupt enable. */
      vuint32_t ECNTOFL_IRQ_EN:1;      /* TIM_ECNTOFLn_IRQ interrupt enable. */
      vuint32_t NEWVAL_IRQ_EN:1;       /* TIM_NEWVALn_IRQ interrupt enable. */
    } B;
  } CH5_IRQ_EN;

  union {                              /* TIM Channel n Force Interrupt Request Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t TRG_GLITCHDET:1;       /* Trigger bit TIM_CHn_IRQ_NOTIFY[GLITCHDET] by software. */
      vuint32_t TRG_TODET:1;           /* Trigger bit TIM_CHn_IRQ_NOTIFY[TODET] by software. */
      vuint32_t TRG_GPROFL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[GPROFL] by software. */
      vuint32_t TRG_CNTOFL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[CNTOFL] by software. */
      vuint32_t TRG_ECNTOFL:1;         /* Trigger bit TIM_CHn_IRQ_NOTIFY[ECNTOFL] by software. */
      vuint32_t TRG_NEWVAL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[NEWVAL] by software. */
    } B;
  } CH5_IRQ_FORCINT;

  union {                              /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH5_IRQ_MODE;

  union {                              /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET_EIRQ_EN:1;   /* TIM_GLITCHDETx_IRQ interrupt enable. */
      vuint32_t TODET_EIRQ_EN:1;       /* TIM_TODETx_IRQ interrupt enable. */
      vuint32_t GPROFL_EIRQ_EN:1;      /* TIM_GPROFL_IRQ interrupt enable. */
      vuint32_t CNTOFL_EIRQ_EN:1;      /* TIM_CNTOFLx_IRQ interrupt enable. */
      vuint32_t ECNTOFL_EIRQ_EN:1;     /* TIM_ECNTOFLx_IRQ interrupt enable. */
      vuint32_t NEWVAL_EIRQ_EN:1;      /* TIM_NEWVALx_EIRQ error interrupt enable. */
    } B;
  } CH5_EIRQ_EN;

  uint8_t TIM_reserved5[64];
  union {                              /* TIM Channel n General Purpose Register 0, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t GPR0:24;               /* Input signal characteristic parameter 0. */
    } B;
  } CH6_GPR0;

  union {                              /* TIM Channel n General Purpose Register 1, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t GPR1:24;               /* Input signal characteristic parameter 1. */
    } B;
  } CH6_GPR1;

  union {                              /* TIM Channel n Count Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CNT:24;                /* Actual SMU counter value. */
    } B;
  } CH6_CNT;

  union {                              /* TIM Channel n Edge Counter Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t ECNT:16;               /* Edge counter. */
    } B;
  } CH6_ECNT;

  union {                              /* TIM Channel n Counter Shadow Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t CNTS:24;               /* Counter shadow register. */
    } B;
  } CH6_CNTS;

  union {                              /* TIM Channel n TDUC Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t TO_CNT:8;              /* Current Timeout value for channel n (n:0...m-1). */
    } B;
  } CH6_TDUC;

  union {                              /* TIM Channel n TDUV Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t TCS:3;                 /* Timeout Clock selection. */
      vuint32_t  :20;
      vuint32_t TOV:8;                 /* Time out duration for channel n (n:0...m-1). */
    } B;
  } CH6_TDUV;

  union {                              /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t FLT_RE:24;             /* Filter parameter for rising edge. */
    } B;
  } CH6_FLT_RE;

  union {                              /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t FLT_FE:24;             /* Filter parameter for falling edge. */
    } B;
  } CH6_FLT_FE;

  union {                              /* TIM Channel n Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t TOCTRL:2;              /* Timeout control */
      vuint32_t EGPR1_SEL:1;           /* Extension of GPR1_SEL bit field. */
      vuint32_t EGPR0_SEL:1;           /* Extension of GPR0_SEL bit field. */
      vuint32_t FR_ECNT_OFL:1;         /* Extended Edge counter overflow behavior. */
      vuint32_t CLK_SEL:3;             /* CMU clock source select for channel. */
      vuint32_t FLT_CTR_FE:1;          /* Filter counter mode for falling edge. */
      vuint32_t FLT_MODE_FE:1;         /* Filter mode for falling edge. */
      vuint32_t FLT_CTR_RE:1;          /* Filter counter mode for rising edge. */
      vuint32_t FLT_MODE_RE:1;         /* Filter mode for rising edge. */
      vuint32_t EXT_CAP_EN:1;          /* Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses, the input event changes are ignored. */
      vuint32_t FLT_CNT_FRQ:2;         /* Filter counter frequency select. */
      vuint32_t FLT_EN:1;              /* Filter enable for channel n. */
      vuint32_t ECNT_RESET:1;          /* Enables resetting the ECNT counter in periodic sampling mode. */
      vuint32_t ISL:1;                 /* Ignore Signal Level. */
      vuint32_t DSL:1;                 /* Signal level control. */
      vuint32_t CNTS_SEL:1;            /* Selection for CNTS register. */
      vuint32_t GPR1_SEL:2;            /* Selection for GPR1 register. */
      vuint32_t GPR0_SEL:2;            /* Selection for GPR0 register. */
      vuint32_t TBU0_SEL:1;            /* TBU_TS0 bits input select for TIM_CHn_GPRz (z: 0, 1) */
      vuint32_t CICTRL:1;              /* Channel Input Control. */
      vuint32_t ARU_EN:1;              /* GPR0 and GPR1 register values routed to ARU. */
      vuint32_t OSM:1;                 /* One-shot mode. */
      vuint32_t TIM_MODE:3;            /* TIM channel n mode. */
      vuint32_t TIM_EN:1;              /* TIM channel n enable. */
    } B;
  } CH6_CTRL;

  union {                              /* TIM Channel n External Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t EXT_CAP_SRC:3;         /* Defines selected source for triggering the EXT_CAPTURE functionality. */
    } B;
  } CH6_ECTRL;

  union {                              /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET:1;           /* Glitch detected on channel n. */
      vuint32_t TODET:1;               /* Timeout reached for input signal of channel n. */
      vuint32_t GPROFL:1;              /* GPR0 and GPR1 data overflow, old data not read out before new data has arrived at input pin. */
      vuint32_t CNTOFL:1;              /* SMU CNT counter overflow of channel n. */
      vuint32_t ECNTOFL:1;             /* ECNT counter overflow of channel n. */
      vuint32_t NEWVAL:1;              /* New measurement value detected by in channel n */
    } B;
  } CH6_IRQ_NOTIFY;

  union {                              /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET_IRQ_EN:1;    /* TIM_GLITCHDETx_IRQ interrupt enable. */
      vuint32_t TODET_IRQ_EN:1;        /* TIM_TODETn_IRQ interrupt enable. */
      vuint32_t GPROFL_IRQ_EN:1;       /* TIM_GPROFL_IRQ interrupt enable. */
      vuint32_t CNTOFL_IRQ_EN:1;       /* TIM_CNTOFLn_IRQ interrupt enable. */
      vuint32_t ECNTOFL_IRQ_EN:1;      /* TIM_ECNTOFLn_IRQ interrupt enable. */
      vuint32_t NEWVAL_IRQ_EN:1;       /* TIM_NEWVALn_IRQ interrupt enable. */
    } B;
  } CH6_IRQ_EN;

  union {                              /* TIM Channel n Force Interrupt Request Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t TRG_GLITCHDET:1;       /* Trigger bit TIM_CHn_IRQ_NOTIFY[GLITCHDET] by software. */
      vuint32_t TRG_TODET:1;           /* Trigger bit TIM_CHn_IRQ_NOTIFY[TODET] by software. */
      vuint32_t TRG_GPROFL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[GPROFL] by software. */
      vuint32_t TRG_CNTOFL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[CNTOFL] by software. */
      vuint32_t TRG_ECNTOFL:1;         /* Trigger bit TIM_CHn_IRQ_NOTIFY[ECNTOFL] by software. */
      vuint32_t TRG_NEWVAL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[NEWVAL] by software. */
    } B;
  } CH6_IRQ_FORCINT;

  union {                              /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH6_IRQ_MODE;

  union {                              /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET_EIRQ_EN:1;   /* TIM_GLITCHDETx_IRQ interrupt enable. */
      vuint32_t TODET_EIRQ_EN:1;       /* TIM_TODETx_IRQ interrupt enable. */
      vuint32_t GPROFL_EIRQ_EN:1;      /* TIM_GPROFL_IRQ interrupt enable. */
      vuint32_t CNTOFL_EIRQ_EN:1;      /* TIM_CNTOFLx_IRQ interrupt enable. */
      vuint32_t ECNTOFL_EIRQ_EN:1;     /* TIM_ECNTOFLx_IRQ interrupt enable. */
      vuint32_t NEWVAL_EIRQ_EN:1;      /* TIM_NEWVALx_EIRQ error interrupt enable. */
    } B;
  } CH6_EIRQ_EN;

  uint8_t TIM_reserved6[64];
  union {                              /* TIM Channel n General Purpose Register 0, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t GPR0:24;               /* Input signal characteristic parameter 0. */
    } B;
  } CH7_GPR0;

  union {                              /* TIM Channel n General Purpose Register 1, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t GPR1:24;               /* Input signal characteristic parameter 1. */
    } B;
  } CH7_GPR1;

  union {                              /* TIM Channel n Count Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CNT:24;                /* Actual SMU counter value. */
    } B;
  } CH7_CNT;

  union {                              /* TIM Channel n Edge Counter Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t ECNT:16;               /* Edge counter. */
    } B;
  } CH7_ECNT;

  union {                              /* TIM Channel n Counter Shadow Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t ECNT:8;                /* Edge counter. */
      vuint32_t CNTS:24;               /* Counter shadow register. */
    } B;
  } CH7_CNTS;

  union {                              /* TIM Channel n TDUC Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t TO_CNT:8;              /* Current Timeout value for channel n (n:0...m-1). */
    } B;
  } CH7_TDUC;

  union {                              /* TIM Channel n TDUV Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t TCS:3;                 /* Timeout Clock selection. */
      vuint32_t  :20;
      vuint32_t TOV:8;                 /* Time out duration for channel n (n:0...m-1). */
    } B;
  } CH7_TDUV;

  union {                              /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t FLT_RE:24;             /* Filter parameter for rising edge. */
    } B;
  } CH7_FLT_RE;

  union {                              /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t FLT_FE:24;             /* Filter parameter for falling edge. */
    } B;
  } CH7_FLT_FE;

  union {                              /* TIM Channel n Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t TOCTRL:2;              /* Timeout control */
      vuint32_t EGPR1_SEL:1;           /* Extension of GPR1_SEL bit field. */
      vuint32_t EGPR0_SEL:1;           /* Extension of GPR0_SEL bit field. */
      vuint32_t FR_ECNT_OFL:1;         /* Extended Edge counter overflow behavior. */
      vuint32_t CLK_SEL:3;             /* CMU clock source select for channel. */
      vuint32_t FLT_CTR_FE:1;          /* Filter counter mode for falling edge. */
      vuint32_t FLT_MODE_FE:1;         /* Filter mode for falling edge. */
      vuint32_t FLT_CTR_RE:1;          /* Filter counter mode for rising edge. */
      vuint32_t FLT_MODE_RE:1;         /* Filter mode for rising edge. */
      vuint32_t EXT_CAP_EN:1;          /* Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses, the input event changes are ignored. */
      vuint32_t FLT_CNT_FRQ:2;         /* Filter counter frequency select. */
      vuint32_t FLT_EN:1;              /* Filter enable for channel n. */
      vuint32_t ECNT_RESET:1;          /* Enables resetting the ECNT counter in periodic sampling mode. */
      vuint32_t ISL:1;                 /* Ignore Signal Level. */
      vuint32_t DSL:1;                 /* Signal level control. */
      vuint32_t CNTS_SEL:1;            /* Selection for CNTS register. */
      vuint32_t GPR1_SEL:2;            /* Selection for GPR1 register. */
      vuint32_t GPR0_SEL:2;            /* Selection for GPR0 register. */
      vuint32_t TBU0_SEL:1;            /* TBU_TS0 bits input select for TIM_CHn_GPRz (z: 0, 1) */
      vuint32_t CICTRL:1;              /* Channel Input Control. */
      vuint32_t ARU_EN:1;              /* GPR0 and GPR1 register values routed to ARU. */
      vuint32_t OSM:1;                 /* One-shot mode. */
      vuint32_t TIM_MODE:3;            /* TIM channel n mode. */
      vuint32_t TIM_EN:1;              /* TIM channel n enable. */
    } B;
  } CH7_CTRL;

  union {                              /* TIM Channel n External Control Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t EXT_CAP_SRC:3;         /* Defines selected source for triggering the EXT_CAPTURE functionality. */
    } B;
  } CH7_ECTRL;

  union {                              /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET:1;           /* Glitch detected on channel n. */
      vuint32_t TODET:1;               /* Timeout reached for input signal of channel n. */
      vuint32_t GPROFL:1;              /* GPR0 and GPR1 data overflow, old data not read out before new data has arrived at input pin. */
      vuint32_t CNTOFL:1;              /* SMU CNT counter overflow of channel n. */
      vuint32_t ECNTOFL:1;             /* ECNT counter overflow of channel n. */
      vuint32_t NEWVAL:1;              /* New measurement value detected by in channel n */
    } B;
  } CH7_IRQ_NOTIFY;

  union {                              /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET_IRQ_EN:1;    /* TIM_GLITCHDETx_IRQ interrupt enable. */
      vuint32_t TODET_IRQ_EN:1;        /* TIM_TODETn_IRQ interrupt enable. */
      vuint32_t GPROFL_IRQ_EN:1;       /* TIM_GPROFL_IRQ interrupt enable. */
      vuint32_t CNTOFL_IRQ_EN:1;       /* TIM_CNTOFLn_IRQ interrupt enable. */
      vuint32_t ECNTOFL_IRQ_EN:1;      /* TIM_ECNTOFLn_IRQ interrupt enable. */
      vuint32_t NEWVAL_IRQ_EN:1;       /* TIM_NEWVALn_IRQ interrupt enable. */
    } B;
  } CH7_IRQ_EN;

  union {                              /* TIM Channel n Force Interrupt Request Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t TRG_GLITCHDET:1;       /* Trigger bit TIM_CHn_IRQ_NOTIFY[GLITCHDET] by software. */
      vuint32_t TRG_TODET:1;           /* Trigger bit TIM_CHn_IRQ_NOTIFY[TODET] by software. */
      vuint32_t TRG_GPROFL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[GPROFL] by software. */
      vuint32_t TRG_CNTOFL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[CNTOFL] by software. */
      vuint32_t TRG_ECNTOFL:1;         /* Trigger bit TIM_CHn_IRQ_NOTIFY[ECNTOFL] by software. */
      vuint32_t TRG_NEWVAL:1;          /* Trigger bit TIM_CHn_IRQ_NOTIFY[NEWVAL] by software. */
    } B;
  } CH7_IRQ_FORCINT;

  union {                              /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH7_IRQ_MODE;

  union {                              /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t GLITCHDET_EIRQ_EN:1;   /* TIM_GLITCHDETx_IRQ interrupt enable. */
      vuint32_t TODET_EIRQ_EN:1;       /* TIM_TODETx_IRQ interrupt enable. */
      vuint32_t GPROFL_EIRQ_EN:1;      /* TIM_GPROFL_IRQ interrupt enable. */
      vuint32_t CNTOFL_EIRQ_EN:1;      /* TIM_CNTOFLx_IRQ interrupt enable. */
      vuint32_t ECNTOFL_EIRQ_EN:1;     /* TIM_ECNTOFLx_IRQ interrupt enable. */
      vuint32_t NEWVAL_EIRQ_EN:1;      /* TIM_NEWVALx_EIRQ error interrupt enable. */
    } B;
  } CH7_EIRQ_EN;
};


/* ============================================================================
   =============================== Module: GTM_TOM ============================
   ============================================================================ */

struct GTM_TOM_tag {
  union {                              /* TOM Channel n Control Register, n[0:14] */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t GCM:1;                 /* Gated Counter Mode enable. */
      vuint32_t SPEM:1;                /* SPE mode enable for channel. */
      vuint32_t  :1;
      vuint32_t OSM:1;                 /* One-shot mode.. */
      vuint32_t  :1;
      vuint32_t TRIGOUT:1;             /* Trigger output selection (output signal TRIG_[n]) of module TOM_CH[n]. */
      vuint32_t  :3;
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :5;
      vuint32_t CLK_SRC_SR:3;          /* Clock source select for channel. */
      vuint32_t SL:1;                  /* Signal level for duty cycle. */
      vuint32_t  :11;
    } B;
  } CH0_CTRL;

  union {                              /* TOM Channel n Shadow 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR0:16;                /* TOM channel n shadow register SR0 for update of compare register CM0. */
    } B;
  } CH0_SR0;

  union {                              /* TOM Channel n Shadow 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR1:16;                /* TOM channel n shadow register SR1 for update of compare register CM1. */
    } B;
  } CH0_SR1;

  union {                              /* TOM Channel n Compare 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM0:16;                /* TOM CCU0 compare register. */
    } B;
  } CH0_CM0;

  union {                              /* TOM Channel n Compare 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM1:16;                /* TOM CCU1 compare register. */
    } B;
  } CH0_CM1;

  union {                              /* TOM Channel n CN0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CN0:16;                /* TOM CCU0 counter register. */
    } B;
  } CH0_CN0;

  union {                              /* TOM Channel n Status Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :31;                  /* Reserved. */
      vuint32_t OL:1;                  /* Output level of output TOM_OUT(n). */
    } B;
  } CH0_STAT;

  union {                              /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH0_IRQ_NOTIFY;

  union {                              /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH0_IRQ_EN;

  union {                              /* TOM Channel n Force Interrupt Request Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t TRG_CCU1TC0:1;         /* Trigger TOM_CCU1TC0_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC0:1;         /* Trigger TOM_CCU0TC0_IRQ interrupt by software. */
    } B;
  } CH0_IRQ_FORCINT;

  union {                              /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH0_IRQ_MODE;

  uint8_t TOM_reserved0[4];
  union {                              /* TOM TGC0 Global Control Register */
    vuint32_t R;
    struct {
      vuint32_t UPEN_CTRL7:2;          /* TOM channel 7 enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL6:2;          /* TOM channel 6 enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL5:2;          /* TOM channel 5 enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL4:2;          /* TOM channel 4 enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL3:2;          /* TOM channel 3 enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL2:2;          /* TOM channel 2 enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL1:2;          /* TOM channel 1 enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL0:2;          /* TOM channel 0 enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t RST_CH7:1;             /* Software reset of channel 7. */
      vuint32_t RST_CH6:1;             /* Software reset of channel 6. */
      vuint32_t RST_CH5:1;             /* Software reset of channel 5. */
      vuint32_t RST_CH4:1;             /* Software reset of channel 4. */
      vuint32_t RST_CH3:1;             /* Software reset of channel 3. */
      vuint32_t RST_CH2:1;             /* Software reset of channel 2. */
      vuint32_t RST_CH1:1;             /* Software reset of channel 1. */
      vuint32_t RST_CH0:1;             /* Software reset of channel 0. */
      vuint32_t  :7;
      vuint32_t HOST_TRIG:1;           /* Trigger request signal (see TGC0, TGC1) to update the register ENDIS_STAT and OUTEN_STAT. */
    } B;
  } TGC0_GLB_CTRL;

  union {                              /* TOM TGC0 Action Time Base Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t TBU_SEL:2;             /* Selection of time base used for comparison. */
      vuint32_t TB_TRIG:1;             /* Set trigger request. */
      vuint32_t ACT_TB:24;             /* Specifies the signed compare value with selected signal TBU_TS[n], x=0..2. */
    } B;
  } TGC0_ACT_TB;

  union {                              /* TOM TGC0 Force Update Control Register */
    vuint32_t R;
    struct {
      vuint32_t RSTCN0_CH7:2;          /* Reset CN0 of channel 7 on force update event. */
      vuint32_t RSTCN0_CH6:2;          /* Reset CN0 of channel 6 on force update event. */
      vuint32_t RSTCN0_CH5:2;          /* Reset CN0 of channel 5 on force update event. */
      vuint32_t RSTCN0_CH4:2;          /* Reset CN0 of channel 4 on force update event. */
      vuint32_t RSTCN0_CH3:2;          /* Reset CN0 of channel 3 on force update event. */
      vuint32_t RSTCN0_CH2:2;          /* Reset CN0 of channel 2 on force update event. */
      vuint32_t RSTCN0_CH1:2;          /* Reset CN0 of channel 1 on force update event. */
      vuint32_t RSTCN0_CH0:2;          /* Reset CN0 of channel 0 on force update event. */
      vuint32_t FUPD_CTRL7:2;          /* Force update of TOM channel 7 operation registers. */
      vuint32_t FUPD_CTRL6:2;          /* Force update of TOM channel 6 operation registers, */
      vuint32_t FUPD_CTRL5:2;          /* Force update of TOM channel 5 operation registers. */
      vuint32_t FUPD_CTRL4:2;          /* Force update of TOM channel 4 operation registers. */
      vuint32_t FUPD_CTRL3:2;          /* Force update of TOM channel 3 operation registers. */
      vuint32_t FUPD_CTRL2:2;          /* ce update of TOM channel 2 operation registers. */
      vuint32_t FUPD_CTRL1:2;          /* Force update of TOM channel 1 operation registers. */
      vuint32_t FUPD_CTRL0:2;          /* Force update of TOM channel 0 operation registers. */
    } B;
  } TGC0_FUPD_CTRL;

  union {                              /* TOM TGC0 Interrupt Trigger Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t INT_TRIG7:2;           /* Select input signal TRIG_7 as a trigger source. */
      vuint32_t INT_TRIG6:2;           /* Select input signal TRIG_6 as a trigger source. */
      vuint32_t INT_TRIG5:2;           /* Select input signal TRIG_5 as a trigger source. */
      vuint32_t INT_TRIG4:2;           /* Select input signal TRIG_4 as a trigger source. */
      vuint32_t INT_TRIG3:2;           /* Select input signal TRIG_3 as a trigger source. */
      vuint32_t INT_TRIG2:2;           /* Select input signal TRIG_2 as a trigger source. */
      vuint32_t INT_TRIG1:2;           /* Select input signal TRIG_1 as a trigger source. */
      vuint32_t INT_TRIG0:2;           /* Select input signal TRIG_0 as a trigger source. */
    } B;
  } TGC0_INT_TRIG;

  union {                              /* TOM Channel n Control Register, n[0:14] */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t GCM:1;                 /* Gated Counter Mode enable. */
      vuint32_t SPEM:1;                /* SPE mode enable for channel. */
      vuint32_t  :1;
      vuint32_t OSM:1;                 /* One-shot mode.. */
      vuint32_t  :1;
      vuint32_t TRIGOUT:1;             /* Trigger output selection (output signal TRIG_[n]) of module TOM_CH[n]. */
      vuint32_t  :3;
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :5;
      vuint32_t CLK_SRC_SR:3;          /* Clock source select for channel. */
      vuint32_t SL:1;                  /* Signal level for duty cycle. */
      vuint32_t  :11;
    } B;
  } CH1_CTRL;

  union {                              /* TOM Channel n Shadow 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR0:16;                /* TOM channel n shadow register SR0 for update of compare register CM0. */
    } B;
  } CH1_SR0;

  union {                              /* TOM Channel n Shadow 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR1:16;                /* TOM channel n shadow register SR1 for update of compare register CM1. */
    } B;
  } CH1_SR1;

  union {                              /* TOM Channel n Compare 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM0:16;                /* TOM CCU0 compare register. */
    } B;
  } CH1_CM0;

  union {                              /* TOM Channel n Compare 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM1:16;                /* TOM CCU1 compare register. */
    } B;
  } CH1_CM1;

  union {                              /* TOM Channel n CN0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CN0:16;                /* TOM CCU0 counter register. */
    } B;
  } CH1_CN0;

  union {                              /* TOM Channel n Status Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :31;                  /* Reserved. */
      vuint32_t OL:1;                  /* Output level of output TOM_OUT(n). */
    } B;
  } CH1_STAT;

  union {                              /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH1_IRQ_NOTIFY;

  union {                              /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH1_IRQ_EN;

  union {                              /* TOM Channel n Force Interrupt Request Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t TRG_CCU1TC0:1;         /* Trigger TOM_CCU1TC0_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC0:1;         /* Trigger TOM_CCU0TC0_IRQ interrupt by software. */
    } B;
  } CH1_IRQ_FORCINT;

  union {                              /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH1_IRQ_MODE;

  uint8_t TOM_reserved1[4];
  union {                              /* TOM TGC0 Enable/Disable Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t ENDIS_CTRL7:2;         /* Channel 7 enable/disable update value. */
      vuint32_t ENDIS_CTRL6:2;         /* Channel 6 enable/disable update value. */
      vuint32_t ENDIS_CTRL5:2;         /* Channel 5 enable/disable update value. */
      vuint32_t ENDIS_CTRL4:2;         /* TOM channel 4 enable/disable update value. */
      vuint32_t ENDIS_CTRL3:2;         /* TOM channel 3 enable/disable update value. */
      vuint32_t ENDIS_CTRL2:2;         /* TOM channel 2 enable/disable update value. */
      vuint32_t ENDIS_CTRL1:2;         /* TOM channel 1 enable/disable update value. */
      vuint32_t ENDIS_CTRL0:2;         /* TOM channel 0 enable/disable update value. */
    } B;
  } TGC0_ENDIS_CTRL;

  union {                              /* TOM TGC0 Enable/Disable Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t ENDIS_STAT7:2;         /* TOM channel 7 enable/disable. */
      vuint32_t ENDIS_STAT6:2;         /* TOM channel 6 enable/disable. */
      vuint32_t ENDIS_STAT5:2;         /* TOM channel 5 enable/disable. */
      vuint32_t ENDIS_STAT4:2;         /* TOM channel 4 enable/disable. */
      vuint32_t ENDIS_STAT3:2;         /* TOM channel 3 enable/disable. */
      vuint32_t ENDIS_STAT2:2;         /* TOM channel 2 enable/disable. */
      vuint32_t ENDIS_STAT1:2;         /* TOM channel 1 enable/disable. */
      vuint32_t ENDIS_STAT0:2;         /* TOM channel 0 enable/disable. */
    } B;
  } TGC0_ENDIS_STAT;

  union {                              /* TOM TGC0 Out Enable Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t OUTEN_CTRL7:2;         /* Output TOM_OUT(7) enable/disable update value. */
      vuint32_t OUTEN_CTRL6:2;         /* Output TOM_OUT(6) enable/disable update value. */
      vuint32_t OUTEN_CTRL5:2;         /* Output TOM_OUT(5) enable/disable update value. */
      vuint32_t OUTEN_CTRL4:2;         /* Output TOM_OUT(4) enable/disable update value. */
      vuint32_t OUTEN_CTRL3:2;         /* Output TOM_OUT(3) enable/disable update value. */
      vuint32_t OUTEN_CTRL2:2;         /* Output TOM_OUT(2) enable/disable update value. */
      vuint32_t OUTEN_CTRL1:2;         /* Output TOM_OUT(1) enable/disable update value. */
      vuint32_t OUTEN_CTRL0:2;         /* Output TOM_OUT(0) enable/disable update value. */
    } B;
  } TGC0_OUTEN_CTRL;

  union {                              /* TOM TGC0 Out Enable Control/Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t OUTEN_STAT7:2;         /* Control/status of output TOM_OUT(7). */
      vuint32_t OUTEN_STAT6:2;         /* Control/status of output TOM_OUT(6). */
      vuint32_t OUTEN_STAT5:2;         /* Control/status of output TOM_OUT(5). */
      vuint32_t OUTEN_STAT4:2;         /* Control/status of output TOM_OUT(4) */
      vuint32_t OUTEN_STAT3:2;         /* Control/status of output TOM_OUT(3). */
      vuint32_t OUTEN_STAT2:2;         /* Control/status of output TOM_OUT(2). */
      vuint32_t OUTEN_STAT1:2;         /* Control/status of output TOM_OUT(1). */
      vuint32_t OUTEN_STAT0:2;         /* Control/status of output TOM_OUT(0). */
    } B;
  } TGC0_OUTEN_STAT;

  union {                              /* TOM Channel n Control Register, n[0:14] */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t GCM:1;                 /* Gated Counter Mode enable. */
      vuint32_t SPEM:1;                /* SPE mode enable for channel. */
      vuint32_t  :1;
      vuint32_t OSM:1;                 /* One-shot mode.. */
      vuint32_t  :1;
      vuint32_t TRIGOUT:1;             /* Trigger output selection (output signal TRIG_[n]) of module TOM_CH[n]. */
      vuint32_t  :3;
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :5;
      vuint32_t CLK_SRC_SR:3;          /* Clock source select for channel. */
      vuint32_t SL:1;                  /* Signal level for duty cycle. */
      vuint32_t  :11;
    } B;
  } CH2_CTRL;

  union {                              /* TOM Channel n Shadow 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR0:16;                /* TOM channel n shadow register SR0 for update of compare register CM0. */
    } B;
  } CH2_SR0;

  union {                              /* TOM Channel n Shadow 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR1:16;                /* TOM channel n shadow register SR1 for update of compare register CM1. */
    } B;
  } CH2_SR1;

  union {                              /* TOM Channel n Compare 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM0:16;                /* TOM CCU0 compare register. */
    } B;
  } CH2_CM0;

  union {                              /* TOM Channel n Compare 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM1:16;                /* TOM CCU1 compare register. */
    } B;
  } CH2_CM1;

  union {                              /* TOM Channel n CN0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CN0:16;                /* TOM CCU0 counter register. */
    } B;
  } CH2_CN0;

  union {                              /* TOM Channel n Status Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :31;                  /* Reserved. */
      vuint32_t OL:1;                  /* Output level of output TOM_OUT(n). */
    } B;
  } CH2_STAT;

  union {                              /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH2_IRQ_NOTIFY;

  union {                              /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH2_IRQ_EN;

  union {                              /* TOM Channel n Force Interrupt Request Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t TRG_CCU1TC0:1;         /* Trigger TOM_CCU1TC0_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC0:1;         /* Trigger TOM_CCU0TC0_IRQ interrupt by software. */
    } B;
  } CH2_IRQ_FORCINT;

  union {                              /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH2_IRQ_MODE;

  uint8_t TOM_reserved2[20];
  union {                              /* TOM Channel n Control Register, n[0:14] */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t GCM:1;                 /* Gated Counter Mode enable. */
      vuint32_t SPEM:1;                /* SPE mode enable for channel. */
      vuint32_t  :1;
      vuint32_t OSM:1;                 /* One-shot mode.. */
      vuint32_t  :1;
      vuint32_t TRIGOUT:1;             /* Trigger output selection (output signal TRIG_[n]) of module TOM_CH[n]. */
      vuint32_t  :3;
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :5;
      vuint32_t CLK_SRC_SR:3;          /* Clock source select for channel. */
      vuint32_t SL:1;                  /* Signal level for duty cycle. */
      vuint32_t  :11;
    } B;
  } CH3_CTRL;

  union {                              /* TOM Channel n Shadow 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR0:16;                /* TOM channel n shadow register SR0 for update of compare register CM0. */
    } B;
  } CH3_SR0;

  union {                              /* TOM Channel n Shadow 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR1:16;                /* TOM channel n shadow register SR1 for update of compare register CM1. */
    } B;
  } CH3_SR1;

  union {                              /* TOM Channel n Compare 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM0:16;                /* TOM CCU0 compare register. */
    } B;
  } CH3_CM0;

  union {                              /* TOM Channel n Compare 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM1:16;                /* TOM CCU1 compare register. */
    } B;
  } CH3_CM1;

  union {                              /* TOM Channel n CN0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CN0:16;                /* TOM CCU0 counter register. */
    } B;
  } CH3_CN0;

  union {                              /* TOM Channel n Status Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :31;                  /* Reserved. */
      vuint32_t OL:1;                  /* Output level of output TOM_OUT(n). */
    } B;
  } CH3_STAT;

  union {                              /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH3_IRQ_NOTIFY;

  union {                              /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH3_IRQ_EN;

  union {                              /* TOM Channel n Force Interrupt Request Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t TRG_CCU1TC0:1;         /* Trigger TOM_CCU1TC0_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC0:1;         /* Trigger TOM_CCU0TC0_IRQ interrupt by software. */
    } B;
  } CH3_IRQ_FORCINT;

  union {                              /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH3_IRQ_MODE;

  uint8_t TOM_reserved3[20];
  union {                              /* TOM Channel n Control Register, n[0:14] */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t GCM:1;                 /* Gated Counter Mode enable. */
      vuint32_t SPEM:1;                /* SPE mode enable for channel. */
      vuint32_t  :1;
      vuint32_t OSM:1;                 /* One-shot mode.. */
      vuint32_t  :1;
      vuint32_t TRIGOUT:1;             /* Trigger output selection (output signal TRIG_[n]) of module TOM_CH[n]. */
      vuint32_t  :3;
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :5;
      vuint32_t CLK_SRC_SR:3;          /* Clock source select for channel. */
      vuint32_t SL:1;                  /* Signal level for duty cycle. */
      vuint32_t  :11;
    } B;
  } CH4_CTRL;

  union {                              /* TOM Channel n Shadow 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR0:16;                /* TOM channel n shadow register SR0 for update of compare register CM0. */
    } B;
  } CH4_SR0;

  union {                              /* TOM Channel n Shadow 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR1:16;                /* TOM channel n shadow register SR1 for update of compare register CM1. */
    } B;
  } CH4_SR1;

  union {                              /* TOM Channel n Compare 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM0:16;                /* TOM CCU0 compare register. */
    } B;
  } CH4_CM0;

  union {                              /* TOM Channel n Compare 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM1:16;                /* TOM CCU1 compare register. */
    } B;
  } CH4_CM1;

  union {                              /* TOM Channel n CN0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CN0:16;                /* TOM CCU0 counter register. */
    } B;
  } CH4_CN0;

  union {                              /* TOM Channel n Status Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :31;                  /* Reserved. */
      vuint32_t OL:1;                  /* Output level of output TOM_OUT(n). */
    } B;
  } CH4_STAT;

  union {                              /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH4_IRQ_NOTIFY;

  union {                              /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH4_IRQ_EN;

  union {                              /* TOM Channel n Force Interrupt Request Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t TRG_CCU1TC0:1;         /* Trigger TOM_CCU1TC0_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC0:1;         /* Trigger TOM_CCU0TC0_IRQ interrupt by software. */
    } B;
  } CH4_IRQ_FORCINT;

  union {                              /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH4_IRQ_MODE;

  uint8_t TOM_reserved4[20];
  union {                              /* TOM Channel n Control Register, n[0:14] */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t GCM:1;                 /* Gated Counter Mode enable. */
      vuint32_t SPEM:1;                /* SPE mode enable for channel. */
      vuint32_t  :1;
      vuint32_t OSM:1;                 /* One-shot mode.. */
      vuint32_t  :1;
      vuint32_t TRIGOUT:1;             /* Trigger output selection (output signal TRIG_[n]) of module TOM_CH[n]. */
      vuint32_t  :3;
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :5;
      vuint32_t CLK_SRC_SR:3;          /* Clock source select for channel. */
      vuint32_t SL:1;                  /* Signal level for duty cycle. */
      vuint32_t  :11;
    } B;
  } CH5_CTRL;

  union {                              /* TOM Channel n Shadow 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR0:16;                /* TOM channel n shadow register SR0 for update of compare register CM0. */
    } B;
  } CH5_SR0;

  union {                              /* TOM Channel n Shadow 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR1:16;                /* TOM channel n shadow register SR1 for update of compare register CM1. */
    } B;
  } CH5_SR1;

  union {                              /* TOM Channel n Compare 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM0:16;                /* TOM CCU0 compare register. */
    } B;
  } CH5_CM0;

  union {                              /* TOM Channel n Compare 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM1:16;                /* TOM CCU1 compare register. */
    } B;
  } CH5_CM1;

  union {                              /* TOM Channel n CN0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CN0:16;                /* TOM CCU0 counter register. */
    } B;
  } CH5_CN0;

  union {                              /* TOM Channel n Status Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :31;                  /* Reserved. */
      vuint32_t OL:1;                  /* Output level of output TOM_OUT(n). */
    } B;
  } CH5_STAT;

  union {                              /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH5_IRQ_NOTIFY;

  union {                              /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH5_IRQ_EN;

  union {                              /* TOM Channel n Force Interrupt Request Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t TRG_CCU1TC0:1;         /* Trigger TOM_CCU1TC0_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC0:1;         /* Trigger TOM_CCU0TC0_IRQ interrupt by software. */
    } B;
  } CH5_IRQ_FORCINT;

  union {                              /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH5_IRQ_MODE;

  uint8_t TOM_reserved5[20];
  union {                              /* TOM Channel n Control Register, n[0:14] */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t GCM:1;                 /* Gated Counter Mode enable. */
      vuint32_t SPEM:1;                /* SPE mode enable for channel. */
      vuint32_t  :1;
      vuint32_t OSM:1;                 /* One-shot mode.. */
      vuint32_t  :1;
      vuint32_t TRIGOUT:1;             /* Trigger output selection (output signal TRIG_[n]) of module TOM_CH[n]. */
      vuint32_t  :3;
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :5;
      vuint32_t CLK_SRC_SR:3;          /* Clock source select for channel. */
      vuint32_t SL:1;                  /* Signal level for duty cycle. */
      vuint32_t  :11;
    } B;
  } CH6_CTRL;

  union {                              /* TOM Channel n Shadow 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR0:16;                /* TOM channel n shadow register SR0 for update of compare register CM0. */
    } B;
  } CH6_SR0;

  union {                              /* TOM Channel n Shadow 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR1:16;                /* TOM channel n shadow register SR1 for update of compare register CM1. */
    } B;
  } CH6_SR1;

  union {                              /* TOM Channel n Compare 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM0:16;                /* TOM CCU0 compare register. */
    } B;
  } CH6_CM0;

  union {                              /* TOM Channel n Compare 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM1:16;                /* TOM CCU1 compare register. */
    } B;
  } CH6_CM1;

  union {                              /* TOM Channel n CN0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CN0:16;                /* TOM CCU0 counter register. */
    } B;
  } CH6_CN0;

  union {                              /* TOM Channel n Status Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :31;                  /* Reserved. */
      vuint32_t OL:1;                  /* Output level of output TOM_OUT(n). */
    } B;
  } CH6_STAT;

  union {                              /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH6_IRQ_NOTIFY;

  union {                              /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH6_IRQ_EN;

  union {                              /* TOM Channel n Force Interrupt Request Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t TRG_CCU1TC0:1;         /* Trigger TOM_CCU1TC0_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC0:1;         /* Trigger TOM_CCU0TC0_IRQ interrupt by software. */
    } B;
  } CH6_IRQ_FORCINT;

  union {                              /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH6_IRQ_MODE;

  uint8_t TOM_reserved6[20];
  union {                              /* TOM Channel n Control Register, n[0:14] */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t GCM:1;                 /* Gated Counter Mode enable. */
      vuint32_t SPEM:1;                /* SPE mode enable for channel. */
      vuint32_t  :1;
      vuint32_t OSM:1;                 /* One-shot mode.. */
      vuint32_t  :1;
      vuint32_t TRIGOUT:1;             /* Trigger output selection (output signal TRIG_[n]) of module TOM_CH[n]. */
      vuint32_t  :3;
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :5;
      vuint32_t CLK_SRC_SR:3;          /* Clock source select for channel. */
      vuint32_t SL:1;                  /* Signal level for duty cycle. */
      vuint32_t  :11;
    } B;
  } CH7_CTRL;

  union {                              /* TOM Channel n Shadow 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR0:16;                /* TOM channel n shadow register SR0 for update of compare register CM0. */
    } B;
  } CH7_SR0;

  union {                              /* TOM Channel n Shadow 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR1:16;                /* TOM channel n shadow register SR1 for update of compare register CM1. */
    } B;
  } CH7_SR1;

  union {                              /* TOM Channel n Compare 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM0:16;                /* TOM CCU0 compare register. */
    } B;
  } CH7_CM0;

  union {                              /* TOM Channel n Compare 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM1:16;                /* TOM CCU1 compare register. */
    } B;
  } CH7_CM1;

  union {                              /* TOM Channel n CN0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CN0:16;                /* TOM CCU0 counter register. */
    } B;
  } CH7_CN0;

  union {                              /* TOM Channel n Status Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :31;                  /* Reserved. */
      vuint32_t OL:1;                  /* Output level of output TOM_OUT(n). */
    } B;
  } CH7_STAT;

  union {                              /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH7_IRQ_NOTIFY;

  union {                              /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH7_IRQ_EN;

  union {                              /* TOM Channel n Force Interrupt Request Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t TRG_CCU1TC0:1;         /* Trigger TOM_CCU1TC0_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC0:1;         /* Trigger TOM_CCU0TC0_IRQ interrupt by software. */
    } B;
  } CH7_IRQ_FORCINT;

  union {                              /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH7_IRQ_MODE;

  uint8_t TOM_reserved7[20];
  union {                              /* TOM Channel n Control Register, n[0:14] */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t GCM:1;                 /* Gated Counter Mode enable. */
      vuint32_t SPEM:1;                /* SPE mode enable for channel. */
      vuint32_t  :1;
      vuint32_t OSM:1;                 /* One-shot mode.. */
      vuint32_t  :1;
      vuint32_t TRIGOUT:1;             /* Trigger output selection (output signal TRIG_[n]) of module TOM_CH[n]. */
      vuint32_t  :3;
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :5;
      vuint32_t CLK_SRC_SR:3;          /* Clock source select for channel. */
      vuint32_t SL:1;                  /* Signal level for duty cycle. */
      vuint32_t  :11;
    } B;
  } CH8_CTRL;

  union {                              /* TOM Channel n Shadow 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR0:16;                /* TOM channel n shadow register SR0 for update of compare register CM0. */
    } B;
  } CH8_SR0;

  union {                              /* TOM Channel n Shadow 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR1:16;                /* TOM channel n shadow register SR1 for update of compare register CM1. */
    } B;
  } CH8_SR1;

  union {                              /* TOM Channel n Compare 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM0:16;                /* TOM CCU0 compare register. */
    } B;
  } CH8_CM0;

  union {                              /* TOM Channel n Compare 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM1:16;                /* TOM CCU1 compare register. */
    } B;
  } CH8_CM1;

  union {                              /* TOM Channel n CN0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CN0:16;                /* TOM CCU0 counter register. */
    } B;
  } CH8_CN0;

  union {                              /* TOM Channel n Status Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :31;                  /* Reserved. */
      vuint32_t OL:1;                  /* Output level of output TOM_OUT(n). */
    } B;
  } CH8_STAT;

  union {                              /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH8_IRQ_NOTIFY;

  union {                              /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH8_IRQ_EN;

  union {                              /* TOM Channel n Force Interrupt Request Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t TRG_CCU1TC0:1;         /* Trigger TOM_CCU1TC0_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC0:1;         /* Trigger TOM_CCU0TC0_IRQ interrupt by software. */
    } B;
  } CH8_IRQ_FORCINT;

  union {                              /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH8_IRQ_MODE;

  uint8_t TOM_reserved8[4];
  union {                              /* TOM TGC1 Global Control Register */
    vuint32_t R;
    struct {
      vuint32_t UPEN_CTRL15:2;         /* TOM channel 15 enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL14:2;         /* TOM channel 14 enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL13:2;         /* TOM channel 13 enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL12:2;         /* TOM channel 12 enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL11:2;         /* TOM channel 11 enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL10:2;         /* TOM channel 10 enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL9:2;          /* TOM channel 9 enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t UPEN_CTRL8:2;          /* TOM channel 8 enable update of register CM0, CM1 and CLK_SRC_STAT from SR0, SR1 and CLK_SRC. */
      vuint32_t RST_CH15:1;            /* Software reset of channel 15. */
      vuint32_t RST_CH14:1;            /* Software reset of channel 14. */
      vuint32_t RST_CH13:1;            /* Software reset of channel 13. */
      vuint32_t RST_CH12:1;            /* Software reset of channel 12. */
      vuint32_t RST_CH11:1;            /* Software reset of channel 11. */
      vuint32_t RST_CH10:1;            /* Software reset of channel 10. */
      vuint32_t RST_CH9:1;             /* Software reset of channel 9. */
      vuint32_t RST_CH8:1;             /* Software reset of channel 8. */
      vuint32_t  :7;
      vuint32_t HOST_TRIG:1;           /* Trigger request signal (see TGC0, TGC1) to update the register ENDIS_STAT and OUTEN_STAT. */
    } B;
  } TGC1_GLB_CTRL;

  union {                              /* TOM TGC1 Action Time Base Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t TBU_SEL:2;             /* Selection of time base used for comparison. */
      vuint32_t TB_TRIG:1;             /* Set trigger request. */
      vuint32_t ACT_TB:24;             /* Specifies the signed compare value with selected signal TBU_TS[n], x=0..2. */
    } B;
  } TGC1_ACT_TB;

  union {                              /* TOM TGC1 Force Update Control Register */
    vuint32_t R;
    struct {
      vuint32_t RSTCN0_CH15:2;         /* Reset CN0 of channel 15 on force update event. */
      vuint32_t RSTCN0_CH14:2;         /* Reset CN0 of channel 14 on force update event. */
      vuint32_t RSTCN0_CH13:2;         /* Reset CN0 of channel 13 on force update event. */
      vuint32_t RSTCN0_CH12:2;         /* Reset CN0 of channel 12 on force update event. */
      vuint32_t RSTCN0_CH11:2;         /* Reset CN0 of channel 11 on force update event. */
      vuint32_t RSTCN0_CH10:2;         /* Reset CN0 of channel 10 on force update event. */
      vuint32_t RSTCN0_CH9:2;          /* Reset CN0 of channel 9 on force update event. */
      vuint32_t RSTCN0_CH8:2;          /* Reset CN0 of channel 8 on force update event. */
      vuint32_t FUPD_CTRL15:2;         /* Force update of TOM channel 15 operation registers. */
      vuint32_t FUPD_CTRL14:2;         /* Force update of TOM channel 14 operation registers, */
      vuint32_t FUPD_CTRL13:2;         /* Force update of TOM channel 13 operation registers. */
      vuint32_t FUPD_CTRL12:2;         /* Force update of TOM channel 12 operation registers. */
      vuint32_t FUPD_CTRL11:2;         /* Force update of TOM channel 11 operation registers. */
      vuint32_t FUPD_CTRL10:2;         /* ce update of TOM channel 10 operation registers. */
      vuint32_t FUPD_CTRL9:2;          /* Force update of TOM channel 9 operation registers. */
      vuint32_t FUPD_CTRL8:2;          /* Force update of TOM channel 8 operation registers. */
    } B;
  } TGC1_FUPD_CTRL;

  union {                              /* TOM TGC1 Interrupt Trigger Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t INT_TRIG15:2;          /* Select input signal TRIG_15 as a trigger source. */
      vuint32_t INT_TRIG14:2;          /* Select input signal TRIG_14 as a trigger source. */
      vuint32_t INT_TRIG13:2;          /* Select input signal TRIG_13as a trigger source. */
      vuint32_t INT_TRIG12:2;          /* Select input signal TRIG_12 as a trigger source. */
      vuint32_t INT_TRIG11:2;          /* Select input signal TRIG_1 as a trigger source. */
      vuint32_t INT_TRIG10:2;          /* Select input signal TRIG_10 as a trigger source. */
      vuint32_t INT_TRIG9:2;           /* Select input signal TRIG_9 as a trigger source. */
      vuint32_t INT_TRIG8:2;           /* Select input signal TRIG_8 as a trigger source. */
    } B;
  } TGC1_INT_TRIG;

  union {                              /* TOM Channel n Control Register, n[0:14] */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t GCM:1;                 /* Gated Counter Mode enable. */
      vuint32_t SPEM:1;                /* SPE mode enable for channel. */
      vuint32_t  :1;
      vuint32_t OSM:1;                 /* One-shot mode.. */
      vuint32_t  :1;
      vuint32_t TRIGOUT:1;             /* Trigger output selection (output signal TRIG_[n]) of module TOM_CH[n]. */
      vuint32_t  :3;
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :5;
      vuint32_t CLK_SRC_SR:3;          /* Clock source select for channel. */
      vuint32_t SL:1;                  /* Signal level for duty cycle. */
      vuint32_t  :11;
    } B;
  } CH9_CTRL;

  union {                              /* TOM Channel n Shadow 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR0:16;                /* TOM channel n shadow register SR0 for update of compare register CM0. */
    } B;
  } CH9_SR0;

  union {                              /* TOM Channel n Shadow 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR1:16;                /* TOM channel n shadow register SR1 for update of compare register CM1. */
    } B;
  } CH9_SR1;

  union {                              /* TOM Channel n Compare 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM0:16;                /* TOM CCU0 compare register. */
    } B;
  } CH9_CM0;

  union {                              /* TOM Channel n Compare 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM1:16;                /* TOM CCU1 compare register. */
    } B;
  } CH9_CM1;

  union {                              /* TOM Channel n CN0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CN0:16;                /* TOM CCU0 counter register. */
    } B;
  } CH9_CN0;

  union {                              /* TOM Channel n Status Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :31;                  /* Reserved. */
      vuint32_t OL:1;                  /* Output level of output TOM_OUT(n). */
    } B;
  } CH9_STAT;

  union {                              /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH9_IRQ_NOTIFY;

  union {                              /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH9_IRQ_EN;

  union {                              /* TOM Channel n Force Interrupt Request Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t TRG_CCU1TC0:1;         /* Trigger TOM_CCU1TC0_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC0:1;         /* Trigger TOM_CCU0TC0_IRQ interrupt by software. */
    } B;
  } CH9_IRQ_FORCINT;

  union {                              /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH9_IRQ_MODE;

  uint8_t TOM_reserved9[4];
  union {                              /* TOM TGC1 Enable/Disable Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t ENDIS_CTRL15:2;        /* Channel 15 enable/disable update value. */
      vuint32_t ENDIS_CTRL14:2;        /* Channel 14 enable/disable update value. */
      vuint32_t ENDIS_CTRL13:2;        /* Channel 13 enable/disable update value. */
      vuint32_t ENDIS_CTRL12:2;        /* TOM channel 12 enable/disable update value. */
      vuint32_t ENDIS_CTRL11:2;        /* TOM channel 11 enable/disable update value. */
      vuint32_t ENDIS_CTRL10:2;        /* TOM channel 10 enable/disable update value. */
      vuint32_t ENDIS_CTRL9:2;         /* TOM channel 9 enable/disable update value. */
      vuint32_t ENDIS_CTRL8:2;         /* TOM channel 8 enable/disable update value. */
    } B;
  } TGC1_ENDIS_CTRL;

  union {                              /* TOM TGC1 Enable/Disable Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t ENDIS_STAT15:2;        /* TOM channel 15 enable/disable. */
      vuint32_t ENDIS_STAT14:2;        /* TOM channel 14 enable/disable. */
      vuint32_t ENDIS_STAT13:2;        /* TOM channel 13 enable/disable. */
      vuint32_t ENDIS_STAT12:2;        /* TOM channel 12 enable/disable. */
      vuint32_t ENDIS_STAT11:2;        /* TOM channel 11 enable/disable. */
      vuint32_t ENDIS_STAT10:2;        /* TOM channel 10 enable/disable. */
      vuint32_t ENDIS_STAT9:2;         /* TOM channel 9 enable/disable. */
      vuint32_t ENDIS_STAT8:2;         /* TOM channel 8 enable/disable. */
    } B;
  } TGC1_ENDIS_STAT;

  union {                              /* TOM TGC1 Out Enable Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t OUTEN_CTRL15:2;        /* Output TOM_OUT(15) enable/disable update value. */
      vuint32_t OUTEN_CTRL14:2;        /* Output TOM_OUT(14) enable/disable update value. */
      vuint32_t OUTEN_CTRL13:2;        /* Output TOM_OUT(13) enable/disable update value. */
      vuint32_t OUTEN_CTRL12:2;        /* Output TOM_OUT(12) enable/disable update value. */
      vuint32_t OUTEN_CTRL11:2;        /* Output TOM_OUT(11) enable/disable update value. */
      vuint32_t OUTEN_CTRL10:2;        /* Output TOM_OUT(10) enable/disable update value. */
      vuint32_t OUTEN_CTRL9:2;         /* Output TOM_OUT(9) enable/disable update value. */
      vuint32_t OUTEN_CTRL8:2;         /* Output TOM_OUT(8) enable/disable update value. */
    } B;
  } TGC1_OUTEN_CTRL;

  union {                              /* TOM TGC1 Out Enable Control/Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t OUTEN_STAT15:2;        /* Control/status of output TOM_OUT(15). */
      vuint32_t OUTEN_STAT14:2;        /* Control/status of output TOM_OUT(14). */
      vuint32_t OUTEN_STAT13:2;        /* Control/status of output TOM_OUT(13). */
      vuint32_t OUTEN_STAT12:2;        /* Control/status of output TOM_OUT(12) */
      vuint32_t OUTEN_STAT11:2;        /* Control/status of output TOM_OUT(11). */
      vuint32_t OUTEN_STAT10:2;        /* Control/status of output TOM_OUT(10). */
      vuint32_t OUTEN_STAT9:2;         /* Control/status of output TOM_OUT(9). */
      vuint32_t OUTEN_STAT8:2;         /* Control/status of output TOM_OUT(8). */
    } B;
  } TGC1_OUTEN_STAT;

  union {                              /* TOM Channel n Control Register, n[0:14] */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t GCM:1;                 /* Gated Counter Mode enable. */
      vuint32_t SPEM:1;                /* SPE mode enable for channel. */
      vuint32_t  :1;
      vuint32_t OSM:1;                 /* One-shot mode.. */
      vuint32_t  :1;
      vuint32_t TRIGOUT:1;             /* Trigger output selection (output signal TRIG_[n]) of module TOM_CH[n]. */
      vuint32_t  :3;
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :5;
      vuint32_t CLK_SRC_SR:3;          /* Clock source select for channel. */
      vuint32_t SL:1;                  /* Signal level for duty cycle. */
      vuint32_t  :11;
    } B;
  } CH10_CTRL;

  union {                              /* TOM Channel n Shadow 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR0:16;                /* TOM channel n shadow register SR0 for update of compare register CM0. */
    } B;
  } CH10_SR0;

  union {                              /* TOM Channel n Shadow 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR1:16;                /* TOM channel n shadow register SR1 for update of compare register CM1. */
    } B;
  } CH10_SR1;

  union {                              /* TOM Channel n Compare 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM0:16;                /* TOM CCU0 compare register. */
    } B;
  } CH10_CM0;

  union {                              /* TOM Channel n Compare 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM1:16;                /* TOM CCU1 compare register. */
    } B;
  } CH10_CM1;

  union {                              /* TOM Channel n CN0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CN0:16;                /* TOM CCU0 counter register. */
    } B;
  } CH10_CN0;

  union {                              /* TOM Channel n Status Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :31;                  /* Reserved. */
      vuint32_t OL:1;                  /* Output level of output TOM_OUT(n). */
    } B;
  } CH10_STAT;

  union {                              /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH10_IRQ_NOTIFY;

  union {                              /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH10_IRQ_EN;

  union {                              /* TOM Channel n Force Interrupt Request Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t TRG_CCU1TC0:1;         /* Trigger TOM_CCU1TC0_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC0:1;         /* Trigger TOM_CCU0TC0_IRQ interrupt by software. */
    } B;
  } CH10_IRQ_FORCINT;

  union {                              /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH10_IRQ_MODE;

  uint8_t TOM_reserved10[20];
  union {                              /* TOM Channel n Control Register, n[0:14] */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t GCM:1;                 /* Gated Counter Mode enable. */
      vuint32_t SPEM:1;                /* SPE mode enable for channel. */
      vuint32_t  :1;
      vuint32_t OSM:1;                 /* One-shot mode.. */
      vuint32_t  :1;
      vuint32_t TRIGOUT:1;             /* Trigger output selection (output signal TRIG_[n]) of module TOM_CH[n]. */
      vuint32_t  :3;
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :5;
      vuint32_t CLK_SRC_SR:3;          /* Clock source select for channel. */
      vuint32_t SL:1;                  /* Signal level for duty cycle. */
      vuint32_t  :11;
    } B;
  } CH11_CTRL;

  union {                              /* TOM Channel n Shadow 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR0:16;                /* TOM channel n shadow register SR0 for update of compare register CM0. */
    } B;
  } CH11_SR0;

  union {                              /* TOM Channel n Shadow 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR1:16;                /* TOM channel n shadow register SR1 for update of compare register CM1. */
    } B;
  } CH11_SR1;

  union {                              /* TOM Channel n Compare 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM0:16;                /* TOM CCU0 compare register. */
    } B;
  } CH11_CM0;

  union {                              /* TOM Channel n Compare 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM1:16;                /* TOM CCU1 compare register. */
    } B;
  } CH11_CM1;

  union {                              /* TOM Channel n CN0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CN0:16;                /* TOM CCU0 counter register. */
    } B;
  } CH11_CN0;

  union {                              /* TOM Channel n Status Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :31;                  /* Reserved. */
      vuint32_t OL:1;                  /* Output level of output TOM_OUT(n). */
    } B;
  } CH11_STAT;

  union {                              /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH11_IRQ_NOTIFY;

  union {                              /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH11_IRQ_EN;

  union {                              /* TOM Channel n Force Interrupt Request Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t TRG_CCU1TC0:1;         /* Trigger TOM_CCU1TC0_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC0:1;         /* Trigger TOM_CCU0TC0_IRQ interrupt by software. */
    } B;
  } CH11_IRQ_FORCINT;

  union {                              /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH11_IRQ_MODE;

  uint8_t TOM_reserved11[20];
  union {                              /* TOM Channel n Control Register, n[0:14] */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t GCM:1;                 /* Gated Counter Mode enable. */
      vuint32_t SPEM:1;                /* SPE mode enable for channel. */
      vuint32_t  :1;
      vuint32_t OSM:1;                 /* One-shot mode.. */
      vuint32_t  :1;
      vuint32_t TRIGOUT:1;             /* Trigger output selection (output signal TRIG_[n]) of module TOM_CH[n]. */
      vuint32_t  :3;
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :5;
      vuint32_t CLK_SRC_SR:3;          /* Clock source select for channel. */
      vuint32_t SL:1;                  /* Signal level for duty cycle. */
      vuint32_t  :11;
    } B;
  } CH12_CTRL;

  union {                              /* TOM Channel n Shadow 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR0:16;                /* TOM channel n shadow register SR0 for update of compare register CM0. */
    } B;
  } CH12_SR0;

  union {                              /* TOM Channel n Shadow 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR1:16;                /* TOM channel n shadow register SR1 for update of compare register CM1. */
    } B;
  } CH12_SR1;

  union {                              /* TOM Channel n Compare 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM0:16;                /* TOM CCU0 compare register. */
    } B;
  } CH12_CM0;

  union {                              /* TOM Channel n Compare 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM1:16;                /* TOM CCU1 compare register. */
    } B;
  } CH12_CM1;

  union {                              /* TOM Channel n CN0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CN0:16;                /* TOM CCU0 counter register. */
    } B;
  } CH12_CN0;

  union {                              /* TOM Channel n Status Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :31;                  /* Reserved. */
      vuint32_t OL:1;                  /* Output level of output TOM_OUT(n). */
    } B;
  } CH12_STAT;

  union {                              /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH12_IRQ_NOTIFY;

  union {                              /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH12_IRQ_EN;

  union {                              /* TOM Channel n Force Interrupt Request Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t TRG_CCU1TC0:1;         /* Trigger TOM_CCU1TC0_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC0:1;         /* Trigger TOM_CCU0TC0_IRQ interrupt by software. */
    } B;
  } CH12_IRQ_FORCINT;

  union {                              /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH12_IRQ_MODE;

  uint8_t TOM_reserved12[20];
  union {                              /* TOM Channel n Control Register, n[0:14] */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t GCM:1;                 /* Gated Counter Mode enable. */
      vuint32_t SPEM:1;                /* SPE mode enable for channel. */
      vuint32_t  :1;
      vuint32_t OSM:1;                 /* One-shot mode.. */
      vuint32_t  :1;
      vuint32_t TRIGOUT:1;             /* Trigger output selection (output signal TRIG_[n]) of module TOM_CH[n]. */
      vuint32_t  :3;
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :5;
      vuint32_t CLK_SRC_SR:3;          /* Clock source select for channel. */
      vuint32_t SL:1;                  /* Signal level for duty cycle. */
      vuint32_t  :11;
    } B;
  } CH13_CTRL;

  union {                              /* TOM Channel n Shadow 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR0:16;                /* TOM channel n shadow register SR0 for update of compare register CM0. */
    } B;
  } CH13_SR0;

  union {                              /* TOM Channel n Shadow 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR1:16;                /* TOM channel n shadow register SR1 for update of compare register CM1. */
    } B;
  } CH13_SR1;

  union {                              /* TOM Channel n Compare 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM0:16;                /* TOM CCU0 compare register. */
    } B;
  } CH13_CM0;

  union {                              /* TOM Channel n Compare 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM1:16;                /* TOM CCU1 compare register. */
    } B;
  } CH13_CM1;

  union {                              /* TOM Channel n CN0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CN0:16;                /* TOM CCU0 counter register. */
    } B;
  } CH13_CN0;

  union {                              /* TOM Channel n Status Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :31;                  /* Reserved. */
      vuint32_t OL:1;                  /* Output level of output TOM_OUT(n). */
    } B;
  } CH13_STAT;

  union {                              /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH13_IRQ_NOTIFY;

  union {                              /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH13_IRQ_EN;

  union {                              /* TOM Channel n Force Interrupt Request Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t TRG_CCU1TC0:1;         /* Trigger TOM_CCU1TC0_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC0:1;         /* Trigger TOM_CCU0TC0_IRQ interrupt by software. */
    } B;
  } CH13_IRQ_FORCINT;

  union {                              /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH13_IRQ_MODE;

  uint8_t TOM_reserved13[20];
  union {                              /* TOM Channel n Control Register, n[0:14] */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t GCM:1;                 /* Gated Counter Mode enable. */
      vuint32_t SPEM:1;                /* SPE mode enable for channel. */
      vuint32_t  :1;
      vuint32_t OSM:1;                 /* One-shot mode.. */
      vuint32_t  :1;
      vuint32_t TRIGOUT:1;             /* Trigger output selection (output signal TRIG_[n]) of module TOM_CH[n]. */
      vuint32_t  :3;
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :5;
      vuint32_t CLK_SRC_SR:3;          /* Clock source select for channel. */
      vuint32_t SL:1;                  /* Signal level for duty cycle. */
      vuint32_t  :11;
    } B;
  } CH14_CTRL;

  union {                              /* TOM Channel n Shadow 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR0:16;                /* TOM channel n shadow register SR0 for update of compare register CM0. */
    } B;
  } CH14_SR0;

  union {                              /* TOM Channel n Shadow 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR1:16;                /* TOM channel n shadow register SR1 for update of compare register CM1. */
    } B;
  } CH14_SR1;

  union {                              /* TOM Channel n Compare 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM0:16;                /* TOM CCU0 compare register. */
    } B;
  } CH14_CM0;

  union {                              /* TOM Channel n Compare 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM1:16;                /* TOM CCU1 compare register. */
    } B;
  } CH14_CM1;

  union {                              /* TOM Channel n CN0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CN0:16;                /* TOM CCU0 counter register. */
    } B;
  } CH14_CN0;

  union {                              /* TOM Channel n Status Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :31;                  /* Reserved. */
      vuint32_t OL:1;                  /* Output level of output TOM_OUT(n). */
    } B;
  } CH14_STAT;

  union {                              /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH14_IRQ_NOTIFY;

  union {                              /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH14_IRQ_EN;

  union {                              /* TOM Channel n Force Interrupt Request Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t TRG_CCU1TC0:1;         /* Trigger TOM_CCU1TC0_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC0:1;         /* Trigger TOM_CCU0TC0_IRQ interrupt by software. */
    } B;
  } CH14_IRQ_FORCINT;

  union {                              /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH14_IRQ_MODE;

  uint8_t TOM_reserved14[20];
  union {                              /* TOM Channel 15 Control register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t BITREV:1;              /* Bit-reversing of output of counter register CN0.. */
      vuint32_t OSM:1;                 /* One-shot mode. */
      vuint32_t  :1;
      vuint32_t TRIGOUT:1;             /* Trigger output selection (output signal TRIG_15) of module TOM_CH15. */
      vuint32_t  :3;
      vuint32_t RST_CCU0:1;            /* Reset source of CCU0. */
      vuint32_t  :5;
      vuint32_t CLK_SRC_SR:3;          /* Clock source select for channel. */
      vuint32_t SL:1;                  /* Signal level for duty cycle. */
      vuint32_t  :11;
    } B;
  } CH15_CTRL;

  union {                              /* TOM Channel n Shadow 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR0:16;                /* TOM channel n shadow register SR0 for update of compare register CM0. */
    } B;
  } CH15_SR0;

  union {                              /* TOM Channel n Shadow 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SR1:16;                /* TOM channel n shadow register SR1 for update of compare register CM1. */
    } B;
  } CH15_SR1;

  union {                              /* TOM Channel n Compare 0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM0:16;                /* TOM CCU0 compare register. */
    } B;
  } CH15_CM0;

  union {                              /* TOM Channel n Compare 1 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CM1:16;                /* TOM CCU1 compare register. */
    } B;
  } CH15_CM1;

  union {                              /* TOM Channel n CN0 Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CN0:16;                /* TOM CCU0 counter register. */
    } B;
  } CH15_CN0;

  union {                              /* TOM Channel n Status Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :31;                  /* Reserved. */
      vuint32_t OL:1;                  /* Output level of output TOM_OUT(n). */
    } B;
  } CH15_STAT;

  union {                              /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC:1;              /* CCU1 Trigger condition interrupt for channel n. */
      vuint32_t CCU0TC:1;              /* CCU0 Trigger condition interrupt for channel n. */
    } B;
  } CH15_IRQ_NOTIFY;

  union {                              /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t CCU1TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
      vuint32_t CCU0TC_IRQ_EN:1;       /* TOM_CCU0TC_IRQ interrupt enable. */
    } B;
  } CH15_IRQ_EN;

  union {                              /* TOM Channel n Force Interrupt Request Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;                  /* Reserved. */
      vuint32_t TRG_CCU1TC0:1;         /* Trigger TOM_CCU1TC0_IRQ interrupt by software. */
      vuint32_t TRG_CCU0TC0:1;         /* Trigger TOM_CCU0TC0_IRQ interrupt by software. */
    } B;
  } CH15_IRQ_FORCINT;

  union {                              /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t IRQ_MODE:2;            /* IRQ mode selection. */
    } B;
  } CH15_IRQ_MODE;
};


/* ============================================================================
   =============================== Module: I2C ================================
   ============================================================================ */

struct I2C_tag {
  union {                              /* I2C Bus Address Register */
    vuint8_t R;
    struct {
      vuint8_t ADR:7;
      vuint8_t  :1;
    } B;
  } IBAD;

  union {                              /* I2C Bus Frequency Divider Register */
    vuint8_t R;
    struct {
      vuint8_t IBC:8;
    } B;
  } IBFD;

  union {                              /* I2C Bus Control Register */
    vuint8_t R;
    struct {
      vuint8_t MDIS:1;
      vuint8_t IBIE:1;
      vuint8_t MSSL:1;
      vuint8_t TXRX:1;
      vuint8_t NOACK:1;
      vuint8_t RSTA:1;
      vuint8_t DMAEN:1;
      vuint8_t  :1;
    } B;
  } IBCR;

  union {                              /* I2C Bus Status Register */
    vuint8_t R;
    struct {
      vuint8_t TCF:1;
      vuint8_t IAAS:1;
      vuint8_t IBB:1;
      vuint8_t IBAL:1;
      vuint8_t  :1;
      vuint8_t SRW:1;
      vuint8_t IBIF:1;
      vuint8_t RXAK:1;
    } B;
  } IBSR;

  union {                              /* I2C Bus Data I/O Register */
    vuint8_t R;
    struct {
      vuint8_t DATA:8;
    } B;
  } IBDR;

  union {                              /* I2C Bus Interrupt Config Register */
    vuint8_t R;
    struct {
      vuint8_t BIIE:1;
      vuint8_t  :7;
    } B;
  } IBIC;

  union {                              /* I2C Bus Debug Register */
    vuint8_t R;
    struct {
      vuint8_t  :6;
      vuint8_t IPG_DEBUG_HALTED:1;
      vuint8_t IPG_DEBUG_EN:1;
    } B;
  } IBDBG;
};


/* ============================================================================
   =============================== Module: IMA ================================
   ============================================================================ */

struct IMA_tag {
  union {                              /* Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t READ:1;
    } B;
  } CTRL;

  union {                              /* Enable Access Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t EN:1;
    } B;
  } ENABLE;

  union {                              /* Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t WRITE_LOCK:1;
      vuint32_t  :7;
      vuint32_t READ_LOCK:1;
    } B;
  } STATUS;

  union {                              /* RAM Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t ROW_SLCT:13;
      vuint32_t  :10;
      vuint32_t ARRAY_SLCT:6;
    } B;
  } SLCT;

  union {                              /* Write Unlock Register */
    vuint32_t R;
    struct {
      vuint32_t WRITE_KEY:32;
    } B;
  } WRITE_UNLOCK;

  union {                              /* Read Unlock Register */
    vuint32_t R;
    struct {
      vuint32_t READ_KEY:32;
    } B;
  } READ_UNLOCK;

  uint8_t IMA_reserved0[20];
  union {                              /* RAM Write Data Register 4 */
    vuint32_t R;
    struct {
      vuint32_t WRITE_4:32;
    } B;
  } WRITE_DATA_4;

  union {                              /* RAM Write Data Register 3 */
    vuint32_t R;
    struct {
      vuint32_t WRITE_3:32;
    } B;
  } WRITE_DATA_3;

  union {                              /* RAM Write Data Register 2 */
    vuint32_t R;
    struct {
      vuint32_t WRITE_2:32;
    } B;
  } WRITE_DATA_2;

  union {                              /* RAM Write Data Register 1 */
    vuint32_t R;
    struct {
      vuint32_t WRITE_1:32;
    } B;
  } WRITE_DATA_1;

  union {                              /* RAM Write Data Register 0 */
    vuint32_t R;
    struct {
      vuint32_t WRITE_0:32;
    } B;
  } WRITE_DATA_0;

  uint8_t IMA_reserved1[12];
  union {                              /* RAM Read Data Register 4 */
    vuint32_t R;
    struct {
      vuint32_t READ_4:32;
    } B;
  } READ_DATA_4;

  union {                              /* RAM Read Data Register 3 */
    vuint32_t R;
    struct {
      vuint32_t READ_3:32;
    } B;
  } READ_DATA_3;

  union {                              /* RAM Read Data Register 2 */
    vuint32_t R;
    struct {
      vuint32_t READ_2:32;
    } B;
  } READ_DATA_2;

  union {                              /* RAM Read Data Register 1 */
    vuint32_t R;
    struct {
      vuint32_t READ_1:32;
    } B;
  } READ_DATA_1;

  union {                              /* RAM Read Data Register 0 */
    vuint32_t R;
    struct {
      vuint32_t READ_0:32;
    } B;
  } READ_DATA_0;
};


/* ============================================================================
   =============================== Module: INTC ===============================
   ============================================================================ */

struct INTC_tag {
  union {                              /* INTC Block Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :19;
      vuint32_t HVEN3:1;
      vuint32_t  :3;
      vuint32_t HVEN2:1;
      vuint32_t  :3;
      vuint32_t HVEN1:1;
      vuint32_t  :3;
      vuint32_t HVEN0:1;
    } B;
  } BCR;

  union {                              /* INTC Master Protection Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t ID:2;
      vuint32_t  :3;
      vuint32_t MPROT:1;
    } B;
  } MPROT;

  uint8_t INTC_reserved0[8];
  union {                              /* INTC Current Priority Register for Processor n */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t PRI:6;
    } B;
  } CPR[4];

  union {                              /* INTC Interrupt Acknowledge Register for Processor n */
    vuint32_t R;
    struct {
      vuint32_t VTBA:20;
      vuint32_t INTVEC:10;
      vuint32_t  :2;
    } B;
  } IACKR[4];

  union {                              /* INTC End Of Interrupt Register for Processor n */
    vuint32_t R;
    struct {
      vuint32_t EOI:32;
    } B;
  } EOIR[4];

  union {                              /* INTC Software Set/Clear Interrupt Register */
    vuint8_t R;
    struct {
      vuint8_t  :6;
      vuint8_t SET:1;
      vuint8_t CLR:1;
    } B;
  } SSCIR[32];

  union {                              /* INTC Priority Select Register */
    vuint16_t R;
    struct {
      vuint16_t PRC_SELN:4;
      vuint16_t  :3;
      vuint16_t SWTN:1;
      vuint16_t  :2;
      vuint16_t PRIN:6;
    } B;
  } PSR[1024];
};


/* ============================================================================
   =============================== Module: IRCOSC =============================
   ============================================================================ */

struct IRCOSC_tag {
  union {                              /* IRCOSC Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t  :1;
      vuint32_t  :3;
      vuint32_t USER_TRIM:5;
      vuint32_t  :3;
      vuint32_t  :5;
      vuint32_t  :2;
      vuint32_t  :1;
      vuint32_t  :5;
    } B;
  } CTL;
};


/* ============================================================================
   =============================== Module: JDC ================================
   ============================================================================ */

struct JDC_tag {
  union {                              /* Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t JIN_IEN:1;
      vuint32_t  :15;
      vuint32_t JOUT_IEN:1;
    } B;
  } MCR;

  union {                              /* Module Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t JIN_RDY:1;
      vuint32_t  :1;
      vuint32_t JIN_INT:1;
      vuint32_t  :13;
      vuint32_t JOUT_RDY:1;
      vuint32_t  :1;
      vuint32_t JOUT_INT:1;
    } B;
  } MSR;

  union {                              /* JTAG Output Data Register */
    vuint32_t R;
    struct {
      vuint32_t Data:32;
    } B;
  } JOUT_IPS;

  union {                              /* JTAG Input Data Register */
    vuint32_t R;
    struct {
      vuint32_t Data:32;
    } B;
  } JIN_IPS;
};


/* ============================================================================
   =============================== Module: JTAGM ==============================
   ============================================================================ */

struct JTAGM_tag {
  union {                              /* Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t SWRESET:1;
      vuint32_t evto0_sense:2;
      vuint32_t evto1_sense:2;
      vuint32_t evto_IE:1;
      vuint32_t evti0_assert:1;
      vuint32_t evti1_assert:1;
      vuint32_t  :10;
      vuint32_t inter_jtag_frame_timer:6;
      vuint32_t  :1;
      vuint32_t SIE:1;
      vuint32_t IIE:1;
      vuint32_t TCKSEL:3;
      vuint32_t jtagm_JCOMP:1;
      vuint32_t DTM:1;
    } B;
  } MCR;

  union {                              /* Status Register */
    vuint32_t R;
    struct {
      vuint32_t Overrun:1;
      vuint32_t  :1;
      vuint32_t TXGOOD:1;
      vuint32_t TXERROR:1;
      vuint32_t RXOVFL:1;
      vuint32_t INVFPS:1;
      vuint32_t INVICLC:1;
      vuint32_t ILLLCT:1;
      vuint32_t  :1;
      vuint32_t LVDSEN:1;
      vuint32_t JTAGEN:1;
      vuint32_t LVDSSAFE:1;
      vuint32_t JTAGSAFE:1;
      vuint32_t LVDSESC:1;
      vuint32_t LFASTEN:1;
      vuint32_t TOOL:1;
      vuint32_t evto0_edge:1;
      vuint32_t evto1_edge:1;
      vuint32_t SPU_INT_CLR:1;
      vuint32_t SPU_INT:1;
      vuint32_t CRC_err:1;
      vuint32_t Nexus_err:1;
      vuint32_t Idle:1;
      vuint32_t NR:1;
      vuint32_t CRC:8;
    } B;
  } SR;

  union {                              /* Data Out Register 0 */
    vuint32_t R;
    struct {
      vuint32_t TMS_HIGH:32;
    } B;
  } DOR0;

  union {                              /* Data Out Register 1 */
    vuint32_t R;
    struct {
      vuint32_t TMS_LOW:28;
      vuint32_t  :4;
    } B;
  } DOR1;

  union {                              /* Data Out Register 2 */
    vuint32_t R;
    struct {
      vuint32_t TDI_HIGH:32;
    } B;
  } DOR2;

  union {                              /* Data Out Register 3 */
    vuint32_t R;
    struct {
      vuint32_t TDI_LOW:28;
      vuint32_t  :3;
      vuint32_t Send:1;
    } B;
  } DOR3;

  union {                              /* Receive CRC Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t CRC:8;
    } B;
  } RxCRC;

  union {                              /* Data Input Register 0 */
    vuint32_t R;
    struct {
      vuint32_t TDO_LOW:32;
    } B;
  } DIR0;

  union {                              /* Data Input Register 1 */
    vuint32_t R;
    struct {
      vuint32_t TDO_HIGH:28;
      vuint32_t  :4;
    } B;
  } DIR1;
};


/* ============================================================================
   =============================== Module: LFAST ==============================
   ============================================================================ */

struct LFAST_tag {
  union {                              /* LFAST Mode Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t MSEN:1;
      vuint32_t  :6;
      vuint32_t IPGDBG:1;
      vuint32_t  :7;
      vuint32_t LSSEL:1;
      vuint32_t DRFEN:1;
      vuint32_t RXEN:1;
      vuint32_t TXEN:1;
      vuint32_t  :8;
      vuint32_t TXARBD:1;
      vuint32_t CTSEN:1;
      vuint32_t  :1;
      vuint32_t DRFRST:1;
      vuint32_t DATAEN:1;
    } B;
  } MCR;

  union {                              /* LFAST Speed Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t DRMD:1;
      vuint32_t  :7;
      vuint32_t RDR:1;
      vuint32_t  :7;
      vuint32_t TDR:1;
    } B;
  } SCR;

  union {                              /* LFAST Correlator Control Register */
    vuint32_t R;
    struct {
      vuint32_t SMPSEL:8;
      vuint32_t  :6;
      vuint32_t  :2;
      vuint32_t  :12;
      vuint32_t CORRTH:3;
      vuint32_t PHSSEL:1;
    } B;
  } COCR;

  union {                              /* LFAST Test Mode Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t CLKTST:1;
      vuint32_t LPON:1;
      vuint32_t  :5;
      vuint32_t LPMOD:3;
      vuint32_t LPFRMTH:16;
    } B;
  } TMCR;

  union {                              /* LFAST Auto Loopback Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t LPCNTEN:1;
      vuint32_t LPFMCNT:16;
    } B;
  } ALCR;

  union {                              /* LFAST Rate Change Delay Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t DRCNT:4;
      vuint32_t  :16;
    } B;
  } RCDCR;

  union {                              /* LFAST Wakeup Delay Control Register */
    vuint32_t R;
    struct {
      vuint32_t HSCNT:8;
      vuint32_t  :4;
      vuint32_t LSCNT:4;
      vuint32_t HWKCNT:8;
      vuint32_t  :4;
      vuint32_t LWKCNT:4;
    } B;
  } SLCR;

  union {                              /* LFAST ICLC Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t ICLCSEQ:1;
      vuint32_t SNDICLC:1;
      vuint32_t  :8;
      vuint32_t ICLCPLD:8;
    } B;
  } ICR;

  union {                              /* LFAST Ping Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t PNGREQ:1;
      vuint32_t PNGAUTO:1;
      vuint32_t  :7;
      vuint32_t PNGPYLD:8;
    } B;
  } PICR;

  uint8_t LFAST_reserved0[8];
  union {                              /* LFAST Rx FIFO CTS Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :10;
      vuint32_t RCTSMX:6;
      vuint32_t  :10;
      vuint32_t RCTSMN:6;
    } B;
  } RFCR;

  union {                              /* LFAST Tx Interrupt Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t TXIIE:1;
      vuint32_t TXOVIE:1;
      vuint32_t  :11;
      vuint32_t TXPNGIE:1;
      vuint32_t  :1;
      vuint32_t TXUNSIE:1;
      vuint32_t TXICLCIE:1;
      vuint32_t TXDTIE:1;
    } B;
  } TIER;

  union {                              /* LFAST Rx Interrupt Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t RXUOIE:1;
      vuint32_t RXMNIE:1;
      vuint32_t RXMXIE:1;
      vuint32_t RXUFIE:1;
      vuint32_t RXOFIE:1;
      vuint32_t RXSZIE:1;
      vuint32_t RXICIE:1;
      vuint32_t RXLCEIE:1;
      vuint32_t  :12;
      vuint32_t RXCTSIE:1;
      vuint32_t RXDIE:1;
      vuint32_t RXUNSIE:1;
      vuint32_t  :1;
    } B;
  } RIER;

  union {                              /* LFAST Rx ICLC Interrupt Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t ICPFIE:1;
      vuint32_t ICPSIE:1;
      vuint32_t ICPRIE:1;
      vuint32_t ICTOIE:1;
      vuint32_t ICLPIE:1;
      vuint32_t ICCTIE:1;
      vuint32_t ICTDIE:1;
      vuint32_t ICTEIE:1;
      vuint32_t ICRFIE:1;
      vuint32_t ICRSIE:1;
      vuint32_t ICTFIE:1;
      vuint32_t ICTSIE:1;
      vuint32_t ICPOFIE:1;
      vuint32_t ICPONIE:1;
    } B;
  } RIIER;

  union {                              /* LFAST PLL Control Register */
    vuint32_t R;
    struct {
      vuint32_t IPTMOD:3;
      vuint32_t  :11;
      vuint32_t SWPOFF:1;
      vuint32_t SWPON:1;
      vuint32_t REFINV:1;
      vuint32_t LPCFG:2;
      vuint32_t  :2;
      vuint32_t PLCKCW:2;
      vuint32_t FDIVEN:1;
      vuint32_t FBDIV:6;
      vuint32_t PREDIV:2;
    } B;
  } PLLCR;

  union {                              /* LFAST LVDS Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SWWKLD:1;
      vuint32_t SWSLPLD:1;
      vuint32_t SWWKLR:1;
      vuint32_t SWSLPLR:1;
      vuint32_t SWOFFLD:1;
      vuint32_t SWONLD:1;
      vuint32_t SWOFFLR:1;
      vuint32_t SWONLR:1;
      vuint32_t LVRXOFF:1;
      vuint32_t LVTXOE:1;
      vuint32_t TXCMUX:1;
      vuint32_t LVRFEN:1;
      vuint32_t LVLPEN:1;              /* Tx LVDS internal loopback enable */
      vuint32_t  :5;
      vuint32_t LVRXOP:3;
      vuint32_t LVTXOP:1;
      vuint32_t LVCKSS:1;
      vuint32_t LVCKP:1;
    } B;
  } LCR;

  union {                              /* LFAST Unsolicited Tx Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t USNDRQ:1;
      vuint32_t  :9;
      vuint32_t UNSHDR:7;
    } B;
  } UNSTCR;

  union {                              /* LFAST Unsolicited Tx Data Registers */
    vuint32_t R;
    struct {
      vuint32_t UNTXD:32;
    } B;
  } UNSTDR[9];

  uint8_t LFAST_reserved1[20];
  union {                              /* LFAST Global Status Register */
    vuint32_t R;
    struct {
      vuint32_t DUALMD:1;
      vuint32_t  :12;
      vuint32_t LRMD:1;
      vuint32_t LDSM:1;
      vuint32_t DRSM:1;
      vuint32_t  :11;
      vuint32_t LPTXDN:1;
      vuint32_t LPFPDV:1;
      vuint32_t LPCPDV:1;
      vuint32_t LPCHDV:1;
      vuint32_t LPCSDV:1;
    } B;
  } GSR;

  union {                              /* LFAST Ping Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t RXPNGD:8;
    } B;
  } PISR;

  uint8_t LFAST_reserved2[12];
  union {                              /* LFAST Data Frame Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t RXDCNT:6;
      vuint32_t  :5;
      vuint32_t RXFCNT:3;
      vuint32_t  :2;
      vuint32_t TXDCNT:6;
      vuint32_t  :5;
      vuint32_t TXFCNT:3;
    } B;
  } DFSR;

  union {                              /* LFAST Tx Interrupt Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t TXIEF:1;
      vuint32_t TXOVF:1;
      vuint32_t  :11;
      vuint32_t TXPNGF:1;
      vuint32_t  :1;
      vuint32_t TXUNSF:1;
      vuint32_t TXICLCF:1;
      vuint32_t TXDTF:1;
    } B;
  } TISR;

  union {                              /* LFAST Rx Interrupt Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t RXUOF:1;
      vuint32_t RXMNF:1;
      vuint32_t RXMXF:1;
      vuint32_t RXUFF:1;
      vuint32_t RXOFF:1;
      vuint32_t RXSZF:1;
      vuint32_t RXICF:1;
      vuint32_t RXLCEF:1;
      vuint32_t  :12;
      vuint32_t RXCTSF:1;
      vuint32_t RXDF:1;
      vuint32_t RXUNSF:1;
      vuint32_t  :1;
    } B;
  } RISR;

  union {                              /* LFAST Rx ICLC Interrupt Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t ICPFF:1;
      vuint32_t ICPSF:1;
      vuint32_t ICPRF:1;
      vuint32_t ICTOF:1;
      vuint32_t ICLPF:1;
      vuint32_t ICCTF:1;
      vuint32_t ICTDF:1;
      vuint32_t ICTEF:1;
      vuint32_t ICRFF:1;
      vuint32_t ICRSF:1;
      vuint32_t ICTFF:1;
      vuint32_t ICTSF:1;
      vuint32_t ICPOFF:1;
      vuint32_t ICPONF:1;
    } B;
  } RIISR;

  union {                              /* LFAST PLL and LVDS Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t PLLDIS:1;
      vuint32_t PLDCR:1;
      vuint32_t  :12;
      vuint32_t LRSLPS:1;
      vuint32_t LDSLPS:1;
      vuint32_t LDPDS:1;
      vuint32_t LRPDS:1;
    } B;
  } PLLLSR;

  union {                              /* LFAST Unsolicited Rx Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t URXDV:1;
      vuint32_t  :5;
      vuint32_t URPCNT:3;
    } B;
  } UNSRSR;

  union {                              /* LFAST Unsolicited Rx Data Register */
    vuint32_t R;
    struct {
      vuint32_t UNRXD:32;
    } B;
  } UNSRDR[9];
};


/* ============================================================================
   =============================== Module: LINFlexD ===========================
   ============================================================================ */

struct LINFlexD_tag {
  union {                              /* LIN Control Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CCD:1;
      vuint32_t CFD:1;
      vuint32_t LASE:1;
      vuint32_t AUTOWU:1;
      vuint32_t MBL:4;
      vuint32_t BF:1;
      vuint32_t  :1;
      vuint32_t LBKM:1;
      vuint32_t MME:1;
      vuint32_t SSBL:1;
      vuint32_t RBLM:1;
      vuint32_t SLEEP:1;
      vuint32_t INIT:1;
    } B;
  } LINCR1;

  union {                              /* LIN Interrupt enable register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SZIE:1;
      vuint32_t OCIE:1;
      vuint32_t BEIE:1;
      vuint32_t CEIE:1;
      vuint32_t HEIE:1;
      vuint32_t  :2;
      vuint32_t FEIE:1;
      vuint32_t BOIE:1;
      vuint32_t LSIE:1;
      vuint32_t WUIE:1;
      vuint32_t DBFIE:1;
      vuint32_t DBEIETOIE:1;
      vuint32_t DRIE:1;
      vuint32_t DTIE:1;
      vuint32_t HRIE:1;
    } B;
  } LINIER;

  union {                              /* LIN Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t AUTOSYNC_COMP:1;
      vuint32_t RDC:3;
      vuint32_t LINS:4;                /* LIN state */
      vuint32_t  :2;
      vuint32_t RMB:1;
      vuint32_t DRBNE:1;
      vuint32_t RXbusy:1;
      vuint32_t RDI:1;
      vuint32_t WUF:1;
      vuint32_t DBFF:1;
      vuint32_t DBEF:1;
      vuint32_t DRF:1;
      vuint32_t DTF:1;
      vuint32_t HRF:1;
    } B;
  } LINSR;

  union {                              /* LIN Error Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SZF:1;
      vuint32_t OCF:1;
      vuint32_t BEF:1;
      vuint32_t CEF:1;
      vuint32_t SFEF:1;
      vuint32_t SDEF:1;
      vuint32_t IDPEF:1;
      vuint32_t FEF:1;
      vuint32_t BOF:1;
      vuint32_t  :6;
      vuint32_t NF:1;
    } B;
  } LINESR;

  union {                              /* UART Mode Control Register */
    vuint32_t R;
    struct {
      vuint32_t MIS:1;
      vuint32_t CSP:3;
      vuint32_t OSR:4;
      vuint32_t ROSE:1;
      vuint32_t NEF:3;
      vuint32_t DTU_PCETX:1;           /* Disable Timeout in UART mode/Parity transmission and checking */
      vuint32_t SBUR:2;
      vuint32_t WLS:1;
      vuint32_t TDFL_TFC:3;
      vuint32_t RDFL_RFC:3;
      vuint32_t RFBM:1;
      vuint32_t TFBM:1;
      vuint32_t WL1:1;
      vuint32_t PC1:1;
      vuint32_t RxEn:1;
      vuint32_t TxEn:1;
      vuint32_t PC0:1;
      vuint32_t PCE:1;
      vuint32_t WL0:1;
      vuint32_t UART:1;
    } B;
  } UARTCR;

  union {                              /* UART Mode Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SZF:1;
      vuint32_t OCF:1;
      vuint32_t PE:4;
      vuint32_t RMB:1;
      vuint32_t FEF:1;
      vuint32_t BOF:1;
      vuint32_t RDI:1;
      vuint32_t WUF:1;
      vuint32_t RFNE:1;
      vuint32_t TO:1;
      vuint32_t DRFRFE:1;
      vuint32_t DTFTFF:1;
      vuint32_t NF:1;
    } B;
  } UARTSR;

  union {                              /* LIN Time-Out Control Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t MODE:1;
      vuint32_t IOT:1;
      vuint32_t TOCE:1;
      vuint32_t CNT:8;
    } B;
  } LINTCSR;

  union {                              /* LIN Output Compare Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t OC2:8;
      vuint32_t OC1:8;
    } B;
  } LINOCR;

  union {                              /* LIN Time-Out Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t RTO:4;
      vuint32_t  :1;
      vuint32_t HTO:7;
    } B;
  } LINTOCR;

  union {                              /* LIN Fractional Baud Rate Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t FBR:4;
    } B;
  } LINFBRR;

  union {                              /* LIN Integer Baud Rate Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t IBR:20;
    } B;
  } LINIBRR;

  union {                              /* LIN Checksum Field Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t CF:8;
    } B;
  } LINCFR;

  union {                              /* LIN Control Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t TBDE:1;
      vuint32_t IOBE:1;
      vuint32_t IOPE:1;
      vuint32_t WURQ:1;
      vuint32_t DDRQ:1;
      vuint32_t DTRQ:1;
      vuint32_t ABRQ:1;
      vuint32_t HTRQ:1;
      vuint32_t  :8;
    } B;
  } LINCR2;

  union {                              /* Buffer Identifier Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DFL:6;
      vuint32_t DIR:1;
      vuint32_t CCS:1;
      vuint32_t  :2;
      vuint32_t ID:6;
    } B;
  } BIDR;

  union {                              /* Buffer Data Register Least Significant */
    vuint32_t R;
    struct {
      vuint32_t DATA3:8;
      vuint32_t DATA2:8;
      vuint32_t DATA1:8;
      vuint32_t DATA0:8;
    } B;
  } BDRL;

  union {                              /* Buffer Data Register Most Significant */
    vuint32_t R;
    struct {
      vuint32_t DATA7:8;
      vuint32_t DATA6:8;
      vuint32_t DATA5:8;
      vuint32_t DATA4:8;
    } B;
  } BDRM;

  union {                              /* Identifier Filter Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t FACT:16;
    } B;
  } IFER;

  union {                              /* Identifier Filter Match Index */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t IFMI:5;
    } B;
  } IFMI;

  union {                              /* Identifier Filter Mode Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t IFM:8;
    } B;
  } IFMR;

  union {                              /* Identifier Filter Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DFL:6;                 /* Data Field Length */
      vuint32_t DIR:1;                 /* Direction */
      vuint32_t CCS:1;                 /* Classic Checksum */
      vuint32_t  :2;
      vuint32_t ID:6;                  /* Identifier */
    } B;
  } IFCR[16];

  union {                              /* Global Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t TDFBM:1;
      vuint32_t RDFBM:1;
      vuint32_t TDLIS:1;
      vuint32_t RDLIS:1;
      vuint32_t STOP:1;
      vuint32_t SR:1;
    } B;
  } GCR;

  union {                              /* UART Preset Timeout Register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t PTO:12;
    } B;
  } UARTPTO;

  union {                              /* UART Current Timeout Register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t CTO:12;
    } B;
  } UARTCTO;

  union {                              /* DMA Tx Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DTE:16;
    } B;
  } DMATXE;

  union {                              /* DMA Rx Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DRE:16;
    } B;
  } DMARXE;

  union {                              /* PSI5-S Tx Delay register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t IFD:5;
      vuint32_t EN:1;
    } B;
  } PTD;
};


/* ============================================================================
   =============================== Module: MC_CGM =============================
   ============================================================================ */

struct MC_CGM_tag {
  uint8_t MC_CGM_reserved0[1664];
  union {                              /* Auxiliary Clock 5 Cascaded Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC0;

  union {                              /* Auxiliary Clock 5 Cascaded Divider 1 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC1;

  union {                              /* Auxiliary Clock 5 Cascaded Divider 2 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC2;

  uint8_t MC_CGM_reserved1[4];
  union {                              /* Auxiliary Clock 5 Cascaded Divider 10 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC10;

  union {                              /* Auxiliary Clock 5 Cascaded Divider 11 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC11;

  union {                              /* Auxiliary Clock 5 Cascaded Divider 12 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC12;

  union {                              /* Auxiliary Clock 5 Cascaded Divider 13 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC13;

  union {                              /* Auxiliary Clock 5 Cascaded Divider 20 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC20;

  union {                              /* Auxiliary Clock 5 Cascaded Divider 21 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC21;

  union {                              /* Auxiliary Clock 5 Cascaded Divider 22 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC22;

  uint8_t MC_CGM_reserved2[84];
  union {                              /* PCS Switch Duration Register */
    vuint8_t R;
    struct {
      vuint8_t SDUR:8;
    } B;
  } PCS_SDUR;

  uint8_t MC_CGM_reserved3[3];
  union {                              /* PCS Divider Change Register 1 */
    vuint32_t R;
    struct {
      vuint32_t INIT:16;
      vuint32_t  :8;
      vuint32_t RATE:8;
    } B;
  } PCS_DIVC1;

  union {                              /* PCS Divider End Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t DIVE:20;
    } B;
  } PCS_DIVE1;

  union {                              /* PCS Divider Start Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t DIVS:20;
    } B;
  } PCS_DIVS1;

  union {                              /* PCS Divider Change Register 2 */
    vuint32_t R;
    struct {
      vuint32_t INIT:16;
      vuint32_t  :8;
      vuint32_t RATE:8;
    } B;
  } PCS_DIVC2;

  union {                              /* PCS Divider End Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t DIVE:20;
    } B;
  } PCS_DIVE2;

  union {                              /* PCS Divider Start Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t DIVS:20;
    } B;
  } PCS_DIVS2;

  uint8_t MC_CGM_reserved4[12];
  union {                              /* PCS Divider Change Register 4 */
    vuint32_t R;
    struct {
      vuint32_t INIT:16;
      vuint32_t  :8;
      vuint32_t RATE:8;
    } B;
  } PCS_DIVC4;

  union {                              /* PCS Divider End Register 4 */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t DIVE:20;
    } B;
  } PCS_DIVE4;

  union {                              /* PCS Divider Start Register 4 */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t DIVS:20;
    } B;
  } PCS_DIVS4;

  uint8_t MC_CGM_reserved5[156];
  union {                              /* System Clock Divider Ratio Change Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t SYS_DIV_RATIO_CHNG:1;
    } B;
  } SC_DIV_RC;

  union {                              /* Divider Update Type Register */
    vuint32_t R;
    struct {
      vuint32_t SYS_UPD_TYPE:1;
      vuint32_t  :31;
    } B;
  } DIV_UPD_TYPE;

  union {                              /* Divider Update Trigger Register */
    vuint32_t R;
    struct {
      vuint32_t DIV_UPD_TRIGGER:32;
    } B;
  } DIV_UPD_TRIG;

  union {                              /* Divider Update Status Register */
    vuint32_t R;
    struct {
      vuint32_t SYS_UPD_STAT:1;
      vuint32_t  :31;
    } B;
  } DIV_UPD_STAT;

  uint8_t MC_CGM_reserved6[4];
  union {                              /* System Clock Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :4;
      vuint32_t SWTRG:3;
      vuint32_t SWIP:1;
      vuint32_t  :16;
    } B;
  } SC_SS;

  union {                              /* System Clock Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :9;
      vuint32_t DIV:6;
      vuint32_t  :16;
    } B;
  } SC_DC0;

  union {                              /* System Clock Divider 1 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :9;
      vuint32_t DIV:6;
      vuint32_t  :16;
    } B;
  } SC_DC1;

  union {                              /* System Clock Divider 2 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :9;
      vuint32_t DIV:6;
      vuint32_t  :16;
    } B;
  } SC_DC2;

  union {                              /* System Clock Divider 3 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :9;
      vuint32_t DIV:6;
      vuint32_t  :16;
    } B;
  } SC_DC3;

  union {                              /* System Clock Divider 4 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :9;
      vuint32_t DIV:6;
      vuint32_t  :16;
    } B;
  } SC_DC4;

  uint8_t MC_CGM_reserved7[4];
  union {                              /* Auxiliary Clock 0 Select Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELCTL:4;
      vuint32_t  :24;
    } B;
  } AC0_SC;

  union {                              /* Auxiliary Clock 0 Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :24;
    } B;
  } AC0_SS;

  union {                              /* Auxiliary Clock 0 Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :11;
      vuint32_t DIV:4;
      vuint32_t  :16;
    } B;
  } AC0_DC0;

  union {                              /* Auxiliary Clock 0 Divider 1 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :8;
      vuint32_t DIV:7;
      vuint32_t  :16;
    } B;
  } AC0_DC1;

  union {                              /* Auxiliary Clock 0 Divider 2 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :8;
      vuint32_t DIV:7;
      vuint32_t  :16;
    } B;
  } AC0_DC2;

  union {                              /* Auxiliary Clock 0 Divider 3 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :6;
      vuint32_t DIV:9;
      vuint32_t  :14;
      vuint32_t DIV_FMT:2;
    } B;
  } AC0_DC3;

  union {                              /* Auxiliary Clock 0 Divider 4 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :11;
      vuint32_t DIV:4;
      vuint32_t  :16;
    } B;
  } AC0_DC4;

  uint8_t MC_CGM_reserved8[4];
  union {                              /* Auxiliary Clock 1 Select Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELCTL:4;
      vuint32_t  :24;
    } B;
  } AC1_SC;

  union {                              /* Auxiliary Clock 1 Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :24;
    } B;
  } AC1_SS;

  union {                              /* Auxiliary Clock 1 Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :8;
      vuint32_t DIV:7;
      vuint32_t  :16;
    } B;
  } AC1_DC0;

  uint8_t MC_CGM_reserved9[28];
  union {                              /* Auxiliary Clock 2 Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :9;
      vuint32_t DIV:6;
      vuint32_t  :16;
    } B;
  } AC2_DC0;

  union {                              /* Auxiliary Clock 2 Divider 1 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :9;
      vuint32_t DIV:6;
      vuint32_t  :16;
    } B;
  } AC2_DC1;

  uint8_t MC_CGM_reserved10[16];
  union {                              /* Auxiliary Clock 3 Select Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELCTL:4;
      vuint32_t  :24;
    } B;
  } AC3_SC;

  union {                              /* Auxiliary Clock 3 Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :24;
    } B;
  } AC3_SS;

  uint8_t MC_CGM_reserved11[24];
  union {                              /* Auxiliary Clock 4 Select Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELCTL:4;
      vuint32_t  :24;
    } B;
  } AC4_SC;

  union {                              /* Auxiliary Clock 4 Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :24;
    } B;
  } AC4_SS;

  uint8_t MC_CGM_reserved12[32];
  union {                              /* Auxiliary Clock 5 Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :2;
      vuint32_t DIV:13;
      vuint32_t  :14;
      vuint32_t DIV_FMT:2;
    } B;
  } AC5_DC0;

  union {                              /* Auxiliary Clock 5 Divider 1 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :7;
      vuint32_t DIV:8;
      vuint32_t  :16;
    } B;
  } AC5_DC1;

  union {                              /* Auxiliary Clock 5 Divider 2 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_DC2;

  uint8_t MC_CGM_reserved13[12];
  union {                              /* Auxiliary Clock 6 Select Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELCTL:4;
      vuint32_t  :24;
    } B;
  } AC6_SC;

  union {                              /* Auxiliary Clock 6 Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :24;
    } B;
  } AC6_SS;

  union {                              /* Auxiliary Clock 6 Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :6;
      vuint32_t DIV:9;
      vuint32_t  :16;
    } B;
  } AC6_DC0;

  uint8_t MC_CGM_reserved14[20];
  union {                              /* Auxiliary Clock 7 Select Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELCTL:4;
      vuint32_t  :24;
    } B;
  } AC7_SC;

  union {                              /* Auxiliary Clock 7 Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :24;
    } B;
  } AC7_SS;

  union {                              /* Auxiliary Clock 7 Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :6;
      vuint32_t DIV:9;
      vuint32_t  :16;
    } B;
  } AC7_DC0;

  uint8_t MC_CGM_reserved15[20];
  union {                              /* Auxiliary Clock 8 Select Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELCTL:4;
      vuint32_t  :24;
    } B;
  } AC8_SC;

  union {                              /* Auxiliary Clock 8 Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :24;
    } B;
  } AC8_SS;

  union {                              /* Auxiliary Clock 8 Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :9;
      vuint32_t DIV:6;
      vuint32_t  :16;
    } B;
  } AC8_DC0;

  uint8_t MC_CGM_reserved16[20];
  union {                              /* Auxiliary Clock 9 Select Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELCTL:4;
      vuint32_t  :24;
    } B;
  } AC9_SC;

  union {                              /* Auxiliary Clock 9 Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :24;
    } B;
  } AC9_SS;

  union {                              /* Auxiliary Clock 9 Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :9;
      vuint32_t DIV:6;
      vuint32_t  :16;
    } B;
  } AC9_DC0;

  uint8_t MC_CGM_reserved17[20];
  union {                              /* Auxiliary Clock 10 Select Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELCTL:4;
      vuint32_t  :24;
    } B;
  } AC10_SC;

  union {                              /* Auxiliary Clock 10 Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :24;
    } B;
  } AC10_SS;

  union {                              /* Auxiliary Clock 10 Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :11;
      vuint32_t DIV:4;
      vuint32_t  :16;
    } B;
  } AC10_DC0;
};


/* ============================================================================
   =============================== Module: MC_ME ==============================
   ============================================================================ */

struct MC_ME_tag {
  union {                              /* Global Status Register */
    vuint32_t R;
    struct {
      vuint32_t S_CURRENT_MODE:4;
      vuint32_t S_MTRANS:1;
      vuint32_t  :1;
      vuint32_t  :2;
      vuint32_t S_PDO:1;
      vuint32_t  :2;
      vuint32_t S_MVR:1;
      vuint32_t  :2;
      vuint32_t S_FLA:2;
      vuint32_t  :8;
      vuint32_t S_PLL1:1;
      vuint32_t S_PLL0:1;
      vuint32_t S_XOSC:1;
      vuint32_t S_IRC:1;
      vuint32_t S_SYSCLK:4;
    } B;
  } GS;

  union {                              /* Mode Control Register */
    vuint32_t R;
    struct {
      vuint32_t TARGET_MODE:4;
      vuint32_t  :12;
      vuint32_t KEY:16;
    } B;
  } MCTL;

  union {                              /* Mode Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t RESET_DEST:1;
      vuint32_t  :4;
      vuint32_t STOP0:1;
      vuint32_t  :1;
      vuint32_t HALT0:1;
      vuint32_t RUN3:1;
      vuint32_t RUN2:1;
      vuint32_t RUN1:1;
      vuint32_t RUN0:1;
      vuint32_t DRUN:1;
      vuint32_t SAFE:1;
      vuint32_t TEST:1;
      vuint32_t RESET_FUNC:1;
    } B;
  } ME;

  union {                              /* Interrupt Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t I_ICONF_CC:1;
      vuint32_t I_ICONF_CU:1;
      vuint32_t I_ICONF:1;
      vuint32_t I_IMODE:1;
      vuint32_t I_SAFE:1;
      vuint32_t I_MTC:1;
    } B;
  } IS;

  union {                              /* Interrupt Mask Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t M_ICONF_CC:1;
      vuint32_t M_ICONF_CU:1;
      vuint32_t M_ICONF:1;
      vuint32_t M_IMODE:1;
      vuint32_t M_SAFE:1;
      vuint32_t M_MTC:1;
    } B;
  } IM;

  union {                              /* Invalid Mode Transition Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t S_MRIG:1;
      vuint32_t S_MTI:1;
      vuint32_t S_MRI:1;
      vuint32_t S_DMA:1;
      vuint32_t S_NMA:1;
      vuint32_t S_SEA:1;
    } B;
  } IMTS;

  union {                              /* Debug Mode Transition Status Register */
    vuint32_t R;
    struct {
      vuint32_t PREVIOUS_MODE:4;
      vuint32_t  :4;
      vuint32_t MPH_BUSY:1;
      vuint32_t  :2;
      vuint32_t PMC_PROG:1;
      vuint32_t DBG_MODE:1;
      vuint32_t CCKL_PROG:1;
      vuint32_t PCS_PROG:1;
      vuint32_t SMR:1;
      vuint32_t  :1;
      vuint32_t VREG_CSRC_SC:1;
      vuint32_t CSRC_CSRC_SC:1;
      vuint32_t IRC_SC:1;
      vuint32_t SCSRC_SC:1;
      vuint32_t SYSCLK_SW:1;
      vuint32_t  :1;
      vuint32_t FLASH_SC:1;
      vuint32_t CDP_PRPH_224_255:1;
      vuint32_t CDP_PRPH_192_223:1;
      vuint32_t CDP_PRPH_160_191:1;
      vuint32_t CDP_PRPH_128_159:1;
      vuint32_t CDP_PRPH_96_127:1;
      vuint32_t CDP_PRPH_64_95:1;
      vuint32_t CDP_PRPH_32_63:1;
      vuint32_t CDP_PRPH_0_31:1;
    } B;
  } DMTS;

  uint8_t MC_ME_reserved0[4];
  union {                              /* RESET Mode Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t PWRLVL:3;
      vuint32_t  :4;
      vuint32_t PDO:1;
      vuint32_t  :2;
      vuint32_t MVRON:1;
      vuint32_t  :2;
      vuint32_t FLAON:2;
      vuint32_t  :8;
      vuint32_t PLL1ON:1;
      vuint32_t PLL0ON:1;
      vuint32_t XOSCON:1;
      vuint32_t IRCON:1;
      vuint32_t SYSCLK:4;
    } B;
  } RESET_MC;

  union {                              /* TEST Mode Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t PWRLVL:3;
      vuint32_t  :4;
      vuint32_t PDO:1;
      vuint32_t  :2;
      vuint32_t MVRON:1;
      vuint32_t  :2;
      vuint32_t FLAON:2;
      vuint32_t  :8;
      vuint32_t PLL1ON:1;
      vuint32_t PLL0ON:1;
      vuint32_t XOSCON:1;
      vuint32_t IRCON:1;
      vuint32_t SYSCLK:4;
    } B;
  } TEST_MC;

  union {                              /* SAFE Mode Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t PWRLVL:3;
      vuint32_t  :4;
      vuint32_t PDO:1;
      vuint32_t  :2;
      vuint32_t MVRON:1;
      vuint32_t  :2;
      vuint32_t FLAON:2;
      vuint32_t  :8;
      vuint32_t PLL1ON:1;
      vuint32_t PLL0ON:1;
      vuint32_t XOSCON:1;
      vuint32_t IRCON:1;
      vuint32_t SYSCLK:4;
    } B;
  } SAFE_MC;

  union {                              /* DRUN Mode Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t PWRLVL:3;
      vuint32_t  :4;
      vuint32_t PDO:1;
      vuint32_t  :2;
      vuint32_t MVRON:1;
      vuint32_t  :2;
      vuint32_t FLAON:2;
      vuint32_t  :8;
      vuint32_t PLL1ON:1;
      vuint32_t PLL0ON:1;
      vuint32_t XOSCON:1;
      vuint32_t IRCON:1;
      vuint32_t SYSCLK:4;
    } B;
  } DRUN_MC;

  union {                              /* RUN0 Mode Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t PWRLVL:3;
      vuint32_t  :4;
      vuint32_t PDO:1;
      vuint32_t  :2;
      vuint32_t MVRON:1;
      vuint32_t  :2;
      vuint32_t FLAON:2;
      vuint32_t  :8;
      vuint32_t PLL1ON:1;
      vuint32_t PLL0ON:1;
      vuint32_t XOSCON:1;
      vuint32_t IRCON:1;
      vuint32_t SYSCLK:4;
    } B;
  } RUN_MC[4];

  union {                              /* HALT0 Mode Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t PWRLVL:3;
      vuint32_t  :4;
      vuint32_t PDO:1;
      vuint32_t  :2;
      vuint32_t MVRON:1;
      vuint32_t  :2;
      vuint32_t FLAON:2;
      vuint32_t  :8;
      vuint32_t PLL1ON:1;
      vuint32_t PLL0ON:1;
      vuint32_t XOSCON:1;
      vuint32_t IRCON:1;
      vuint32_t SYSCLK:4;
    } B;
  } HALT0_MC;

  uint8_t MC_ME_reserved1[4];
  union {                              /* STOP0 Mode Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t PWRLVL:3;
      vuint32_t  :4;
      vuint32_t PDO:1;
      vuint32_t  :2;
      vuint32_t MVRON:1;
      vuint32_t  :2;
      vuint32_t FLAON:2;
      vuint32_t  :8;
      vuint32_t PLL1ON:1;
      vuint32_t PLL0ON:1;
      vuint32_t XOSCON:1;
      vuint32_t IRCON:1;
      vuint32_t SYSCLK:4;
    } B;
  } STOP0_MC;

  uint8_t MC_ME_reserved2[20];
  union {                              /* Peripheral Status Register 0 */
    vuint32_t R;
    struct {
      vuint32_t S_PIT_RTC_1:1;
      vuint32_t S_PIT_RTC_0:1;
      vuint32_t  :14;
      vuint32_t S_SIUL:1;
      vuint32_t  :3;
      vuint32_t S_SIPI_0:1;
      vuint32_t  :1;
      vuint32_t S_LFAST_0:1;
      vuint32_t  :5;
      vuint32_t S_EBI_0:1;
      vuint32_t  :3;
    } B;
  } PS0;

  union {                              /* Peripheral Status Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t S_ADCSD_0:1;
      vuint32_t S_ADCSD_2:1;
      vuint32_t S_ADCSD_4:1;
      vuint32_t S_ADCSD_6:1;
      vuint32_t S_ADCSD_8:1;
      vuint32_t  :17;
      vuint32_t S_CRC_0:1;
      vuint32_t  :1;
      vuint32_t S_DMAMUX_0:1;
      vuint32_t  :4;
    } B;
  } PS1;

  union {                              /* Peripheral Status Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t S_DSPI_12:1;
      vuint32_t S_LINFlexD_0:1;
      vuint32_t S_LINFlexD_1:1;
      vuint32_t  :5;
      vuint32_t S_LINFlexD_14:1;
      vuint32_t S_LINFlexD_16:1;
      vuint32_t  :9;
      vuint32_t S_CAN_RAM_CTRL:1;
      vuint32_t  :1;
      vuint32_t S_TTCAN:1;
      vuint32_t  :1;
      vuint32_t S_MCAN_1:1;
      vuint32_t S_MCAN_2:1;
      vuint32_t S_MCAN_3:1;
      vuint32_t S_MCAN_4:1;
      vuint32_t  :3;
    } B;
  } PS2;

  union {                              /* Peripheral Status Register 3 */
    vuint32_t R;
    struct {
      vuint32_t S_ADCSAR_0:1;
      vuint32_t  :3;
      vuint32_t S_ADCSAR_4:1;
      vuint32_t  :10;
      vuint32_t S_ADCSAR_b:1;
      vuint32_t S_PSI5_0:1;
      vuint32_t  :3;
      vuint32_t S_FLEXRAY_0:1;
      vuint32_t  :2;
      vuint32_t S_SENT_0:1;
      vuint32_t  :2;
      vuint32_t S_IIC_0:1;
      vuint32_t  :1;
      vuint32_t S_DSPI_0:1;
      vuint32_t S_DSPI_1:1;
      vuint32_t S_DSPI_4:1;
      vuint32_t S_DSPI_6:1;
    } B;
  } PS3;

  union {                              /* Peripheral Status Register 4 */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t S_GTMINT:1;
    } B;
  } PS4;

  union {                              /* Peripheral Status Register 5 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t S_ADCSD_1:1;
      vuint32_t S_ADCSD_3:1;
      vuint32_t S_ADCSD_5:1;
      vuint32_t S_ADCSD_7:1;
      vuint32_t S_ADCSD_9:1;
      vuint32_t  :17;
      vuint32_t S_CRC_1:1;
      vuint32_t  :3;
      vuint32_t S_PSI5S_0:1;
      vuint32_t  :2;
    } B;
  } PS5;

  union {                              /* Peripheral Status Register 6 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t S_LINFlexD_2:1;
      vuint32_t  :6;
      vuint32_t S_LINFlexD_15:1;
      vuint32_t  :21;
    } B;
  } PS6;

  union {                              /* Peripheral Status Register 7 */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t S_ADCSAR_1:1;
      vuint32_t S_ADCSAR_2:1;
      vuint32_t S_ADCSAR_3:1;
      vuint32_t  :1;
      vuint32_t S_ADCSAR_5:1;
      vuint32_t S_ADCSAR_6:1;
      vuint32_t S_ADCSAR_7:1;
      vuint32_t S_ADCSAR_8:1;
      vuint32_t S_ADCSAR_9:1;
      vuint32_t S_ADCSAR_10:1;
      vuint32_t  :5;
      vuint32_t S_PSI5_1:1;
      vuint32_t  :3;
      vuint32_t S_FLEXRAY_1:1;
      vuint32_t  :2;
      vuint32_t S_SENT_1:1;
      vuint32_t  :2;
      vuint32_t S_IIC_1:1;
      vuint32_t  :1;
      vuint32_t S_DSPI_2:1;
      vuint32_t S_DSPI_3:1;
      vuint32_t S_DSPI_5:1;
      vuint32_t  :1;
    } B;
  } PS7;

  union {                              /* Run Peripheral Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t RUN3:1;
      vuint32_t RUN2:1;
      vuint32_t RUN1:1;
      vuint32_t RUN0:1;
      vuint32_t DRUN:1;
      vuint32_t SAFE:1;
      vuint32_t TEST:1;
      vuint32_t RESET:1;
    } B;
  } RUN_PC[8];

  union {                              /* Low-Power Peripheral Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t STOP0:1;
      vuint32_t  :1;
      vuint32_t HALT0:1;
      vuint32_t  :8;
    } B;
  } LP_PC[8];

  uint8_t MC_ME_reserved3[3];
  union {                              /* EBI_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL3;

  uint8_t MC_ME_reserved4[5];
  union {                              /* LFAST_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL9;

  uint8_t MC_ME_reserved5[1];
  union {                              /* SIPI_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL11;

  uint8_t MC_ME_reserved6[3];
  union {                              /* SIUL Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL15;

  uint8_t MC_ME_reserved7[14];
  union {                              /* PIT_RTC_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL30;

  union {                              /* PIT_RTC_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL31;

  uint8_t MC_ME_reserved8[4];
  union {                              /* DMAMUX_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL36;

  uint8_t MC_ME_reserved9[1];
  union {                              /* CRC_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL38;

  uint8_t MC_ME_reserved10[17];
  union {                              /* ADCSD_8 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL56;

  union {                              /* ADCSD_6 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL57;

  union {                              /* ADCSD_4 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL58;

  union {                              /* ADCSD_2 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL59;

  union {                              /* ADCSD_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL60;

  uint8_t MC_ME_reserved11[6];
  union {                              /* MCAN_4 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL67;

  union {                              /* MCAN_3 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL68;

  union {                              /* MCAN_2 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL69;

  union {                              /* MCAN_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL70;

  uint8_t MC_ME_reserved12[1];
  union {                              /* TTCAN Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL72;

  uint8_t MC_ME_reserved13[1];
  union {                              /* CAN_RAM_CTRL Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL74;

  uint8_t MC_ME_reserved14[9];
  union {                              /* LINFlexD_16 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL84;

  union {                              /* LINFlexD_14 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL85;

  uint8_t MC_ME_reserved15[5];
  union {                              /* LINFlexD_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL91;

  union {                              /* LINFlexD_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL92;

  union {                              /* DSPI_12 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL93;

  uint8_t MC_ME_reserved16[2];
  union {                              /* DSPI_6 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL96;

  union {                              /* DSPI_4 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL97;

  union {                              /* DSPI_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL98;

  union {                              /* DSPI_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL99;

  uint8_t MC_ME_reserved17[1];
  union {                              /* IIC_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL101;

  uint8_t MC_ME_reserved18[2];
  union {                              /* SENT_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL104;

  uint8_t MC_ME_reserved19[2];
  union {                              /* FLEXRAY_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL107;

  uint8_t MC_ME_reserved20[3];
  union {                              /* PSI5_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL111;

  union {                              /* ADCSAR_b Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL112;

  uint8_t MC_ME_reserved21[10];
  union {                              /* ADCSAR_4 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL123;

  uint8_t MC_ME_reserved22[3];
  union {                              /* ADCSAR_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL127;

  union {                              /* GTMINT Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL128;

  uint8_t MC_ME_reserved23[33];
  union {                              /* PSI5_S_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL162;

  uint8_t MC_ME_reserved24[3];
  union {                              /* CRC_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL166;

  uint8_t MC_ME_reserved25[17];
  union {                              /* ADCSD_9 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL184;

  union {                              /* ADCSD_7 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL185;

  union {                              /* ADCSD_5 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL186;

  union {                              /* ADCSD_3 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL187;

  union {                              /* ADCSD_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL188;

  uint8_t MC_ME_reserved26[24];
  union {                              /* LINFlexD_15 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL213;

  uint8_t MC_ME_reserved27[6];
  union {                              /* LINFlexD_2 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL220;

  uint8_t MC_ME_reserved28[4];
  union {                              /* DSPI_5 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL225;

  union {                              /* DSPI_3 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL226;

  union {                              /* DSPI_2 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL227;

  uint8_t MC_ME_reserved29[1];
  union {                              /* IIC_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL229;

  uint8_t MC_ME_reserved30[2];
  union {                              /* SENT_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL232;

  uint8_t MC_ME_reserved31[2];
  union {                              /* FLEXRAY_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL235;

  uint8_t MC_ME_reserved32[3];
  union {                              /* PSI5_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL239;

  uint8_t MC_ME_reserved33[5];
  union {                              /* ADCSAR_10 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL245;

  union {                              /* ADCSAR_9 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL246;

  union {                              /* ADCSAR_8 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL247;

  union {                              /* ADCSAR_7 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL248;

  union {                              /* ADCSAR_6 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL249;

  union {                              /* ADCSAR_5 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL250;

  uint8_t MC_ME_reserved34[1];
  union {                              /* ADCSAR_3 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL252;

  union {                              /* ADCSAR_2 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL253;

  union {                              /* ADCSAR_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL254;

  uint8_t MC_ME_reserved35[1];
  union {                              /* Core Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t S_CORE4:1;
      vuint32_t S_CORE3:1;
      vuint32_t S_CORE2:1;
      vuint32_t S_CORE1:1;
      vuint32_t S_CORE0:1;
    } B;
  } CS;

  union {                              /* CORE0 Core Control Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t STOP0:1;
      vuint16_t  :1;
      vuint16_t HALT0:1;
      vuint16_t RUN3:1;
      vuint16_t RUN2:1;
      vuint16_t RUN1:1;
      vuint16_t RUN0:1;
      vuint16_t DRUN:1;
      vuint16_t SAFE:1;
      vuint16_t TEST:1;
      vuint16_t RESET:1;
    } B;
  } CCTL0;

  union {                              /* CORE1 Core Control Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t STOP0:1;
      vuint16_t  :1;
      vuint16_t HALT0:1;
      vuint16_t RUN3:1;
      vuint16_t RUN2:1;
      vuint16_t RUN1:1;
      vuint16_t RUN0:1;
      vuint16_t DRUN:1;
      vuint16_t SAFE:1;
      vuint16_t TEST:1;
      vuint16_t RESET:1;
    } B;
  } CCTL1;

  union {                              /* CORE2 Core Control Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t STOP0:1;
      vuint16_t  :1;
      vuint16_t HALT0:1;
      vuint16_t RUN3:1;
      vuint16_t RUN2:1;
      vuint16_t RUN1:1;
      vuint16_t RUN0:1;
      vuint16_t DRUN:1;
      vuint16_t SAFE:1;
      vuint16_t TEST:1;
      vuint16_t RESET:1;
    } B;
  } CCTL2;

  union {                              /* CORE3 Core Control Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t STOP0:1;
      vuint16_t  :1;
      vuint16_t HALT0:1;
      vuint16_t RUN3:1;
      vuint16_t RUN2:1;
      vuint16_t RUN1:1;
      vuint16_t RUN0:1;
      vuint16_t DRUN:1;
      vuint16_t SAFE:1;
      vuint16_t TEST:1;
      vuint16_t RESET:1;
    } B;
  } CCTL3;

  union {                              /* CORE4 Core Control Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t STOP0:1;
      vuint16_t  :1;
      vuint16_t HALT0:1;
      vuint16_t RUN3:1;
      vuint16_t RUN2:1;
      vuint16_t RUN1:1;
      vuint16_t RUN0:1;
      vuint16_t DRUN:1;
      vuint16_t SAFE:1;
      vuint16_t TEST:1;
      vuint16_t RESET:1;
    } B;
  } CCTL4;

  uint8_t MC_ME_reserved36[18];
  union {                              /* CORE0 Core Address Register */
    vuint32_t R;
    struct {
      vuint32_t ADDR:30;
      vuint32_t  :1;
      vuint32_t RMC:1;
    } B;
  } CADDR0;

  union {                              /* CORE1 Core Address Register */
    vuint32_t R;
    struct {
      vuint32_t ADDR:30;
      vuint32_t  :1;
      vuint32_t RMC:1;
    } B;
  } CADDR1;

  union {                              /* CORE2 Core Address Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t RMC:1;
    } B;
  } CADDR2;

  union {                              /* CORE3 Core Address Register */
    vuint32_t R;
    struct {
      vuint32_t ADDR:30;
      vuint32_t  :1;
      vuint32_t RMC:1;
    } B;
  } CADDR3;

  union {                              /* CORE4 Core Address Register */
    vuint32_t R;
    struct {
      vuint32_t ADDR:30;
      vuint32_t  :1;
      vuint32_t RMC:1;
    } B;
  } CADDR4;
};


/* ============================================================================
   =============================== Module: MC_PCU =============================
   ============================================================================ */

struct MC_PCU_tag {
  uint8_t MC_PCU_reserved0[64];
  union {                              /* Power Domain Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t PD0:1;
    } B;
  } PSTAT;
};


/* ============================================================================
   =============================== Module: MC_RGM =============================
   ============================================================================ */

struct MC_RGM_tag {
  union {                              /* 'Destructive' Event Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t F_VOR_DEST:1;
      vuint32_t F_TSR_DEST:1;
      vuint32_t  :7;
      vuint32_t F_HSM_DEST:1;
      vuint32_t F_SSCM_DEST:1;
      vuint32_t  :3;
      vuint32_t F_JTAG_DEST:1;
      vuint32_t F_FIF:1;
      vuint32_t F_EDR:1;
      vuint32_t  :2;
      vuint32_t F_SUF:1;
      vuint32_t F_FFRR:1;
      vuint32_t F_SOFT_DEST:1;
      vuint32_t  :1;
      vuint32_t F_PORST:1;
      vuint32_t F_POR:1;
    } B;
  } DES;

  uint8_t MC_RGM_reserved0[12];
  union {                              /* 'Destructive' Event Reset Disable Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t D_VOR_DEST:1;
      vuint32_t  :8;
      vuint32_t D_HSM_DEST:1;
      vuint32_t D_SSCM_DEST:1;
      vuint32_t  :3;
      vuint32_t D_JTAG_DEST:1;
      vuint32_t D_FIF:1;
      vuint32_t D_EDR:1;
      vuint32_t  :2;
      vuint32_t D_SUF:1;
      vuint32_t D_FFRR:1;
      vuint32_t D_SOFT_DEST:1;
      vuint32_t  :1;
      vuint32_t D_PORST:1;
      vuint32_t D_POR:1;
    } B;
  } DERD;

  uint8_t MC_RGM_reserved1[12];
  union {                              /* 'Destructive' Event Alternate Request Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t AR_PORST:1;
      vuint32_t  :1;
    } B;
  } DEAR;

  uint8_t MC_RGM_reserved2[12];
  union {                              /* 'Destructive' Bidirectional Reset Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t BE_VOR_DEST:1;
      vuint32_t BE_TSR_DEST:1;
      vuint32_t  :7;
      vuint32_t BE_HSM_DEST:1;
      vuint32_t BE_SSCM_DEST:1;
      vuint32_t  :3;
      vuint32_t BE_JTAG_DEST:1;
      vuint32_t BE_FIF:1;
      vuint32_t BE_EDR:1;
      vuint32_t  :2;
      vuint32_t BE_SUF:1;
      vuint32_t BE_FFRR:1;
      vuint32_t BE_SOFT_DEST:1;
      vuint32_t  :1;
      vuint32_t BE_PORST:1;
      vuint32_t BE_POR:1;
    } B;
  } DBRE;

  uint8_t MC_RGM_reserved3[716];
  union {                              /* 'Functional' Event Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t F_VOR_FUNC:1;
      vuint32_t F_TSR_FUNC:1;
      vuint32_t  :7;
      vuint32_t F_HSM_FUNC:1;
      vuint32_t  :4;
      vuint32_t F_JTAG_FUNC:1;
      vuint32_t  :3;
      vuint32_t F_FCCU_SOFT:1;
      vuint32_t F_FCCU_HARD:1;
      vuint32_t  :1;
      vuint32_t F_SOFT_FUNC:1;
      vuint32_t F_ST_DONE:1;
      vuint32_t F_ESR1:1;
      vuint32_t F_ESR0:1;
    } B;
  } FES;

  uint8_t MC_RGM_reserved4[12];
  union {                              /* 'Functional' Event Reset Disable Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t D_VOR_FUNC:1;
      vuint32_t D_TSR_FUNC:1;
      vuint32_t  :7;
      vuint32_t D_HSM_FUNC:1;
      vuint32_t  :4;
      vuint32_t D_JTAG_FUNC:1;
      vuint32_t  :3;
      vuint32_t D_FCCU_SOFT:1;
      vuint32_t D_FCCU_HARD:1;
      vuint32_t  :2;
      vuint32_t D_ST_DONE:1;
      vuint32_t D_ESR1:1;
      vuint32_t D_ESR0:1;
    } B;
  } FERD;

  uint8_t MC_RGM_reserved5[12];
  union {                              /* 'Functional' Event Alternate Request Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t AR_VOR_FUNC:1;
      vuint32_t AR_TSR_FUNC:1;
      vuint32_t  :21;
      vuint32_t AR_ESR1:1;
      vuint32_t  :1;
    } B;
  } FEAR;

  uint8_t MC_RGM_reserved6[12];
  union {                              /* 'Functional' Bidirectional Reset Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t BE_VOR_FUNC:1;
      vuint32_t BE_TSR_FUNC:1;
      vuint32_t  :7;
      vuint32_t BE_HSM_FUNC:1;
      vuint32_t  :4;
      vuint32_t BE_JTAG_FUNC:1;
      vuint32_t  :3;
      vuint32_t BE_FCCU_SOFT:1;
      vuint32_t BE_FCCU_HARD:1;
      vuint32_t  :1;
      vuint32_t BE_SOFT_FUNC:1;
      vuint32_t BE_ST_DONE:1;
      vuint32_t BE_ESR1:1;
      vuint32_t BE_ESR0:1;
    } B;
  } FBRE;

  uint8_t MC_RGM_reserved7[12];
  union {                              /* 'Functional' Event Short Sequence Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t SS_VOR_FUNC:1;
      vuint32_t SS_TSR_FUNC:1;
      vuint32_t  :7;
      vuint32_t SS_HSM_FUNC:1;
      vuint32_t  :4;
      vuint32_t SS_JTAG_FUNC:1;
      vuint32_t  :3;
      vuint32_t SS_FCCU_SOFT:1;
      vuint32_t SS_FCCU_HARD:1;
      vuint32_t  :1;
      vuint32_t SS_SOFT_FUNC:1;
      vuint32_t SS_ST_DONE:1;
      vuint32_t SS_ESR1:1;
      vuint32_t SS_ESR0:1;
    } B;
  } FESS;

  uint8_t MC_RGM_reserved8[704];
  union {                              /* 'Functional' Reset Escalation Threshold Register */
    vuint8_t R;
    struct {
      vuint8_t  :4;
      vuint8_t FRET:4;
    } B;
  } FRET;

  uint8_t MC_RGM_reserved9[3];
  union {                              /* 'Destructive' Reset Escalation Threshold Register */
    vuint8_t R;
    struct {
      vuint8_t  :4;
      vuint8_t DRET:4;
    } B;
  } DRET;

  uint8_t MC_RGM_reserved10[3];
  union {                              /* External Reset Output Extension Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :6;
      vuint8_t ERIS:1;
      vuint8_t EROEC:1;
    } B;
  } EROEC;

  uint8_t MC_RGM_reserved11[3];
  union {                              /* Peripheral Reset Register 0 */
    vuint32_t R;
    struct {
      vuint32_t PIT_RTC_1_RST:1;
      vuint32_t PIT_RTC_0_RST:1;
      vuint32_t  :14;
      vuint32_t SIUL_RST:1;
      vuint32_t  :3;
      vuint32_t SIPI_0_RST:1;
      vuint32_t  :1;
      vuint32_t LFAST_0_RST:1;
      vuint32_t  :5;
      vuint32_t EBI_0_RST:1;
      vuint32_t  :3;
    } B;
  } PRST0;

  union {                              /* Peripheral Reset Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t ADCSD_0_RST:1;
      vuint32_t ADCSD_2_RST:1;
      vuint32_t ADCSD_4_RST:1;
      vuint32_t ADCSD_6_RST:1;
      vuint32_t ADCSD_8_RST:1;
      vuint32_t  :17;
      vuint32_t CRC_0_RST:1;
      vuint32_t  :1;
      vuint32_t DMAMUX_0_RST:1;
      vuint32_t  :4;
    } B;
  } PRST1;

  union {                              /* Peripheral Reset Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t DSPI_12_RST:1;
      vuint32_t LINFlexD_0_RST:1;
      vuint32_t LINFlexD_1_RST:1;
      vuint32_t  :5;
      vuint32_t LINFlexD_14_RST:1;
      vuint32_t LINFlexD_16_RST:1;
      vuint32_t  :9;
      vuint32_t CAN_RAM_CTR_RST:1;
      vuint32_t  :1;
      vuint32_t TTCAN_RST:1;
      vuint32_t  :1;
      vuint32_t MCAN_1_RST:1;
      vuint32_t MCAN_2_RST:1;
      vuint32_t MCAN_3_RST:1;
      vuint32_t MCAN_4_RST:1;
      vuint32_t  :3;
    } B;
  } PRST2;

  union {                              /* Peripheral Reset Register 3 */
    vuint32_t R;
    struct {
      vuint32_t ADCSAR_0_RST:1;
      vuint32_t  :3;
      vuint32_t ADCSAR_4_RST:1;
      vuint32_t  :10;
      vuint32_t ADCSAR_b_RST:1;
      vuint32_t PSI5_0_RST:1;
      vuint32_t  :3;
      vuint32_t FLEXRAY_0_RST:1;
      vuint32_t  :2;
      vuint32_t SENT_0_RST:1;
      vuint32_t  :2;
      vuint32_t IIC_0_RST:1;
      vuint32_t  :1;
      vuint32_t DSPI_0_RST:1;
      vuint32_t DSPI_1_RST:1;
      vuint32_t DSPI_4_RST:1;
      vuint32_t DSPI_6_RST:1;
    } B;
  } PRST3;

  union {                              /* Peripheral Reset Register 4 */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t GTMINT_RST:1;
    } B;
  } PRST4;

  union {                              /* Peripheral Reset Register 5 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t ADCSD_1_RST:1;
      vuint32_t ADCSD_3_RST:1;
      vuint32_t ADCSD_5_RST:1;
      vuint32_t ADCSD_7_RST:1;
      vuint32_t ADCSD_9_RST:1;
      vuint32_t  :14;
      vuint32_t FCCU_RST:1;
      vuint32_t  :2;
      vuint32_t CRC_1_RST:1;
      vuint32_t  :3;
      vuint32_t PSI5_S_0_RST:1;
      vuint32_t  :2;
    } B;
  } PRST5;

  union {                              /* Peripheral Reset Register 6 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t LINFlexD_2_RST:1;
      vuint32_t  :6;
      vuint32_t LINFlexD_15_RST:1;
      vuint32_t  :21;
    } B;
  } PRST6;

  union {                              /* Peripheral Reset Register 7 */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t ADCSAR_1_RST:1;
      vuint32_t ADCSAR_2_RST:1;
      vuint32_t ADCSAR_3_RST:1;
      vuint32_t  :1;
      vuint32_t ADCSAR_5_RST:1;
      vuint32_t ADCSAR_6_RST:1;
      vuint32_t ADCSAR_7_RST:1;
      vuint32_t ADCSAR_8_RST:1;
      vuint32_t ADCSAR_9_RST:1;
      vuint32_t ADCSAR_10_RST:1;
      vuint32_t  :5;
      vuint32_t PSI5_1_RST:1;
      vuint32_t  :3;
      vuint32_t FLEXRAY_1_RST:1;
      vuint32_t  :2;
      vuint32_t SENT_1_RST:1;
      vuint32_t  :2;
      vuint32_t IIC_1_RST:1;
      vuint32_t  :1;
      vuint32_t DSPI_2_RST:1;
      vuint32_t DSPI_3_RST:1;
      vuint32_t DSPI_5_RST:1;
      vuint32_t  :1;
    } B;
  } PRST7;
};


/* ============================================================================
   =============================== Module: MEMU ===============================
   ============================================================================ */

struct MEMU_tag {
  union {                              /* Control register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SWR:1;
      vuint32_t  :15;
    } B;
  } CTRL;

  union {                              /* Error flag register */
    vuint32_t R;
    struct {
      vuint32_t  :11;
      vuint32_t PR_CE:1;
      vuint32_t PR_UCE:1;
      vuint32_t PR_CEO:1;
      vuint32_t PR_UCO:1;
      vuint32_t PR_EBO:1;
      vuint32_t  :3;
      vuint32_t F_CE:1;
      vuint32_t F_UCE:1;
      vuint32_t F_CEO:1;
      vuint32_t F_UCO:1;
      vuint32_t F_EBO:1;
      vuint32_t  :3;
      vuint32_t SR_CE:1;
      vuint32_t SR_UCE:1;
      vuint32_t SR_CEO:1;
      vuint32_t SR_UCO:1;
      vuint32_t SR_EBO:1;
    } B;
  } ERR_FLAG;

  uint8_t MEMU_reserved0[4];
  union {                              /* Debug register */
    vuint32_t R;
    struct {
      vuint32_t  :11;
      vuint32_t FR_PR_CE:1;
      vuint32_t FR_PR_UCE:1;
      vuint32_t FR_PR_CEO:1;
      vuint32_t FR_PR_UCO:1;
      vuint32_t FR_PR_EBO:1;
      vuint32_t  :3;
      vuint32_t FR_F_CE:1;
      vuint32_t FR_F_UCE:1;
      vuint32_t FR_F_CEO:1;
      vuint32_t FR_F_UCO:1;
      vuint32_t FR_F_EBO:1;
      vuint32_t  :3;
      vuint32_t FR_SR_CE:1;
      vuint32_t FR_SR_UCE:1;
      vuint32_t FR_SR_CEO:1;
      vuint32_t FR_SR_UCO:1;
      vuint32_t FR_SR_EBO:1;
    } B;
  } DEBUG;

  uint8_t MEMU_reserved1[16];
  struct {
    union {                            /* System RAM correctable error reporting table status register */
      vuint32_t R;
      struct {
        vuint32_t VLD:1;
        vuint32_t  :23;
        vuint32_t BAD_BIT:8;
      } B;
    } STS;
    union {                            /* System RAM correctable error reporting table address register */
      vuint32_t R;
      struct {
        vuint32_t ERR_ADD:32;
      } B;
    } ADDR;
  } SYS_RAM_CERR[10];

  union {                              /* System RAM uncorrectable error reporting table status register */
    vuint32_t R;
    struct {
      vuint32_t VLD:1;
      vuint32_t  :31;
    } B;
  } SYS_RAM_UNCERR_STS;

  union {                              /* System RAM uncorrectable error reporting table address register */
    vuint32_t R;
    struct {
      vuint32_t ERR_ADD:32;
    } B;
  } SYS_RAM_UNCERR_ADDR;

  union {                              /* System RAM concurrent overflow register */
    vuint32_t R;
    struct {
      vuint32_t OFLW:32;
    } B;
  } SYS_RAM_OFLW[3];

  uint8_t MEMU_reserved2[1436];
  struct {
    union {                            /* Peripheral RAM correctable error reporting table status register */
      vuint32_t R;
      struct {
        vuint32_t VLD:1;
        vuint32_t  :23;
        vuint32_t BAD_BIT:8;
      } B;
    } STS;
    union {                            /* Peripheral RAM correctable error reporting table address register */
      vuint32_t R;
      struct {
        vuint32_t ERR_ADD:32;
      } B;
    } ADDR;
  } PERIPH_RAM_CERR[2];

  union {                              /* Peripheral RAM uncorrectable error reporting table status register */
    vuint32_t R;
    struct {
      vuint32_t VLD:1;
      vuint32_t  :31;
    } B;
  } PERIPH_RAM_UNCERR_STS;

  union {                              /* Peripheral RAM uncorrectable error reporting table address register */
    vuint32_t R;
    struct {
      vuint32_t ERR_ADD:32;
    } B;
  } PERIPH_RAM_UNCERR_ADDR;

  union {                              /* Peripheral RAM concurrent overflow register */
    vuint32_t R;
    struct {
      vuint32_t OFLW:32;
    } B;
  } PERIPH_RAM_OFLW0;

  uint8_t MEMU_reserved3[1508];
  struct {
    union {                            /* Flash memory correctable error reporting table status register */
      vuint32_t R;
      struct {
        vuint32_t VLD:1;
        vuint32_t  :23;
        vuint32_t BAD_BIT:8;
      } B;
    } STS;
    union {                            /* Flash memory correctable error reporting table address register */
      vuint32_t R;
      struct {
        vuint32_t ERR_ADD:32;
      } B;
    } ADDR;
  } FLASH_CERR[20];

  union {                              /* Flash memory uncorrectable error reporting table status register */
    vuint32_t R;
    struct {
      vuint32_t VLD:1;
      vuint32_t  :31;
    } B;
  } FLASH_UNCERR_STS;

  union {                              /* Flash memory uncorrectable error reporting table address register */
    vuint32_t R;
    struct {
      vuint32_t ERR_ADD:32;
    } B;
  } FLASH_UNCERR_ADDR;

  union {                              /* Flash memory concurrent overflow register */
    vuint32_t R;
    struct {
      vuint32_t OFLW:32;
    } B;
  } FLASH_OFLW0;
};


/* ============================================================================
   =============================== Module: M_CAN ==============================
   ============================================================================ */

struct M_CAN_tag {
  union {                              /* Core Release Register */
    vuint32_t R;
    struct {
      vuint32_t REL:4;
      vuint32_t STEP:4;
      vuint32_t SUBSTEP:4;
      vuint32_t YEAR:4;
      vuint32_t MON:8;
      vuint32_t DAY:8;
    } B;
  } CREL;

  union {                              /* Endian Register */
    vuint32_t R;
    struct {
      vuint32_t ETV:32;
    } B;
  } ENDN;

  uint8_t M_CAN_reserved0[4];
  union {                              /* Fast Bit Timing and Prescaler Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t TDCO:5;                /* Transceiver Delay Compensation Offset */
      vuint32_t TDC:1;                 /* Transceiver Delay Compensation */
      vuint32_t  :2;
      vuint32_t FBRP:5;                /* Fast Baud Rate Prescaler */
      vuint32_t  :4;
      vuint32_t FTSEG1:4;              /* Fast time segment before sample point */
      vuint32_t  :1;
      vuint32_t FTSEG2:3;              /* Fast time segment before sample point */
      vuint32_t  :2;
      vuint32_t FSJW:2;                /* Fast (Re) Synchronization Jump Width */
    } B;
  } FBTP;

  union {                              /* Test Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t TDCV:6;                /* Transceiver Delay Compensation Value */
      vuint32_t RX:1;
      vuint32_t TX:2;
      vuint32_t LBCK:1;
      vuint32_t  :4;
    } B;
  } TEST;

  union {                              /* RAM Watchdog Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t WDV:8;
      vuint32_t WDC:8;
    } B;
  } RWD;

  union {                              /* CC Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t  :1;
      vuint32_t TXP:1;                 /* Transmit Pause */
      vuint32_t FDBS:1;                /* CAN FD Bit Rate Switching */
      vuint32_t FDO:1;                 /* Fast Frame Mode Active */
      vuint32_t CMR:2;                 /* CAN Mode Request */
      vuint32_t CME:2;                 /* CAN Mode Enable */
      vuint32_t TEST:1;
      vuint32_t DAR:1;
      vuint32_t MON:1;
      vuint32_t CSR:1;
      vuint32_t CSA:1;
      vuint32_t ASM:1;
      vuint32_t CCE:1;
      vuint32_t INIT:1;
    } B;
  } CCCR;

  union {                              /* Bit Timing and Prescaler Register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t BRP:10;                /* Baud Rate Prescaler */
      vuint32_t  :2;
      vuint32_t TSEG1:6;
      vuint32_t TSEG2:4;
      vuint32_t SJW:4;
    } B;
  } BTP;

  union {                              /* Timestamp Counter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t TCP:4;
      vuint32_t  :14;
      vuint32_t TSS:2;
    } B;
  } TSCC;

  union {                              /* Timestamp Counter Value Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t TSC:16;                /* Timestamp Counter */
    } B;
  } TSCV;

  union {                              /* Timeout Counter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t TOP:16;
      vuint32_t  :13;
      vuint32_t TOS:2;
      vuint32_t ETOC:1;
    } B;
  } TOCC;

  union {                              /* Timeout Counter Value Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t TOC:16;
    } B;
  } TOCV;

  uint8_t M_CAN_reserved1[16];
  union {                              /* Error Counter Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CEL:8;
      vuint32_t RP:1;
      vuint32_t REC:7;
      vuint32_t TEC:8;
    } B;
  } ECR;

  union {                              /* Protocol Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t REDL:1;                /* Received CAN FD Message with EDL flag */
      vuint32_t RBRS:1;                /* BRS flag of last received CAN FD Message */
      vuint32_t RESI:1;                /* ESI CAN FD Message with ESI flag */
      vuint32_t FLEC:3;                /* Fast Last Error Code */
      vuint32_t BO:1;
      vuint32_t EW:1;
      vuint32_t EP:1;
      vuint32_t ACT:2;
      vuint32_t LEC:3;
    } B;
  } PSR;

  uint8_t M_CAN_reserved2[8];
  union {                              /* Interrupt Register */
    vuint32_t R;
    struct {
      vuint32_t STE:1;
      vuint32_t FOE:1;
      vuint32_t ACKE:1;
      vuint32_t BE:1;
      vuint32_t CRCE:1;
      vuint32_t WDI:1;
      vuint32_t BO:1;
      vuint32_t EW:1;
      vuint32_t EP:1;
      vuint32_t ELO:1;
      vuint32_t BEU:1;
      vuint32_t BEC:1;
      vuint32_t DRX:1;                 /* Message stored to Dedicated Rx Buffer */
      vuint32_t TOO:1;
      vuint32_t MRAF:1;                /* Message RAM Access Failure */
      vuint32_t TSW:1;
      vuint32_t TEFL:1;
      vuint32_t TEFF:1;
      vuint32_t TEFW:1;
      vuint32_t TEFN:1;
      vuint32_t TFE:1;
      vuint32_t TCF:1;
      vuint32_t TC:1;
      vuint32_t HPM:1;
      vuint32_t RF1L:1;
      vuint32_t RF1F:1;
      vuint32_t RF1W:1;
      vuint32_t RF1N:1;
      vuint32_t RF0L:1;
      vuint32_t RF0F:1;
      vuint32_t RF0W:1;
      vuint32_t RF0N:1;
    } B;
  } IR;

  union {                              /* Interrupt Enable Register */
    vuint32_t R;
    struct {
      vuint32_t STEE:1;
      vuint32_t FOEE:1;
      vuint32_t ACKEE:1;
      vuint32_t BEE:1;
      vuint32_t CRCEE:1;
      vuint32_t WDIE:1;
      vuint32_t BOE:1;
      vuint32_t EWE:1;
      vuint32_t EPE:1;
      vuint32_t ELOE:1;
      vuint32_t BEUE:1;
      vuint32_t BECE:1;
      vuint32_t DRXE:1;                /* Message stored to Dedicated Rx Buffer Interrupt Enable */
      vuint32_t TOOE:1;
      vuint32_t MRAFE:1;
      vuint32_t TSWE:1;
      vuint32_t TEFLE:1;
      vuint32_t TEFFE:1;
      vuint32_t TEFWE:1;
      vuint32_t TEFNE:1;
      vuint32_t TFEE:1;
      vuint32_t TCFE:1;
      vuint32_t TCE:1;
      vuint32_t HPME:1;
      vuint32_t RF1LE:1;
      vuint32_t RF1FE:1;
      vuint32_t RF1WE:1;
      vuint32_t RF1NE:1;
      vuint32_t RF0LE:1;
      vuint32_t RF0FE:1;
      vuint32_t RF0WE:1;
      vuint32_t RF0NE:1;
    } B;
  } IE;

  union {                              /* Interrupt Line Select Register */
    vuint32_t R;
    struct {
      vuint32_t STEL:1;
      vuint32_t FOEL:1;
      vuint32_t ACKEL:1;
      vuint32_t BEL:1;
      vuint32_t CRCEL:1;
      vuint32_t WDIL:1;
      vuint32_t BOL:1;
      vuint32_t EWL:1;
      vuint32_t EPL:1;
      vuint32_t ELOL:1;
      vuint32_t BEUL:1;
      vuint32_t BECL:1;
      vuint32_t DRXL:1;                /* Message stored to Dedicated Rx Buffer Interrupt Line */
      vuint32_t TOOL:1;
      vuint32_t MRAFL:1;
      vuint32_t TSWL:1;
      vuint32_t TEFLL:1;
      vuint32_t TEFFL:1;
      vuint32_t TEFWL:1;
      vuint32_t TEFNL:1;
      vuint32_t TFEL:1;
      vuint32_t TCFL:1;
      vuint32_t TCL:1;
      vuint32_t HPML:1;
      vuint32_t RF1LL:1;
      vuint32_t RF1FL:1;
      vuint32_t RF1WL:1;
      vuint32_t RF1NL:1;
      vuint32_t RF0LL:1;
      vuint32_t RF0FL:1;
      vuint32_t RF0WL:1;
      vuint32_t RF0NL:1;
    } B;
  } ILS;

  union {                              /* Interrupt Line Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t EINT1:1;
      vuint32_t EINT0:1;
    } B;
  } ILE;

  uint8_t M_CAN_reserved3[32];
  union {                              /* Global Filter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t ANFS:2;
      vuint32_t ANFE:2;
      vuint32_t RRFS:1;
      vuint32_t RRFE:1;
    } B;
  } GFC;

  union {                              /* Standard ID Filter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t LSS:8;
      vuint32_t FLSSA:14;
      vuint32_t  :2;
    } B;
  } SIDFC;

  union {                              /* Extended ID Filter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :9;
      vuint32_t LSE:7;
      vuint32_t FLESA:14;
      vuint32_t  :2;
    } B;
  } XIDFC;

  uint8_t M_CAN_reserved4[4];
  union {                              /* Extended ID and Mask Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t EIDM:29;
    } B;
  } XIDAM;

  union {                              /* High Priority Message Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t FLST:1;
      vuint32_t FIDX:7;
      vuint32_t MSI:2;
      vuint32_t BIDX:6;
    } B;
  } HPMS;

  union {                              /* New Data 1 Register */
    vuint32_t R;
    struct {
      vuint32_t ND1:32;                /* New Data[0:31] */
    } B;
  } NDAT1;

  union {                              /* New Data 2 Register */
    vuint32_t R;
    struct {
      vuint32_t ND2:32;                /* New Data[32:63] */
    } B;
  } NDAT2;

  union {                              /* Rx FIFO 0 Configuration */
    vuint32_t R;
    struct {
      vuint32_t F0OM:1;                /* FIFO 0 Operation Mode */
      vuint32_t F0WM:7;
      vuint32_t  :2;
      vuint32_t F0S:6;
      vuint32_t F0SA:14;
      vuint32_t  :2;
    } B;
  } RXF0C;

  union {                              /* Rx FIFO 0 Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t RF0L:1;
      vuint32_t F0F:1;
      vuint32_t  :2;
      vuint32_t F0PI:6;                /* Rx FIFO 0 Put Index */
      vuint32_t  :2;
      vuint32_t F0GI:6;
      vuint32_t  :1;
      vuint32_t F0FL:7;
    } B;
  } RXF0S;

  union {                              /* Rx FIFO 0 Acknowledge Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t F0AI:6;
    } B;
  } RXF0A;

  union {                              /* Rx Buffer Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t RBSA:14;               /* Rx Buffer Start Address */
      vuint32_t  :2;
    } B;
  } RXBC;

  union {                              /* Rx FIFO 1 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t F1OM:1;                /* FIFO 1 Operation Mode */
      vuint32_t F1WM:7;
      vuint32_t  :1;
      vuint32_t F1S:7;
      vuint32_t F1SA:14;
      vuint32_t  :2;
    } B;
  } RXF1C;

  union {                              /* Rx FIFO 1 Status Register */
    vuint32_t R;
    struct {
      vuint32_t DMS:2;
      vuint32_t  :4;
      vuint32_t RF1L:1;
      vuint32_t F1F:1;
      vuint32_t  :2;
      vuint32_t F1PI:6;                /* Rx FIFO 1 Put Index */
      vuint32_t  :2;
      vuint32_t F1G1:6;
      vuint32_t  :1;
      vuint32_t F1FL:7;
    } B;
  } RXF1S;

  union {                              /* Rx FIFO 1 Acknowledge Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t F1AI:6;
    } B;
  } RXF1A;

  union {                              /* Rx Buffer / FIFO Element Size Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t RBDS:3;                /* Rx Buffer Data Field Size */
      vuint32_t  :1;
      vuint32_t F1DS:3;                /* Rx FIFO 1 Data Field Size */
      vuint32_t  :1;
      vuint32_t F0DS:3;                /* Rx FIFO 0 Data Field Size */
    } B;
  } RXESC;

  union {                              /* Tx Buffer Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t TQFM:1;
      vuint32_t TQFS:6;
      vuint32_t  :2;
      vuint32_t NDTB:6;
      vuint32_t TBSA:14;
      vuint32_t  :2;
    } B;
  } TXBC;

  union {                              /* Tx FIFO/Queue Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :10;
      vuint32_t TFQF:1;
      vuint32_t TFQPI:5;
      vuint32_t  :3;
      vuint32_t TFGI:5;                /* Tx FIFO Get Index */
      vuint32_t  :2;
      vuint32_t TFFL:6;
    } B;
  } TXFQS;

  union {                              /* Tx Buffer Element Size Configuration */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t TBDS:3;
    } B;
  } TXESC;

  union {                              /* Tx Buffer Request Pending Register */
    vuint32_t R;
    struct {
      vuint32_t TRP:32;                /* Transmission Request Pending */
    } B;
  } TXBRP;

  union {                              /* Tx Buffer Add Request register */
    vuint32_t R;
    struct {
      vuint32_t AR:32;                 /* Add Request */
    } B;
  } TXBAR;

  union {                              /* Tx Buffer Cancellation Request register */
    vuint32_t R;
    struct {
      vuint32_t CR:32;                 /* Cancellation Request */
    } B;
  } TXBCR;

  union {                              /* Tx Buffer Transmission Occurred register */
    vuint32_t R;
    struct {
      vuint32_t TO:32;                 /* Transmission Occurred */
    } B;
  } TXBTO;

  union {                              /* Tx Buffer Cancellation Finished register */
    vuint32_t R;
    struct {
      vuint32_t CF:32;                 /* Cancellation Finished */
    } B;
  } TXBCF;

  union {                              /* Tx Buffer Transmission Interrupt Enable register */
    vuint32_t R;
    struct {
      vuint32_t TIE:32;
    } B;
  } TXBTIE;

  union {                              /* Tx Buffer Cancellation Finished Interrupt Enable register */
    vuint32_t R;
    struct {
      vuint32_t CFIE:32;
    } B;
  } TXBCIE;

  uint8_t M_CAN_reserved5[8];
  union {                              /* Tx Event FIFO Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t EFWM:6;
      vuint32_t  :2;
      vuint32_t EFS:6;
      vuint32_t EFSA:14;
      vuint32_t  :2;
    } B;
  } TXEFC;

  union {                              /* Tx Event FIFO Status register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t TEFL:1;
      vuint32_t EFF:1;
      vuint32_t  :3;
      vuint32_t EFPI:5;
      vuint32_t  :3;
      vuint32_t EFGI:5;
      vuint32_t  :2;
      vuint32_t EFFL:6;
    } B;
  } TXEFS;

  union {                              /* Tx Event FIFO Acknowledge register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t EFAI:5;
    } B;
  } TXEFA;
};


/* ============================================================================
   =============================== Module: M_TTCAN ============================
   ============================================================================ */

struct M_TTCAN_tag {
  union {                              /* Core Release Register */
    vuint32_t R;
    struct {
      vuint32_t REL:4;
      vuint32_t STEP:4;
      vuint32_t SUBSTEP:4;
      vuint32_t YEAR:4;
      vuint32_t MON:8;
      vuint32_t DAY:8;
    } B;
  } CREL;

  union {                              /* Endian Register */
    vuint32_t R;
    struct {
      vuint32_t ETV:32;
    } B;
  } ENDN;

  uint8_t M_TTCAN_reserved0[4];
  union {                              /* Fast Bit Timing and Prescaler Register */
    vuint32_t R;
    struct {
      vuint32_t TDCO:3;                /* Transceiver Delay Compensation Offset */
      vuint32_t TDC:1;                 /* Transceiver Delay Compensation */
      vuint32_t  :1;
      vuint32_t FBRP:12;               /* Fast Baud Rate Prescaler */
      vuint32_t  :3;
      vuint32_t FTSEG1:4;              /* Fast time segment before sample point */
      vuint32_t  :1;
      vuint32_t FTSEG2:3;              /* Fast time segment before sample point */
      vuint32_t  :2;
      vuint32_t FSJW:2;                /* Fast (Re) Synchronization Jump Width */
    } B;
  } FBTP;

  union {                              /* Test Register */
    vuint32_t R;
    struct {
      vuint32_t  :19;
      vuint32_t TDCV:5;                /* Transceiver Delay Compensation Value */
      vuint32_t RX:1;
      vuint32_t TX:2;
      vuint32_t LBCK:1;
      vuint32_t CAT:1;                 /* Check ASC Transmit Control */
      vuint32_t CAM:1;                 /* Check ASC Multiplexer Control */
      vuint32_t TAT:1;                 /* Test ASC Transmit Control */
      vuint32_t TAM:1;                 /* Test ASC Multiplexer Control */
    } B;
  } TEST;

  union {                              /* RAM Watchdog Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t WDV:8;
      vuint32_t WDC:8;
    } B;
  } RWD;

  union {                              /* CC Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t FDBS:1;                /* Long Frame Mode Active */
      vuint32_t FDO:1;                 /* Fast Frame Mode Active */
      vuint32_t CMR:2;                 /* CAN Mode Request */
      vuint32_t CME:2;                 /* CAN Mode Enable */
      vuint32_t TEST:1;
      vuint32_t DAR:1;
      vuint32_t MON:1;
      vuint32_t CSR:1;
      vuint32_t CSA:1;
      vuint32_t ASM:1;                 /* ASM Restricted Operation Mode */
      vuint32_t CCE:1;
      vuint32_t INIT:1;
    } B;
  } CCCR;

  union {                              /* Bit Timing and Prescaler Register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t BRP:10;                /* Baud Rate Prescaler */
      vuint32_t  :2;
      vuint32_t TSEG1:6;
      vuint32_t TSEG2:4;               /* Time segment after sample point */
      vuint32_t SJW:4;                 /* (Re) Synchronization Jump Width */
    } B;
  } BTP;

  union {                              /* Timestamp Counter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t TCP:4;
      vuint32_t  :14;
      vuint32_t TSS:2;
    } B;
  } TSCC;

  union {                              /* Timestamp Counter Value Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t TSC:16;
    } B;
  } TSCV;

  union {                              /* Timeout Counter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t TOP:16;
      vuint32_t  :13;
      vuint32_t TOS:2;
      vuint32_t ETOC:1;
    } B;
  } TOCC;

  union {                              /* Timeout Counter Value Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t TOC:16;
    } B;
  } TOCV;

  uint8_t M_TTCAN_reserved1[16];
  union {                              /* Error Counter Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CEL:8;
      vuint32_t RP:1;
      vuint32_t REC:7;
      vuint32_t TEC:8;
    } B;
  } ECR;

  union {                              /* Protocol Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t REDL:1;                /* Received a CAN FD Message */
      vuint32_t RBRS:1;                /* BRS flag of last received CAN FD Message */
      vuint32_t RESI:1;                /* ESI CAN FD Message with ESI flag */
      vuint32_t FLEC:3;                /* Fast Last Error Code */
      vuint32_t BO:1;
      vuint32_t EW:1;
      vuint32_t EP:1;
      vuint32_t ACT:2;
      vuint32_t LEC:3;
    } B;
  } PSR;

  uint8_t M_TTCAN_reserved2[8];
  union {                              /* Interrupt Register */
    vuint32_t R;
    struct {
      vuint32_t STE:1;
      vuint32_t FOE:1;
      vuint32_t ACKE:1;
      vuint32_t BE:1;
      vuint32_t CRCE:1;
      vuint32_t WDI:1;
      vuint32_t BO:1;
      vuint32_t EW:1;
      vuint32_t EP:1;
      vuint32_t ELO:1;
      vuint32_t BEU:1;
      vuint32_t BEC:1;
      vuint32_t DRX:1;                 /* Message stored to Dedicated Rx Buffer */
      vuint32_t TOO:1;
      vuint32_t UMD:1;
      vuint32_t TSW:1;
      vuint32_t TEFL:1;
      vuint32_t TEFF:1;
      vuint32_t TEFW:1;
      vuint32_t TEFN:1;
      vuint32_t TFE:1;
      vuint32_t TCF:1;
      vuint32_t TC:1;
      vuint32_t HPM:1;
      vuint32_t RF1L:1;
      vuint32_t RF1F:1;
      vuint32_t RF1W:1;
      vuint32_t RF1N:1;
      vuint32_t RF0L:1;
      vuint32_t RF0F:1;
      vuint32_t RF0W:1;
      vuint32_t RF0N:1;
    } B;
  } IR;

  union {                              /* Interrupt Enable Register */
    vuint32_t R;
    struct {
      vuint32_t STEE:1;
      vuint32_t FOEE:1;
      vuint32_t ACKEE:1;
      vuint32_t BEE:1;
      vuint32_t CRCEE:1;
      vuint32_t WDIE:1;
      vuint32_t BOE:1;
      vuint32_t EWE:1;
      vuint32_t EPE:1;
      vuint32_t ELOE:1;
      vuint32_t BEUE:1;
      vuint32_t BECE:1;
      vuint32_t DRXE:1;                /* Message stored to Dedicated Rx Buffer Interrupt Enable */
      vuint32_t TOOE:1;
      vuint32_t UMDE:1;
      vuint32_t TSWE:1;
      vuint32_t TEFLE:1;
      vuint32_t TEFFE:1;
      vuint32_t TEFWE:1;
      vuint32_t TEFNE:1;
      vuint32_t TFEE:1;
      vuint32_t TCFE:1;
      vuint32_t TCE:1;
      vuint32_t HPME:1;
      vuint32_t RF1LE:1;
      vuint32_t RF1FE:1;
      vuint32_t RF1WE:1;
      vuint32_t RF1NE:1;
      vuint32_t RF0LE:1;
      vuint32_t RF0FE:1;
      vuint32_t RF0WE:1;
      vuint32_t RF0NE:1;
    } B;
  } IE;

  union {                              /* Interrupt Line Select Register */
    vuint32_t R;
    struct {
      vuint32_t STEL:1;
      vuint32_t FOEL:1;
      vuint32_t ACKEL:1;
      vuint32_t BEL:1;
      vuint32_t CRCEL:1;
      vuint32_t WDIL:1;
      vuint32_t BOL:1;
      vuint32_t EWL:1;
      vuint32_t EPL:1;
      vuint32_t ELOL:1;
      vuint32_t BEUL:1;
      vuint32_t BECL:1;
      vuint32_t DRXL:1;                /* Message stored to Dedicated Rx Buffer Interrupt Line */
      vuint32_t TOOL:1;
      vuint32_t UMDL:1;
      vuint32_t TSWL:1;
      vuint32_t TEFLL:1;
      vuint32_t TEFFL:1;
      vuint32_t TEFWL:1;
      vuint32_t TEFNL:1;
      vuint32_t TFEL:1;
      vuint32_t TCFL:1;
      vuint32_t TCL:1;
      vuint32_t HPML:1;
      vuint32_t RF1LL:1;
      vuint32_t RF1FL:1;
      vuint32_t RF1WL:1;
      vuint32_t RF1NL:1;
      vuint32_t RF0LL:1;
      vuint32_t RF0FL:1;
      vuint32_t RF0WL:1;
      vuint32_t RF0NL:1;
    } B;
  } ILS;

  union {                              /* Interrupt Line Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t EINT1:1;
      vuint32_t EINT0:1;
    } B;
  } ILE;

  uint8_t M_TTCAN_reserved3[32];
  union {                              /* Global Filter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t ANFS:2;
      vuint32_t ANFE:2;
      vuint32_t RRFS:1;
      vuint32_t RRFE:1;
    } B;
  } GFC;

  union {                              /* Standard ID Filter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t LSS:8;
      vuint32_t FLSSA:14;
      vuint32_t  :2;
    } B;
  } SIDFC;

  union {                              /* Extended ID Filter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :9;
      vuint32_t LSE:7;
      vuint32_t FLESA:14;
      vuint32_t  :2;
    } B;
  } XIDFC;

  uint8_t M_TTCAN_reserved4[4];
  union {                              /* Extended ID and Mask Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t EIDM:29;
    } B;
  } XIDAM;

  union {                              /* High Priority Message Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t FLST:1;
      vuint32_t FIDX:7;
      vuint32_t MSI:2;
      vuint32_t BIDX:6;
    } B;
  } HPMS;

  union {                              /* New Data 1 Register */
    vuint32_t R;
    struct {
      vuint32_t ND1:32;                /* New Data[0:31] */
    } B;
  } NDAT1;

  union {                              /* New Data 2 Register */
    vuint32_t R;
    struct {
      vuint32_t ND2:32;                /* New Data[63:32] */
    } B;
  } NDAT2;

  union {                              /* Rx FIFO 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t F0WM:7;
      vuint32_t  :1;
      vuint32_t F0S:7;
      vuint32_t FOSA:14;
      vuint32_t  :2;
    } B;
  } RXF0C;

  union {                              /* Rx FIFO 0 Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t RF0L:1;
      vuint32_t F0F:1;
      vuint32_t  :2;
      vuint32_t F0PI:6;
      vuint32_t  :2;
      vuint32_t F0GI:6;
      vuint32_t  :1;
      vuint32_t F0FL:7;
    } B;
  } RXF0S;

  union {                              /* Rx FIFO 0 Acknowledge Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t F0AI:6;
    } B;
  } RXF0A;

  union {                              /* Rx Buffer Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t RBSA:14;               /* Rx Buffer Start Address */
      vuint32_t  :2;
    } B;
  } RXBC;

  union {                              /* Rx FIFO 1 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t F1WM:7;
      vuint32_t  :1;
      vuint32_t F1S:7;
      vuint32_t F1SA:14;
      vuint32_t  :2;
    } B;
  } RXF1C;

  union {                              /* Rx FIFO 1 Status Register */
    vuint32_t R;
    struct {
      vuint32_t DMS:2;                 /* Debug Message Status */
      vuint32_t  :4;
      vuint32_t RF1L:1;
      vuint32_t F1F:1;
      vuint32_t  :2;
      vuint32_t F1PI:6;
      vuint32_t  :2;
      vuint32_t F1GI:6;
      vuint32_t  :1;
      vuint32_t F1FL:7;
    } B;
  } RXF1S;

  union {                              /* Rx FIFO 1 Acknowledge register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t F1A1:6;
    } B;
  } RXF1A;

  uint8_t M_TTCAN_reserved5[4];
  union {                              /* Tx Buffer Configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t TFQM:1;
      vuint32_t TFQS:6;
      vuint32_t  :2;
      vuint32_t NDTB:6;
      vuint32_t TBSA:14;
      vuint32_t  :2;
    } B;
  } TXBC;

  union {                              /* Tx FIFO/Queue Status register */
    vuint32_t R;
    struct {
      vuint32_t  :10;
      vuint32_t TFQF:1;
      vuint32_t TFQPI:5;
      vuint32_t  :3;
      vuint32_t TFGI:5;
      vuint32_t  :2;
      vuint32_t TFFL:6;
    } B;
  } TXFQS;

  uint8_t M_TTCAN_reserved6[4];
  union {                              /* Tx Buffer Request Pending register */
    vuint32_t R;
    struct {
      vuint32_t TRP:32;
    } B;
  } TXBRP;

  union {                              /* Tx Buffer Add Request register */
    vuint32_t R;
    struct {
      vuint32_t AR:32;
    } B;
  } TXBAR;

  union {                              /* Tx Buffer Cancellation Request register */
    vuint32_t R;
    struct {
      vuint32_t CR:32;
    } B;
  } TXBCR;

  union {                              /* Tx Buffer Transmission Occurred register */
    vuint32_t R;
    struct {
      vuint32_t TO:32;
    } B;
  } TXBTO;

  union {                              /* Tx Buffer Cancellation Finished register */
    vuint32_t R;
    struct {
      vuint32_t CF:32;
    } B;
  } TXBCF;

  union {                              /* Tx Buffer Transmission Interrupt Enable register */
    vuint32_t R;
    struct {
      vuint32_t TIE:32;
    } B;
  } TXBTIE;

  union {                              /* Tx Buffer Cancellation Finished Interrupt Enable register */
    vuint32_t R;
    struct {
      vuint32_t CFIE:32;
    } B;
  } TXBCIE;

  uint8_t M_TTCAN_reserved7[8];
  union {                              /* Tx Event FIFO Configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t EFWM:6;
      vuint32_t  :2;
      vuint32_t EFS:6;
      vuint32_t EFSA:14;
      vuint32_t  :2;
    } B;
  } TXEFC;

  union {                              /* Tx Event FIFO Status register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t TEFL:1;
      vuint32_t EFF:1;
      vuint32_t  :3;
      vuint32_t EFPI:5;
      vuint32_t  :3;
      vuint32_t EFGI:5;
      vuint32_t  :2;
      vuint32_t EFFL:6;
    } B;
  } TXEFS;

  union {                              /* Tx Event FIFO Acknowledge register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t EFAI:5;
    } B;
  } TXEFA;

  uint8_t M_TTCAN_reserved8[4];
  union {                              /* TT Trigger Memory Configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :9;
      vuint32_t TME:7;
      vuint32_t TMSA:14;
      vuint32_t  :2;
    } B;
  } TTTMC;

  union {                              /* TT Reference Message Configuration register */
    vuint32_t R;
    struct {
      vuint32_t RMPS:1;
      vuint32_t XTD:1;
      vuint32_t  :1;
      vuint32_t RID:29;
    } B;
  } TTRMC;

  union {                              /* TT Operation Configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t EVTP:1;
      vuint32_t ECC:1;
      vuint32_t EGTF:1;
      vuint32_t AWL:8;
      vuint32_t EECS:1;
      vuint32_t IRTO:7;
      vuint32_t LDSDL:3;
      vuint32_t TM:1;
      vuint32_t GEN:1;
      vuint32_t  :1;
      vuint32_t OM:2;
    } B;
  } TTOCF;

  union {                              /* TT Matrix Limits register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t ENTT:12;
      vuint32_t  :4;
      vuint32_t TXEW:4;
      vuint32_t CSS:2;                 /* Cycle Start Synchronization */
      vuint32_t CCM:6;
    } B;
  } TTMLM;

  union {                              /* TUR Configuration register */
    vuint32_t R;
    struct {
      vuint32_t ELT:1;
      vuint32_t  :1;
      vuint32_t DC:14;
      vuint32_t NCL:16;
    } B;
  } TURCF;

  union {                              /* TT Operation Control register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t LCKC:1;
      vuint32_t  :1;
      vuint32_t ESCN:1;
      vuint32_t NIG:1;
      vuint32_t TMG:1;
      vuint32_t FGP:1;
      vuint32_t GCS:1;
      vuint32_t TTIE:1;                /* Trigger Time Mark Interrupt Pulse Enable */
      vuint32_t TMC:2;
      vuint32_t RTIE:1;
      vuint32_t SWS:2;
      vuint32_t SWP:1;
      vuint32_t ECS:1;
      vuint32_t SGT:1;
    } B;
  } TTOCN;

  union {                              /* TT Global Time Preset register */
    vuint32_t R;
    struct {
      vuint32_t CTP:16;
      vuint32_t TP:16;
    } B;
  } TTGTP;

  union {                              /* TT Time Mark register */
    vuint32_t R;
    struct {
      vuint32_t LCKM:1;
      vuint32_t  :8;
      vuint32_t TICC:7;
      vuint32_t TM:16;
    } B;
  } TTTMK;

  union {                              /* TT Interrupt Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t CER:1;
      vuint32_t AW:1;
      vuint32_t WT:1;
      vuint32_t IWT:1;
      vuint32_t ELC:1;
      vuint32_t SE2:1;
      vuint32_t SE1:1;
      vuint32_t TXO:1;
      vuint32_t TXU:1;
      vuint32_t GTE:1;
      vuint32_t GTD:1;
      vuint32_t GTW:1;
      vuint32_t SWE:1;
      vuint32_t TTMI:1;
      vuint32_t RTMI:1;
      vuint32_t SOG:1;
      vuint32_t CSM:1;
      vuint32_t SMC:1;
      vuint32_t SBC:1;
    } B;
  } TTIR;

  union {                              /* TT Interrupt Enable register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t CERE:1;
      vuint32_t AWE:1;
      vuint32_t WTE:1;
      vuint32_t IWTE:1;
      vuint32_t ELCE:1;
      vuint32_t SE2E:1;
      vuint32_t SE1E:1;
      vuint32_t TXOE:1;
      vuint32_t TXUE:1;
      vuint32_t GTEE:1;
      vuint32_t GTDE:1;
      vuint32_t GTWE:1;
      vuint32_t SWEE:1;
      vuint32_t TTMIE:1;
      vuint32_t RTMIE:1;
      vuint32_t SOGE:1;
      vuint32_t CSME:1;
      vuint32_t SMCE:1;
      vuint32_t SBCE:1;
    } B;
  } TTIE;

  union {                              /* TT Interrupt Line Select register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t CERL:1;
      vuint32_t AWL:1;
      vuint32_t WTL:1;
      vuint32_t IWTL:1;
      vuint32_t ELCL:1;
      vuint32_t SE2L:1;
      vuint32_t SE1L:1;
      vuint32_t TXOL:1;
      vuint32_t TXUL:1;
      vuint32_t GTEL:1;
      vuint32_t GTDL:1;
      vuint32_t GTWE:1;
      vuint32_t SWEL:1;
      vuint32_t TTMIL:1;
      vuint32_t RTMIL:1;
      vuint32_t SOGL:1;
      vuint32_t CSML:1;
      vuint32_t SMCL:1;
      vuint32_t SBCL:1;
    } B;
  } TTILS;

  union {                              /* TT Operation Status register */
    vuint32_t R;
    struct {
      vuint32_t SPL:1;
      vuint32_t WECS:1;
      vuint32_t AWE:1;
      vuint32_t WFE:1;
      vuint32_t GSI:1;
      vuint32_t TMP:3;
      vuint32_t GFI:1;
      vuint32_t WGTD:1;
      vuint32_t  :6;
      vuint32_t RTO:8;
      vuint32_t QCS:1;
      vuint32_t QGTP:1;
      vuint32_t SYS:2;
      vuint32_t MS:2;
      vuint32_t EL:2;
    } B;
  } TTOST;

  union {                              /* TUR Numerator Actual register */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t NAV:18;
    } B;
  } TURNA;

  union {                              /* TT Local and Global Time register */
    vuint32_t R;
    struct {
      vuint32_t GT:16;
      vuint32_t LT:16;
    } B;
  } TTLGT;

  union {                              /* TT Cycle Time and Count register */
    vuint32_t R;
    struct {
      vuint32_t  :10;
      vuint32_t CC:6;
      vuint32_t CT:16;
    } B;
  } TTCTC;

  union {                              /* TT Capture Time register */
    vuint32_t R;
    struct {
      vuint32_t SWV:16;
      vuint32_t  :10;
      vuint32_t CCV:6;
    } B;
  } TTCPT;

  union {                              /* TT Cycle Sync Mark register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CSM:16;
    } B;
  } TTCSM;
};


/* ============================================================================
   =============================== Module: PASS ===============================
   ============================================================================ */

struct PASS_tag {
  union {                              /* Life Cycle Status Register */
    vuint32_t R;
    struct {
      vuint32_t CNS:1;
      vuint32_t JUN:1;
      vuint32_t FBE:1;
      vuint32_t  :26;
      vuint32_t LIFE:3;
    } B;
  } LCSTAT;

  uint8_t PASS_reserved0[4];
  union {                              /* Challenge Selector Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t GRP:2;
    } B;
  } CHSEL;

  uint8_t PASS_reserved1[4];
  union {                              /* Challenge Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t CMST:4;
    } B;
  } CSTAT;

  uint8_t PASS_reserved2[12];
  union {                              /* Challenge Input Register */
    vuint32_t R;
    struct {
      vuint32_t PW32:32;
    } B;
  } CIN[8];

  uint8_t PASS_reserved3[144];
  union {                              /* Clock Jitter Enable */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t CJE:1;
    } B;
  } CJE;

  uint8_t PASS_reserved4[44];
  struct {
    union {                            /* Password Group n - Lock 0 Status Register */
      vuint32_t R;
      struct {
        vuint32_t TSLOCK:1;
        vuint32_t ATSL:1;
        vuint32_t LOWLOCK:14;
        vuint32_t MIDLOCK:16;
      } B;
    } LOCK0;
    union {                            /* Password Group n - Lock 1 Status Register */
      vuint32_t R;
      struct {
        vuint32_t  :16;
        vuint32_t HIGHLOCK:16;
      } B;
    } LOCK1;
    union {                            /* Password Group n - Lock 2 Status Register */
      vuint32_t R;
      struct {
        vuint32_t L_256LCK:32;
      } B;
    } LOCK2;
    union {                            /* Password Group n - Lock 3 Status Register */
      vuint32_t R;
      struct {
        vuint32_t PGL:1;
        vuint32_t DBL:1;
        vuint32_t MO:1;
        vuint32_t  :1;
        vuint32_t MSTR:4;
        vuint32_t  :3;
        vuint32_t RL4:1;
        vuint32_t RL3:1;
        vuint32_t RL2:1;
        vuint32_t RL1:1;
        vuint32_t RL0:1;
        vuint32_t U_256LCK:16;
      } B;
    } LOCK3;
  } PG[4];
};


/* ============================================================================
   =============================== Module: PBRIDGE ============================
   ============================================================================ */

struct PBRIDGE_tag {
  union {                              /* Master Privilege Register A */
    vuint32_t R;
    struct {
      vuint32_t MPROT0:4;
      vuint32_t MPROT1:4;
      vuint32_t MPROT2:4;
      vuint32_t MPROT3:4;
      vuint32_t MPROT4:4;
      vuint32_t MPROT5:4;
      vuint32_t MPROT6:4;
      vuint32_t MPROT7:4;
    } B;
  } MPRA;

  union {                              /* Master Privilege Register B */
    vuint32_t R;
    struct {
      vuint32_t MPROT8:4;
      vuint32_t MPROT9:4;
      vuint32_t MPROT10:4;
      vuint32_t MPROT11:4;
      vuint32_t MPROT12:4;
      vuint32_t MPROT13:4;
      vuint32_t MPROT14:4;
      vuint32_t MPROT15:4;
    } B;
  } MPRB;

  uint8_t PBRIDGE_reserved0[248];
  union {                              /* Peripheral Access Control Register */
    vuint32_t R;
    struct {
      vuint32_t PACRa:4;
      vuint32_t PACRb:4;
      vuint32_t PACRc:4;
      vuint32_t PACRd:4;
      vuint32_t PACRe:4;
      vuint32_t PACRf:4;
      vuint32_t PACRg:4;
      vuint32_t PACRh:4;
    } B;
  } PACR[8];

  uint8_t PBRIDGE_reserved1[32];
  union {                              /* Off-platform Peripheral Access Control Register */
    vuint32_t R;
    struct {
      vuint32_t OPACRa:4;
      vuint32_t OPACRb:4;
      vuint32_t OPACRc:4;
      vuint32_t OPACRd:4;
      vuint32_t OPACRe:4;
      vuint32_t OPACRf:4;
      vuint32_t OPACRg:4;
      vuint32_t OPACRh:4;
    } B;
  } OPACR[32];
};


/* ============================================================================
   =============================== Module: PCM ================================
   ============================================================================ */

struct PCM_tag {
  union {                              /* FEC Burst Optimization Master Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t ACCERR:1;
      vuint32_t WBEN:1;
      vuint32_t RBEN:1;
      vuint32_t FXSBE:8;
    } B;
  } FBOMCR;

  union {                              /* IAHB Burst Enable 1 Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t RSV:3;
      vuint32_t  :5;
      vuint32_t PRE_DMA:1;
      vuint32_t BRE_DMA:1;
      vuint32_t BWE_DMA:1;
      vuint32_t  :5;
      vuint32_t PRE_S0:1;
      vuint32_t BRE_S0:1;
      vuint32_t BWE_S0:1;
      vuint32_t  :5;
      vuint32_t PRE_M3:1;
      vuint32_t BRE_M3:1;
      vuint32_t BWE_M3:1;
    } B;
  } IAHB_BE1;

  union {                              /* IAHB Burst Enable 2 Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t RSV:3;
      vuint32_t  :5;
      vuint32_t PRE_SIPI:1;
      vuint32_t BRE_SIPI:1;
      vuint32_t BWE_SIPI:1;
      vuint32_t  :5;
      vuint32_t PRE_FlexRay:1;
      vuint32_t BRE_FlexRay:1;
      vuint32_t BWE_FlexRay:1;
      vuint32_t  :5;
      vuint32_t PRE_FEC:1;
      vuint32_t BRE_FEC:1;
      vuint32_t BWE_FEC:1;
    } B;
  } IAHB_BE2;
};


/* ============================================================================
   =============================== Module: PFLASH =============================
   ============================================================================ */

struct PFLASH_tag {
  union {                              /* Platform Flash Configuration Register 1 */
    vuint32_t R;
    struct {
      vuint32_t P0_M15PFE:1;
      vuint32_t P0_M14PFE:1;
      vuint32_t P0_M13PFE:1;
      vuint32_t P0_M12PFE:1;
      vuint32_t P0_M11PFE:1;
      vuint32_t P0_M10PFE:1;
      vuint32_t P0_M9PFE:1;
      vuint32_t P0_M8PFE:1;
      vuint32_t P0_M7PFE:1;
      vuint32_t P0_M6PFE:1;
      vuint32_t P0_M5PFE:1;
      vuint32_t P0_M4PFE:1;
      vuint32_t P0_M3PFE:1;
      vuint32_t P0_M2PFE:1;
      vuint32_t P0_M1PFE:1;
      vuint32_t P0_M0PFE:1;
      vuint32_t APC:3;
      vuint32_t RWSC:5;
      vuint32_t  :1;
      vuint32_t P0_DPFEN:1;
      vuint32_t  :1;
      vuint32_t P0_IPFEN:1;
      vuint32_t  :1;
      vuint32_t P0_PFLIM:2;
      vuint32_t P0_BFEN:1;
    } B;
  } PFCR1;

  union {                              /* Platform Flash Configuration Register 2 */
    vuint32_t R;
    struct {
      vuint32_t P1_M15PFE:1;
      vuint32_t P1_M14PFE:1;
      vuint32_t P1_M13PFE:1;
      vuint32_t P1_M12PFE:1;
      vuint32_t P1_M11PFE:1;
      vuint32_t P1_M10PFE:1;
      vuint32_t P1_M9PFE:1;
      vuint32_t P1_M8PFE:1;
      vuint32_t P1_M7PFE:1;
      vuint32_t P1_M6PFE:1;
      vuint32_t P1_M5PFE:1;
      vuint32_t P1_M4PFE:1;
      vuint32_t P1_M3PFE:1;
      vuint32_t P1_M2PFE:1;
      vuint32_t P1_M1PFE:1;
      vuint32_t P1_M0PFE:1;
      vuint32_t  :9;
      vuint32_t P1_DPFEN:1;
      vuint32_t  :1;
      vuint32_t P1_IPFEN:1;
      vuint32_t  :1;
      vuint32_t P1_PFLIM:2;
      vuint32_t P1_BFEN:1;
    } B;
  } PFCR2;

  union {                              /* Platform Flash Configuration Register 3 */
    vuint32_t R;
    struct {
      vuint32_t P0_WCFG:2;
      vuint32_t P1_WCFG:2;
      vuint32_t  :2;
      vuint32_t  :5;
      vuint32_t BDRM:1;
      vuint32_t  :3;
      vuint32_t BAF_DIS:1;
      vuint32_t ARBM:2;
      vuint32_t  :2;
      vuint32_t  :11;
      vuint32_t  :1;
    } B;
  } PFCR3;

  union {                              /* Platform Flash Access Protection Register */
    vuint32_t R;
    struct {
      vuint32_t M0AP:2;
      vuint32_t M1AP:2;
      vuint32_t M2AP:2;
      vuint32_t M3AP:2;
      vuint32_t M4AP:2;
      vuint32_t M5AP:2;
      vuint32_t M6AP:2;
      vuint32_t M7AP:2;
      vuint32_t M8AP:2;
      vuint32_t M9AP:2;
      vuint32_t M10AP:2;
      vuint32_t M11AP:2;
      vuint32_t M12AP:2;
      vuint32_t M13AP:2;
      vuint32_t M14AP:2;
      vuint32_t M15AP:2;
    } B;
  } PFAPR;

  union {                              /* Platform Flash Remap Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t SAFE_CAL:1;
      vuint32_t  :3;
      vuint32_t IRMEN:1;
      vuint32_t  :3;
      vuint32_t GRMEN:1;
    } B;
  } PFCRCR;

  union {                              /* Platform Flash Remap Descriptor Enable Register */
    vuint32_t R;
    struct {
      vuint32_t CRD0EN:1;
      vuint32_t CRD1EN:1;
      vuint32_t CRD2EN:1;
      vuint32_t CRD3EN:1;
      vuint32_t CRD4EN:1;
      vuint32_t CRD5EN:1;
      vuint32_t CRD6EN:1;
      vuint32_t CRD7EN:1;
      vuint32_t CRD8EN:1;
      vuint32_t CRD9EN:1;
      vuint32_t CRD10EN:1;
      vuint32_t CRD11EN:1;
      vuint32_t CRD12EN:1;
      vuint32_t CRD13EN:1;
      vuint32_t CRD14EN:1;
      vuint32_t CRD15EN:1;
      vuint32_t CRD16EN:1;
      vuint32_t CRD17EN:1;
      vuint32_t CRD18EN:1;
      vuint32_t CRD19EN:1;
      vuint32_t CRD20EN:1;
      vuint32_t CRD21EN:1;
      vuint32_t CRD22EN:1;
      vuint32_t CRD23EN:1;
      vuint32_t CRD24EN:1;
      vuint32_t CRD25EN:1;
      vuint32_t CRD26EN:1;
      vuint32_t CRD27EN:1;
      vuint32_t CRD28EN:1;
      vuint32_t CRD29EN:1;
      vuint32_t CRD30EN:1;
      vuint32_t CRD31EN:1;
    } B;
  } PFCRDE;

  uint8_t PFLASH_reserved0[232];
  struct {
    union {                            /* Platform Flash Calibration Region Descriptor n Word0 */
      vuint32_t R;
      struct {
        vuint32_t LSTARTADDR:32;
      } B;
    } Word0;
    union {                            /* Platform Flash Calibration Region Descriptor n Word1 */
      vuint32_t R;
      struct {
        vuint32_t PSTARTADDR:32;
      } B;
    } Word1;
    union {                            /* Platform Flash Calibration Region Descriptor n Word2 */
      vuint32_t R;
      struct {
        vuint32_t M0EN:1;
        vuint32_t M1EN:1;
        vuint32_t M2EN:1;
        vuint32_t M3EN:1;
        vuint32_t M4EN:1;
        vuint32_t M5EN:1;
        vuint32_t M6EN:1;
        vuint32_t M7EN:1;
        vuint32_t M8EN:1;
        vuint32_t M9EN:1;
        vuint32_t M10EN:1;
        vuint32_t M11EN:1;
        vuint32_t M12EN:1;
        vuint32_t M13EN:1;
        vuint32_t M14EN:1;
        vuint32_t M15EN:1;
        vuint32_t  :11;
        vuint32_t CRDSize:5;
      } B;
    } Word2;
    uint8_t PFCRD_reserved0[4];
  } PFCRD[32];
};


/* ============================================================================
   =============================== Module: PIT ================================
   ============================================================================ */

struct PIT_tag {
  union {                              /* PIT Module Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MDIS_RTI:1;
      vuint32_t MDIS:1;
      vuint32_t FRZ:1;
    } B;
  } MCR;

  uint8_t PIT_reserved0[220];
  union {                              /* PIT Upper Lifetime Timer Register */
    vuint32_t R;
    struct {
      vuint32_t LTH:32;
    } B;
  } LTMR64H;

  union {                              /* PIT Lower Lifetime Timer Register */
    vuint32_t R;
    struct {
      vuint32_t LTL:32;
    } B;
  } LTMR64L;

  uint8_t PIT_reserved1[8];
  union {                              /* PIT RTI Timer Load Value Register */
    vuint32_t R;
    struct {
      vuint32_t TSV:32;
    } B;
  } RTI_LDVAL;

  union {                              /* PIT RTI Current Timer Value Register */
    vuint32_t R;
    struct {
      vuint32_t TVL:32;
    } B;
  } RTI_CVAL;

  union {                              /* PIT RTI Timer Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t CHN:1;
      vuint32_t TIE:1;
      vuint32_t TEN:1;
    } B;
  } RTI_TCTRL;

  union {                              /* PIT RTI Timer Flag Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t TIF:1;
    } B;
  } RTI_TFLG;

  struct {
    union {                            /* PIT Timer Load Value Register n */
      vuint32_t R;
      struct {
        vuint32_t TSV:32;
      } B;
    } LDVAL;
    union {                            /* PIT Current Timer Value Register n */
      vuint32_t R;
      struct {
        vuint32_t TVL:32;
      } B;
    } CVAL;
    union {                            /* PIT Timer Control Register n */
      vuint32_t R;
      struct {
        vuint32_t  :29;
        vuint32_t CHN:1;
        vuint32_t TIE:1;
        vuint32_t TEN:1;
      } B;
    } TCTRL;
    union {                            /* PIT Timer Flag Register n */
      vuint32_t R;
      struct {
        vuint32_t  :31;
        vuint32_t TIF:1;
      } B;
    } TFLG;
  } TIMER[8];
};


/* ============================================================================
   =============================== Module: PLLDIG =============================
   ============================================================================ */

struct PLLDIG_tag {
  union {                              /* PLLDIG PLL0 Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t  :1;
      vuint32_t CLKCFG:2;              /* Clock Configuration */
      vuint32_t EXPDIE:1;              /* External Power Down Cycle Complete indication interrupt enable. */
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t LOLIE:1;               /* Loss-of-lock interrupt enable. */
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t  :1;
    } B;
  } PLL0CR;

  union {                              /* PLLDIG PLL0 Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t EXTPDF:1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t LOLF:1;                /* Loss-of-lock flag. */
      vuint32_t LOCK:1;
      vuint32_t  :1;
      vuint32_t  :1;
    } B;
  } PLL0SR;

  union {                              /* PLLDIG PLL0 Divider Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t RFDPHI1:4;             /* PHI1 reduced frequency divider. */
      vuint32_t  :5;
      vuint32_t RFDPHI:6;              /* PHI reduced frequency divider. */
      vuint32_t  :1;
      vuint32_t PREDIV:3;              /* Input clock predivider. */
      vuint32_t  :5;
      vuint32_t MFD:7;                 /* Loop multiplication factor divider. */
    } B;
  } PLL0DV;

  uint8_t PLLDIG_reserved0[20];
  union {                              /* PLLDIG PLL1 Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t  :1;
      vuint32_t CLKCFG:2;              /* Clock Configuration */
      vuint32_t EXPDIE:1;              /* External Power Down Cycle Complete indication interrupt enable. */
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t LOLIE:1;               /* Loss-of-lock interrupt enable. */
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t  :1;
    } B;
  } PLL1CR;

  union {                              /* PLLDIG PLL1 Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t EXTPDF:1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t LOLF:1;                /* Loss-of-lock flag. */
      vuint32_t LOCK:1;
      vuint32_t  :1;
      vuint32_t  :1;
    } B;
  } PLL1SR;

  union {                              /* PLLDIG PLL1 Divider Register */
    vuint32_t R;
    struct {
      vuint32_t  :10;
      vuint32_t RFDPHI:6;              /* PHI reduced frequency divider. */
      vuint32_t  :5;
      vuint32_t  :4;
      vuint32_t MFD:7;                 /* Loop multiplication factor divider. */
    } B;
  } PLL1DV;

  union {                              /* PLLDIG PLL1 Frequency Modulation Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t MODEN:1;               /* Modulation enable. */
      vuint32_t MODSEL:1;              /* Modulation selection. */
      vuint32_t MODPRD:13;             /* Modulation period. */
      vuint32_t  :1;
      vuint32_t INCSTP:15;             /* Increment step. */
    } B;
  } PLL1FM;

  union {                              /* PLLDIG PLL1 Fractional Divide Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t FDEN:1;                /* Fractional Divide Enable */
      vuint32_t  :12;
      vuint32_t DTHDIS:2;              /* Dither Disable. */
      vuint32_t  :4;
      vuint32_t FRCDIV:12;
    } B;
  } PLL1FD;
};


/* ============================================================================
   =============================== Module: PMCDIG =============================
   ============================================================================ */

struct PMCDIG_tag {
  union {                              /* Supply Gauge Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;                   /* Reserved. */
      vuint32_t TS3:1;                 /* TS3 over temperature detect flag. */
      vuint32_t TS2:1;                 /* TS2 over temperature detect flag. */
      vuint32_t TS0:1;                 /* TS0 under temperature detect flag. */
      vuint32_t  :8;
      vuint32_t VD15:1;                /* VD15 high-voltage detect flag. */
      vuint32_t VD14:1;                /* VD14 low-voltage detect flag. */
      vuint32_t VD13:1;                /* VD13 low-voltage detect flag. */
      vuint32_t VD12:1;                /* VD12 high-voltage detect flag. */
      vuint32_t  :1;
      vuint32_t VD10:1;                /* HVD occurrence detected on the high voltage 3.60 V supply. */
      vuint32_t VD9:1;                 /* VD9 low-voltage detect flag. */
      vuint32_t VD8:1;                 /* VD8 high-voltage detect flag. */
      vuint32_t VD7:1;                 /* VD7 high-voltage detect flag. */
      vuint32_t  :2;
      vuint32_t VD4:1;                 /* VD4 low-voltage detect flag. */
      vuint32_t VD3:1;                 /* VD3 low-voltage detect flag. */
      vuint32_t  :3;                   /* Reserved */
    } B;
  } GR_S;

  union {                              /* Pending Gauge Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t VD15_A:1;              /* VD15_A high-voltage detect flag. */
      vuint32_t VD15_C:1;              /* VD15_C high-voltage detect flag. */
      vuint32_t  :1;
      vuint32_t VD14_A:1;              /* VD14_A low-voltage detect flag. */
      vuint32_t VD14_IM:1;             /* VD14_IM low-voltage detect flag. */
      vuint32_t  :2;
      vuint32_t VD13_IM:1;             /* VD13_IM low-voltage detect flag. */
      vuint32_t VD12_F:1;              /* VD12_F high-voltage detect flag. */
      vuint32_t VD10_A:1;              /* VD10_A low-voltage detect flag. */
      vuint32_t VD10_F:1;              /* VD10_F low-voltage detect flag. */
      vuint32_t VD9_O:1;               /* VD9_O low-voltage detect flag. */
      vuint32_t VD9_IF2:1;             /* VD9_IF2 low-voltage detect flag. */
      vuint32_t VD9_IF:1;              /* VD9_IF low-voltage detect flag. */
      vuint32_t VD9_IJ:1;              /* VD9_IJ low-voltage detect flag. */
      vuint32_t VD9_IM:1;              /* VD9_IM low-voltage detect flag. */
      vuint32_t VD9_F:1;               /* VD9_F low-voltage detect flag. */
      vuint32_t VD9_EBI:1;             /* VD9_EBI low-voltage detect flag. */
      vuint32_t VD9_C:1;               /* VD9_C low-voltage detect flag. */
      vuint32_t VD8_C:1;               /* VD8_C high-voltage detect flag. */
      vuint32_t VD8_F:1;               /* VD8_F high-voltage detect flag. */
      vuint32_t VD7_C:1;               /* VD7_C high-voltage detect flag. */
      vuint32_t VD4_C:1;               /* VD4_C low-voltage detect flag. */
      vuint32_t VD3_P:1;               /* VD3_P low-voltage detect flag. */
      vuint32_t VD3_F:1;               /* VD3_F low-voltage detect flag. */
      vuint32_t VD3_C:1;               /* VD3_C low-voltage detect flag. */
    } B;
  } GR_P;

  union {                              /* Interrupt Enable Pending Register */
    vuint32_t R;
    struct {
      vuint32_t IE_EN:1;
      vuint32_t  :5;
      vuint32_t VD15IE_A:1;            /* VD15IE_A Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD15IE_C:1;            /* VD15IE_C Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t  :1;
      vuint32_t VD14IE_A:1;            /* VD14IE_A Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD14IE_IM:1;           /* VD14IE_IM Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t  :2;
      vuint32_t VD13IE_IM:1;           /* VD13IE_IM Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD12IE_F:1;            /* VD12IE_F Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD10IE_A:1;            /* VD10IE_F Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD10IE_F:1;            /* VD10IE_A Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD9IE_O:1;             /* VD9IE_O Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD9IE_IF2:1;           /* VD9IE_IF2 Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD9IE_IF:1;            /* VD9IE_IF Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD9IE_IJ:1;            /* VD9IE_IJ Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD9IE_IM:1;            /* VD9IE_IM Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD9IE_F:1;             /* VD9IE_F Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD9IE_EBI:1;           /* VD9IE_EBI Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD9IE_C:1;             /* VD9IE_C Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD8IE_C:1;             /* VD8IE_C Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD8IE_F:1;             /* VD8IE_F Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD7IE_C:1;             /* VD7IE_C Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD4IE_C:1;             /* VD4IE_C Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD3IE_P:1;             /* VD3IE_P Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD3IE_F:1;             /* VD3IE_F Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD3IE_C:1;             /* VD3IE_C Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
    } B;
  } IE_P;

  uint8_t PMCDIG_reserved0[36];
  union {                              /* Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t LVD3_P:1;              /* LVD3_P flag. */
      vuint32_t LVD3_F:1;              /* LVD3_F flag. */
      vuint32_t  :5;
      vuint32_t LVD3_C:1;              /* LVD3_C flag. */
    } B;
  } EPR_VD3;

  union {                              /* Reset Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t LVD3_P:1;              /* LVD3_P reset enable. */
      vuint32_t LVD3_F:1;              /* LVD3_F reset enable. */
      vuint32_t  :5;
      vuint32_t LVD3_C:1;              /* LVD3_C reset enable. */
    } B;
  } REE_VD3;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t LVD3_P:1;              /* LVD3_P reset event select. */
      vuint32_t LVD3_F:1;              /* LVD3_F reset event select. */
      vuint32_t  :5;
      vuint32_t LVD3_C:1;              /* LVD3_C reset event select. */
    } B;
  } RES_VD3;

  union {                              /* FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t FEE3_P:1;              /* FEE3_P FCCU event enable. */
      vuint32_t FEE3_F:1;              /* FEE3_F FCCU event enable. */
      vuint32_t  :5;
      vuint32_t FEE3_C:1;              /* FEE3_C FCCU event enable. */
    } B;
  } FEE_VD3;

  union {                              /* LVD108 Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t LVD4_C:1;              /* LVD4_C flag. */
    } B;
  } EPR_VD4;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t LVD4_C:1;              /* LVD4_C reset enable. */
    } B;
  } REE_VD4;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t LVD4_C:1;              /* LVD4_H reset event select. */
    } B;
  } RES_VD4;

  union {                              /* FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t FEE4_C:1;              /* FEE4_C FCCU event enable. */
    } B;
  } FEE_VD4;

  uint8_t PMCDIG_reserved1[32];
  union {                              /* Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t  :9;
      vuint32_t  :1;
      vuint32_t  :5;
      vuint32_t HVD7_C:1;              /* HVD7_C flag. */
    } B;
  } EPR_VD7;

  union {                              /* Reset Event Enable VD7 Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t  :9;
      vuint32_t  :1;
      vuint32_t  :5;
      vuint32_t HVD7_C:1;              /* HVD7_C reset enable. */
    } B;
  } REE_VD7;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t  :9;
      vuint32_t  :1;
      vuint32_t  :5;
      vuint32_t HVD7_C:1;              /* HVD7_C reset event select. */
    } B;
  } RES_VD7;

  union {                              /* FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t  :9;
      vuint32_t  :1;
      vuint32_t  :5;
      vuint32_t FEE7_C:1;              /* FEE7_C FCCU event enable. This bit defines whether an HVD assertion on the supply of the cold point generates an FCCU event. */
    } B;
  } FEE_VD7;

  union {                              /* Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :25;
      vuint32_t HVD8_F:1;              /* HVD8_F flag. */
      vuint32_t  :5;                   /* Reserved. */
      vuint32_t HVD8_C:1;              /* HVD8_C flag. */
    } B;
  } EPR_VD8;

  union {                              /* Reset Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :25;
      vuint32_t HVD8_F:1;              /* HVD8_F reset enable. */
      vuint32_t  :5;                   /* Reserved. */
      vuint32_t HVD8_C:1;              /* HVD8_C reset enable. */
    } B;
  } REE_VD8;

  union {                              /* Reset Event Select Registerr */
    vuint32_t R;
    struct {
      vuint32_t  :25;
      vuint32_t HVD8_F:1;              /* HVD8_F reset event select */
      vuint32_t  :5;                   /* Reserved. */
      vuint32_t HVD8_C:1;              /* HVD8_C reset event select. */
    } B;
  } RES_VD8;

  union {                              /* FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :25;
      vuint32_t FEE8_F:1;              /* FEE8_F FCCU event enable. */
      vuint32_t  :5;
      vuint32_t FEE8_C:1;              /* FEE8_C FCCU event enable. */
    } B;
  } FEE_VD8;

  union {                              /* LVD270 Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :17;
      vuint32_t LVD9_O:1;              /* LVD9_O flag. */
      vuint32_t  :2;
      vuint32_t LVD9_IF2:1;            /* LVD9_IF2 flag. */
      vuint32_t LVD9_IF:1;             /* LVD9_IF flag. */
      vuint32_t LVD9_IJ:1;             /* LVD9_IJ flag. */
      vuint32_t LVD9_IM:1;             /* LVD9_IM flag. */
      vuint32_t  :1;
      vuint32_t LVD9_F:1;              /* LVD9_F flag. */
      vuint32_t  :2;
      vuint32_t LVD9_EBI:1;            /* LVD9_EBI flag. */
      vuint32_t  :2;
      vuint32_t LVD9_C:1;              /* LVD9_C flag. */
    } B;
  } EPR_VD9;

  union {                              /* Reset Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :17;
      vuint32_t LVD9_O:1;              /* LVD9_O reset enable. */
      vuint32_t  :2;
      vuint32_t LVD9_IF2:1;            /* LVD9_IF2 reset enable. */
      vuint32_t LVD9_IF:1;             /* LVD9_IF reset enable. */
      vuint32_t LVD9_IJ:1;             /* LVD9_IJ reset enable. */
      vuint32_t LVD9_IM:1;             /* LVD9_IM reset enable. */
      vuint32_t  :1;
      vuint32_t LVD9_F:1;              /* LVD9_F reset enable. */
      vuint32_t  :2;
      vuint32_t LVD9_EBI:1;            /* LVD9_EBI reset enable. */
      vuint32_t  :2;
      vuint32_t LVD9_C:1;              /* LVD9_C reset enable. */
    } B;
  } REE_VD9;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t LVD9_IF2:1;            /* LVD9_IF2 reset event select. */
      vuint32_t LVD9_IF:1;             /* LVD9_IF reset event select. */
      vuint32_t  :6;
      vuint32_t LVD9_EBI:1;            /* LVD9_EBI reset event select. */
      vuint32_t  :3;
    } B;
  } RES_VD9;

  union {                              /* FCCU Event Enable VD9 */
    vuint32_t R;
    struct {
      vuint32_t  :17;
      vuint32_t FEE9_O:1;              /* FEE9_O FCCU event enable. */
      vuint32_t  :2;
      vuint32_t FEE9_IF2:1;            /* FEE9_IF2 FCCU event enable. */
      vuint32_t FEE9_IF:1;             /* FEE9_IF FCCU event enable. */
      vuint32_t FEE9_IJ:1;             /* FEE9_IJ FCCU event enable. */
      vuint32_t FEE9_IM:1;             /* FEE9_IM FCCU event enable. */
      vuint32_t  :1;
      vuint32_t FEE9_F:1;              /* FEE9_F FCCU event enable. */
      vuint32_t  :2;
      vuint32_t FEE9_EBI:1;            /* FEE9_EBI FCCU event enable. */
      vuint32_t  :2;
      vuint32_t FEE9_C:1;              /* FEE9_C FCCU event enable. */
    } B;
  } FEE_VD9;

  union {                              /* LVD295 Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t LVD10_A:1;             /* LVD10_A flag. */
      vuint32_t  :8;
      vuint32_t LVD10_F:1;             /* LVD10_F flag. */
      vuint32_t  :6;
    } B;
  } EPR_VD10;

  union {                              /* Reset Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t LVD10_A:1;             /* LVD10_A reset enable. */
      vuint32_t  :8;
      vuint32_t LVD10_F:1;             /* LVD10_F reset enable. */
      vuint32_t  :6;
    } B;
  } REE_VD10;

  uint8_t PMCDIG_reserved2[4];
  union {                              /* FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t FEE10_A:1;             /* FEE10_A FCCU event enable. */
      vuint32_t  :8;
      vuint32_t FEE10_F:1;             /* FEE10_F FCCU event enable. */
      vuint32_t  :6;
    } B;
  } FEE_VD10;

  uint8_t PMCDIG_reserved3[16];
  union {                              /* HVD360 Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :25;
      vuint32_t HVD12_F:1;             /* HVD12_F flag. */
      vuint32_t  :6;
    } B;
  } EPR_VD12;

  union {                              /* Reset Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :25;
      vuint32_t HVD12_F:1;             /* HVD12_F reset enable. */
      vuint32_t  :6;
    } B;
  } REE_VD12;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :25;
      vuint32_t HVD12_F:1;             /* HVD12_F reset event select. */
      vuint32_t  :6;
    } B;
  } RES_VD12;

  union {                              /* FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :25;
      vuint32_t FEE12_F:1;             /* FEE12_F FCCU event enable. */
      vuint32_t  :6;
    } B;
  } FEE_VD12;

  union {                              /* Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t LVD13_IM:1;            /* LVD13_IM flag. */
      vuint32_t  :8;
    } B;
  } EPR_VD13;

  union {                              /* Reset Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t LVD13_IM:1;            /* LVD13_IM reset enable. */
      vuint32_t  :8;
    } B;
  } REE_VD13;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t LVD13_IM:1;            /* LVD13_IM reset event select. */
      vuint32_t  :8;
    } B;
  } RES_VD13;

  union {                              /* FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t FEE13_IM:1;            /* FEE13_IM FCCU event enable. */
      vuint32_t  :8;
    } B;
  } FEE_VD13;

  union {                              /* Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t LVD14_A:1;             /* LVD14_A flag. */
      vuint32_t  :6;
      vuint32_t LVD14_IM:1;            /* LVD14_IM flag. */
      vuint32_t  :8;
    } B;
  } EPR_VD14;

  union {                              /* Reset Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t LVD14_A:1;             /* LVD14_A reset enable. */
      vuint32_t  :6;
      vuint32_t LVD14_IM:1;            /* LVD14_IM reset enable. */
      vuint32_t  :8;
    } B;
  } REE_VD14;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t LVD14_A:1;             /* LVD14_A reset event select. */
      vuint32_t  :6;
      vuint32_t LVD14_IM:1;            /* LVD14_IM reset event select. */
      vuint32_t  :8;
    } B;
  } RES_VD14;

  union {                              /* FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t FEE14_A:1;             /* FEE14_A FCCU event enable. */
      vuint32_t  :6;
      vuint32_t FEE14_IM:1;            /* FEE14_IM FCCU event enable. */
      vuint32_t  :8;
    } B;
  } FEE_VD14;

  union {                              /* Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t HVD15_A:1;             /* HVD15_A flag. */
      vuint32_t  :14;
      vuint32_t HVD15_C:1;             /* HVD15_C flag. */
    } B;
  } EPR_VD15;

  union {                              /* Reset Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t HVD15_A:1;             /* HVD15_A reset enable. */
      vuint32_t  :14;
      vuint32_t HVD15_C:1;
    } B;
  } REE_VD15;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t HVD15_A:1;             /* HVD15_A reset event select. */
      vuint32_t  :14;
      vuint32_t HVD15_C:1;             /* HVD15_C reset event select. */
    } B;
  } RES_VD15;

  union {                              /* FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t FEE15_A:1;             /* FEE15_A FCCU event enable. */
      vuint32_t  :14;
      vuint32_t FEE15_C:1;             /* FEE15_C FCCU event enable. */
    } B;
  } FEE_VD15;

  uint8_t PMCDIG_reserved4[4];
  union {                              /* Voltage Supply for I/O Segment Register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t VSIO_IF2:1;            /* VSIO_IF2 control. */
      vuint32_t VSIO_IF:1;             /* VSIO_IF control. */
      vuint32_t VSIO_IJ:1;             /* VSIO_IJ control. */
      vuint32_t VSIO_IM:1;             /* VSIO_IM control. */
      vuint32_t  :8;
    } B;
  } VSIO;

  uint8_t PMCDIG_reserved5[504];
  union {                              /* Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t TEMP_3:1;              /* TEMP_3 flag. */
      vuint32_t TEMP_2:1;              /* TEMP_2 flag. */
      vuint32_t  :1;
      vuint32_t TEMP_0:1;              /* TEMP_0 flag. */
    } B;
  } EPR_TD;

  union {                              /* Reset Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t TEMP_3:1;              /* TEMP_3 reset enable. */
      vuint32_t TEMP_2:1;              /* TEMP_2 reset enable. */
      vuint32_t  :1;
      vuint32_t TEMP_0:1;              /* TEMP_0 reset enable. */
    } B;
  } REE_TD;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t TEMP_3:1;              /* TEMP_3 reset event select. */
      vuint32_t TEMP_2:1;              /* TEMP_2 reset event select. */
      vuint32_t  :1;
      vuint32_t TEMP_0:1;              /* TEMP_0 reset event select. */
    } B;
  } RES_TD;

  union {                              /* Temperature Sensor Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t TS3IE:1;               /* TS3IE Temperature Sensor input 3 Interrupt Enable. */
      vuint32_t TS2IE:1;               /* TS2IE Temperature Sensor input 0 Interrupt Enable. */
      vuint32_t TS0IE:1;               /* TS0IE Temperature Sensor input 0 Interrupt Enable. */
      vuint32_t  :1;
      vuint32_t TRIM_ADJ_OVER:4;       /* Customer adjustable over trim register. */
      vuint32_t  :2;
      vuint32_t TRIM_ADJ_UNDER:4;      /* Customer adjustable trim register. */
      vuint32_t DOUT_EN:1;             /* Digital Output Enable. */
      vuint32_t AOUT_EN:1;             /* Analog Output Enable. */
    } B;
  } CTL_TD;

  uint8_t PMCDIG_reserved6[8];
  union {                              /* Temp Sensor FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t FEE_TS3:1;             /* FEE_TS3 Temp Sensor FCCU event enable. */
      vuint32_t FEE_TS2:1;             /* FEE_TS2 Temp Sensor FCCU event enable. */
      vuint32_t  :1;
      vuint32_t FEE_TS0:1;             /* FEE_TS0 Temp Sensor FCCU event enable. */
    } B;
  } FEE_TD;

  uint8_t PMCDIG_reserved7[36];
  union {                              /* Voltage Detect User Mode Test Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;                   /* Reserved. */
      vuint32_t VOLT4_EN:1;            /* VOLT4 enable. */
      vuint32_t VOLT3_EN:1;            /* VOLT3 enable. */
      vuint32_t VOLT2_EN:1;            /* VOLT2 enable. */
      vuint32_t VOLT1_EN:1;            /* VOLT1 enable. */
      vuint32_t  :4;                   /* Reserved. */
      vuint32_t VOLT4:1;               /* VOLT4 flag. */
      vuint32_t VOLT3:1;               /* VOLT3 flag. */
      vuint32_t VOLT2:1;               /* VOLT2 flag. */
      vuint32_t VOLT1:1;               /* VOLT1 flag. */
      vuint32_t  :10;
      vuint32_t VD_UTST:6;             /* Voltage Detect: User Test. */
    } B;
  } VD_UTST;

  union {                              /* ADC Channel Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t ADC_CS:6;              /* ADC_CS Channel Select. */
    } B;
  } ADC_CH;

  uint8_t PMCDIG_reserved8[4];
  union {                              /* Voltage Regulator 1.2V Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t VREG1P2_DIS:1;         /* This bit controls if the AUX Regulator (Vreg1p2) is disabled. */
    } B;
  } VREG1P2_CTRL;

  union {                              /* Module Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;                  /* Reserved. */
      vuint32_t ADC_CHSEL_EN:1;        /* This bit allows the ADC_CS bits int he ADC_CH register to be enabled. */
      vuint32_t USER_SELF_TEST_EN:1;   /* This bit allows the VD_UTST bits int he VD_UTST register to be enabled. */
      vuint32_t  :6;                   /* Reserved. */
      vuint32_t TEST_PIN:1;            /* This bit is indicates the current value of the Test Pin. */
      vuint32_t  :6;                   /* Reserved. */
      vuint32_t SBRAM_BRDET:1;         /* SBRAM_BRDET. */
    } B;
  } MCR;
};


/* ============================================================================
   =============================== Module: PRAMC ==============================
   ============================================================================ */

struct PRAMC_tag {
  union {                              /* Platform RAM Configuration Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t PRI:2;                 /* AHB port arbitration mode. */
      vuint32_t P1_BO_DIS:1;           /* Port p1 read burst optimization disable. */
      vuint32_t P0_BO_DIS:1;           /* Port p0 read burst optimization disable. */
      vuint32_t P1_RB_DIS:1;           /* Port p1 read buffer disable. */
      vuint32_t P0_RB_DIS:1;           /* Port p0 read buffer disable. */
      vuint32_t  :3;
      vuint32_t FT_DIS:1;              /* Flow through disabled. */
    } B;
  } PRCR1;
};


/* ============================================================================
   =============================== Module: PSI5 ===============================
   ============================================================================ */

struct PSI5_tag {
  union {                              /* Global Control Register */
    vuint16_t R;
    struct {
      vuint16_t  :14;
      vuint16_t CTC_GED:1;
      vuint16_t GLOBAL_DISABLE_REQ:1;
    } B;
  } GCR;

  uint8_t PSI5_reserved0[6];
  union {                              /* PSI5 Channel Control Register */
    vuint32_t R;
    struct {
      vuint32_t CTC_GED_SEL:1;
      vuint32_t CTC_ED:1;
      vuint32_t  :1;
      vuint32_t MEM_DEPTH:5;
      vuint32_t  :3;
      vuint32_t ERROR_SELECT4:1;
      vuint32_t ERROR_SELECT3:1;
      vuint32_t ERROR_SELECT2:1;
      vuint32_t ERROR_SELECT1:1;
      vuint32_t ERROR_SELECT0:1;
      vuint32_t  :1;
      vuint32_t GTM_RESET_ASYNC_EN:1;
      vuint32_t  :3;
      vuint32_t DEBUG_EN:1;
      vuint32_t DEBUG_FREEZE_CTRL:1;
      vuint32_t SP_TS_CLK_SEL:1;
      vuint32_t  :2;
      vuint32_t FAST_CLR_SMC:1;
      vuint32_t FAST_CLR_PSI5:1;
      vuint32_t BIT_RATE:1;
      vuint32_t MODE:1;
      vuint32_t PSI5_CH_CONFIG:1;
      vuint32_t PSI5_CH_EN:1;
    } B;
  } CH0_PCCR;

  union {                              /* DMA Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t DMA_PM_DS_WM:5;
      vuint32_t  :5;
      vuint32_t IE_DMA_TF_SF:1;
      vuint32_t IE_DMA_TF_PM_DS:1;
      vuint32_t  :5;
      vuint32_t IE_DMA_PM_DS_FIFO_FULL:1;
      vuint32_t IE_DMA_SFUF:1;
      vuint32_t  :1;
      vuint32_t IE_DMA_PM_DS_UF:1;
      vuint32_t  :5;
      vuint32_t DMA_EN_SF:1;
      vuint32_t DMA_PM_DS_CONFIG:2;
    } B;
  } CH0_DCR;

  union {                              /* DMA Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t IS_DMA_TF_SF:1;
      vuint32_t IS_DMA_TF_PM_DS:1;
      vuint32_t  :5;
      vuint32_t IS_DMA_PM_DS_FIFO_FULL:1;
      vuint32_t IS_DMA_SFUF:1;
      vuint32_t  :1;
      vuint32_t IS_DMA_PM_DS_UF:1;
      vuint32_t  :8;
    } B;
  } CH0_DSR;

  union {                              /* General Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t IE_CESM:6;
      vuint32_t IE_STS:1;
      vuint32_t IE_DTS:1;
      vuint32_t IE_DSROW:1;
      vuint32_t IE_BROW:1;
      vuint32_t IE_PROW:1;
      vuint32_t IE_DSRR:1;
      vuint32_t IE_BRR:1;
      vuint32_t IE_PRR:1;
      vuint32_t  :2;
      vuint32_t IE_OWSM:6;
      vuint32_t  :2;
      vuint32_t IE_NVSM:6;
    } B;
  } CH0_GICR;

  union {                              /* New Data Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t IE_ND:32;
    } B;
  } CH0_NDICR;

  union {                              /* Overwrite Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t IE_OW:32;
    } B;
  } CH0_OWICR;

  union {                              /* Error Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t IE_ERROR:32;
    } B;
  } CH0_EICR;

  union {                              /* General Interrupt Status Register */
    vuint32_t R;
    struct {
      vuint32_t IS_DB_FR:1;
      vuint32_t  :1;
      vuint32_t IS_CESM:6;
      vuint32_t IS_STS:1;
      vuint32_t IS_DTS:1;
      vuint32_t IS_DSROW:1;
      vuint32_t IS_BROW:1;
      vuint32_t IS_PROW:1;
      vuint32_t DSR_RDY:1;
      vuint32_t DBR_RDY:1;
      vuint32_t DPR_RDY:1;
      vuint32_t  :2;
      vuint32_t IS_OWSM:6;
      vuint32_t  :2;
      vuint32_t IS_NVSM:6;
    } B;
  } CH0_GISR;

  union {                              /* DMA PSI5 Message Register */
    vuint32_t R;
    struct {
      vuint32_t PSI5_RXDATA:32;
    } B;
  } CH0_DPMR;

  union {                              /* DMA SMC Frame Register */
    vuint32_t R;
    struct {
      vuint32_t SMC_RXDATA:32;
    } B;
  } CH0_DSFR;

  union {                              /* DMA Diagnostic Status Register */
    vuint32_t R;
    struct {
      vuint32_t DDS:32;
    } B;
  } CH0_DDSR;

  union {                              /* PSI5 Message Receive Register Low */
    vuint32_t R;
    struct {
      vuint32_t DATA_REGION:28;
      vuint32_t CRC:3;
      vuint32_t C:1;
    } B;
  } CH0_PMRRL;

  union {                              /* PSI5 Message Receive Register High */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t F:1;
      vuint32_t EM:1;
      vuint32_t E:1;
      vuint32_t T:1;
      vuint32_t SlotCounter:3;
      vuint32_t TimeStampValue:24;
    } B;
  } CH0_PMRRH;

  struct {
    union {                            /* PSI5 Message Register Low i */
      vuint32_t R;
      struct {
        vuint32_t DATA_REGION:28;
        vuint32_t CRCP:3;
        vuint32_t C:1;
      } B;
    } PMRL;
    union {                            /* PSI5 Message Register High i */
      vuint32_t R;
      struct {
        vuint32_t O:1;
        vuint32_t F:1;
        vuint32_t EM:1;
        vuint32_t E:1;
        vuint32_t T:1;
        vuint32_t Slot_Counter:3;
        vuint32_t TimeStampValue:24;
      } B;
    } PMRH;
  } CH0[32];

  union {                              /* SMC Frame Register n */
    vuint32_t R;
    struct {
      vuint32_t SLOT_NO:3;
      vuint32_t CER:1;
      vuint32_t OW:1;
      vuint32_t CRC:6;
      vuint32_t C:1;
      vuint32_t ID:4;
      vuint32_t IDDATA:4;
      vuint32_t DATA:12;
    } B;
  } CH0_SFR[6];

  union {                              /* New Data Status Register */
    vuint32_t R;
    struct {
      vuint32_t NDS:32;
    } B;
  } CH0_NDSR;

  union {                              /* Overwrite Status Register */
    vuint32_t R;
    struct {
      vuint32_t OWS:32;
    } B;
  } CH0_OWSR;

  union {                              /* Error Indication Status Register */
    vuint32_t R;
    struct {
      vuint32_t ERROR:32;
    } B;
  } CH0_EISR;

  union {                              /* Set New Data Status Register */
    vuint32_t R;
    struct {
      vuint32_t SNDS:32;
    } B;
  } CH0_SNDSR;

  union {                              /* Set Overwrite Status Register */
    vuint32_t R;
    struct {
      vuint32_t SOWS:32;
    } B;
  } CH0_SOWSR;

  union {                              /* Set Error Status Register */
    vuint32_t R;
    struct {
      vuint32_t SERROR:32;
    } B;
  } CH0_SEISR;

  union {                              /* Set SMC Error Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t SCESM:6;
      vuint32_t  :10;
      vuint32_t SOWSM:6;
      vuint32_t  :2;
      vuint32_t SNVSM:6;
    } B;
  } CH0_SSESR;

  union {                              /* Sync Time Stamp Read Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t STSV:24;
    } B;
  } CH0_STSRR;

  union {                              /* Data Time Stamp Read Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t SLOT_COUNTER:3;
      vuint32_t DTSV:24;
    } B;
  } CH0_DTSRR;

  union {                              /* Slot n Frame Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t SLOT_EN:1;
      vuint32_t TS_CAPT:1;
      vuint32_t  :1;
      vuint32_t SMCL:1;
      vuint32_t  :9;
      vuint32_t DRL:5;
      vuint32_t CRCP:1;
    } B;
  } CH0_SFCR[6];

  union {                              /* Slot 1 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S1SBT:15;
    } B;
  } CH0_S1SBR;

  union {                              /* Slot 2 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S2SBT:15;
    } B;
  } CH0_S2SBR;

  union {                              /* Slot 3 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S3SBT:15;
    } B;
  } CH0_S3SBR;

  union {                              /* Slot 4 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S4SBT:15;
    } B;
  } CH0_S4SBR;

  union {                              /* Slot 5 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S5SBT:15;
    } B;
  } CH0_S5SBR;

  union {                              /* Slot 6 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S6SBT:15;
    } B;
  } CH0_S6SBR;

  union {                              /* Slot n End Boundary Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t SLOT_NO:3;
      vuint32_t  :1;
      vuint32_t SnEBT:15;
    } B;
  } CH0_SnEBR;

  union {                              /* Data Output Block Configuration Register */
    vuint16_t R;
    struct {
      vuint16_t DATA_LENGTH:6;
      vuint16_t DBR_RST:1;
      vuint16_t DSR_RST:1;
      vuint16_t CMD_TYPE:3;
      vuint16_t DEFAULT_SYNC:1;
      vuint16_t GTM_TRIG_SEL:1;
      vuint16_t SP_PULSE_SEL:1;
      vuint16_t OP_SEL:1;
      vuint16_t SW_READY:1;
    } B;
  } CH0_DOBCR;

  union {                              /* Manchestor Decoder Disable Offset */
    vuint16_t R;
    struct {
      vuint16_t  :9;
      vuint16_t MDDIS_OFF:7;
    } B;
  } CH0_MDDIS_OFF;

  union {                              /* Pulse Width for Data Bit Value 0 */
    vuint16_t R;
    struct {
      vuint16_t  :9;
      vuint16_t Pulse_Width0:7;
    } B;
  } CH0_PW0D;

  union {                              /* Pulse Width for Data Bit Value 1 */
    vuint16_t R;
    struct {
      vuint16_t  :9;
      vuint16_t Pulse_Width1:7;
    } B;
  } CH0_PW1D;

  union {                              /* Counter Target Pulse Register */
    vuint16_t R;
    struct {
      vuint16_t CTPR:16;
    } B;
  } CH0_CTPR;

  union {                              /* Counter Initialize Pulse Register */
    vuint16_t R;
    struct {
      vuint16_t CIPR:16;
    } B;
  } CH0_CIPR;

  union {                              /* Data Preparation Register Low */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DPR:24;
    } B;
  } CH0_DPRL;

  union {                              /* Data Preparation Register High */
    vuint32_t R;
    struct {
      vuint32_t  :32;
    } B;
  } CH0_DPRH;

  union {                              /* Data Buffer Register Low */
    vuint32_t R;
    struct {
      vuint32_t DBR:32;
    } B;
  } CH0_DBRL;

  union {                              /* Data Buffer Register High */
    vuint32_t R;
    struct {
      vuint32_t DBR:32;
    } B;
  } CH0_DBRH;

  union {                              /* Data Shift Register Low */
    vuint32_t R;
    struct {
      vuint32_t DSR:32;
    } B;
  } CH0_DSRL;

  union {                              /* Data Shift Register High */
    vuint32_t R;
    struct {
      vuint32_t DSR:32;
    } B;
  } CH0_DSRH;

  uint8_t PSI5_reserved1[4];
  union {                              /* PSI5 Channel Control Register */
    vuint32_t R;
    struct {
      vuint32_t CTC_GED_SEL:1;
      vuint32_t CTC_ED:1;
      vuint32_t  :1;
      vuint32_t MEM_DEPTH:5;
      vuint32_t  :3;
      vuint32_t ERROR_SELECT4:1;
      vuint32_t ERROR_SELECT3:1;
      vuint32_t ERROR_SELECT2:1;
      vuint32_t ERROR_SELECT1:1;
      vuint32_t ERROR_SELECT0:1;
      vuint32_t  :1;
      vuint32_t GTM_RESET_ASYNC_EN:1;
      vuint32_t  :3;
      vuint32_t DEBUG_EN:1;
      vuint32_t DEBUG_FREEZE_CTRL:1;
      vuint32_t SP_TS_CLK_SEL:1;
      vuint32_t  :2;
      vuint32_t FAST_CLR_SMC:1;
      vuint32_t FAST_CLR_PSI5:1;
      vuint32_t BIT_RATE:1;
      vuint32_t MODE:1;
      vuint32_t PSI5_CH_CONFIG:1;
      vuint32_t PSI5_CH_EN:1;
    } B;
  } CH1_PCCR;

  union {                              /* DMA Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t DMA_PM_DS_WM:5;
      vuint32_t  :5;
      vuint32_t IE_DMA_TF_SF:1;
      vuint32_t IE_DMA_TF_PM_DS:1;
      vuint32_t  :5;
      vuint32_t IE_DMA_PM_DS_FIFO_FULL:1;
      vuint32_t IE_DMA_SFUF:1;
      vuint32_t  :1;
      vuint32_t IE_DMA_PM_DS_UF:1;
      vuint32_t  :5;
      vuint32_t DMA_EN_SF:1;
      vuint32_t DMA_PM_DS_CONFIG:2;
    } B;
  } CH1_DCR;

  union {                              /* DMA Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t IS_DMA_TF_SF:1;
      vuint32_t IS_DMA_TF_PM_DS:1;
      vuint32_t  :5;
      vuint32_t IS_DMA_PM_DS_FIFO_FULL:1;
      vuint32_t IS_DMA_SFUF:1;
      vuint32_t  :1;
      vuint32_t IS_DMA_PM_DS_UF:1;
      vuint32_t  :8;
    } B;
  } CH1_DSR;

  union {                              /* General Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t IE_CESM:6;
      vuint32_t IE_STS:1;
      vuint32_t IE_DTS:1;
      vuint32_t IE_DSROW:1;
      vuint32_t IE_BROW:1;
      vuint32_t IE_PROW:1;
      vuint32_t IE_DSRR:1;
      vuint32_t IE_BRR:1;
      vuint32_t IE_PRR:1;
      vuint32_t  :2;
      vuint32_t IE_OWSM:6;
      vuint32_t  :2;
      vuint32_t IE_NVSM:6;
    } B;
  } CH1_GICR;

  union {                              /* New Data Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t IE_ND:32;
    } B;
  } CH1_NDICR;

  union {                              /* Overwrite Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t IE_OW:32;
    } B;
  } CH1_OWICR;

  union {                              /* Error Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t IE_ERROR:32;
    } B;
  } CH1_EICR;

  union {                              /* General Interrupt Status Register */
    vuint32_t R;
    struct {
      vuint32_t IS_DB_FR:1;
      vuint32_t  :1;
      vuint32_t IS_CESM:6;
      vuint32_t IS_STS:1;
      vuint32_t IS_DTS:1;
      vuint32_t IS_DSROW:1;
      vuint32_t IS_BROW:1;
      vuint32_t IS_PROW:1;
      vuint32_t DSR_RDY:1;
      vuint32_t DBR_RDY:1;
      vuint32_t DPR_RDY:1;
      vuint32_t  :2;
      vuint32_t IS_OWSM:6;
      vuint32_t  :2;
      vuint32_t IS_NVSM:6;
    } B;
  } CH1_GISR;

  union {                              /* DMA PSI5 Message Register */
    vuint32_t R;
    struct {
      vuint32_t PSI5_RXDATA:32;
    } B;
  } CH1_DPMR;

  union {                              /* DMA SMC Frame Register */
    vuint32_t R;
    struct {
      vuint32_t SMC_RXDATA:32;
    } B;
  } CH1_DSFR;

  union {                              /* DMA Diagnostic Status Register */
    vuint32_t R;
    struct {
      vuint32_t DDS:32;
    } B;
  } CH1_DDSR;

  union {                              /* PSI5 Message Receive Register Low */
    vuint32_t R;
    struct {
      vuint32_t DATA_REGION:28;
      vuint32_t CRC:3;
      vuint32_t C:1;
    } B;
  } CH1_PMRRL;

  union {                              /* PSI5 Message Receive Register High */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t F:1;
      vuint32_t EM:1;
      vuint32_t E:1;
      vuint32_t T:1;
      vuint32_t SlotCounter:3;
      vuint32_t TimeStampValue:24;
    } B;
  } CH1_PMRRH;

  struct {
    union {                            /* PSI5 Message Register Low i */
      vuint32_t R;
      struct {
        vuint32_t DATA_REGION:28;
        vuint32_t CRCP:3;
        vuint32_t C:1;
      } B;
    } PMRL;
    union {                            /* PSI5 Message Register High i */
      vuint32_t R;
      struct {
        vuint32_t O:1;
        vuint32_t F:1;
        vuint32_t EM:1;
        vuint32_t E:1;
        vuint32_t T:1;
        vuint32_t Slot_Counter:3;
        vuint32_t TimeStampValue:24;
      } B;
    } PMRH;
  } CH1[32];

  union {                              /* SMC Frame Register n */
    vuint32_t R;
    struct {
      vuint32_t SLOT_NO:3;
      vuint32_t CER:1;
      vuint32_t OW:1;
      vuint32_t CRC:6;
      vuint32_t C:1;
      vuint32_t ID:4;
      vuint32_t IDDATA:4;
      vuint32_t DATA:12;
    } B;
  } CH1_SFR[6];

  union {                              /* New Data Status Register */
    vuint32_t R;
    struct {
      vuint32_t NDS:32;
    } B;
  } CH1_NDSR;

  union {                              /* Overwrite Status Register */
    vuint32_t R;
    struct {
      vuint32_t OWS:32;
    } B;
  } CH1_OWSR;

  union {                              /* Error Indication Status Register */
    vuint32_t R;
    struct {
      vuint32_t ERROR:32;
    } B;
  } CH1_EISR;

  union {                              /* Set New Data Status Register */
    vuint32_t R;
    struct {
      vuint32_t SNDS:32;
    } B;
  } CH1_SNDSR;

  union {                              /* Set Overwrite Status Register */
    vuint32_t R;
    struct {
      vuint32_t SOWS:32;
    } B;
  } CH1_SOWSR;

  union {                              /* Set Error Status Register */
    vuint32_t R;
    struct {
      vuint32_t SERROR:32;
    } B;
  } CH1_SEISR;

  union {                              /* Set SMC Error Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t SCESM:6;
      vuint32_t  :10;
      vuint32_t SOWSM:6;
      vuint32_t  :2;
      vuint32_t SNVSM:6;
    } B;
  } CH1_SSESR;

  union {                              /* Sync Time Stamp Read Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t STSV:24;
    } B;
  } CH1_STSRR;

  union {                              /* Data Time Stamp Read Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t SLOT_COUNTER:3;
      vuint32_t DTSV:24;
    } B;
  } CH1_DTSRR;

  union {                              /* Slot n Frame Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t SLOT_EN:1;             /* SLOT_EN */
      vuint32_t TS_CAPT:1;             /* TS_CAPT */
      vuint32_t  :1;
      vuint32_t SMCL:1;
      vuint32_t  :9;
      vuint32_t DRL:5;
      vuint32_t CRCP:1;                /* CRCP */
    } B;
  } CH1_SFCR[6];

  union {                              /* Slot 1 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S1SBT:15;
    } B;
  } CH1_S1SBR;

  union {                              /* Slot 2 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S2SBT:15;
    } B;
  } CH1_S2SBR;

  union {                              /* Slot 3 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S3SBT:15;
    } B;
  } CH1_S3SBR;

  union {                              /* Slot 4 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S4SBT:15;
    } B;
  } CH1_S4SBR;

  union {                              /* Slot 5 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S5SBT:15;
    } B;
  } CH1_S5SBR;

  union {                              /* Slot 6 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S6SBT:15;
    } B;
  } CH1_S6SBR;

  union {                              /* Slot n End Boundary Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t SLOT_NO:3;
      vuint32_t  :1;
      vuint32_t SnEBT:15;
    } B;
  } CH1_SnEBR;

  union {                              /* Data Output Block Configuration Register */
    vuint16_t R;
    struct {
      vuint16_t DATA_LENGTH:6;
      vuint16_t DBR_RST:1;
      vuint16_t DSR_RST:1;
      vuint16_t CMD_TYPE:3;
      vuint16_t DEFAULT_SYNC:1;
      vuint16_t GTM_TRIG_SEL:1;
      vuint16_t SP_PULSE_SEL:1;
      vuint16_t OP_SEL:1;
      vuint16_t SW_READY:1;
    } B;
  } CH1_DOBCR;

  union {                              /* Manchestor Decoder Disable Offset */
    vuint16_t R;
    struct {
      vuint16_t  :9;
      vuint16_t MDDIS_OFF:7;
    } B;
  } CH1_MDDIS_OFF;

  union {                              /* Pulse Width for Data Bit Value 0 */
    vuint16_t R;
    struct {
      vuint16_t  :9;
      vuint16_t Pulse_Width0:7;
    } B;
  } CH1_PW0D;

  union {                              /* Pulse Width for Data Bit Value 1 */
    vuint16_t R;
    struct {
      vuint16_t  :9;
      vuint16_t Pulse_Width1:7;
    } B;
  } CH1_PW1D;

  union {                              /* Counter Target Pulse Register */
    vuint16_t R;
    struct {
      vuint16_t CTPR:16;
    } B;
  } CH1_CTPR;

  union {                              /* Counter Initialize Pulse Register */
    vuint16_t R;
    struct {
      vuint16_t CIPR:16;
    } B;
  } CH1_CIPR;

  union {                              /* Data Preparation Register Low */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DPR:24;
    } B;
  } CH1_DPRL;

  union {                              /* Data Preparation Register High */
    vuint32_t R;
    struct {
      vuint32_t  :32;
    } B;
  } CH1_DPRH;

  union {                              /* Data Buffer Register Low */
    vuint32_t R;
    struct {
      vuint32_t DBR:32;
    } B;
  } CH1_DBRL;

  union {                              /* Data Buffer Register High */
    vuint32_t R;
    struct {
      vuint32_t DBR:32;
    } B;
  } CH1_DBRH;

  union {                              /* Data Shift Register Low */
    vuint32_t R;
    struct {
      vuint32_t DSR:32;
    } B;
  } CH1_DSRL;

  union {                              /* Data Shift Register High */
    vuint32_t R;
    struct {
      vuint32_t DSR:32;
    } B;
  } CH1_DSRH;

  uint8_t PSI5_reserved2[4];
  union {                              /* PSI5 Channel Control Register */
    vuint32_t R;
    struct {
      vuint32_t CTC_GED_SEL:1;
      vuint32_t CTC_ED:1;
      vuint32_t  :1;
      vuint32_t MEM_DEPTH:5;
      vuint32_t  :3;
      vuint32_t ERROR_SELECT4:1;
      vuint32_t ERROR_SELECT3:1;
      vuint32_t ERROR_SELECT2:1;
      vuint32_t ERROR_SELECT1:1;
      vuint32_t ERROR_SELECT0:1;
      vuint32_t  :1;
      vuint32_t GTM_RESET_ASYNC_EN:1;
      vuint32_t  :3;
      vuint32_t DEBUG_EN:1;
      vuint32_t DEBUG_FREEZE_CTRL:1;
      vuint32_t SP_TS_CLK_SEL:1;
      vuint32_t  :2;
      vuint32_t FAST_CLR_SMC:1;
      vuint32_t FAST_CLR_PSI5:1;
      vuint32_t BIT_RATE:1;
      vuint32_t MODE:1;
      vuint32_t PSI5_CH_CONFIG:1;
      vuint32_t PSI5_CH_EN:1;
    } B;
  } CH2_PCCR;

  union {                              /* DMA Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t DMA_PM_DS_WM:5;
      vuint32_t  :5;
      vuint32_t IE_DMA_TF_SF:1;
      vuint32_t IE_DMA_TF_PM_DS:1;
      vuint32_t  :5;
      vuint32_t IE_DMA_PM_DS_FIFO_FULL:1;
      vuint32_t IE_DMA_SFUF:1;
      vuint32_t  :1;
      vuint32_t IE_DMA_PM_DS_UF:1;
      vuint32_t  :5;
      vuint32_t DMA_EN_SF:1;
      vuint32_t DMA_PM_DS_CONFIG:2;
    } B;
  } CH2_DCR;

  union {                              /* DMA Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t IS_DMA_TF_SF:1;
      vuint32_t IS_DMA_TF_PM_DS:1;
      vuint32_t  :5;
      vuint32_t IS_DMA_PM_DS_FIFO_FULL:1;
      vuint32_t IS_DMA_SFUF:1;
      vuint32_t  :1;
      vuint32_t IS_DMA_PM_DS_UF:1;
      vuint32_t  :8;
    } B;
  } CH2_DSR;

  union {                              /* General Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t IE_CESM:6;
      vuint32_t IE_STS:1;
      vuint32_t IE_DTS:1;
      vuint32_t IE_DSROW:1;
      vuint32_t IE_BROW:1;
      vuint32_t IE_PROW:1;
      vuint32_t IE_DSRR:1;
      vuint32_t IE_BRR:1;
      vuint32_t IE_PRR:1;
      vuint32_t  :2;
      vuint32_t IE_OWSM:6;
      vuint32_t  :2;
      vuint32_t IE_NVSM:6;
    } B;
  } CH2_GICR;

  union {                              /* New Data Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t IE_ND:32;
    } B;
  } CH2_NDICR;

  union {                              /* Overwrite Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t IE_OW:32;
    } B;
  } CH2_OWICR;

  union {                              /* Error Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t IE_ERROR:32;
    } B;
  } CH2_EICR;

  union {                              /* General Interrupt Status Register */
    vuint32_t R;
    struct {
      vuint32_t IS_DB_FR:1;
      vuint32_t  :1;
      vuint32_t IS_CESM:6;
      vuint32_t IS_STS:1;
      vuint32_t IS_DTS:1;
      vuint32_t IS_DSROW:1;
      vuint32_t IS_BROW:1;
      vuint32_t IS_PROW:1;
      vuint32_t DSR_RDY:1;
      vuint32_t DBR_RDY:1;
      vuint32_t DPR_RDY:1;
      vuint32_t  :2;
      vuint32_t IS_OWSM:6;
      vuint32_t  :2;
      vuint32_t IS_NVSM:6;
    } B;
  } CH2_GISR;

  union {                              /* DMA PSI5 Message Register */
    vuint32_t R;
    struct {
      vuint32_t PSI5_RXDATA:32;
    } B;
  } CH2_DPMR;

  union {                              /* DMA SMC Frame Register */
    vuint32_t R;
    struct {
      vuint32_t SMC_RXDATA:32;
    } B;
  } CH2_DSFR;

  union {                              /* DMA Diagnostic Status Register */
    vuint32_t R;
    struct {
      vuint32_t DDS:32;
    } B;
  } CH2_DDSR;

  union {                              /* PSI5 Message Receive Register Low */
    vuint32_t R;
    struct {
      vuint32_t DATA_REGION:28;
      vuint32_t CRC:3;
      vuint32_t C:1;
    } B;
  } CH2_PMRRL;

  union {                              /* PSI5 Message Receive Register High */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t F:1;
      vuint32_t EM:1;
      vuint32_t E:1;
      vuint32_t T:1;
      vuint32_t SlotCounter:3;
      vuint32_t TimeStampValue:24;
    } B;
  } CH2_PMRRH;

  struct {
    union {                            /* PSI5 Message Register Low i */
      vuint32_t R;
      struct {
        vuint32_t DATA_REGION:28;
        vuint32_t CRCP:3;
        vuint32_t C:1;
      } B;
    } PMRL;
    union {                            /* PSI5 Message Register High i */
      vuint32_t R;
      struct {
        vuint32_t O:1;
        vuint32_t F:1;
        vuint32_t EM:1;
        vuint32_t E:1;
        vuint32_t T:1;
        vuint32_t Slot_Counter:3;
        vuint32_t TimeStampValue:24;
      } B;
    } PMRH;
  } CH2[32];

  union {                              /* SMC Frame Register n */
    vuint32_t R;
    struct {
      vuint32_t SLOT_NO:3;
      vuint32_t CER:1;
      vuint32_t OW:1;
      vuint32_t CRC:6;
      vuint32_t C:1;
      vuint32_t ID:4;
      vuint32_t IDDATA:4;
      vuint32_t DATA:12;
    } B;
  } CH2_SFR[6];

  union {                              /* New Data Status Register */
    vuint32_t R;
    struct {
      vuint32_t NDS:32;
    } B;
  } CH2_NDSR;

  union {                              /* Overwrite Status Register */
    vuint32_t R;
    struct {
      vuint32_t OWS:32;
    } B;
  } CH2_OWSR;

  union {                              /* Error Indication Status Register */
    vuint32_t R;
    struct {
      vuint32_t ERROR:32;
    } B;
  } CH2_EISR;

  union {                              /* Set New Data Status Register */
    vuint32_t R;
    struct {
      vuint32_t SNDS:32;
    } B;
  } CH2_SNDSR;

  union {                              /* Set Overwrite Status Register */
    vuint32_t R;
    struct {
      vuint32_t SOWS:32;
    } B;
  } CH2_SOWSR;

  union {                              /* Set Error Status Register */
    vuint32_t R;
    struct {
      vuint32_t SERROR:32;
    } B;
  } CH2_SEISR;

  union {                              /* Set SMC Error Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t SCESM:6;
      vuint32_t  :10;
      vuint32_t SOWSM:6;
      vuint32_t  :2;
      vuint32_t SNVSM:6;
    } B;
  } CH2_SSESR;

  union {                              /* Sync Time Stamp Read Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t STSV:24;
    } B;
  } CH2_STSRR;

  union {                              /* Data Time Stamp Read Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t SLOT_COUNTER:3;
      vuint32_t DTSV:24;
    } B;
  } CH2_DTSRR;

  union {                              /* Slot n Frame Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t SLOT_EN:1;
      vuint32_t TS_CAPT:1;
      vuint32_t  :1;
      vuint32_t SMCL:1;
      vuint32_t  :9;
      vuint32_t DRL:5;
      vuint32_t CRCP:1;
    } B;
  } CH2_SFCR[6];

  union {                              /* Slot 1 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S1SBT:15;
    } B;
  } CH2_S1SBR;

  union {                              /* Slot 2 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S2SBT:15;
    } B;
  } CH2_S2SBR;

  union {                              /* Slot 3 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S3SBT:15;
    } B;
  } CH2_S3SBR;

  union {                              /* Slot 4 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S4SBT:15;
    } B;
  } CH2_S4SBR;

  union {                              /* Slot 5 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S5SBT:15;
    } B;
  } CH2_S5SBR;

  union {                              /* Slot 6 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S6SBT:15;
    } B;
  } CH2_S6SBR;

  union {                              /* Slot n End Boundary Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t SLOT_NO:3;
      vuint32_t  :1;
      vuint32_t SnEBT:15;
    } B;
  } CH2_SnEBR;

  union {                              /* Data Output Block Configuration Register */
    vuint16_t R;
    struct {
      vuint16_t DATA_LENGTH:6;
      vuint16_t DBR_RST:1;
      vuint16_t DSR_RST:1;
      vuint16_t CMD_TYPE:3;
      vuint16_t DEFAULT_SYNC:1;
      vuint16_t GTM_TRIG_SEL:1;
      vuint16_t SP_PULSE_SEL:1;
      vuint16_t OP_SEL:1;
      vuint16_t SW_READY:1;
    } B;
  } CH2_DOBCR;

  union {                              /* Manchestor Decoder Disable Offset */
    vuint16_t R;
    struct {
      vuint16_t  :9;
      vuint16_t MDDIS_OFF:7;
    } B;
  } CH2_MDDIS_OFF;

  union {                              /* Pulse Width for Data Bit Value 0 */
    vuint16_t R;
    struct {
      vuint16_t  :9;
      vuint16_t Pulse_Width0:7;
    } B;
  } CH2_PW0D;

  union {                              /* Pulse Width for Data Bit Value 1 */
    vuint16_t R;
    struct {
      vuint16_t  :9;
      vuint16_t Pulse_Width1:7;
    } B;
  } CH2_PW1D;

  union {                              /* Counter Target Pulse Register */
    vuint16_t R;
    struct {
      vuint16_t CTPR:16;
    } B;
  } CH2_CTPR;

  union {                              /* Counter Initialize Pulse Register */
    vuint16_t R;
    struct {
      vuint16_t CIPR:16;
    } B;
  } CH2_CIPR;

  union {                              /* Data Preparation Register Low */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DPR:24;
    } B;
  } CH2_DPRL;

  union {                              /* Data Preparation Register High */
    vuint32_t R;
    struct {
      vuint32_t  :32;
    } B;
  } CH2_DPRH;

  union {                              /* Data Buffer Register Low */
    vuint32_t R;
    struct {
      vuint32_t DBR:32;
    } B;
  } CH2_DBRL;

  union {                              /* Data Buffer Register High */
    vuint32_t R;
    struct {
      vuint32_t DBR:32;
    } B;
  } CH2_DBRH;

  union {                              /* Data Shift Register Low */
    vuint32_t R;
    struct {
      vuint32_t DSR:32;
    } B;
  } CH2_DSRL;

  union {                              /* Data Shift Register High */
    vuint32_t R;
    struct {
      vuint32_t DSR:32;
    } B;
  } CH2_DSRH;
};


/* ============================================================================
   =============================== Module: PSI5S ==============================
   ============================================================================ */

struct PSI5S_tag {
  union {                              /* PSI5-S LIN Control Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :19;
      vuint32_t AUTOWU:1;
      vuint32_t  :4;
      vuint32_t  :1;
      vuint32_t SLFM:1;
      vuint32_t LBKM:1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t RBLM:1;
      vuint32_t SLEEP:1;
      vuint32_t INIT:1;
    } B;
  } LINCR1;

  union {                              /* PSI5-S LIN Interrupt enable register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SZIE:1;
      vuint32_t OCIE:1;
      vuint32_t  :5;
      vuint32_t FEIE:1;
      vuint32_t BOIE:1;
      vuint32_t  :1;
      vuint32_t WUIE:1;
      vuint32_t  :1;
      vuint32_t TOIE:1;
      vuint32_t DRIE:1;
      vuint32_t DTIE:1;
      vuint32_t  :1;
    } B;
  } LINIER;

  union {                              /* PSI5-S LIN Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t LINS3:1;
      vuint32_t LINS2:1;
      vuint32_t LINS1:1;
      vuint32_t LINS0:1;
      vuint32_t  :5;
      vuint32_t  :1;
      vuint32_t  :6;
    } B;
  } LINSR;

  uint8_t PSI5S_reserved0[4];
  union {                              /* PSI5-S UART Mode Control Register */
    vuint32_t R;
    struct {
      vuint32_t MIS:1;
      vuint32_t CSP:3;
      vuint32_t OSR:4;
      vuint32_t ROSE:1;
      vuint32_t NEF:3;
      vuint32_t PCE_TXDTU:1;
      vuint32_t SBUR:2;
      vuint32_t WLS:1;
      vuint32_t TDFLTFC:3;
      vuint32_t RDFLRFC:3;
      vuint32_t RFBM:1;
      vuint32_t TFBM:1;
      vuint32_t WL1:1;
      vuint32_t PC1:1;
      vuint32_t RxEn:1;
      vuint32_t TxEn:1;
      vuint32_t PC0:1;
      vuint32_t PCE_Rx:1;
      vuint32_t WL0:1;
      vuint32_t UART:1;
    } B;
  } UARTCR;

  union {                              /* PSI5-S UART Mode Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SZF:1;
      vuint32_t OCF:1;
      vuint32_t PE3:1;
      vuint32_t PE2:1;
      vuint32_t PE1:1;
      vuint32_t PE0:1;
      vuint32_t RMB:1;
      vuint32_t FEF:1;
      vuint32_t BOF:1;
      vuint32_t RDI:1;
      vuint32_t WUF:1;
      vuint32_t RFNE:1;
      vuint32_t TO:1;
      vuint32_t DRF:1;
      vuint32_t DTF:1;
      vuint32_t NF:1;
    } B;
  } UARTSR;

  uint8_t PSI5S_reserved1[12];
  union {                              /* PSI5-S LIN Fractional Baud Rate Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t FBR:4;
    } B;
  } LINFBRR;

  union {                              /* PSI5-S LIN Integer Baud Rate Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t IBR:20;
    } B;
  } LINIBRR;

  uint8_t PSI5S_reserved2[4];
  union {                              /* PSI5-S LIN Control Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :17;
      vuint32_t  :1;
      vuint32_t  :4;
      vuint32_t ABRQ:1;
      vuint32_t  :9;
    } B;
  } LINCR2;

  uint8_t PSI5S_reserved3[4];
  union {                              /* PSI5-S Buffer Data Register Least Significant */
    vuint32_t R;
    struct {
      vuint32_t DATA_TX3:8;
      vuint32_t DATA_TX2:8;
      vuint32_t DATA_TX1:8;
      vuint32_t DATA_TX0:8;
    } B;
  } BDRL;

  union {                              /* PSI5-S Buffer Data Register Most Significant */
    vuint32_t R;
    struct {
      vuint32_t DATA_RX3:8;
      vuint32_t DATA_RX2:8;
      vuint32_t DATA_RX1:8;
      vuint32_t DATA_RX0:8;
    } B;
  } BDRM;

  uint8_t PSI5S_reserved4[12];
  union {                              /* PSI5-S Global Control register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t TDFBM:1;
      vuint32_t RDFBM:1;
      vuint32_t TDLIS:1;
      vuint32_t RDLIS:1;
      vuint32_t STOP:1;
      vuint32_t SR:1;
    } B;
  } GCR;

  union {                              /* PSI5-S UART Preset Timeout Register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t PTO:12;
    } B;
  } UARTPTO;

  union {                              /* UPSI5-S ART Current Timeout register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t CTO:12;
    } B;
  } UARTCTO;

  union {                              /* DMA Tx Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t DTE0:1;
    } B;
  } DMATXE;

  union {                              /* DMA Rx Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t DRE0:1;
    } B;
  } DMARXE;

  union {                              /* PSI5-S UART Tx Idle Delay Time Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t IFD:5;
      vuint32_t EN:1;
    } B;
  } PTD;

  uint8_t PSI5S_reserved5[80];
  union {                              /* PSI5-S Global Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DIRCMD_LEN:2;
      vuint32_t  :1;
      vuint32_t IE_DIRCMD_RDY:1;
      vuint32_t  :1;
      vuint32_t DEBUG_EN:1;
      vuint32_t GTM_TRIG_SEL:2;
      vuint32_t GL_DDSR_TRIG:1;
      vuint32_t GL_MODETR_DONE_EN:1;
      vuint32_t MRU_ERR_EN:1;
      vuint32_t TSCS_B:1;
      vuint32_t TSCS_A:1;
      vuint32_t CLR_CNTR_B:1;
      vuint32_t CLR_CNTR_A:1;
      vuint32_t CLRTSCNT_G:1;
      vuint32_t CLRTSCNT_G_L:1;
      vuint32_t TSCNT_EN_B:1;
      vuint32_t TSCNT_EN_A:1;
      vuint32_t TSCNTEN_G:1;
      vuint32_t TSCNTEN_G_L:1;
      vuint32_t GLOBAL_MODE:3;
    } B;
  } GLCR;

  union {                              /* PSI5-S Global Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t DIRCMD_RDY:1;
      vuint32_t  :4;
      vuint32_t GL_MODETR_DONE:1;
      vuint32_t MRU_ERR:1;
      vuint32_t  :7;
      vuint32_t FID:3;
      vuint32_t CHID:3;
    } B;
  } GLSR;

  union {                              /* PSI5-S CHANNEL_BASE_ADDRESS */
    vuint32_t R;
    struct {
      vuint32_t MAILBOX_BASE_ADDR:32;
    } B;
  } CH_BASE_ADDR;

  union {                              /* PSI5-S MRU OUTPUT BUFFER2 REGISTER0 */
    vuint32_t R;
    struct {
      vuint32_t CHANNEL_SPECIFIC_MAILBOX_ADDR:32;
    } B;
  } MRU_BUF2_REG0;

  union {                              /* PSI5-S MRU OUTPUT BUFFER2 REGISTER1 */
    vuint32_t R;
    struct {
      vuint32_t DCI:4;
      vuint32_t  :1;
      vuint32_t R_UVL_ERR:1;
      vuint32_t N_ERR:1;
      vuint32_t CHID:3;
      vuint32_t FID:3;
      vuint32_t R_OVL_ERR:1;
      vuint32_t F_WD_ERR:1;
      vuint32_t SCI_O_ERR:1;
      vuint32_t SCI_F_ERR:1;
      vuint32_t SCI_P_ERR:1;
      vuint32_t HD_ERR:1;
      vuint32_t ERR:2;
      vuint32_t CRC_ERR_P_ERR:1;
      vuint32_t CRC:3;
      vuint32_t XCRC_ERR:1;
      vuint32_t XCRC:6;
    } B;
  } MRU_BUF2_REG1;

  union {                              /* PSI5-S MRU OUTPUT BUFFER2 REGISTER2 */
    vuint32_t R;
    struct {
      vuint32_t DCI:4;
      vuint32_t PS_DATA:28;
    } B;
  } MRU_BUF2_REG2;

  union {                              /* PSI5-S MRU OUTPUT BUFFER2 REGISTER3 */
    vuint32_t R;
    struct {
      vuint32_t DCI:4;
      vuint32_t  :4;
      vuint32_t TIMESTAMP:24;
    } B;
  } MRU_BUF2_REG3;

  union {                              /* PSI5-S Clock Divider "0" for WatchDog and DownStream Data Shift Register Trigger Counters. Used for Channel1 and Channel2 */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t WD_CLKDIV0:10;
      vuint32_t  :6;
      vuint32_t DDTRIG_CLKDIV0:10;
    } B;
  } WD_DDTRIG_CLKDIV0;

  union {                              /* PSI5-S Clock Divider "1" for WatchDog and DownStream Data Shift Register Trigger Counters. Used for Channel3 and Channel4 */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t WD_CLKDIV1:10;
      vuint32_t  :6;
      vuint32_t DDTRIG_CLKDIV1:10;
    } B;
  } WD_DDTRIG_CLKDIV1;

  union {                              /* PSI5-S Clock Divider "2" for WatchDog and DownStream Data Shift Register Trigger Counters. Used for Channel5 and Channel6 */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t WD_CLKDIV2:10;
      vuint32_t  :6;
      vuint32_t DDTRIG_CLKDIV2:10;
    } B;
  } WD_DDTRIG_CLKDIV2;

  union {                              /* PSI5-S Clock Divider "3" for WatchDog and DownStream Data Shift Register Trigger Counters. Used for Channel7 */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t WD_CLKDIV3:10;
      vuint32_t  :6;
      vuint32_t DDTRIG_CLKDIV3:10;
    } B;
  } WD_DDTRIG_CLKDIV3;

  union {                              /* PSI5-S Mbox Status Irq */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t MBOX_CH7:1;
      vuint32_t MBOX_CH6:1;
      vuint32_t MBOX_CH5:1;
      vuint32_t MBOX_CH4:1;
      vuint32_t MBOX_CH3:1;
      vuint32_t MBOX_CH2:1;
      vuint32_t MBOX_CH1:1;
      vuint32_t MBOX_CH0:1;
    } B;
  } MBOX_SR_IRQ;

  union {                              /* PSI5-S Error Status Irq */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t R_UVL_ERR:1;
      vuint32_t N_ERR:1;
      vuint32_t R_OVL_ERR:1;
      vuint32_t F_WD_ERR:1;
      vuint32_t SCI_O_ERR:1;
      vuint32_t SCI_F_ERR:1;
      vuint32_t SCI_P_ERR:1;
      vuint32_t HD_ERR:1;
      vuint32_t CRC_ERR_P_ERR:1;
      vuint32_t XCRC_ERR:1;
    } B;
  } ERR_SR_IRQ;

  struct {
    union {                            /* PSI5-S Mailbox select IRQ[irq_n] */
      vuint32_t R;
      struct {
        vuint32_t  :24;
        vuint32_t MBOX_CH7_SEL:1;
        vuint32_t MBOX_CH6_SEL:1;
        vuint32_t MBOX_CH5_SEL:1;
        vuint32_t MBOX_CH4_SEL:1;
        vuint32_t MBOX_CH3_SEL:1;
        vuint32_t MBOX_CH2_SEL:1;
        vuint32_t MBOX_CH1_SEL:1;
        vuint32_t MBOX_CH0_SEL:1;
      } B;
    } MBOX;
    union {                            /* PSI5-S Error Select IRQ[iq_n] */
      vuint32_t R;
      struct {
        vuint32_t  :22;
        vuint32_t R_UVL_ERR_SEL:1;
        vuint32_t N_ERR_SEL:1;
        vuint32_t R_OVL_ERR_SEL:1;
        vuint32_t F_WD_ERR_SEL:1;
        vuint32_t SCI_O_ERR_SEL:1;
        vuint32_t SCI_F_ERR_SEL:1;
        vuint32_t SCI_P_ERR_SEL:1;
        vuint32_t HD_ERR_SEL:1;
        vuint32_t CRC_ERR_SEL:1;
        vuint32_t XCRC_ERR_SEL:1;
      } B;
    } ERR;
  } SEL_IRQ[8];

  union {                              /* PSI5-S Watchdog Error Status and Watchdog Timestamp status register */
    vuint32_t R;
    struct {
      vuint32_t F_WD_ERR_STATUS:7;
      vuint32_t  :1;
      vuint32_t WDTS_STATUS:24;
    } B;
  } WDGTSSR;

  uint8_t PSI5S_reserved6[64];
  union {                              /* PSI5-S channel 0 message configuration register A */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t F0_BYTE:3;
      vuint32_t  :2;
      vuint32_t TIMESTAMP_A_B_SEL:1;
      vuint32_t  :1;
      vuint32_t TSBUF_CLR:1;
      vuint32_t TSBUF_EN:1;
      vuint32_t  :2;
    } B;
  } MSGA_CH0;

  union {                              /* PSI5-S channel 0 message configuration register B */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t F0_payload:5;
    } B;
  } MSGB_CH0;

  uint8_t PSI5S_reserved7[4];
  union {                              /* PSI5-S Mailbox status register channel0 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t F1_ERR:1;
      vuint32_t F1_OV:1;
      vuint32_t F1_READ:1;
      vuint32_t F0_ERR:1;
      vuint32_t F0_OV:1;
      vuint32_t F0_READ:1;
    } B;
  } MBOX_SR_CH0;

  uint8_t PSI5S_reserved8[20];
  union {                              /* PSI5-S channel message configuration register A */
    vuint32_t R;
    struct {
      vuint32_t L_PC_EN:1;
      vuint32_t F5_BYTE:3;
      vuint32_t L_PC5:1;
      vuint32_t F4_BYTE:3;
      vuint32_t L_PC4:1;
      vuint32_t F3_BYTE:3;
      vuint32_t L_PC3:1;
      vuint32_t F2_BYTE:3;
      vuint32_t L_PC2:1;
      vuint32_t F1_BYTE:3;
      vuint32_t L_PC1:1;
      vuint32_t F0_BYTE:3;
      vuint32_t L_PC0:1;
      vuint32_t MODE:1;
      vuint32_t TIME_STAMP_A_B_SEL:1;
      vuint32_t TMSG_TCMD:1;
      vuint32_t TSBUF_CLR:1;
      vuint32_t TSBUF_EN:1;
      vuint32_t G_PC:1;
      vuint32_t CH_EN:1;
    } B;
  } MSGA_CH1;

  union {                              /* PSI5-S channel message configuration register B */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t F5_payload:5;
      vuint32_t F4_payload:5;
      vuint32_t F3_payload:5;
      vuint32_t F2_payload:5;
      vuint32_t F1_payload:5;
      vuint32_t F0_payload:5;
    } B;
  } MSGB_CH1;

  uint8_t PSI5S_reserved9[4];
  union {                              /* PSI5-S Mailbox status register channel */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t F5_ERR:1;
      vuint32_t F5_OV:1;
      vuint32_t F5_READ:1;
      vuint32_t F4_ERR:1;
      vuint32_t F4_OV:1;
      vuint32_t F4_READ:1;
      vuint32_t F3_ERR:1;
      vuint32_t F3_OV:1;
      vuint32_t F3_READ:1;
      vuint32_t F2_ERR:1;
      vuint32_t F2_OV:1;
      vuint32_t F2_READ:1;
      vuint32_t F1_ERR:1;
      vuint32_t F1_OV:1;
      vuint32_t F1_READ:1;
      vuint32_t F0_ERR:1;
      vuint32_t F0_OV:1;
      vuint32_t F0_READ:1;
    } B;
  } MBOX_SR_CH1;

  union {                              /* PSI5-S channel watchdog configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t WDRST:1;
      vuint32_t WDCS:1;
      vuint32_t WDEN:1;
      vuint32_t  :1;
      vuint32_t WD_TO:24;
    } B;
  } WD_CFGR_CH1;

  union {                              /* PSI5-S DDSR Trigger offset register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_OFFR:16;
    } B;
  } DDTRIG_OFFR_CH1;

  union {                              /* PSI5-S DDSR Trigger period register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_PERR:16;
    } B;
  } DDTRIG_PERR_CH1;

  union {                              /* PSI5-S ECU to Sensor Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t CMD:5;
      vuint32_t  :1;
      vuint32_t ACMD:5;
      vuint32_t  :2;
      vuint32_t CH_TRIG:1;
      vuint32_t GL_TRIG_SEL:1;
      vuint32_t DEFAULT_SYNC:1;
      vuint32_t DDSR_SHIFT_SEL:1;
      vuint32_t DDSR_CLR:1;
      vuint32_t DDSR_CLK_SEL:1;
      vuint32_t CMDTR_SW_CTRL:1;
      vuint32_t  :1;
      vuint32_t SYNCHRO_OVF_IE:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT_IE:1;
      vuint32_t CMDPR_BZY_IE:1;
      vuint32_t DDSR_RDY_IE:1;
      vuint32_t  :2;
      vuint32_t CMD_TYPE:3;
    } B;
  } E2SCR_CH1;

  union {                              /* PSI5-S ECU to Sensor Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t SYCHRO_OVF:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT:1;
      vuint32_t CMDPR_BZY:1;
      vuint32_t DDSR_RDY:1;
      vuint32_t  :5;
    } B;
  } E2SSR_CH1;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t DDSR_H:11;
    } B;
  } DDSR_H_CH1;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
    vuint32_t R;
    struct {
      vuint32_t DDSR_L1:8;
      vuint32_t DDSR_L2:24;
    } B;
  } DDSR_L_CH1;

  uint8_t PSI5S_reserved10[16];
  union {                              /* PSI5-S channel message configuration register A */
    vuint32_t R;
    struct {
      vuint32_t L_PC_EN:1;
      vuint32_t F5_BYTE:3;
      vuint32_t L_PC5:1;
      vuint32_t F4_BYTE:3;
      vuint32_t L_PC4:1;
      vuint32_t F3_BYTE:3;
      vuint32_t L_PC3:1;
      vuint32_t F2_BYTE:3;
      vuint32_t L_PC2:1;
      vuint32_t F1_BYTE:3;
      vuint32_t L_PC1:1;
      vuint32_t F0_BYTE:3;
      vuint32_t L_PC0:1;
      vuint32_t MODE:1;
      vuint32_t TIME_STAMP_A_B_SEL:1;
      vuint32_t TMSG_TCMD:1;
      vuint32_t TSBUF_CLR:1;
      vuint32_t TSBUF_EN:1;
      vuint32_t G_PC:1;
      vuint32_t CH_EN:1;
    } B;
  } MSGA_CH2;

  union {                              /* PSI5-S channel message configuration register B */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t F5_payload:5;
      vuint32_t F4_payload:5;
      vuint32_t F3_payload:5;
      vuint32_t F2_payload:5;
      vuint32_t F1_payload:5;
      vuint32_t F0_payload:5;
    } B;
  } MSGB_CH2;

  uint8_t PSI5S_reserved11[4];
  union {                              /* PSI5-S Mailbox status register channel */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t F5_ERR:1;
      vuint32_t F5_OV:1;
      vuint32_t F5_READ:1;
      vuint32_t F4_ERR:1;
      vuint32_t F4_OV:1;
      vuint32_t F4_READ:1;
      vuint32_t F3_ERR:1;
      vuint32_t F3_OV:1;
      vuint32_t F3_READ:1;
      vuint32_t F2_ERR:1;
      vuint32_t F2_OV:1;
      vuint32_t F2_READ:1;
      vuint32_t F1_ERR:1;
      vuint32_t F1_OV:1;
      vuint32_t F1_READ:1;
      vuint32_t F0_ERR:1;
      vuint32_t F0_OV:1;
      vuint32_t F0_READ:1;
    } B;
  } MBOX_SR_CH2;

  union {                              /* PSI5-S channel watchdog configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t WDRST:1;
      vuint32_t WDCS:1;
      vuint32_t WDEN:1;
      vuint32_t  :1;
      vuint32_t WD_TO:24;
    } B;
  } WD_CFGR_CH2;

  union {                              /* PSI5-S DDSR Trigger offset register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_OFFR:16;
    } B;
  } DDTRIG_OFFR_CH2;

  union {                              /* PSI5-S DDSR Trigger period register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_PERR:16;
    } B;
  } DDTRIG_PERR_CH2;

  union {                              /* PSI5-S ECU to Sensor Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t CMD:5;
      vuint32_t  :1;
      vuint32_t ACMD:5;
      vuint32_t  :2;
      vuint32_t CH_TRIG:1;
      vuint32_t GL_TRIG_SEL:1;
      vuint32_t DEFAULT_SYNC:1;
      vuint32_t DDSR_SHIFT_SEL:1;
      vuint32_t DDSR_CLR:1;
      vuint32_t DDSR_CLK_SEL:1;
      vuint32_t CMDTR_SW_CTRL:1;
      vuint32_t  :1;
      vuint32_t SYNCHRO_OVF_IE:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT_IE:1;
      vuint32_t CMDPR_BZY_IE:1;
      vuint32_t DDSR_RDY_IE:1;
      vuint32_t  :2;
      vuint32_t CMD_TYPE:3;
    } B;
  } E2SCR_CH2;

  union {                              /* PSI5-S ECU to Sensor Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t SYCHRO_OVF:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT:1;
      vuint32_t CMDPR_BZY:1;
      vuint32_t DDSR_RDY:1;
      vuint32_t  :5;
    } B;
  } E2SSR_CH2;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t DDSR_H:11;
    } B;
  } DDSR_H_CH2;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
    vuint32_t R;
    struct {
      vuint32_t DDSR_L1:8;
      vuint32_t DDSR_L2:24;
    } B;
  } DDSR_L_CH2;

  uint8_t PSI5S_reserved12[16];
  union {                              /* PSI5-S channel message configuration register A */
    vuint32_t R;
    struct {
      vuint32_t L_PC_EN:1;
      vuint32_t F5_BYTE:3;
      vuint32_t L_PC5:1;
      vuint32_t F4_BYTE:3;
      vuint32_t L_PC4:1;
      vuint32_t F3_BYTE:3;
      vuint32_t L_PC3:1;
      vuint32_t F2_BYTE:3;
      vuint32_t L_PC2:1;
      vuint32_t F1_BYTE:3;
      vuint32_t L_PC1:1;
      vuint32_t F0_BYTE:3;
      vuint32_t L_PC0:1;
      vuint32_t MODE:1;
      vuint32_t TIME_STAMP_A_B_SEL:1;
      vuint32_t TMSG_TCMD:1;
      vuint32_t TSBUF_CLR:1;
      vuint32_t TSBUF_EN:1;
      vuint32_t G_PC:1;
      vuint32_t CH_EN:1;
    } B;
  } MSGA_CH3;

  union {                              /* PSI5-S channel message configuration register B */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t F5_payload:5;
      vuint32_t F4_payload:5;
      vuint32_t F3_payload:5;
      vuint32_t F2_payload:5;
      vuint32_t F1_payload:5;
      vuint32_t F0_payload:5;
    } B;
  } MSGB_CH3;

  uint8_t PSI5S_reserved13[4];
  union {                              /* PSI5-S Mailbox status register channel */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t F5_ERR:1;
      vuint32_t F5_OV:1;
      vuint32_t F5_READ:1;
      vuint32_t F4_ERR:1;
      vuint32_t F4_OV:1;
      vuint32_t F4_READ:1;
      vuint32_t F3_ERR:1;
      vuint32_t F3_OV:1;
      vuint32_t F3_READ:1;
      vuint32_t F2_ERR:1;
      vuint32_t F2_OV:1;
      vuint32_t F2_READ:1;
      vuint32_t F1_ERR:1;
      vuint32_t F1_OV:1;
      vuint32_t F1_READ:1;
      vuint32_t F0_ERR:1;
      vuint32_t F0_OV:1;
      vuint32_t F0_READ:1;
    } B;
  } MBOX_SR_CH3;

  union {                              /* PSI5-S channel watchdog configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t WDRST:1;
      vuint32_t WDCS:1;
      vuint32_t WDEN:1;
      vuint32_t  :1;
      vuint32_t WD_TO:24;
    } B;
  } WD_CFGR_CH3;

  union {                              /* PSI5-S DDSR Trigger offset register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_OFFR:16;
    } B;
  } DDTRIG_OFFR_CH3;

  union {                              /* PSI5-S DDSR Trigger period register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_PERR:16;
    } B;
  } DDTRIG_PERR_CH3;

  union {                              /* PSI5-S ECU to Sensor Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t CMD:5;
      vuint32_t  :1;
      vuint32_t ACMD:5;
      vuint32_t  :2;
      vuint32_t CH_TRIG:1;
      vuint32_t GL_TRIG_SEL:1;
      vuint32_t DEFAULT_SYNC:1;
      vuint32_t DDSR_SHIFT_SEL:1;
      vuint32_t DDSR_CLR:1;
      vuint32_t DDSR_CLK_SEL:1;
      vuint32_t CMDTR_SW_CTRL:1;
      vuint32_t  :1;
      vuint32_t SYNCHRO_OVF_IE:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT_IE:1;
      vuint32_t CMDPR_BZY_IE:1;
      vuint32_t DDSR_RDY_IE:1;
      vuint32_t  :2;
      vuint32_t CMD_TYPE:3;
    } B;
  } E2SCR_CH3;

  union {                              /* PSI5-S ECU to Sensor Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t SYCHRO_OVF:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT:1;
      vuint32_t CMDPR_BZY:1;
      vuint32_t DDSR_RDY:1;
      vuint32_t  :5;
    } B;
  } E2SSR_CH3;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t DDSR_H:11;
    } B;
  } DDSR_H_CH3;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
    vuint32_t R;
    struct {
      vuint32_t DDSR_L1:8;
      vuint32_t DDSR_L2:24;
    } B;
  } DDSR_L_CH3;

  uint8_t PSI5S_reserved14[16];
  union {                              /* PSI5-S channel message configuration register A */
    vuint32_t R;
    struct {
      vuint32_t L_PC_EN:1;
      vuint32_t F5_BYTE:3;
      vuint32_t L_PC5:1;
      vuint32_t F4_BYTE:3;
      vuint32_t L_PC4:1;
      vuint32_t F3_BYTE:3;
      vuint32_t L_PC3:1;
      vuint32_t F2_BYTE:3;
      vuint32_t L_PC2:1;
      vuint32_t F1_BYTE:3;
      vuint32_t L_PC1:1;
      vuint32_t F0_BYTE:3;
      vuint32_t L_PC0:1;
      vuint32_t MODE:1;
      vuint32_t TIME_STAMP_A_B_SEL:1;
      vuint32_t TMSG_TCMD:1;
      vuint32_t TSBUF_CLR:1;
      vuint32_t TSBUF_EN:1;
      vuint32_t G_PC:1;
      vuint32_t CH_EN:1;
    } B;
  } MSGA_CH4;

  union {                              /* PSI5-S channel message configuration register B */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t F5_payload:5;
      vuint32_t F4_payload:5;
      vuint32_t F3_payload:5;
      vuint32_t F2_payload:5;
      vuint32_t F1_payload:5;
      vuint32_t F0_payload:5;
    } B;
  } MSGB_CH4;

  uint8_t PSI5S_reserved15[4];
  union {                              /* PSI5-S Mailbox status register channel */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t F5_ERR:1;
      vuint32_t F5_OV:1;
      vuint32_t F5_READ:1;
      vuint32_t F4_ERR:1;
      vuint32_t F4_OV:1;
      vuint32_t F4_READ:1;
      vuint32_t F3_ERR:1;
      vuint32_t F3_OV:1;
      vuint32_t F3_READ:1;
      vuint32_t F2_ERR:1;
      vuint32_t F2_OV:1;
      vuint32_t F2_READ:1;
      vuint32_t F1_ERR:1;
      vuint32_t F1_OV:1;
      vuint32_t F1_READ:1;
      vuint32_t F0_ERR:1;
      vuint32_t F0_OV:1;
      vuint32_t F0_READ:1;
    } B;
  } MBOX_SR_CH4;

  union {                              /* PSI5-S channel watchdog configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t WDRST:1;
      vuint32_t WDCS:1;
      vuint32_t WDEN:1;
      vuint32_t  :1;
      vuint32_t WD_TO:24;
    } B;
  } WD_CFGR_CH4;

  union {                              /* PSI5-S DDSR Trigger offset register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_OFFR:16;
    } B;
  } DDTRIG_OFFR_CH4;

  union {                              /* PSI5-S DDSR Trigger period register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_PERR:16;
    } B;
  } DDTRIG_PERR_CH4;

  union {                              /* PSI5-S ECU to Sensor Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t CMD:5;
      vuint32_t  :1;
      vuint32_t ACMD:5;
      vuint32_t  :2;
      vuint32_t CH_TRIG:1;
      vuint32_t GL_TRIG_SEL:1;
      vuint32_t DEFAULT_SYNC:1;
      vuint32_t DDSR_SHIFT_SEL:1;
      vuint32_t DDSR_CLR:1;
      vuint32_t DDSR_CLK_SEL:1;
      vuint32_t CMDTR_SW_CTRL:1;
      vuint32_t  :1;
      vuint32_t SYNCHRO_OVF_IE:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT_IE:1;
      vuint32_t CMDPR_BZY_IE:1;
      vuint32_t DDSR_RDY_IE:1;
      vuint32_t  :2;
      vuint32_t CMD_TYPE:3;
    } B;
  } E2SCR_CH4;

  union {                              /* PSI5-S ECU to Sensor Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t SYCHRO_OVF:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT:1;
      vuint32_t CMDPR_BZY:1;
      vuint32_t DDSR_RDY:1;
      vuint32_t  :5;
    } B;
  } E2SSR_CH4;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t DDSR_H:11;
    } B;
  } DDSR_H_CH4;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
    vuint32_t R;
    struct {
      vuint32_t DDSR_L1:8;
      vuint32_t DDSR_L2:24;
    } B;
  } DDSR_L_CH4;

  uint8_t PSI5S_reserved16[16];
  union {                              /* PSI5-S channel message configuration register A */
    vuint32_t R;
    struct {
      vuint32_t L_PC_EN:1;
      vuint32_t F5_BYTE:3;
      vuint32_t L_PC5:1;
      vuint32_t F4_BYTE:3;
      vuint32_t L_PC4:1;
      vuint32_t F3_BYTE:3;
      vuint32_t L_PC3:1;
      vuint32_t F2_BYTE:3;
      vuint32_t L_PC2:1;
      vuint32_t F1_BYTE:3;
      vuint32_t L_PC1:1;
      vuint32_t F0_BYTE:3;
      vuint32_t L_PC0:1;
      vuint32_t MODE:1;
      vuint32_t TIME_STAMP_A_B_SEL:1;
      vuint32_t TMSG_TCMD:1;
      vuint32_t TSBUF_CLR:1;
      vuint32_t TSBUF_EN:1;
      vuint32_t G_PC:1;
      vuint32_t CH_EN:1;
    } B;
  } MSGA_CH5;

  union {                              /* PSI5-S channel message configuration register B */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t F5_payload:5;
      vuint32_t F4_payload:5;
      vuint32_t F3_payload:5;
      vuint32_t F2_payload:5;
      vuint32_t F1_payload:5;
      vuint32_t F0_payload:5;
    } B;
  } MSGB_CH5;

  uint8_t PSI5S_reserved17[4];
  union {                              /* PSI5-S Mailbox status register channel */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t F5_ERR:1;
      vuint32_t F5_OV:1;
      vuint32_t F5_READ:1;
      vuint32_t F4_ERR:1;
      vuint32_t F4_OV:1;
      vuint32_t F4_READ:1;
      vuint32_t F3_ERR:1;
      vuint32_t F3_OV:1;
      vuint32_t F3_READ:1;
      vuint32_t F2_ERR:1;
      vuint32_t F2_OV:1;
      vuint32_t F2_READ:1;
      vuint32_t F1_ERR:1;
      vuint32_t F1_OV:1;
      vuint32_t F1_READ:1;
      vuint32_t F0_ERR:1;
      vuint32_t F0_OV:1;
      vuint32_t F0_READ:1;
    } B;
  } MBOX_SR_CH5;

  union {                              /* PSI5-S channel watchdog configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t WDRST:1;
      vuint32_t WDCS:1;
      vuint32_t WDEN:1;
      vuint32_t  :1;
      vuint32_t WD_TO:24;
    } B;
  } WD_CFGR_CH5;

  union {                              /* PSI5-S DDSR Trigger offset register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_OFFR:16;
    } B;
  } DDTRIG_OFFR_CH5;

  union {                              /* PSI5-S DDSR Trigger period register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_PERR:16;
    } B;
  } DDTRIG_PERR_CH5;

  union {                              /* PSI5-S ECU to Sensor Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t CMD:5;
      vuint32_t  :1;
      vuint32_t ACMD:5;
      vuint32_t  :2;
      vuint32_t CH_TRIG:1;
      vuint32_t GL_TRIG_SEL:1;
      vuint32_t DEFAULT_SYNC:1;
      vuint32_t DDSR_SHIFT_SEL:1;
      vuint32_t DDSR_CLR:1;
      vuint32_t DDSR_CLK_SEL:1;
      vuint32_t CMDTR_SW_CTRL:1;
      vuint32_t  :1;
      vuint32_t SYNCHRO_OVF_IE:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT_IE:1;
      vuint32_t CMDPR_BZY_IE:1;
      vuint32_t DDSR_RDY_IE:1;
      vuint32_t  :2;
      vuint32_t CMD_TYPE:3;
    } B;
  } E2SCR_CH5;

  union {                              /* PSI5-S ECU to Sensor Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t SYCHRO_OVF:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT:1;
      vuint32_t CMDPR_BZY:1;
      vuint32_t DDSR_RDY:1;
      vuint32_t  :5;
    } B;
  } E2SSR_CH5;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t DDSR_H:11;
    } B;
  } DDSR_H_CH5;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
    vuint32_t R;
    struct {
      vuint32_t DDSR_L1:8;
      vuint32_t DDSR_L2:24;
    } B;
  } DDSR_L_CH5;

  uint8_t PSI5S_reserved18[16];
  union {                              /* PSI5-S channel message configuration register A */
    vuint32_t R;
    struct {
      vuint32_t L_PC_EN:1;
      vuint32_t F5_BYTE:3;
      vuint32_t L_PC5:1;
      vuint32_t F4_BYTE:3;
      vuint32_t L_PC4:1;
      vuint32_t F3_BYTE:3;
      vuint32_t L_PC3:1;
      vuint32_t F2_BYTE:3;
      vuint32_t L_PC2:1;
      vuint32_t F1_BYTE:3;
      vuint32_t L_PC1:1;
      vuint32_t F0_BYTE:3;
      vuint32_t L_PC0:1;
      vuint32_t MODE:1;
      vuint32_t TIME_STAMP_A_B_SEL:1;
      vuint32_t TMSG_TCMD:1;
      vuint32_t TSBUF_CLR:1;
      vuint32_t TSBUF_EN:1;
      vuint32_t G_PC:1;
      vuint32_t CH_EN:1;
    } B;
  } MSGA_CH6;

  union {                              /* PSI5-S channel message configuration register B */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t F5_payload:5;
      vuint32_t F4_payload:5;
      vuint32_t F3_payload:5;
      vuint32_t F2_payload:5;
      vuint32_t F1_payload:5;
      vuint32_t F0_payload:5;
    } B;
  } MSGB_CH6;

  uint8_t PSI5S_reserved19[4];
  union {                              /* PSI5-S Mailbox status register channel */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t F5_ERR:1;
      vuint32_t F5_OV:1;
      vuint32_t F5_READ:1;
      vuint32_t F4_ERR:1;
      vuint32_t F4_OV:1;
      vuint32_t F4_READ:1;
      vuint32_t F3_ERR:1;
      vuint32_t F3_OV:1;
      vuint32_t F3_READ:1;
      vuint32_t F2_ERR:1;
      vuint32_t F2_OV:1;
      vuint32_t F2_READ:1;
      vuint32_t F1_ERR:1;
      vuint32_t F1_OV:1;
      vuint32_t F1_READ:1;
      vuint32_t F0_ERR:1;
      vuint32_t F0_OV:1;
      vuint32_t F0_READ:1;
    } B;
  } MBOX_SR_CH6;

  union {                              /* PSI5-S channel watchdog configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t WDRST:1;
      vuint32_t WDCS:1;
      vuint32_t WDEN:1;
      vuint32_t  :1;
      vuint32_t WD_TO:24;
    } B;
  } WD_CFGR_CH6;

  union {                              /* PSI5-S DDSR Trigger offset register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_OFFR:16;
    } B;
  } DDTRIG_OFFR_CH6;

  union {                              /* PSI5-S DDSR Trigger period register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_PERR:16;
    } B;
  } DDTRIG_PERR_CH6;

  union {                              /* PSI5-S ECU to Sensor Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t CMD:5;
      vuint32_t  :1;
      vuint32_t ACMD:5;
      vuint32_t  :2;
      vuint32_t CH_TRIG:1;
      vuint32_t GL_TRIG_SEL:1;
      vuint32_t DEFAULT_SYNC:1;
      vuint32_t DDSR_SHIFT_SEL:1;
      vuint32_t DDSR_CLR:1;
      vuint32_t DDSR_CLK_SEL:1;
      vuint32_t CMDTR_SW_CTRL:1;
      vuint32_t  :1;
      vuint32_t SYNCHRO_OVF_IE:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT_IE:1;
      vuint32_t CMDPR_BZY_IE:1;
      vuint32_t DDSR_RDY_IE:1;
      vuint32_t  :2;
      vuint32_t CMD_TYPE:3;
    } B;
  } E2SCR_CH6;

  union {                              /* PSI5-S ECU to Sensor Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t SYCHRO_OVF:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT:1;
      vuint32_t CMDPR_BZY:1;
      vuint32_t DDSR_RDY:1;
      vuint32_t  :5;
    } B;
  } E2SSR_CH6;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t DDSR_H:11;
    } B;
  } DDSR_H_CH6;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
    vuint32_t R;
    struct {
      vuint32_t DDSR_L1:8;
      vuint32_t DDSR_L2:24;
    } B;
  } DDSR_L_CH6;

  uint8_t PSI5S_reserved20[16];
  union {                              /* PSI5-S channel message configuration register A */
    vuint32_t R;
    struct {
      vuint32_t L_PC_EN:1;
      vuint32_t F5_BYTE:3;
      vuint32_t L_PC5:1;
      vuint32_t F4_BYTE:3;
      vuint32_t L_PC4:1;
      vuint32_t F3_BYTE:3;
      vuint32_t L_PC3:1;
      vuint32_t F2_BYTE:3;
      vuint32_t L_PC2:1;
      vuint32_t F1_BYTE:3;
      vuint32_t L_PC1:1;
      vuint32_t F0_BYTE:3;
      vuint32_t L_PC0:1;
      vuint32_t MODE:1;
      vuint32_t TIME_STAMP_A_B_SEL:1;
      vuint32_t TMSG_TCMD:1;
      vuint32_t TSBUF_CLR:1;
      vuint32_t TSBUF_EN:1;
      vuint32_t G_PC:1;
      vuint32_t CH_EN:1;
    } B;
  } MSGA_CH7;

  union {                              /* PSI5-S channel message configuration register B */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t F5_payload:5;
      vuint32_t F4_payload:5;
      vuint32_t F3_payload:5;
      vuint32_t F2_payload:5;
      vuint32_t F1_payload:5;
      vuint32_t F0_payload:5;
    } B;
  } MSGB_CH7;

  uint8_t PSI5S_reserved21[4];
  union {                              /* PSI5-S Mailbox status register channel */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t F5_ERR:1;
      vuint32_t F5_OV:1;
      vuint32_t F5_READ:1;
      vuint32_t F4_ERR:1;
      vuint32_t F4_OV:1;
      vuint32_t F4_READ:1;
      vuint32_t F3_ERR:1;
      vuint32_t F3_OV:1;
      vuint32_t F3_READ:1;
      vuint32_t F2_ERR:1;
      vuint32_t F2_OV:1;
      vuint32_t F2_READ:1;
      vuint32_t F1_ERR:1;
      vuint32_t F1_OV:1;
      vuint32_t F1_READ:1;
      vuint32_t F0_ERR:1;
      vuint32_t F0_OV:1;
      vuint32_t F0_READ:1;
    } B;
  } MBOX_SR_CH7;

  union {                              /* PSI5-S channel watchdog configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t WDRST:1;
      vuint32_t WDCS:1;
      vuint32_t WDEN:1;
      vuint32_t  :1;
      vuint32_t WD_TO:24;
    } B;
  } WD_CFGR_CH7;

  union {                              /* PSI5-S DDSR Trigger offset register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_OFFR:16;
    } B;
  } DDTRIG_OFFR_CH7;

  union {                              /* PSI5-S DDSR Trigger period register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_PERR:16;
    } B;
  } DDTRIG_PERR_CH7;

  union {                              /* PSI5-S ECU to Sensor Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t CMD:5;
      vuint32_t  :1;
      vuint32_t ACMD:5;
      vuint32_t  :2;
      vuint32_t CH_TRIG:1;
      vuint32_t GL_TRIG_SEL:1;
      vuint32_t DEFAULT_SYNC:1;
      vuint32_t DDSR_SHIFT_SEL:1;
      vuint32_t DDSR_CLR:1;
      vuint32_t DDSR_CLK_SEL:1;
      vuint32_t CMDTR_SW_CTRL:1;
      vuint32_t  :1;
      vuint32_t SYNCHRO_OVF_IE:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT_IE:1;
      vuint32_t CMDPR_BZY_IE:1;
      vuint32_t DDSR_RDY_IE:1;
      vuint32_t  :2;
      vuint32_t CMD_TYPE:3;
    } B;
  } E2SCR_CH7;

  union {                              /* PSI5-S ECU to Sensor Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t SYCHRO_OVF:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT:1;
      vuint32_t CMDPR_BZY:1;
      vuint32_t DDSR_RDY:1;
      vuint32_t  :5;
    } B;
  } E2SSR_CH7;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t DDSR_H:11;
    } B;
  } DDSR_H_CH7;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
    vuint32_t R;
    struct {
      vuint32_t DDSR_L1:8;
      vuint32_t DDSR_L2:24;
    } B;
  } DDSR_L_CH7;
};


/* ============================================================================
   =============================== Module: REG_PROT ===========================
   ============================================================================ */

struct REG_PROT_tag {
  uint8_t REG_PROT_reserved0[14336];
  union {                              /* Soft Lock Bit Register n */
    vuint8_t R;
    struct {
      vuint8_t WE0:1;                  /* Write Enable Bits for Soft Lock Bits (SLB) */
      vuint8_t WE1:1;                  /* Write Enable Bits for Soft Lock Bits (SLB) */
      vuint8_t WE2:1;                  /* Write Enable Bits for Soft Lock Bits (SLB) */
      vuint8_t WE3:1;                  /* Write Enable Bits for Soft Lock Bits (SLB) */
      vuint8_t SLB0:1;                 /* Soft Lock Bits for one MRn register */
      vuint8_t SLB1:1;                 /* Soft Lock Bits for one MRn register */
      vuint8_t SLB2:1;                 /* Soft Lock Bits for one MRn register */
      vuint8_t SLB3:1;                 /* Soft Lock Bits for one MRn register */
    } B;
  } SLBRn;

  uint8_t REG_PROT_reserved1[2043];
  union {                              /* Global Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t HLB:1;                 /* Hard Lock Bit */
      vuint32_t  :7;
      vuint32_t UAA:1;                 /* User Access Allowed. */
      vuint32_t  :23;
    } B;
  } GCR;
};


/* ============================================================================
   =============================== Module: SARADC =============================
   ============================================================================ */

struct SARADC_tag {
  union {                              /* Main Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t OWREN:1;
      vuint32_t WLSIDE:1;
      vuint32_t MODE:1;
      vuint32_t  :1;
      vuint32_t NSTART:1;
      vuint32_t NTRGEN:1;
      vuint32_t NEDGESEL:2;
      vuint32_t JSTART:1;
      vuint32_t JTRGEN:1;
      vuint32_t JEDGESEL:2;
      vuint32_t JTRGSEQ:1;
      vuint32_t  :1;
      vuint32_t  :2;
      vuint32_t WTRIGOUT:1;
      vuint32_t  :3;
      vuint32_t JTRGSEL:4;
      vuint32_t ABORTCHAIN:1;
      vuint32_t ABORT:1;
      vuint32_t  :1;
      vuint32_t FRZ:1;
      vuint32_t  :2;
      vuint32_t EDCSELF:1;
      vuint32_t PWDN:1;
    } B;
  } MCR;

  union {                              /* Main Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t NSTART:1;
      vuint32_t  :3;
      vuint32_t JSTART:1;
      vuint32_t  :4;
      vuint32_t JABORTCHAIN:1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t CHADDR:8;
      vuint32_t  :5;
      vuint32_t ADCSTATUS:3;
    } B;
  } MSR;

  uint8_t SARADC_reserved0[8];
  union {                              /* Interrupt Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t  :1;
      vuint32_t JEOC:1;
      vuint32_t JECH:1;
      vuint32_t NEOC:1;
      vuint32_t NECH:1;
    } B;
  } ISR;

  union {                              /* Internal channel Interrupt Pending Register */
    vuint32_t R;
    struct {
      vuint32_t EOC_CHx:32;
    } B;
  } ICIPR[3];

  union {                              /* Interrupt Mask Register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t  :1;
      vuint32_t MSKJEOC:1;
      vuint32_t MSKJECH:1;
      vuint32_t MSKNEOC:1;
      vuint32_t MSKNECH:1;
    } B;
  } IMR;

  union {                              /* Internal Channel Interrupt Mask Register */
    vuint32_t R;
    struct {
      vuint32_t IM_CHx:32;
    } B;
  } ICIMR[3];

  union {                              /* Watchdog Threshold Interrupt Status Register */
    vuint32_t R;
    struct {
      vuint32_t WDG15H:1;
      vuint32_t WDG15L:1;
      vuint32_t WDG14H:1;
      vuint32_t WDG14L:1;
      vuint32_t WDG13H:1;
      vuint32_t WDG13L:1;
      vuint32_t WDG12H:1;
      vuint32_t WDG12L:1;
      vuint32_t WDG11H:1;
      vuint32_t WDG11L:1;
      vuint32_t WDG10H:1;
      vuint32_t WDG10L:1;
      vuint32_t WDG9H:1;
      vuint32_t WDG9L:1;
      vuint32_t WDG8H:1;
      vuint32_t WDG8L:1;
      vuint32_t WDG7H:1;
      vuint32_t WDG7L:1;
      vuint32_t WDG6H:1;
      vuint32_t WDG6L:1;
      vuint32_t WDG5H:1;
      vuint32_t WDG5L:1;
      vuint32_t WDG4H:1;
      vuint32_t WDG4L:1;
      vuint32_t WDG3H:1;
      vuint32_t WDG3L:1;
      vuint32_t WDG2H:1;
      vuint32_t WDG2L:1;
      vuint32_t WDG1H:1;
      vuint32_t WDG1L:1;
      vuint32_t WDG0H:1;
      vuint32_t WDG0L:1;
    } B;
  } WTISR;

  union {                              /* Watchdog Threshold Interrupt Mask Register */
    vuint32_t R;
    struct {
      vuint32_t MSKWDG15H:1;
      vuint32_t MSKWDG15L:1;
      vuint32_t MSKWDG14H:1;
      vuint32_t MSKWDG14L:1;
      vuint32_t MSKWDG13H:1;
      vuint32_t MSKWDG13L:1;
      vuint32_t MSKWDG12H:1;
      vuint32_t MSKWDG12L:1;
      vuint32_t MSKWDG11H:1;
      vuint32_t MSKWDG11L:1;
      vuint32_t MSKWDG10H:1;
      vuint32_t MSKWDG10L:1;
      vuint32_t MSKWDG9H:1;
      vuint32_t MSKWDG9L:1;
      vuint32_t MSKWDG8H:1;
      vuint32_t MSKWDG8L:1;
      vuint32_t MSKWDG7H:1;
      vuint32_t MSKWDG7L:1;
      vuint32_t MSKWDG6H:1;
      vuint32_t MSKWDG6L:1;
      vuint32_t MSKWDG5H:1;
      vuint32_t MSKWDG5L:1;
      vuint32_t MSKWDG4H:1;
      vuint32_t MSKWDG4L:1;
      vuint32_t MSKWDG3H:1;
      vuint32_t MSKWDG3L:1;
      vuint32_t MSKWDG2H:1;
      vuint32_t MSKWDG2L:1;
      vuint32_t MSKWDG1H:1;
      vuint32_t MSKWDG1L:1;
      vuint32_t MSKWDG0H:1;
      vuint32_t MSKWDG0L:1;
    } B;
  } WTIMR;

  uint8_t SARADC_reserved1[8];
  union {                              /* DMA Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t DCLR:1;
      vuint32_t DMAEN:1;
    } B;
  } DMAE;

  union {                              /* Internal Channel DMA Select Register */
    vuint32_t R;
    struct {
      vuint32_t DS_CHx:32;
    } B;
  } ICDSR[3];

  uint8_t SARADC_reserved2[16];
  union {                              /* Watchdog Threshold Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t THRH:12;
      vuint32_t  :4;
      vuint32_t THRL:12;
    } B;
  } WTHRHLR[4];

  uint8_t SARADC_reserved3[36];
  union {                              /* Conversion Timing Register */
    vuint32_t R;
    struct {
      vuint32_t CRES:1;
      vuint32_t  :19;
      vuint32_t PRECHG:4;
      vuint32_t INPSAMP:8;
    } B;
  } CTR[4];

  union {                              /* Internal Channel Normal Conversion Mask Register */
    vuint32_t R;
    struct {
      vuint32_t NCE_CHx:32;
    } B;
  } ICNCMR[3];

  uint8_t SARADC_reserved4[4];
  union {                              /* Internal Channel Injected Conversion Mask Register */
    vuint32_t R;
    struct {
      vuint32_t JCE_CH:32;
    } B;
  } ICJCMR[3];

  uint8_t SARADC_reserved5[8];
  union {                              /* Power Down Exit Delay Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t PDED:8;
    } B;
  } PDEDR;

  uint8_t SARADC_reserved6[52];
  union {                              /* Internal Channel Data Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t REFSEL:1;
      vuint32_t  :2;
      vuint32_t PCE:1;
      vuint32_t  :1;
      vuint32_t CTSEL:2;
      vuint32_t  :4;
      vuint32_t VALID:1;
      vuint32_t OVERW:1;
      vuint32_t RESULT:2;
      vuint32_t CDATA:16;
    } B;
  } ICDR[96];

  uint8_t SARADC_reserved7[48];
  union {                              /* Internal Channel Watchdog Selection Register */
    vuint32_t R;
    struct {
      vuint32_t WSEL_CH7:4;
      vuint32_t WSEL_CH6:4;
      vuint32_t WSEL_CH5:4;
      vuint32_t WSEL_CH4:4;
      vuint32_t WSEL_CH3:4;
      vuint32_t WSEL_CH2:4;
      vuint32_t WSEL_CH1:4;
      vuint32_t WSEL_CH0:4;
    } B;
  } ICWSELR[12];

  union {                              /* Internal Channel Watchdog Enable Register */
    vuint32_t R;
    struct {
      vuint32_t WEN_CHx:32;
    } B;
  } ICWENR[3];

  uint8_t SARADC_reserved8[4];
  union {                              /* Internal Channel Analog Watchdog Out of Range register */
    vuint32_t R;
    struct {
      vuint32_t AWOR_CHx:32;
    } B;
  } ICAWORR[3];

  uint8_t SARADC_reserved9[260];
  union {                              /* Test Channel Interrupt Pending Register */
    vuint32_t R;
    struct {
      vuint32_t EOC_CHx:32;
    } B;
  } TCIPR;

  union {                              /* Test Channel Interrupt Mask Register */
    vuint32_t R;
    struct {
      vuint32_t IM_CHx:32;
    } B;
  } TCIMR;

  union {                              /* Test Channel DMA Select Register */
    vuint32_t R;
    struct {
      vuint32_t DS_CHx:32;
    } B;
  } TCDSR;

  union {                              /* Test Channel Normal Conversion Mask Register */
    vuint32_t R;
    struct {
      vuint32_t NCE_CHx:32;
    } B;
  } TCNCMR;

  union {                              /* Test Channel Injected Conversion Mask Register */
    vuint32_t R;
    struct {
      vuint32_t JCE_CHx:32;
    } B;
  } TCJCMR;

  union {                              /* Test Channel Watchdog Selection Register */
    vuint32_t R;
    struct {
      vuint32_t WSEL_CHa:4;
      vuint32_t WSEL_CHb:4;
      vuint32_t WSEL_CHc:4;
      vuint32_t WSEL_CHd:4;
      vuint32_t WSEL_CHe:4;
      vuint32_t WSEL_CHf:4;
      vuint32_t WSEL_CHg:4;
      vuint32_t WSEL_CHh:4;
    } B;
  } TCWSELR[4];

  union {                              /* Test Channel Watchdog Enable Register */
    vuint32_t R;
    struct {
      vuint32_t WEN_CHx:32;
    } B;
  } TCWENR;

  union {                              /* Test Channel Analog Watchdog Out of Range Register */
    vuint32_t R;
    struct {
      vuint32_t AWOR_CHx:32;
    } B;
  } TCAWORR;

  uint8_t SARADC_reserved10[4];
  union {                              /* Test Channel Connection with Analog Pin Register */
    vuint32_t R;
    struct {
      vuint32_t ESIC_TCH3:1;
      vuint32_t ICSEL_TCH3:7;
      vuint32_t ESIC_TCH2:1;
      vuint32_t ICSEL_TCH2:7;
      vuint32_t ESIC_TCH1:1;
      vuint32_t ICSEL_TCH1:7;
      vuint32_t ESIC_TCH0:1;
      vuint32_t ICSEL_TCH0:7;
    } B;
  } TCCAPR[8];

  union {                              /* Test Channel Data Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t REFSEL:1;
      vuint32_t  :2;
      vuint32_t PCE:1;
      vuint32_t  :1;
      vuint32_t CTSEL:2;
      vuint32_t  :4;
      vuint32_t VALID:1;
      vuint32_t OVERW:1;
      vuint32_t RESULT:2;
      vuint32_t CDATA:16;
    } B;
  } TCDR[32];

  uint8_t SARADC_reserved11[48];
  union {                              /* External Channel Decode Signals Delay Register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t DSD:12;
    } B;
  } ECDSDR;

  uint8_t SARADC_reserved12[12];
  union {                              /* External Channel Interrupt Pending Register */
    vuint32_t R;
    struct {
      vuint32_t EOC_CHx:32;
    } B;
  } ECIPR[4];

  union {                              /* External Channel Interrupt Mask Register */
    vuint32_t R;
    struct {
      vuint32_t IM_CHx:32;
    } B;
  } ECIMR[4];

  union {                              /* External Channel DMA Select Register */
    vuint32_t R;
    struct {
      vuint32_t DS_CHx:32;
    } B;
  } ECDSR[4];

  union {                              /* External Channel Normal Conversion Mask Register */
    vuint32_t R;
    struct {
      vuint32_t NCE_CHx:32;
    } B;
  } ECNCMR[4];

  union {                              /* External Channel Injected Conversion Mask Register */
    vuint32_t R;
    struct {
      vuint32_t JCE_CHx:32;
    } B;
  } ECJCMR[4];

  union {                              /* External Channel Watchdog Selection Register */
    vuint32_t R;
    struct {
      vuint32_t WSEL_CHa:4;
      vuint32_t WSEL_CHb:4;
      vuint32_t WSEL_CHc:4;
      vuint32_t WSEL_CHd:4;
      vuint32_t WSEL_CHe:4;
      vuint32_t WSEL_CHf:4;
      vuint32_t WSEL_CHg:4;
      vuint32_t WSEL_CHh:4;
    } B;
  } ECWSELR[16];

  union {                              /* External Channel Watchdog Enable Register */
    vuint32_t R;
    struct {
      vuint32_t WEN_CHx:32;
    } B;
  } ECWENR[4];

  union {                              /* External Channel Analog Watchdog Out of Range register */
    vuint32_t R;
    struct {
      vuint32_t AWOR_CHx:32;
    } B;
  } ECAWORR[4];

  union {                              /* External Channel Mapping to Internal Channel Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t ICSEL_ECH152_159:7;
      vuint32_t  :1;
      vuint32_t ICSEL_ECH144_151:7;
      vuint32_t  :1;
      vuint32_t ICSEL_ECH136_143:7;
      vuint32_t  :1;
      vuint32_t ICSEL_ECH128_135:7;
    } B;
  } ECMICR[4];

  union {                              /* External Channel Data Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t REFSEL:1;
      vuint32_t  :2;
      vuint32_t PCE:1;
      vuint32_t  :1;
      vuint32_t CTSEL:2;
      vuint32_t  :4;
      vuint32_t VALID:1;
      vuint32_t OVERW:1;
      vuint32_t RESULT:2;
      vuint32_t CDATA:16;
    } B;
  } ECDR[128];
};


/* ============================================================================
   =============================== Module: SDADC ==============================
   ============================================================================ */

struct SDADC_tag {
  union {                              /* Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t PDR:5;
      vuint32_t  :1;
      vuint32_t PGAN:3;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t EMSEL:1;
      vuint32_t HPFEN:1;
      vuint32_t WDGEN:1;
      vuint32_t TRIGEDSEL:2;
      vuint32_t TRIGEN:1;
      vuint32_t TRIGSEL:4;
      vuint32_t FRZ:1;
      vuint32_t  :2;
      vuint32_t VCOMSEL:1;
      vuint32_t WRMODE:1;
      vuint32_t GECEN:1;               /* Accurate Gain Error Mode Enable */
      vuint32_t MODE:1;
      vuint32_t EN:1;
    } B;
  } MCR;

  union {                              /* Channel Selection Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t BIASEN:8;
      vuint32_t  :5;
      vuint32_t ANCHSEL_WRAP:3;
      vuint32_t  :5;
      vuint32_t ANCHSEL:3;
    } B;
  } CSR;

  union {                              /* Reset Key Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t RESET_KEY:16;
    } B;
  } RKR;

  union {                              /* Status Flag Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t ANCHSEL_CNT:3;
      vuint32_t  :7;
      vuint32_t DFEF:1;
      vuint32_t  :3;
      vuint32_t WTHH:1;
      vuint32_t WTHL:1;
      vuint32_t CDVF:1;
      vuint32_t DFORF:1;
      vuint32_t DFFF:1;
    } B;
  } SFR;

  union {                              /* Request Select and Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t WTHDIRS:1;
      vuint32_t DFFDIRS:1;
      vuint32_t GDIGE:1;
      vuint32_t  :11;
      vuint32_t WTHDIRE:1;
      vuint32_t CDVEE:1;
      vuint32_t DFORIE:1;
      vuint32_t DFFDIRE:1;
    } B;
  } RSER;

  union {                              /* Output Settling Delay Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t OSD:8;
    } B;
  } OSDR;

  union {                              /* FIFO Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t FRST:1;
      vuint32_t  :3;
      vuint32_t FTHLD:5;
      vuint32_t  :4;
      vuint32_t FOWEN:1;
      vuint32_t FSIZE:2;
      vuint32_t FE:1;
    } B;
  } FCR;

  union {                              /* Software Trigger Key Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t ST_KEY:16;
    } B;
  } STKR;

  union {                              /* Converted Data Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CDATA:16;
    } B;
  } CDR;

  union {                              /* WDG Threshold Register */
    vuint32_t R;
    struct {
      vuint32_t THRH:16;
      vuint32_t THRL:16;
    } B;
  } WTHHLR;
};


/* ============================================================================
   =============================== Module: SEMA42 =============================
   ============================================================================ */

struct SEMA42_tag {
  union {                              /* Gate Register */
    vuint8_t R;
    struct {
      vuint8_t  :4;
      vuint8_t GTFSM:4;                /* [BLG_SEMA42_0001] [Covers: ADD06.057] Gate Finite State Machine. [end] */
    } B;
  } GATE[16];

  uint8_t SEMA42_reserved0[48];
  union {
    union {                            /* Reset Gate Read */
      vuint16_t R;
      struct {
        vuint16_t  :2;
        vuint16_t RSTGSM:2;
        vuint16_t RSTGMS:4;
        vuint16_t RSTGTN:8;
      } B;
    } R;
    union {                            /* Reset Gate Write */
      vuint16_t R;
      struct {
        vuint16_t RSTGDP:8;
        vuint16_t RSTGTN:8;
      } B;
    } W;
  } RSTGT;
};


/* ============================================================================
   =============================== Module: SIPI ===============================
   ============================================================================ */

struct SIPI_tag {
  union {                              /* SIPI Channel Control Register 0 */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t TC:1;                  /* Send Trigger Command. */
      vuint32_t  :8;
      vuint32_t WL:2;                  /* Word Length Transfer. */
      vuint32_t CHEN:1;                /* Channel Enable. */
      vuint32_t ST:1;                  /* Streaming Transfer. */
      vuint32_t IDT:1;                 /* ID Read Request Transfer. */
      vuint32_t RRT:1;                 /* Read Request Transfer. */
      vuint32_t WRT:1;                 /* Write Request Transfer. */
      vuint32_t DEN:1;                 /* DMA Enable. */
    } B;
  } CCR0;

  union {                              /* SIPI Channel Status Register 0 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t RAR:1;
      vuint32_t TID:3;                 /* Transaction ID of transmitted frame. */
      vuint32_t ACKR:1;
      vuint32_t CB:1;                  /* Channel Busy. */
      vuint32_t  :2;
    } B;
  } CSR0;

  uint8_t SIPI_reserved0[4];
  union {                              /* SIPI Channel Interrupt Register 0 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t WAIE:1;                /* Write Acknowledge Interrupt Enable. */
      vuint32_t RAIE:1;                /* Read Answer Interrupt Enable. */
      vuint32_t TCIE:1;                /* Trigger Command Interrupt Enable. */
      vuint32_t TOIE:1;                /* Timeout Error Interrupt Enabled. */
      vuint32_t TIDIE:1;               /* Transaction ID Error Interrupt Enable. */
      vuint32_t ACKIE:1;               /* Acknowledge Error Interrupt Enable. */
    } B;
  } CIR0;

  union {                              /* SIPI Channel Timeout Register 0 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t TOR:8;                 /* Timeout value for transmitted requests. */
    } B;
  } CTOR0;

  union {                              /* SIPI Channel CRC Register 0 */
    vuint32_t R;
    struct {
      vuint32_t CRCI:16;
      vuint32_t CRCT:16;
    } B;
  } CCRC0;

  union {                              /* SIPI Channel Address Register 0 */
    vuint32_t R;
    struct {
      vuint32_t CAR:32;
    } B;
  } CAR0;

  union {                              /* SIPI Channel Data Register 0 */
    vuint32_t R;
    struct {
      vuint32_t CDR:32;
    } B;
  } CDR0;

  union {                              /* SIPI Channel Control Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t TC:1;                  /* Send Trigger Command. */
      vuint32_t  :8;
      vuint32_t WL:2;                  /* Word Length Transfer. */
      vuint32_t CHEN:1;                /* Channel Enable. */
      vuint32_t ST:1;
      vuint32_t IDT:1;                 /* ID Read Request Transfer. */
      vuint32_t RRT:1;
      vuint32_t WRT:1;                 /* Write Request Transfer. */
      vuint32_t DEN:1;                 /* DMA Enable. */
    } B;
  } CCR1;

  union {                              /* SIPI Channel Status Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t RAR:1;
      vuint32_t TID:3;
      vuint32_t ACKR:1;
      vuint32_t CB:1;                  /* Channel Busy. */
      vuint32_t  :2;
    } B;
  } CSR1;

  uint8_t SIPI_reserved1[4];
  union {                              /* SIPI Channel Interrupt Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t WAIE:1;
      vuint32_t RAIE:1;
      vuint32_t TCIE:1;
      vuint32_t TOIE:1;
      vuint32_t TIDIE:1;
      vuint32_t ACKIE:1;
    } B;
  } CIR1;

  union {                              /* SIPI Channel Timeout Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t TOR:8;                 /* Timeout value for transmitted requests. */
    } B;
  } CTOR1;

  union {                              /* SIPI Channel CRC Register 1 */
    vuint32_t R;
    struct {
      vuint32_t CRCI:16;
      vuint32_t CRCT:16;
    } B;
  } CCRC1;

  union {                              /* SIPI Channel Address Register 1 */
    vuint32_t R;
    struct {
      vuint32_t CAR:32;
    } B;
  } CAR1;

  union {                              /* SIPI Channel Data Register 1 */
    vuint32_t R;
    struct {
      vuint32_t CDR:32;
    } B;
  } CDR1;

  union {                              /* SIPI Channel Control Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t TC:1;                  /* Send Trigger Command. */
      vuint32_t  :8;
      vuint32_t WL:2;                  /* Word Length Transfer. */
      vuint32_t CHEN:1;                /* Channel Enable. */
      vuint32_t ST:1;
      vuint32_t IDT:1;                 /* ID Read Request Transfer. */
      vuint32_t RRT:1;                 /* Read Request Transfer. */
      vuint32_t WRT:1;
      vuint32_t DEN:1;                 /* DMA Enable. */
    } B;
  } CCR2;

  union {                              /* SIPI Channel Status Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t RAR:1;
      vuint32_t TID:3;                 /* Transaction ID of transmitted frame. */
      vuint32_t ACKR:1;
      vuint32_t CB:1;                  /* Channel Busy. */
      vuint32_t  :2;
    } B;
  } CSR2;

  uint8_t SIPI_reserved2[4];
  union {                              /* SIPI Channel Interrupt Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t WAIE:1;
      vuint32_t RAIE:1;
      vuint32_t TCIE:1;
      vuint32_t TOIE:1;
      vuint32_t TIDIE:1;
      vuint32_t ACKIE:1;
    } B;
  } CIR2;

  union {                              /* SIPI Channel Timeout Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t TOR:8;
    } B;
  } CTOR2;

  union {                              /* SIPI Channel CRC Register 2 */
    vuint32_t R;
    struct {
      vuint32_t CRCI:16;
      vuint32_t CRCT:16;
    } B;
  } CCRC2;

  union {                              /* SIPI Channel Address Register 2 */
    vuint32_t R;
    struct {
      vuint32_t CAR:32;
    } B;
  } CAR2;

  union {                              /* SIPI Channel Data Register 2 */
    vuint32_t R;
    struct {
      vuint32_t CDR2:32;
    } B;
  } CDR2[8];

  union {                              /* SIPI Channel Control Register 3 */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t TC:1;                  /* Send Trigger Command. */
      vuint32_t  :8;
      vuint32_t WL:2;                  /* Word Length Transfer. */
      vuint32_t CHEN:1;                /* Channel Enable. */
      vuint32_t ST:1;                  /* Streaming Transfer. */
      vuint32_t IDT:1;                 /* ID Read Request Transfer. */
      vuint32_t RRT:1;                 /* Read Request Transfer. */
      vuint32_t WRT:1;                 /* Write Request Transfer. */
      vuint32_t DEN:1;                 /* DMA Enable. */
    } B;
  } CCR3;

  union {                              /* SIPI Channel Status Register 3 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t RAR:1;
      vuint32_t TID:3;                 /* Transaction ID of transmitted frame. */
      vuint32_t ACKR:1;
      vuint32_t CB:1;                  /* Channel Busy. */
      vuint32_t  :2;
    } B;
  } CSR3;

  uint8_t SIPI_reserved3[4];
  union {                              /* SIPI Channel Interrupt Register 3 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t WAIE:1;
      vuint32_t RAIE:1;
      vuint32_t TCIE:1;
      vuint32_t TOIE:1;
      vuint32_t TIDIE:1;
      vuint32_t ACKIE:1;
    } B;
  } CIR3;

  union {                              /* SIPI Channel Timeout Register 3 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t TOR:8;                 /* Timeout value for transmitted requests. */
    } B;
  } CTOR3;

  union {                              /* SIPI Channel CRC Register 3 */
    vuint32_t R;
    struct {
      vuint32_t CRCI:16;
      vuint32_t CRCT:16;
    } B;
  } CCRC3;

  union {                              /* SIPI Channel Address Register 3 */
    vuint32_t R;
    struct {
      vuint32_t CAR:32;
    } B;
  } CAR3;

  union {                              /* SIPI Channel Data Register 3 */
    vuint32_t R;
    struct {
      vuint32_t CDR:32;
    } B;
  } CDR3;

  union {                              /* SIPI Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t FRZ:1;                 /* Freeze Enable */
      vuint32_t  :1;
      vuint32_t HALT:1;                /* Halt Mode Enable */
      vuint32_t  :2;
      vuint32_t PRSCLR:11;             /* Timeout counter prescaler */
      vuint32_t AID:2;                 /* Address Increment/Decrement */
      vuint32_t  :3;
      vuint32_t CRCIE:1;               /* CRC Error Interrupt Enable */
      vuint32_t MCRIE:1;               /* Max Count Reached Interrupt Enable */
      vuint32_t  :4;
      vuint32_t CHNSB:1;               /* Channel coding select bit. */
      vuint32_t TEN:1;                 /* Target Enable */
      vuint32_t INIT:1;                /* Initialization Mode */
      vuint32_t MOEN:1;                /* Module Enable */
      vuint32_t SR:1;                  /* Soft Reset */
    } B;
  } MCR;

  union {                              /* SIPI Status Register */
    vuint32_t R;
    struct {
      vuint32_t FRZACK:1;
      vuint32_t LPMACK:1;              /* Low Power Mode Acknowledge. */
      vuint32_t  :19;
      vuint32_t GCRCE:1;
      vuint32_t MCR:1;                 /* Maximum Count Reached. */
      vuint32_t  :1;
      vuint32_t TE:4;
      vuint32_t STATE:4;
    } B;
  } SR;

  union {                              /* SIPI Max Count Register */
    vuint32_t R;
    struct {
      vuint32_t MXCNT:30;
      vuint32_t  :2;
    } B;
  } MAXCR;

  union {                              /* SIPI Address Reload Register */
    vuint32_t R;
    struct {
      vuint32_t ADRLD:30;
      vuint32_t  :2;
    } B;
  } ARR;

  union {                              /* SIPI Address Count Register */
    vuint32_t R;
    struct {
      vuint32_t ADCNT:30;              /* Feflects the count value of address counter at target node. */
      vuint32_t  :2;
    } B;
  } ACR;

  union {                              /* SIPI Error Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t TOE3:1;
      vuint32_t TIDE3:1;
      vuint32_t ACKE3:1;
      vuint32_t  :5;
      vuint32_t TOE2:1;
      vuint32_t TIDE2:1;
      vuint32_t ACKE2:1;
      vuint32_t  :5;
      vuint32_t TOE1:1;
      vuint32_t TIDE1:1;
      vuint32_t ACKE1:1;
      vuint32_t  :5;
      vuint32_t TOE0:1;
      vuint32_t TIDE0:1;
      vuint32_t ACKE0:1;
    } B;
  } ERR;
};


/* ============================================================================
   =============================== Module: SIUL2 ==============================
   ============================================================================ */

struct SIUL2_tag {
  uint8_t SIUL2_reserved0[4];
  union {                              /* MCU ID Register #1 */
    vuint32_t R;
    struct {
      vuint32_t PARTNUM:16;
      vuint32_t ED:1;
      vuint32_t PKG:5;
      vuint32_t  :2;
      vuint32_t MAJOR_MASK:4;
      vuint32_t MINOR_MASK:4;
    } B;
  } MIDR1;

  union {                              /* MCU ID Register #2 */
    vuint32_t R;
    struct {
      vuint32_t SF:1;
      vuint32_t FLASH_SIZE_1:4;
      vuint32_t FLASH_SIZE_2:4;
      vuint32_t  :7;
      vuint32_t FAMILYNUM:8;
      vuint32_t  :8;
    } B;
  } MIDR2;

  uint8_t SIUL2_reserved1[4];
  union {                              /* DMA/Interrupt Status Flag Register0 */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t EIF11:1;
      vuint32_t EIF10:1;
      vuint32_t EIF9:1;
      vuint32_t EIF8:1;
      vuint32_t  :2;
      vuint32_t EIF5:1;
      vuint32_t EIF4:1;
      vuint32_t EIF3:1;
      vuint32_t EIF2:1;
      vuint32_t EIF1:1;
      vuint32_t EIF0:1;
    } B;
  } DISR0;

  uint8_t SIUL2_reserved2[4];
  union {                              /* DMA/Interrupt Request Enable Register0 */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t EIRE11:1;
      vuint32_t EIRE10:1;
      vuint32_t EIRE9:1;
      vuint32_t EIRE8:1;
      vuint32_t  :2;
      vuint32_t EIRE5:1;
      vuint32_t EIRE4:1;
      vuint32_t EIRE3:1;
      vuint32_t EIRE2:1;
      vuint32_t EIRE1:1;
      vuint32_t EIRE0:1;
    } B;
  } DIRER0;

  uint8_t SIUL2_reserved3[4];
  union {                              /* DMA/Interrupt Request Select Register0 */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t DIRS11:1;
      vuint32_t DIRS10:1;
      vuint32_t DIRS9:1;
      vuint32_t DIRS8:1;
      vuint32_t  :2;
      vuint32_t DIRS5:1;
      vuint32_t DIRS4:1;
      vuint32_t DIRS3:1;
      vuint32_t DIRS2:1;
      vuint32_t DIRS1:1;
      vuint32_t DIRS0:1;
    } B;
  } DIRSR0;

  uint8_t SIUL2_reserved4[4];
  union {                              /* Interrupt Rising-Edge Event Enable Register0 */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t IREE11:1;
      vuint32_t IREE10:1;
      vuint32_t IREE9:1;
      vuint32_t IREE8:1;
      vuint32_t  :2;
      vuint32_t IREE5:1;
      vuint32_t IREE4:1;
      vuint32_t IREE3:1;
      vuint32_t IREE2:1;
      vuint32_t IREE1:1;
      vuint32_t IREE0:1;
    } B;
  } IREER0;

  uint8_t SIUL2_reserved5[4];
  union {                              /* Interrupt Falling-Edge Event Enable Register0 */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t IFEE11:1;
      vuint32_t IFEE10:1;
      vuint32_t IFEE9:1;
      vuint32_t IFEE8:1;
      vuint32_t  :2;
      vuint32_t IFEE5:1;
      vuint32_t IFEE4:1;
      vuint32_t IFEE3:1;
      vuint32_t IFEE2:1;
      vuint32_t IFEE1:1;
      vuint32_t IFEE0:1;
    } B;
  } IFEER0;

  uint8_t SIUL2_reserved6[4];
  union {                              /* Interrupt Filter Enable Register0 */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t IFE11:1;
      vuint32_t IFE10:1;
      vuint32_t IFE9:1;
      vuint32_t IFE8:1;
      vuint32_t  :2;
      vuint32_t IFE5:1;
      vuint32_t IFE4:1;
      vuint32_t IFE3:1;
      vuint32_t IFE2:1;
      vuint32_t IFE1:1;
      vuint32_t IFE0:1;
    } B;
  } IFER0;

  uint8_t SIUL2_reserved7[4];
  union {                              /* Interrupt Filter Maximum Counter Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t MAXCNTx:4;
    } B;
  } IFMCR[32];

  union {                              /* Interrupt Filter Clock Prescaler */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t IFCP:4;
    } B;
  } IFCPR;

  uint8_t SIUL2_reserved8[60];
  union {                              /* SoC Configuration Register0 */
    vuint32_t R;
    struct {
      vuint32_t FEC_MODE:1;
      vuint32_t  :7;
      vuint32_t ESR0_ASSERT:1;
      vuint32_t  :23;
    } B;
  } SCR0;

  uint8_t SIUL2_reserved9[316];
  union {                              /* I/O Pin Multiplexed Signal Configuration Registers */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t OERC:3;
      vuint32_t  :1;
      vuint32_t ODC:3;
      vuint32_t SMC:1;
      vuint32_t APC:1;
      vuint32_t ILS:2;
      vuint32_t IBE:1;
      vuint32_t HYS:1;
      vuint32_t WPDE:1;
      vuint32_t WPUE:1;
      vuint32_t INV:1;
      vuint32_t  :7;
      vuint32_t SSS:8;
    } B;
  } MSCR_IO[512];

  union {                              /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t INV:1;
      vuint32_t  :7;
      vuint32_t SSS:8;
    } B;
  } MSCR_MUX[512];

  uint8_t SIUL2_reserved10[192];
  union {                              /* GPIO Pad Data Out Register */
    vuint8_t R;
    struct {
      vuint8_t  :7;
      vuint8_t PDO:1;
    } B;
  } GPDO[512];

  union {                              /* GPIO Pad Data In Register */
    vuint8_t R;
    struct {
      vuint8_t  :7;
      vuint8_t PDI:1;
    } B;
  } GPDI[512];

  union {                              /* Parallel GPIO Pad Data Out Register */
    vuint16_t R;
    struct {
      vuint16_t PPDO:16;
    } B;
  } PGPDO[32];

  union {                              /* Parallel GPIO Pad Data In Register */
    vuint16_t R;
    struct {
      vuint16_t PPDI:16;
    } B;
  } PGPDI[32];

  union {                              /* Masked Parallel GPIO Pad Data Out Register */
    vuint32_t R;
    struct {
      vuint32_t MASK:16;
      vuint32_t MPPDO:16;
    } B;
  } MPGPDO[32];
};


/* ============================================================================
   =============================== Module: SMPU ===============================
   ============================================================================ */

struct SMPU_tag {
  union {                              /* Control/Error Status Register 0 */
    vuint32_t R;
    struct {
      vuint32_t MERR:16;
      vuint32_t  :1;
      vuint32_t  :11;
      vuint32_t HRL:3;
      vuint32_t GVLD:1;
    } B;
  } CESR0;

  union {                              /* Control/Error Status Register 1 */
    vuint32_t R;
    struct {
      vuint32_t MEOVR:16;
      vuint32_t  :1;
      vuint32_t  :11;
      vuint32_t NRGD:4;
    } B;
  } CESR1;

  uint8_t SMPU_reserved0[248];
  struct {
    union {                            /* Error Address Register, Bus Master n */
      vuint32_t R;
      struct {
        vuint32_t EADDR:32;
      } B;
    } EAR;
    union {                            /* Error Detail Register, Bus Master n */
      vuint32_t R;
      struct {
        vuint32_t EACD:24;
        vuint32_t  :1;
        vuint32_t EATTR:2;
        vuint32_t ERW:1;
        vuint32_t EMN:4;
      } B;
    } EDR;
  } ERROR[16];

  uint8_t SMPU_reserved1[640];
  struct {
    union {                            /* Region Descriptor n, Word 0 */
      vuint32_t R;
      struct {
        vuint32_t SRTADDR:32;
      } B;
    } WORD0;
    union {                            /* Region Descriptor n, Word 1 */
      vuint32_t R;
      struct {
        vuint32_t ENDADDR:32;
      } B;
    } WORD1;
    union {                            /* Region Descriptor n, Word 2 Format 0 */
      vuint32_t R;
      struct {
        vuint32_t M0P:2;
        vuint32_t M1P:2;
        vuint32_t M2P:2;
        vuint32_t M3P:2;
        vuint32_t M4P:2;
        vuint32_t M5P:2;
        vuint32_t M6P:2;
        vuint32_t M7P:2;
        vuint32_t M8P:2;
        vuint32_t M9P:2;
        vuint32_t M10P:2;
        vuint32_t M11P:2;
        vuint32_t M12P:2;
        vuint32_t M13P:2;
        vuint32_t M14P:2;
        vuint32_t M15P:2;
      } B;
    } WORD2;
    union {                            /* Region Descriptor n, Word 3 */
      vuint32_t R;
      struct {
        vuint32_t  :27;
        vuint32_t FMT:1;
        vuint32_t RO:1;
        vuint32_t  :1;
        vuint32_t CI:1;
        vuint32_t VLD:1;
      } B;
    } WORD3;
  } RGD[12];
};


/* ============================================================================
   =============================== Module: SRX ================================
   ============================================================================ */

struct SRX_tag {
  union {                              /* Global Control Register */
    vuint32_t R;
    struct {
      vuint32_t TSPRSC:8;
      vuint32_t  :8;
      vuint32_t  :1;
      vuint32_t  :5;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t FAST_CLR:1;
      vuint32_t  :1;
      vuint32_t DBG_FRZ:1;
      vuint32_t  :1;
      vuint32_t SENT_EN:1;
    } B;
  } GBL_CTRL;

  union {                              /* Channel Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t EN_CH:8;
    } B;
  } CHNL_EN;

  union {                              /* Global Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t FMDU:1;
      vuint32_t SMDU:1;
      vuint32_t  :8;
    } B;
  } GBL_STATUS;

  union {                              /* Fast Message Ready Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t F_RDY:8;
    } B;
  } FMSG_RDY;

  union {                              /* Slow Serial Message Ready Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t S_RDY:8;
    } B;
  } SMSG_RDY;

  uint8_t SRX_reserved0[4];
  union {                              /* Data Control Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t NIBBCH0:3;
      vuint32_t  :1;
      vuint32_t NIBBCH1:3;
      vuint32_t  :1;
      vuint32_t NIBBCH2:3;
      vuint32_t  :1;
      vuint32_t NIBBCH3:3;
      vuint32_t  :1;
      vuint32_t NIBBCH4:3;
      vuint32_t  :1;
      vuint32_t NIBBCH5:3;
      vuint32_t  :1;
      vuint32_t NIBBCH6:3;
      vuint32_t  :1;
      vuint32_t NIBBCH7:3;
    } B;
  } DATA_CTRL1;

  uint8_t SRX_reserved1[12];
  union {                              /* Fast Message DMA Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t FDMA_EN:8;
    } B;
  } FDMA_CTRL;

  union {                              /* Slow Serial Message DMA Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t SDMA_EN:8;
    } B;
  } SDMA_CTRL;

  uint8_t SRX_reserved2[4];
  union {                              /* Fast Message Ready Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t FRDY_IE:8;
    } B;
  } FRDY_IE;

  union {                              /* Slow Serial Message Ready Interrupt Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t SRDY_IE:8;
    } B;
  } SRDY_IE;

  uint8_t SRX_reserved3[4];
  union {                              /* DMA Fast Message Data Read Register */
    vuint32_t R;
    struct {
      vuint32_t CHNUM:4;
      vuint32_t SCNIB:4;
      vuint32_t DNIB1:4;
      vuint32_t DNIB2:4;
      vuint32_t DNIB3:4;
      vuint32_t DNIB4:4;
      vuint32_t DNIB5:4;
      vuint32_t DNIB6:4;
    } B;
  } DMA_FMSG_DATA;

  union {                              /* DMA Fast Message CRC Read Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t CRC4b:4;
      vuint32_t  :16;
    } B;
  } DMA_FMSG_CRC;

  union {                              /* DMA Fast Message Time Stamp Read Register */
    vuint32_t R;
    struct {
      vuint32_t TS:32;
    } B;
  } DMA_FMSG_TS;

  uint8_t SRX_reserved4[4];
  union {                              /* DMA Slow Serial Message Bit3 Read Register */
    vuint32_t R;
    struct {
      vuint32_t CHNUM:4;
      vuint32_t TYPE:1;
      vuint32_t  :16;
      vuint32_t CFG:1;
      vuint32_t ID7_4_D3_0:4;
      vuint32_t  :1;
      vuint32_t ID3_0_DATA15_12:4;
      vuint32_t  :1;
    } B;
  } DMA_SMSG_BIT3;

  union {                              /* DMA Slow Serial Message Bit2 Read Register */
    vuint32_t R;
    struct {
      vuint32_t  :10;
      vuint32_t SMCRC:6;
      vuint32_t  :4;
      vuint32_t DATA:12;
    } B;
  } DMA_SMSG_BIT2;

  union {                              /* DMA Slow Serial Message Time Stamp Read Register */
    vuint32_t R;
    struct {
      vuint32_t TS:32;
    } B;
  } DMA_SMSG_TS;

  uint8_t SRX_reserved5[4];
  struct {
    union {                            /* Channel 'n' Clock Control Register (n = 0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t  :1;
        vuint32_t CM_PRSC:15;
        vuint32_t COMP_EN:1;
        vuint32_t  :1;
        vuint32_t PRSC:14;
      } B;
    } CLK_CTRL;
    union {                            /* Channel 'n' Status Register (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t BUS_IDLE:1;
        vuint32_t  :3;
        vuint32_t CAL_RESYNC:1;
        vuint32_t CAL_20_25:1;
        vuint32_t SMSG_OFLW:1;
        vuint32_t FMSG_OFLW:1;
        vuint32_t  :1;
        vuint32_t PP_DIAG_ERR:1;
        vuint32_t CAL_LEN_ERR:1;
        vuint32_t CAL_DIAG_ERR:1;
        vuint32_t NIB_VAL_ERR:1;
        vuint32_t SMSG_CRC_ERR:1;
        vuint32_t FMSG_CRC_ERR:1;
        vuint32_t NUM_EDGES_ERR:1;
        vuint32_t  :16;
      } B;
    } STATUS;
    union {                            /* Channel 'n' Configuration Register (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t BUS_IDLE_CNT:4;
        vuint32_t IE_CAL_RESYNC:1;
        vuint32_t IE_CAL_20_25:1;
        vuint32_t IE_SMSG_OFLW:1;
        vuint32_t IE_FMSG_OFLW:1;
        vuint32_t FCRC_CHK_OFF:1;
        vuint32_t IE_PP_DIAG_ERR:1;
        vuint32_t IE_CAL_LEN_ERR:1;
        vuint32_t IE_CAL_DIAG_ERR:1;
        vuint32_t IE_NIB_VAL_ERR:1;
        vuint32_t IE_SMSG_CRC_ERR:1;
        vuint32_t IE_FMSG_CRC_ERR:1;
        vuint32_t IE_NUM_EDGES_ERR:1;
        vuint32_t DCHNG_INT:1;
        vuint32_t CAL_RNG:1;
        vuint32_t PP_CHKSEL:1;
        vuint32_t FCRC_TYPE:1;
        vuint32_t FCRC_SC_EN:1;
        vuint32_t SCRC_TYPE:1;
        vuint32_t PAUSE_EN:1;
        vuint32_t SUCC_CAL_CHK:1;
        vuint32_t FIL_CNT:8;
      } B;
    } CONFIG;
    uint8_t CH_reserved0[4];
  } CH[8];

  uint8_t SRX_reserved6[128];
  struct {
    union {                            /* Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t CHNUM:4;
        vuint32_t SCNIB:4;
        vuint32_t DNIB1:4;
        vuint32_t DNIB2:4;
        vuint32_t DNIB3:4;
        vuint32_t DNIB4:4;
        vuint32_t DNIB5:4;
        vuint32_t DNIB6:4;
      } B;
    } FMSG_DATA;
    union {                            /* Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t  :12;
        vuint32_t CRC4b:4;
        vuint32_t  :16;
      } B;
    } FMSG_CRC;
    union {                            /* Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t TS:32;
      } B;
    } FMSG_TS;
    union {                            /* Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t CHNUM:4;
        vuint32_t TYPE:1;
        vuint32_t  :16;
        vuint32_t CFG:1;
        vuint32_t ID7_4_ID3_0:4;
        vuint32_t  :1;
        vuint32_t ID3_0_DATA15_12:4;
        vuint32_t  :1;
      } B;
    } SMSG_BIT3;
    union {                            /* Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t  :10;
        vuint32_t SMCRC:6;
        vuint32_t  :4;
        vuint32_t DATA:12;
      } B;
    } SMSG_BIT2;
    union {                            /* Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t TS:32;
      } B;
    } SMSG_TS;
  } CHANNEL[8];
};


/* ============================================================================
   =============================== Module: SSCM ===============================
   ============================================================================ */

struct SSCM_tag {
  union {                              /* SSCM System Status */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t CER:1;                 /* Configuration Error */
      vuint16_t  :1;
      vuint16_t NXEN1:1;               /* Processor 1 Nexus enable status */
      vuint16_t NXEN:1;                /* Processor 0 Nexus enable status */
      vuint16_t  :1;
      vuint16_t  :1;
      vuint16_t  :1;
      vuint16_t BMODE:3;               /* Device Boot Mode */
      vuint16_t VLE:1;                 /* Variable Length Instruction Mode */
      vuint16_t  :1;
      vuint16_t  :1;
      vuint16_t  :2;
    } B;
  } STATUS;

  union {                              /* SSCM System Memory and ID Register */
    vuint16_t R;
    struct {
      vuint16_t JPIN:10;
      vuint16_t  :1;
      vuint16_t MREV:4;                /* Minor Mask Revision */
      vuint16_t  :1;
    } B;
  } MEMCONFIG;

  uint8_t SSCM_reserved0[2];
  union {                              /* SSCM Error Configuration Register */
    vuint16_t R;
    struct {
      vuint16_t  :14;
      vuint16_t PAE:1;                 /* Peripheral Bus Abort Enable. */
      vuint16_t RAE:1;                 /* Register Bus Abort Enable. */
    } B;
  } ERROR;

  uint8_t SSCM_reserved1[24];
  union {                              /* SSCM HSM and User Option Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t HSB:3;                 /* HSM Boot Configuration */
      vuint32_t HSE:1;                 /* HSM Enabled */
    } B;
  } UOPS;

  uint8_t SSCM_reserved2[4];
  union {                              /* Processor Start Address Register */
    vuint32_t R;
    struct {
      vuint32_t SADR:32;               /* Processor Start Address */
    } B;
  } PSA;

  uint8_t SSCM_reserved3[4];
  union {                              /* SSCM HSM Start Address Register */
    vuint32_t R;
    struct {
      vuint32_t HADR:32;               /* HSM Start Address */
    } B;
  } HSA;

  union {                              /* Life Cycle Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t  :2;
      vuint32_t  :5;
      vuint32_t LC:3;                  /* Life Cycle */
    } B;
  } LCSTAT;
};


/* ============================================================================
   =============================== Module: STCU2 ==============================
   ============================================================================ */

struct STCU2_tag {
  union {                              /* STCU2 Run Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t BYP:1;
      vuint32_t MBPLLEN:1;
      vuint32_t LBPLLEN:1;
      vuint32_t  :7;
      vuint32_t RUN:1;
    } B;
  } RUN;

  union {                              /* STCU2 Run Software Register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t MBIE:1;
      vuint32_t LBIE:1;
      vuint32_t MBSWPLLEN:1;
      vuint32_t LBSWPLLEN:1;
      vuint32_t  :6;
      vuint32_t RUNSW_ABORT:1;
      vuint32_t RUNSW:1;
    } B;
  } RUNSW;

  union {                              /* STCU2 SK Code Register */
    vuint32_t R;
    struct {
      vuint32_t SKC:32;
    } B;
  } SKC;

  union {                              /* STCU2 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t PTR:7;
      vuint32_t LB_DELAY:8;
      vuint32_t  :7;
      vuint32_t WRP:1;
      vuint32_t  :2;
      vuint32_t CRCEN:1;
      vuint32_t PMOSEN:1;
      vuint32_t MBU:1;
      vuint32_t CLK_CFG:3;
    } B;
  } CFG;

  union {                              /* STCU2 PLL Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t PLLODF:6;
      vuint32_t  :5;
      vuint32_t PLLIDF:3;
      vuint32_t  :9;
      vuint32_t PLLLDF:7;
    } B;
  } PLL_CFG;

  union {                              /* STCU2 Watchdog Register Granularity */
    vuint32_t R;
    struct {
      vuint32_t WDGEOC:32;
    } B;
  } WDG;

  union {                              /* STCU2 Interrupt Flag Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t MBIFLG:1;
      vuint32_t LBIFLG:1;
    } B;
  } INT_FLG;

  union {                              /* STCU2 CRC Expected Status Register */
    vuint32_t R;
    struct {
      vuint32_t CRCE:32;
    } B;
  } CRCE;

  union {                              /* STCU2 CRC Read Status Register */
    vuint32_t R;
    struct {
      vuint32_t CRCR:32;
    } B;
  } CRCR;

  union {                              /* STCU2 Error Register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t ABORTHW:1;
      vuint32_t ABORTSW:1;
      vuint32_t  :3;
      vuint32_t LOCKESW:1;
      vuint32_t WDTOSW:1;
      vuint32_t CRCSSW:1;
      vuint32_t ENGESW:1;
      vuint32_t INVPSW:1;
      vuint32_t  :6;
      vuint32_t UFSF:1;
      vuint32_t RFSF:1;
      vuint32_t  :3;
      vuint32_t LOCKE:1;
      vuint32_t WDTO:1;
      vuint32_t CRCS:1;
      vuint32_t ENGE:1;
      vuint32_t INVP:1;
    } B;
  } ERR_STAT;

  union {                              /* STCU2 Error FM Register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t LOCKEUFM:1;
      vuint32_t WDTOUFM:1;
      vuint32_t CRCSUFM:1;
      vuint32_t ENGEUFM:1;
      vuint32_t INVPUFM:1;
    } B;
  } ERR_FM;

  union {                              /* STCU2 Off-Line LBIST Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t LBS9:1;
      vuint32_t LBS8:1;
      vuint32_t LBS7:1;
      vuint32_t LBS6:1;
      vuint32_t LBS5:1;
      vuint32_t LBS4:1;
      vuint32_t LBS3:1;
      vuint32_t LBS2:1;
      vuint32_t LBS1:1;
      vuint32_t LBS0:1;
    } B;
  } LBS;

  union {                              /* STCU2 Off-Line LBIST End Flag Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t LBE9:1;
      vuint32_t LBE8:1;
      vuint32_t LBE7:1;
      vuint32_t LBE6:1;
      vuint32_t LBE5:1;
      vuint32_t LBE4:1;
      vuint32_t LBE3:1;
      vuint32_t LBE2:1;
      vuint32_t LBE1:1;
      vuint32_t LBE0:1;
    } B;
  } LBE;

  union {                              /* STCU2 On-Line LBIST Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t LBSSW9:1;
      vuint32_t LBSSW8:1;
      vuint32_t LBSSW7:1;
      vuint32_t LBSSW6:1;
      vuint32_t LBSSW5:1;
      vuint32_t LBSSW4:1;
      vuint32_t LBSSW3:1;
      vuint32_t LBSSW2:1;
      vuint32_t LBSSW1:1;
      vuint32_t LBSSW0:1;
    } B;
  } LBSSW;

  union {                              /* STCU2 On-Line LBIST End Flag Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t LBESW9:1;
      vuint32_t LBESW8:1;
      vuint32_t LBESW7:1;
      vuint32_t LBESW6:1;
      vuint32_t LBESW5:1;
      vuint32_t LBESW4:1;
      vuint32_t LBESW3:1;
      vuint32_t LBESW2:1;
      vuint32_t LBESW1:1;
      vuint32_t LBESW0:1;
    } B;
  } LBESW;

  union {                              /* STCU2 On-Line LBIST Reset Management */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t LBRMSW9:1;
      vuint32_t LBRMSW8:1;
      vuint32_t LBRMSW7:1;
      vuint32_t LBRMSW6:1;
      vuint32_t LBRMSW5:1;
      vuint32_t LBRMSW4:1;
      vuint32_t LBRMSW3:1;
      vuint32_t LBRMSW2:1;
      vuint32_t LBRMSW1:1;
      vuint32_t LBRMSW0:1;
    } B;
  } LBRMSW;

  union {                              /* STCU2 LBIST Unrecoverable FM Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t LBUFM9:1;
      vuint32_t LBUFM8:1;
      vuint32_t LBUFM7:1;
      vuint32_t LBUFM6:1;
      vuint32_t LBUFM5:1;
      vuint32_t LBUFM4:1;
      vuint32_t LBUFM3:1;
      vuint32_t LBUFM2:1;
      vuint32_t LBUFM1:1;
      vuint32_t LBUFM0:1;
    } B;
  } LBUFM;

  union {                              /* STCU2 Off-Line MBIST Status Low Register */
    vuint32_t R;
    struct {
      vuint32_t MBS31:1;
      vuint32_t MBS30:1;
      vuint32_t MBS29:1;
      vuint32_t MBS28:1;
      vuint32_t MBS27:1;
      vuint32_t MBS26:1;
      vuint32_t MBS25:1;
      vuint32_t MBS24:1;
      vuint32_t MBS23:1;
      vuint32_t MBS22:1;
      vuint32_t MBS21:1;
      vuint32_t MBS20:1;
      vuint32_t MBS19:1;
      vuint32_t MBS18:1;
      vuint32_t MBS17:1;
      vuint32_t MBS16:1;
      vuint32_t MBS15:1;
      vuint32_t MBS14:1;
      vuint32_t MBS13:1;
      vuint32_t MBS12:1;
      vuint32_t MBS11:1;
      vuint32_t MBS10:1;
      vuint32_t MBS9:1;
      vuint32_t MBS8:1;
      vuint32_t MBS7:1;
      vuint32_t MBS6:1;
      vuint32_t MBS5:1;
      vuint32_t MBS4:1;
      vuint32_t MBS3:1;
      vuint32_t MBS2:1;
      vuint32_t MBS1:1;
      vuint32_t MBS0:1;
    } B;
  } MBSL;

  union {                              /* STCU2 Off-Line MBIST Status Medium Register */
    vuint32_t R;
    struct {
      vuint32_t MBS63:1;
      vuint32_t MBS62:1;
      vuint32_t MBS61:1;
      vuint32_t MBS60:1;
      vuint32_t MBS59:1;
      vuint32_t MBS58:1;
      vuint32_t MBS57:1;
      vuint32_t MBS56:1;
      vuint32_t MBS55:1;
      vuint32_t MBS54:1;
      vuint32_t MBS53:1;
      vuint32_t MBS52:1;
      vuint32_t MBS51:1;
      vuint32_t MBS50:1;
      vuint32_t MBS49:1;
      vuint32_t MBS48:1;
      vuint32_t MBS47:1;
      vuint32_t MBS46:1;
      vuint32_t MBS45:1;
      vuint32_t MBS44:1;
      vuint32_t MBS43:1;
      vuint32_t MBS42:1;
      vuint32_t MBS41:1;
      vuint32_t MBS40:1;
      vuint32_t MBS39:1;
      vuint32_t MBS38:1;
      vuint32_t MBS37:1;
      vuint32_t MBS36:1;
      vuint32_t MBS35:1;
      vuint32_t MBS34:1;
      vuint32_t MBS33:1;
      vuint32_t MBS32:1;
    } B;
  } MBSM;

  union {                              /* STCU2 Off-Line MBIST Status High Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t MBS77:1;
      vuint32_t MBS76:1;
      vuint32_t MBS75:1;
      vuint32_t MBS74:1;
      vuint32_t MBS73:1;
      vuint32_t MBS72:1;
      vuint32_t MBS71:1;
      vuint32_t MBS70:1;
      vuint32_t MBS69:1;
      vuint32_t MBS68:1;
      vuint32_t MBS67:1;
      vuint32_t MBS66:1;
      vuint32_t MBS65:1;
      vuint32_t MBS64:1;
    } B;
  } MBSH;

  union {                              /* STCU2 Off-Line MBIST End Flag Low Register */
    vuint32_t R;
    struct {
      vuint32_t MBE31:1;
      vuint32_t MBE30:1;
      vuint32_t MBE29:1;
      vuint32_t MBE28:1;
      vuint32_t MBE27:1;
      vuint32_t MBE26:1;
      vuint32_t MBE25:1;
      vuint32_t MBE24:1;
      vuint32_t MBE23:1;
      vuint32_t MBE22:1;
      vuint32_t MBE21:1;
      vuint32_t MBE20:1;
      vuint32_t MBE19:1;
      vuint32_t MBE18:1;
      vuint32_t MBE17:1;
      vuint32_t MBE16:1;
      vuint32_t MBE15:1;
      vuint32_t MBE14:1;
      vuint32_t MBE13:1;
      vuint32_t MBE12:1;
      vuint32_t MBE11:1;
      vuint32_t MBE10:1;
      vuint32_t MBE9:1;
      vuint32_t MBE8:1;
      vuint32_t MBE7:1;
      vuint32_t MBE6:1;
      vuint32_t MBE5:1;
      vuint32_t MBE4:1;
      vuint32_t MBE3:1;
      vuint32_t MBE2:1;
      vuint32_t MBE1:1;
      vuint32_t MBE0:1;
    } B;
  } MBEL;

  union {                              /* STCU2 Off-Line MBIST End Flag Medium Register */
    vuint32_t R;
    struct {
      vuint32_t MBE63:1;
      vuint32_t MBE62:1;
      vuint32_t MBE61:1;
      vuint32_t MBE60:1;
      vuint32_t MBE59:1;
      vuint32_t MBE58:1;
      vuint32_t MBE57:1;
      vuint32_t MBE56:1;
      vuint32_t MBE55:1;
      vuint32_t MBE54:1;
      vuint32_t MBE53:1;
      vuint32_t MBE52:1;
      vuint32_t MBE51:1;
      vuint32_t MBE50:1;
      vuint32_t MBE49:1;
      vuint32_t MBE48:1;
      vuint32_t MBE47:1;
      vuint32_t MBE46:1;
      vuint32_t MBE45:1;
      vuint32_t MBE44:1;
      vuint32_t MBE43:1;
      vuint32_t MBE42:1;
      vuint32_t MBE41:1;
      vuint32_t MBE40:1;
      vuint32_t MBE39:1;
      vuint32_t MBE38:1;
      vuint32_t MBE37:1;
      vuint32_t MBE36:1;
      vuint32_t MBE35:1;
      vuint32_t MBE34:1;
      vuint32_t MBE33:1;
      vuint32_t MBE32:1;
    } B;
  } MBEM;

  union {                              /* STCU2 Off-Line MBIST End Flag High Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t MBE77:1;
      vuint32_t MBE76:1;
      vuint32_t MBE75:1;
      vuint32_t MBE74:1;
      vuint32_t MBE73:1;
      vuint32_t MBE72:1;
      vuint32_t MBE71:1;
      vuint32_t MBE70:1;
      vuint32_t MBE69:1;
      vuint32_t MBE68:1;
      vuint32_t MBE67:1;
      vuint32_t MBE66:1;
      vuint32_t MBE65:1;
      vuint32_t MBE64:1;
    } B;
  } MBEH;

  union {                              /* STCU2 On-Line MBIST Status Low Register */
    vuint32_t R;
    struct {
      vuint32_t MBSSW31:1;
      vuint32_t MBSSW30:1;
      vuint32_t MBSSW29:1;
      vuint32_t MBSSW28:1;
      vuint32_t MBSSW27:1;
      vuint32_t MBSSW26:1;
      vuint32_t MBSSW25:1;
      vuint32_t MBSSW24:1;
      vuint32_t MBSSW23:1;
      vuint32_t MBSSW22:1;
      vuint32_t MBSSW21:1;
      vuint32_t MBSSW20:1;
      vuint32_t MBSSW19:1;
      vuint32_t MBSSW18:1;
      vuint32_t MBSSW17:1;
      vuint32_t MBSSW16:1;
      vuint32_t MBSSW15:1;
      vuint32_t MBSSW14:1;
      vuint32_t MBSSW13:1;
      vuint32_t MBSSW12:1;
      vuint32_t MBSSW11:1;
      vuint32_t MBSSW10:1;
      vuint32_t MBSSW9:1;
      vuint32_t MBSSW8:1;
      vuint32_t MBSSW7:1;
      vuint32_t MBSSW6:1;
      vuint32_t MBSSW5:1;
      vuint32_t MBSSW4:1;
      vuint32_t MBSSW3:1;
      vuint32_t MBSSW2:1;
      vuint32_t MBSSW1:1;
      vuint32_t MBSSW0:1;
    } B;
  } MBSLSW;

  union {                              /* STCU2 On-Line MBIST Status Medium Register */
    vuint32_t R;
    struct {
      vuint32_t MBSSW63:1;
      vuint32_t MBSSW62:1;
      vuint32_t MBSSW61:1;
      vuint32_t MBSSW60:1;
      vuint32_t MBSSW59:1;
      vuint32_t MBSSW58:1;
      vuint32_t MBSSW57:1;
      vuint32_t MBSSW56:1;
      vuint32_t MBSSW55:1;
      vuint32_t MBSSW54:1;
      vuint32_t MBSSW53:1;
      vuint32_t MBSSW52:1;
      vuint32_t MBSSW51:1;
      vuint32_t MBSSW50:1;
      vuint32_t MBSSW49:1;
      vuint32_t MBSSW48:1;
      vuint32_t MBSSW47:1;
      vuint32_t MBSSW46:1;
      vuint32_t MBSSW45:1;
      vuint32_t MBSSW44:1;
      vuint32_t MBSSW43:1;
      vuint32_t MBSSW42:1;
      vuint32_t MBSSW41:1;
      vuint32_t MBSSW40:1;
      vuint32_t MBSSW39:1;
      vuint32_t MBSSW38:1;
      vuint32_t MBSSW37:1;
      vuint32_t MBSSW36:1;
      vuint32_t MBSSW35:1;
      vuint32_t MBSSW34:1;
      vuint32_t MBSSW33:1;
      vuint32_t MBSSW32:1;
    } B;
  } MBSMSW;

  union {                              /* STCU2 On-Line MBIST Status High Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t MBSSW77:1;
      vuint32_t MBSSW76:1;
      vuint32_t MBSSW75:1;
      vuint32_t MBSSW74:1;
      vuint32_t MBSSW73:1;
      vuint32_t MBSSW72:1;
      vuint32_t MBSSW71:1;
      vuint32_t MBSSW70:1;
      vuint32_t MBSSW69:1;
      vuint32_t MBSSW68:1;
      vuint32_t MBSSW67:1;
      vuint32_t MBSSW66:1;
      vuint32_t MBSSW65:1;
      vuint32_t MBSSW64:1;
    } B;
  } MBSHSW;

  union {                              /* STCU2 On-Line MBIST End Flag Low Register */
    vuint32_t R;
    struct {
      vuint32_t MBESW31:1;
      vuint32_t MBESW30:1;
      vuint32_t MBESW29:1;
      vuint32_t MBESW28:1;
      vuint32_t MBESW27:1;
      vuint32_t MBESW26:1;
      vuint32_t MBESW25:1;
      vuint32_t MBESW24:1;
      vuint32_t MBESW23:1;
      vuint32_t MBESW22:1;
      vuint32_t MBESW21:1;
      vuint32_t MBESW20:1;
      vuint32_t MBESW19:1;
      vuint32_t MBESW18:1;
      vuint32_t MBESW17:1;
      vuint32_t MBESW16:1;
      vuint32_t MBESW15:1;
      vuint32_t MBESW14:1;
      vuint32_t MBESW13:1;
      vuint32_t MBESW12:1;
      vuint32_t MBESW11:1;
      vuint32_t MBESW10:1;
      vuint32_t MBESW9:1;
      vuint32_t MBESW8:1;
      vuint32_t MBESW7:1;
      vuint32_t MBESW6:1;
      vuint32_t MBESW5:1;
      vuint32_t MBESW4:1;
      vuint32_t MBESW3:1;
      vuint32_t MBESW2:1;
      vuint32_t MBESW1:1;
      vuint32_t MBESW0:1;
    } B;
  } MBELSW;

  union {                              /* STCU2 On-Line MBIST End Flag Medium Register */
    vuint32_t R;
    struct {
      vuint32_t MBESW63:1;
      vuint32_t MBESW62:1;
      vuint32_t MBESW61:1;
      vuint32_t MBESW60:1;
      vuint32_t MBESW59:1;
      vuint32_t MBESW58:1;
      vuint32_t MBESW57:1;
      vuint32_t MBESW56:1;
      vuint32_t MBESW55:1;
      vuint32_t MBESW54:1;
      vuint32_t MBESW53:1;
      vuint32_t MBESW52:1;
      vuint32_t MBESW51:1;
      vuint32_t MBESW50:1;
      vuint32_t MBESW49:1;
      vuint32_t MBESW48:1;
      vuint32_t MBESW47:1;
      vuint32_t MBESW46:1;
      vuint32_t MBESW45:1;
      vuint32_t MBESW44:1;
      vuint32_t MBESW43:1;
      vuint32_t MBESW42:1;
      vuint32_t MBESW41:1;
      vuint32_t MBESW40:1;
      vuint32_t MBESW39:1;
      vuint32_t MBESW38:1;
      vuint32_t MBESW37:1;
      vuint32_t MBESW36:1;
      vuint32_t MBESW35:1;
      vuint32_t MBESW34:1;
      vuint32_t MBESW33:1;
      vuint32_t MBESW32:1;
    } B;
  } MBEMSW;

  union {                              /* STCU2 On-Line MBIST End Flag High Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t MBESW77:1;
      vuint32_t MBESW76:1;
      vuint32_t MBESW75:1;
      vuint32_t MBESW74:1;
      vuint32_t MBESW73:1;
      vuint32_t MBESW72:1;
      vuint32_t MBESW71:1;
      vuint32_t MBESW70:1;
      vuint32_t MBESW69:1;
      vuint32_t MBESW68:1;
      vuint32_t MBESW67:1;
      vuint32_t MBESW66:1;
      vuint32_t MBESW65:1;
      vuint32_t MBESW64:1;
    } B;
  } MBEHSW;

  union {                              /* STCU2 MBIST Unrecoverable FM Low Register */
    vuint32_t R;
    struct {
      vuint32_t MBUFM31:1;
      vuint32_t MBUFM30:1;
      vuint32_t MBUFM29:1;
      vuint32_t MBUFM28:1;
      vuint32_t MBUFM27:1;
      vuint32_t MBUFM26:1;
      vuint32_t MBUFM25:1;
      vuint32_t MBUFM24:1;
      vuint32_t MBUFM23:1;
      vuint32_t MBUFM22:1;
      vuint32_t MBUFM21:1;
      vuint32_t MBUFM20:1;
      vuint32_t MBUFM19:1;
      vuint32_t MBUFM18:1;
      vuint32_t MBUFM17:1;
      vuint32_t MBUFM16:1;
      vuint32_t MBUFM15:1;
      vuint32_t MBUFM14:1;
      vuint32_t MBUFM13:1;
      vuint32_t MBUFM12:1;
      vuint32_t MBUFM11:1;
      vuint32_t MBUFM10:1;
      vuint32_t MBUFM9:1;
      vuint32_t MBUFM8:1;
      vuint32_t MBUFM7:1;
      vuint32_t MBUFM6:1;
      vuint32_t MBUFM5:1;
      vuint32_t MBUFM4:1;
      vuint32_t MBUFM3:1;
      vuint32_t MBUFM2:1;
      vuint32_t MBUFM1:1;
      vuint32_t MBUFM0:1;
    } B;
  } MBUFML;

  union {                              /* STCU2 MBIST Unrecoverable FM Medium Register */
    vuint32_t R;
    struct {
      vuint32_t MBUFM63:1;
      vuint32_t MBUFM62:1;
      vuint32_t MBUFM61:1;
      vuint32_t MBUFM60:1;
      vuint32_t MBUFM59:1;
      vuint32_t MBUFM58:1;
      vuint32_t MBUFM57:1;
      vuint32_t MBUFM56:1;
      vuint32_t MBUFM55:1;
      vuint32_t MBUFM54:1;
      vuint32_t MBUFM53:1;
      vuint32_t MBUFM52:1;
      vuint32_t MBUFM51:1;
      vuint32_t MBUFM50:1;
      vuint32_t MBUFM49:1;
      vuint32_t MBUFM48:1;
      vuint32_t MBUFM47:1;
      vuint32_t MBUFM46:1;
      vuint32_t MBUFM45:1;
      vuint32_t MBUFM44:1;
      vuint32_t MBUFM43:1;
      vuint32_t MBUFM42:1;
      vuint32_t MBUFM41:1;
      vuint32_t MBUFM40:1;
      vuint32_t MBUFM39:1;
      vuint32_t MBUFM38:1;
      vuint32_t MBUFM37:1;
      vuint32_t MBUFM36:1;
      vuint32_t MBUFM35:1;
      vuint32_t MBUFM34:1;
      vuint32_t MBUFM33:1;
      vuint32_t MBUFM32:1;
    } B;
  } MBUFMM;

  union {                              /* STCU2 MBIST Unrecoverable FM High Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t MBUFM77:1;
      vuint32_t MBUFM76:1;
      vuint32_t MBUFM75:1;
      vuint32_t MBUFM74:1;
      vuint32_t MBUFM73:1;
      vuint32_t MBUFM72:1;
      vuint32_t MBUFM71:1;
      vuint32_t MBUFM70:1;
      vuint32_t MBUFM69:1;
      vuint32_t MBUFM68:1;
      vuint32_t MBUFM67:1;
      vuint32_t MBUFM66:1;
      vuint32_t MBUFM65:1;
      vuint32_t MBUFM64:1;
    } B;
  } MBUFMH;

  uint8_t STCU2_reserved0[128];
  struct {
    union {                            /* STCU2 LBIST Control Register */
      vuint32_t R;
      struct {
        vuint32_t CSM:1;
        vuint32_t PTR:7;
        vuint32_t  :4;
        vuint32_t PRPGEN:1;
        vuint32_t SHS:3;
        vuint32_t SCEN_OFF:4;
        vuint32_t SCEN_ON:4;
        vuint32_t  :4;
        vuint32_t PFT:1;
        vuint32_t CWS:3;
      } B;
    } LB_CTRL;
    union {                            /* STCU2 LBIST PC Stop Register */
      vuint32_t R;
      struct {
        vuint32_t  :6;
        vuint32_t PCS:26;
      } B;
    } LB_PCS;
    union {                            /* STCU2 LBIST PRPG Low Register */
      vuint32_t R;
      struct {
        vuint32_t PRPGx:32;
      } B;
    } LB_PRPGL;
    union {                            /* STCU2 LBIST PRPG High Register */
      vuint32_t R;
      struct {
        vuint32_t PRPGx:32;
      } B;
    } LB_PRPGH;
    union {                            /* STCU2 Off-Line LBIST MISR Expected Low Register */
      vuint32_t R;
      struct {
        vuint32_t MISREx:32;
      } B;
    } LB_MISREL;
    union {                            /* STCU2 Off-Line LBIST MISR Expected High Register */
      vuint32_t R;
      struct {
        vuint32_t MISREx:32;
      } B;
    } LB_MISREH;
    union {                            /* STCU2 Off-Line LBIST MISR Read Low Register */
      vuint32_t R;
      struct {
        vuint32_t MISRRx:32;
      } B;
    } LB_MISRRL;
    union {                            /* STCU2 Off-Line LBIST MISR Read High Register */
      vuint32_t R;
      struct {
        vuint32_t MISRRx:32;
      } B;
    } LB_MISRRH;
    union {                            /* STCU2 On-Line LBIST MISR Expected Low Register */
      vuint32_t R;
      struct {
        vuint32_t MISRESWx:32;
      } B;
    } LB_MISRELSW;
    union {                            /* STCU2 On-Line LBIST MISR Expected High Register */
      vuint32_t R;
      struct {
        vuint32_t MISRESWx:32;
      } B;
    } LB_MISREHSW;
    union {                            /* STCU2 On-Line LBIST MISR Read Low Register */
      vuint32_t R;
      struct {
        vuint32_t MISRRSWx:32;
      } B;
    } LB_MISRRLSW;
    union {                            /* STCU2 On-Line LBIST MISR Read High Register */
      vuint32_t R;
      struct {
        vuint32_t MISRRSWx:32;
      } B;
    } LB_MISRRHSW;
    uint8_t LB_reserved0[16];
  } LB[10];

  uint8_t STCU2_reserved1[640];
  union {                              /* STCU2 MBIST Control Register */
    vuint32_t R;
    struct {
      vuint32_t CSM:1;
      vuint32_t PTR:7;
      vuint32_t  :24;
    } B;
  } MB_CTRL[78];
};


/* ============================================================================
   =============================== Module: STM ================================
   ============================================================================ */

struct STM_tag {
  union {                              /* STM Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CPS:8;                 /* Counter Prescaler. */
      vuint32_t  :6;
      vuint32_t FRZ:1;                 /* Freeze. */
      vuint32_t TEN:1;                 /* Timer counter Enabled. */
    } B;
  } CR;

  union {                              /* STM Count Register */
    vuint32_t R;
    struct {
      vuint32_t CNT:32;                /* Timer count value used as the time base for all channels. */
    } B;
  } CNT;

  uint8_t STM_reserved0[8];
  struct {
    union {                            /* STM Channel Control Register */
      vuint32_t R;
      struct {
        vuint32_t  :31;
        vuint32_t CEN:1;               /* Channel Enable */
      } B;
    } CCR;
    union {                            /* STM Channel Interrupt Register */
      vuint32_t R;
      struct {
        vuint32_t  :31;
        vuint32_t CIF:1;               /* Channel Interrupt Flag */
      } B;
    } CIR;
    union {                            /* STM Channel Compare Register */
      vuint32_t R;
      struct {
        vuint32_t CMP:32;              /* Compare value for channel n. */
      } B;
    } CMP;
    uint8_t CHANNEL_reserved0[4];
  } CHANNEL[4];
};


/* ============================================================================
   =============================== Module: SWT ================================
   ============================================================================ */

struct SWT_tag {
  union {                              /* SWT Control Register */
    vuint32_t R;
    struct {
      vuint32_t MAP0:1;
      vuint32_t MAP1:1;
      vuint32_t MAP2:1;
      vuint32_t MAP3:1;
      vuint32_t MAP4:1;
      vuint32_t MAP5:1;
      vuint32_t MAP6:1;
      vuint32_t MAP7:1;
      vuint32_t  :13;
      vuint32_t SMD:2;                 /* Service Mode. */
      vuint32_t RIA:1;
      vuint32_t WND:1;
      vuint32_t ITR:1;
      vuint32_t HLK:1;
      vuint32_t SLK:1;
      vuint32_t  :1;                   /* Reserved. */
      vuint32_t STP:1;
      vuint32_t FRZ:1;
      vuint32_t WEN:1;
    } B;
  } CR;

  union {                              /* SWT Interrupt Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t TIF:1;
    } B;
  } IR;

  union {                              /* SWT Time-out Register */
    vuint32_t R;
    struct {
      vuint32_t WTO:32;
    } B;
  } TO;

  union {                              /* SWT Window Register */
    vuint32_t R;
    struct {
      vuint32_t WST:32;
    } B;
  } WN;

  union {                              /* SWT Service Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t WSC:16;
    } B;
  } SR;

  union {                              /* SWT Counter Output Register */
    vuint32_t R;
    struct {
      vuint32_t CNT:32;
    } B;
  } CO;

  union {                              /* SWT Service Key Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SK:16;                 /* Service Key. */
    } B;
  } SK;
};


/* ============================================================================
   =============================== Module: TDM ================================
   ============================================================================ */

struct TDM_tag {
  union {                              /* TDR Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t TDRSR5:1;
      vuint32_t TDRSR4:1;
      vuint32_t TDRSR3:1;
      vuint32_t TDRSR2:1;
      vuint32_t TDRSR1:1;
      vuint32_t TDRSR0:1;
    } B;
  } TDRSR;

  union {                              /* Last Flash Programmed Address Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t LFPAR:24;
    } B;
  } LFPAR;

  union {                              /* Diary Base Address */
    vuint32_t R;
    struct {
      vuint32_t DBA:32;
    } B;
  } DBA;

  uint8_t TDM_reserved0[4];
  union {                              /* Software Tamper Override Key Region */
    vuint32_t R;
    struct {
      vuint32_t STO_KEY:32;
    } B;
  } STO_KEY[6];
};


/* ============================================================================
   =============================== Module: WKPU ===============================
   ============================================================================ */

struct WKPU_tag {
  union {                              /* NMI Status Flag Register */
    vuint32_t R;
    struct {
      vuint32_t NIF0:1;                /* NMI Status Flag 0 (safety core) */
      vuint32_t NOVF0:1;               /* NMI Overrun Status Flag 0 (safety core) */
      vuint32_t  :6;
      vuint32_t NIF1:1;                /* NMI Status Flag 1 (main core) */
      vuint32_t NOVF1:1;               /* NMI Overrun Status Flag 1 (main core) */
      vuint32_t  :6;
      vuint32_t NIF2:1;                /* NMI Status Flag 2 (IOP) */
      vuint32_t NOVF2:1;               /* NMI Overrun Status Flag 2 (IOP) */
      vuint32_t  :6;
      vuint32_t RIF:1;                 /* Reset Status Flag */
      vuint32_t ROVF:1;                /* Reset Overrun Status Flag */
      vuint32_t  :6;
    } B;
  } NSR;

  uint8_t WKPU_reserved0[4];
  union {                              /* NMI Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t NLOCK0:1;              /* NMI Configuration Lock Register 0 */
      vuint32_t NDSS0:2;               /* NMI Destination Source Select 0 */
      vuint32_t NWRE0:1;               /* NMI Wakeup Request Enable 0 */
      vuint32_t  :1;
      vuint32_t NREE0:1;               /* NMI Rising-edge Events Enable 0 */
      vuint32_t NFEE0:1;               /* NMI Falling-edge Events Enable 0 */
      vuint32_t NFE0:1;                /* NMI Filter Enable */
      vuint32_t NLOCK1:1;              /* NMI Configuration Lock Register 1 */
      vuint32_t NDSS1:2;               /* NMI Destination Source Select 1 */
      vuint32_t NWRE1:1;               /* NMI Wakeup Request Enable 1 */
      vuint32_t  :1;
      vuint32_t NREE1:1;               /* NMI Rising-edge Events Enable 1 */
      vuint32_t NFEE1:1;               /* NMI Falling-edge Events Enable 1 */
      vuint32_t  :1;
      vuint32_t NLOCK2:1;              /* NMI Configuration Lock Register 2 */
      vuint32_t NDSS2:2;               /* NMI Destination Source Select 2 */
      vuint32_t NWRE2:1;               /* NMI Wakeup Request Enable 2 */
      vuint32_t  :1;
      vuint32_t NREE2:1;               /* NMI Rising-edge Events Enable 2 */
      vuint32_t NFEE2:1;               /* NMI Falling-edge Events Enable 2 */
      vuint32_t  :1;
      vuint32_t RLOCK:1;               /* Reset Configuration Lock Register */
      vuint32_t RDSS:2;                /* Reset Destination Source Select */
      vuint32_t RWRE:1;                /* Reset Wakeup Request Enable */
      vuint32_t  :1;
      vuint32_t RREE:1;                /* Reset Rising-edge Events Enable */
      vuint32_t RFEE:1;                /* Reset Falling-edge Events Enable */
      vuint32_t  :1;
    } B;
  } NCR;
};


/* ============================================================================
   =============================== Module: XBAR ===============================
   ============================================================================ */

struct XBAR_tag {
  struct {
    union {                            /* XBAR Priority Registers Slave */
      vuint32_t R;
      struct {
        vuint32_t  :1;
        vuint32_t M7:3;
        vuint32_t  :1;
        vuint32_t M6:3;
        vuint32_t  :1;
        vuint32_t M5:3;
        vuint32_t  :1;
        vuint32_t M4:3;
        vuint32_t  :1;
        vuint32_t M3:3;
        vuint32_t  :1;
        vuint32_t M2:3;
        vuint32_t  :1;
        vuint32_t M1:3;
        vuint32_t  :1;
        vuint32_t M0:3;
      } B;
    } PRS;
    uint8_t PORT_reserved0[12];
    union {                            /* XBAR Control Register */
      vuint32_t R;
      struct {
        vuint32_t RO:1;
        vuint32_t HRP:1;
        vuint32_t  :6;
        vuint32_t HPEx:8;              /* High Priority Enable */
        vuint32_t  :6;
        vuint32_t ARB:2;
        vuint32_t  :2;
        vuint32_t PCTL:2;
        vuint32_t  :1;
        vuint32_t PARK:3;
      } B;
    } CRS;
    uint8_t PORT_reserved1[236];
  } PORT[8];
};


/* ============================================================================
   =============================== Module: XBIC ===============================
   ============================================================================ */

struct XBIC_tag {
  union {                              /* XBIC Module Control Register */
    vuint32_t R;
    struct {
      vuint32_t SE0:1;
      vuint32_t SE1:1;
      vuint32_t SE2:1;
      vuint32_t SE3:1;
      vuint32_t SE4:1;
      vuint32_t SE5:1;
      vuint32_t SE6:1;
      vuint32_t SE7:1;
      vuint32_t ME0:1;
      vuint32_t ME1:1;
      vuint32_t ME2:1;
      vuint32_t ME3:1;
      vuint32_t ME4:1;
      vuint32_t ME5:1;
      vuint32_t ME6:1;
      vuint32_t ME7:1;
      vuint32_t  :16;
    } B;
  } MCR;

  union {                              /* XBIC Error Injection Register */
    vuint32_t R;
    struct {
      vuint32_t EIE:1;
      vuint32_t  :16;
      vuint32_t SLV:3;
      vuint32_t MST:4;
      vuint32_t SYN:8;
    } B;
  } EIR;

  union {                              /* XBIC Error Status Register */
    vuint32_t R;
    struct {
      vuint32_t VLD:1;
      vuint32_t DPSE0:1;
      vuint32_t DPSE1:1;
      vuint32_t DPSE2:1;
      vuint32_t DPSE3:1;
      vuint32_t DPSE4:1;
      vuint32_t DPSE5:1;
      vuint32_t DPSE6:1;
      vuint32_t DPSE7:1;
      vuint32_t DPME0:1;
      vuint32_t DPME1:1;
      vuint32_t DPME2:1;
      vuint32_t DPME3:1;
      vuint32_t DPME4:1;
      vuint32_t DPME5:1;
      vuint32_t DPME6:1;
      vuint32_t DPME7:1;
      vuint32_t SLV:3;
      vuint32_t MST:4;
      vuint32_t SYN:8;
    } B;
  } ESR;

  union {                              /* XBIC Error Address Register */
    vuint32_t R;
    struct {
      vuint32_t ADDR:32;
    } B;
  } EAR;
};


/* ============================================================================
   =============================== Module: XOSC ===============================
   ============================================================================ */

struct XOSC_tag {
  union {                              /* XOSC Control Register */
    vuint32_t R;
    struct {
      vuint32_t OSCBYP:1;
      vuint32_t  :2;
      vuint32_t  :5;
      vuint32_t EOCV:8;                /* End of Count Value */
      vuint32_t M_OSC:1;               /* Crystal oscillator clock interrupt mask */
      vuint32_t  :2;
      vuint32_t  :5;
      vuint32_t I_OSC:1;
      vuint32_t  :5;
      vuint32_t  :1;
      vuint32_t  :1;
    } B;
  } CTL;
};


/* ============================================================================
   =============================== Module: eDMA ===============================
   ============================================================================ */

struct eDMA_tag {
  union {                              /* Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t CX:1;
      vuint32_t ECX:1;
      vuint32_t GRP3PRI:2;
      vuint32_t GRP2PRI:2;
      vuint32_t GRP1PRI:2;
      vuint32_t GRP0PRI:2;
      vuint32_t EMLM:1;
      vuint32_t CLM:1;
      vuint32_t HALT:1;
      vuint32_t HOE:1;
      vuint32_t ERGA:1;
      vuint32_t ERCA:1;
      vuint32_t EDBG:1;
      vuint32_t  :1;
    } B;
  } CR;

  union {                              /* Error Status */
    vuint32_t R;
    struct {
      vuint32_t VLD:1;
      vuint32_t  :13;
      vuint32_t UCE:1;
      vuint32_t ECX:1;
      vuint32_t GPE:1;
      vuint32_t CPE:1;
      vuint32_t ERRCHN:6;
      vuint32_t SAE:1;
      vuint32_t SOE:1;
      vuint32_t DAE:1;
      vuint32_t DOE:1;
      vuint32_t NCE:1;
      vuint32_t SGE:1;
      vuint32_t SBE:1;
      vuint32_t DBE:1;
    } B;
  } ES;

  union {                              /* Enable Request Register High */
    vuint32_t R;
    struct {
      vuint32_t ERQ63:1;
      vuint32_t ERQ62:1;
      vuint32_t ERQ61:1;
      vuint32_t ERQ60:1;
      vuint32_t ERQ59:1;
      vuint32_t ERQ58:1;
      vuint32_t ERQ57:1;
      vuint32_t ERQ56:1;
      vuint32_t ERQ55:1;
      vuint32_t ERQ54:1;
      vuint32_t ERQ53:1;
      vuint32_t ERQ52:1;
      vuint32_t ERQ51:1;
      vuint32_t ERQ50:1;
      vuint32_t ERQ49:1;
      vuint32_t ERQ48:1;
      vuint32_t ERQ47:1;
      vuint32_t ERQ46:1;
      vuint32_t ERQ45:1;
      vuint32_t ERQ44:1;
      vuint32_t ERQ43:1;
      vuint32_t ERQ42:1;
      vuint32_t ERQ41:1;
      vuint32_t ERQ40:1;
      vuint32_t ERQ39:1;
      vuint32_t ERQ38:1;
      vuint32_t ERQ37:1;
      vuint32_t ERQ36:1;
      vuint32_t ERQ35:1;
      vuint32_t ERQ34:1;
      vuint32_t ERQ33:1;
      vuint32_t ERQ32:1;
    } B;
  } ERQH;

  union {                              /* Enable Request Register Low */
    vuint32_t R;
    struct {
      vuint32_t ERQ31:1;
      vuint32_t ERQ30:1;
      vuint32_t ERQ29:1;
      vuint32_t ERQ28:1;
      vuint32_t ERQ27:1;
      vuint32_t ERQ26:1;
      vuint32_t ERQ25:1;
      vuint32_t ERQ24:1;
      vuint32_t ERQ23:1;
      vuint32_t ERQ22:1;
      vuint32_t ERQ21:1;
      vuint32_t ERQ20:1;
      vuint32_t ERQ19:1;
      vuint32_t ERQ18:1;
      vuint32_t ERQ17:1;
      vuint32_t ERQ16:1;
      vuint32_t ERQ15:1;
      vuint32_t ERQ14:1;
      vuint32_t ERQ13:1;
      vuint32_t ERQ12:1;
      vuint32_t ERQ11:1;
      vuint32_t ERQ10:1;
      vuint32_t ERQ9:1;
      vuint32_t ERQ8:1;
      vuint32_t ERQ7:1;
      vuint32_t ERQ6:1;
      vuint32_t ERQ5:1;
      vuint32_t ERQ4:1;
      vuint32_t ERQ3:1;
      vuint32_t ERQ2:1;
      vuint32_t ERQ1:1;
      vuint32_t ERQ0:1;
    } B;
  } ERQL;

  union {                              /* Enable Error Interrupt Register High */
    vuint32_t R;
    struct {
      vuint32_t EEI63:1;
      vuint32_t EEI62:1;
      vuint32_t EEI61:1;
      vuint32_t EEI60:1;
      vuint32_t EEI59:1;
      vuint32_t EEI58:1;
      vuint32_t EEI57:1;
      vuint32_t EEI56:1;
      vuint32_t EEI55:1;
      vuint32_t EEI54:1;
      vuint32_t EEI53:1;
      vuint32_t EEI52:1;
      vuint32_t EEI51:1;
      vuint32_t EEI50:1;
      vuint32_t EEI49:1;
      vuint32_t EEI48:1;
      vuint32_t EEI47:1;
      vuint32_t EEI46:1;
      vuint32_t EEI45:1;
      vuint32_t EEI44:1;
      vuint32_t EEI43:1;
      vuint32_t EEI42:1;
      vuint32_t EEI41:1;
      vuint32_t EEI40:1;
      vuint32_t EEI39:1;
      vuint32_t EEI38:1;
      vuint32_t EEI37:1;
      vuint32_t EEI36:1;
      vuint32_t EEI35:1;
      vuint32_t EEI34:1;
      vuint32_t EEI33:1;
      vuint32_t EEI32:1;
    } B;
  } EEIH;

  union {                              /* Enable Error Interrupt Register Low */
    vuint32_t R;
    struct {
      vuint32_t EEI31:1;
      vuint32_t EEI30:1;
      vuint32_t EEI29:1;
      vuint32_t EEI28:1;
      vuint32_t EEI27:1;
      vuint32_t EEI26:1;
      vuint32_t EEI25:1;
      vuint32_t EEI24:1;
      vuint32_t EEI23:1;
      vuint32_t EEI22:1;
      vuint32_t EEI21:1;
      vuint32_t EEI20:1;
      vuint32_t EEI19:1;
      vuint32_t EEI18:1;
      vuint32_t EEI17:1;
      vuint32_t EEI16:1;
      vuint32_t EEI15:1;
      vuint32_t EEI14:1;
      vuint32_t EEI13:1;
      vuint32_t EEI12:1;
      vuint32_t EEI11:1;
      vuint32_t EEI10:1;
      vuint32_t EEI9:1;
      vuint32_t EEI8:1;
      vuint32_t EEI7:1;
      vuint32_t EEI6:1;
      vuint32_t EEI5:1;
      vuint32_t EEI4:1;
      vuint32_t EEI3:1;
      vuint32_t EEI2:1;
      vuint32_t EEI1:1;
      vuint32_t EEI0:1;
    } B;
  } EEIL;

  union {                              /* Set Enable Request Register */
    vuint8_t R;
    struct {
      vuint8_t NOP:1;
      vuint8_t SAER:1;
      vuint8_t SERQ:6;
    } B;
  } SERQ;

  union {                              /* Clear Enable Request Register */
    vuint8_t R;
    struct {
      vuint8_t NOP:1;
      vuint8_t CAER:1;
      vuint8_t CERQ:6;
    } B;
  } CERQ;

  union {                              /* Set Enable Error Interrupt Register */
    vuint8_t R;
    struct {
      vuint8_t NOP:1;
      vuint8_t SAEE:1;
      vuint8_t SEEI:6;
    } B;
  } SEEI;

  union {                              /* Clear Enable Error Interrupt Register */
    vuint8_t R;
    struct {
      vuint8_t NOP:1;
      vuint8_t CAEE:1;
      vuint8_t CEEI:6;
    } B;
  } CEEI;

  union {                              /* Clear Interrupt Request Register */
    vuint8_t R;
    struct {
      vuint8_t NOP:1;
      vuint8_t CAIR:1;
      vuint8_t CINT:6;
    } B;
  } CINT;

  union {                              /* Clear Error Register */
    vuint8_t R;
    struct {
      vuint8_t NOP:1;
      vuint8_t CAEI:1;
      vuint8_t CERR:6;
    } B;
  } CERR;

  union {                              /* Set START Bit Register */
    vuint8_t R;
    struct {
      vuint8_t NOP:1;
      vuint8_t SAST:1;
      vuint8_t SSRT:6;
    } B;
  } SSRT;

  union {                              /* Clear DONE Status Bit Register */
    vuint8_t R;
    struct {
      vuint8_t NOP:1;
      vuint8_t CADN:1;
      vuint8_t CDNE:6;
    } B;
  } CDNE;

  union {                              /* Interrupt Request Register High */
    vuint32_t R;
    struct {
      vuint32_t INT63:1;
      vuint32_t INT62:1;
      vuint32_t INT61:1;
      vuint32_t INT60:1;
      vuint32_t INT59:1;
      vuint32_t INT58:1;
      vuint32_t INT57:1;
      vuint32_t INT56:1;
      vuint32_t INT55:1;
      vuint32_t INT54:1;
      vuint32_t INT53:1;
      vuint32_t INT52:1;
      vuint32_t INT51:1;
      vuint32_t INT50:1;
      vuint32_t INT49:1;
      vuint32_t INT48:1;
      vuint32_t INT47:1;
      vuint32_t INT46:1;
      vuint32_t INT45:1;
      vuint32_t INT44:1;
      vuint32_t INT43:1;
      vuint32_t INT42:1;
      vuint32_t INT41:1;
      vuint32_t INT40:1;
      vuint32_t INT39:1;
      vuint32_t INT38:1;
      vuint32_t INT37:1;
      vuint32_t INT36:1;
      vuint32_t INT35:1;
      vuint32_t INT34:1;
      vuint32_t INT33:1;
      vuint32_t INT32:1;
    } B;
  } INTH;

  union {                              /* Interrupt Request Register Low */
    vuint32_t R;
    struct {
      vuint32_t INT31:1;
      vuint32_t INT30:1;
      vuint32_t INT29:1;
      vuint32_t INT28:1;
      vuint32_t INT27:1;
      vuint32_t INT26:1;
      vuint32_t INT25:1;
      vuint32_t INT24:1;
      vuint32_t INT23:1;
      vuint32_t INT22:1;
      vuint32_t INT21:1;
      vuint32_t INT20:1;
      vuint32_t INT19:1;
      vuint32_t INT18:1;
      vuint32_t INT17:1;
      vuint32_t INT16:1;
      vuint32_t INT15:1;
      vuint32_t INT14:1;
      vuint32_t INT13:1;
      vuint32_t INT12:1;
      vuint32_t INT11:1;
      vuint32_t INT10:1;
      vuint32_t INT9:1;
      vuint32_t INT8:1;
      vuint32_t INT7:1;
      vuint32_t INT6:1;
      vuint32_t INT5:1;
      vuint32_t INT4:1;
      vuint32_t INT3:1;
      vuint32_t INT2:1;
      vuint32_t INT1:1;
      vuint32_t INT0:1;
    } B;
  } INTL;

  union {                              /* Error Register High */
    vuint32_t R;
    struct {
      vuint32_t ERR63:1;
      vuint32_t ERR62:1;
      vuint32_t ERR61:1;
      vuint32_t ERR60:1;
      vuint32_t ERR59:1;
      vuint32_t ERR58:1;
      vuint32_t ERR57:1;
      vuint32_t ERR56:1;
      vuint32_t ERR55:1;
      vuint32_t ERR54:1;
      vuint32_t ERR53:1;
      vuint32_t ERR52:1;
      vuint32_t ERR51:1;
      vuint32_t ERR50:1;
      vuint32_t ERR49:1;
      vuint32_t ERR48:1;
      vuint32_t ERR47:1;
      vuint32_t ERR46:1;
      vuint32_t ERR45:1;
      vuint32_t ERR44:1;
      vuint32_t ERR43:1;
      vuint32_t ERR42:1;
      vuint32_t ERR41:1;
      vuint32_t ERR40:1;
      vuint32_t ERR39:1;
      vuint32_t ERR38:1;
      vuint32_t ERR37:1;
      vuint32_t ERR36:1;
      vuint32_t ERR35:1;
      vuint32_t ERR34:1;
      vuint32_t ERR33:1;
      vuint32_t ERR32:1;
    } B;
  } ERRH;

  union {                              /* Error Register Low */
    vuint32_t R;
    struct {
      vuint32_t ERR31:1;
      vuint32_t ERR30:1;
      vuint32_t ERR29:1;
      vuint32_t ERR28:1;
      vuint32_t ERR27:1;
      vuint32_t ERR26:1;
      vuint32_t ERR25:1;
      vuint32_t ERR24:1;
      vuint32_t ERR23:1;
      vuint32_t ERR22:1;
      vuint32_t ERR21:1;
      vuint32_t ERR20:1;
      vuint32_t ERR19:1;
      vuint32_t ERR18:1;
      vuint32_t ERR17:1;
      vuint32_t ERR16:1;
      vuint32_t ERR15:1;
      vuint32_t ERR14:1;
      vuint32_t ERR13:1;
      vuint32_t ERR12:1;
      vuint32_t ERR11:1;
      vuint32_t ERR10:1;
      vuint32_t ERR9:1;
      vuint32_t ERR8:1;
      vuint32_t ERR7:1;
      vuint32_t ERR6:1;
      vuint32_t ERR5:1;
      vuint32_t ERR4:1;
      vuint32_t ERR3:1;
      vuint32_t ERR2:1;
      vuint32_t ERR1:1;
      vuint32_t ERR0:1;
    } B;
  } ERRL;

  union {                              /* Hardware Request Status Register High */
    vuint32_t R;
    struct {
      vuint32_t HRS63:1;
      vuint32_t HRS62:1;
      vuint32_t HRS61:1;
      vuint32_t HRS60:1;
      vuint32_t HRS59:1;
      vuint32_t HRS58:1;
      vuint32_t HRS57:1;
      vuint32_t HRS56:1;
      vuint32_t HRS55:1;
      vuint32_t HRS54:1;
      vuint32_t HRS53:1;
      vuint32_t HRS52:1;
      vuint32_t HRS51:1;
      vuint32_t HRS50:1;
      vuint32_t HRS49:1;
      vuint32_t HRS48:1;
      vuint32_t HRS47:1;
      vuint32_t HRS46:1;
      vuint32_t HRS45:1;
      vuint32_t HRS44:1;
      vuint32_t HRS43:1;
      vuint32_t HRS42:1;
      vuint32_t HRS41:1;
      vuint32_t HRS40:1;
      vuint32_t HRS39:1;
      vuint32_t HRS38:1;
      vuint32_t HRS37:1;
      vuint32_t HRS36:1;
      vuint32_t HRS35:1;
      vuint32_t HRS34:1;
      vuint32_t HRS33:1;
      vuint32_t HRS32:1;
    } B;
  } HRSH;

  union {                              /* Hardware Request Status Register Low */
    vuint32_t R;
    struct {
      vuint32_t HRS31:1;
      vuint32_t HRS30:1;
      vuint32_t HRS29:1;
      vuint32_t HRS28:1;
      vuint32_t HRS27:1;
      vuint32_t HRS26:1;
      vuint32_t HRS25:1;
      vuint32_t HRS24:1;
      vuint32_t HRS23:1;
      vuint32_t HRS22:1;
      vuint32_t HRS21:1;
      vuint32_t HRS20:1;
      vuint32_t HRS19:1;
      vuint32_t HRS18:1;
      vuint32_t HRS17:1;
      vuint32_t HRS16:1;
      vuint32_t HRS15:1;
      vuint32_t HRS14:1;
      vuint32_t HRS13:1;
      vuint32_t HRS12:1;
      vuint32_t HRS11:1;
      vuint32_t HRS10:1;
      vuint32_t HRS9:1;
      vuint32_t HRS8:1;
      vuint32_t HRS7:1;
      vuint32_t HRS6:1;
      vuint32_t HRS5:1;
      vuint32_t HRS4:1;
      vuint32_t HRS3:1;
      vuint32_t HRS2:1;
      vuint32_t HRS1:1;
      vuint32_t HRS0:1;
    } B;
  } HRSL;

  uint8_t eDMA_reserved0[200];
  union {                              /* Channel Priority Register */
    vuint8_t R;
    struct {
      vuint8_t ECP:1;
      vuint8_t DPA:1;
      vuint8_t GRPPRI:2;
      vuint8_t CHPRI:4;
    } B;
  } DCHPRI[64];

  union {                              /* Channel Master ID Register */
    vuint8_t R;
    struct {
      vuint8_t EMI:1;
      vuint8_t PAL:1;
      vuint8_t  :2;
      vuint8_t MID:4;
    } B;
  } DCHMID[64];

  uint8_t eDMA_reserved1[3712];
  struct {
    union {                            /* TCD Source Address */
      vuint32_t R;
      struct {
        vuint32_t SADDR:32;
      } B;
    } SADDR;
    union {                            /* TCD Transfer Attributes */
      vuint16_t R;
      struct {
        vuint16_t SMOD:5;
        vuint16_t SSIZE:3;
        vuint16_t DMOD:5;
        vuint16_t DSIZE:3;
      } B;
    } ATTR;
    union {                            /* TCD Signed Source Address Offset */
      vuint16_t R;
      struct {
        vuint16_t SOFF:16;
      } B;
    } SOFF;
    union {
      union {                          /* TCD Minor Byte Count Minor Loop Disabled */
        vuint32_t R;
        struct {
          vuint32_t NBYTES:32;
        } B;
      } MLNO;
      union {                          /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
        vuint32_t R;
        struct {
          vuint32_t SMLOE:1;
          vuint32_t DMLOE:1;
          vuint32_t NBYTES:30;
        } B;
      } MLOFFNO;
      union {                          /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
        vuint32_t R;
        struct {
          vuint32_t SMLOE:1;
          vuint32_t DMLOE:1;
          vuint32_t MLOFF:20;
          vuint32_t NBYTES:10;
        } B;
      } MLOFFYES;
    } NBYTES;
    union {                            /* TCD Last Source Address Adjustment */
      vuint32_t R;
      struct {
        vuint32_t SLAST:32;
      } B;
    } SLAST;
    union {                            /* TCD Destination Address */
      vuint32_t R;
      struct {
        vuint32_t DADDR:32;
      } B;
    } DADDR;
    union {
      union {                          /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
        vuint16_t R;
        struct {
          vuint16_t ELINK:1;
          vuint16_t CITER:15;
        } B;
      } ELINKNO;
      union {                          /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
        vuint16_t R;
        struct {
          vuint16_t ELINK:1;
          vuint16_t LINKCH:6;
          vuint16_t CITER:9;
        } B;
      } ELINKYES;
    } CITER;
    union {                            /* TCD Signed Destination Address Offset */
      vuint16_t R;
      struct {
        vuint16_t DOFF:16;
      } B;
    } DOFF;
    union {                            /* TCD Last Destination Address Adjustment/Scatter Gather Address */
      vuint32_t R;
      struct {
        vuint32_t DLASTSGA:32;
      } B;
    } DLASTSGA;
    union {
      union {                          /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
        vuint16_t R;
        struct {
          vuint16_t ELINK:1;
          vuint16_t BITER:15;
        } B;
      } ELINKNO;
      union {                          /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
        vuint16_t R;
        struct {
          vuint16_t ELINK:1;
          vuint16_t LINKCH:6;
          vuint16_t BITER:9;
        } B;
      } ELINKYES;
    } BITER;
    union {                            /* TCD Control and Status */
      vuint16_t R;
      struct {
        vuint16_t BWC:2;
        vuint16_t MAJORLINKCH:6;
        vuint16_t DONE:1;
        vuint16_t ACTIVE:1;
        vuint16_t MAJORELINK:1;
        vuint16_t ESG:1;
        vuint16_t DREQ:1;
        vuint16_t INTHALF:1;
        vuint16_t INTMAJOR:1;
        vuint16_t START:1;
      } B;
    } CSR;
  } TCD[64];
};

#define SRAM0_START 0x40000000UL;
#define C55FMC (*(volatile struct C55FMC_tag *) 0xFFFE0000UL)
#define CMU_ADCSAR (*(volatile struct CMU_tag *) 0xFBFB0340UL)
#define CMU_ADCSD (*(volatile struct CMU_tag *) 0xFBFB0300UL)
#define CMU_CLKOUT (*(volatile struct CMU_tag *) 0xFBFB04C0UL)
#define CMU_CORE (*(volatile struct CMU_tag *) 0xFBFB0480UL)
#define CMU_FXBAR (*(volatile struct CMU_tag *) 0xFBFB0200UL)
#define CMU_PBRIDGE (*(volatile struct CMU_tag *) 0xFBFB0280UL)
#define CMU_PER (*(volatile struct CMU_tag *) 0xFBFB02C0UL)
#define CMU_PLL (*(volatile struct CMU_tag *) 0xFFFB0200UL)
#define CMU_PSI5_1US (*(volatile struct CMU_tag *) 0xFBFB0440UL)
#define CMU_PSI5_F125 (*(volatile struct CMU_tag *) 0xFBFB0400UL)
#define CMU_PSI5_F189 (*(volatile struct CMU_tag *) 0xFBFB03C0UL)
#define CMU_SENT (*(volatile struct CMU_tag *) 0xFBFB0380UL)
#define CMU_SXBAR (*(volatile struct CMU_tag *) 0xFBFB0240UL)
#define CRC_0 (*(volatile struct CRC_tag *) 0xFFF64000UL)
#define CRC_1 (*(volatile struct CRC_tag *) 0xFBF64000UL)
#define DMAMUX_0 (*(volatile struct DMAMUX_tag *) 0xFFF6C000UL)
#define DMAMUX_1 (*(volatile struct DMAMUX_tag *) 0xFFF6C200UL)
#define DMAMUX_2 (*(volatile struct DMAMUX_tag *) 0xFFF6C400UL)
#define DMAMUX_3 (*(volatile struct DMAMUX_tag *) 0xFFF6C600UL)
#define DMAMUX_4 (*(volatile struct DMAMUX_tag *) 0xFFF6C800UL)
#define DMAMUX_5 (*(volatile struct DMAMUX_tag *) 0xFFF6CA00UL)
#define DMAMUX_6 (*(volatile struct DMAMUX_tag *) 0xFFF6CC00UL)
#define DMAMUX_7 (*(volatile struct DMAMUX_tag *) 0xFFF6CE00UL)
#define DMAMUX_8 (*(volatile struct DMAMUX_tag *) 0xFFF6D000UL)
#define DMAMUX_9 (*(volatile struct DMAMUX_tag *) 0xFFF6D200UL)
#define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFE70000UL)
#define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFE74000UL)
#define DSPI_12 (*(volatile struct DSPI_tag *) 0xFFE88000UL)
#define DSPI_2 (*(volatile struct DSPI_tag *) 0xFBE70000UL)
#define DSPI_3 (*(volatile struct DSPI_tag *) 0xFBE74000UL)
#define DSPI_4 (*(volatile struct DSPI_tag *) 0xFFE78000UL)
#define DSPI_5 (*(volatile struct DSPI_tag *) 0xFBE78000UL)
#define DSPI_6 (*(volatile struct DSPI_tag *) 0xFFE7C000UL)
#define DTS (*(volatile struct DTS_tag *) 0xFFF38000UL)
#define EBI (*(volatile struct EBI_tag *) 0xFFFF0000UL)
#define FCCU (*(volatile struct FCCU_tag *) 0xFBF58000UL)
#define FEC (*(volatile struct FEC_tag *) 0xFC0B0000UL)
#define FR_0 (*(volatile struct FR_tag *) 0xFFE50000UL)
#define FR_1 (*(volatile struct FR_tag *) 0xFBE50000UL)
#define GTM (*(volatile struct GTM_tag *) 0xFFD00000UL)
#define GTMINT (*(volatile struct GTMINT_tag *) 0xFFD00000UL)
#define GTM_AFD_0 (*(volatile struct GTM_AFD_tag *) 0xFFD18000UL)
#define GTM_AFD_1 (*(volatile struct GTM_AFD_tag *) 0xFFD1C000UL)
#define GTM_ARU (*(volatile struct GTM_ARU_tag *) 0xFFD00280UL)
#define GTM_ATOM_0 (*(volatile struct GTM_ATOM_tag *) 0xFFD0D000UL)
#define GTM_ATOM_1 (*(volatile struct GTM_ATOM_tag *) 0xFFD0D800UL)
#define GTM_ATOM_2 (*(volatile struct GTM_ATOM_tag *) 0xFFD0E000UL)
#define GTM_ATOM_3 (*(volatile struct GTM_ATOM_tag *) 0xFFD0E800UL)
#define GTM_ATOM_4 (*(volatile struct GTM_ATOM_tag *) 0xFFD0F000UL)
#define GTM_ATOM_5 (*(volatile struct GTM_ATOM_tag *) 0xFFD0F800UL)
#define GTM_ATOM_6 (*(volatile struct GTM_ATOM_tag *) 0xFFD10000UL)
#define GTM_ATOM_7 (*(volatile struct GTM_ATOM_tag *) 0xFFD10800UL)
#define GTM_ATOM_8 (*(volatile struct GTM_ATOM_tag *) 0xFFD11000UL)
#define GTM_BRC (*(volatile struct GTM_BRC_tag *) 0xFFD00400UL)
#define GTM_CMP (*(volatile struct GTM_CMP_tag *) 0xFFD00200UL)
#define GTM_CMU (*(volatile struct GTM_CMU_tag *) 0xFFD00300UL)
#define GTM_DPLL (*(volatile struct GTM_DPLL_tag *) 0xFFD28000UL)
#define GTM_F2A_0 (*(volatile struct GTM_F2A_tag *) 0xFFD18080UL)
#define GTM_F2A_1 (*(volatile struct GTM_F2A_tag *) 0xFFD1C080UL)
#define GTM_FIFO_0 (*(volatile struct GTM_FIFO_tag *) 0xFFD18400UL)
#define GTM_FIFO_1 (*(volatile struct GTM_FIFO_tag *) 0xFFD1C400UL)
#define GTM_ICM (*(volatile struct GTM_ICM_tag *) 0xFFD00600UL)
#define GTM_MAP (*(volatile struct GTM_MAP_tag *) 0xFFD00F00UL)
#define GTM_MCFG (*(volatile struct GTM_MCFG_tag *) 0xFFD00F40UL)
#define GTM_MCS_0 (*(volatile struct GTM_MCS_tag *) 0xFFD30000UL)
#define GTM_MCS_1 (*(volatile struct GTM_MCS_tag *) 0xFFD31000UL)
#define GTM_MCS_2 (*(volatile struct GTM_MCS_tag *) 0xFFD32000UL)
#define GTM_MCS_3 (*(volatile struct GTM_MCS_tag *) 0xFFD33000UL)
#define GTM_MCS_4 (*(volatile struct GTM_MCS_tag *) 0xFFD34000UL)
#define GTM_MCS_5 (*(volatile struct GTM_MCS_tag *) 0xFFD35000UL)
#define GTM_MON (*(volatile struct GTM_MON_tag *) 0xFFD00180UL)
#define GTM_SPE_0 (*(volatile struct GTM_SPE_tag *) 0xFFD00800UL)
#define GTM_SPE_1 (*(volatile struct GTM_SPE_tag *) 0xFFD00880UL)
#define GTM_SPE_2 (*(volatile struct GTM_SPE_tag *) 0xFFD00900UL)
#define GTM_SPE_3 (*(volatile struct GTM_SPE_tag *) 0xFFD00980UL)
#define GTM_TBU (*(volatile struct GTM_TBU_tag *) 0xFFD00100UL)
#define GTM_TIM_0 (*(volatile struct GTM_TIM_tag *) 0xFFD01000UL)
#define GTM_TIM_1 (*(volatile struct GTM_TIM_tag *) 0xFFD01800UL)
#define GTM_TIM_2 (*(volatile struct GTM_TIM_tag *) 0xFFD02000UL)
#define GTM_TIM_3 (*(volatile struct GTM_TIM_tag *) 0xFFD02800UL)
#define GTM_TIM_4 (*(volatile struct GTM_TIM_tag *) 0xFFD03000UL)
#define GTM_TIM_5 (*(volatile struct GTM_TIM_tag *) 0xFFD03800UL)
#define GTM_TOM_0 (*(volatile struct GTM_TOM_tag *) 0xFFD08000UL)
#define GTM_TOM_1 (*(volatile struct GTM_TOM_tag *) 0xFFD08800UL)
#define GTM_TOM_2 (*(volatile struct GTM_TOM_tag *) 0xFFD09000UL)
#define GTM_TOM_3 (*(volatile struct GTM_TOM_tag *) 0xFFD09800UL)
#define GTM_TOM_4 (*(volatile struct GTM_TOM_tag *) 0xFFD0A000UL)
#define I2C_0 (*(volatile struct I2C_tag *) 0xFFE68000UL)
#define I2C_1 (*(volatile struct I2C_tag *) 0xFBE68000UL)
#define IMA (*(volatile struct IMA_tag *) 0xFFF54000UL)
#define INTC_0 (*(volatile struct INTC_tag *) 0xFC040000UL)
#define IRCOSC (*(volatile struct IRCOSC_tag *) 0xFFFB0000UL)
#define JDC (*(volatile struct JDC_tag *) 0xFFF3C000UL)
#define JTAGM (*(volatile struct JTAGM_tag *) 0xFFF48000UL)
#define LFAST_0 (*(volatile struct LFAST_tag *) 0xFFFD8000UL)
#define LINFlexD_0 (*(volatile struct LINFlexD_tag *) 0xFFE8C000UL)
#define LINFlexD_1 (*(volatile struct LINFlexD_tag *) 0xFFE90000UL)
#define LINFlexD_14 (*(volatile struct LINFlexD_tag *) 0xFFEA8000UL)
#define LINFlexD_15 (*(volatile struct LINFlexD_tag *) 0xFBEA8000UL)
#define LINFlexD_16 (*(volatile struct LINFlexD_tag *) 0xFFEAC000UL)
#define LINFlexD_2 (*(volatile struct LINFlexD_tag *) 0xFBE8C000UL)
#define MC_CGM (*(volatile struct MC_CGM_tag *) 0xFFFB0000UL)
#define MC_ME (*(volatile struct MC_ME_tag *) 0xFFFB8000UL)
#define MC_PCU (*(volatile struct MC_PCU_tag *) 0xFFFA0000UL)
#define MC_RGM (*(volatile struct MC_RGM_tag *) 0xFFFA8000UL)
#define MEMU (*(volatile struct MEMU_tag *) 0xFFF50000UL)
#define M_CAN_1 (*(volatile struct M_CAN_tag *) 0xFFEE4000UL)
#define M_CAN_2 (*(volatile struct M_CAN_tag *) 0xFFEE8000UL)
#define M_CAN_3 (*(volatile struct M_CAN_tag *) 0xFFEEC000UL)
#define M_CAN_4 (*(volatile struct M_CAN_tag *) 0xFFEF0000UL)
#define M_TTCAN (*(volatile struct M_TTCAN_tag *) 0xFFEDC000UL)
#define PASS (*(volatile struct PASS_tag *) 0xFFFF4000UL)
#define PBRIDGE_A (*(volatile struct PBRIDGE_tag *) 0xFC000000UL)
#define PBRIDGE_B (*(volatile struct PBRIDGE_tag *) 0xF8000000UL)
#define PCM (*(volatile struct PCM_tag *) 0xFC028000UL)
#define PFLASH (*(volatile struct PFLASH_tag *) 0xFC030000UL)
#define PIT_0 (*(volatile struct PIT_tag *) 0xFFF84000UL)
#define PIT_1 (*(volatile struct PIT_tag *) 0xFFF80000UL)
#define PLLDIG (*(volatile struct PLLDIG_tag *) 0xFFFB0100UL)
#define PMCDIG (*(volatile struct PMCDIG_tag *) 0xFFFA0400UL)
#define PRAMC (*(volatile struct PRAMC_tag *) 0xFC020000UL)
#define PSI5_0 (*(volatile struct PSI5_tag *) 0xFFE40000UL)
#define PSI5_1 (*(volatile struct PSI5_tag *) 0xFBE40000UL)
#define PSI5S (*(volatile struct PSI5S_tag *) 0xFBF74000UL)
#define REG_PROT (*(volatile struct REG_PROT_tag *) 0UL)
#define SARADC_0 (*(volatile struct SARADC_tag *) 0xFFE00000UL)
#define SARADC_1 (*(volatile struct SARADC_tag *) 0xFBE04000UL)
#define SARADC_10 (*(volatile struct SARADC_tag *) 0xFBE28000UL)
#define SARADC_2 (*(volatile struct SARADC_tag *) 0xFBE08000UL)
#define SARADC_3 (*(volatile struct SARADC_tag *) 0xFBE0C000UL)
#define SARADC_4 (*(volatile struct SARADC_tag *) 0xFFE10000UL)
#define SARADC_5 (*(volatile struct SARADC_tag *) 0xFBE14000UL)
#define SARADC_6 (*(volatile struct SARADC_tag *) 0xFBE18000UL)
#define SARADC_7 (*(volatile struct SARADC_tag *) 0xFBE1C000UL)
#define SARADC_8 (*(volatile struct SARADC_tag *) 0xFBE20000UL)
#define SARADC_9 (*(volatile struct SARADC_tag *) 0xFBE24000UL)
#define SARADC_B (*(volatile struct SARADC_tag *) 0xFFE3C000UL)
#define SDADC_0 (*(volatile struct SDADC_tag *) 0xFFF0C000UL)
#define SDADC_1 (*(volatile struct SDADC_tag *) 0xFBF0C000UL)
#define SDADC_2 (*(volatile struct SDADC_tag *) 0xFFF10000UL)
#define SDADC_3 (*(volatile struct SDADC_tag *) 0xFBF10000UL)
#define SDADC_4 (*(volatile struct SDADC_tag *) 0xFFF14000UL)
#define SDADC_5 (*(volatile struct SDADC_tag *) 0xFBF14000UL)
#define SDADC_6 (*(volatile struct SDADC_tag *) 0xFFF18000UL)
#define SDADC_7 (*(volatile struct SDADC_tag *) 0xFBF18000UL)
#define SDADC_8 (*(volatile struct SDADC_tag *) 0xFFF1C000UL)
#define SDADC_9 (*(volatile struct SDADC_tag *) 0xFBF1C000UL)
#define SEMA42 (*(volatile struct SEMA42_tag *) 0xFC03C000UL)
#define SIPI_0 (*(volatile struct SIPI_tag *) 0xFFFD0000UL)
#define SIPI_1 (*(volatile struct SIPI_tag *) 0xFFFD4000UL)
#define SIUL2 (*(volatile struct SIUL2_tag *) 0xFFFC0000UL)
#define SMPU_0 (*(volatile struct SMPU_tag *) 0xFC010000UL)
#define SMPU_1 (*(volatile struct SMPU_tag *) 0xFC014000UL)
#define SRX_0 (*(volatile struct SRX_tag *) 0xFFE5C000UL)
#define SRX_1 (*(volatile struct SRX_tag *) 0xFBE5C000UL)
#define SSCM (*(volatile struct SSCM_tag *) 0xFFFF8000UL)
#define STCU2 (*(volatile struct STCU2_tag *) 0xFFF44000UL)
#define STM_0 (*(volatile struct STM_tag *) 0xFC068000UL)
#define STM_1 (*(volatile struct STM_tag *) 0xFC06C000UL)
#define STM_2 (*(volatile struct STM_tag *) 0xFC070000UL)
#define SWT_0 (*(volatile struct SWT_tag *) 0xFC050000UL)
#define SWT_1 (*(volatile struct SWT_tag *) 0xFC054000UL)
#define SWT_2 (*(volatile struct SWT_tag *) 0xFC058000UL)
#define SWT_3 (*(volatile struct SWT_tag *) 0xFC05C000UL)
#define TDM (*(volatile struct TDM_tag *) 0xFFF34000UL)
#define WKPU (*(volatile struct WKPU_tag *) 0xFFF98000UL)
#define XBAR_0 (*(volatile struct XBAR_tag *) 0xFC004000UL)
#define XBAR_1 (*(volatile struct XBAR_tag *) 0xFC008000UL)
#define XBIC_0 (*(volatile struct XBIC_tag *) 0xFC018000UL)
#define XBIC_1 (*(volatile struct XBIC_tag *) 0xFC01C000UL)
#define XOSC (*(volatile struct XOSC_tag *) 0xFFFB0080UL)
#define eDMA_0 (*(volatile struct eDMA_tag *) 0xFC0A0000UL)
#define eDMA_1 (*(volatile struct eDMA_tag *) 0xFC0A4000UL)

/* C55FMC */
#define C55FMC_MCR           C55FMC.MCR.R                  /* Module Configuration Register */
#define C55FMC_MCRA          C55FMC.MCRA.R                 /* Alternate Module Configuration Register */
#define C55FMC_MCRE          C55FMC.MCRE.R                 /* Extended Module Configuration Register */
#define C55FMC_LOCK0         C55FMC.LOCK0.R                /* Lock 0 register */
#define C55FMC_LOCK1         C55FMC.LOCK1.R                /* Lock 1 register */
#define C55FMC_LOCK2         C55FMC.LOCK2.R                /* Lock 2 register */
#define C55FMC_LOCK3         C55FMC.LOCK3.R                /* Lock 3 register */
#define C55FMC_LOCK0A        C55FMC.LOCK0A.R               /* Alternate Lock 0 register */
#define C55FMC_LOCK1A        C55FMC.LOCK1A.R               /* Alternate Lock 1 register */
#define C55FMC_SEL0          C55FMC.SEL0.R                 /* Select 0 register */
#define C55FMC_SEL1          C55FMC.SEL1.R                 /* Select 1 register */
#define C55FMC_SEL2          C55FMC.SEL2.R                 /* Select 2 register */
#define C55FMC_SEL3          C55FMC.SEL3.R                 /* Select 3 register */
#define C55FMC_ADR           C55FMC.ADR.R                  /* Address register */
#define C55FMC_UT0           C55FMC.UT0.R                  /* UTest 0 register */
#define C55FMC_UM0           C55FMC.UM[0].R                /* UMISR register */
#define C55FMC_UM1           C55FMC.UM[1].R                /* UMISR register */
#define C55FMC_UM2           C55FMC.UM[2].R                /* UMISR register */
#define C55FMC_UM3           C55FMC.UM[3].R                /* UMISR register */
#define C55FMC_UM4           C55FMC.UM[4].R                /* UMISR register */
#define C55FMC_UM5           C55FMC.UM[5].R                /* UMISR register */
#define C55FMC_UM6           C55FMC.UM[6].R                /* UMISR register */
#define C55FMC_UM7           C55FMC.UM[7].R                /* UMISR register */
#define C55FMC_UM8           C55FMC.UM[8].R                /* UMISR register */
#define C55FMC_UM9           C55FMC.UM9.R                  /* UMISR register */
#define C55FMC_OPP0          C55FMC.OPP0.R                 /* Over-Program Protection 0 register */
#define C55FMC_OPP1          C55FMC.OPP1.R                 /* Over-Program Protection 1 register */
#define C55FMC_OPP2          C55FMC.OPP2.R                 /* Over-Program Protection 2 register */
#define C55FMC_OPP3          C55FMC.OPP3.R                 /* Over-Program Protection 3 register */
#define C55FMC_TMD           C55FMC.TMD.R                  /* Test Mode Disable Password Check register */

/* CMU */
#define CMU_ADCSAR_CSR       CMU_ADCSAR.CSR.R              /* CMU Control Status Register */
#define CMU_ADCSAR_FDR       CMU_ADCSAR.FDR.R              /* CMU Frequency Display Register */
#define CMU_ADCSAR_HFREFR    CMU_ADCSAR.HFREFR.R           /* CMU High Frequency Reference Register CLKMN1 */
#define CMU_ADCSAR_LFREFR    CMU_ADCSAR.LFREFR.R           /* CMU Low Frequency Reference Register CLKMN1 */
#define CMU_ADCSAR_ISR       CMU_ADCSAR.ISR.R              /* CMU Interrupt Status Register */
#define CMU_ADCSAR_MDR       CMU_ADCSAR.MDR.R              /* CMU Measurement Duration Register */

/* CMU */
#define CMU_ADCSD_CSR        CMU_ADCSD.CSR.R               /* CMU Control Status Register */
#define CMU_ADCSD_FDR        CMU_ADCSD.FDR.R               /* CMU Frequency Display Register */
#define CMU_ADCSD_HFREFR     CMU_ADCSD.HFREFR.R            /* CMU High Frequency Reference Register CLKMN1 */
#define CMU_ADCSD_LFREFR     CMU_ADCSD.LFREFR.R            /* CMU Low Frequency Reference Register CLKMN1 */
#define CMU_ADCSD_ISR        CMU_ADCSD.ISR.R               /* CMU Interrupt Status Register */
#define CMU_ADCSD_MDR        CMU_ADCSD.MDR.R               /* CMU Measurement Duration Register */

/* CMU */
#define CMU_CLKOUT_CSR       CMU_CLKOUT.CSR.R              /* CMU Control Status Register */
#define CMU_CLKOUT_FDR       CMU_CLKOUT.FDR.R              /* CMU Frequency Display Register */
#define CMU_CLKOUT_HFREFR    CMU_CLKOUT.HFREFR.R           /* CMU High Frequency Reference Register CLKMN1 */
#define CMU_CLKOUT_LFREFR    CMU_CLKOUT.LFREFR.R           /* CMU Low Frequency Reference Register CLKMN1 */
#define CMU_CLKOUT_ISR       CMU_CLKOUT.ISR.R              /* CMU Interrupt Status Register */
#define CMU_CLKOUT_MDR       CMU_CLKOUT.MDR.R              /* CMU Measurement Duration Register */

/* CMU */
#define CMU_CORE_CSR         CMU_CORE.CSR.R                /* CMU Control Status Register */
#define CMU_CORE_FDR         CMU_CORE.FDR.R                /* CMU Frequency Display Register */
#define CMU_CORE_HFREFR      CMU_CORE.HFREFR.R             /* CMU High Frequency Reference Register CLKMN1 */
#define CMU_CORE_LFREFR      CMU_CORE.LFREFR.R             /* CMU Low Frequency Reference Register CLKMN1 */
#define CMU_CORE_ISR         CMU_CORE.ISR.R                /* CMU Interrupt Status Register */
#define CMU_CORE_MDR         CMU_CORE.MDR.R                /* CMU Measurement Duration Register */

/* CMU */
#define CMU_FXBAR_CSR        CMU_FXBAR.CSR.R               /* CMU Control Status Register */
#define CMU_FXBAR_FDR        CMU_FXBAR.FDR.R               /* CMU Frequency Display Register */
#define CMU_FXBAR_HFREFR     CMU_FXBAR.HFREFR.R            /* CMU High Frequency Reference Register CLKMN1 */
#define CMU_FXBAR_LFREFR     CMU_FXBAR.LFREFR.R            /* CMU Low Frequency Reference Register CLKMN1 */
#define CMU_FXBAR_ISR        CMU_FXBAR.ISR.R               /* CMU Interrupt Status Register */
#define CMU_FXBAR_MDR        CMU_FXBAR.MDR.R               /* CMU Measurement Duration Register */

/* CMU */
#define CMU_PBRIDGE_CSR      CMU_PBRIDGE.CSR.R             /* CMU Control Status Register */
#define CMU_PBRIDGE_FDR      CMU_PBRIDGE.FDR.R             /* CMU Frequency Display Register */
#define CMU_PBRIDGE_HFREFR   CMU_PBRIDGE.HFREFR.R          /* CMU High Frequency Reference Register CLKMN1 */
#define CMU_PBRIDGE_LFREFR   CMU_PBRIDGE.LFREFR.R          /* CMU Low Frequency Reference Register CLKMN1 */
#define CMU_PBRIDGE_ISR      CMU_PBRIDGE.ISR.R             /* CMU Interrupt Status Register */
#define CMU_PBRIDGE_MDR      CMU_PBRIDGE.MDR.R             /* CMU Measurement Duration Register */

/* CMU */
#define CMU_PER_CSR          CMU_PER.CSR.R                 /* CMU Control Status Register */
#define CMU_PER_FDR          CMU_PER.FDR.R                 /* CMU Frequency Display Register */
#define CMU_PER_HFREFR       CMU_PER.HFREFR.R              /* CMU High Frequency Reference Register CLKMN1 */
#define CMU_PER_LFREFR       CMU_PER.LFREFR.R              /* CMU Low Frequency Reference Register CLKMN1 */
#define CMU_PER_ISR          CMU_PER.ISR.R                 /* CMU Interrupt Status Register */
#define CMU_PER_MDR          CMU_PER.MDR.R                 /* CMU Measurement Duration Register */

/* CMU */
#define CMU_PLL_CSR          CMU_PLL.CSR.R                 /* CMU Control Status Register */
#define CMU_PLL_FDR          CMU_PLL.FDR.R                 /* CMU Frequency Display Register */
#define CMU_PLL_HFREFR       CMU_PLL.HFREFR.R              /* CMU High Frequency Reference Register CLKMN1 */
#define CMU_PLL_LFREFR       CMU_PLL.LFREFR.R              /* CMU Low Frequency Reference Register CLKMN1 */
#define CMU_PLL_ISR          CMU_PLL.ISR.R                 /* CMU Interrupt Status Register */
#define CMU_PLL_MDR          CMU_PLL.MDR.R                 /* CMU Measurement Duration Register */

/* CMU */
#define CMU_PSI5_1US_CSR     CMU_PSI5_1US.CSR.R            /* CMU Control Status Register */
#define CMU_PSI5_1US_FDR     CMU_PSI5_1US.FDR.R            /* CMU Frequency Display Register */
#define CMU_PSI5_1US_HFREFR  CMU_PSI5_1US.HFREFR.R         /* CMU High Frequency Reference Register CLKMN1 */
#define CMU_PSI5_1US_LFREFR  CMU_PSI5_1US.LFREFR.R         /* CMU Low Frequency Reference Register CLKMN1 */
#define CMU_PSI5_1US_ISR     CMU_PSI5_1US.ISR.R            /* CMU Interrupt Status Register */
#define CMU_PSI5_1US_MDR     CMU_PSI5_1US.MDR.R            /* CMU Measurement Duration Register */

/* CMU */
#define CMU_PSI5_F125_CSR    CMU_PSI5_F125.CSR.R           /* CMU Control Status Register */
#define CMU_PSI5_F125_FDR    CMU_PSI5_F125.FDR.R           /* CMU Frequency Display Register */
#define CMU_PSI5_F125_HFREFR CMU_PSI5_F125.HFREFR.R        /* CMU High Frequency Reference Register CLKMN1 */
#define CMU_PSI5_F125_LFREFR CMU_PSI5_F125.LFREFR.R        /* CMU Low Frequency Reference Register CLKMN1 */
#define CMU_PSI5_F125_ISR    CMU_PSI5_F125.ISR.R           /* CMU Interrupt Status Register */
#define CMU_PSI5_F125_MDR    CMU_PSI5_F125.MDR.R           /* CMU Measurement Duration Register */

/* CMU */
#define CMU_PSI5_F189_CSR    CMU_PSI5_F189.CSR.R           /* CMU Control Status Register */
#define CMU_PSI5_F189_FDR    CMU_PSI5_F189.FDR.R           /* CMU Frequency Display Register */
#define CMU_PSI5_F189_HFREFR CMU_PSI5_F189.HFREFR.R        /* CMU High Frequency Reference Register CLKMN1 */
#define CMU_PSI5_F189_LFREFR CMU_PSI5_F189.LFREFR.R        /* CMU Low Frequency Reference Register CLKMN1 */
#define CMU_PSI5_F189_ISR    CMU_PSI5_F189.ISR.R           /* CMU Interrupt Status Register */
#define CMU_PSI5_F189_MDR    CMU_PSI5_F189.MDR.R           /* CMU Measurement Duration Register */

/* CMU */
#define CMU_SENT_CSR         CMU_SENT.CSR.R                /* CMU Control Status Register */
#define CMU_SENT_FDR         CMU_SENT.FDR.R                /* CMU Frequency Display Register */
#define CMU_SENT_HFREFR      CMU_SENT.HFREFR.R             /* CMU High Frequency Reference Register CLKMN1 */
#define CMU_SENT_LFREFR      CMU_SENT.LFREFR.R             /* CMU Low Frequency Reference Register CLKMN1 */
#define CMU_SENT_ISR         CMU_SENT.ISR.R                /* CMU Interrupt Status Register */
#define CMU_SENT_MDR         CMU_SENT.MDR.R                /* CMU Measurement Duration Register */

/* CMU */
#define CMU_SXBAR_CSR        CMU_SXBAR.CSR.R               /* CMU Control Status Register */
#define CMU_SXBAR_FDR        CMU_SXBAR.FDR.R               /* CMU Frequency Display Register */
#define CMU_SXBAR_HFREFR     CMU_SXBAR.HFREFR.R            /* CMU High Frequency Reference Register CLKMN1 */
#define CMU_SXBAR_LFREFR     CMU_SXBAR.LFREFR.R            /* CMU Low Frequency Reference Register CLKMN1 */
#define CMU_SXBAR_ISR        CMU_SXBAR.ISR.R               /* CMU Interrupt Status Register */
#define CMU_SXBAR_MDR        CMU_SXBAR.MDR.R               /* CMU Measurement Duration Register */

/* CRC */
#define CRC_0_CFG            CRC_0.CFG.R                   /* Configuration Register */
#define CRC_0_INP            CRC_0.INP.R                   /* Input Register */
#define CRC_0_CSTAT          CRC_0.CSTAT.R                 /* Current Status Register */
#define CRC_0_OUTP           CRC_0.OUTP.R                  /* Output Register */

/* CRC */
#define CRC_1_CFG            CRC_1.CFG.R                   /* Configuration Register */
#define CRC_1_INP            CRC_1.INP.R                   /* Input Register */
#define CRC_1_CSTAT          CRC_1.CSTAT.R                 /* Current Status Register */
#define CRC_1_OUTP           CRC_1.OUTP.R                  /* Output Register */

/* DMAMUX */
#define DMAMUX_0_CHCFG0      DMAMUX_0.CHCFG[0].R           /* Channel Configuration register */
#define DMAMUX_0_CHCFG1      DMAMUX_0.CHCFG[1].R           /* Channel Configuration register */
#define DMAMUX_0_CHCFG2      DMAMUX_0.CHCFG[2].R           /* Channel Configuration register */
#define DMAMUX_0_CHCFG3      DMAMUX_0.CHCFG[3].R           /* Channel Configuration register */
#define DMAMUX_0_CHCFG4      DMAMUX_0.CHCFG[4].R           /* Channel Configuration register */
#define DMAMUX_0_CHCFG5      DMAMUX_0.CHCFG[5].R           /* Channel Configuration register */
#define DMAMUX_0_CHCFG6      DMAMUX_0.CHCFG[6].R           /* Channel Configuration register */
#define DMAMUX_0_CHCFG7      DMAMUX_0.CHCFG[7].R           /* Channel Configuration register */
#define DMAMUX_0_CHCFG8      DMAMUX_0.CHCFG[8].R           /* Channel Configuration register */
#define DMAMUX_0_CHCFG9      DMAMUX_0.CHCFG[9].R           /* Channel Configuration register */
#define DMAMUX_0_CHCFG10     DMAMUX_0.CHCFG[10].R          /* Channel Configuration register */
#define DMAMUX_0_CHCFG11     DMAMUX_0.CHCFG[11].R          /* Channel Configuration register */
#define DMAMUX_0_CHCFG12     DMAMUX_0.CHCFG[12].R          /* Channel Configuration register */
#define DMAMUX_0_CHCFG13     DMAMUX_0.CHCFG[13].R          /* Channel Configuration register */
#define DMAMUX_0_CHCFG14     DMAMUX_0.CHCFG[14].R          /* Channel Configuration register */
#define DMAMUX_0_CHCFG15     DMAMUX_0.CHCFG[15].R          /* Channel Configuration register */

/* DMAMUX */
#define DMAMUX_1_CHCFG0      DMAMUX_1.CHCFG[0].R           /* Channel Configuration register */
#define DMAMUX_1_CHCFG1      DMAMUX_1.CHCFG[1].R           /* Channel Configuration register */
#define DMAMUX_1_CHCFG2      DMAMUX_1.CHCFG[2].R           /* Channel Configuration register */
#define DMAMUX_1_CHCFG3      DMAMUX_1.CHCFG[3].R           /* Channel Configuration register */
#define DMAMUX_1_CHCFG4      DMAMUX_1.CHCFG[4].R           /* Channel Configuration register */
#define DMAMUX_1_CHCFG5      DMAMUX_1.CHCFG[5].R           /* Channel Configuration register */
#define DMAMUX_1_CHCFG6      DMAMUX_1.CHCFG[6].R           /* Channel Configuration register */
#define DMAMUX_1_CHCFG7      DMAMUX_1.CHCFG[7].R           /* Channel Configuration register */
#define DMAMUX_1_CHCFG8      DMAMUX_1.CHCFG[8].R           /* Channel Configuration register */
#define DMAMUX_1_CHCFG9      DMAMUX_1.CHCFG[9].R           /* Channel Configuration register */
#define DMAMUX_1_CHCFG10     DMAMUX_1.CHCFG[10].R          /* Channel Configuration register */
#define DMAMUX_1_CHCFG11     DMAMUX_1.CHCFG[11].R          /* Channel Configuration register */
#define DMAMUX_1_CHCFG12     DMAMUX_1.CHCFG[12].R          /* Channel Configuration register */
#define DMAMUX_1_CHCFG13     DMAMUX_1.CHCFG[13].R          /* Channel Configuration register */
#define DMAMUX_1_CHCFG14     DMAMUX_1.CHCFG[14].R          /* Channel Configuration register */
#define DMAMUX_1_CHCFG15     DMAMUX_1.CHCFG[15].R          /* Channel Configuration register */

/* DMAMUX */
#define DMAMUX_2_CHCFG0      DMAMUX_2.CHCFG[0].R           /* Channel Configuration register */
#define DMAMUX_2_CHCFG1      DMAMUX_2.CHCFG[1].R           /* Channel Configuration register */
#define DMAMUX_2_CHCFG2      DMAMUX_2.CHCFG[2].R           /* Channel Configuration register */
#define DMAMUX_2_CHCFG3      DMAMUX_2.CHCFG[3].R           /* Channel Configuration register */
#define DMAMUX_2_CHCFG4      DMAMUX_2.CHCFG[4].R           /* Channel Configuration register */
#define DMAMUX_2_CHCFG5      DMAMUX_2.CHCFG[5].R           /* Channel Configuration register */
#define DMAMUX_2_CHCFG6      DMAMUX_2.CHCFG[6].R           /* Channel Configuration register */
#define DMAMUX_2_CHCFG7      DMAMUX_2.CHCFG[7].R           /* Channel Configuration register */
#define DMAMUX_2_CHCFG8      DMAMUX_2.CHCFG[8].R           /* Channel Configuration register */
#define DMAMUX_2_CHCFG9      DMAMUX_2.CHCFG[9].R           /* Channel Configuration register */
#define DMAMUX_2_CHCFG10     DMAMUX_2.CHCFG[10].R          /* Channel Configuration register */
#define DMAMUX_2_CHCFG11     DMAMUX_2.CHCFG[11].R          /* Channel Configuration register */
#define DMAMUX_2_CHCFG12     DMAMUX_2.CHCFG[12].R          /* Channel Configuration register */
#define DMAMUX_2_CHCFG13     DMAMUX_2.CHCFG[13].R          /* Channel Configuration register */
#define DMAMUX_2_CHCFG14     DMAMUX_2.CHCFG[14].R          /* Channel Configuration register */
#define DMAMUX_2_CHCFG15     DMAMUX_2.CHCFG[15].R          /* Channel Configuration register */

/* DMAMUX */
#define DMAMUX_3_CHCFG0      DMAMUX_3.CHCFG[0].R           /* Channel Configuration register */
#define DMAMUX_3_CHCFG1      DMAMUX_3.CHCFG[1].R           /* Channel Configuration register */
#define DMAMUX_3_CHCFG2      DMAMUX_3.CHCFG[2].R           /* Channel Configuration register */
#define DMAMUX_3_CHCFG3      DMAMUX_3.CHCFG[3].R           /* Channel Configuration register */
#define DMAMUX_3_CHCFG4      DMAMUX_3.CHCFG[4].R           /* Channel Configuration register */
#define DMAMUX_3_CHCFG5      DMAMUX_3.CHCFG[5].R           /* Channel Configuration register */
#define DMAMUX_3_CHCFG6      DMAMUX_3.CHCFG[6].R           /* Channel Configuration register */
#define DMAMUX_3_CHCFG7      DMAMUX_3.CHCFG[7].R           /* Channel Configuration register */
#define DMAMUX_3_CHCFG8      DMAMUX_3.CHCFG[8].R           /* Channel Configuration register */
#define DMAMUX_3_CHCFG9      DMAMUX_3.CHCFG[9].R           /* Channel Configuration register */
#define DMAMUX_3_CHCFG10     DMAMUX_3.CHCFG[10].R          /* Channel Configuration register */
#define DMAMUX_3_CHCFG11     DMAMUX_3.CHCFG[11].R          /* Channel Configuration register */
#define DMAMUX_3_CHCFG12     DMAMUX_3.CHCFG[12].R          /* Channel Configuration register */
#define DMAMUX_3_CHCFG13     DMAMUX_3.CHCFG[13].R          /* Channel Configuration register */
#define DMAMUX_3_CHCFG14     DMAMUX_3.CHCFG[14].R          /* Channel Configuration register */
#define DMAMUX_3_CHCFG15     DMAMUX_3.CHCFG[15].R          /* Channel Configuration register */

/* DMAMUX */
#define DMAMUX_4_CHCFG0      DMAMUX_4.CHCFG[0].R           /* Channel Configuration register */
#define DMAMUX_4_CHCFG1      DMAMUX_4.CHCFG[1].R           /* Channel Configuration register */
#define DMAMUX_4_CHCFG2      DMAMUX_4.CHCFG[2].R           /* Channel Configuration register */
#define DMAMUX_4_CHCFG3      DMAMUX_4.CHCFG[3].R           /* Channel Configuration register */
#define DMAMUX_4_CHCFG4      DMAMUX_4.CHCFG[4].R           /* Channel Configuration register */
#define DMAMUX_4_CHCFG5      DMAMUX_4.CHCFG[5].R           /* Channel Configuration register */
#define DMAMUX_4_CHCFG6      DMAMUX_4.CHCFG[6].R           /* Channel Configuration register */
#define DMAMUX_4_CHCFG7      DMAMUX_4.CHCFG[7].R           /* Channel Configuration register */
#define DMAMUX_4_CHCFG8      DMAMUX_4.CHCFG[8].R           /* Channel Configuration register */
#define DMAMUX_4_CHCFG9      DMAMUX_4.CHCFG[9].R           /* Channel Configuration register */
#define DMAMUX_4_CHCFG10     DMAMUX_4.CHCFG[10].R          /* Channel Configuration register */
#define DMAMUX_4_CHCFG11     DMAMUX_4.CHCFG[11].R          /* Channel Configuration register */
#define DMAMUX_4_CHCFG12     DMAMUX_4.CHCFG[12].R          /* Channel Configuration register */
#define DMAMUX_4_CHCFG13     DMAMUX_4.CHCFG[13].R          /* Channel Configuration register */
#define DMAMUX_4_CHCFG14     DMAMUX_4.CHCFG[14].R          /* Channel Configuration register */
#define DMAMUX_4_CHCFG15     DMAMUX_4.CHCFG[15].R          /* Channel Configuration register */

/* DMAMUX */
#define DMAMUX_5_CHCFG0      DMAMUX_5.CHCFG[0].R           /* Channel Configuration register */
#define DMAMUX_5_CHCFG1      DMAMUX_5.CHCFG[1].R           /* Channel Configuration register */
#define DMAMUX_5_CHCFG2      DMAMUX_5.CHCFG[2].R           /* Channel Configuration register */
#define DMAMUX_5_CHCFG3      DMAMUX_5.CHCFG[3].R           /* Channel Configuration register */
#define DMAMUX_5_CHCFG4      DMAMUX_5.CHCFG[4].R           /* Channel Configuration register */
#define DMAMUX_5_CHCFG5      DMAMUX_5.CHCFG[5].R           /* Channel Configuration register */
#define DMAMUX_5_CHCFG6      DMAMUX_5.CHCFG[6].R           /* Channel Configuration register */
#define DMAMUX_5_CHCFG7      DMAMUX_5.CHCFG[7].R           /* Channel Configuration register */
#define DMAMUX_5_CHCFG8      DMAMUX_5.CHCFG[8].R           /* Channel Configuration register */
#define DMAMUX_5_CHCFG9      DMAMUX_5.CHCFG[9].R           /* Channel Configuration register */
#define DMAMUX_5_CHCFG10     DMAMUX_5.CHCFG[10].R          /* Channel Configuration register */
#define DMAMUX_5_CHCFG11     DMAMUX_5.CHCFG[11].R          /* Channel Configuration register */
#define DMAMUX_5_CHCFG12     DMAMUX_5.CHCFG[12].R          /* Channel Configuration register */
#define DMAMUX_5_CHCFG13     DMAMUX_5.CHCFG[13].R          /* Channel Configuration register */
#define DMAMUX_5_CHCFG14     DMAMUX_5.CHCFG[14].R          /* Channel Configuration register */
#define DMAMUX_5_CHCFG15     DMAMUX_5.CHCFG[15].R          /* Channel Configuration register */

/* DMAMUX */
#define DMAMUX_6_CHCFG0      DMAMUX_6.CHCFG[0].R           /* Channel Configuration register */
#define DMAMUX_6_CHCFG1      DMAMUX_6.CHCFG[1].R           /* Channel Configuration register */
#define DMAMUX_6_CHCFG2      DMAMUX_6.CHCFG[2].R           /* Channel Configuration register */
#define DMAMUX_6_CHCFG3      DMAMUX_6.CHCFG[3].R           /* Channel Configuration register */
#define DMAMUX_6_CHCFG4      DMAMUX_6.CHCFG[4].R           /* Channel Configuration register */
#define DMAMUX_6_CHCFG5      DMAMUX_6.CHCFG[5].R           /* Channel Configuration register */
#define DMAMUX_6_CHCFG6      DMAMUX_6.CHCFG[6].R           /* Channel Configuration register */
#define DMAMUX_6_CHCFG7      DMAMUX_6.CHCFG[7].R           /* Channel Configuration register */
#define DMAMUX_6_CHCFG8      DMAMUX_6.CHCFG[8].R           /* Channel Configuration register */
#define DMAMUX_6_CHCFG9      DMAMUX_6.CHCFG[9].R           /* Channel Configuration register */
#define DMAMUX_6_CHCFG10     DMAMUX_6.CHCFG[10].R          /* Channel Configuration register */
#define DMAMUX_6_CHCFG11     DMAMUX_6.CHCFG[11].R          /* Channel Configuration register */
#define DMAMUX_6_CHCFG12     DMAMUX_6.CHCFG[12].R          /* Channel Configuration register */
#define DMAMUX_6_CHCFG13     DMAMUX_6.CHCFG[13].R          /* Channel Configuration register */
#define DMAMUX_6_CHCFG14     DMAMUX_6.CHCFG[14].R          /* Channel Configuration register */
#define DMAMUX_6_CHCFG15     DMAMUX_6.CHCFG[15].R          /* Channel Configuration register */

/* DMAMUX */
#define DMAMUX_7_CHCFG0      DMAMUX_7.CHCFG[0].R           /* Channel Configuration register */
#define DMAMUX_7_CHCFG1      DMAMUX_7.CHCFG[1].R           /* Channel Configuration register */
#define DMAMUX_7_CHCFG2      DMAMUX_7.CHCFG[2].R           /* Channel Configuration register */
#define DMAMUX_7_CHCFG3      DMAMUX_7.CHCFG[3].R           /* Channel Configuration register */
#define DMAMUX_7_CHCFG4      DMAMUX_7.CHCFG[4].R           /* Channel Configuration register */
#define DMAMUX_7_CHCFG5      DMAMUX_7.CHCFG[5].R           /* Channel Configuration register */
#define DMAMUX_7_CHCFG6      DMAMUX_7.CHCFG[6].R           /* Channel Configuration register */
#define DMAMUX_7_CHCFG7      DMAMUX_7.CHCFG[7].R           /* Channel Configuration register */
#define DMAMUX_7_CHCFG8      DMAMUX_7.CHCFG[8].R           /* Channel Configuration register */
#define DMAMUX_7_CHCFG9      DMAMUX_7.CHCFG[9].R           /* Channel Configuration register */
#define DMAMUX_7_CHCFG10     DMAMUX_7.CHCFG[10].R          /* Channel Configuration register */
#define DMAMUX_7_CHCFG11     DMAMUX_7.CHCFG[11].R          /* Channel Configuration register */
#define DMAMUX_7_CHCFG12     DMAMUX_7.CHCFG[12].R          /* Channel Configuration register */
#define DMAMUX_7_CHCFG13     DMAMUX_7.CHCFG[13].R          /* Channel Configuration register */
#define DMAMUX_7_CHCFG14     DMAMUX_7.CHCFG[14].R          /* Channel Configuration register */
#define DMAMUX_7_CHCFG15     DMAMUX_7.CHCFG[15].R          /* Channel Configuration register */

/* DMAMUX */
#define DMAMUX_8_CHCFG0      DMAMUX_8.CHCFG[0].R           /* Channel Configuration register */
#define DMAMUX_8_CHCFG1      DMAMUX_8.CHCFG[1].R           /* Channel Configuration register */
#define DMAMUX_8_CHCFG2      DMAMUX_8.CHCFG[2].R           /* Channel Configuration register */
#define DMAMUX_8_CHCFG3      DMAMUX_8.CHCFG[3].R           /* Channel Configuration register */
#define DMAMUX_8_CHCFG4      DMAMUX_8.CHCFG[4].R           /* Channel Configuration register */
#define DMAMUX_8_CHCFG5      DMAMUX_8.CHCFG[5].R           /* Channel Configuration register */
#define DMAMUX_8_CHCFG6      DMAMUX_8.CHCFG[6].R           /* Channel Configuration register */
#define DMAMUX_8_CHCFG7      DMAMUX_8.CHCFG[7].R           /* Channel Configuration register */
#define DMAMUX_8_CHCFG8      DMAMUX_8.CHCFG[8].R           /* Channel Configuration register */
#define DMAMUX_8_CHCFG9      DMAMUX_8.CHCFG[9].R           /* Channel Configuration register */
#define DMAMUX_8_CHCFG10     DMAMUX_8.CHCFG[10].R          /* Channel Configuration register */
#define DMAMUX_8_CHCFG11     DMAMUX_8.CHCFG[11].R          /* Channel Configuration register */
#define DMAMUX_8_CHCFG12     DMAMUX_8.CHCFG[12].R          /* Channel Configuration register */
#define DMAMUX_8_CHCFG13     DMAMUX_8.CHCFG[13].R          /* Channel Configuration register */
#define DMAMUX_8_CHCFG14     DMAMUX_8.CHCFG[14].R          /* Channel Configuration register */
#define DMAMUX_8_CHCFG15     DMAMUX_8.CHCFG[15].R          /* Channel Configuration register */

/* DMAMUX */
#define DMAMUX_9_CHCFG0      DMAMUX_9.CHCFG[0].R           /* Channel Configuration register */
#define DMAMUX_9_CHCFG1      DMAMUX_9.CHCFG[1].R           /* Channel Configuration register */
#define DMAMUX_9_CHCFG2      DMAMUX_9.CHCFG[2].R           /* Channel Configuration register */
#define DMAMUX_9_CHCFG3      DMAMUX_9.CHCFG[3].R           /* Channel Configuration register */
#define DMAMUX_9_CHCFG4      DMAMUX_9.CHCFG[4].R           /* Channel Configuration register */
#define DMAMUX_9_CHCFG5      DMAMUX_9.CHCFG[5].R           /* Channel Configuration register */
#define DMAMUX_9_CHCFG6      DMAMUX_9.CHCFG[6].R           /* Channel Configuration register */
#define DMAMUX_9_CHCFG7      DMAMUX_9.CHCFG[7].R           /* Channel Configuration register */
#define DMAMUX_9_CHCFG8      DMAMUX_9.CHCFG[8].R           /* Channel Configuration register */
#define DMAMUX_9_CHCFG9      DMAMUX_9.CHCFG[9].R           /* Channel Configuration register */
#define DMAMUX_9_CHCFG10     DMAMUX_9.CHCFG[10].R          /* Channel Configuration register */
#define DMAMUX_9_CHCFG11     DMAMUX_9.CHCFG[11].R          /* Channel Configuration register */
#define DMAMUX_9_CHCFG12     DMAMUX_9.CHCFG[12].R          /* Channel Configuration register */
#define DMAMUX_9_CHCFG13     DMAMUX_9.CHCFG[13].R          /* Channel Configuration register */
#define DMAMUX_9_CHCFG14     DMAMUX_9.CHCFG[14].R          /* Channel Configuration register */
#define DMAMUX_9_CHCFG15     DMAMUX_9.CHCFG[15].R          /* Channel Configuration register */

/* DSPI */
#define DSPI_0_MCR           DSPI_0.MCR.R                  /* DSPI Module Configuration Register */
#define DSPI_0_TCR           DSPI_0.TCR.R                  /* DSPI Transfer Count Register */
#define DSPI_0_CTAR0         DSPI_0.MODE.CTAR[0].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_0_CTAR1         DSPI_0.MODE.CTAR[1].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_0_CTAR2         DSPI_0.MODE.CTAR[2].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_0_CTAR3         DSPI_0.MODE.CTAR[3].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_0_CTAR4         DSPI_0.MODE.CTAR[4].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_0_CTAR5         DSPI_0.MODE.CTAR[5].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_0_CTAR6         DSPI_0.MODE.CTAR[6].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_0_CTAR7         DSPI_0.MODE.CTAR[7].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_0_CTAR_SLAVE0   DSPI_0.MODE.CTAR_SLAVE[0].R   /* DSPI Clock and Transfer Attributes Register (In Slave Mode) */
#define DSPI_0_CTAR_SLAVE1   DSPI_0.MODE.CTAR_SLAVE[1].R   /* DSPI Clock and Transfer Attributes Register (In Slave Mode) */
#define DSPI_0_SR            DSPI_0.SR.R                   /* DSPI Status Register */
#define DSPI_0_RSER          DSPI_0.RSER.R                 /* DSPI DMA/Interrupt Request Select and Enable Register */
#define DSPI_0_PUSHR         DSPI_0.PUSHR.PUSHR.R          /* DSPI PUSH FIFO Register In Master Mode */
#define DSPI_0_PUSHR_SLAVE   DSPI_0.PUSHR.PUSHR_SLAVE.R    /* DSPI PUSH FIFO Register In Slave Mode */
#define DSPI_0_POPR          DSPI_0.POPR.R                 /* DSPI POP FIFO Register */
#define DSPI_0_TXFR0         DSPI_0.TXFR[0].R              /* DSPI Transmit FIFO Registers */
#define DSPI_0_TXFR1         DSPI_0.TXFR[1].R              /* DSPI Transmit FIFO Registers */
#define DSPI_0_TXFR2         DSPI_0.TXFR[2].R              /* DSPI Transmit FIFO Registers */
#define DSPI_0_TXFR3         DSPI_0.TXFR[3].R              /* DSPI Transmit FIFO Registers */
#define DSPI_0_RXFR0         DSPI_0.RXFR[0].R              /* DSPI Receive FIFO Registers */
#define DSPI_0_RXFR1         DSPI_0.RXFR[1].R              /* DSPI Receive FIFO Registers */
#define DSPI_0_RXFR2         DSPI_0.RXFR[2].R              /* DSPI Receive FIFO Registers */
#define DSPI_0_RXFR3         DSPI_0.RXFR[3].R              /* DSPI Receive FIFO Registers */
#define DSPI_0_DSICR0        DSPI_0.DSICR0.R               /* DSPI DSI Configuration Register 0 */
#define DSPI_0_SDR0          DSPI_0.SDR0.R                 /* DSPI DSI Serialization Data Register 0 */
#define DSPI_0_ASDR0         DSPI_0.ASDR0.R                /* DSPI DSI Alternate Serialization Data Register 0 */
#define DSPI_0_COMPR0        DSPI_0.COMPR0.R               /* DSPI DSI Transmit Comparison Register 0 */
#define DSPI_0_DDR0          DSPI_0.DDR0.R                 /* DSPI DSI Deserialization Data Register 0 */
#define DSPI_0_DSICR1        DSPI_0.DSICR1.R               /* DSPI DSI Configuration Register 1 */
#define DSPI_0_SSR0          DSPI_0.SSR0.R                 /* DSPI DSI Serialization Source Select Register 0 */
#define DSPI_0_PISR0         DSPI_0.PISR0.R                /* DSPI DSI Parallel Input Select Register 0 */
#define DSPI_0_PISR1         DSPI_0.PISR1.R                /* DSPI DSI Parallel Input Select Register 1 */
#define DSPI_0_PISR2         DSPI_0.PISR2.R                /* DSPI DSI Parallel Input Select Register 2 */
#define DSPI_0_PISR3         DSPI_0.PISR3.R                /* DSPI DSI Parallel Input Select Register 3 */
#define DSPI_0_DIMR0         DSPI_0.DIMR0.R                /* DSPI DSI Deserialized Data Interrupt Mask Register 0 */
#define DSPI_0_DPIR0         DSPI_0.DPIR0.R                /* DSPI DSI Deserialized Data Polarity Interrupt Register 0 */
#define DSPI_0_SDR1          DSPI_0.SDR1.R                 /* DSPI DSI Serialization Data Register 1 */
#define DSPI_0_ASDR1         DSPI_0.ASDR1.R                /* DSPI DSI Alternate Serialization Data Register 1 */
#define DSPI_0_COMPR1        DSPI_0.COMPR1.R               /* DSPI DSI Transmit Comparison Register 1 */
#define DSPI_0_DDR1          DSPI_0.DDR1.R                 /* DSPI DSI Deserialization Data Register 1 */
#define DSPI_0_SSR1          DSPI_0.SSR1.R                 /* DSPI DSI Serialization Source Select Register 1 */
#define DSPI_0_PISR4         DSPI_0.PISR4.R                /* DSPI DSI Parallel Input Select Register 4 */
#define DSPI_0_PISR5         DSPI_0.PISR5.R                /* DSPI DSI Parallel Input Select Register 5 */
#define DSPI_0_PISR6         DSPI_0.PISR6.R                /* DSPI DSI Parallel Input Select Register 6 */
#define DSPI_0_PISR7         DSPI_0.PISR7.R                /* DSPI DSI Parallel Input Select Register 7 */
#define DSPI_0_DIMR1         DSPI_0.DIMR1.R                /* DSPI DSI Deserialized Data Interrupt Mask Register 1 */
#define DSPI_0_DPIR1         DSPI_0.DPIR1.R                /* DSPI DSI Deserialized Data Polarity Interrupt Register 1 */
#define DSPI_0_CTARE0        DSPI_0.CTARE[0].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_0_CTARE1        DSPI_0.CTARE[1].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_0_CTARE2        DSPI_0.CTARE[2].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_0_CTARE3        DSPI_0.CTARE[3].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_0_CTARE4        DSPI_0.CTARE[4].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_0_CTARE5        DSPI_0.CTARE[5].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_0_CTARE6        DSPI_0.CTARE[6].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_0_CTARE7        DSPI_0.CTARE[7].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_0_SREX          DSPI_0.SREX.R                 /* DSPI Status Register Extended */

/* DSPI */
#define DSPI_1_MCR           DSPI_1.MCR.R                  /* DSPI Module Configuration Register */
#define DSPI_1_TCR           DSPI_1.TCR.R                  /* DSPI Transfer Count Register */
#define DSPI_1_CTAR0         DSPI_1.MODE.CTAR[0].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_1_CTAR1         DSPI_1.MODE.CTAR[1].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_1_CTAR2         DSPI_1.MODE.CTAR[2].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_1_CTAR3         DSPI_1.MODE.CTAR[3].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_1_CTAR4         DSPI_1.MODE.CTAR[4].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_1_CTAR5         DSPI_1.MODE.CTAR[5].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_1_CTAR6         DSPI_1.MODE.CTAR[6].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_1_CTAR7         DSPI_1.MODE.CTAR[7].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_1_CTAR_SLAVE0   DSPI_1.MODE.CTAR_SLAVE[0].R   /* DSPI Clock and Transfer Attributes Register (In Slave Mode) */
#define DSPI_1_CTAR_SLAVE1   DSPI_1.MODE.CTAR_SLAVE[1].R   /* DSPI Clock and Transfer Attributes Register (In Slave Mode) */
#define DSPI_1_SR            DSPI_1.SR.R                   /* DSPI Status Register */
#define DSPI_1_RSER          DSPI_1.RSER.R                 /* DSPI DMA/Interrupt Request Select and Enable Register */
#define DSPI_1_PUSHR         DSPI_1.PUSHR.PUSHR.R          /* DSPI PUSH FIFO Register In Master Mode */
#define DSPI_1_PUSHR_SLAVE   DSPI_1.PUSHR.PUSHR_SLAVE.R    /* DSPI PUSH FIFO Register In Slave Mode */
#define DSPI_1_POPR          DSPI_1.POPR.R                 /* DSPI POP FIFO Register */
#define DSPI_1_TXFR0         DSPI_1.TXFR[0].R              /* DSPI Transmit FIFO Registers */
#define DSPI_1_TXFR1         DSPI_1.TXFR[1].R              /* DSPI Transmit FIFO Registers */
#define DSPI_1_TXFR2         DSPI_1.TXFR[2].R              /* DSPI Transmit FIFO Registers */
#define DSPI_1_TXFR3         DSPI_1.TXFR[3].R              /* DSPI Transmit FIFO Registers */
#define DSPI_1_RXFR0         DSPI_1.RXFR[0].R              /* DSPI Receive FIFO Registers */
#define DSPI_1_RXFR1         DSPI_1.RXFR[1].R              /* DSPI Receive FIFO Registers */
#define DSPI_1_RXFR2         DSPI_1.RXFR[2].R              /* DSPI Receive FIFO Registers */
#define DSPI_1_RXFR3         DSPI_1.RXFR[3].R              /* DSPI Receive FIFO Registers */
#define DSPI_1_DSICR0        DSPI_1.DSICR0.R               /* DSPI DSI Configuration Register 0 */
#define DSPI_1_SDR0          DSPI_1.SDR0.R                 /* DSPI DSI Serialization Data Register 0 */
#define DSPI_1_ASDR0         DSPI_1.ASDR0.R                /* DSPI DSI Alternate Serialization Data Register 0 */
#define DSPI_1_COMPR0        DSPI_1.COMPR0.R               /* DSPI DSI Transmit Comparison Register 0 */
#define DSPI_1_DDR0          DSPI_1.DDR0.R                 /* DSPI DSI Deserialization Data Register 0 */
#define DSPI_1_DSICR1        DSPI_1.DSICR1.R               /* DSPI DSI Configuration Register 1 */
#define DSPI_1_SSR0          DSPI_1.SSR0.R                 /* DSPI DSI Serialization Source Select Register 0 */
#define DSPI_1_PISR0         DSPI_1.PISR0.R                /* DSPI DSI Parallel Input Select Register 0 */
#define DSPI_1_PISR1         DSPI_1.PISR1.R                /* DSPI DSI Parallel Input Select Register 1 */
#define DSPI_1_PISR2         DSPI_1.PISR2.R                /* DSPI DSI Parallel Input Select Register 2 */
#define DSPI_1_PISR3         DSPI_1.PISR3.R                /* DSPI DSI Parallel Input Select Register 3 */
#define DSPI_1_DIMR0         DSPI_1.DIMR0.R                /* DSPI DSI Deserialized Data Interrupt Mask Register 0 */
#define DSPI_1_DPIR0         DSPI_1.DPIR0.R                /* DSPI DSI Deserialized Data Polarity Interrupt Register 0 */
#define DSPI_1_SDR1          DSPI_1.SDR1.R                 /* DSPI DSI Serialization Data Register 1 */
#define DSPI_1_ASDR1         DSPI_1.ASDR1.R                /* DSPI DSI Alternate Serialization Data Register 1 */
#define DSPI_1_COMPR1        DSPI_1.COMPR1.R               /* DSPI DSI Transmit Comparison Register 1 */
#define DSPI_1_DDR1          DSPI_1.DDR1.R                 /* DSPI DSI Deserialization Data Register 1 */
#define DSPI_1_SSR1          DSPI_1.SSR1.R                 /* DSPI DSI Serialization Source Select Register 1 */
#define DSPI_1_PISR4         DSPI_1.PISR4.R                /* DSPI DSI Parallel Input Select Register 4 */
#define DSPI_1_PISR5         DSPI_1.PISR5.R                /* DSPI DSI Parallel Input Select Register 5 */
#define DSPI_1_PISR6         DSPI_1.PISR6.R                /* DSPI DSI Parallel Input Select Register 6 */
#define DSPI_1_PISR7         DSPI_1.PISR7.R                /* DSPI DSI Parallel Input Select Register 7 */
#define DSPI_1_DIMR1         DSPI_1.DIMR1.R                /* DSPI DSI Deserialized Data Interrupt Mask Register 1 */
#define DSPI_1_DPIR1         DSPI_1.DPIR1.R                /* DSPI DSI Deserialized Data Polarity Interrupt Register 1 */
#define DSPI_1_CTARE0        DSPI_1.CTARE[0].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_1_CTARE1        DSPI_1.CTARE[1].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_1_CTARE2        DSPI_1.CTARE[2].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_1_CTARE3        DSPI_1.CTARE[3].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_1_CTARE4        DSPI_1.CTARE[4].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_1_CTARE5        DSPI_1.CTARE[5].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_1_CTARE6        DSPI_1.CTARE[6].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_1_CTARE7        DSPI_1.CTARE[7].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_1_SREX          DSPI_1.SREX.R                 /* DSPI Status Register Extended */

/* DSPI */
#define DSPI_12_MCR          DSPI_12.MCR.R                 /* DSPI Module Configuration Register */
#define DSPI_12_TCR          DSPI_12.TCR.R                 /* DSPI Transfer Count Register */
#define DSPI_12_CTAR0        DSPI_12.MODE.CTAR[0].R        /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_12_CTAR1        DSPI_12.MODE.CTAR[1].R        /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_12_CTAR2        DSPI_12.MODE.CTAR[2].R        /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_12_CTAR3        DSPI_12.MODE.CTAR[3].R        /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_12_CTAR4        DSPI_12.MODE.CTAR[4].R        /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_12_CTAR5        DSPI_12.MODE.CTAR[5].R        /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_12_CTAR6        DSPI_12.MODE.CTAR[6].R        /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_12_CTAR7        DSPI_12.MODE.CTAR[7].R        /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_12_CTAR_SLAVE0  DSPI_12.MODE.CTAR_SLAVE[0].R  /* DSPI Clock and Transfer Attributes Register (In Slave Mode) */
#define DSPI_12_CTAR_SLAVE1  DSPI_12.MODE.CTAR_SLAVE[1].R  /* DSPI Clock and Transfer Attributes Register (In Slave Mode) */
#define DSPI_12_SR           DSPI_12.SR.R                  /* DSPI Status Register */
#define DSPI_12_RSER         DSPI_12.RSER.R                /* DSPI DMA/Interrupt Request Select and Enable Register */
#define DSPI_12_PUSHR        DSPI_12.PUSHR.PUSHR.R         /* DSPI PUSH FIFO Register In Master Mode */
#define DSPI_12_PUSHR_SLAVE  DSPI_12.PUSHR.PUSHR_SLAVE.R   /* DSPI PUSH FIFO Register In Slave Mode */
#define DSPI_12_POPR         DSPI_12.POPR.R                /* DSPI POP FIFO Register */
#define DSPI_12_TXFR0        DSPI_12.TXFR[0].R             /* DSPI Transmit FIFO Registers */
#define DSPI_12_TXFR1        DSPI_12.TXFR[1].R             /* DSPI Transmit FIFO Registers */
#define DSPI_12_TXFR2        DSPI_12.TXFR[2].R             /* DSPI Transmit FIFO Registers */
#define DSPI_12_TXFR3        DSPI_12.TXFR[3].R             /* DSPI Transmit FIFO Registers */
#define DSPI_12_RXFR0        DSPI_12.RXFR[0].R             /* DSPI Receive FIFO Registers */
#define DSPI_12_RXFR1        DSPI_12.RXFR[1].R             /* DSPI Receive FIFO Registers */
#define DSPI_12_RXFR2        DSPI_12.RXFR[2].R             /* DSPI Receive FIFO Registers */
#define DSPI_12_RXFR3        DSPI_12.RXFR[3].R             /* DSPI Receive FIFO Registers */
#define DSPI_12_DSICR0       DSPI_12.DSICR0.R              /* DSPI DSI Configuration Register 0 */
#define DSPI_12_SDR0         DSPI_12.SDR0.R                /* DSPI DSI Serialization Data Register 0 */
#define DSPI_12_ASDR0        DSPI_12.ASDR0.R               /* DSPI DSI Alternate Serialization Data Register 0 */
#define DSPI_12_COMPR0       DSPI_12.COMPR0.R              /* DSPI DSI Transmit Comparison Register 0 */
#define DSPI_12_DDR0         DSPI_12.DDR0.R                /* DSPI DSI Deserialization Data Register 0 */
#define DSPI_12_DSICR1       DSPI_12.DSICR1.R              /* DSPI DSI Configuration Register 1 */
#define DSPI_12_SSR0         DSPI_12.SSR0.R                /* DSPI DSI Serialization Source Select Register 0 */
#define DSPI_12_PISR0        DSPI_12.PISR0.R               /* DSPI DSI Parallel Input Select Register 0 */
#define DSPI_12_PISR1        DSPI_12.PISR1.R               /* DSPI DSI Parallel Input Select Register 1 */
#define DSPI_12_PISR2        DSPI_12.PISR2.R               /* DSPI DSI Parallel Input Select Register 2 */
#define DSPI_12_PISR3        DSPI_12.PISR3.R               /* DSPI DSI Parallel Input Select Register 3 */
#define DSPI_12_DIMR0        DSPI_12.DIMR0.R               /* DSPI DSI Deserialized Data Interrupt Mask Register 0 */
#define DSPI_12_DPIR0        DSPI_12.DPIR0.R               /* DSPI DSI Deserialized Data Polarity Interrupt Register 0 */
#define DSPI_12_SDR1         DSPI_12.SDR1.R                /* DSPI DSI Serialization Data Register 1 */
#define DSPI_12_ASDR1        DSPI_12.ASDR1.R               /* DSPI DSI Alternate Serialization Data Register 1 */
#define DSPI_12_COMPR1       DSPI_12.COMPR1.R              /* DSPI DSI Transmit Comparison Register 1 */
#define DSPI_12_DDR1         DSPI_12.DDR1.R                /* DSPI DSI Deserialization Data Register 1 */
#define DSPI_12_SSR1         DSPI_12.SSR1.R                /* DSPI DSI Serialization Source Select Register 1 */
#define DSPI_12_PISR4        DSPI_12.PISR4.R               /* DSPI DSI Parallel Input Select Register 4 */
#define DSPI_12_PISR5        DSPI_12.PISR5.R               /* DSPI DSI Parallel Input Select Register 5 */
#define DSPI_12_PISR6        DSPI_12.PISR6.R               /* DSPI DSI Parallel Input Select Register 6 */
#define DSPI_12_PISR7        DSPI_12.PISR7.R               /* DSPI DSI Parallel Input Select Register 7 */
#define DSPI_12_DIMR1        DSPI_12.DIMR1.R               /* DSPI DSI Deserialized Data Interrupt Mask Register 1 */
#define DSPI_12_DPIR1        DSPI_12.DPIR1.R               /* DSPI DSI Deserialized Data Polarity Interrupt Register 1 */
#define DSPI_12_CTARE0       DSPI_12.CTARE[0].R            /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_12_CTARE1       DSPI_12.CTARE[1].R            /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_12_CTARE2       DSPI_12.CTARE[2].R            /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_12_CTARE3       DSPI_12.CTARE[3].R            /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_12_CTARE4       DSPI_12.CTARE[4].R            /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_12_CTARE5       DSPI_12.CTARE[5].R            /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_12_CTARE6       DSPI_12.CTARE[6].R            /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_12_CTARE7       DSPI_12.CTARE[7].R            /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_12_SREX         DSPI_12.SREX.R                /* DSPI Status Register Extended */

/* DSPI */
#define DSPI_2_MCR           DSPI_2.MCR.R                  /* DSPI Module Configuration Register */
#define DSPI_2_TCR           DSPI_2.TCR.R                  /* DSPI Transfer Count Register */
#define DSPI_2_CTAR0         DSPI_2.MODE.CTAR[0].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_2_CTAR1         DSPI_2.MODE.CTAR[1].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_2_CTAR2         DSPI_2.MODE.CTAR[2].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_2_CTAR3         DSPI_2.MODE.CTAR[3].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_2_CTAR4         DSPI_2.MODE.CTAR[4].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_2_CTAR5         DSPI_2.MODE.CTAR[5].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_2_CTAR6         DSPI_2.MODE.CTAR[6].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_2_CTAR7         DSPI_2.MODE.CTAR[7].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_2_CTAR_SLAVE0   DSPI_2.MODE.CTAR_SLAVE[0].R   /* DSPI Clock and Transfer Attributes Register (In Slave Mode) */
#define DSPI_2_CTAR_SLAVE1   DSPI_2.MODE.CTAR_SLAVE[1].R   /* DSPI Clock and Transfer Attributes Register (In Slave Mode) */
#define DSPI_2_SR            DSPI_2.SR.R                   /* DSPI Status Register */
#define DSPI_2_RSER          DSPI_2.RSER.R                 /* DSPI DMA/Interrupt Request Select and Enable Register */
#define DSPI_2_PUSHR         DSPI_2.PUSHR.PUSHR.R          /* DSPI PUSH FIFO Register In Master Mode */
#define DSPI_2_PUSHR_SLAVE   DSPI_2.PUSHR.PUSHR_SLAVE.R    /* DSPI PUSH FIFO Register In Slave Mode */
#define DSPI_2_POPR          DSPI_2.POPR.R                 /* DSPI POP FIFO Register */
#define DSPI_2_TXFR0         DSPI_2.TXFR[0].R              /* DSPI Transmit FIFO Registers */
#define DSPI_2_TXFR1         DSPI_2.TXFR[1].R              /* DSPI Transmit FIFO Registers */
#define DSPI_2_TXFR2         DSPI_2.TXFR[2].R              /* DSPI Transmit FIFO Registers */
#define DSPI_2_TXFR3         DSPI_2.TXFR[3].R              /* DSPI Transmit FIFO Registers */
#define DSPI_2_RXFR0         DSPI_2.RXFR[0].R              /* DSPI Receive FIFO Registers */
#define DSPI_2_RXFR1         DSPI_2.RXFR[1].R              /* DSPI Receive FIFO Registers */
#define DSPI_2_RXFR2         DSPI_2.RXFR[2].R              /* DSPI Receive FIFO Registers */
#define DSPI_2_RXFR3         DSPI_2.RXFR[3].R              /* DSPI Receive FIFO Registers */
#define DSPI_2_DSICR0        DSPI_2.DSICR0.R               /* DSPI DSI Configuration Register 0 */
#define DSPI_2_SDR0          DSPI_2.SDR0.R                 /* DSPI DSI Serialization Data Register 0 */
#define DSPI_2_ASDR0         DSPI_2.ASDR0.R                /* DSPI DSI Alternate Serialization Data Register 0 */
#define DSPI_2_COMPR0        DSPI_2.COMPR0.R               /* DSPI DSI Transmit Comparison Register 0 */
#define DSPI_2_DDR0          DSPI_2.DDR0.R                 /* DSPI DSI Deserialization Data Register 0 */
#define DSPI_2_DSICR1        DSPI_2.DSICR1.R               /* DSPI DSI Configuration Register 1 */
#define DSPI_2_SSR0          DSPI_2.SSR0.R                 /* DSPI DSI Serialization Source Select Register 0 */
#define DSPI_2_PISR0         DSPI_2.PISR0.R                /* DSPI DSI Parallel Input Select Register 0 */
#define DSPI_2_PISR1         DSPI_2.PISR1.R                /* DSPI DSI Parallel Input Select Register 1 */
#define DSPI_2_PISR2         DSPI_2.PISR2.R                /* DSPI DSI Parallel Input Select Register 2 */
#define DSPI_2_PISR3         DSPI_2.PISR3.R                /* DSPI DSI Parallel Input Select Register 3 */
#define DSPI_2_DIMR0         DSPI_2.DIMR0.R                /* DSPI DSI Deserialized Data Interrupt Mask Register 0 */
#define DSPI_2_DPIR0         DSPI_2.DPIR0.R                /* DSPI DSI Deserialized Data Polarity Interrupt Register 0 */
#define DSPI_2_SDR1          DSPI_2.SDR1.R                 /* DSPI DSI Serialization Data Register 1 */
#define DSPI_2_ASDR1         DSPI_2.ASDR1.R                /* DSPI DSI Alternate Serialization Data Register 1 */
#define DSPI_2_COMPR1        DSPI_2.COMPR1.R               /* DSPI DSI Transmit Comparison Register 1 */
#define DSPI_2_DDR1          DSPI_2.DDR1.R                 /* DSPI DSI Deserialization Data Register 1 */
#define DSPI_2_SSR1          DSPI_2.SSR1.R                 /* DSPI DSI Serialization Source Select Register 1 */
#define DSPI_2_PISR4         DSPI_2.PISR4.R                /* DSPI DSI Parallel Input Select Register 4 */
#define DSPI_2_PISR5         DSPI_2.PISR5.R                /* DSPI DSI Parallel Input Select Register 5 */
#define DSPI_2_PISR6         DSPI_2.PISR6.R                /* DSPI DSI Parallel Input Select Register 6 */
#define DSPI_2_PISR7         DSPI_2.PISR7.R                /* DSPI DSI Parallel Input Select Register 7 */
#define DSPI_2_DIMR1         DSPI_2.DIMR1.R                /* DSPI DSI Deserialized Data Interrupt Mask Register 1 */
#define DSPI_2_DPIR1         DSPI_2.DPIR1.R                /* DSPI DSI Deserialized Data Polarity Interrupt Register 1 */
#define DSPI_2_CTARE0        DSPI_2.CTARE[0].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_2_CTARE1        DSPI_2.CTARE[1].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_2_CTARE2        DSPI_2.CTARE[2].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_2_CTARE3        DSPI_2.CTARE[3].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_2_CTARE4        DSPI_2.CTARE[4].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_2_CTARE5        DSPI_2.CTARE[5].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_2_CTARE6        DSPI_2.CTARE[6].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_2_CTARE7        DSPI_2.CTARE[7].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_2_SREX          DSPI_2.SREX.R                 /* DSPI Status Register Extended */

/* DSPI */
#define DSPI_3_MCR           DSPI_3.MCR.R                  /* DSPI Module Configuration Register */
#define DSPI_3_TCR           DSPI_3.TCR.R                  /* DSPI Transfer Count Register */
#define DSPI_3_CTAR0         DSPI_3.MODE.CTAR[0].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_3_CTAR1         DSPI_3.MODE.CTAR[1].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_3_CTAR2         DSPI_3.MODE.CTAR[2].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_3_CTAR3         DSPI_3.MODE.CTAR[3].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_3_CTAR4         DSPI_3.MODE.CTAR[4].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_3_CTAR5         DSPI_3.MODE.CTAR[5].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_3_CTAR6         DSPI_3.MODE.CTAR[6].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_3_CTAR7         DSPI_3.MODE.CTAR[7].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_3_CTAR_SLAVE0   DSPI_3.MODE.CTAR_SLAVE[0].R   /* DSPI Clock and Transfer Attributes Register (In Slave Mode) */
#define DSPI_3_CTAR_SLAVE1   DSPI_3.MODE.CTAR_SLAVE[1].R   /* DSPI Clock and Transfer Attributes Register (In Slave Mode) */
#define DSPI_3_SR            DSPI_3.SR.R                   /* DSPI Status Register */
#define DSPI_3_RSER          DSPI_3.RSER.R                 /* DSPI DMA/Interrupt Request Select and Enable Register */
#define DSPI_3_PUSHR         DSPI_3.PUSHR.PUSHR.R          /* DSPI PUSH FIFO Register In Master Mode */
#define DSPI_3_PUSHR_SLAVE   DSPI_3.PUSHR.PUSHR_SLAVE.R    /* DSPI PUSH FIFO Register In Slave Mode */
#define DSPI_3_POPR          DSPI_3.POPR.R                 /* DSPI POP FIFO Register */
#define DSPI_3_TXFR0         DSPI_3.TXFR[0].R              /* DSPI Transmit FIFO Registers */
#define DSPI_3_TXFR1         DSPI_3.TXFR[1].R              /* DSPI Transmit FIFO Registers */
#define DSPI_3_TXFR2         DSPI_3.TXFR[2].R              /* DSPI Transmit FIFO Registers */
#define DSPI_3_TXFR3         DSPI_3.TXFR[3].R              /* DSPI Transmit FIFO Registers */
#define DSPI_3_RXFR0         DSPI_3.RXFR[0].R              /* DSPI Receive FIFO Registers */
#define DSPI_3_RXFR1         DSPI_3.RXFR[1].R              /* DSPI Receive FIFO Registers */
#define DSPI_3_RXFR2         DSPI_3.RXFR[2].R              /* DSPI Receive FIFO Registers */
#define DSPI_3_RXFR3         DSPI_3.RXFR[3].R              /* DSPI Receive FIFO Registers */
#define DSPI_3_DSICR0        DSPI_3.DSICR0.R               /* DSPI DSI Configuration Register 0 */
#define DSPI_3_SDR0          DSPI_3.SDR0.R                 /* DSPI DSI Serialization Data Register 0 */
#define DSPI_3_ASDR0         DSPI_3.ASDR0.R                /* DSPI DSI Alternate Serialization Data Register 0 */
#define DSPI_3_COMPR0        DSPI_3.COMPR0.R               /* DSPI DSI Transmit Comparison Register 0 */
#define DSPI_3_DDR0          DSPI_3.DDR0.R                 /* DSPI DSI Deserialization Data Register 0 */
#define DSPI_3_DSICR1        DSPI_3.DSICR1.R               /* DSPI DSI Configuration Register 1 */
#define DSPI_3_SSR0          DSPI_3.SSR0.R                 /* DSPI DSI Serialization Source Select Register 0 */
#define DSPI_3_PISR0         DSPI_3.PISR0.R                /* DSPI DSI Parallel Input Select Register 0 */
#define DSPI_3_PISR1         DSPI_3.PISR1.R                /* DSPI DSI Parallel Input Select Register 1 */
#define DSPI_3_PISR2         DSPI_3.PISR2.R                /* DSPI DSI Parallel Input Select Register 2 */
#define DSPI_3_PISR3         DSPI_3.PISR3.R                /* DSPI DSI Parallel Input Select Register 3 */
#define DSPI_3_DIMR0         DSPI_3.DIMR0.R                /* DSPI DSI Deserialized Data Interrupt Mask Register 0 */
#define DSPI_3_DPIR0         DSPI_3.DPIR0.R                /* DSPI DSI Deserialized Data Polarity Interrupt Register 0 */
#define DSPI_3_SDR1          DSPI_3.SDR1.R                 /* DSPI DSI Serialization Data Register 1 */
#define DSPI_3_ASDR1         DSPI_3.ASDR1.R                /* DSPI DSI Alternate Serialization Data Register 1 */
#define DSPI_3_COMPR1        DSPI_3.COMPR1.R               /* DSPI DSI Transmit Comparison Register 1 */
#define DSPI_3_DDR1          DSPI_3.DDR1.R                 /* DSPI DSI Deserialization Data Register 1 */
#define DSPI_3_SSR1          DSPI_3.SSR1.R                 /* DSPI DSI Serialization Source Select Register 1 */
#define DSPI_3_PISR4         DSPI_3.PISR4.R                /* DSPI DSI Parallel Input Select Register 4 */
#define DSPI_3_PISR5         DSPI_3.PISR5.R                /* DSPI DSI Parallel Input Select Register 5 */
#define DSPI_3_PISR6         DSPI_3.PISR6.R                /* DSPI DSI Parallel Input Select Register 6 */
#define DSPI_3_PISR7         DSPI_3.PISR7.R                /* DSPI DSI Parallel Input Select Register 7 */
#define DSPI_3_DIMR1         DSPI_3.DIMR1.R                /* DSPI DSI Deserialized Data Interrupt Mask Register 1 */
#define DSPI_3_DPIR1         DSPI_3.DPIR1.R                /* DSPI DSI Deserialized Data Polarity Interrupt Register 1 */
#define DSPI_3_CTARE0        DSPI_3.CTARE[0].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_3_CTARE1        DSPI_3.CTARE[1].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_3_CTARE2        DSPI_3.CTARE[2].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_3_CTARE3        DSPI_3.CTARE[3].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_3_CTARE4        DSPI_3.CTARE[4].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_3_CTARE5        DSPI_3.CTARE[5].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_3_CTARE6        DSPI_3.CTARE[6].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_3_CTARE7        DSPI_3.CTARE[7].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_3_SREX          DSPI_3.SREX.R                 /* DSPI Status Register Extended */

/* DSPI */
#define DSPI_4_MCR           DSPI_4.MCR.R                  /* DSPI Module Configuration Register */
#define DSPI_4_TCR           DSPI_4.TCR.R                  /* DSPI Transfer Count Register */
#define DSPI_4_CTAR0         DSPI_4.MODE.CTAR[0].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_4_CTAR1         DSPI_4.MODE.CTAR[1].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_4_CTAR2         DSPI_4.MODE.CTAR[2].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_4_CTAR3         DSPI_4.MODE.CTAR[3].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_4_CTAR4         DSPI_4.MODE.CTAR[4].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_4_CTAR5         DSPI_4.MODE.CTAR[5].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_4_CTAR6         DSPI_4.MODE.CTAR[6].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_4_CTAR7         DSPI_4.MODE.CTAR[7].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_4_CTAR_SLAVE0   DSPI_4.MODE.CTAR_SLAVE[0].R   /* DSPI Clock and Transfer Attributes Register (In Slave Mode) */
#define DSPI_4_CTAR_SLAVE1   DSPI_4.MODE.CTAR_SLAVE[1].R   /* DSPI Clock and Transfer Attributes Register (In Slave Mode) */
#define DSPI_4_SR            DSPI_4.SR.R                   /* DSPI Status Register */
#define DSPI_4_RSER          DSPI_4.RSER.R                 /* DSPI DMA/Interrupt Request Select and Enable Register */
#define DSPI_4_PUSHR         DSPI_4.PUSHR.PUSHR.R          /* DSPI PUSH FIFO Register In Master Mode */
#define DSPI_4_PUSHR_SLAVE   DSPI_4.PUSHR.PUSHR_SLAVE.R    /* DSPI PUSH FIFO Register In Slave Mode */
#define DSPI_4_POPR          DSPI_4.POPR.R                 /* DSPI POP FIFO Register */
#define DSPI_4_TXFR0         DSPI_4.TXFR[0].R              /* DSPI Transmit FIFO Registers */
#define DSPI_4_TXFR1         DSPI_4.TXFR[1].R              /* DSPI Transmit FIFO Registers */
#define DSPI_4_TXFR2         DSPI_4.TXFR[2].R              /* DSPI Transmit FIFO Registers */
#define DSPI_4_TXFR3         DSPI_4.TXFR[3].R              /* DSPI Transmit FIFO Registers */
#define DSPI_4_RXFR0         DSPI_4.RXFR[0].R              /* DSPI Receive FIFO Registers */
#define DSPI_4_RXFR1         DSPI_4.RXFR[1].R              /* DSPI Receive FIFO Registers */
#define DSPI_4_RXFR2         DSPI_4.RXFR[2].R              /* DSPI Receive FIFO Registers */
#define DSPI_4_RXFR3         DSPI_4.RXFR[3].R              /* DSPI Receive FIFO Registers */
#define DSPI_4_DSICR0        DSPI_4.DSICR0.R               /* DSPI DSI Configuration Register 0 */
#define DSPI_4_SDR0          DSPI_4.SDR0.R                 /* DSPI DSI Serialization Data Register 0 */
#define DSPI_4_ASDR0         DSPI_4.ASDR0.R                /* DSPI DSI Alternate Serialization Data Register 0 */
#define DSPI_4_COMPR0        DSPI_4.COMPR0.R               /* DSPI DSI Transmit Comparison Register 0 */
#define DSPI_4_DDR0          DSPI_4.DDR0.R                 /* DSPI DSI Deserialization Data Register 0 */
#define DSPI_4_DSICR1        DSPI_4.DSICR1.R               /* DSPI DSI Configuration Register 1 */
#define DSPI_4_SSR0          DSPI_4.SSR0.R                 /* DSPI DSI Serialization Source Select Register 0 */
#define DSPI_4_PISR0         DSPI_4.PISR0.R                /* DSPI DSI Parallel Input Select Register 0 */
#define DSPI_4_PISR1         DSPI_4.PISR1.R                /* DSPI DSI Parallel Input Select Register 1 */
#define DSPI_4_PISR2         DSPI_4.PISR2.R                /* DSPI DSI Parallel Input Select Register 2 */
#define DSPI_4_PISR3         DSPI_4.PISR3.R                /* DSPI DSI Parallel Input Select Register 3 */
#define DSPI_4_DIMR0         DSPI_4.DIMR0.R                /* DSPI DSI Deserialized Data Interrupt Mask Register 0 */
#define DSPI_4_DPIR0         DSPI_4.DPIR0.R                /* DSPI DSI Deserialized Data Polarity Interrupt Register 0 */
#define DSPI_4_SDR1          DSPI_4.SDR1.R                 /* DSPI DSI Serialization Data Register 1 */
#define DSPI_4_ASDR1         DSPI_4.ASDR1.R                /* DSPI DSI Alternate Serialization Data Register 1 */
#define DSPI_4_COMPR1        DSPI_4.COMPR1.R               /* DSPI DSI Transmit Comparison Register 1 */
#define DSPI_4_DDR1          DSPI_4.DDR1.R                 /* DSPI DSI Deserialization Data Register 1 */
#define DSPI_4_SSR1          DSPI_4.SSR1.R                 /* DSPI DSI Serialization Source Select Register 1 */
#define DSPI_4_PISR4         DSPI_4.PISR4.R                /* DSPI DSI Parallel Input Select Register 4 */
#define DSPI_4_PISR5         DSPI_4.PISR5.R                /* DSPI DSI Parallel Input Select Register 5 */
#define DSPI_4_PISR6         DSPI_4.PISR6.R                /* DSPI DSI Parallel Input Select Register 6 */
#define DSPI_4_PISR7         DSPI_4.PISR7.R                /* DSPI DSI Parallel Input Select Register 7 */
#define DSPI_4_DIMR1         DSPI_4.DIMR1.R                /* DSPI DSI Deserialized Data Interrupt Mask Register 1 */
#define DSPI_4_DPIR1         DSPI_4.DPIR1.R                /* DSPI DSI Deserialized Data Polarity Interrupt Register 1 */
#define DSPI_4_CTARE0        DSPI_4.CTARE[0].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_4_CTARE1        DSPI_4.CTARE[1].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_4_CTARE2        DSPI_4.CTARE[2].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_4_CTARE3        DSPI_4.CTARE[3].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_4_CTARE4        DSPI_4.CTARE[4].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_4_CTARE5        DSPI_4.CTARE[5].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_4_CTARE6        DSPI_4.CTARE[6].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_4_CTARE7        DSPI_4.CTARE[7].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_4_SREX          DSPI_4.SREX.R                 /* DSPI Status Register Extended */

/* DSPI */
#define DSPI_5_MCR           DSPI_5.MCR.R                  /* DSPI Module Configuration Register */
#define DSPI_5_TCR           DSPI_5.TCR.R                  /* DSPI Transfer Count Register */
#define DSPI_5_CTAR0         DSPI_5.MODE.CTAR[0].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_5_CTAR1         DSPI_5.MODE.CTAR[1].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_5_CTAR2         DSPI_5.MODE.CTAR[2].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_5_CTAR3         DSPI_5.MODE.CTAR[3].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_5_CTAR4         DSPI_5.MODE.CTAR[4].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_5_CTAR5         DSPI_5.MODE.CTAR[5].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_5_CTAR6         DSPI_5.MODE.CTAR[6].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_5_CTAR7         DSPI_5.MODE.CTAR[7].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_5_CTAR_SLAVE0   DSPI_5.MODE.CTAR_SLAVE[0].R   /* DSPI Clock and Transfer Attributes Register (In Slave Mode) */
#define DSPI_5_CTAR_SLAVE1   DSPI_5.MODE.CTAR_SLAVE[1].R   /* DSPI Clock and Transfer Attributes Register (In Slave Mode) */
#define DSPI_5_SR            DSPI_5.SR.R                   /* DSPI Status Register */
#define DSPI_5_RSER          DSPI_5.RSER.R                 /* DSPI DMA/Interrupt Request Select and Enable Register */
#define DSPI_5_PUSHR         DSPI_5.PUSHR.PUSHR.R          /* DSPI PUSH FIFO Register In Master Mode */
#define DSPI_5_PUSHR_SLAVE   DSPI_5.PUSHR.PUSHR_SLAVE.R    /* DSPI PUSH FIFO Register In Slave Mode */
#define DSPI_5_POPR          DSPI_5.POPR.R                 /* DSPI POP FIFO Register */
#define DSPI_5_TXFR0         DSPI_5.TXFR[0].R              /* DSPI Transmit FIFO Registers */
#define DSPI_5_TXFR1         DSPI_5.TXFR[1].R              /* DSPI Transmit FIFO Registers */
#define DSPI_5_TXFR2         DSPI_5.TXFR[2].R              /* DSPI Transmit FIFO Registers */
#define DSPI_5_TXFR3         DSPI_5.TXFR[3].R              /* DSPI Transmit FIFO Registers */
#define DSPI_5_RXFR0         DSPI_5.RXFR[0].R              /* DSPI Receive FIFO Registers */
#define DSPI_5_RXFR1         DSPI_5.RXFR[1].R              /* DSPI Receive FIFO Registers */
#define DSPI_5_RXFR2         DSPI_5.RXFR[2].R              /* DSPI Receive FIFO Registers */
#define DSPI_5_RXFR3         DSPI_5.RXFR[3].R              /* DSPI Receive FIFO Registers */
#define DSPI_5_DSICR0        DSPI_5.DSICR0.R               /* DSPI DSI Configuration Register 0 */
#define DSPI_5_SDR0          DSPI_5.SDR0.R                 /* DSPI DSI Serialization Data Register 0 */
#define DSPI_5_ASDR0         DSPI_5.ASDR0.R                /* DSPI DSI Alternate Serialization Data Register 0 */
#define DSPI_5_COMPR0        DSPI_5.COMPR0.R               /* DSPI DSI Transmit Comparison Register 0 */
#define DSPI_5_DDR0          DSPI_5.DDR0.R                 /* DSPI DSI Deserialization Data Register 0 */
#define DSPI_5_DSICR1        DSPI_5.DSICR1.R               /* DSPI DSI Configuration Register 1 */
#define DSPI_5_SSR0          DSPI_5.SSR0.R                 /* DSPI DSI Serialization Source Select Register 0 */
#define DSPI_5_PISR0         DSPI_5.PISR0.R                /* DSPI DSI Parallel Input Select Register 0 */
#define DSPI_5_PISR1         DSPI_5.PISR1.R                /* DSPI DSI Parallel Input Select Register 1 */
#define DSPI_5_PISR2         DSPI_5.PISR2.R                /* DSPI DSI Parallel Input Select Register 2 */
#define DSPI_5_PISR3         DSPI_5.PISR3.R                /* DSPI DSI Parallel Input Select Register 3 */
#define DSPI_5_DIMR0         DSPI_5.DIMR0.R                /* DSPI DSI Deserialized Data Interrupt Mask Register 0 */
#define DSPI_5_DPIR0         DSPI_5.DPIR0.R                /* DSPI DSI Deserialized Data Polarity Interrupt Register 0 */
#define DSPI_5_SDR1          DSPI_5.SDR1.R                 /* DSPI DSI Serialization Data Register 1 */
#define DSPI_5_ASDR1         DSPI_5.ASDR1.R                /* DSPI DSI Alternate Serialization Data Register 1 */
#define DSPI_5_COMPR1        DSPI_5.COMPR1.R               /* DSPI DSI Transmit Comparison Register 1 */
#define DSPI_5_DDR1          DSPI_5.DDR1.R                 /* DSPI DSI Deserialization Data Register 1 */
#define DSPI_5_SSR1          DSPI_5.SSR1.R                 /* DSPI DSI Serialization Source Select Register 1 */
#define DSPI_5_PISR4         DSPI_5.PISR4.R                /* DSPI DSI Parallel Input Select Register 4 */
#define DSPI_5_PISR5         DSPI_5.PISR5.R                /* DSPI DSI Parallel Input Select Register 5 */
#define DSPI_5_PISR6         DSPI_5.PISR6.R                /* DSPI DSI Parallel Input Select Register 6 */
#define DSPI_5_PISR7         DSPI_5.PISR7.R                /* DSPI DSI Parallel Input Select Register 7 */
#define DSPI_5_DIMR1         DSPI_5.DIMR1.R                /* DSPI DSI Deserialized Data Interrupt Mask Register 1 */
#define DSPI_5_DPIR1         DSPI_5.DPIR1.R                /* DSPI DSI Deserialized Data Polarity Interrupt Register 1 */
#define DSPI_5_CTARE0        DSPI_5.CTARE[0].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_5_CTARE1        DSPI_5.CTARE[1].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_5_CTARE2        DSPI_5.CTARE[2].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_5_CTARE3        DSPI_5.CTARE[3].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_5_CTARE4        DSPI_5.CTARE[4].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_5_CTARE5        DSPI_5.CTARE[5].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_5_CTARE6        DSPI_5.CTARE[6].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_5_CTARE7        DSPI_5.CTARE[7].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_5_SREX          DSPI_5.SREX.R                 /* DSPI Status Register Extended */

/* DSPI */
#define DSPI_6_MCR           DSPI_6.MCR.R                  /* DSPI Module Configuration Register */
#define DSPI_6_TCR           DSPI_6.TCR.R                  /* DSPI Transfer Count Register */
#define DSPI_6_CTAR0         DSPI_6.MODE.CTAR[0].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_6_CTAR1         DSPI_6.MODE.CTAR[1].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_6_CTAR2         DSPI_6.MODE.CTAR[2].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_6_CTAR3         DSPI_6.MODE.CTAR[3].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_6_CTAR4         DSPI_6.MODE.CTAR[4].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_6_CTAR5         DSPI_6.MODE.CTAR[5].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_6_CTAR6         DSPI_6.MODE.CTAR[6].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_6_CTAR7         DSPI_6.MODE.CTAR[7].R         /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
#define DSPI_6_CTAR_SLAVE0   DSPI_6.MODE.CTAR_SLAVE[0].R   /* DSPI Clock and Transfer Attributes Register (In Slave Mode) */
#define DSPI_6_CTAR_SLAVE1   DSPI_6.MODE.CTAR_SLAVE[1].R   /* DSPI Clock and Transfer Attributes Register (In Slave Mode) */
#define DSPI_6_SR            DSPI_6.SR.R                   /* DSPI Status Register */
#define DSPI_6_RSER          DSPI_6.RSER.R                 /* DSPI DMA/Interrupt Request Select and Enable Register */
#define DSPI_6_PUSHR         DSPI_6.PUSHR.PUSHR.R          /* DSPI PUSH FIFO Register In Master Mode */
#define DSPI_6_PUSHR_SLAVE   DSPI_6.PUSHR.PUSHR_SLAVE.R    /* DSPI PUSH FIFO Register In Slave Mode */
#define DSPI_6_POPR          DSPI_6.POPR.R                 /* DSPI POP FIFO Register */
#define DSPI_6_TXFR0         DSPI_6.TXFR[0].R              /* DSPI Transmit FIFO Registers */
#define DSPI_6_TXFR1         DSPI_6.TXFR[1].R              /* DSPI Transmit FIFO Registers */
#define DSPI_6_TXFR2         DSPI_6.TXFR[2].R              /* DSPI Transmit FIFO Registers */
#define DSPI_6_TXFR3         DSPI_6.TXFR[3].R              /* DSPI Transmit FIFO Registers */
#define DSPI_6_RXFR0         DSPI_6.RXFR[0].R              /* DSPI Receive FIFO Registers */
#define DSPI_6_RXFR1         DSPI_6.RXFR[1].R              /* DSPI Receive FIFO Registers */
#define DSPI_6_RXFR2         DSPI_6.RXFR[2].R              /* DSPI Receive FIFO Registers */
#define DSPI_6_RXFR3         DSPI_6.RXFR[3].R              /* DSPI Receive FIFO Registers */
#define DSPI_6_DSICR0        DSPI_6.DSICR0.R               /* DSPI DSI Configuration Register 0 */
#define DSPI_6_SDR0          DSPI_6.SDR0.R                 /* DSPI DSI Serialization Data Register 0 */
#define DSPI_6_ASDR0         DSPI_6.ASDR0.R                /* DSPI DSI Alternate Serialization Data Register 0 */
#define DSPI_6_COMPR0        DSPI_6.COMPR0.R               /* DSPI DSI Transmit Comparison Register 0 */
#define DSPI_6_DDR0          DSPI_6.DDR0.R                 /* DSPI DSI Deserialization Data Register 0 */
#define DSPI_6_DSICR1        DSPI_6.DSICR1.R               /* DSPI DSI Configuration Register 1 */
#define DSPI_6_SSR0          DSPI_6.SSR0.R                 /* DSPI DSI Serialization Source Select Register 0 */
#define DSPI_6_PISR0         DSPI_6.PISR0.R                /* DSPI DSI Parallel Input Select Register 0 */
#define DSPI_6_PISR1         DSPI_6.PISR1.R                /* DSPI DSI Parallel Input Select Register 1 */
#define DSPI_6_PISR2         DSPI_6.PISR2.R                /* DSPI DSI Parallel Input Select Register 2 */
#define DSPI_6_PISR3         DSPI_6.PISR3.R                /* DSPI DSI Parallel Input Select Register 3 */
#define DSPI_6_DIMR0         DSPI_6.DIMR0.R                /* DSPI DSI Deserialized Data Interrupt Mask Register 0 */
#define DSPI_6_DPIR0         DSPI_6.DPIR0.R                /* DSPI DSI Deserialized Data Polarity Interrupt Register 0 */
#define DSPI_6_SDR1          DSPI_6.SDR1.R                 /* DSPI DSI Serialization Data Register 1 */
#define DSPI_6_ASDR1         DSPI_6.ASDR1.R                /* DSPI DSI Alternate Serialization Data Register 1 */
#define DSPI_6_COMPR1        DSPI_6.COMPR1.R               /* DSPI DSI Transmit Comparison Register 1 */
#define DSPI_6_DDR1          DSPI_6.DDR1.R                 /* DSPI DSI Deserialization Data Register 1 */
#define DSPI_6_SSR1          DSPI_6.SSR1.R                 /* DSPI DSI Serialization Source Select Register 1 */
#define DSPI_6_PISR4         DSPI_6.PISR4.R                /* DSPI DSI Parallel Input Select Register 4 */
#define DSPI_6_PISR5         DSPI_6.PISR5.R                /* DSPI DSI Parallel Input Select Register 5 */
#define DSPI_6_PISR6         DSPI_6.PISR6.R                /* DSPI DSI Parallel Input Select Register 6 */
#define DSPI_6_PISR7         DSPI_6.PISR7.R                /* DSPI DSI Parallel Input Select Register 7 */
#define DSPI_6_DIMR1         DSPI_6.DIMR1.R                /* DSPI DSI Deserialized Data Interrupt Mask Register 1 */
#define DSPI_6_DPIR1         DSPI_6.DPIR1.R                /* DSPI DSI Deserialized Data Polarity Interrupt Register 1 */
#define DSPI_6_CTARE0        DSPI_6.CTARE[0].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_6_CTARE1        DSPI_6.CTARE[1].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_6_CTARE2        DSPI_6.CTARE[2].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_6_CTARE3        DSPI_6.CTARE[3].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_6_CTARE4        DSPI_6.CTARE[4].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_6_CTARE5        DSPI_6.CTARE[5].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_6_CTARE6        DSPI_6.CTARE[6].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_6_CTARE7        DSPI_6.CTARE[7].R             /* DSPI Clock and Transfer Attributes Register Extended */
#define DSPI_6_SREX          DSPI_6.SREX.R                 /* DSPI Status Register Extended */

/* DTS */
#define DTS_ENABLE           DTS.ENABLE.R                  /* Output Enable Register */
#define DTS_STARTUP          DTS.STARTUP.R                 /* Startup Register */
#define DTS_SEMAPHORE        DTS.SEMAPHORE.R               /* Semaphore Register */
#define DTS_SEMAPHORE_B      DTS.SEMAPHORE_B.R             /* Semaphore Extension */

/* EBI */
#define EBI_MCR              EBI.MCR.R                     /* Module Configuration Register */
#define EBI_BR0              EBI.BR0.R                     /* Base Register Bank */
#define EBI_OR0              EBI.OR0.R                     /* Option Register Bank */
#define EBI_BR1              EBI.BR1.R                     /* Base Register Bank */
#define EBI_OR1              EBI.OR1.R                     /* Option Register Bank */
#define EBI_BR2              EBI.BR2.R                     /* Base Register Bank */
#define EBI_OR2              EBI.OR2.R                     /* Option Register Bank */
#define EBI_BR3              EBI.BR3.R                     /* Base Register Bank */
#define EBI_OR3              EBI.OR3.R                     /* Option Register Bank */

/* FCCU */
#define FCCU_CTRL            FCCU.CTRL.R                   /* Control Register */
#define FCCU_CTRLK           FCCU.CTRLK.R                  /* CTRL Key Register */
#define FCCU_CFG             FCCU.CFG.R                    /* Configuration Register */
#define FCCU_RF_CFG0         FCCU.RF_CFG[0].R              /* RF Configuration Register */
#define FCCU_RF_CFG1         FCCU.RF_CFG[1].R              /* RF Configuration Register */
#define FCCU_RF_CFG2         FCCU.RF_CFG[2].R              /* RF Configuration Register */
#define FCCU_RF_CFG3         FCCU.RF_CFG[3].R              /* RF Configuration Register */
#define FCCU_RFS_CFG0        FCCU.RFS_CFG[0].R             /* RFS Configuration Register */
#define FCCU_RFS_CFG1        FCCU.RFS_CFG[1].R             /* RFS Configuration Register */
#define FCCU_RFS_CFG2        FCCU.RFS_CFG[2].R             /* RFS Configuration Register */
#define FCCU_RFS_CFG3        FCCU.RFS_CFG[3].R             /* RFS Configuration Register */
#define FCCU_RFS_CFG4        FCCU.RFS_CFG[4].R             /* RFS Configuration Register */
#define FCCU_RFS_CFG5        FCCU.RFS_CFG[5].R             /* RFS Configuration Register */
#define FCCU_RFS_CFG6        FCCU.RFS_CFG[6].R             /* RFS Configuration Register */
#define FCCU_RFS_CFG7        FCCU.RFS_CFG[7].R             /* RFS Configuration Register */
#define FCCU_RF_S0           FCCU.RF_S[0].R                /* UF Status Register */
#define FCCU_RF_S1           FCCU.RF_S[1].R                /* UF Status Register */
#define FCCU_RF_S2           FCCU.RF_S[2].R                /* UF Status Register */
#define FCCU_RF_S3           FCCU.RF_S[3].R                /* UF Status Register */
#define FCCU_RFK             FCCU.RFK.R                    /* RF Key Register */
#define FCCU_RF_E0           FCCU.RF_E[0].R                /* RF Enable Register */
#define FCCU_RF_E1           FCCU.RF_E[1].R                /* RF Enable Register */
#define FCCU_RF_E2           FCCU.RF_E[2].R                /* RF Enable Register */
#define FCCU_RF_E3           FCCU.RF_E[3].R                /* RF Enable Register */
#define FCCU_RF_TOE0         FCCU.RF_TOE[0].R              /* RF Time-out Enable Register */
#define FCCU_RF_TOE1         FCCU.RF_TOE[1].R              /* RF Time-out Enable Register */
#define FCCU_RF_TOE2         FCCU.RF_TOE[2].R              /* RF Time-out Enable Register */
#define FCCU_RF_TOE3         FCCU.RF_TOE[3].R              /* RF Time-out Enable Register */
#define FCCU_RF_TO           FCCU.RF_TO.R                  /* RF Time-out Register */
#define FCCU_CFG_TO          FCCU.CFG_TO.R                 /* CFG Timeout Register */
#define FCCU_EINOUT          FCCU.EINOUT.R                 /* IO Control Register */
#define FCCU_STAT            FCCU.STAT.R                   /* Status Register */
#define FCCU_N2AF_STATUS     FCCU.N2AF_STATUS.R            /* NA Freeze Status Register */
#define FCCU_A2FF_STATUS     FCCU.A2FF_STATUS.R            /* AF Freeze Status Register */
#define FCCU_N2FF_STATUS     FCCU.N2FF_STATUS.R            /* NF Freeze Status Register */
#define FCCU_F2A_STATUS      FCCU.F2A_STATUS.R             /* FA Freeze Status Register */
#define FCCU_RFF             FCCU.RFF.R                    /* RF Fake Register */
#define FCCU_IRQ_STAT        FCCU.IRQ_STAT.R               /* IRQ Status Register */
#define FCCU_IRQ_EN          FCCU.IRQ_EN.R                 /* IRQ Enable Register */
#define FCCU_XTMR            FCCU.XTMR.R                   /* XTMR Register */
#define FCCU_MCS             FCCU.MCS.R                    /* MCS Register */
#define FCCU_TRANS_LOCK      FCCU.TRANS_LOCK.R             /* Transient Lock Register */
#define FCCU_PERMNT_LOCK     FCCU.PERMNT_LOCK.R            /* Permanent Lock Register */
#define FCCU_DELTA_T         FCCU.DELTA_T.R                /* Delta T Register */
#define FCCU_IRQ_ALARM_EN0   FCCU.IRQ_ALARM_EN[0].R        /* IRQ Alarm Enable Register */
#define FCCU_IRQ_ALARM_EN1   FCCU.IRQ_ALARM_EN[1].R        /* IRQ Alarm Enable Register */
#define FCCU_IRQ_ALARM_EN2   FCCU.IRQ_ALARM_EN[2].R        /* IRQ Alarm Enable Register */
#define FCCU_IRQ_ALARM_EN3   FCCU.IRQ_ALARM_EN[3].R        /* IRQ Alarm Enable Register */
#define FCCU_NMI_EN0         FCCU.NMI_EN[0].R              /* NMI Enable Register */
#define FCCU_NMI_EN1         FCCU.NMI_EN[1].R              /* NMI Enable Register */
#define FCCU_NMI_EN2         FCCU.NMI_EN[2].R              /* NMI Enable Register */
#define FCCU_NMI_EN3         FCCU.NMI_EN[3].R              /* NMI Enable Register */
#define FCCU_EOUT_SIG_EN0    FCCU.EOUT_SIG_EN[0].R         /* EOUT Signaling Enable Register */
#define FCCU_EOUT_SIG_EN1    FCCU.EOUT_SIG_EN[1].R         /* EOUT Signaling Enable Register */
#define FCCU_EOUT_SIG_EN2    FCCU.EOUT_SIG_EN[2].R         /* EOUT Signaling Enable Register */
#define FCCU_EOUT_SIG_EN3    FCCU.EOUT_SIG_EN[3].R         /* EOUT Signaling Enable Register */

/* FEC */
#define FEC_EIR              FEC.EIR.R                     /* Interrupt Event Register */
#define FEC_EIMR             FEC.EIMR.R                    /* Interrupt Mask Register */
#define FEC_RDAR             FEC.RDAR.R                    /* Receive Descriptor Active Register */
#define FEC_TDAR             FEC.TDAR.R                    /* Transmit Descriptor Active Register */
#define FEC_ECR              FEC.ECR.R                     /* Ethernet Control Register */
#define FEC_MMFR             FEC.MMFR.R                    /* MII Management Frame Register */
#define FEC_MSCR             FEC.MSCR.R                    /* MII Speed Control Register */
#define FEC_MIBC             FEC.MIBC.R                    /* MIB Control Register */
#define FEC_RCR              FEC.RCR.R                     /* Receive Control Register */
#define FEC_TCR              FEC.TCR.R                     /* Transmit Control Register */
#define FEC_PALR             FEC.PALR.R                    /* Physical Address Low Register */
#define FEC_PAUR             FEC.PAUR.R                    /* Physical Address High Register and Type Field */
#define FEC_OPD              FEC.OPD.R                     /* Opcode/Pause Duration */
#define FEC_IAUR             FEC.IAUR.R                    /* Descriptor Individual Upper Address Register */
#define FEC_IALR             FEC.IALR.R                    /* Descriptor Individual Lower Address Register */
#define FEC_GAUR             FEC.GAUR.R                    /* Descriptor Group Upper Address Register */
#define FEC_GALR             FEC.GALR.R                    /* Descriptor Group Lower Address Register */
#define FEC_TFWR             FEC.TFWR.R                    /* Transmit FIFO Watermark */
#define FEC_FRBR             FEC.FRBR.R                    /* FIFO Receive Bound Register */
#define FEC_FRSR             FEC.FRSR.R                    /* FIFO Receive Start Register */
#define FEC_ERDSR            FEC.ERDSR.R                   /* Receive Descriptor Ring Start Register */
#define FEC_ETDSR            FEC.ETDSR.R                   /* Transmit Buffer Descriptor Ring Start Register */
#define FEC_EMRBR            FEC.EMRBR.R                   /* Receive Buffer Size Register */
#define FEC_RMON_T_DROP      FEC.RMON_T_DROP.R             /* Count of frames not counted correctly */
#define FEC_RMON_T_PACKETS   FEC.RMON_T_PACKETS.R          /* RMON Tx packet count */
#define FEC_RMON_T_BC_PKT    FEC.RMON_T_BC_PKT.R           /* RMON Tx broadcast packets */
#define FEC_RMON_T_MC_PKT    FEC.RMON_T_MC_PKT.R           /* RMON Tx multicast packets */
#define FEC_RMON_T_CRC_ALIGN FEC.RMON_T_CRC_ALIGN.R        /* RMON Tx packets with CRC/align error */
#define FEC_RMON_T_UNDERSIZE FEC.RMON_T_UNDERSIZE.R        /* RMON Tx packets < 64 bytes, good CRC */
#define FEC_RMON_T_OVERSIZE  FEC.RMON_T_OVERSIZE.R         /* RMON Tx packets > MAX_FL bytes, good CRC */
#define FEC_RMON_T_FRAG      FEC.RMON_T_FRAG.R             /* RMON Tx packets < 64 bytes, bad CRC */
#define FEC_RMON_T_JAB       FEC.RMON_T_JAB.R              /* RMON Tx packets > MAX_FL bytes, bad CRC */
#define FEC_RMON_T_COL       FEC.RMON_T_COL.R              /* RMON Tx collision count */
#define FEC_RMON_T_P64       FEC.RMON_T_P64.R              /* RMON Tx 64 byte packets */
#define FEC_RMON_T_P65TO127  FEC.RMON_T_P65TO127.R         /* RMON Tx 65 to 127 byte packets */
#define FEC_RMON_T_P128TO255 FEC.RMON_T_P128TO255.R        /* RMON Tx 128 to 255 byte packets */
#define FEC_RMON_T_P256TO511 FEC.RMON_T_P256TO511.R        /* RMON Tx 256 to 511 byte packets */
#define FEC_RMON_T_P512TO1023 FEC.RMON_T_P512TO1023.R      /* RMON Tx 512 to 1023 byte packets */
#define FEC_RMON_T_P1024TO2047 FEC.RMON_T_P1024TO2047.R    /* RMON Tx 1024 to 2047 byte packets */
#define FEC_RMON_T_P_GTE2048 FEC.RMON_T_P_GTE2048.R        /* RMON Tx packets with > 2048 bytes */
#define FEC_RMON_T_OCTETS    FEC.RMON_T_OCTETS.R           /* RMON Tx Octets */
#define FEC_IEEE_T_DROP      FEC.IEEE_T_DROP.R             /* Count of transmitted frames not counted correctly */
#define FEC_IEEE_T_FRAME_OK  FEC.IEEE_T_FRAME_OK.R         /* Frames transmitted OK */
#define FEC_IEEE_T_1COL      FEC.IEEE_T_1COL.R             /* Frames transmitted with single collision */
#define FEC_IEEE_T_MCOL      FEC.IEEE_T_MCOL.R             /* Frames transmitted with multiple collisions */
#define FEC_IEEE_T_DEF       FEC.IEEE_T_DEF.R              /* Frames transmitted after deferral delay */
#define FEC_IEEE_T_LCOL      FEC.IEEE_T_LCOL.R             /* Frames transmitted with late collision */
#define FEC_IEEE_T_EXCOL     FEC.IEEE_T_EXCOL.R            /* Frames transmitted with excessive collisions */
#define FEC_IEEE_T_MACERR    FEC.IEEE_T_MACERR.R           /* Frames transmitted with Tx FIFO underrun */
#define FEC_IEEE_T_CSERR     FEC.IEEE_T_CSERR.R            /* Frames transmitted with carrier sense error */
#define FEC_IEEE_T_SQE       FEC.IEEE_T_SQE.R              /* Frames transmitted with SQE error */
#define FEC_IEEE_T_FDXFC     FEC.IEEE_T_FDXFC.R            /* Flow control pause frames transmitted */
#define FEC_IEEE_T_OCTETS_OK FEC.IEEE_T_OCTETS_OK.R        /* Octet count for frames transmitted without error */
#define FEC_RMON_R_DROP      FEC.RMON_R_DROP.R             /* Count of received frames not counted correctly */
#define FEC_RMON_R_PACKETS   FEC.RMON_R_PACKETS.R          /* RMON Rx packet count */
#define FEC_RMON_R_BC_PKT    FEC.RMON_R_BC_PKT.R           /* RMON Rx broadcast packets */
#define FEC_RMON_R_MC_PKT    FEC.RMON_R_MC_PKT.R           /* RMON Rx multicast packets */
#define FEC_RMON_R_CRC_ALIGN FEC.RMON_R_CRC_ALIGN.R        /* RMON Rx packets with CRC/Align error */
#define FEC_RMON_R_UNDERSIZE FEC.RMON_R_UNDERSIZE.R        /* RMON Rx packets < 64 bytes, good CRC */
#define FEC_RMON_R_OVERSIZE  FEC.RMON_R_OVERSIZE.R         /* RMON Rx packets > MAX_FL bytes, good CRC */
#define FEC_RMON_R_FRAG      FEC.RMON_R_FRAG.R             /* RMON Rx packets < 64 bytes, bad CRC */
#define FEC_RMON_R_JAB       FEC.RMON_R_JAB.R              /* RMON Rx packets > MAX_FL bytes, bad CRC */
#define FEC_RMON_R_RESVD_0   FEC.RMON_R_RESVD_0.R          /* Reserved */
#define FEC_RMON_R_P64       FEC.RMON_R_P64.R              /* RMON Rx 64 byte packets */
#define FEC_RMON_R_P65TO127  FEC.RMON_R_P65TO127.R         /* RMON Rx 65 to 127 byte packets */
#define FEC_RMON_R_P128TO255 FEC.RMON_R_P128TO255.R        /* RMON Rx 128 to 255 byte packets */
#define FEC_RMON_R_P256TO511 FEC.RMON_R_P256TO511.R        /* RMON Rx 256 to 511 byte packets */
#define FEC_RMON_R_P512TO1023 FEC.RMON_R_P512TO1023.R      /* RMON Rx 512 to 1023 byte packets */
#define FEC_RMON_R_P1024TO2047 FEC.RMON_R_P1024TO2047.R    /* RMON Rx 1024 to 2047 byte packets */
#define FEC_RMON_R_P_GTE2048 FEC.RMON_R_P_GTE2048.R        /* RMON Rx packets with > 2048 bytes */
#define FEC_RMON_R_OCTETS    FEC.RMON_R_OCTETS.R           /* RMON Rx octets */
#define FEC_IEEE_R_DROP      FEC.IEEE_R_DROP.R             /* Count of received frames not counted correctly */
#define FEC_IEEE_R_FRAME_OK  FEC.IEEE_R_FRAME_OK.R         /* Frames received OK */
#define FEC_IEEE_R_CRC       FEC.IEEE_R_CRC.R              /* Frames received with CRC error */
#define FEC_IEEE_R_ALIGN     FEC.IEEE_R_ALIGN.R            /* Frames received with alignment error */
#define FEC_IEEE_R_MACERR    FEC.IEEE_R_MACERR.R           /* Receive FIFO overflow count */
#define FEC_IEEE_R_FDXFC     FEC.IEEE_R_FDXFC.R            /* Flow control pause frames received */
#define FEC_IEEE_R_OCTETS_OK FEC.IEEE_R_OCTETS_OK.R        /* Octet count for frames received without error */

/* FR */
#define FR_0_MVR             FR_0.MVR.R                    /* Module Version Register */
#define FR_0_MCR             FR_0.MCR.R                    /* Module Configuration Register */
#define FR_0_SYMBADHR        FR_0.SYMBADHR.R               /* System Memory Base Address High Register */
#define FR_0_SYMBADLR        FR_0.SYMBADLR.R               /* System Memory Base Address Low Register */
#define FR_0_STBSCR          FR_0.STBSCR.R                 /* Strobe Signal Control Register */
#define FR_0_MBDSR           FR_0.MBDSR.R                  /* Message Buffer Data Size Register */
#define FR_0_MBSSUTR         FR_0.MBSSUTR.R                /* Message Buffer Segment Size and Utilization Register */
#define FR_0_PEDRAR          FR_0.PEDRAR.R                 /* PE DRAM Access Register */
#define FR_0_PEDRDR          FR_0.PEDRDR.R                 /* PE DRAM Data Register */
#define FR_0_POCR            FR_0.POCR.R                   /* Protocol Operation Control Register */
#define FR_0_GIFER           FR_0.GIFER.R                  /* Global Interrupt Flag and Enable Register */
#define FR_0_PIFR0           FR_0.PIFR0.R                  /* Protocol Interrupt Flag Register 0 */
#define FR_0_PIFR1           FR_0.PIFR1.R                  /* Protocol Interrupt Flag Register 1 */
#define FR_0_PIER0           FR_0.PIER0.R                  /* Protocol Interrupt Enable Register 0 */
#define FR_0_PIER1           FR_0.PIER1.R                  /* Protocol Interrupt Enable Register 1 */
#define FR_0_CHIERFR         FR_0.CHIERFR.R                /* CHI Error Flag Register */
#define FR_0_MBIVEC          FR_0.MBIVEC.R                 /* Message Buffer Interrupt Vector Register */
#define FR_0_CASERCR         FR_0.CASERCR.R                /* Channel A Status Error Counter Register */
#define FR_0_CBSERCR         FR_0.CBSERCR.R                /* Channel B Status Error Counter Register */
#define FR_0_PSR0            FR_0.PSR0.R                   /* Protocol Status Register 0 */
#define FR_0_PSR1            FR_0.PSR1.R                   /* Protocol Status Register 1 */
#define FR_0_PSR2            FR_0.PSR2.R                   /* Protocol Status Register 2 */
#define FR_0_PSR3            FR_0.PSR3.R                   /* Protocol Status Register 3 */
#define FR_0_MTCTR           FR_0.MTCTR.R                  /* Macrotick Counter Register */
#define FR_0_CYCTR           FR_0.CYCTR.R                  /* Cycle Counter Register */
#define FR_0_SLTCTAR         FR_0.SLTCTAR.R                /* Slot Counter Channel A Register */
#define FR_0_SLTCTBR         FR_0.SLTCTBR.R                /* Slot Counter Channel B Register */
#define FR_0_RTCORVR         FR_0.RTCORVR.R                /* Rate Correction Value Register */
#define FR_0_OFCORVR         FR_0.OFCORVR.R                /* Offset Correction Value Register */
#define FR_0_CIFR            FR_0.CIFR.R                   /* Combined Interrupt Flag Register */
#define FR_0_SYMATOR         FR_0.SYMATOR.R                /* System Memory Access Time-Out Register */
#define FR_0_SFCNTR          FR_0.SFCNTR.R                 /* Sync Frame Counter Register */
#define FR_0_SFTOR           FR_0.SFTOR.R                  /* Sync Frame Table Offset Register */
#define FR_0_SFTCCSR         FR_0.SFTCCSR.R                /* Sync Frame Table Configuration, Control, Status Register */
#define FR_0_SFIDRFR         FR_0.SFIDRFR.R                /* Sync Frame ID Rejection Filter Register */
#define FR_0_SFIDAFVR        FR_0.SFIDAFVR.R               /* Sync Frame ID Acceptance Filter Value Register */
#define FR_0_SFIDAFMR        FR_0.SFIDAFMR.R               /* Sync Frame ID Acceptance Filter Mask Register */
#define FR_0_NMVR0           FR_0.NMVR[0].R                /* Network Management Vector Register */
#define FR_0_NMVR1           FR_0.NMVR[1].R                /* Network Management Vector Register */
#define FR_0_NMVR2           FR_0.NMVR[2].R                /* Network Management Vector Register */
#define FR_0_NMVR3           FR_0.NMVR[3].R                /* Network Management Vector Register */
#define FR_0_NMVR4           FR_0.NMVR[4].R                /* Network Management Vector Register */
#define FR_0_NMVR5           FR_0.NMVR[5].R                /* Network Management Vector Register */
#define FR_0_NMVLR           FR_0.NMVLR.R                  /* Network Management Vector Length Register */
#define FR_0_TICCR           FR_0.TICCR.R                  /* Timer Configuration and Control Register */
#define FR_0_TI1CYSR         FR_0.TI1CYSR.R                /* Timer 1 Cycle Set Register */
#define FR_0_TI1MTOR         FR_0.TI1MTOR.R                /* Timer 1 Macrotick Offset Register */
#define FR_0_TI2CR0_ABS      FR_0.TI2CR0.ABS.R             /* Timer 2 Configuration Register 0 (Absolute Timer Configuration) */
#define FR_0_TI2CR0_REL      FR_0.TI2CR0.REL.R             /* Timer 2 Configuration Register 0 (Relative Timer Configuration) */
#define FR_0_TI2CR1_ABS      FR_0.TI2CR1.ABS.R             /* Timer 2 Configuration Register 1 (Absolute Timer Configuration) */
#define FR_0_TI2CR1_REL      FR_0.TI2CR1.REL.R             /* Timer 2 Configuration Register 1 (Relative Timer Configuration) */
#define FR_0_SSSR            FR_0.SSSR.R                   /* Slot Status Selection Register */
#define FR_0_SSCCR           FR_0.SSCCR.R                  /* Slot Status Counter Condition Register */
#define FR_0_SSR0            FR_0.SSR[0].R                 /* Slot Status Register */
#define FR_0_SSR1            FR_0.SSR[1].R                 /* Slot Status Register */
#define FR_0_SSR2            FR_0.SSR[2].R                 /* Slot Status Register */
#define FR_0_SSR3            FR_0.SSR[3].R                 /* Slot Status Register */
#define FR_0_SSR4            FR_0.SSR[4].R                 /* Slot Status Register */
#define FR_0_SSR5            FR_0.SSR[5].R                 /* Slot Status Register */
#define FR_0_SSR6            FR_0.SSR[6].R                 /* Slot Status Register */
#define FR_0_SSR7            FR_0.SSR[7].R                 /* Slot Status Register */
#define FR_0_SSCR0           FR_0.SSCR[0].R                /* Slot Status Counter Register */
#define FR_0_SSCR1           FR_0.SSCR[1].R                /* Slot Status Counter Register */
#define FR_0_SSCR2           FR_0.SSCR[2].R                /* Slot Status Counter Register */
#define FR_0_SSCR3           FR_0.SSCR[3].R                /* Slot Status Counter Register */
#define FR_0_MTSACFR         FR_0.MTSACFR.R                /* MTS A Configuration Register */
#define FR_0_MTSBCFR         FR_0.MTSBCFR.R                /* MTS B Configuration Register */
#define FR_0_RSBIR           FR_0.RSBIR.R                  /* Receive Shadow Buffer Index Register */
#define FR_0_RFWMSR          FR_0.RFWMSR.R                 /* Receive FIFO Watermark and Selection Register */
#define FR_0_RFSIR           FR_0.RFSIR.R                  /* Receive FIFO Start Index Register */
#define FR_0_RFDSR           FR_0.RFDSR.R                  /* Receive FIFO Depth and Size Register */
#define FR_0_RFARIR          FR_0.RFARIR.R                 /* Receive FIFO A Read Index Register */
#define FR_0_RFBRIR          FR_0.RFBRIR.R                 /* Receive FIFO B Read Index Register */
#define FR_0_RFMIDAFVR       FR_0.RFMIDAFVR.R              /* Receive FIFO Message ID Acceptance Filter Value Register */
#define FR_0_RFMIDAFMR       FR_0.RFMIDAFMR.R              /* Receive FIFO Message ID Acceptance Filter Mask Register */
#define FR_0_RFFIDRFVR       FR_0.RFFIDRFVR.R              /* Receive FIFO Frame ID Rejection Filter Value Register */
#define FR_0_RFFIDRFMR       FR_0.RFFIDRFMR.R              /* Receive FIFO Frame ID Rejection Filter Mask Register */
#define FR_0_RFRFCFR         FR_0.RFRFCFR.R                /* Receive FIFO Range Filter Configuration Register */
#define FR_0_RFRFCTR         FR_0.RFRFCTR.R                /* Receive FIFO Range Filter Control Register */
#define FR_0_LDTXSLAR        FR_0.LDTXSLAR.R               /* Last Dynamic Transmit Slot Channel A Register */
#define FR_0_LDTXSLBR        FR_0.LDTXSLBR.R               /* Last Dynamic Transmit Slot Channel B Register */
#define FR_0_PCR0            FR_0.PCR0.R                   /* Protocol Configuration Register 0 */
#define FR_0_PCR1            FR_0.PCR1.R                   /* Protocol Configuration Register 1 */
#define FR_0_PCR2            FR_0.PCR2.R                   /* Protocol Configuration Register 2 */
#define FR_0_PCR3            FR_0.PCR3.R                   /* Protocol Configuration Register 3 */
#define FR_0_PCR4            FR_0.PCR4.R                   /* Protocol Configuration Register 4 */
#define FR_0_PCR5            FR_0.PCR5.R                   /* Protocol Configuration Register 5 */
#define FR_0_PCR6            FR_0.PCR6.R                   /* Protocol Configuration Register 6 */
#define FR_0_PCR7            FR_0.PCR7.R                   /* Protocol Configuration Register 7 */
#define FR_0_PCR8            FR_0.PCR8.R                   /* Protocol Configuration Register 8 */
#define FR_0_PCR9            FR_0.PCR9.R                   /* Protocol Configuration Register 9 */
#define FR_0_PCR10           FR_0.PCR10.R                  /* Protocol Configuration Register 10 */
#define FR_0_PCR11           FR_0.PCR11.R                  /* Protocol Configuration Register 11 */
#define FR_0_PCR12           FR_0.PCR12.R                  /* Protocol Configuration Register 12 */
#define FR_0_PCR13           FR_0.PCR13.R                  /* Protocol Configuration Register 13 */
#define FR_0_PCR14           FR_0.PCR14.R                  /* Protocol Configuration Register 14 */
#define FR_0_PCR15           FR_0.PCR15.R                  /* Protocol Configuration Register 15 */
#define FR_0_PCR16           FR_0.PCR16.R                  /* Protocol Configuration Register 16 */
#define FR_0_PCR17           FR_0.PCR17.R                  /* Protocol Configuration Register 17 */
#define FR_0_PCR18           FR_0.PCR18.R                  /* Protocol Configuration Register 18 */
#define FR_0_PCR19           FR_0.PCR19.R                  /* Protocol Configuration Register 19 */
#define FR_0_PCR20           FR_0.PCR20.R                  /* Protocol Configuration Register 20 */
#define FR_0_PCR21           FR_0.PCR21.R                  /* Protocol Configuration Register 21 */
#define FR_0_PCR22           FR_0.PCR22.R                  /* Protocol Configuration Register 22 */
#define FR_0_PCR23           FR_0.PCR23.R                  /* Protocol Configuration Register 23 */
#define FR_0_PCR24           FR_0.PCR24.R                  /* Protocol Configuration Register 24 */
#define FR_0_PCR25           FR_0.PCR25.R                  /* Protocol Configuration Register 25 */
#define FR_0_PCR26           FR_0.PCR26.R                  /* Protocol Configuration Register 26 */
#define FR_0_PCR27           FR_0.PCR27.R                  /* Protocol Configuration Register 27 */
#define FR_0_PCR28           FR_0.PCR28.R                  /* Protocol Configuration Register 28 */
#define FR_0_PCR29           FR_0.PCR29.R                  /* Protocol Configuration Register 29 */
#define FR_0_PCR30           FR_0.PCR30.R                  /* Protocol Configuration Register 30 */
#define FR_0_STPWR           FR_0.STPWR.R                  /* StopWatch Count Register */
#define FR_0_PEOER           FR_0.PEOER.R                  /* Protocol Event Output Enable and StopWatch Control Register */
#define FR_0_RFSDOR          FR_0.RFSDOR.R                 /* Receive FIFO Start Data Offset Register */
#define FR_0_RFSYMBADHR      FR_0.RFSYMBADHR.R             /* Receive FIFO System Memory Base Address High Register */
#define FR_0_RFSYMBADLR      FR_0.RFSYMBADLR.R             /* Receive FIFO System Memory Base Address Low Register */
#define FR_0_RFPTR           FR_0.RFPTR.R                  /* Receive FIFO Periodic Timer Register */
#define FR_0_RFFLPCR         FR_0.RFFLPCR.R                /* Receive FIFO Fill Level and POP Count Register */
#define FR_0_EEIFER          FR_0.EEIFER.R                 /* ECC Error Interrupt Flag and Enable Register */
#define FR_0_EERICR          FR_0.EERICR.R                 /* ECC Error Report and Injection Control Register */
#define FR_0_EERAR           FR_0.EERAR.R                  /* ECC Error Report Address Register */
#define FR_0_EERDR           FR_0.EERDR.R                  /* ECC Error Report Data Register */
#define FR_0_EERCR           FR_0.EERCR.R                  /* ECC Error Report Code Register */
#define FR_0_EEIAR           FR_0.EEIAR.R                  /* ECC Error Injection Address Register */
#define FR_0_EEIDR           FR_0.EEIDR.R                  /* ECC Error Injection Data Register */
#define FR_0_EEICR           FR_0.EEICR.R                  /* ECC Error Injection Code Register */
#define FR_0_MBCCSR0         FR_0.MB[0].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR0         FR_0.MB[0].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR0         FR_0.MB[0].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR0         FR_0.MB[0].IDXR.R             /* Message Buffer Index Register */
#define FR_0_MBCCSR1         FR_0.MB[1].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR1         FR_0.MB[1].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR1         FR_0.MB[1].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR1         FR_0.MB[1].IDXR.R             /* Message Buffer Index Register */
#define FR_0_MBCCSR2         FR_0.MB[2].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR2         FR_0.MB[2].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR2         FR_0.MB[2].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR2         FR_0.MB[2].IDXR.R             /* Message Buffer Index Register */
#define FR_0_MBCCSR3         FR_0.MB[3].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR3         FR_0.MB[3].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR3         FR_0.MB[3].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR3         FR_0.MB[3].IDXR.R             /* Message Buffer Index Register */
#define FR_0_MBCCSR4         FR_0.MB[4].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR4         FR_0.MB[4].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR4         FR_0.MB[4].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR4         FR_0.MB[4].IDXR.R             /* Message Buffer Index Register */
#define FR_0_MBCCSR5         FR_0.MB[5].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR5         FR_0.MB[5].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR5         FR_0.MB[5].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR5         FR_0.MB[5].IDXR.R             /* Message Buffer Index Register */
#define FR_0_MBCCSR6         FR_0.MB[6].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR6         FR_0.MB[6].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR6         FR_0.MB[6].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR6         FR_0.MB[6].IDXR.R             /* Message Buffer Index Register */
#define FR_0_MBCCSR7         FR_0.MB[7].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR7         FR_0.MB[7].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR7         FR_0.MB[7].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR7         FR_0.MB[7].IDXR.R             /* Message Buffer Index Register */
#define FR_0_MBCCSR8         FR_0.MB[8].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR8         FR_0.MB[8].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR8         FR_0.MB[8].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR8         FR_0.MB[8].IDXR.R             /* Message Buffer Index Register */
#define FR_0_MBCCSR9         FR_0.MB[9].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR9         FR_0.MB[9].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR9         FR_0.MB[9].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR9         FR_0.MB[9].IDXR.R             /* Message Buffer Index Register */
#define FR_0_MBCCSR10        FR_0.MB[10].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR10        FR_0.MB[10].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR10        FR_0.MB[10].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR10        FR_0.MB[10].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR11        FR_0.MB[11].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR11        FR_0.MB[11].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR11        FR_0.MB[11].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR11        FR_0.MB[11].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR12        FR_0.MB[12].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR12        FR_0.MB[12].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR12        FR_0.MB[12].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR12        FR_0.MB[12].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR13        FR_0.MB[13].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR13        FR_0.MB[13].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR13        FR_0.MB[13].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR13        FR_0.MB[13].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR14        FR_0.MB[14].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR14        FR_0.MB[14].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR14        FR_0.MB[14].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR14        FR_0.MB[14].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR15        FR_0.MB[15].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR15        FR_0.MB[15].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR15        FR_0.MB[15].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR15        FR_0.MB[15].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR16        FR_0.MB[16].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR16        FR_0.MB[16].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR16        FR_0.MB[16].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR16        FR_0.MB[16].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR17        FR_0.MB[17].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR17        FR_0.MB[17].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR17        FR_0.MB[17].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR17        FR_0.MB[17].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR18        FR_0.MB[18].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR18        FR_0.MB[18].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR18        FR_0.MB[18].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR18        FR_0.MB[18].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR19        FR_0.MB[19].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR19        FR_0.MB[19].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR19        FR_0.MB[19].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR19        FR_0.MB[19].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR20        FR_0.MB[20].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR20        FR_0.MB[20].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR20        FR_0.MB[20].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR20        FR_0.MB[20].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR21        FR_0.MB[21].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR21        FR_0.MB[21].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR21        FR_0.MB[21].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR21        FR_0.MB[21].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR22        FR_0.MB[22].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR22        FR_0.MB[22].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR22        FR_0.MB[22].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR22        FR_0.MB[22].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR23        FR_0.MB[23].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR23        FR_0.MB[23].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR23        FR_0.MB[23].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR23        FR_0.MB[23].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR24        FR_0.MB[24].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR24        FR_0.MB[24].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR24        FR_0.MB[24].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR24        FR_0.MB[24].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR25        FR_0.MB[25].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR25        FR_0.MB[25].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR25        FR_0.MB[25].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR25        FR_0.MB[25].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR26        FR_0.MB[26].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR26        FR_0.MB[26].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR26        FR_0.MB[26].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR26        FR_0.MB[26].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR27        FR_0.MB[27].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR27        FR_0.MB[27].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR27        FR_0.MB[27].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR27        FR_0.MB[27].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR28        FR_0.MB[28].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR28        FR_0.MB[28].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR28        FR_0.MB[28].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR28        FR_0.MB[28].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR29        FR_0.MB[29].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR29        FR_0.MB[29].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR29        FR_0.MB[29].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR29        FR_0.MB[29].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR30        FR_0.MB[30].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR30        FR_0.MB[30].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR30        FR_0.MB[30].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR30        FR_0.MB[30].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR31        FR_0.MB[31].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR31        FR_0.MB[31].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR31        FR_0.MB[31].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR31        FR_0.MB[31].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR32        FR_0.MB[32].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR32        FR_0.MB[32].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR32        FR_0.MB[32].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR32        FR_0.MB[32].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR33        FR_0.MB[33].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR33        FR_0.MB[33].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR33        FR_0.MB[33].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR33        FR_0.MB[33].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR34        FR_0.MB[34].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR34        FR_0.MB[34].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR34        FR_0.MB[34].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR34        FR_0.MB[34].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR35        FR_0.MB[35].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR35        FR_0.MB[35].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR35        FR_0.MB[35].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR35        FR_0.MB[35].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR36        FR_0.MB[36].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR36        FR_0.MB[36].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR36        FR_0.MB[36].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR36        FR_0.MB[36].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR37        FR_0.MB[37].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR37        FR_0.MB[37].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR37        FR_0.MB[37].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR37        FR_0.MB[37].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR38        FR_0.MB[38].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR38        FR_0.MB[38].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR38        FR_0.MB[38].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR38        FR_0.MB[38].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR39        FR_0.MB[39].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR39        FR_0.MB[39].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR39        FR_0.MB[39].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR39        FR_0.MB[39].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR40        FR_0.MB[40].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR40        FR_0.MB[40].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR40        FR_0.MB[40].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR40        FR_0.MB[40].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR41        FR_0.MB[41].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR41        FR_0.MB[41].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR41        FR_0.MB[41].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR41        FR_0.MB[41].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR42        FR_0.MB[42].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR42        FR_0.MB[42].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR42        FR_0.MB[42].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR42        FR_0.MB[42].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR43        FR_0.MB[43].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR43        FR_0.MB[43].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR43        FR_0.MB[43].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR43        FR_0.MB[43].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR44        FR_0.MB[44].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR44        FR_0.MB[44].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR44        FR_0.MB[44].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR44        FR_0.MB[44].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR45        FR_0.MB[45].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR45        FR_0.MB[45].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR45        FR_0.MB[45].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR45        FR_0.MB[45].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR46        FR_0.MB[46].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR46        FR_0.MB[46].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR46        FR_0.MB[46].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR46        FR_0.MB[46].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR47        FR_0.MB[47].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR47        FR_0.MB[47].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR47        FR_0.MB[47].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR47        FR_0.MB[47].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR48        FR_0.MB[48].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR48        FR_0.MB[48].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR48        FR_0.MB[48].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR48        FR_0.MB[48].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR49        FR_0.MB[49].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR49        FR_0.MB[49].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR49        FR_0.MB[49].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR49        FR_0.MB[49].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR50        FR_0.MB[50].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR50        FR_0.MB[50].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR50        FR_0.MB[50].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR50        FR_0.MB[50].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR51        FR_0.MB[51].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR51        FR_0.MB[51].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR51        FR_0.MB[51].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR51        FR_0.MB[51].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR52        FR_0.MB[52].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR52        FR_0.MB[52].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR52        FR_0.MB[52].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR52        FR_0.MB[52].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR53        FR_0.MB[53].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR53        FR_0.MB[53].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR53        FR_0.MB[53].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR53        FR_0.MB[53].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR54        FR_0.MB[54].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR54        FR_0.MB[54].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR54        FR_0.MB[54].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR54        FR_0.MB[54].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR55        FR_0.MB[55].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR55        FR_0.MB[55].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR55        FR_0.MB[55].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR55        FR_0.MB[55].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR56        FR_0.MB[56].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR56        FR_0.MB[56].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR56        FR_0.MB[56].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR56        FR_0.MB[56].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR57        FR_0.MB[57].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR57        FR_0.MB[57].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR57        FR_0.MB[57].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR57        FR_0.MB[57].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR58        FR_0.MB[58].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR58        FR_0.MB[58].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR58        FR_0.MB[58].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR58        FR_0.MB[58].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR59        FR_0.MB[59].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR59        FR_0.MB[59].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR59        FR_0.MB[59].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR59        FR_0.MB[59].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR60        FR_0.MB[60].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR60        FR_0.MB[60].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR60        FR_0.MB[60].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR60        FR_0.MB[60].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR61        FR_0.MB[61].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR61        FR_0.MB[61].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR61        FR_0.MB[61].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR61        FR_0.MB[61].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR62        FR_0.MB[62].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR62        FR_0.MB[62].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR62        FR_0.MB[62].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR62        FR_0.MB[62].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR63        FR_0.MB[63].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR63        FR_0.MB[63].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR63        FR_0.MB[63].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR63        FR_0.MB[63].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR64        FR_0.MB[64].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR64        FR_0.MB[64].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR64        FR_0.MB[64].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR64        FR_0.MB[64].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR65        FR_0.MB[65].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR65        FR_0.MB[65].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR65        FR_0.MB[65].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR65        FR_0.MB[65].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR66        FR_0.MB[66].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR66        FR_0.MB[66].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR66        FR_0.MB[66].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR66        FR_0.MB[66].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR67        FR_0.MB[67].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR67        FR_0.MB[67].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR67        FR_0.MB[67].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR67        FR_0.MB[67].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR68        FR_0.MB[68].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR68        FR_0.MB[68].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR68        FR_0.MB[68].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR68        FR_0.MB[68].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR69        FR_0.MB[69].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR69        FR_0.MB[69].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR69        FR_0.MB[69].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR69        FR_0.MB[69].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR70        FR_0.MB[70].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR70        FR_0.MB[70].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR70        FR_0.MB[70].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR70        FR_0.MB[70].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR71        FR_0.MB[71].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR71        FR_0.MB[71].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR71        FR_0.MB[71].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR71        FR_0.MB[71].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR72        FR_0.MB[72].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR72        FR_0.MB[72].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR72        FR_0.MB[72].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR72        FR_0.MB[72].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR73        FR_0.MB[73].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR73        FR_0.MB[73].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR73        FR_0.MB[73].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR73        FR_0.MB[73].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR74        FR_0.MB[74].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR74        FR_0.MB[74].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR74        FR_0.MB[74].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR74        FR_0.MB[74].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR75        FR_0.MB[75].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR75        FR_0.MB[75].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR75        FR_0.MB[75].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR75        FR_0.MB[75].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR76        FR_0.MB[76].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR76        FR_0.MB[76].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR76        FR_0.MB[76].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR76        FR_0.MB[76].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR77        FR_0.MB[77].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR77        FR_0.MB[77].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR77        FR_0.MB[77].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR77        FR_0.MB[77].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR78        FR_0.MB[78].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR78        FR_0.MB[78].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR78        FR_0.MB[78].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR78        FR_0.MB[78].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR79        FR_0.MB[79].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR79        FR_0.MB[79].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR79        FR_0.MB[79].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR79        FR_0.MB[79].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR80        FR_0.MB[80].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR80        FR_0.MB[80].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR80        FR_0.MB[80].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR80        FR_0.MB[80].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR81        FR_0.MB[81].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR81        FR_0.MB[81].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR81        FR_0.MB[81].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR81        FR_0.MB[81].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR82        FR_0.MB[82].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR82        FR_0.MB[82].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR82        FR_0.MB[82].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR82        FR_0.MB[82].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR83        FR_0.MB[83].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR83        FR_0.MB[83].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR83        FR_0.MB[83].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR83        FR_0.MB[83].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR84        FR_0.MB[84].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR84        FR_0.MB[84].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR84        FR_0.MB[84].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR84        FR_0.MB[84].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR85        FR_0.MB[85].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR85        FR_0.MB[85].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR85        FR_0.MB[85].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR85        FR_0.MB[85].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR86        FR_0.MB[86].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR86        FR_0.MB[86].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR86        FR_0.MB[86].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR86        FR_0.MB[86].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR87        FR_0.MB[87].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR87        FR_0.MB[87].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR87        FR_0.MB[87].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR87        FR_0.MB[87].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR88        FR_0.MB[88].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR88        FR_0.MB[88].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR88        FR_0.MB[88].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR88        FR_0.MB[88].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR89        FR_0.MB[89].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR89        FR_0.MB[89].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR89        FR_0.MB[89].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR89        FR_0.MB[89].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR90        FR_0.MB[90].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR90        FR_0.MB[90].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR90        FR_0.MB[90].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR90        FR_0.MB[90].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR91        FR_0.MB[91].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR91        FR_0.MB[91].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR91        FR_0.MB[91].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR91        FR_0.MB[91].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR92        FR_0.MB[92].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR92        FR_0.MB[92].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR92        FR_0.MB[92].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR92        FR_0.MB[92].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR93        FR_0.MB[93].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR93        FR_0.MB[93].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR93        FR_0.MB[93].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR93        FR_0.MB[93].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR94        FR_0.MB[94].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR94        FR_0.MB[94].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR94        FR_0.MB[94].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR94        FR_0.MB[94].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR95        FR_0.MB[95].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR95        FR_0.MB[95].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR95        FR_0.MB[95].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR95        FR_0.MB[95].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR96        FR_0.MB[96].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR96        FR_0.MB[96].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR96        FR_0.MB[96].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR96        FR_0.MB[96].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR97        FR_0.MB[97].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR97        FR_0.MB[97].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR97        FR_0.MB[97].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR97        FR_0.MB[97].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR98        FR_0.MB[98].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR98        FR_0.MB[98].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR98        FR_0.MB[98].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR98        FR_0.MB[98].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR99        FR_0.MB[99].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR99        FR_0.MB[99].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR99        FR_0.MB[99].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR99        FR_0.MB[99].IDXR.R            /* Message Buffer Index Register */
#define FR_0_MBCCSR100       FR_0.MB[100].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR100       FR_0.MB[100].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR100       FR_0.MB[100].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR100       FR_0.MB[100].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR101       FR_0.MB[101].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR101       FR_0.MB[101].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR101       FR_0.MB[101].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR101       FR_0.MB[101].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR102       FR_0.MB[102].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR102       FR_0.MB[102].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR102       FR_0.MB[102].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR102       FR_0.MB[102].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR103       FR_0.MB[103].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR103       FR_0.MB[103].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR103       FR_0.MB[103].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR103       FR_0.MB[103].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR104       FR_0.MB[104].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR104       FR_0.MB[104].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR104       FR_0.MB[104].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR104       FR_0.MB[104].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR105       FR_0.MB[105].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR105       FR_0.MB[105].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR105       FR_0.MB[105].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR105       FR_0.MB[105].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR106       FR_0.MB[106].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR106       FR_0.MB[106].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR106       FR_0.MB[106].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR106       FR_0.MB[106].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR107       FR_0.MB[107].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR107       FR_0.MB[107].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR107       FR_0.MB[107].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR107       FR_0.MB[107].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR108       FR_0.MB[108].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR108       FR_0.MB[108].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR108       FR_0.MB[108].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR108       FR_0.MB[108].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR109       FR_0.MB[109].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR109       FR_0.MB[109].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR109       FR_0.MB[109].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR109       FR_0.MB[109].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR110       FR_0.MB[110].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR110       FR_0.MB[110].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR110       FR_0.MB[110].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR110       FR_0.MB[110].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR111       FR_0.MB[111].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR111       FR_0.MB[111].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR111       FR_0.MB[111].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR111       FR_0.MB[111].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR112       FR_0.MB[112].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR112       FR_0.MB[112].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR112       FR_0.MB[112].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR112       FR_0.MB[112].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR113       FR_0.MB[113].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR113       FR_0.MB[113].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR113       FR_0.MB[113].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR113       FR_0.MB[113].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR114       FR_0.MB[114].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR114       FR_0.MB[114].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR114       FR_0.MB[114].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR114       FR_0.MB[114].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR115       FR_0.MB[115].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR115       FR_0.MB[115].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR115       FR_0.MB[115].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR115       FR_0.MB[115].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR116       FR_0.MB[116].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR116       FR_0.MB[116].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR116       FR_0.MB[116].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR116       FR_0.MB[116].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR117       FR_0.MB[117].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR117       FR_0.MB[117].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR117       FR_0.MB[117].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR117       FR_0.MB[117].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR118       FR_0.MB[118].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR118       FR_0.MB[118].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR118       FR_0.MB[118].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR118       FR_0.MB[118].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR119       FR_0.MB[119].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR119       FR_0.MB[119].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR119       FR_0.MB[119].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR119       FR_0.MB[119].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR120       FR_0.MB[120].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR120       FR_0.MB[120].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR120       FR_0.MB[120].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR120       FR_0.MB[120].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR121       FR_0.MB[121].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR121       FR_0.MB[121].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR121       FR_0.MB[121].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR121       FR_0.MB[121].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR122       FR_0.MB[122].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR122       FR_0.MB[122].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR122       FR_0.MB[122].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR122       FR_0.MB[122].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR123       FR_0.MB[123].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR123       FR_0.MB[123].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR123       FR_0.MB[123].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR123       FR_0.MB[123].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR124       FR_0.MB[124].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR124       FR_0.MB[124].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR124       FR_0.MB[124].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR124       FR_0.MB[124].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR125       FR_0.MB[125].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR125       FR_0.MB[125].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR125       FR_0.MB[125].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR125       FR_0.MB[125].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR126       FR_0.MB[126].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR126       FR_0.MB[126].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR126       FR_0.MB[126].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR126       FR_0.MB[126].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBCCSR127       FR_0.MB[127].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_0_MBCCFR127       FR_0.MB[127].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_0_MBFIDR127       FR_0.MB[127].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_0_MBIDXR127       FR_0.MB[127].IDXR.R           /* Message Buffer Index Register */
#define FR_0_MBDOR0          FR_0.MBDOR[0].R               /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR1          FR_0.MBDOR[1].R               /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR2          FR_0.MBDOR[2].R               /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR3          FR_0.MBDOR[3].R               /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR4          FR_0.MBDOR[4].R               /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR5          FR_0.MBDOR[5].R               /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR6          FR_0.MBDOR[6].R               /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR7          FR_0.MBDOR[7].R               /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR8          FR_0.MBDOR[8].R               /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR9          FR_0.MBDOR[9].R               /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR10         FR_0.MBDOR[10].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR11         FR_0.MBDOR[11].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR12         FR_0.MBDOR[12].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR13         FR_0.MBDOR[13].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR14         FR_0.MBDOR[14].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR15         FR_0.MBDOR[15].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR16         FR_0.MBDOR[16].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR17         FR_0.MBDOR[17].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR18         FR_0.MBDOR[18].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR19         FR_0.MBDOR[19].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR20         FR_0.MBDOR[20].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR21         FR_0.MBDOR[21].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR22         FR_0.MBDOR[22].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR23         FR_0.MBDOR[23].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR24         FR_0.MBDOR[24].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR25         FR_0.MBDOR[25].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR26         FR_0.MBDOR[26].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR27         FR_0.MBDOR[27].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR28         FR_0.MBDOR[28].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR29         FR_0.MBDOR[29].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR30         FR_0.MBDOR[30].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR31         FR_0.MBDOR[31].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR32         FR_0.MBDOR[32].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR33         FR_0.MBDOR[33].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR34         FR_0.MBDOR[34].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR35         FR_0.MBDOR[35].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR36         FR_0.MBDOR[36].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR37         FR_0.MBDOR[37].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR38         FR_0.MBDOR[38].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR39         FR_0.MBDOR[39].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR40         FR_0.MBDOR[40].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR41         FR_0.MBDOR[41].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR42         FR_0.MBDOR[42].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR43         FR_0.MBDOR[43].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR44         FR_0.MBDOR[44].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR45         FR_0.MBDOR[45].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR46         FR_0.MBDOR[46].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR47         FR_0.MBDOR[47].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR48         FR_0.MBDOR[48].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR49         FR_0.MBDOR[49].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR50         FR_0.MBDOR[50].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR51         FR_0.MBDOR[51].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR52         FR_0.MBDOR[52].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR53         FR_0.MBDOR[53].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR54         FR_0.MBDOR[54].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR55         FR_0.MBDOR[55].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR56         FR_0.MBDOR[56].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR57         FR_0.MBDOR[57].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR58         FR_0.MBDOR[58].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR59         FR_0.MBDOR[59].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR60         FR_0.MBDOR[60].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR61         FR_0.MBDOR[61].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR62         FR_0.MBDOR[62].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR63         FR_0.MBDOR[63].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR64         FR_0.MBDOR[64].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR65         FR_0.MBDOR[65].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR66         FR_0.MBDOR[66].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR67         FR_0.MBDOR[67].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR68         FR_0.MBDOR[68].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR69         FR_0.MBDOR[69].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR70         FR_0.MBDOR[70].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR71         FR_0.MBDOR[71].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR72         FR_0.MBDOR[72].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR73         FR_0.MBDOR[73].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR74         FR_0.MBDOR[74].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR75         FR_0.MBDOR[75].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR76         FR_0.MBDOR[76].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR77         FR_0.MBDOR[77].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR78         FR_0.MBDOR[78].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR79         FR_0.MBDOR[79].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR80         FR_0.MBDOR[80].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR81         FR_0.MBDOR[81].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR82         FR_0.MBDOR[82].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR83         FR_0.MBDOR[83].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR84         FR_0.MBDOR[84].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR85         FR_0.MBDOR[85].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR86         FR_0.MBDOR[86].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR87         FR_0.MBDOR[87].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR88         FR_0.MBDOR[88].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR89         FR_0.MBDOR[89].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR90         FR_0.MBDOR[90].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR91         FR_0.MBDOR[91].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR92         FR_0.MBDOR[92].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR93         FR_0.MBDOR[93].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR94         FR_0.MBDOR[94].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR95         FR_0.MBDOR[95].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR96         FR_0.MBDOR[96].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR97         FR_0.MBDOR[97].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR98         FR_0.MBDOR[98].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR99         FR_0.MBDOR[99].R              /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR100        FR_0.MBDOR[100].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR101        FR_0.MBDOR[101].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR102        FR_0.MBDOR[102].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR103        FR_0.MBDOR[103].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR104        FR_0.MBDOR[104].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR105        FR_0.MBDOR[105].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR106        FR_0.MBDOR[106].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR107        FR_0.MBDOR[107].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR108        FR_0.MBDOR[108].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR109        FR_0.MBDOR[109].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR110        FR_0.MBDOR[110].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR111        FR_0.MBDOR[111].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR112        FR_0.MBDOR[112].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR113        FR_0.MBDOR[113].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR114        FR_0.MBDOR[114].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR115        FR_0.MBDOR[115].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR116        FR_0.MBDOR[116].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR117        FR_0.MBDOR[117].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR118        FR_0.MBDOR[118].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR119        FR_0.MBDOR[119].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR120        FR_0.MBDOR[120].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR121        FR_0.MBDOR[121].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR122        FR_0.MBDOR[122].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR123        FR_0.MBDOR[123].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR124        FR_0.MBDOR[124].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR125        FR_0.MBDOR[125].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR126        FR_0.MBDOR[126].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR127        FR_0.MBDOR[127].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR128        FR_0.MBDOR[128].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR129        FR_0.MBDOR[129].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR130        FR_0.MBDOR[130].R             /* Message Buffer Data Field Offset Register */
#define FR_0_MBDOR131        FR_0.MBDOR[131].R             /* Message Buffer Data Field Offset Register */
#define FR_0_LEETR0          FR_0.LEETR[0].R               /* LRAM ECC Error Test Register */
#define FR_0_LEETR1          FR_0.LEETR[1].R               /* LRAM ECC Error Test Register */
#define FR_0_LEETR2          FR_0.LEETR[2].R               /* LRAM ECC Error Test Register */
#define FR_0_LEETR3          FR_0.LEETR[3].R               /* LRAM ECC Error Test Register */
#define FR_0_LEETR4          FR_0.LEETR[4].R               /* LRAM ECC Error Test Register */
#define FR_0_LEETR5          FR_0.LEETR[5].R               /* LRAM ECC Error Test Register */

/* FR */
#define FR_1_MVR             FR_1.MVR.R                    /* Module Version Register */
#define FR_1_MCR             FR_1.MCR.R                    /* Module Configuration Register */
#define FR_1_SYMBADHR        FR_1.SYMBADHR.R               /* System Memory Base Address High Register */
#define FR_1_SYMBADLR        FR_1.SYMBADLR.R               /* System Memory Base Address Low Register */
#define FR_1_STBSCR          FR_1.STBSCR.R                 /* Strobe Signal Control Register */
#define FR_1_MBDSR           FR_1.MBDSR.R                  /* Message Buffer Data Size Register */
#define FR_1_MBSSUTR         FR_1.MBSSUTR.R                /* Message Buffer Segment Size and Utilization Register */
#define FR_1_PEDRAR          FR_1.PEDRAR.R                 /* PE DRAM Access Register */
#define FR_1_PEDRDR          FR_1.PEDRDR.R                 /* PE DRAM Data Register */
#define FR_1_POCR            FR_1.POCR.R                   /* Protocol Operation Control Register */
#define FR_1_GIFER           FR_1.GIFER.R                  /* Global Interrupt Flag and Enable Register */
#define FR_1_PIFR0           FR_1.PIFR0.R                  /* Protocol Interrupt Flag Register 0 */
#define FR_1_PIFR1           FR_1.PIFR1.R                  /* Protocol Interrupt Flag Register 1 */
#define FR_1_PIER0           FR_1.PIER0.R                  /* Protocol Interrupt Enable Register 0 */
#define FR_1_PIER1           FR_1.PIER1.R                  /* Protocol Interrupt Enable Register 1 */
#define FR_1_CHIERFR         FR_1.CHIERFR.R                /* CHI Error Flag Register */
#define FR_1_MBIVEC          FR_1.MBIVEC.R                 /* Message Buffer Interrupt Vector Register */
#define FR_1_CASERCR         FR_1.CASERCR.R                /* Channel A Status Error Counter Register */
#define FR_1_CBSERCR         FR_1.CBSERCR.R                /* Channel B Status Error Counter Register */
#define FR_1_PSR0            FR_1.PSR0.R                   /* Protocol Status Register 0 */
#define FR_1_PSR1            FR_1.PSR1.R                   /* Protocol Status Register 1 */
#define FR_1_PSR2            FR_1.PSR2.R                   /* Protocol Status Register 2 */
#define FR_1_PSR3            FR_1.PSR3.R                   /* Protocol Status Register 3 */
#define FR_1_MTCTR           FR_1.MTCTR.R                  /* Macrotick Counter Register */
#define FR_1_CYCTR           FR_1.CYCTR.R                  /* Cycle Counter Register */
#define FR_1_SLTCTAR         FR_1.SLTCTAR.R                /* Slot Counter Channel A Register */
#define FR_1_SLTCTBR         FR_1.SLTCTBR.R                /* Slot Counter Channel B Register */
#define FR_1_RTCORVR         FR_1.RTCORVR.R                /* Rate Correction Value Register */
#define FR_1_OFCORVR         FR_1.OFCORVR.R                /* Offset Correction Value Register */
#define FR_1_CIFR            FR_1.CIFR.R                   /* Combined Interrupt Flag Register */
#define FR_1_SYMATOR         FR_1.SYMATOR.R                /* System Memory Access Time-Out Register */
#define FR_1_SFCNTR          FR_1.SFCNTR.R                 /* Sync Frame Counter Register */
#define FR_1_SFTOR           FR_1.SFTOR.R                  /* Sync Frame Table Offset Register */
#define FR_1_SFTCCSR         FR_1.SFTCCSR.R                /* Sync Frame Table Configuration, Control, Status Register */
#define FR_1_SFIDRFR         FR_1.SFIDRFR.R                /* Sync Frame ID Rejection Filter Register */
#define FR_1_SFIDAFVR        FR_1.SFIDAFVR.R               /* Sync Frame ID Acceptance Filter Value Register */
#define FR_1_SFIDAFMR        FR_1.SFIDAFMR.R               /* Sync Frame ID Acceptance Filter Mask Register */
#define FR_1_NMVR0           FR_1.NMVR[0].R                /* Network Management Vector Register */
#define FR_1_NMVR1           FR_1.NMVR[1].R                /* Network Management Vector Register */
#define FR_1_NMVR2           FR_1.NMVR[2].R                /* Network Management Vector Register */
#define FR_1_NMVR3           FR_1.NMVR[3].R                /* Network Management Vector Register */
#define FR_1_NMVR4           FR_1.NMVR[4].R                /* Network Management Vector Register */
#define FR_1_NMVR5           FR_1.NMVR[5].R                /* Network Management Vector Register */
#define FR_1_NMVLR           FR_1.NMVLR.R                  /* Network Management Vector Length Register */
#define FR_1_TICCR           FR_1.TICCR.R                  /* Timer Configuration and Control Register */
#define FR_1_TI1CYSR         FR_1.TI1CYSR.R                /* Timer 1 Cycle Set Register */
#define FR_1_TI1MTOR         FR_1.TI1MTOR.R                /* Timer 1 Macrotick Offset Register */
#define FR_1_TI2CR0_ABS      FR_1.TI2CR0.ABS.R             /* Timer 2 Configuration Register 0 (Absolute Timer Configuration) */
#define FR_1_TI2CR0_REL      FR_1.TI2CR0.REL.R             /* Timer 2 Configuration Register 0 (Relative Timer Configuration) */
#define FR_1_TI2CR1_ABS      FR_1.TI2CR1.ABS.R             /* Timer 2 Configuration Register 1 (Absolute Timer Configuration) */
#define FR_1_TI2CR1_REL      FR_1.TI2CR1.REL.R             /* Timer 2 Configuration Register 1 (Relative Timer Configuration) */
#define FR_1_SSSR            FR_1.SSSR.R                   /* Slot Status Selection Register */
#define FR_1_SSCCR           FR_1.SSCCR.R                  /* Slot Status Counter Condition Register */
#define FR_1_SSR0            FR_1.SSR[0].R                 /* Slot Status Register */
#define FR_1_SSR1            FR_1.SSR[1].R                 /* Slot Status Register */
#define FR_1_SSR2            FR_1.SSR[2].R                 /* Slot Status Register */
#define FR_1_SSR3            FR_1.SSR[3].R                 /* Slot Status Register */
#define FR_1_SSR4            FR_1.SSR[4].R                 /* Slot Status Register */
#define FR_1_SSR5            FR_1.SSR[5].R                 /* Slot Status Register */
#define FR_1_SSR6            FR_1.SSR[6].R                 /* Slot Status Register */
#define FR_1_SSR7            FR_1.SSR[7].R                 /* Slot Status Register */
#define FR_1_SSCR0           FR_1.SSCR[0].R                /* Slot Status Counter Register */
#define FR_1_SSCR1           FR_1.SSCR[1].R                /* Slot Status Counter Register */
#define FR_1_SSCR2           FR_1.SSCR[2].R                /* Slot Status Counter Register */
#define FR_1_SSCR3           FR_1.SSCR[3].R                /* Slot Status Counter Register */
#define FR_1_MTSACFR         FR_1.MTSACFR.R                /* MTS A Configuration Register */
#define FR_1_MTSBCFR         FR_1.MTSBCFR.R                /* MTS B Configuration Register */
#define FR_1_RSBIR           FR_1.RSBIR.R                  /* Receive Shadow Buffer Index Register */
#define FR_1_RFWMSR          FR_1.RFWMSR.R                 /* Receive FIFO Watermark and Selection Register */
#define FR_1_RFSIR           FR_1.RFSIR.R                  /* Receive FIFO Start Index Register */
#define FR_1_RFDSR           FR_1.RFDSR.R                  /* Receive FIFO Depth and Size Register */
#define FR_1_RFARIR          FR_1.RFARIR.R                 /* Receive FIFO A Read Index Register */
#define FR_1_RFBRIR          FR_1.RFBRIR.R                 /* Receive FIFO B Read Index Register */
#define FR_1_RFMIDAFVR       FR_1.RFMIDAFVR.R              /* Receive FIFO Message ID Acceptance Filter Value Register */
#define FR_1_RFMIDAFMR       FR_1.RFMIDAFMR.R              /* Receive FIFO Message ID Acceptance Filter Mask Register */
#define FR_1_RFFIDRFVR       FR_1.RFFIDRFVR.R              /* Receive FIFO Frame ID Rejection Filter Value Register */
#define FR_1_RFFIDRFMR       FR_1.RFFIDRFMR.R              /* Receive FIFO Frame ID Rejection Filter Mask Register */
#define FR_1_RFRFCFR         FR_1.RFRFCFR.R                /* Receive FIFO Range Filter Configuration Register */
#define FR_1_RFRFCTR         FR_1.RFRFCTR.R                /* Receive FIFO Range Filter Control Register */
#define FR_1_LDTXSLAR        FR_1.LDTXSLAR.R               /* Last Dynamic Transmit Slot Channel A Register */
#define FR_1_LDTXSLBR        FR_1.LDTXSLBR.R               /* Last Dynamic Transmit Slot Channel B Register */
#define FR_1_PCR0            FR_1.PCR0.R                   /* Protocol Configuration Register 0 */
#define FR_1_PCR1            FR_1.PCR1.R                   /* Protocol Configuration Register 1 */
#define FR_1_PCR2            FR_1.PCR2.R                   /* Protocol Configuration Register 2 */
#define FR_1_PCR3            FR_1.PCR3.R                   /* Protocol Configuration Register 3 */
#define FR_1_PCR4            FR_1.PCR4.R                   /* Protocol Configuration Register 4 */
#define FR_1_PCR5            FR_1.PCR5.R                   /* Protocol Configuration Register 5 */
#define FR_1_PCR6            FR_1.PCR6.R                   /* Protocol Configuration Register 6 */
#define FR_1_PCR7            FR_1.PCR7.R                   /* Protocol Configuration Register 7 */
#define FR_1_PCR8            FR_1.PCR8.R                   /* Protocol Configuration Register 8 */
#define FR_1_PCR9            FR_1.PCR9.R                   /* Protocol Configuration Register 9 */
#define FR_1_PCR10           FR_1.PCR10.R                  /* Protocol Configuration Register 10 */
#define FR_1_PCR11           FR_1.PCR11.R                  /* Protocol Configuration Register 11 */
#define FR_1_PCR12           FR_1.PCR12.R                  /* Protocol Configuration Register 12 */
#define FR_1_PCR13           FR_1.PCR13.R                  /* Protocol Configuration Register 13 */
#define FR_1_PCR14           FR_1.PCR14.R                  /* Protocol Configuration Register 14 */
#define FR_1_PCR15           FR_1.PCR15.R                  /* Protocol Configuration Register 15 */
#define FR_1_PCR16           FR_1.PCR16.R                  /* Protocol Configuration Register 16 */
#define FR_1_PCR17           FR_1.PCR17.R                  /* Protocol Configuration Register 17 */
#define FR_1_PCR18           FR_1.PCR18.R                  /* Protocol Configuration Register 18 */
#define FR_1_PCR19           FR_1.PCR19.R                  /* Protocol Configuration Register 19 */
#define FR_1_PCR20           FR_1.PCR20.R                  /* Protocol Configuration Register 20 */
#define FR_1_PCR21           FR_1.PCR21.R                  /* Protocol Configuration Register 21 */
#define FR_1_PCR22           FR_1.PCR22.R                  /* Protocol Configuration Register 22 */
#define FR_1_PCR23           FR_1.PCR23.R                  /* Protocol Configuration Register 23 */
#define FR_1_PCR24           FR_1.PCR24.R                  /* Protocol Configuration Register 24 */
#define FR_1_PCR25           FR_1.PCR25.R                  /* Protocol Configuration Register 25 */
#define FR_1_PCR26           FR_1.PCR26.R                  /* Protocol Configuration Register 26 */
#define FR_1_PCR27           FR_1.PCR27.R                  /* Protocol Configuration Register 27 */
#define FR_1_PCR28           FR_1.PCR28.R                  /* Protocol Configuration Register 28 */
#define FR_1_PCR29           FR_1.PCR29.R                  /* Protocol Configuration Register 29 */
#define FR_1_PCR30           FR_1.PCR30.R                  /* Protocol Configuration Register 30 */
#define FR_1_STPWR           FR_1.STPWR.R                  /* StopWatch Count Register */
#define FR_1_PEOER           FR_1.PEOER.R                  /* Protocol Event Output Enable and StopWatch Control Register */
#define FR_1_RFSDOR          FR_1.RFSDOR.R                 /* Receive FIFO Start Data Offset Register */
#define FR_1_RFSYMBADHR      FR_1.RFSYMBADHR.R             /* Receive FIFO System Memory Base Address High Register */
#define FR_1_RFSYMBADLR      FR_1.RFSYMBADLR.R             /* Receive FIFO System Memory Base Address Low Register */
#define FR_1_RFPTR           FR_1.RFPTR.R                  /* Receive FIFO Periodic Timer Register */
#define FR_1_RFFLPCR         FR_1.RFFLPCR.R                /* Receive FIFO Fill Level and POP Count Register */
#define FR_1_EEIFER          FR_1.EEIFER.R                 /* ECC Error Interrupt Flag and Enable Register */
#define FR_1_EERICR          FR_1.EERICR.R                 /* ECC Error Report and Injection Control Register */
#define FR_1_EERAR           FR_1.EERAR.R                  /* ECC Error Report Address Register */
#define FR_1_EERDR           FR_1.EERDR.R                  /* ECC Error Report Data Register */
#define FR_1_EERCR           FR_1.EERCR.R                  /* ECC Error Report Code Register */
#define FR_1_EEIAR           FR_1.EEIAR.R                  /* ECC Error Injection Address Register */
#define FR_1_EEIDR           FR_1.EEIDR.R                  /* ECC Error Injection Data Register */
#define FR_1_EEICR           FR_1.EEICR.R                  /* ECC Error Injection Code Register */
#define FR_1_MBCCSR0         FR_1.MB[0].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR0         FR_1.MB[0].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR0         FR_1.MB[0].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR0         FR_1.MB[0].IDXR.R             /* Message Buffer Index Register */
#define FR_1_MBCCSR1         FR_1.MB[1].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR1         FR_1.MB[1].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR1         FR_1.MB[1].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR1         FR_1.MB[1].IDXR.R             /* Message Buffer Index Register */
#define FR_1_MBCCSR2         FR_1.MB[2].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR2         FR_1.MB[2].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR2         FR_1.MB[2].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR2         FR_1.MB[2].IDXR.R             /* Message Buffer Index Register */
#define FR_1_MBCCSR3         FR_1.MB[3].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR3         FR_1.MB[3].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR3         FR_1.MB[3].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR3         FR_1.MB[3].IDXR.R             /* Message Buffer Index Register */
#define FR_1_MBCCSR4         FR_1.MB[4].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR4         FR_1.MB[4].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR4         FR_1.MB[4].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR4         FR_1.MB[4].IDXR.R             /* Message Buffer Index Register */
#define FR_1_MBCCSR5         FR_1.MB[5].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR5         FR_1.MB[5].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR5         FR_1.MB[5].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR5         FR_1.MB[5].IDXR.R             /* Message Buffer Index Register */
#define FR_1_MBCCSR6         FR_1.MB[6].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR6         FR_1.MB[6].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR6         FR_1.MB[6].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR6         FR_1.MB[6].IDXR.R             /* Message Buffer Index Register */
#define FR_1_MBCCSR7         FR_1.MB[7].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR7         FR_1.MB[7].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR7         FR_1.MB[7].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR7         FR_1.MB[7].IDXR.R             /* Message Buffer Index Register */
#define FR_1_MBCCSR8         FR_1.MB[8].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR8         FR_1.MB[8].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR8         FR_1.MB[8].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR8         FR_1.MB[8].IDXR.R             /* Message Buffer Index Register */
#define FR_1_MBCCSR9         FR_1.MB[9].CCSR.R             /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR9         FR_1.MB[9].CCFR.R             /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR9         FR_1.MB[9].FIDR.R             /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR9         FR_1.MB[9].IDXR.R             /* Message Buffer Index Register */
#define FR_1_MBCCSR10        FR_1.MB[10].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR10        FR_1.MB[10].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR10        FR_1.MB[10].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR10        FR_1.MB[10].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR11        FR_1.MB[11].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR11        FR_1.MB[11].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR11        FR_1.MB[11].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR11        FR_1.MB[11].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR12        FR_1.MB[12].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR12        FR_1.MB[12].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR12        FR_1.MB[12].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR12        FR_1.MB[12].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR13        FR_1.MB[13].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR13        FR_1.MB[13].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR13        FR_1.MB[13].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR13        FR_1.MB[13].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR14        FR_1.MB[14].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR14        FR_1.MB[14].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR14        FR_1.MB[14].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR14        FR_1.MB[14].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR15        FR_1.MB[15].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR15        FR_1.MB[15].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR15        FR_1.MB[15].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR15        FR_1.MB[15].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR16        FR_1.MB[16].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR16        FR_1.MB[16].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR16        FR_1.MB[16].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR16        FR_1.MB[16].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR17        FR_1.MB[17].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR17        FR_1.MB[17].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR17        FR_1.MB[17].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR17        FR_1.MB[17].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR18        FR_1.MB[18].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR18        FR_1.MB[18].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR18        FR_1.MB[18].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR18        FR_1.MB[18].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR19        FR_1.MB[19].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR19        FR_1.MB[19].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR19        FR_1.MB[19].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR19        FR_1.MB[19].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR20        FR_1.MB[20].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR20        FR_1.MB[20].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR20        FR_1.MB[20].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR20        FR_1.MB[20].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR21        FR_1.MB[21].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR21        FR_1.MB[21].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR21        FR_1.MB[21].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR21        FR_1.MB[21].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR22        FR_1.MB[22].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR22        FR_1.MB[22].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR22        FR_1.MB[22].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR22        FR_1.MB[22].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR23        FR_1.MB[23].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR23        FR_1.MB[23].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR23        FR_1.MB[23].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR23        FR_1.MB[23].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR24        FR_1.MB[24].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR24        FR_1.MB[24].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR24        FR_1.MB[24].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR24        FR_1.MB[24].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR25        FR_1.MB[25].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR25        FR_1.MB[25].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR25        FR_1.MB[25].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR25        FR_1.MB[25].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR26        FR_1.MB[26].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR26        FR_1.MB[26].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR26        FR_1.MB[26].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR26        FR_1.MB[26].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR27        FR_1.MB[27].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR27        FR_1.MB[27].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR27        FR_1.MB[27].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR27        FR_1.MB[27].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR28        FR_1.MB[28].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR28        FR_1.MB[28].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR28        FR_1.MB[28].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR28        FR_1.MB[28].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR29        FR_1.MB[29].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR29        FR_1.MB[29].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR29        FR_1.MB[29].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR29        FR_1.MB[29].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR30        FR_1.MB[30].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR30        FR_1.MB[30].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR30        FR_1.MB[30].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR30        FR_1.MB[30].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR31        FR_1.MB[31].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR31        FR_1.MB[31].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR31        FR_1.MB[31].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR31        FR_1.MB[31].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR32        FR_1.MB[32].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR32        FR_1.MB[32].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR32        FR_1.MB[32].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR32        FR_1.MB[32].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR33        FR_1.MB[33].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR33        FR_1.MB[33].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR33        FR_1.MB[33].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR33        FR_1.MB[33].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR34        FR_1.MB[34].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR34        FR_1.MB[34].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR34        FR_1.MB[34].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR34        FR_1.MB[34].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR35        FR_1.MB[35].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR35        FR_1.MB[35].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR35        FR_1.MB[35].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR35        FR_1.MB[35].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR36        FR_1.MB[36].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR36        FR_1.MB[36].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR36        FR_1.MB[36].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR36        FR_1.MB[36].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR37        FR_1.MB[37].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR37        FR_1.MB[37].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR37        FR_1.MB[37].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR37        FR_1.MB[37].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR38        FR_1.MB[38].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR38        FR_1.MB[38].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR38        FR_1.MB[38].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR38        FR_1.MB[38].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR39        FR_1.MB[39].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR39        FR_1.MB[39].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR39        FR_1.MB[39].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR39        FR_1.MB[39].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR40        FR_1.MB[40].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR40        FR_1.MB[40].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR40        FR_1.MB[40].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR40        FR_1.MB[40].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR41        FR_1.MB[41].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR41        FR_1.MB[41].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR41        FR_1.MB[41].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR41        FR_1.MB[41].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR42        FR_1.MB[42].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR42        FR_1.MB[42].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR42        FR_1.MB[42].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR42        FR_1.MB[42].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR43        FR_1.MB[43].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR43        FR_1.MB[43].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR43        FR_1.MB[43].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR43        FR_1.MB[43].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR44        FR_1.MB[44].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR44        FR_1.MB[44].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR44        FR_1.MB[44].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR44        FR_1.MB[44].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR45        FR_1.MB[45].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR45        FR_1.MB[45].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR45        FR_1.MB[45].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR45        FR_1.MB[45].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR46        FR_1.MB[46].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR46        FR_1.MB[46].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR46        FR_1.MB[46].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR46        FR_1.MB[46].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR47        FR_1.MB[47].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR47        FR_1.MB[47].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR47        FR_1.MB[47].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR47        FR_1.MB[47].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR48        FR_1.MB[48].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR48        FR_1.MB[48].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR48        FR_1.MB[48].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR48        FR_1.MB[48].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR49        FR_1.MB[49].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR49        FR_1.MB[49].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR49        FR_1.MB[49].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR49        FR_1.MB[49].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR50        FR_1.MB[50].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR50        FR_1.MB[50].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR50        FR_1.MB[50].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR50        FR_1.MB[50].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR51        FR_1.MB[51].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR51        FR_1.MB[51].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR51        FR_1.MB[51].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR51        FR_1.MB[51].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR52        FR_1.MB[52].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR52        FR_1.MB[52].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR52        FR_1.MB[52].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR52        FR_1.MB[52].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR53        FR_1.MB[53].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR53        FR_1.MB[53].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR53        FR_1.MB[53].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR53        FR_1.MB[53].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR54        FR_1.MB[54].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR54        FR_1.MB[54].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR54        FR_1.MB[54].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR54        FR_1.MB[54].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR55        FR_1.MB[55].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR55        FR_1.MB[55].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR55        FR_1.MB[55].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR55        FR_1.MB[55].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR56        FR_1.MB[56].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR56        FR_1.MB[56].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR56        FR_1.MB[56].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR56        FR_1.MB[56].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR57        FR_1.MB[57].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR57        FR_1.MB[57].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR57        FR_1.MB[57].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR57        FR_1.MB[57].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR58        FR_1.MB[58].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR58        FR_1.MB[58].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR58        FR_1.MB[58].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR58        FR_1.MB[58].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR59        FR_1.MB[59].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR59        FR_1.MB[59].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR59        FR_1.MB[59].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR59        FR_1.MB[59].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR60        FR_1.MB[60].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR60        FR_1.MB[60].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR60        FR_1.MB[60].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR60        FR_1.MB[60].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR61        FR_1.MB[61].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR61        FR_1.MB[61].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR61        FR_1.MB[61].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR61        FR_1.MB[61].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR62        FR_1.MB[62].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR62        FR_1.MB[62].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR62        FR_1.MB[62].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR62        FR_1.MB[62].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR63        FR_1.MB[63].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR63        FR_1.MB[63].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR63        FR_1.MB[63].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR63        FR_1.MB[63].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR64        FR_1.MB[64].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR64        FR_1.MB[64].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR64        FR_1.MB[64].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR64        FR_1.MB[64].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR65        FR_1.MB[65].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR65        FR_1.MB[65].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR65        FR_1.MB[65].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR65        FR_1.MB[65].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR66        FR_1.MB[66].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR66        FR_1.MB[66].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR66        FR_1.MB[66].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR66        FR_1.MB[66].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR67        FR_1.MB[67].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR67        FR_1.MB[67].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR67        FR_1.MB[67].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR67        FR_1.MB[67].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR68        FR_1.MB[68].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR68        FR_1.MB[68].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR68        FR_1.MB[68].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR68        FR_1.MB[68].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR69        FR_1.MB[69].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR69        FR_1.MB[69].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR69        FR_1.MB[69].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR69        FR_1.MB[69].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR70        FR_1.MB[70].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR70        FR_1.MB[70].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR70        FR_1.MB[70].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR70        FR_1.MB[70].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR71        FR_1.MB[71].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR71        FR_1.MB[71].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR71        FR_1.MB[71].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR71        FR_1.MB[71].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR72        FR_1.MB[72].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR72        FR_1.MB[72].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR72        FR_1.MB[72].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR72        FR_1.MB[72].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR73        FR_1.MB[73].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR73        FR_1.MB[73].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR73        FR_1.MB[73].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR73        FR_1.MB[73].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR74        FR_1.MB[74].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR74        FR_1.MB[74].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR74        FR_1.MB[74].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR74        FR_1.MB[74].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR75        FR_1.MB[75].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR75        FR_1.MB[75].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR75        FR_1.MB[75].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR75        FR_1.MB[75].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR76        FR_1.MB[76].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR76        FR_1.MB[76].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR76        FR_1.MB[76].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR76        FR_1.MB[76].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR77        FR_1.MB[77].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR77        FR_1.MB[77].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR77        FR_1.MB[77].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR77        FR_1.MB[77].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR78        FR_1.MB[78].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR78        FR_1.MB[78].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR78        FR_1.MB[78].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR78        FR_1.MB[78].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR79        FR_1.MB[79].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR79        FR_1.MB[79].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR79        FR_1.MB[79].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR79        FR_1.MB[79].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR80        FR_1.MB[80].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR80        FR_1.MB[80].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR80        FR_1.MB[80].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR80        FR_1.MB[80].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR81        FR_1.MB[81].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR81        FR_1.MB[81].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR81        FR_1.MB[81].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR81        FR_1.MB[81].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR82        FR_1.MB[82].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR82        FR_1.MB[82].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR82        FR_1.MB[82].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR82        FR_1.MB[82].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR83        FR_1.MB[83].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR83        FR_1.MB[83].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR83        FR_1.MB[83].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR83        FR_1.MB[83].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR84        FR_1.MB[84].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR84        FR_1.MB[84].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR84        FR_1.MB[84].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR84        FR_1.MB[84].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR85        FR_1.MB[85].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR85        FR_1.MB[85].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR85        FR_1.MB[85].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR85        FR_1.MB[85].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR86        FR_1.MB[86].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR86        FR_1.MB[86].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR86        FR_1.MB[86].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR86        FR_1.MB[86].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR87        FR_1.MB[87].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR87        FR_1.MB[87].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR87        FR_1.MB[87].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR87        FR_1.MB[87].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR88        FR_1.MB[88].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR88        FR_1.MB[88].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR88        FR_1.MB[88].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR88        FR_1.MB[88].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR89        FR_1.MB[89].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR89        FR_1.MB[89].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR89        FR_1.MB[89].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR89        FR_1.MB[89].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR90        FR_1.MB[90].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR90        FR_1.MB[90].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR90        FR_1.MB[90].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR90        FR_1.MB[90].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR91        FR_1.MB[91].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR91        FR_1.MB[91].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR91        FR_1.MB[91].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR91        FR_1.MB[91].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR92        FR_1.MB[92].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR92        FR_1.MB[92].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR92        FR_1.MB[92].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR92        FR_1.MB[92].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR93        FR_1.MB[93].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR93        FR_1.MB[93].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR93        FR_1.MB[93].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR93        FR_1.MB[93].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR94        FR_1.MB[94].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR94        FR_1.MB[94].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR94        FR_1.MB[94].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR94        FR_1.MB[94].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR95        FR_1.MB[95].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR95        FR_1.MB[95].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR95        FR_1.MB[95].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR95        FR_1.MB[95].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR96        FR_1.MB[96].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR96        FR_1.MB[96].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR96        FR_1.MB[96].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR96        FR_1.MB[96].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR97        FR_1.MB[97].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR97        FR_1.MB[97].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR97        FR_1.MB[97].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR97        FR_1.MB[97].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR98        FR_1.MB[98].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR98        FR_1.MB[98].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR98        FR_1.MB[98].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR98        FR_1.MB[98].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR99        FR_1.MB[99].CCSR.R            /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR99        FR_1.MB[99].CCFR.R            /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR99        FR_1.MB[99].FIDR.R            /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR99        FR_1.MB[99].IDXR.R            /* Message Buffer Index Register */
#define FR_1_MBCCSR100       FR_1.MB[100].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR100       FR_1.MB[100].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR100       FR_1.MB[100].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR100       FR_1.MB[100].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR101       FR_1.MB[101].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR101       FR_1.MB[101].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR101       FR_1.MB[101].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR101       FR_1.MB[101].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR102       FR_1.MB[102].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR102       FR_1.MB[102].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR102       FR_1.MB[102].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR102       FR_1.MB[102].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR103       FR_1.MB[103].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR103       FR_1.MB[103].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR103       FR_1.MB[103].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR103       FR_1.MB[103].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR104       FR_1.MB[104].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR104       FR_1.MB[104].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR104       FR_1.MB[104].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR104       FR_1.MB[104].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR105       FR_1.MB[105].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR105       FR_1.MB[105].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR105       FR_1.MB[105].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR105       FR_1.MB[105].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR106       FR_1.MB[106].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR106       FR_1.MB[106].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR106       FR_1.MB[106].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR106       FR_1.MB[106].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR107       FR_1.MB[107].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR107       FR_1.MB[107].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR107       FR_1.MB[107].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR107       FR_1.MB[107].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR108       FR_1.MB[108].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR108       FR_1.MB[108].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR108       FR_1.MB[108].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR108       FR_1.MB[108].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR109       FR_1.MB[109].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR109       FR_1.MB[109].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR109       FR_1.MB[109].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR109       FR_1.MB[109].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR110       FR_1.MB[110].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR110       FR_1.MB[110].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR110       FR_1.MB[110].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR110       FR_1.MB[110].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR111       FR_1.MB[111].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR111       FR_1.MB[111].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR111       FR_1.MB[111].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR111       FR_1.MB[111].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR112       FR_1.MB[112].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR112       FR_1.MB[112].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR112       FR_1.MB[112].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR112       FR_1.MB[112].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR113       FR_1.MB[113].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR113       FR_1.MB[113].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR113       FR_1.MB[113].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR113       FR_1.MB[113].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR114       FR_1.MB[114].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR114       FR_1.MB[114].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR114       FR_1.MB[114].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR114       FR_1.MB[114].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR115       FR_1.MB[115].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR115       FR_1.MB[115].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR115       FR_1.MB[115].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR115       FR_1.MB[115].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR116       FR_1.MB[116].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR116       FR_1.MB[116].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR116       FR_1.MB[116].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR116       FR_1.MB[116].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR117       FR_1.MB[117].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR117       FR_1.MB[117].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR117       FR_1.MB[117].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR117       FR_1.MB[117].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR118       FR_1.MB[118].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR118       FR_1.MB[118].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR118       FR_1.MB[118].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR118       FR_1.MB[118].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR119       FR_1.MB[119].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR119       FR_1.MB[119].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR119       FR_1.MB[119].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR119       FR_1.MB[119].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR120       FR_1.MB[120].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR120       FR_1.MB[120].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR120       FR_1.MB[120].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR120       FR_1.MB[120].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR121       FR_1.MB[121].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR121       FR_1.MB[121].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR121       FR_1.MB[121].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR121       FR_1.MB[121].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR122       FR_1.MB[122].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR122       FR_1.MB[122].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR122       FR_1.MB[122].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR122       FR_1.MB[122].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR123       FR_1.MB[123].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR123       FR_1.MB[123].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR123       FR_1.MB[123].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR123       FR_1.MB[123].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR124       FR_1.MB[124].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR124       FR_1.MB[124].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR124       FR_1.MB[124].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR124       FR_1.MB[124].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR125       FR_1.MB[125].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR125       FR_1.MB[125].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR125       FR_1.MB[125].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR125       FR_1.MB[125].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR126       FR_1.MB[126].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR126       FR_1.MB[126].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR126       FR_1.MB[126].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR126       FR_1.MB[126].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBCCSR127       FR_1.MB[127].CCSR.R           /* Message Buffer Configuration, Control, Status Register */
#define FR_1_MBCCFR127       FR_1.MB[127].CCFR.R           /* Message Buffer Cycle Counter Filter Register */
#define FR_1_MBFIDR127       FR_1.MB[127].FIDR.R           /* Message Buffer Frame ID Register */
#define FR_1_MBIDXR127       FR_1.MB[127].IDXR.R           /* Message Buffer Index Register */
#define FR_1_MBDOR0          FR_1.MBDOR[0].R               /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR1          FR_1.MBDOR[1].R               /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR2          FR_1.MBDOR[2].R               /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR3          FR_1.MBDOR[3].R               /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR4          FR_1.MBDOR[4].R               /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR5          FR_1.MBDOR[5].R               /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR6          FR_1.MBDOR[6].R               /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR7          FR_1.MBDOR[7].R               /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR8          FR_1.MBDOR[8].R               /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR9          FR_1.MBDOR[9].R               /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR10         FR_1.MBDOR[10].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR11         FR_1.MBDOR[11].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR12         FR_1.MBDOR[12].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR13         FR_1.MBDOR[13].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR14         FR_1.MBDOR[14].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR15         FR_1.MBDOR[15].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR16         FR_1.MBDOR[16].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR17         FR_1.MBDOR[17].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR18         FR_1.MBDOR[18].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR19         FR_1.MBDOR[19].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR20         FR_1.MBDOR[20].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR21         FR_1.MBDOR[21].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR22         FR_1.MBDOR[22].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR23         FR_1.MBDOR[23].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR24         FR_1.MBDOR[24].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR25         FR_1.MBDOR[25].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR26         FR_1.MBDOR[26].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR27         FR_1.MBDOR[27].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR28         FR_1.MBDOR[28].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR29         FR_1.MBDOR[29].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR30         FR_1.MBDOR[30].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR31         FR_1.MBDOR[31].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR32         FR_1.MBDOR[32].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR33         FR_1.MBDOR[33].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR34         FR_1.MBDOR[34].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR35         FR_1.MBDOR[35].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR36         FR_1.MBDOR[36].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR37         FR_1.MBDOR[37].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR38         FR_1.MBDOR[38].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR39         FR_1.MBDOR[39].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR40         FR_1.MBDOR[40].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR41         FR_1.MBDOR[41].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR42         FR_1.MBDOR[42].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR43         FR_1.MBDOR[43].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR44         FR_1.MBDOR[44].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR45         FR_1.MBDOR[45].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR46         FR_1.MBDOR[46].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR47         FR_1.MBDOR[47].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR48         FR_1.MBDOR[48].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR49         FR_1.MBDOR[49].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR50         FR_1.MBDOR[50].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR51         FR_1.MBDOR[51].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR52         FR_1.MBDOR[52].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR53         FR_1.MBDOR[53].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR54         FR_1.MBDOR[54].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR55         FR_1.MBDOR[55].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR56         FR_1.MBDOR[56].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR57         FR_1.MBDOR[57].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR58         FR_1.MBDOR[58].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR59         FR_1.MBDOR[59].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR60         FR_1.MBDOR[60].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR61         FR_1.MBDOR[61].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR62         FR_1.MBDOR[62].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR63         FR_1.MBDOR[63].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR64         FR_1.MBDOR[64].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR65         FR_1.MBDOR[65].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR66         FR_1.MBDOR[66].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR67         FR_1.MBDOR[67].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR68         FR_1.MBDOR[68].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR69         FR_1.MBDOR[69].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR70         FR_1.MBDOR[70].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR71         FR_1.MBDOR[71].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR72         FR_1.MBDOR[72].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR73         FR_1.MBDOR[73].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR74         FR_1.MBDOR[74].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR75         FR_1.MBDOR[75].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR76         FR_1.MBDOR[76].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR77         FR_1.MBDOR[77].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR78         FR_1.MBDOR[78].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR79         FR_1.MBDOR[79].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR80         FR_1.MBDOR[80].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR81         FR_1.MBDOR[81].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR82         FR_1.MBDOR[82].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR83         FR_1.MBDOR[83].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR84         FR_1.MBDOR[84].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR85         FR_1.MBDOR[85].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR86         FR_1.MBDOR[86].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR87         FR_1.MBDOR[87].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR88         FR_1.MBDOR[88].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR89         FR_1.MBDOR[89].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR90         FR_1.MBDOR[90].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR91         FR_1.MBDOR[91].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR92         FR_1.MBDOR[92].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR93         FR_1.MBDOR[93].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR94         FR_1.MBDOR[94].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR95         FR_1.MBDOR[95].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR96         FR_1.MBDOR[96].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR97         FR_1.MBDOR[97].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR98         FR_1.MBDOR[98].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR99         FR_1.MBDOR[99].R              /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR100        FR_1.MBDOR[100].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR101        FR_1.MBDOR[101].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR102        FR_1.MBDOR[102].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR103        FR_1.MBDOR[103].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR104        FR_1.MBDOR[104].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR105        FR_1.MBDOR[105].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR106        FR_1.MBDOR[106].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR107        FR_1.MBDOR[107].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR108        FR_1.MBDOR[108].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR109        FR_1.MBDOR[109].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR110        FR_1.MBDOR[110].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR111        FR_1.MBDOR[111].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR112        FR_1.MBDOR[112].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR113        FR_1.MBDOR[113].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR114        FR_1.MBDOR[114].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR115        FR_1.MBDOR[115].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR116        FR_1.MBDOR[116].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR117        FR_1.MBDOR[117].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR118        FR_1.MBDOR[118].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR119        FR_1.MBDOR[119].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR120        FR_1.MBDOR[120].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR121        FR_1.MBDOR[121].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR122        FR_1.MBDOR[122].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR123        FR_1.MBDOR[123].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR124        FR_1.MBDOR[124].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR125        FR_1.MBDOR[125].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR126        FR_1.MBDOR[126].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR127        FR_1.MBDOR[127].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR128        FR_1.MBDOR[128].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR129        FR_1.MBDOR[129].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR130        FR_1.MBDOR[130].R             /* Message Buffer Data Field Offset Register */
#define FR_1_MBDOR131        FR_1.MBDOR[131].R             /* Message Buffer Data Field Offset Register */
#define FR_1_LEETR0          FR_1.LEETR[0].R               /* LRAM ECC Error Test Register */
#define FR_1_LEETR1          FR_1.LEETR[1].R               /* LRAM ECC Error Test Register */
#define FR_1_LEETR2          FR_1.LEETR[2].R               /* LRAM ECC Error Test Register */
#define FR_1_LEETR3          FR_1.LEETR[3].R               /* LRAM ECC Error Test Register */
#define FR_1_LEETR4          FR_1.LEETR[4].R               /* LRAM ECC Error Test Register */
#define FR_1_LEETR5          FR_1.LEETR[5].R               /* LRAM ECC Error Test Register */

/* GTM */
#define GTM_REV              GTM.REV.R                     /* GTM Revision Register */
#define GTM_RST              GTM.RST.R                     /* GTM Reset Register */
#define GTM_CTRL             GTM.CTRL.R                    /* GTM Control Register */
#define GTM_AEI_ADDR_XPT     GTM.AEI_ADDR_XPT.R            /* GTM AEI Address Pointer Register */
#define GTM_IRQ_NOTIFY       GTM.IRQ_NOTIFY.R              /* GTM Interrupt Request Notification Register */
#define GTM_IRQ_EN           GTM.IRQ_EN.R                  /* GTM Interrupt Request Enable Register */
#define GTM_IRQ_FORCINT      GTM.IRQ_FORCINT.R             /* GTM Force Interrupt Request Register */
#define GTM_IRQ_MODE         GTM.IRQ_MODE.R                /* GTM Interrupt Request Mode Register */
#define GTM_EIRQ_EN          GTM.EIRQ_EN.R                 /* GTM Error Interrupt Request Enable register */
#define GTM_BRIDGE_MODE      GTM.BRIDGE_MODE.R             /* GTM Bridge Mode Register */
#define GTM_BRIDGE_PTR1      GTM.BRIDGE_PTR1.R             /* GTM Bridge Pointer 1 Register */
#define GTM_BRIDGE_PTR2      GTM.BRIDGE_PTR2.R             /* GTM Bridge Pointer 2 Register */
#define GTM_TIM0_AUX_IN_SRC  GTM.TIM0_AUX_IN_SRC.R         /* GTM TIM0 Auxiliary Input Source register */
#define GTM_TIM1_AUX_IN_SRC  GTM.TIM1_AUX_IN_SRC.R         /* GTM TIM1 Auxiliary Input Source register */
#define GTM_TIM2_AUX_IN_SRC  GTM.TIM2_AUX_IN_SRC.R         /* GTM TIM2 Auxiliary Input Source register */
#define GTM_TIM3_AUX_IN_SRC  GTM.TIM3_AUX_IN_SRC.R         /* GTM TIM3 Auxiliary Input Source register */
#define GTM_TIM4_AUX_IN_SRC  GTM.TIM4_AUX_IN_SRC.R         /* GTM TIM4 Auxiliary Input Source register */
#define GTM_TIM5_AUX_IN_SRC  GTM.TIM5_AUX_IN_SRC.R         /* GTM TIM5 Auxiliary Input Source register */

/* GTMINT */
#define GTMINT_GTMMCR        GTMINT.GTMMCR.R               /* GTM Module Configuration Register */
#define GTMINT_GTMINTCLR     GTMINT.GTMINTCLR.R            /* GTM Interrupts Clear Register */
#define GTMINT_GTMAEICR      GTMINT.GTMAEICR.R             /* GTM AEI Control Register */

/* GTM_AFD */
#define GTM_AFD_0_CH0_BUF_ACC    GTM_AFD_0.CHANNEL[0].BUF_ACC.R /* AFD FIFO Channel n Buffer Access Register, n=0:7 */
#define GTM_AFD_0_CH1_BUF_ACC    GTM_AFD_0.CHANNEL[1].BUF_ACC.R /* AFD FIFO Channel n Buffer Access Register, n=0:7 */
#define GTM_AFD_0_CH2_BUF_ACC    GTM_AFD_0.CHANNEL[2].BUF_ACC.R /* AFD FIFO Channel n Buffer Access Register, n=0:7 */
#define GTM_AFD_0_CH3_BUF_ACC    GTM_AFD_0.CHANNEL[3].BUF_ACC.R /* AFD FIFO Channel n Buffer Access Register, n=0:7 */
#define GTM_AFD_0_CH4_BUF_ACC    GTM_AFD_0.CHANNEL[4].BUF_ACC.R /* AFD FIFO Channel n Buffer Access Register, n=0:7 */
#define GTM_AFD_0_CH5_BUF_ACC    GTM_AFD_0.CHANNEL[5].BUF_ACC.R /* AFD FIFO Channel n Buffer Access Register, n=0:7 */
#define GTM_AFD_0_CH6_BUF_ACC    GTM_AFD_0.CHANNEL[6].BUF_ACC.R /* AFD FIFO Channel n Buffer Access Register, n=0:7 */
#define GTM_AFD_0_CH7_BUF_ACC    GTM_AFD_0.CHANNEL[7].BUF_ACC.R /* AFD FIFO Channel n Buffer Access Register, n=0:7 */

/* GTM_AFD */
#define GTM_AFD_1_CH0_BUF_ACC    GTM_AFD_1.CHANNEL[0].BUF_ACC.R /* AFD FIFO Channel n Buffer Access Register, n=0:7 */
#define GTM_AFD_1_CH1_BUF_ACC    GTM_AFD_1.CHANNEL[1].BUF_ACC.R /* AFD FIFO Channel n Buffer Access Register, n=0:7 */
#define GTM_AFD_1_CH2_BUF_ACC    GTM_AFD_1.CHANNEL[2].BUF_ACC.R /* AFD FIFO Channel n Buffer Access Register, n=0:7 */
#define GTM_AFD_1_CH3_BUF_ACC    GTM_AFD_1.CHANNEL[3].BUF_ACC.R /* AFD FIFO Channel n Buffer Access Register, n=0:7 */
#define GTM_AFD_1_CH4_BUF_ACC    GTM_AFD_1.CHANNEL[4].BUF_ACC.R /* AFD FIFO Channel n Buffer Access Register, n=0:7 */
#define GTM_AFD_1_CH5_BUF_ACC    GTM_AFD_1.CHANNEL[5].BUF_ACC.R /* AFD FIFO Channel n Buffer Access Register, n=0:7 */
#define GTM_AFD_1_CH6_BUF_ACC    GTM_AFD_1.CHANNEL[6].BUF_ACC.R /* AFD FIFO Channel n Buffer Access Register, n=0:7 */
#define GTM_AFD_1_CH7_BUF_ACC    GTM_AFD_1.CHANNEL[7].BUF_ACC.R /* AFD FIFO Channel n Buffer Access Register, n=0:7 */

/* GTM_ARU */
#define GTM_ARU_ACCESS           GTM_ARU.ACCESS.R                  /* ARU Access Register */
#define GTM_ARU_DATA_H           GTM_ARU.DATA_H.R                  /* ARU Data High Register */
#define GTM_ARU_DATA_L           GTM_ARU.DATA_L.R                  /* ARU Data Low Register */
#define GTM_ARU_DBG_ACCESS0      GTM_ARU.DBG_ACCESS0.R             /* ARU Debug Access 0 Register */
#define GTM_ARU_DBG_DATA0_H      GTM_ARU.DBG_DATA0_H.R             /* ARU Debug Data 0 High Register */
#define GTM_ARU_DBG_DATA0_L      GTM_ARU.DBG_DATA0_L.R             /* ARU Debug Data 0 Low Register */
#define GTM_ARU_DBG_ACCESS1      GTM_ARU.DBG_ACCESS1.R             /* ARU Debug Access 1 Register */
#define GTM_ARU_DBG_DATA1_H      GTM_ARU.DBG_DATA1_H.R             /* ARU Debug Data 1 High */
#define GTM_ARU_DBG_DATA1_L      GTM_ARU.DBG_DATA1_L.R             /* ARU Debug Data 1 Low Register */
#define GTM_ARU_IRQ_NOTIFY       GTM_ARU.IRQ_NOTIFY.R              /* ARU Interrupt Request Notification Register */
#define GTM_ARU_IRQ_EN           GTM_ARU.IRQ_EN.R                  /* ARU Interrupt Request Enable Register */
#define GTM_ARU_IRQ_FORCINT      GTM_ARU.IRQ_FORCINT.R             /* ARU Force Interrupt Request Register */
#define GTM_ARU_IRQ_MODE         GTM_ARU.IRQ_MODE.R                /* ARU Interrupt Request Mode Register */

/* GTM_ATOM */
#define GTM_ATOM_0_CH0_RDADDR    GTM_ATOM_0.CH0_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_0_CH0_CTRL      GTM_ATOM_0.CH0_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_0_CH0_SR0       GTM_ATOM_0.CH0_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_0_CH0_SR1       GTM_ATOM_0.CH0_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_0_CH0_CM0       GTM_ATOM_0.CH0_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_0_CH0_CM1       GTM_ATOM_0.CH0_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_0_CH0_CN0       GTM_ATOM_0.CH0_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_0_CH0_STAT      GTM_ATOM_0.CH0_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_0_CH0_IRQ_NOTIFY GTM_ATOM_0.CH0_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_0_CH0_IRQ_EN    GTM_ATOM_0.CH0_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_0_CH0_IRQ_FORCINT GTM_ATOM_0.CH0_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_0_CH0_IRQ_MODE  GTM_ATOM_0.CH0_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_0_AGC_GLB_CTRL  GTM_ATOM_0.AGC_GLB_CTRL.R         /* ATOM AGC Global Control Register */
#define GTM_ATOM_0_AGC_ENDIS_CTRL GTM_ATOM_0.AGC_ENDIS_CTRL.R      /* ATOM TGC0 Enable/Disable Control Register */
#define GTM_ATOM_0_AGC_ENDIS_STAT GTM_ATOM_0.AGC_ENDIS_STAT.R      /* ATOM TGC0 Enable/Disable Status Register */
#define GTM_ATOM_0_AGC_ACT_TB    GTM_ATOM_0.AGC_ACT_TB.R           /* ATOM TGC0 Action Time Base Register */
#define GTM_ATOM_0_AGC_OUTEN_CTRL GTM_ATOM_0.AGC_OUTEN_CTRL.R      /* ATOM TGC0 Out Enable Control Register */
#define GTM_ATOM_0_AGC_OUTEN_STAT GTM_ATOM_0.AGC_OUTEN_STAT.R      /* ATOM TGC0 Out Enable Control/Status Register */
#define GTM_ATOM_0_AGC_FUPD_CTRL GTM_ATOM_0.AGC_FUPD_CTRL.R        /* ATOM TGC0 Force Update Control Register */
#define GTM_ATOM_0_AGC_INT_TRIG  GTM_ATOM_0.AGC_INT_TRIG.R         /* ATOM TGC0 Interrupt Trigger Register */
#define GTM_ATOM_0_CH1_RDADDR    GTM_ATOM_0.CH1_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_0_CH1_CTRL      GTM_ATOM_0.CH1_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_0_CH1_SR0       GTM_ATOM_0.CH1_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_0_CH1_SR1       GTM_ATOM_0.CH1_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_0_CH1_CM0       GTM_ATOM_0.CH1_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_0_CH1_CM1       GTM_ATOM_0.CH1_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_0_CH1_CN0       GTM_ATOM_0.CH1_CN0.R               /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_0_CH1_STAT      GTM_ATOM_0.CH1_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_0_CH1_IRQ_NOTIFY GTM_ATOM_0.CH1_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_0_CH1_IRQ_EN    GTM_ATOM_0.CH1_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_0_CH1_IRQ_FORCINT GTM_ATOM_0.CH1_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_0_CH1_IRQ_MODE  GTM_ATOM_0.CH1_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_0_CH2_RDADDR    GTM_ATOM_0.CH2_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_0_CH2_CTRL      GTM_ATOM_0.CH2_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_0_CH2_SR0       GTM_ATOM_0.CH2_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_0_CH2_SR1       GTM_ATOM_0.CH2_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_0_CH2_CM0       GTM_ATOM_0.CH2_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_0_CH2_CM1       GTM_ATOM_0.CH2_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_0_CH2_CN0       GTM_ATOM_0.CH2_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_0_CH2_STAT      GTM_ATOM_0.CH2_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_0_CH2_IRQ_NOTIFY GTM_ATOM_0.CH2_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_0_CH2_IRQ_EN    GTM_ATOM_0.CH2_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_0_CH2_IRQ_FORCINT GTM_ATOM_0.CH2_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_0_CH2_IRQ_MODE  GTM_ATOM_0.CH2_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_0_CH3_RDADDR    GTM_ATOM_0.CH3_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_0_CH3_CTRL      GTM_ATOM_0.CH3_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_0_CH3_SR0       GTM_ATOM_0.CH3_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_0_CH3_SR1       GTM_ATOM_0.CH3_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_0_CH3_CM0       GTM_ATOM_0.CH3_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_0_CH3_CM1       GTM_ATOM_0.CH3_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_0_CH3_CN0       GTM_ATOM_0.CH3_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_0_CH3_STAT      GTM_ATOM_0.CH3_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_0_CH3_IRQ_NOTIFY GTM_ATOM_0.CH3_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_0_CH3_IRQ_EN    GTM_ATOM_0.CH3_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_0_CH3_IRQ_FORCINT GTM_ATOM_0.CH3_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_0_CH3_IRQ_MODE  GTM_ATOM_0.CH3_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_0_CH4_RDADDR    GTM_ATOM_0.CH4_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_0_CH4_CTRL      GTM_ATOM_0.CH4_CTRL.R            /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_0_CH4_SR0       GTM_ATOM_0.CH4_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_0_CH4_SR1       GTM_ATOM_0.CH4_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_0_CH4_CM0       GTM_ATOM_0.CH4_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_0_CH4_CM1       GTM_ATOM_0.CH4_CM1.R               /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_0_CH4_CN0       GTM_ATOM_0.CH4_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_0_CH4_STAT      GTM_ATOM_0.CH4_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_0_CH4_IRQ_NOTIFY GTM_ATOM_0.CH4_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_0_CH4_IRQ_EN    GTM_ATOM_0.CH4_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_0_CH4_IRQ_FORCINT GTM_ATOM_0.CH4_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_0_CH4_IRQ_MODE  GTM_ATOM_0.CH4_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_0_CH5_RDADDR    GTM_ATOM_0.CH5_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_0_CH5_CTRL      GTM_ATOM_0.CH5_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_0_CH5_SR0       GTM_ATOM_0.CH5_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_0_CH5_SR1       GTM_ATOM_0.CH5_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_0_CH5_CM0       GTM_ATOM_0.CH5_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_0_CH5_CM1       GTM_ATOM_0.CH5_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_0_CH5_CN0       GTM_ATOM_0.CH5_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_0_CH5_STAT      GTM_ATOM_0.CH5_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_0_CH5_IRQ_NOTIFY GTM_ATOM_0.CH5_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_0_CH5_IRQ_EN    GTM_ATOM_0.CH5_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_0_CH5_IRQ_FORCINT GTM_ATOM_0.CH5_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_0_CH5_IRQ_MODE  GTM_ATOM_0.CH5_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_0_CH6_RDADDR    GTM_ATOM_0.CH6_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_0_CH6_CTRL      GTM_ATOM_0.CH6_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_0_CH6_SR0       GTM_ATOM_0.CH6_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_0_CH6_SR1       GTM_ATOM_0.CH6_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_0_CH6_CM0       GTM_ATOM_0.CH6_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_0_CH6_CM1       GTM_ATOM_0.CH6_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_0_CH6_CN0       GTM_ATOM_0.CH6_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_0_CH6_STAT      GTM_ATOM_0.CH6_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_0_CH6_IRQ_NOTIFY GTM_ATOM_0.CH6_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_0_CH6_IRQ_EN    GTM_ATOM_0.CH6_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_0_CH6_IRQ_FORCINT GTM_ATOM_0.CH6_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_0_CH6_IRQ_MODE  GTM_ATOM_0.CH6_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_0_CH7_RDADDR    GTM_ATOM_0.CH7_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_0_CH7_CTRL      GTM_ATOM_0.CH7_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_0_CH7_SR0       GTM_ATOM_0.CH7_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_0_CH7_SR1       GTM_ATOM_0.CH7_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_0_CH7_CM0       GTM_ATOM_0.CH7_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_0_CH7_CM1       GTM_ATOM_0.CH7_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_0_CH7_CN0       GTM_ATOM_0.CH7_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_0_CH7_STAT      GTM_ATOM_0.CH7_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_0_CH7_IRQ_NOTIFY GTM_ATOM_0.CH7_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_0_CH7_IRQ_EN    GTM_ATOM_0.CH7_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_0_CH7_IRQ_FORCINT GTM_ATOM_0.CH7_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_0_CH7_IRQ_MODE  GTM_ATOM_0.CH7_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */

/* GTM_ATOM */
#define GTM_ATOM_1_CH0_RDADDR    GTM_ATOM_1.CH0_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_1_CH0_CTRL      GTM_ATOM_1.CH0_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_1_CH0_SR0       GTM_ATOM_1.CH0_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_1_CH0_SR1       GTM_ATOM_1.CH0_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_1_CH0_CM0       GTM_ATOM_1.CH0_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_1_CH0_CM1       GTM_ATOM_1.CH0_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_1_CH0_CN0       GTM_ATOM_1.CH0_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_1_CH0_STAT      GTM_ATOM_1.CH0_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_1_CH0_IRQ_NOTIFY GTM_ATOM_1.CH0_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_1_CH0_IRQ_EN    GTM_ATOM_1.CH0_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_1_CH0_IRQ_FORCINT GTM_ATOM_1.CH0_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_1_CH0_IRQ_MODE  GTM_ATOM_1.CH0_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_1_AGC_GLB_CTRL  GTM_ATOM_1.AGC_GLB_CTRL.R         /* ATOM AGC Global Control Register */
#define GTM_ATOM_1_AGC_ENDIS_CTRL GTM_ATOM_1.AGC_ENDIS_CTRL.R      /* ATOM TGC0 Enable/Disable Control Register */
#define GTM_ATOM_1_AGC_ENDIS_STAT GTM_ATOM_1.AGC_ENDIS_STAT.R      /* ATOM TGC0 Enable/Disable Status Register */
#define GTM_ATOM_1_AGC_ACT_TB    GTM_ATOM_1.AGC_ACT_TB.R           /* ATOM TGC0 Action Time Base Register */
#define GTM_ATOM_1_AGC_OUTEN_CTRL GTM_ATOM_1.AGC_OUTEN_CTRL.R      /* ATOM TGC0 Out Enable Control Register */
#define GTM_ATOM_1_AGC_OUTEN_STAT GTM_ATOM_1.AGC_OUTEN_STAT.R      /* ATOM TGC0 Out Enable Control/Status Register */
#define GTM_ATOM_1_AGC_FUPD_CTRL GTM_ATOM_1.AGC_FUPD_CTRL.R        /* ATOM TGC0 Force Update Control Register */
#define GTM_ATOM_1_AGC_INT_TRIG  GTM_ATOM_1.AGC_INT_TRIG.R         /* ATOM TGC0 Interrupt Trigger Register */
#define GTM_ATOM_1_CH1_RDADDR    GTM_ATOM_1.CH1_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_1_CH1_CTRL      GTM_ATOM_1.CH1_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_1_CH1_SR0       GTM_ATOM_1.CH1_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_1_CH1_SR1       GTM_ATOM_1.CH1_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_1_CH1_CM0       GTM_ATOM_1.CH1_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_1_CH1_CM1       GTM_ATOM_1.CH1_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_1_CH1_CN0       GTM_ATOM_1.CH1_CN0.R               /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_1_CH1_STAT      GTM_ATOM_1.CH1_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_1_CH1_IRQ_NOTIFY GTM_ATOM_1.CH1_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_1_CH1_IRQ_EN    GTM_ATOM_1.CH1_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_1_CH1_IRQ_FORCINT GTM_ATOM_1.CH1_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_1_CH1_IRQ_MODE  GTM_ATOM_1.CH1_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_1_CH2_RDADDR    GTM_ATOM_1.CH2_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_1_CH2_CTRL      GTM_ATOM_1.CH2_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_1_CH2_SR0       GTM_ATOM_1.CH2_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_1_CH2_SR1       GTM_ATOM_1.CH2_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_1_CH2_CM0       GTM_ATOM_1.CH2_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_1_CH2_CM1       GTM_ATOM_1.CH2_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_1_CH2_CN0       GTM_ATOM_1.CH2_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_1_CH2_STAT      GTM_ATOM_1.CH2_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_1_CH2_IRQ_NOTIFY GTM_ATOM_1.CH2_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_1_CH2_IRQ_EN    GTM_ATOM_1.CH2_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_1_CH2_IRQ_FORCINT GTM_ATOM_1.CH2_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_1_CH2_IRQ_MODE  GTM_ATOM_1.CH2_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_1_CH3_RDADDR    GTM_ATOM_1.CH3_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_1_CH3_CTRL      GTM_ATOM_1.CH3_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_1_CH3_SR0       GTM_ATOM_1.CH3_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_1_CH3_SR1       GTM_ATOM_1.CH3_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_1_CH3_CM0       GTM_ATOM_1.CH3_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_1_CH3_CM1       GTM_ATOM_1.CH3_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_1_CH3_CN0       GTM_ATOM_1.CH3_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_1_CH3_STAT      GTM_ATOM_1.CH3_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_1_CH3_IRQ_NOTIFY GTM_ATOM_1.CH3_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_1_CH3_IRQ_EN    GTM_ATOM_1.CH3_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_1_CH3_IRQ_FORCINT GTM_ATOM_1.CH3_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_1_CH3_IRQ_MODE  GTM_ATOM_1.CH3_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_1_CH4_RDADDR    GTM_ATOM_1.CH4_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_1_CH4_CTRL      GTM_ATOM_1.CH4_CTRL.R            /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_1_CH4_SR0       GTM_ATOM_1.CH4_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_1_CH4_SR1       GTM_ATOM_1.CH4_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_1_CH4_CM0       GTM_ATOM_1.CH4_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_1_CH4_CM1       GTM_ATOM_1.CH4_CM1.R               /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_1_CH4_CN0       GTM_ATOM_1.CH4_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_1_CH4_STAT      GTM_ATOM_1.CH4_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_1_CH4_IRQ_NOTIFY GTM_ATOM_1.CH4_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_1_CH4_IRQ_EN    GTM_ATOM_1.CH4_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_1_CH4_IRQ_FORCINT GTM_ATOM_1.CH4_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_1_CH4_IRQ_MODE  GTM_ATOM_1.CH4_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_1_CH5_RDADDR    GTM_ATOM_1.CH5_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_1_CH5_CTRL      GTM_ATOM_1.CH5_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_1_CH5_SR0       GTM_ATOM_1.CH5_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_1_CH5_SR1       GTM_ATOM_1.CH5_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_1_CH5_CM0       GTM_ATOM_1.CH5_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_1_CH5_CM1       GTM_ATOM_1.CH5_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_1_CH5_CN0       GTM_ATOM_1.CH5_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_1_CH5_STAT      GTM_ATOM_1.CH5_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_1_CH5_IRQ_NOTIFY GTM_ATOM_1.CH5_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_1_CH5_IRQ_EN    GTM_ATOM_1.CH5_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_1_CH5_IRQ_FORCINT GTM_ATOM_1.CH5_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_1_CH5_IRQ_MODE  GTM_ATOM_1.CH5_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_1_CH6_RDADDR    GTM_ATOM_1.CH6_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_1_CH6_CTRL      GTM_ATOM_1.CH6_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_1_CH6_SR0       GTM_ATOM_1.CH6_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_1_CH6_SR1       GTM_ATOM_1.CH6_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_1_CH6_CM0       GTM_ATOM_1.CH6_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_1_CH6_CM1       GTM_ATOM_1.CH6_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_1_CH6_CN0       GTM_ATOM_1.CH6_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_1_CH6_STAT      GTM_ATOM_1.CH6_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_1_CH6_IRQ_NOTIFY GTM_ATOM_1.CH6_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_1_CH6_IRQ_EN    GTM_ATOM_1.CH6_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_1_CH6_IRQ_FORCINT GTM_ATOM_1.CH6_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_1_CH6_IRQ_MODE  GTM_ATOM_1.CH6_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_1_CH7_RDADDR    GTM_ATOM_1.CH7_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_1_CH7_CTRL      GTM_ATOM_1.CH7_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_1_CH7_SR0       GTM_ATOM_1.CH7_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_1_CH7_SR1       GTM_ATOM_1.CH7_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_1_CH7_CM0       GTM_ATOM_1.CH7_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_1_CH7_CM1       GTM_ATOM_1.CH7_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_1_CH7_CN0       GTM_ATOM_1.CH7_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_1_CH7_STAT      GTM_ATOM_1.CH7_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_1_CH7_IRQ_NOTIFY GTM_ATOM_1.CH7_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_1_CH7_IRQ_EN    GTM_ATOM_1.CH7_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_1_CH7_IRQ_FORCINT GTM_ATOM_1.CH7_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_1_CH7_IRQ_MODE  GTM_ATOM_1.CH7_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */

/* GTM_ATOM */
#define GTM_ATOM_2_CH0_RDADDR    GTM_ATOM_2.CH0_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_2_CH0_CTRL      GTM_ATOM_2.CH0_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_2_CH0_SR0       GTM_ATOM_2.CH0_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_2_CH0_SR1       GTM_ATOM_2.CH0_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_2_CH0_CM0       GTM_ATOM_2.CH0_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_2_CH0_CM1       GTM_ATOM_2.CH0_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_2_CH0_CN0       GTM_ATOM_2.CH0_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_2_CH0_STAT      GTM_ATOM_2.CH0_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_2_CH0_IRQ_NOTIFY GTM_ATOM_2.CH0_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_2_CH0_IRQ_EN    GTM_ATOM_2.CH0_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_2_CH0_IRQ_FORCINT GTM_ATOM_2.CH0_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_2_CH0_IRQ_MODE  GTM_ATOM_2.CH0_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_2_AGC_GLB_CTRL  GTM_ATOM_2.AGC_GLB_CTRL.R         /* ATOM AGC Global Control Register */
#define GTM_ATOM_2_AGC_ENDIS_CTRL GTM_ATOM_2.AGC_ENDIS_CTRL.R      /* ATOM TGC0 Enable/Disable Control Register */
#define GTM_ATOM_2_AGC_ENDIS_STAT GTM_ATOM_2.AGC_ENDIS_STAT.R      /* ATOM TGC0 Enable/Disable Status Register */
#define GTM_ATOM_2_AGC_ACT_TB    GTM_ATOM_2.AGC_ACT_TB.R           /* ATOM TGC0 Action Time Base Register */
#define GTM_ATOM_2_AGC_OUTEN_CTRL GTM_ATOM_2.AGC_OUTEN_CTRL.R      /* ATOM TGC0 Out Enable Control Register */
#define GTM_ATOM_2_AGC_OUTEN_STAT GTM_ATOM_2.AGC_OUTEN_STAT.R      /* ATOM TGC0 Out Enable Control/Status Register */
#define GTM_ATOM_2_AGC_FUPD_CTRL GTM_ATOM_2.AGC_FUPD_CTRL.R        /* ATOM TGC0 Force Update Control Register */
#define GTM_ATOM_2_AGC_INT_TRIG  GTM_ATOM_2.AGC_INT_TRIG.R         /* ATOM TGC0 Interrupt Trigger Register */
#define GTM_ATOM_2_CH1_RDADDR    GTM_ATOM_2.CH1_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_2_CH1_CTRL      GTM_ATOM_2.CH1_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_2_CH1_SR0       GTM_ATOM_2.CH1_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_2_CH1_SR1       GTM_ATOM_2.CH1_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_2_CH1_CM0       GTM_ATOM_2.CH1_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_2_CH1_CM1       GTM_ATOM_2.CH1_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_2_CH1_CN0       GTM_ATOM_2.CH1_CN0.R               /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_2_CH1_STAT      GTM_ATOM_2.CH1_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_2_CH1_IRQ_NOTIFY GTM_ATOM_2.CH1_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_2_CH1_IRQ_EN    GTM_ATOM_2.CH1_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_2_CH1_IRQ_FORCINT GTM_ATOM_2.CH1_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_2_CH1_IRQ_MODE  GTM_ATOM_2.CH1_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_2_CH2_RDADDR    GTM_ATOM_2.CH2_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_2_CH2_CTRL      GTM_ATOM_2.CH2_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_2_CH2_SR0       GTM_ATOM_2.CH2_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_2_CH2_SR1       GTM_ATOM_2.CH2_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_2_CH2_CM0       GTM_ATOM_2.CH2_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_2_CH2_CM1       GTM_ATOM_2.CH2_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_2_CH2_CN0       GTM_ATOM_2.CH2_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_2_CH2_STAT      GTM_ATOM_2.CH2_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_2_CH2_IRQ_NOTIFY GTM_ATOM_2.CH2_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_2_CH2_IRQ_EN    GTM_ATOM_2.CH2_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_2_CH2_IRQ_FORCINT GTM_ATOM_2.CH2_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_2_CH2_IRQ_MODE  GTM_ATOM_2.CH2_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_2_CH3_RDADDR    GTM_ATOM_2.CH3_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_2_CH3_CTRL      GTM_ATOM_2.CH3_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_2_CH3_SR0       GTM_ATOM_2.CH3_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_2_CH3_SR1       GTM_ATOM_2.CH3_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_2_CH3_CM0       GTM_ATOM_2.CH3_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_2_CH3_CM1       GTM_ATOM_2.CH3_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_2_CH3_CN0       GTM_ATOM_2.CH3_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_2_CH3_STAT      GTM_ATOM_2.CH3_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_2_CH3_IRQ_NOTIFY GTM_ATOM_2.CH3_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_2_CH3_IRQ_EN    GTM_ATOM_2.CH3_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_2_CH3_IRQ_FORCINT GTM_ATOM_2.CH3_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_2_CH3_IRQ_MODE  GTM_ATOM_2.CH3_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_2_CH4_RDADDR    GTM_ATOM_2.CH4_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_2_CH4_CTRL      GTM_ATOM_2.CH4_CTRL.R            /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_2_CH4_SR0       GTM_ATOM_2.CH4_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_2_CH4_SR1       GTM_ATOM_2.CH4_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_2_CH4_CM0       GTM_ATOM_2.CH4_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_2_CH4_CM1       GTM_ATOM_2.CH4_CM1.R               /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_2_CH4_CN0       GTM_ATOM_2.CH4_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_2_CH4_STAT      GTM_ATOM_2.CH4_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_2_CH4_IRQ_NOTIFY GTM_ATOM_2.CH4_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_2_CH4_IRQ_EN    GTM_ATOM_2.CH4_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_2_CH4_IRQ_FORCINT GTM_ATOM_2.CH4_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_2_CH4_IRQ_MODE  GTM_ATOM_2.CH4_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_2_CH5_RDADDR    GTM_ATOM_2.CH5_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_2_CH5_CTRL      GTM_ATOM_2.CH5_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_2_CH5_SR0       GTM_ATOM_2.CH5_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_2_CH5_SR1       GTM_ATOM_2.CH5_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_2_CH5_CM0       GTM_ATOM_2.CH5_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_2_CH5_CM1       GTM_ATOM_2.CH5_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_2_CH5_CN0       GTM_ATOM_2.CH5_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_2_CH5_STAT      GTM_ATOM_2.CH5_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_2_CH5_IRQ_NOTIFY GTM_ATOM_2.CH5_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_2_CH5_IRQ_EN    GTM_ATOM_2.CH5_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_2_CH5_IRQ_FORCINT GTM_ATOM_2.CH5_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_2_CH5_IRQ_MODE  GTM_ATOM_2.CH5_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_2_CH6_RDADDR    GTM_ATOM_2.CH6_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_2_CH6_CTRL      GTM_ATOM_2.CH6_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_2_CH6_SR0       GTM_ATOM_2.CH6_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_2_CH6_SR1       GTM_ATOM_2.CH6_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_2_CH6_CM0       GTM_ATOM_2.CH6_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_2_CH6_CM1       GTM_ATOM_2.CH6_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_2_CH6_CN0       GTM_ATOM_2.CH6_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_2_CH6_STAT      GTM_ATOM_2.CH6_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_2_CH6_IRQ_NOTIFY GTM_ATOM_2.CH6_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_2_CH6_IRQ_EN    GTM_ATOM_2.CH6_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_2_CH6_IRQ_FORCINT GTM_ATOM_2.CH6_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_2_CH6_IRQ_MODE  GTM_ATOM_2.CH6_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_2_CH7_RDADDR    GTM_ATOM_2.CH7_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_2_CH7_CTRL      GTM_ATOM_2.CH7_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_2_CH7_SR0       GTM_ATOM_2.CH7_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_2_CH7_SR1       GTM_ATOM_2.CH7_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_2_CH7_CM0       GTM_ATOM_2.CH7_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_2_CH7_CM1       GTM_ATOM_2.CH7_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_2_CH7_CN0       GTM_ATOM_2.CH7_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_2_CH7_STAT      GTM_ATOM_2.CH7_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_2_CH7_IRQ_NOTIFY GTM_ATOM_2.CH7_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_2_CH7_IRQ_EN    GTM_ATOM_2.CH7_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_2_CH7_IRQ_FORCINT GTM_ATOM_2.CH7_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_2_CH7_IRQ_MODE  GTM_ATOM_2.CH7_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */

/* GTM_ATOM */
#define GTM_ATOM_3_CH0_RDADDR    GTM_ATOM_3.CH0_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_3_CH0_CTRL      GTM_ATOM_3.CH0_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_3_CH0_SR0       GTM_ATOM_3.CH0_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_3_CH0_SR1       GTM_ATOM_3.CH0_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_3_CH0_CM0       GTM_ATOM_3.CH0_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_3_CH0_CM1       GTM_ATOM_3.CH0_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_3_CH0_CN0       GTM_ATOM_3.CH0_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_3_CH0_STAT      GTM_ATOM_3.CH0_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_3_CH0_IRQ_NOTIFY GTM_ATOM_3.CH0_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_3_CH0_IRQ_EN    GTM_ATOM_3.CH0_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_3_CH0_IRQ_FORCINT GTM_ATOM_3.CH0_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_3_CH0_IRQ_MODE  GTM_ATOM_3.CH0_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_3_AGC_GLB_CTRL  GTM_ATOM_3.AGC_GLB_CTRL.R         /* ATOM AGC Global Control Register */
#define GTM_ATOM_3_AGC_ENDIS_CTRL GTM_ATOM_3.AGC_ENDIS_CTRL.R      /* ATOM TGC0 Enable/Disable Control Register */
#define GTM_ATOM_3_AGC_ENDIS_STAT GTM_ATOM_3.AGC_ENDIS_STAT.R      /* ATOM TGC0 Enable/Disable Status Register */
#define GTM_ATOM_3_AGC_ACT_TB    GTM_ATOM_3.AGC_ACT_TB.R           /* ATOM TGC0 Action Time Base Register */
#define GTM_ATOM_3_AGC_OUTEN_CTRL GTM_ATOM_3.AGC_OUTEN_CTRL.R      /* ATOM TGC0 Out Enable Control Register */
#define GTM_ATOM_3_AGC_OUTEN_STAT GTM_ATOM_3.AGC_OUTEN_STAT.R      /* ATOM TGC0 Out Enable Control/Status Register */
#define GTM_ATOM_3_AGC_FUPD_CTRL GTM_ATOM_3.AGC_FUPD_CTRL.R        /* ATOM TGC0 Force Update Control Register */
#define GTM_ATOM_3_AGC_INT_TRIG  GTM_ATOM_3.AGC_INT_TRIG.R         /* ATOM TGC0 Interrupt Trigger Register */
#define GTM_ATOM_3_CH1_RDADDR    GTM_ATOM_3.CH1_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_3_CH1_CTRL      GTM_ATOM_3.CH1_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_3_CH1_SR0       GTM_ATOM_3.CH1_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_3_CH1_SR1       GTM_ATOM_3.CH1_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_3_CH1_CM0       GTM_ATOM_3.CH1_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_3_CH1_CM1       GTM_ATOM_3.CH1_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_3_CH1_CN0       GTM_ATOM_3.CH1_CN0.R               /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_3_CH1_STAT      GTM_ATOM_3.CH1_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_3_CH1_IRQ_NOTIFY GTM_ATOM_3.CH1_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_3_CH1_IRQ_EN    GTM_ATOM_3.CH1_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_3_CH1_IRQ_FORCINT GTM_ATOM_3.CH1_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_3_CH1_IRQ_MODE  GTM_ATOM_3.CH1_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_3_CH2_RDADDR    GTM_ATOM_3.CH2_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_3_CH2_CTRL      GTM_ATOM_3.CH2_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_3_CH2_SR0       GTM_ATOM_3.CH2_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_3_CH2_SR1       GTM_ATOM_3.CH2_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_3_CH2_CM0       GTM_ATOM_3.CH2_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_3_CH2_CM1       GTM_ATOM_3.CH2_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_3_CH2_CN0       GTM_ATOM_3.CH2_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_3_CH2_STAT      GTM_ATOM_3.CH2_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_3_CH2_IRQ_NOTIFY GTM_ATOM_3.CH2_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_3_CH2_IRQ_EN    GTM_ATOM_3.CH2_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_3_CH2_IRQ_FORCINT GTM_ATOM_3.CH2_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_3_CH2_IRQ_MODE  GTM_ATOM_3.CH2_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_3_CH3_RDADDR    GTM_ATOM_3.CH3_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_3_CH3_CTRL      GTM_ATOM_3.CH3_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_3_CH3_SR0       GTM_ATOM_3.CH3_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_3_CH3_SR1       GTM_ATOM_3.CH3_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_3_CH3_CM0       GTM_ATOM_3.CH3_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_3_CH3_CM1       GTM_ATOM_3.CH3_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_3_CH3_CN0       GTM_ATOM_3.CH3_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_3_CH3_STAT      GTM_ATOM_3.CH3_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_3_CH3_IRQ_NOTIFY GTM_ATOM_3.CH3_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_3_CH3_IRQ_EN    GTM_ATOM_3.CH3_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_3_CH3_IRQ_FORCINT GTM_ATOM_3.CH3_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_3_CH3_IRQ_MODE  GTM_ATOM_3.CH3_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_3_CH4_RDADDR    GTM_ATOM_3.CH4_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_3_CH4_CTRL      GTM_ATOM_3.CH4_CTRL.R            /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_3_CH4_SR0       GTM_ATOM_3.CH4_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_3_CH4_SR1       GTM_ATOM_3.CH4_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_3_CH4_CM0       GTM_ATOM_3.CH4_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_3_CH4_CM1       GTM_ATOM_3.CH4_CM1.R               /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_3_CH4_CN0       GTM_ATOM_3.CH4_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_3_CH4_STAT      GTM_ATOM_3.CH4_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_3_CH4_IRQ_NOTIFY GTM_ATOM_3.CH4_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_3_CH4_IRQ_EN    GTM_ATOM_3.CH4_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_3_CH4_IRQ_FORCINT GTM_ATOM_3.CH4_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_3_CH4_IRQ_MODE  GTM_ATOM_3.CH4_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_3_CH5_RDADDR    GTM_ATOM_3.CH5_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_3_CH5_CTRL      GTM_ATOM_3.CH5_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_3_CH5_SR0       GTM_ATOM_3.CH5_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_3_CH5_SR1       GTM_ATOM_3.CH5_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_3_CH5_CM0       GTM_ATOM_3.CH5_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_3_CH5_CM1       GTM_ATOM_3.CH5_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_3_CH5_CN0       GTM_ATOM_3.CH5_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_3_CH5_STAT      GTM_ATOM_3.CH5_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_3_CH5_IRQ_NOTIFY GTM_ATOM_3.CH5_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_3_CH5_IRQ_EN    GTM_ATOM_3.CH5_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_3_CH5_IRQ_FORCINT GTM_ATOM_3.CH5_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_3_CH5_IRQ_MODE  GTM_ATOM_3.CH5_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_3_CH6_RDADDR    GTM_ATOM_3.CH6_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_3_CH6_CTRL      GTM_ATOM_3.CH6_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_3_CH6_SR0       GTM_ATOM_3.CH6_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_3_CH6_SR1       GTM_ATOM_3.CH6_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_3_CH6_CM0       GTM_ATOM_3.CH6_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_3_CH6_CM1       GTM_ATOM_3.CH6_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_3_CH6_CN0       GTM_ATOM_3.CH6_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_3_CH6_STAT      GTM_ATOM_3.CH6_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_3_CH6_IRQ_NOTIFY GTM_ATOM_3.CH6_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_3_CH6_IRQ_EN    GTM_ATOM_3.CH6_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_3_CH6_IRQ_FORCINT GTM_ATOM_3.CH6_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_3_CH6_IRQ_MODE  GTM_ATOM_3.CH6_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_3_CH7_RDADDR    GTM_ATOM_3.CH7_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_3_CH7_CTRL      GTM_ATOM_3.CH7_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_3_CH7_SR0       GTM_ATOM_3.CH7_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_3_CH7_SR1       GTM_ATOM_3.CH7_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_3_CH7_CM0       GTM_ATOM_3.CH7_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_3_CH7_CM1       GTM_ATOM_3.CH7_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_3_CH7_CN0       GTM_ATOM_3.CH7_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_3_CH7_STAT      GTM_ATOM_3.CH7_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_3_CH7_IRQ_NOTIFY GTM_ATOM_3.CH7_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_3_CH7_IRQ_EN    GTM_ATOM_3.CH7_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_3_CH7_IRQ_FORCINT GTM_ATOM_3.CH7_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_3_CH7_IRQ_MODE  GTM_ATOM_3.CH7_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */

/* GTM_ATOM */
#define GTM_ATOM_4_CH0_RDADDR    GTM_ATOM_4.CH0_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_4_CH0_CTRL      GTM_ATOM_4.CH0_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_4_CH0_SR0       GTM_ATOM_4.CH0_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_4_CH0_SR1       GTM_ATOM_4.CH0_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_4_CH0_CM0       GTM_ATOM_4.CH0_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_4_CH0_CM1       GTM_ATOM_4.CH0_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_4_CH0_CN0       GTM_ATOM_4.CH0_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_4_CH0_STAT      GTM_ATOM_4.CH0_STAT.R             /* ATOM Channel n Status Register, n=0:7ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_4_CH0_IRQ_NOTIFY GTM_ATOM_4.CH0_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_4_CH0_IRQ_EN    GTM_ATOM_4.CH0_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_4_CH0_IRQ_FORCINT GTM_ATOM_4.CH0_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_4_CH0_IRQ_MODE  GTM_ATOM_4.CH0_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_4_AGC_GLB_CTRL  GTM_ATOM_4.AGC_GLB_CTRL.R         /* ATOM AGC Global Control Register */
#define GTM_ATOM_4_AGC_ENDIS_CTRL GTM_ATOM_4.AGC_ENDIS_CTRL.R      /* ATOM TGC0 Enable/Disable Control Register */
#define GTM_ATOM_4_AGC_ENDIS_STAT GTM_ATOM_4.AGC_ENDIS_STAT.R      /* ATOM TGC0 Enable/Disable Status Register */
#define GTM_ATOM_4_AGC_ACT_TB    GTM_ATOM_4.AGC_ACT_TB.R           /* ATOM TGC0 Action Time Base Register */
#define GTM_ATOM_4_AGC_OUTEN_CTRL GTM_ATOM_4.AGC_OUTEN_CTRL.R      /* ATOM TGC0 Out Enable Control Register */
#define GTM_ATOM_4_AGC_OUTEN_STAT GTM_ATOM_4.AGC_OUTEN_STAT.R      /* ATOM TGC0 Out Enable Control/Status Register */
#define GTM_ATOM_4_AGC_FUPD_CTRL GTM_ATOM_4.AGC_FUPD_CTRL.R        /* ATOM TGC0 Force Update Control Register */
#define GTM_ATOM_4_AGC_INT_TRIG  GTM_ATOM_4.AGC_INT_TRIG.R         /* ATOM TGC0 Interrupt Trigger Register */
#define GTM_ATOM_4_CH1_RDADDR    GTM_ATOM_4.CH1_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_4_CH1_CTRL      GTM_ATOM_4.CH1_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_4_CH1_SR0       GTM_ATOM_4.CH1_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_4_CH1_SR1       GTM_ATOM_4.CH1_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_4_CH1_CM0       GTM_ATOM_4.CH1_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_4_CH1_CM1       GTM_ATOM_4.CH1_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_4_CH1_CN0       GTM_ATOM_4.CH1_CN0.R               /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_4_CH1_STAT      GTM_ATOM_4.CH1_STAT.R             /* ATOM Channel n Status Register, n=0:7ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_4_CH1_IRQ_NOTIFY GTM_ATOM_4.CH1_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_4_CH1_IRQ_EN    GTM_ATOM_4.CH1_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_4_CH1_IRQ_FORCINT GTM_ATOM_4.CH1_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_4_CH1_IRQ_MODE  GTM_ATOM_4.CH1_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_4_CH2_RDADDR    GTM_ATOM_4.CH2_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_4_CH2_CTRL      GTM_ATOM_4.CH2_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_4_CH2_SR0       GTM_ATOM_4.CH2_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_4_CH2_SR1       GTM_ATOM_4.CH2_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_4_CH2_CM0       GTM_ATOM_4.CH2_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_4_CH2_CM1       GTM_ATOM_4.CH2_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_4_CH2_CN0       GTM_ATOM_4.CH2_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_4_CH2_STAT      GTM_ATOM_4.CH2_STAT.R             /* ATOM Channel n Status Register, n=0:7ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_4_CH2_IRQ_NOTIFY GTM_ATOM_4.CH2_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_4_CH2_IRQ_EN    GTM_ATOM_4.CH2_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_4_CH2_IRQ_FORCINT GTM_ATOM_4.CH2_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_4_CH2_IRQ_MODE  GTM_ATOM_4.CH2_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_4_CH3_RDADDR    GTM_ATOM_4.CH3_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_4_CH3_CTRL      GTM_ATOM_4.CH3_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_4_CH3_SR0       GTM_ATOM_4.CH3_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_4_CH3_SR1       GTM_ATOM_4.CH3_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_4_CH3_CM0       GTM_ATOM_4.CH3_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_4_CH3_CM1       GTM_ATOM_4.CH3_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_4_CH3_CN0       GTM_ATOM_4.CH3_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_4_CH3_STAT      GTM_ATOM_4.CH3_STAT.R             /* ATOM Channel n Status Register, n=0:7ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_4_CH3_IRQ_NOTIFY GTM_ATOM_4.CH3_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_4_CH3_IRQ_EN    GTM_ATOM_4.CH3_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_4_CH3_IRQ_FORCINT GTM_ATOM_4.CH3_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_4_CH3_IRQ_MODE  GTM_ATOM_4.CH3_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_4_CH4_RDADDR    GTM_ATOM_4.CH4_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_4_CH4_CTRL      GTM_ATOM_4.CH4_CTRL.R            /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_4_CH4_SR0       GTM_ATOM_4.CH4_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_4_CH4_SR1       GTM_ATOM_4.CH4_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_4_CH4_CM0       GTM_ATOM_4.CH4_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_4_CH4_CM1       GTM_ATOM_4.CH4_CM1.R               /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_4_CH4_CN0       GTM_ATOM_4.CH4_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_4_CH4_STAT      GTM_ATOM_4.CH4_STAT.R             /* ATOM Channel n Status Register, n=0:7ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_4_CH4_IRQ_NOTIFY GTM_ATOM_4.CH4_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_4_CH4_IRQ_EN    GTM_ATOM_4.CH4_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_4_CH4_IRQ_FORCINT GTM_ATOM_4.CH4_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_4_CH4_IRQ_MODE  GTM_ATOM_4.CH4_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_4_CH5_RDADDR    GTM_ATOM_4.CH5_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_4_CH5_CTRL      GTM_ATOM_4.CH5_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_4_CH5_SR0       GTM_ATOM_4.CH5_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_4_CH5_SR1       GTM_ATOM_4.CH5_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_4_CH5_CM0       GTM_ATOM_4.CH5_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_4_CH5_CM1       GTM_ATOM_4.CH5_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_4_CH5_CN0       GTM_ATOM_4.CH5_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_4_CH5_STAT      GTM_ATOM_4.CH5_STAT.R             /* ATOM Channel n Status Register, n=0:7ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_4_CH5_IRQ_NOTIFY GTM_ATOM_4.CH5_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_4_CH5_IRQ_EN    GTM_ATOM_4.CH5_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_4_CH5_IRQ_FORCINT GTM_ATOM_4.CH5_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_4_CH5_IRQ_MODE  GTM_ATOM_4.CH5_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_4_CH6_RDADDR    GTM_ATOM_4.CH6_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_4_CH6_CTRL      GTM_ATOM_4.CH6_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_4_CH6_SR0       GTM_ATOM_4.CH6_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_4_CH6_SR1       GTM_ATOM_4.CH6_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_4_CH6_CM0       GTM_ATOM_4.CH6_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_4_CH6_CM1       GTM_ATOM_4.CH6_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_4_CH6_CN0       GTM_ATOM_4.CH6_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_4_CH6_STAT      GTM_ATOM_4.CH6_STAT.R             /* ATOM Channel n Status Register, n=0:7ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_4_CH6_IRQ_NOTIFY GTM_ATOM_4.CH6_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_4_CH6_IRQ_EN    GTM_ATOM_4.CH6_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_4_CH6_IRQ_FORCINT GTM_ATOM_4.CH6_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_4_CH6_IRQ_MODE  GTM_ATOM_4.CH6_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_4_CH7_RDADDR    GTM_ATOM_4.CH7_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_4_CH7_CTRL      GTM_ATOM_4.CH7_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_4_CH7_SR0       GTM_ATOM_4.CH7_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_4_CH7_SR1       GTM_ATOM_4.CH7_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_4_CH7_CM0       GTM_ATOM_4.CH7_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_4_CH7_CM1       GTM_ATOM_4.CH7_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_4_CH7_CN0       GTM_ATOM_4.CH7_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_4_CH7_STAT      GTM_ATOM_4.CH7_STAT.R             /* ATOM Channel n Status Register, n=0:7ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_4_CH7_IRQ_NOTIFY GTM_ATOM_4.CH7_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_4_CH7_IRQ_EN    GTM_ATOM_4.CH7_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_4_CH7_IRQ_FORCINT GTM_ATOM_4.CH7_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_4_CH7_IRQ_MODE  GTM_ATOM_4.CH7_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */

/* GTM_ATOM */
#define GTM_ATOM_5_CH0_RDADDR    GTM_ATOM_5.CH0_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_5_CH0_CTRL      GTM_ATOM_5.CH0_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_5_CH0_SR0       GTM_ATOM_5.CH0_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_5_CH0_SR1       GTM_ATOM_5.CH0_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_5_CH0_CM0       GTM_ATOM_5.CH0_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_5_CH0_CM1       GTM_ATOM_5.CH0_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_5_CH0_CN0       GTM_ATOM_5.CH0_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_5_CH0_STAT      GTM_ATOM_5.CH0_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_5_CH0_IRQ_NOTIFY GTM_ATOM_5.CH0_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_5_CH0_IRQ_EN    GTM_ATOM_5.CH0_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_5_CH0_IRQ_FORCINT GTM_ATOM_5.CH0_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_5_CH0_IRQ_MODE  GTM_ATOM_5.CH0_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_5_AGC_GLB_CTRL  GTM_ATOM_5.AGC_GLB_CTRL.R         /* ATOM AGC Global Control Register */
#define GTM_ATOM_5_AGC_ENDIS_CTRL GTM_ATOM_5.AGC_ENDIS_CTRL.R      /* ATOM TGC0 Enable/Disable Control Register */
#define GTM_ATOM_5_AGC_ENDIS_STAT GTM_ATOM_5.AGC_ENDIS_STAT.R      /* ATOM TGC0 Enable/Disable Status Register */
#define GTM_ATOM_5_AGC_ACT_TB    GTM_ATOM_5.AGC_ACT_TB.R           /* ATOM TGC0 Action Time Base Register */
#define GTM_ATOM_5_AGC_OUTEN_CTRL GTM_ATOM_5.AGC_OUTEN_CTRL.R      /* ATOM TGC0 Out Enable Control Register */
#define GTM_ATOM_5_AGC_OUTEN_STAT GTM_ATOM_5.AGC_OUTEN_STAT.R      /* ATOM TGC0 Out Enable Control/Status Register */
#define GTM_ATOM_5_AGC_FUPD_CTRL GTM_ATOM_5.AGC_FUPD_CTRL.R        /* ATOM TGC0 Force Update Control Register */
#define GTM_ATOM_5_AGC_INT_TRIG  GTM_ATOM_5.AGC_INT_TRIG.R         /* ATOM TGC0 Interrupt Trigger Register */
#define GTM_ATOM_5_CH1_RDADDR    GTM_ATOM_5.CH1_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_5_CH1_CTRL      GTM_ATOM_5.CH1_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_5_CH1_SR0       GTM_ATOM_5.CH1_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_5_CH1_SR1       GTM_ATOM_5.CH1_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_5_CH1_CM0       GTM_ATOM_5.CH1_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_5_CH1_CM1       GTM_ATOM_5.CH1_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_5_CH1_CN0       GTM_ATOM_5.CH1_CN0.R               /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_5_CH1_STAT      GTM_ATOM_5.CH1_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_5_CH1_IRQ_NOTIFY GTM_ATOM_5.CH1_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_5_CH1_IRQ_EN    GTM_ATOM_5.CH1_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_5_CH1_IRQ_FORCINT GTM_ATOM_5.CH1_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_5_CH1_IRQ_MODE  GTM_ATOM_5.CH1_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_5_CH2_RDADDR    GTM_ATOM_5.CH2_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_5_CH2_CTRL      GTM_ATOM_5.CH2_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_5_CH2_SR0       GTM_ATOM_5.CH2_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_5_CH2_SR1       GTM_ATOM_5.CH2_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_5_CH2_CM0       GTM_ATOM_5.CH2_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_5_CH2_CM1       GTM_ATOM_5.CH2_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_5_CH2_CN0       GTM_ATOM_5.CH2_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_5_CH2_STAT      GTM_ATOM_5.CH2_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_5_CH2_IRQ_NOTIFY GTM_ATOM_5.CH2_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_5_CH2_IRQ_EN    GTM_ATOM_5.CH2_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_5_CH2_IRQ_FORCINT GTM_ATOM_5.CH2_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_5_CH2_IRQ_MODE  GTM_ATOM_5.CH2_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_5_CH3_RDADDR    GTM_ATOM_5.CH3_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_5_CH3_CTRL      GTM_ATOM_5.CH3_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_5_CH3_SR0       GTM_ATOM_5.CH3_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_5_CH3_SR1       GTM_ATOM_5.CH3_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_5_CH3_CM0       GTM_ATOM_5.CH3_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_5_CH3_CM1       GTM_ATOM_5.CH3_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_5_CH3_CN0       GTM_ATOM_5.CH3_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_5_CH3_STAT      GTM_ATOM_5.CH3_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_5_CH3_IRQ_NOTIFY GTM_ATOM_5.CH3_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_5_CH3_IRQ_EN    GTM_ATOM_5.CH3_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_5_CH3_IRQ_FORCINT GTM_ATOM_5.CH3_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_5_CH3_IRQ_MODE  GTM_ATOM_5.CH3_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_5_CH4_RDADDR    GTM_ATOM_5.CH4_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_5_CH4_CTRL      GTM_ATOM_5.CH4_CTRL.R            /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_5_CH4_SR0       GTM_ATOM_5.CH4_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_5_CH4_SR1       GTM_ATOM_5.CH4_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_5_CH4_CM0       GTM_ATOM_5.CH4_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_5_CH4_CM1       GTM_ATOM_5.CH4_CM1.R               /* ATOM Channel n Compare Match 1 Register, n=0:7ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_5_CH4_CN0       GTM_ATOM_5.CH4_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_5_CH4_STAT      GTM_ATOM_5.CH4_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_5_CH4_IRQ_NOTIFY GTM_ATOM_5.CH4_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_5_CH4_IRQ_EN    GTM_ATOM_5.CH4_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_5_CH4_IRQ_FORCINT GTM_ATOM_5.CH4_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_5_CH4_IRQ_MODE  GTM_ATOM_5.CH4_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_5_CH5_RDADDR    GTM_ATOM_5.CH5_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_5_CH5_CTRL      GTM_ATOM_5.CH5_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_5_CH5_SR0       GTM_ATOM_5.CH5_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_5_CH5_SR1       GTM_ATOM_5.CH5_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_5_CH5_CM0       GTM_ATOM_5.CH5_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_5_CH5_CM1       GTM_ATOM_5.CH5_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_5_CH5_CN0       GTM_ATOM_5.CH5_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_5_CH5_STAT      GTM_ATOM_5.CH5_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_5_CH5_IRQ_NOTIFY GTM_ATOM_5.CH5_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_5_CH5_IRQ_EN    GTM_ATOM_5.CH5_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_5_CH5_IRQ_FORCINT GTM_ATOM_5.CH5_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_5_CH5_IRQ_MODE  GTM_ATOM_5.CH5_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_5_CH6_RDADDR    GTM_ATOM_5.CH6_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_5_CH6_CTRL      GTM_ATOM_5.CH6_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_5_CH6_SR0       GTM_ATOM_5.CH6_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_5_CH6_SR1       GTM_ATOM_5.CH6_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_5_CH6_CM0       GTM_ATOM_5.CH6_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_5_CH6_CM1       GTM_ATOM_5.CH6_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_5_CH6_CN0       GTM_ATOM_5.CH6_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_5_CH6_STAT      GTM_ATOM_5.CH6_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_5_CH6_IRQ_NOTIFY GTM_ATOM_5.CH6_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_5_CH6_IRQ_EN    GTM_ATOM_5.CH6_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_5_CH6_IRQ_FORCINT GTM_ATOM_5.CH6_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_5_CH6_IRQ_MODE  GTM_ATOM_5.CH6_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_5_CH7_RDADDR    GTM_ATOM_5.CH7_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_5_CH7_CTRL      GTM_ATOM_5.CH7_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_5_CH7_SR0       GTM_ATOM_5.CH7_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_5_CH7_SR1       GTM_ATOM_5.CH7_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_5_CH7_CM0       GTM_ATOM_5.CH7_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_5_CH7_CM1       GTM_ATOM_5.CH7_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_5_CH7_CN0       GTM_ATOM_5.CH7_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_5_CH7_STAT      GTM_ATOM_5.CH7_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_5_CH7_IRQ_NOTIFY GTM_ATOM_5.CH7_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_5_CH7_IRQ_EN    GTM_ATOM_5.CH7_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_5_CH7_IRQ_FORCINT GTM_ATOM_5.CH7_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_5_CH7_IRQ_MODE  GTM_ATOM_5.CH7_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7ATOM Channel n Interrupt Request Mode Register, n=0:7 */

/* GTM_ATOM */
#define GTM_ATOM_6_CH0_RDADDR    GTM_ATOM_6.CH0_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_6_CH0_CTRL      GTM_ATOM_6.CH0_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_6_CH0_SR0       GTM_ATOM_6.CH0_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_6_CH0_SR1       GTM_ATOM_6.CH0_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_6_CH0_CM0       GTM_ATOM_6.CH0_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_6_CH0_CM1       GTM_ATOM_6.CH0_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_6_CH0_CN0       GTM_ATOM_6.CH0_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_6_CH0_STAT      GTM_ATOM_6.CH0_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_6_CH0_IRQ_NOTIFY GTM_ATOM_6.CH0_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_6_CH0_IRQ_EN    GTM_ATOM_6.CH0_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_6_CH0_IRQ_FORCINT GTM_ATOM_6.CH0_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_6_CH0_IRQ_MODE  GTM_ATOM_6.CH0_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_6_AGC_GLB_CTRL  GTM_ATOM_6.AGC_GLB_CTRL.R         /* ATOM AGC Global Control Register */
#define GTM_ATOM_6_AGC_ENDIS_CTRL GTM_ATOM_6.AGC_ENDIS_CTRL.R      /* ATOM TGC0 Enable/Disable Control Register */
#define GTM_ATOM_6_AGC_ENDIS_STAT GTM_ATOM_6.AGC_ENDIS_STAT.R      /* ATOM TGC0 Enable/Disable Status Register */
#define GTM_ATOM_6_AGC_ACT_TB    GTM_ATOM_6.AGC_ACT_TB.R           /* ATOM TGC0 Action Time Base Register */
#define GTM_ATOM_6_AGC_OUTEN_CTRL GTM_ATOM_6.AGC_OUTEN_CTRL.R      /* ATOM TGC0 Out Enable Control Register */
#define GTM_ATOM_6_AGC_OUTEN_STAT GTM_ATOM_6.AGC_OUTEN_STAT.R      /* ATOM TGC0 Out Enable Control/Status Register */
#define GTM_ATOM_6_AGC_FUPD_CTRL GTM_ATOM_6.AGC_FUPD_CTRL.R        /* ATOM TGC0 Force Update Control Register */
#define GTM_ATOM_6_AGC_INT_TRIG  GTM_ATOM_6.AGC_INT_TRIG.R         /* ATOM TGC0 Interrupt Trigger Register */
#define GTM_ATOM_6_CH1_RDADDR    GTM_ATOM_6.CH1_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_6_CH1_CTRL      GTM_ATOM_6.CH1_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_6_CH1_SR0       GTM_ATOM_6.CH1_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_6_CH1_SR1       GTM_ATOM_6.CH1_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_6_CH1_CM0       GTM_ATOM_6.CH1_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_6_CH1_CM1       GTM_ATOM_6.CH1_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_6_CH1_CN0       GTM_ATOM_6.CH1_CN0.R               /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_6_CH1_STAT      GTM_ATOM_6.CH1_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_6_CH1_IRQ_NOTIFY GTM_ATOM_6.CH1_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_6_CH1_IRQ_EN    GTM_ATOM_6.CH1_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_6_CH1_IRQ_FORCINT GTM_ATOM_6.CH1_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_6_CH1_IRQ_MODE  GTM_ATOM_6.CH1_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_6_CH2_RDADDR    GTM_ATOM_6.CH2_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_6_CH2_CTRL      GTM_ATOM_6.CH2_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_6_CH2_SR0       GTM_ATOM_6.CH2_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_6_CH2_SR1       GTM_ATOM_6.CH2_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_6_CH2_CM0       GTM_ATOM_6.CH2_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_6_CH2_CM1       GTM_ATOM_6.CH2_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_6_CH2_CN0       GTM_ATOM_6.CH2_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_6_CH2_STAT      GTM_ATOM_6.CH2_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_6_CH2_IRQ_NOTIFY GTM_ATOM_6.CH2_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_6_CH2_IRQ_EN    GTM_ATOM_6.CH2_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_6_CH2_IRQ_FORCINT GTM_ATOM_6.CH2_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_6_CH2_IRQ_MODE  GTM_ATOM_6.CH2_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_6_CH3_RDADDR    GTM_ATOM_6.CH3_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_6_CH3_CTRL      GTM_ATOM_6.CH3_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_6_CH3_SR0       GTM_ATOM_6.CH3_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_6_CH3_SR1       GTM_ATOM_6.CH3_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_6_CH3_CM0       GTM_ATOM_6.CH3_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_6_CH3_CM1       GTM_ATOM_6.CH3_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_6_CH3_CN0       GTM_ATOM_6.CH3_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_6_CH3_STAT      GTM_ATOM_6.CH3_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_6_CH3_IRQ_NOTIFY GTM_ATOM_6.CH3_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_6_CH3_IRQ_EN    GTM_ATOM_6.CH3_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_6_CH3_IRQ_FORCINT GTM_ATOM_6.CH3_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_6_CH3_IRQ_MODE  GTM_ATOM_6.CH3_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_6_CH4_RDADDR    GTM_ATOM_6.CH4_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_6_CH4_CTRL      GTM_ATOM_6.CH4_CTRL.R            /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_6_CH4_SR0       GTM_ATOM_6.CH4_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_6_CH4_SR1       GTM_ATOM_6.CH4_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_6_CH4_CM0       GTM_ATOM_6.CH4_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_6_CH4_CM1       GTM_ATOM_6.CH4_CM1.R               /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_6_CH4_CN0       GTM_ATOM_6.CH4_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_6_CH4_STAT      GTM_ATOM_6.CH4_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_6_CH4_IRQ_NOTIFY GTM_ATOM_6.CH4_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_6_CH4_IRQ_EN    GTM_ATOM_6.CH4_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_6_CH4_IRQ_FORCINT GTM_ATOM_6.CH4_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_6_CH4_IRQ_MODE  GTM_ATOM_6.CH4_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_6_CH5_RDADDR    GTM_ATOM_6.CH5_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_6_CH5_CTRL      GTM_ATOM_6.CH5_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_6_CH5_SR0       GTM_ATOM_6.CH5_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_6_CH5_SR1       GTM_ATOM_6.CH5_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_6_CH5_CM0       GTM_ATOM_6.CH5_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_6_CH5_CM1       GTM_ATOM_6.CH5_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_6_CH5_CN0       GTM_ATOM_6.CH5_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_6_CH5_STAT      GTM_ATOM_6.CH5_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_6_CH5_IRQ_NOTIFY GTM_ATOM_6.CH5_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_6_CH5_IRQ_EN    GTM_ATOM_6.CH5_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_6_CH5_IRQ_FORCINT GTM_ATOM_6.CH5_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_6_CH5_IRQ_MODE  GTM_ATOM_6.CH5_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_6_CH6_RDADDR    GTM_ATOM_6.CH6_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_6_CH6_CTRL      GTM_ATOM_6.CH6_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_6_CH6_SR0       GTM_ATOM_6.CH6_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_6_CH6_SR1       GTM_ATOM_6.CH6_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_6_CH6_CM0       GTM_ATOM_6.CH6_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_6_CH6_CM1       GTM_ATOM_6.CH6_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_6_CH6_CN0       GTM_ATOM_6.CH6_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_6_CH6_STAT      GTM_ATOM_6.CH6_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_6_CH6_IRQ_NOTIFY GTM_ATOM_6.CH6_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_6_CH6_IRQ_EN    GTM_ATOM_6.CH6_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_6_CH6_IRQ_FORCINT GTM_ATOM_6.CH6_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_6_CH6_IRQ_MODE  GTM_ATOM_6.CH6_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_6_CH7_RDADDR    GTM_ATOM_6.CH7_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_6_CH7_CTRL      GTM_ATOM_6.CH7_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_6_CH7_SR0       GTM_ATOM_6.CH7_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_6_CH7_SR1       GTM_ATOM_6.CH7_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_6_CH7_CM0       GTM_ATOM_6.CH7_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_6_CH7_CM1       GTM_ATOM_6.CH7_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_6_CH7_CN0       GTM_ATOM_6.CH7_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_6_CH7_STAT      GTM_ATOM_6.CH7_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_6_CH7_IRQ_NOTIFY GTM_ATOM_6.CH7_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_6_CH7_IRQ_EN    GTM_ATOM_6.CH7_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_6_CH7_IRQ_FORCINT GTM_ATOM_6.CH7_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_6_CH7_IRQ_MODE  GTM_ATOM_6.CH7_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */

/* GTM_ATOM */
#define GTM_ATOM_7_CH0_RDADDR    GTM_ATOM_7.CH0_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_7_CH0_CTRL      GTM_ATOM_7.CH0_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_7_CH0_SR0       GTM_ATOM_7.CH0_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_7_CH0_SR1       GTM_ATOM_7.CH0_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_7_CH0_CM0       GTM_ATOM_7.CH0_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_7_CH0_CM1       GTM_ATOM_7.CH0_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_7_CH0_CN0       GTM_ATOM_7.CH0_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_7_CH0_STAT      GTM_ATOM_7.CH0_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_7_CH0_IRQ_NOTIFY GTM_ATOM_7.CH0_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_7_CH0_IRQ_EN    GTM_ATOM_7.CH0_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_7_CH0_IRQ_FORCINT GTM_ATOM_7.CH0_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_7_CH0_IRQ_MODE  GTM_ATOM_7.CH0_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_7_AGC_GLB_CTRL  GTM_ATOM_7.AGC_GLB_CTRL.R         /* ATOM AGC Global Control Register */
#define GTM_ATOM_7_AGC_ENDIS_CTRL GTM_ATOM_7.AGC_ENDIS_CTRL.R      /* ATOM TGC0 Enable/Disable Control Register */
#define GTM_ATOM_7_AGC_ENDIS_STAT GTM_ATOM_7.AGC_ENDIS_STAT.R      /* ATOM TGC0 Enable/Disable Status Register */
#define GTM_ATOM_7_AGC_ACT_TB    GTM_ATOM_7.AGC_ACT_TB.R           /* ATOM TGC0 Action Time Base RegisterATOM TGC0 Action Time Base Register */
#define GTM_ATOM_7_AGC_OUTEN_CTRL GTM_ATOM_7.AGC_OUTEN_CTRL.R      /* ATOM TGC0 Out Enable Control Register */
#define GTM_ATOM_7_AGC_OUTEN_STAT GTM_ATOM_7.AGC_OUTEN_STAT.R      /* ATOM TGC0 Out Enable Control/Status RegisterATOM TGC0 Out Enable Control/Status Register */
#define GTM_ATOM_7_AGC_FUPD_CTRL GTM_ATOM_7.AGC_FUPD_CTRL.R        /* ATOM TGC0 Force Update Control Register */
#define GTM_ATOM_7_AGC_INT_TRIG  GTM_ATOM_7.AGC_INT_TRIG.R         /* ATOM TGC0 Interrupt Trigger Register */
#define GTM_ATOM_7_CH1_RDADDR    GTM_ATOM_7.CH1_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_7_CH1_CTRL      GTM_ATOM_7.CH1_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_7_CH1_SR0       GTM_ATOM_7.CH1_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_7_CH1_SR1       GTM_ATOM_7.CH1_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_7_CH1_CM0       GTM_ATOM_7.CH1_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_7_CH1_CM1       GTM_ATOM_7.CH1_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_7_CH1_CN0       GTM_ATOM_7.CH1_CN0.R               /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_7_CH1_STAT      GTM_ATOM_7.CH1_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_7_CH1_IRQ_NOTIFY GTM_ATOM_7.CH1_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_7_CH1_IRQ_EN    GTM_ATOM_7.CH1_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_7_CH1_IRQ_FORCINT GTM_ATOM_7.CH1_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_7_CH1_IRQ_MODE  GTM_ATOM_7.CH1_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_7_CH2_RDADDR    GTM_ATOM_7.CH2_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_7_CH2_CTRL      GTM_ATOM_7.CH2_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_7_CH2_SR0       GTM_ATOM_7.CH2_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_7_CH2_SR1       GTM_ATOM_7.CH2_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_7_CH2_CM0       GTM_ATOM_7.CH2_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_7_CH2_CM1       GTM_ATOM_7.CH2_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_7_CH2_CN0       GTM_ATOM_7.CH2_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_7_CH2_STAT      GTM_ATOM_7.CH2_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_7_CH2_IRQ_NOTIFY GTM_ATOM_7.CH2_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_7_CH2_IRQ_EN    GTM_ATOM_7.CH2_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_7_CH2_IRQ_FORCINT GTM_ATOM_7.CH2_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_7_CH2_IRQ_MODE  GTM_ATOM_7.CH2_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_7_CH3_RDADDR    GTM_ATOM_7.CH3_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_7_CH3_CTRL      GTM_ATOM_7.CH3_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_7_CH3_SR0       GTM_ATOM_7.CH3_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_7_CH3_SR1       GTM_ATOM_7.CH3_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_7_CH3_CM0       GTM_ATOM_7.CH3_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_7_CH3_CM1       GTM_ATOM_7.CH3_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_7_CH3_CN0       GTM_ATOM_7.CH3_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_7_CH3_STAT      GTM_ATOM_7.CH3_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_7_CH3_IRQ_NOTIFY GTM_ATOM_7.CH3_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_7_CH3_IRQ_EN    GTM_ATOM_7.CH3_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_7_CH3_IRQ_FORCINT GTM_ATOM_7.CH3_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_7_CH3_IRQ_MODE  GTM_ATOM_7.CH3_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_7_CH4_RDADDR    GTM_ATOM_7.CH4_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_7_CH4_CTRL      GTM_ATOM_7.CH4_CTRL.R            /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_7_CH4_SR0       GTM_ATOM_7.CH4_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_7_CH4_SR1       GTM_ATOM_7.CH4_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_7_CH4_CM0       GTM_ATOM_7.CH4_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_7_CH4_CM1       GTM_ATOM_7.CH4_CM1.R               /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_7_CH4_CN0       GTM_ATOM_7.CH4_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_7_CH4_STAT      GTM_ATOM_7.CH4_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_7_CH4_IRQ_NOTIFY GTM_ATOM_7.CH4_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_7_CH4_IRQ_EN    GTM_ATOM_7.CH4_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_7_CH4_IRQ_FORCINT GTM_ATOM_7.CH4_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_7_CH4_IRQ_MODE  GTM_ATOM_7.CH4_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_7_CH5_RDADDR    GTM_ATOM_7.CH5_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_7_CH5_CTRL      GTM_ATOM_7.CH5_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_7_CH5_SR0       GTM_ATOM_7.CH5_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_7_CH5_SR1       GTM_ATOM_7.CH5_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_7_CH5_CM0       GTM_ATOM_7.CH5_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_7_CH5_CM1       GTM_ATOM_7.CH5_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_7_CH5_CN0       GTM_ATOM_7.CH5_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_7_CH5_STAT      GTM_ATOM_7.CH5_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_7_CH5_IRQ_NOTIFY GTM_ATOM_7.CH5_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_7_CH5_IRQ_EN    GTM_ATOM_7.CH5_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_7_CH5_IRQ_FORCINT GTM_ATOM_7.CH5_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_7_CH5_IRQ_MODE  GTM_ATOM_7.CH5_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_7_CH6_RDADDR    GTM_ATOM_7.CH6_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_7_CH6_CTRL      GTM_ATOM_7.CH6_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_7_CH6_SR0       GTM_ATOM_7.CH6_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_7_CH6_SR1       GTM_ATOM_7.CH6_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_7_CH6_CM0       GTM_ATOM_7.CH6_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_7_CH6_CM1       GTM_ATOM_7.CH6_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_7_CH6_CN0       GTM_ATOM_7.CH6_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_7_CH6_STAT      GTM_ATOM_7.CH6_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_7_CH6_IRQ_NOTIFY GTM_ATOM_7.CH6_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_7_CH6_IRQ_EN    GTM_ATOM_7.CH6_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_7_CH6_IRQ_FORCINT GTM_ATOM_7.CH6_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_7_CH6_IRQ_MODE  GTM_ATOM_7.CH6_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_7_CH7_RDADDR    GTM_ATOM_7.CH7_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_7_CH7_CTRL      GTM_ATOM_7.CH7_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_7_CH7_SR0       GTM_ATOM_7.CH7_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_7_CH7_SR1       GTM_ATOM_7.CH7_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_7_CH7_CM0       GTM_ATOM_7.CH7_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_7_CH7_CM1       GTM_ATOM_7.CH7_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_7_CH7_CN0       GTM_ATOM_7.CH7_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_7_CH7_STAT      GTM_ATOM_7.CH7_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_7_CH7_IRQ_NOTIFY GTM_ATOM_7.CH7_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_7_CH7_IRQ_EN    GTM_ATOM_7.CH7_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_7_CH7_IRQ_FORCINT GTM_ATOM_7.CH7_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_7_CH7_IRQ_MODE  GTM_ATOM_7.CH7_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */

/* GTM_ATOM */
#define GTM_ATOM_8_CH0_RDADDR    GTM_ATOM_8.CH0_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_8_CH0_CTRL      GTM_ATOM_8.CH0_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_8_CH0_SR0       GTM_ATOM_8.CH0_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_8_CH0_SR1       GTM_ATOM_8.CH0_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_8_CH0_CM0       GTM_ATOM_8.CH0_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_8_CH0_CM1       GTM_ATOM_8.CH0_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_8_CH0_CN0       GTM_ATOM_8.CH0_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_8_CH0_STAT      GTM_ATOM_8.CH0_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_8_CH0_IRQ_NOTIFY GTM_ATOM_8.CH0_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_8_CH0_IRQ_EN    GTM_ATOM_8.CH0_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_8_CH0_IRQ_FORCINT GTM_ATOM_8.CH0_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_8_CH0_IRQ_MODE  GTM_ATOM_8.CH0_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_8_AGC_GLB_CTRL  GTM_ATOM_8.AGC_GLB_CTRL.R         /* ATOM AGC Global Control Register */
#define GTM_ATOM_8_AGC_ENDIS_CTRL GTM_ATOM_8.AGC_ENDIS_CTRL.R      /* ATOM TGC0 Enable/Disable Control Register */
#define GTM_ATOM_8_AGC_ENDIS_STAT GTM_ATOM_8.AGC_ENDIS_STAT.R      /* ATOM TGC0 Enable/Disable Status Register */
#define GTM_ATOM_8_AGC_ACT_TB    GTM_ATOM_8.AGC_ACT_TB.R           /* ATOM TGC0 Action Time Base Register */
#define GTM_ATOM_8_AGC_OUTEN_CTRL GTM_ATOM_8.AGC_OUTEN_CTRL.R      /* ATOM TGC0 Out Enable Control Register */
#define GTM_ATOM_8_AGC_OUTEN_STAT GTM_ATOM_8.AGC_OUTEN_STAT.R      /* ATOM TGC0 Out Enable Control/Status Register */
#define GTM_ATOM_8_AGC_FUPD_CTRL GTM_ATOM_8.AGC_FUPD_CTRL.R        /* ATOM TGC0 Force Update Control Register */
#define GTM_ATOM_8_AGC_INT_TRIG  GTM_ATOM_8.AGC_INT_TRIG.R         /* ATOM TGC0 Interrupt Trigger Register */
#define GTM_ATOM_8_CH1_RDADDR    GTM_ATOM_8.CH1_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_8_CH1_CTRL      GTM_ATOM_8.CH1_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_8_CH1_SR0       GTM_ATOM_8.CH1_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_8_CH1_SR1       GTM_ATOM_8.CH1_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_8_CH1_CM0       GTM_ATOM_8.CH1_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_8_CH1_CM1       GTM_ATOM_8.CH1_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_8_CH1_CN0       GTM_ATOM_8.CH1_CN0.R               /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_8_CH1_STAT      GTM_ATOM_8.CH1_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_8_CH1_IRQ_NOTIFY GTM_ATOM_8.CH1_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_8_CH1_IRQ_EN    GTM_ATOM_8.CH1_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_8_CH1_IRQ_FORCINT GTM_ATOM_8.CH1_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_8_CH1_IRQ_MODE  GTM_ATOM_8.CH1_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_8_CH2_RDADDR    GTM_ATOM_8.CH2_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_8_CH2_CTRL      GTM_ATOM_8.CH2_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_8_CH2_SR0       GTM_ATOM_8.CH2_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_8_CH2_SR1       GTM_ATOM_8.CH2_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_8_CH2_CM0       GTM_ATOM_8.CH2_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_8_CH2_CM1       GTM_ATOM_8.CH2_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_8_CH2_CN0       GTM_ATOM_8.CH2_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_8_CH2_STAT      GTM_ATOM_8.CH2_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_8_CH2_IRQ_NOTIFY GTM_ATOM_8.CH2_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_8_CH2_IRQ_EN    GTM_ATOM_8.CH2_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_8_CH2_IRQ_FORCINT GTM_ATOM_8.CH2_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_8_CH2_IRQ_MODE  GTM_ATOM_8.CH2_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_8_CH3_RDADDR    GTM_ATOM_8.CH3_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_8_CH3_CTRL      GTM_ATOM_8.CH3_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_8_CH3_SR0       GTM_ATOM_8.CH3_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_8_CH3_SR1       GTM_ATOM_8.CH3_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_8_CH3_CM0       GTM_ATOM_8.CH3_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_8_CH3_CM1       GTM_ATOM_8.CH3_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_8_CH3_CN0       GTM_ATOM_8.CH3_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_8_CH3_STAT      GTM_ATOM_8.CH3_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_8_CH3_IRQ_NOTIFY GTM_ATOM_8.CH3_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_8_CH3_IRQ_EN    GTM_ATOM_8.CH3_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_8_CH3_IRQ_FORCINT GTM_ATOM_8.CH3_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_8_CH3_IRQ_MODE  GTM_ATOM_8.CH3_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_8_CH4_RDADDR    GTM_ATOM_8.CH4_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_8_CH4_CTRL      GTM_ATOM_8.CH4_CTRL.R            /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_8_CH4_SR0       GTM_ATOM_8.CH4_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_8_CH4_SR1       GTM_ATOM_8.CH4_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_8_CH4_CM0       GTM_ATOM_8.CH4_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_8_CH4_CM1       GTM_ATOM_8.CH4_CM1.R               /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_8_CH4_CN0       GTM_ATOM_8.CH4_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_8_CH4_STAT      GTM_ATOM_8.CH4_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_8_CH4_IRQ_NOTIFY GTM_ATOM_8.CH4_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_8_CH4_IRQ_EN    GTM_ATOM_8.CH4_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_8_CH4_IRQ_FORCINT GTM_ATOM_8.CH4_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_8_CH4_IRQ_MODE  GTM_ATOM_8.CH4_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_8_CH5_RDADDR    GTM_ATOM_8.CH5_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_8_CH5_CTRL      GTM_ATOM_8.CH5_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_8_CH5_SR0       GTM_ATOM_8.CH5_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_8_CH5_SR1       GTM_ATOM_8.CH5_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_8_CH5_CM0       GTM_ATOM_8.CH5_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_8_CH5_CM1       GTM_ATOM_8.CH5_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_8_CH5_CN0       GTM_ATOM_8.CH5_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_8_CH5_STAT      GTM_ATOM_8.CH5_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_8_CH5_IRQ_NOTIFY GTM_ATOM_8.CH5_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_8_CH5_IRQ_EN    GTM_ATOM_8.CH5_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_8_CH5_IRQ_FORCINT GTM_ATOM_8.CH5_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_8_CH5_IRQ_MODE  GTM_ATOM_8.CH5_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_8_CH6_RDADDR    GTM_ATOM_8.CH6_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_8_CH6_CTRL      GTM_ATOM_8.CH6_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_8_CH6_SR0       GTM_ATOM_8.CH6_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_8_CH6_SR1       GTM_ATOM_8.CH6_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_8_CH6_CM0       GTM_ATOM_8.CH6_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_8_CH6_CM1       GTM_ATOM_8.CH6_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_8_CH6_CN0       GTM_ATOM_8.CH6_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_8_CH6_STAT      GTM_ATOM_8.CH6_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_8_CH6_IRQ_NOTIFY GTM_ATOM_8.CH6_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_8_CH6_IRQ_EN    GTM_ATOM_8.CH6_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_8_CH6_IRQ_FORCINT GTM_ATOM_8.CH6_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_8_CH6_IRQ_MODE  GTM_ATOM_8.CH6_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_ATOM_8_CH7_RDADDR    GTM_ATOM_8.CH7_RDADDR.R           /* ATOM Channel n Read Address Register, n=0:7 */
#define GTM_ATOM_8_CH7_CTRL      GTM_ATOM_8.CH7_CTRL.R             /* ATOM Channel n Control Register, n=0:7 */
#define GTM_ATOM_8_CH7_SR0       GTM_ATOM_8.CH7_SR0.R              /* ATOM Channel n Shadow 0 Register, n=0:7ATOM Channel n Shadow 0 Register, n=0:7 */
#define GTM_ATOM_8_CH7_SR1       GTM_ATOM_8.CH7_SR1.R              /* ATOM Channel n Shadow 1 Register, n=0:7 */
#define GTM_ATOM_8_CH7_CM0       GTM_ATOM_8.CH7_CM0.R              /* ATOM Channel n Compare Match 0 Register, n=0:7 */
#define GTM_ATOM_8_CH7_CM1       GTM_ATOM_8.CH7_CM1.R              /* ATOM Channel n Compare Match 1 Register, n=0:7 */
#define GTM_ATOM_8_CH7_CN0       GTM_ATOM_8.CH7_CN0.R              /* ATOM Channel n Counter 0 Register, n=0:7 */
#define GTM_ATOM_8_CH7_STAT      GTM_ATOM_8.CH7_STAT.R             /* ATOM Channel n Status Register, n=0:7 */
#define GTM_ATOM_8_CH7_IRQ_NOTIFY GTM_ATOM_8.CH7_IRQ_NOTIFY.R      /* ATOM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_ATOM_8_CH7_IRQ_EN    GTM_ATOM_8.CH7_IRQ_EN.R           /* ATOM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_ATOM_8_CH7_IRQ_FORCINT GTM_ATOM_8.CH7_IRQ_FORCINT.R    /* ATOM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_ATOM_8_CH7_IRQ_MODE  GTM_ATOM_8.CH7_IRQ_MODE.R         /* ATOM Channel n Interrupt Request Mode Register, n=0:7 */

/* GTM_BRC */
#define GTM_BRC_SRC0_ADDR        GTM_BRC.SRC[0].ADDR.R             /* BRC Source n Address Register, n[0:11] */
#define GTM_BRC_SRC0_DEST        GTM_BRC.SRC[0].DEST.R             /* BRC Source n to Destination Register, n[0:11] */
#define GTM_BRC_SRC1_ADDR        GTM_BRC.SRC[1].ADDR.R             /* BRC Source n Address Register, n[0:11] */
#define GTM_BRC_SRC1_DEST        GTM_BRC.SRC[1].DEST.R             /* BRC Source n to Destination Register, n[0:11] */
#define GTM_BRC_SRC2_ADDR        GTM_BRC.SRC[2].ADDR.R             /* BRC Source n Address Register, n[0:11] */
#define GTM_BRC_SRC2_DEST        GTM_BRC.SRC[2].DEST.R             /* BRC Source n to Destination Register, n[0:11] */
#define GTM_BRC_SRC3_ADDR        GTM_BRC.SRC[3].ADDR.R             /* BRC Source n Address Register, n[0:11] */
#define GTM_BRC_SRC3_DEST        GTM_BRC.SRC[3].DEST.R             /* BRC Source n to Destination Register, n[0:11] */
#define GTM_BRC_SRC4_ADDR        GTM_BRC.SRC[4].ADDR.R             /* BRC Source n Address Register, n[0:11] */
#define GTM_BRC_SRC4_DEST        GTM_BRC.SRC[4].DEST.R             /* BRC Source n to Destination Register, n[0:11] */
#define GTM_BRC_SRC5_ADDR        GTM_BRC.SRC[5].ADDR.R             /* BRC Source n Address Register, n[0:11] */
#define GTM_BRC_SRC5_DEST        GTM_BRC.SRC[5].DEST.R             /* BRC Source n to Destination Register, n[0:11] */
#define GTM_BRC_SRC6_ADDR        GTM_BRC.SRC[6].ADDR.R             /* BRC Source n Address Register, n[0:11] */
#define GTM_BRC_SRC6_DEST        GTM_BRC.SRC[6].DEST.R             /* BRC Source n to Destination Register, n[0:11] */
#define GTM_BRC_SRC7_ADDR        GTM_BRC.SRC[7].ADDR.R             /* BRC Source n Address Register, n[0:11] */
#define GTM_BRC_SRC7_DEST        GTM_BRC.SRC[7].DEST.R             /* BRC Source n to Destination Register, n[0:11] */
#define GTM_BRC_SRC8_ADDR        GTM_BRC.SRC[8].ADDR.R             /* BRC Source n Address Register, n[0:11] */
#define GTM_BRC_SRC8_DEST        GTM_BRC.SRC[8].DEST.R             /* BRC Source n to Destination Register, n[0:11] */
#define GTM_BRC_SRC9_ADDR        GTM_BRC.SRC[9].ADDR.R             /* BRC Source n Address Register, n[0:11] */
#define GTM_BRC_SRC9_DEST        GTM_BRC.SRC[9].DEST.R             /* BRC Source n to Destination Register, n[0:11] */
#define GTM_BRC_SRC10_ADDR       GTM_BRC.SRC[10].ADDR.R            /* BRC Source n Address Register, n[0:11] */
#define GTM_BRC_SRC10_DEST       GTM_BRC.SRC[10].DEST.R            /* BRC Source n to Destination Register, n[0:11] */
#define GTM_BRC_SRC11_ADDR       GTM_BRC.SRC[11].ADDR.R            /* BRC Source n Address Register, n[0:11] */
#define GTM_BRC_SRC11_DEST       GTM_BRC.SRC[11].DEST.R            /* BRC Source n to Destination Register, n[0:11] */
#define GTM_BRC_IRQ_NOTIFY       GTM_BRC.IRQ_NOTIFY.R              /* BRC Interrupt Request Notification Register */
#define GTM_BRC_IRQ_EN           GTM_BRC.IRQ_EN.R                  /* BRC Interrupt Request Enable Register */
#define GTM_BRC_IRQ_FORCINT      GTM_BRC.IRQ_FORCINT.R             /* BRC Force Interrupt Request Register */
#define GTM_BRC_IRQ_MODE         GTM_BRC.IRQ_MODE.R                /* BRC Interrupt Request Mode Register */
#define GTM_BRC_RST              GTM_BRC.RST.R                     /* BRC Software Reset Register */
#define GTM_BRC_EIRQ_EN          GTM_BRC.EIRQ_EN.R                 /* BRC Error Interrupt Request Enable Register */

/* GTM_CMP */
#define GTM_CMP_EN               GTM_CMP.EN.R                      /* Compare Enable Register */
#define GTM_CMP_IRQ_NOTIFY       GTM_CMP.IRQ_NOTIFY.R              /* Compare Interrupt Request Notification Register */
#define GTM_CMP_IRQ_EN           GTM_CMP.IRQ_EN.R                  /* Compare Interrupt Request Enable Register */
#define GTM_CMP_IRQ_FORCINT      GTM_CMP.IRQ_FORCINT.R             /* Compare Force Interrupt Request Register */
#define GTM_CMP_IRQ_MODE         GTM_CMP.IRQ_MODE.R                /* Compare Interrupt Request Mode Register */
#define GTM_CMP_EIRQ_EN          GTM_CMP.EIRQ_EN.R                 /* Compare Error Interrupt Request Enable register */

/* GTM_CMU */
#define GTM_CMU_CLK_EN           GTM_CMU.CLK_EN.R                  /* CMU Clock Enable Register */
#define GTM_CMU_GCLK_NUM         GTM_CMU.GCLK_NUM.R                /* Global Clock Control Numerator Register */
#define GTM_CMU_GCLK_DEN         GTM_CMU.GCLK_DEN.R                /* Global Clock Control Denominator Register */
#define GTM_CMU_CLK_0_CTRL       GTM_CMU.CLK_CTRL[0].R            /* Control for Clock Source n register */
#define GTM_CMU_CLK_1_CTRL       GTM_CMU.CLK_CTRL[1].R            /* Control for Clock Source n register */
#define GTM_CMU_CLK_2_CTRL       GTM_CMU.CLK_CTRL[2].R            /* Control for Clock Source n register */
#define GTM_CMU_CLK_3_CTRL       GTM_CMU.CLK_CTRL[3].R            /* Control for Clock Source n register */
#define GTM_CMU_CLK_4_CTRL       GTM_CMU.CLK_CTRL[4].R            /* Control for Clock Source n register */
#define GTM_CMU_CLK_5_CTRL       GTM_CMU.CLK_CTRL[5].R            /* Control for Clock Source n register */
#define GTM_CMU_CLK_6_CTRL       GTM_CMU.CLK_6_CTRL.R              /* Control for Clock Source 6 register */
#define GTM_CMU_CLK_7_CTRL       GTM_CMU.CLK_7_CTRL.R              /* Control for Clock Source 7 register */
#define GTM_CMU_ECLK0_NUM        GTM_CMU.ECLK[0].NUM.R             /* CMU External Clock n Numerator Register */
#define GTM_CMU_ECLK0__DEN       GTM_CMU.ECLK[0].DEN.R             /* CMU External Clock n Denominator Register */
#define GTM_CMU_ECLK1_NUM        GTM_CMU.ECLK[1].NUM.R             /* CMU External Clock n Numerator Register */
#define GTM_CMU_ECLK1__DEN       GTM_CMU.ECLK[1].DEN.R             /* CMU External Clock n Denominator Register */
#define GTM_CMU_ECLK2_NUM        GTM_CMU.ECLK[2].NUM.R             /* CMU External Clock n Numerator Register */
#define GTM_CMU_ECLK2__DEN       GTM_CMU.ECLK[2].DEN.R             /* CMU External Clock n Denominator Register */
#define GTM_CMU_FXCLK_CTRL       GTM_CMU.FXCLK_CTRL.R              /* CMU FX Clock Control register */

/* GTM_DPLL */
#define GTM_DPLL_CTRL_0          GTM_DPLL.CTRL_0.R                 /* Control Register 0 */
#define GTM_DPLL_CTRL_1          GTM_DPLL.CTRL_1.R                 /* Control Register 1 */
#define GTM_DPLL_CTRL_2          GTM_DPLL.CTRL_2.R                 /* Action Enable Register */
#define GTM_DPLL_CTRL_3          GTM_DPLL.CTRL_3.R                 /* Action Enable Register */
#define GTM_DPLL_CTRL_4          GTM_DPLL.CTRL_4.R                 /* Action Enable Register */
#define GTM_DPLL_CTRL_5          GTM_DPLL.CTRL_5.R                 /* Action Enable Register */
#define GTM_DPLL_ACT_STA         GTM_DPLL.ACT_STA.R                /* Action Status Register including Shadow Register */
#define GTM_DPLL_OSW             GTM_DPLL.OSW.R                    /* Offset and Switch Old/New Address Register */
#define GTM_DPLL_AOSV_2          GTM_DPLL.AOSV_2.R                 /* Address Offset Register of RAM2 Regions */
#define GTM_DPLL_APT             GTM_DPLL.APT.R                    /* Actual RAM Pointer Address for Trigger */
#define GTM_DPLL_APS             GTM_DPLL.APS.R                    /* Actual RAM Pointer Address for STATE */
#define GTM_DPLL_APT_2C          GTM_DPLL.APT_2C.R                 /* Actual RAM Pointer Address for Region 2C */
#define GTM_DPLL_APS_1C3         GTM_DPLL.APS_1C3.R                /* Actual RAM Pointer Address for Region 1C3 */
#define GTM_DPLL_NUTC            GTM_DPLL.NUTC.R                   /* Number of Recent TRIGGER Events used for Calculations */
#define GTM_DPLL_NUSC            GTM_DPLL.NUSC.R                   /* Number of Recent STATE Events used for Calculations */
#define GTM_DPLL_NTI_CNT         GTM_DPLL.NTI_CNT.R                /* Number of Active TRIGGER Events to Interrupt */
#define GTM_DPLL_IRQ_NOTIFY      GTM_DPLL.IRQ_NOTIFY.R             /* Interrupt Register */
#define GTM_DPLL_IRQ_EN          GTM_DPLL.IRQ_EN.R                 /* Interrupt Enable Register */
#define GTM_DPLL_IRQ_FORCINT     GTM_DPLL.IRQ_FORCINT.R            /* Force Interrupt Register */
#define GTM_DPLL_IRQ_MODE        GTM_DPLL.IRQ_MODE.R               /* Interrupt Request Mode */
#define GTM_DPLL_EIRQ_EN         GTM_DPLL.EIRQ_EN.R                /* Error Interrupt Enable Register */
#define GTM_DPLL_INC_CNT1        GTM_DPLL.INC_CNT1.R               /* Counter Value of Sent SUB_INC1 Pulses */
#define GTM_DPLL_INC_CNT2        GTM_DPLL.INC_CNT2.R               /* Counter Value of sent SUB_INC2 values (for SMC=1 and RMO=1) */
#define GTM_DPLL_APT_SYNC        GTM_DPLL.APT_SYNC.R               /* TRIGGER Time Stamp Field Offset at Synchronization Time */
#define GTM_DPLL_APS_SYNC        GTM_DPLL.APS_SYNC.R               /* STATE Time Stamp Field Offset at Synchronization Time */
#define GTM_DPLL_TBU_TS0_T       GTM_DPLL.TBU_TS0_T.R              /* Time Stamp Value for the last valid TRIGGER */
#define GTM_DPLL_TBU_TS0_S       GTM_DPLL.TBU_TS0_S.R              /* Time Stamp Value for the last valid STATE */
#define GTM_DPLL_ADD_IN_LD1      GTM_DPLL.ADD_IN_LD1.R             /* ADD_IN Value in Direct Load Mode for TRIGGER */
#define GTM_DPLL_ADD_IN_LD2      GTM_DPLL.ADD_IN_LD2.R             /* ADD_IN Value in Direct Load Mode for STATE */
#define GTM_DPLL_STATUS          GTM_DPLL.STATUS.R                 /* Status Register */
#define GTM_DPLL_ID_PMTR_0       GTM_DPLL.ID_PMTR[0].R            /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_1       GTM_DPLL.ID_PMTR[1].R            /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_2       GTM_DPLL.ID_PMTR[2].R            /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_3       GTM_DPLL.ID_PMTR[3].R            /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_4       GTM_DPLL.ID_PMTR[4].R            /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_5       GTM_DPLL.ID_PMTR[5].R            /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_6       GTM_DPLL.ID_PMTR[6].R            /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_7       GTM_DPLL.ID_PMTR[7].R            /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_8       GTM_DPLL.ID_PMTR[8].R            /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_9       GTM_DPLL.ID_PMTR[9].R            /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_10      GTM_DPLL.ID_PMTR[10].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_11      GTM_DPLL.ID_PMTR[11].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_12      GTM_DPLL.ID_PMTR[12].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_13      GTM_DPLL.ID_PMTR[13].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_14      GTM_DPLL.ID_PMTR[14].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_15      GTM_DPLL.ID_PMTR[15].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_16      GTM_DPLL.ID_PMTR[16].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_17      GTM_DPLL.ID_PMTR[17].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_18      GTM_DPLL.ID_PMTR[18].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_19      GTM_DPLL.ID_PMTR[19].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_20      GTM_DPLL.ID_PMTR[20].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_21      GTM_DPLL.ID_PMTR[21].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_22      GTM_DPLL.ID_PMTR[22].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_23      GTM_DPLL.ID_PMTR[23].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_24      GTM_DPLL.ID_PMTR[24].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_25      GTM_DPLL.ID_PMTR[25].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_26      GTM_DPLL.ID_PMTR[26].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_27      GTM_DPLL.ID_PMTR[27].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_28      GTM_DPLL.ID_PMTR[28].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_29      GTM_DPLL.ID_PMTR[29].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_30      GTM_DPLL.ID_PMTR[30].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_ID_PMTR_31      GTM_DPLL.ID_PMTR[31].R           /* ID Information for In ut Signal PTR x (Position minus Time Request) */
#define GTM_DPLL_CTRL_0_SHADOW_TRIGGER GTM_DPLL.CTRL_0_SHADOW_TRIGGER.R /* Shadow Register of DPLL_CTRL_0 controlled by a valid TRIGGER Slope */
#define GTM_DPLL_CTRL_0_SHADOW_STATE GTM_DPLL.CTRL_0_SHADOW_STATE.R /* Shadow Register of DPLL_CTRL_0 controlled by a valid STATE Slope */
#define GTM_DPLL_CTRL_1_SHADOW_TRIGGER GTM_DPLL.CTRL_1_SHADOW_TRIGGER.R /* Shadow Register of DPLL_CTRL_1 controlled by a valid TRIGGER Slope */
#define GTM_DPLL_CTRL_1_SHADOW_STATE GTM_DPLL.CTRL_1_SHADOW_STATE.R /* Shadow Register of DPLL_CTRL_1 controlled by a valid STATE Slope */
#define GTM_DPLL_RAM_INI         GTM_DPLL.RAM_INI.R                /* Register to control the RAM Initialization */
#define GTM_DPLL_TSAC_0          GTM_DPLL.TSAC[0].R               /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_1          GTM_DPLL.TSAC[1].R               /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_2          GTM_DPLL.TSAC[2].R               /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_3          GTM_DPLL.TSAC[3].R               /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_4          GTM_DPLL.TSAC[4].R               /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_5          GTM_DPLL.TSAC[5].R               /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_6          GTM_DPLL.TSAC[6].R               /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_7          GTM_DPLL.TSAC[7].R               /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_8          GTM_DPLL.TSAC[8].R               /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_9          GTM_DPLL.TSAC[9].R               /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_10         GTM_DPLL.TSAC[10].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_11         GTM_DPLL.TSAC[11].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_12         GTM_DPLL.TSAC[12].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_13         GTM_DPLL.TSAC[13].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_14         GTM_DPLL.TSAC[14].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_15         GTM_DPLL.TSAC[15].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_16         GTM_DPLL.TSAC[16].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_17         GTM_DPLL.TSAC[17].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_18         GTM_DPLL.TSAC[18].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_19         GTM_DPLL.TSAC[19].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_20         GTM_DPLL.TSAC[20].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_21         GTM_DPLL.TSAC[21].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_22         GTM_DPLL.TSAC[22].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_23         GTM_DPLL.TSAC[23].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_24         GTM_DPLL.TSAC[24].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_25         GTM_DPLL.TSAC[25].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_26         GTM_DPLL.TSAC[26].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_27         GTM_DPLL.TSAC[27].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_28         GTM_DPLL.TSAC[28].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_29         GTM_DPLL.TSAC[29].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_30         GTM_DPLL.TSAC[30].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_TSAC_31         GTM_DPLL.TSAC[31].R              /* Calculated Time Value to start Action i */
#define GTM_DPLL_PSAC_0          GTM_DPLL.PSAC[0].R               /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_1          GTM_DPLL.PSAC[1].R               /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_2          GTM_DPLL.PSAC[2].R               /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_3          GTM_DPLL.PSAC[3].R               /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_4          GTM_DPLL.PSAC[4].R               /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_5          GTM_DPLL.PSAC[5].R               /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_6          GTM_DPLL.PSAC[6].R               /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_7          GTM_DPLL.PSAC[7].R               /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_8          GTM_DPLL.PSAC[8].R               /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_9          GTM_DPLL.PSAC[9].R               /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_10         GTM_DPLL.PSAC[10].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_11         GTM_DPLL.PSAC[11].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_12         GTM_DPLL.PSAC[12].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_13         GTM_DPLL.PSAC[13].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_14         GTM_DPLL.PSAC[14].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_15         GTM_DPLL.PSAC[15].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_16         GTM_DPLL.PSAC[16].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_17         GTM_DPLL.PSAC[17].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_18         GTM_DPLL.PSAC[18].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_19         GTM_DPLL.PSAC[19].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_20         GTM_DPLL.PSAC[20].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_21         GTM_DPLL.PSAC[21].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_22         GTM_DPLL.PSAC[22].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_23         GTM_DPLL.PSAC[23].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_24         GTM_DPLL.PSAC[24].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_25         GTM_DPLL.PSAC[25].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_26         GTM_DPLL.PSAC[26].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_27         GTM_DPLL.PSAC[27].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_28         GTM_DPLL.PSAC[28].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_29         GTM_DPLL.PSAC[29].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_30         GTM_DPLL.PSAC[30].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_PSAC_31         GTM_DPLL.PSAC[31].R              /* DPLL Calculated Position Value ACTION i */
#define GTM_DPLL_ACB_0           GTM_DPLL.ACB[0].R                /* Control Bits for up to 32 Actions */
#define GTM_DPLL_ACB_1           GTM_DPLL.ACB[1].R                /* Control Bits for up to 32 Actions */
#define GTM_DPLL_ACB_2           GTM_DPLL.ACB[2].R                /* Control Bits for up to 32 Actions */
#define GTM_DPLL_ACB_3           GTM_DPLL.ACB[3].R                /* Control Bits for up to 32 Actions */
#define GTM_DPLL_ACB_4           GTM_DPLL.ACB[4].R                /* Control Bits for up to 32 Actions */
#define GTM_DPLL_ACB_5           GTM_DPLL.ACB[5].R                /* Control Bits for up to 32 Actions */
#define GTM_DPLL_ACB_6           GTM_DPLL.ACB[6].R                /* Control Bits for up to 32 Actions */
#define GTM_DPLL_ACB_7           GTM_DPLL.ACB[7].R                /* Control Bits for up to 32 Actions */

/* GTM_F2A */
#define GTM_F2A_0_CH0_ARU_RD_FIFO GTM_F2A_0.CH_ARU_RD_FIFO[0].R    /* F2A Read Channel n Address Register, n=0:7 */
#define GTM_F2A_0_CH1_ARU_RD_FIFO GTM_F2A_0.CH_ARU_RD_FIFO[1].R    /* F2A Read Channel n Address Register, n=0:7 */
#define GTM_F2A_0_CH2_ARU_RD_FIFO GTM_F2A_0.CH_ARU_RD_FIFO[2].R    /* F2A Read Channel n Address Register, n=0:7 */
#define GTM_F2A_0_CH3_ARU_RD_FIFO GTM_F2A_0.CH_ARU_RD_FIFO[3].R    /* F2A Read Channel n Address Register, n=0:7 */
#define GTM_F2A_0_CH4_ARU_RD_FIFO GTM_F2A_0.CH_ARU_RD_FIFO[4].R    /* F2A Read Channel n Address Register, n=0:7 */
#define GTM_F2A_0_CH5_ARU_RD_FIFO GTM_F2A_0.CH_ARU_RD_FIFO[5].R    /* F2A Read Channel n Address Register, n=0:7 */
#define GTM_F2A_0_CH6_ARU_RD_FIFO GTM_F2A_0.CH_ARU_RD_FIFO[6].R    /* F2A Read Channel n Address Register, n=0:7 */
#define GTM_F2A_0_CH7_ARU_RD_FIFO GTM_F2A_0.CH_ARU_RD_FIFO[7].R    /* F2A Read Channel n Address Register, n=0:7 */
#define GTM_F2A_0_CH0_STR_CFG    GTM_F2A_0.CH_STR_CFG[0].R         /* F2A Channel n Stream Configuration Register, n=0:7 */
#define GTM_F2A_0_CH1_STR_CFG    GTM_F2A_0.CH_STR_CFG[1].R         /* F2A Channel n Stream Configuration Register, n=0:7 */
#define GTM_F2A_0_CH2_STR_CFG    GTM_F2A_0.CH_STR_CFG[2].R         /* F2A Channel n Stream Configuration Register, n=0:7 */
#define GTM_F2A_0_CH3_STR_CFG    GTM_F2A_0.CH_STR_CFG[3].R         /* F2A Channel n Stream Configuration Register, n=0:7 */
#define GTM_F2A_0_CH4_STR_CFG    GTM_F2A_0.CH_STR_CFG[4].R         /* F2A Channel n Stream Configuration Register, n=0:7 */
#define GTM_F2A_0_CH5_STR_CFG    GTM_F2A_0.CH_STR_CFG[5].R         /* F2A Channel n Stream Configuration Register, n=0:7 */
#define GTM_F2A_0_CH6_STR_CFG    GTM_F2A_0.CH_STR_CFG[6].R         /* F2A Channel n Stream Configuration Register, n=0:7 */
#define GTM_F2A_0_CH7_STR_CFG    GTM_F2A_0.CH_STR_CFG[7].R         /* F2A Channel n Stream Configuration Register, n=0:7 */
#define GTM_F2A_0_ENABLE         GTM_F2A_0.ENABLE.R                /* F2A Stream Activation Register */

/* GTM_F2A */
#define GTM_F2A_1_CH0_ARU_RD_FIFO GTM_F2A_1.CH_ARU_RD_FIFO[0].R    /* F2A Read Channel n Address Register, n=0:7 */
#define GTM_F2A_1_CH1_ARU_RD_FIFO GTM_F2A_1.CH_ARU_RD_FIFO[1].R    /* F2A Read Channel n Address Register, n=0:7 */
#define GTM_F2A_1_CH2_ARU_RD_FIFO GTM_F2A_1.CH_ARU_RD_FIFO[2].R    /* F2A Read Channel n Address Register, n=0:7 */
#define GTM_F2A_1_CH3_ARU_RD_FIFO GTM_F2A_1.CH_ARU_RD_FIFO[3].R    /* F2A Read Channel n Address Register, n=0:7 */
#define GTM_F2A_1_CH4_ARU_RD_FIFO GTM_F2A_1.CH_ARU_RD_FIFO[4].R    /* F2A Read Channel n Address Register, n=0:7 */
#define GTM_F2A_1_CH5_ARU_RD_FIFO GTM_F2A_1.CH_ARU_RD_FIFO[5].R    /* F2A Read Channel n Address Register, n=0:7 */
#define GTM_F2A_1_CH6_ARU_RD_FIFO GTM_F2A_1.CH_ARU_RD_FIFO[6].R    /* F2A Read Channel n Address Register, n=0:7 */
#define GTM_F2A_1_CH7_ARU_RD_FIFO GTM_F2A_1.CH_ARU_RD_FIFO[7].R    /* F2A Read Channel n Address Register, n=0:7 */
#define GTM_F2A_1_CH0_STR_CFG    GTM_F2A_1.CH_STR_CFG[0].R         /* F2A Channel n Stream Configuration Register, n=0:7 */
#define GTM_F2A_1_CH1_STR_CFG    GTM_F2A_1.CH_STR_CFG[1].R         /* F2A Channel n Stream Configuration Register, n=0:7 */
#define GTM_F2A_1_CH2_STR_CFG    GTM_F2A_1.CH_STR_CFG[2].R         /* F2A Channel n Stream Configuration Register, n=0:7 */
#define GTM_F2A_1_CH3_STR_CFG    GTM_F2A_1.CH_STR_CFG[3].R         /* F2A Channel n Stream Configuration Register, n=0:7 */
#define GTM_F2A_1_CH4_STR_CFG    GTM_F2A_1.CH_STR_CFG[4].R         /* F2A Channel n Stream Configuration Register, n=0:7 */
#define GTM_F2A_1_CH5_STR_CFG    GTM_F2A_1.CH_STR_CFG[5].R         /* F2A Channel n Stream Configuration Register, n=0:7 */
#define GTM_F2A_1_CH6_STR_CFG    GTM_F2A_1.CH_STR_CFG[6].R         /* F2A Channel n Stream Configuration Register, n=0:7 */
#define GTM_F2A_1_CH7_STR_CFG    GTM_F2A_1.CH_STR_CFG[7].R         /* F2A Channel n Stream Configuration Register, n=0:7 */
#define GTM_F2A_1_ENABLE         GTM_F2A_1.ENABLE.R                /* F2A Stream Activation Register */

/* GTM_FIFO */
#define GTM_FIFO_0_CH0_CTRL      GTM_FIFO_0.CHANNEL[0].CTRL.R      /* FIFO Channel Control Register */
#define GTM_FIFO_0_CH0_END_ADDR  GTM_FIFO_0.CHANNEL[0].END_ADDR.R  /* FIFO Channel End Address Register */
#define GTM_FIFO_0_CH0_START_ADDR GTM_FIFO_0.CHANNEL[0].START_ADDR.R /* FIFO Channel Start Address Register */
#define GTM_FIFO_0_CH0_UPPER_WM  GTM_FIFO_0.CHANNEL[0].UPPER_WM.R  /* FIFO Channel Upper Watermark Register */
#define GTM_FIFO_0_CH0_LOWER_WM  GTM_FIFO_0.CHANNEL[0].LOWER_WM.R  /* FIFO Channel Lower Watermark Register */
#define GTM_FIFO_0_CH0_STATUS    GTM_FIFO_0.CHANNEL[0].STATUS.R    /* FIFO Channel Status Register */
#define GTM_FIFO_0_CH0_FILL_LEVEL GTM_FIFO_0.CHANNEL[0].FILL_LEVEL.R /* FIFO Channel Fill Level Register */
#define GTM_FIFO_0_CH0_WR_PTR    GTM_FIFO_0.CHANNEL[0].WR_PTR.R    /* FIFO Channel Write Pointer Register */
#define GTM_FIFO_0_CH0_RD_PTR    GTM_FIFO_0.CHANNEL[0].RD_PTR.R    /* FIFO Channel Read Pointer */
#define GTM_FIFO_0_CH0_IRQ_NOTIFY GTM_FIFO_0.CHANNEL[0].IRQ_NOTIFY.R /* FIFO Channel IRQ Notification Register */
#define GTM_FIFO_0_CH0_IRQ_EN    GTM_FIFO_0.CHANNEL[0].IRQ_EN.R    /* FIFO Channel IRQ Enable Register */
#define GTM_FIFO_0_CH0_IRQ_FORCINT GTM_FIFO_0.CHANNEL[0].IRQ_FORCINT.R /* FIFO Channel Force Interrupt Register */
#define GTM_FIFO_0_CH0_IRQ_MODE  GTM_FIFO_0.CHANNEL[0].IRQ_MODE.R  /* FIFO Channel IRQ Mode Register */
#define GTM_FIFO_0_CH0_EIRQ_EN   GTM_FIFO_0.CHANNEL[0].EIRQ_EN.R   /* FIFO Channel Error Interrupt Request Register */
#define GTM_FIFO_0_CH1_CTRL      GTM_FIFO_0.CHANNEL[1].CTRL.R      /* FIFO Channel Control Register */
#define GTM_FIFO_0_CH1_END_ADDR  GTM_FIFO_0.CHANNEL[1].END_ADDR.R  /* FIFO Channel End Address Register */
#define GTM_FIFO_0_CH1_START_ADDR GTM_FIFO_0.CHANNEL[1].START_ADDR.R /* FIFO Channel Start Address Register */
#define GTM_FIFO_0_CH1_UPPER_WM  GTM_FIFO_0.CHANNEL[1].UPPER_WM.R  /* FIFO Channel Upper Watermark Register */
#define GTM_FIFO_0_CH1_LOWER_WM  GTM_FIFO_0.CHANNEL[1].LOWER_WM.R  /* FIFO Channel Lower Watermark Register */
#define GTM_FIFO_0_CH1_STATUS    GTM_FIFO_0.CHANNEL[1].STATUS.R    /* FIFO Channel Status Register */
#define GTM_FIFO_0_CH1_FILL_LEVEL GTM_FIFO_0.CHANNEL[1].FILL_LEVEL.R /* FIFO Channel Fill Level Register */
#define GTM_FIFO_0_CH1_WR_PTR    GTM_FIFO_0.CHANNEL[1].WR_PTR.R    /* FIFO Channel Write Pointer Register */
#define GTM_FIFO_0_CH1_RD_PTR    GTM_FIFO_0.CHANNEL[1].RD_PTR.R    /* FIFO Channel Read Pointer */
#define GTM_FIFO_0_CH1_IRQ_NOTIFY GTM_FIFO_0.CHANNEL[1].IRQ_NOTIFY.R /* FIFO Channel IRQ Notification Register */
#define GTM_FIFO_0_CH1_IRQ_EN    GTM_FIFO_0.CHANNEL[1].IRQ_EN.R    /* FIFO Channel IRQ Enable Register */
#define GTM_FIFO_0_CH1_IRQ_FORCINT GTM_FIFO_0.CHANNEL[1].IRQ_FORCINT.R /* FIFO Channel Force Interrupt Register */
#define GTM_FIFO_0_CH1_IRQ_MODE  GTM_FIFO_0.CHANNEL[1].IRQ_MODE.R  /* FIFO Channel IRQ Mode Register */
#define GTM_FIFO_0_CH1_EIRQ_EN   GTM_FIFO_0.CHANNEL[1].EIRQ_EN.R   /* FIFO Channel Error Interrupt Request Register */
#define GTM_FIFO_0_CH2_CTRL      GTM_FIFO_0.CHANNEL[2].CTRL.R      /* FIFO Channel Control Register */
#define GTM_FIFO_0_CH2_END_ADDR  GTM_FIFO_0.CHANNEL[2].END_ADDR.R  /* FIFO Channel End Address Register */
#define GTM_FIFO_0_CH2_START_ADDR GTM_FIFO_0.CHANNEL[2].START_ADDR.R /* FIFO Channel Start Address Register */
#define GTM_FIFO_0_CH2_UPPER_WM  GTM_FIFO_0.CHANNEL[2].UPPER_WM.R  /* FIFO Channel Upper Watermark Register */
#define GTM_FIFO_0_CH2_LOWER_WM  GTM_FIFO_0.CHANNEL[2].LOWER_WM.R  /* FIFO Channel Lower Watermark Register */
#define GTM_FIFO_0_CH2_STATUS    GTM_FIFO_0.CHANNEL[2].STATUS.R    /* FIFO Channel Status Register */
#define GTM_FIFO_0_CH2_FILL_LEVEL GTM_FIFO_0.CHANNEL[2].FILL_LEVEL.R /* FIFO Channel Fill Level Register */
#define GTM_FIFO_0_CH2_WR_PTR    GTM_FIFO_0.CHANNEL[2].WR_PTR.R    /* FIFO Channel Write Pointer Register */
#define GTM_FIFO_0_CH2_RD_PTR    GTM_FIFO_0.CHANNEL[2].RD_PTR.R    /* FIFO Channel Read Pointer */
#define GTM_FIFO_0_CH2_IRQ_NOTIFY GTM_FIFO_0.CHANNEL[2].IRQ_NOTIFY.R /* FIFO Channel IRQ Notification Register */
#define GTM_FIFO_0_CH2_IRQ_EN    GTM_FIFO_0.CHANNEL[2].IRQ_EN.R    /* FIFO Channel IRQ Enable Register */
#define GTM_FIFO_0_CH2_IRQ_FORCINT GTM_FIFO_0.CHANNEL[2].IRQ_FORCINT.R /* FIFO Channel Force Interrupt Register */
#define GTM_FIFO_0_CH2_IRQ_MODE  GTM_FIFO_0.CHANNEL[2].IRQ_MODE.R  /* FIFO Channel IRQ Mode Register */
#define GTM_FIFO_0_CH2_EIRQ_EN   GTM_FIFO_0.CHANNEL[2].EIRQ_EN.R   /* FIFO Channel Error Interrupt Request Register */
#define GTM_FIFO_0_CH3_CTRL      GTM_FIFO_0.CHANNEL[3].CTRL.R      /* FIFO Channel Control Register */
#define GTM_FIFO_0_CH3_END_ADDR  GTM_FIFO_0.CHANNEL[3].END_ADDR.R  /* FIFO Channel End Address Register */
#define GTM_FIFO_0_CH3_START_ADDR GTM_FIFO_0.CHANNEL[3].START_ADDR.R /* FIFO Channel Start Address Register */
#define GTM_FIFO_0_CH3_UPPER_WM  GTM_FIFO_0.CHANNEL[3].UPPER_WM.R  /* FIFO Channel Upper Watermark Register */
#define GTM_FIFO_0_CH3_LOWER_WM  GTM_FIFO_0.CHANNEL[3].LOWER_WM.R  /* FIFO Channel Lower Watermark Register */
#define GTM_FIFO_0_CH3_STATUS    GTM_FIFO_0.CHANNEL[3].STATUS.R    /* FIFO Channel Status Register */
#define GTM_FIFO_0_CH3_FILL_LEVEL GTM_FIFO_0.CHANNEL[3].FILL_LEVEL.R /* FIFO Channel Fill Level Register */
#define GTM_FIFO_0_CH3_WR_PTR    GTM_FIFO_0.CHANNEL[3].WR_PTR.R    /* FIFO Channel Write Pointer Register */
#define GTM_FIFO_0_CH3_RD_PTR    GTM_FIFO_0.CHANNEL[3].RD_PTR.R    /* FIFO Channel Read Pointer */
#define GTM_FIFO_0_CH3_IRQ_NOTIFY GTM_FIFO_0.CHANNEL[3].IRQ_NOTIFY.R /* FIFO Channel IRQ Notification Register */
#define GTM_FIFO_0_CH3_IRQ_EN    GTM_FIFO_0.CHANNEL[3].IRQ_EN.R    /* FIFO Channel IRQ Enable Register */
#define GTM_FIFO_0_CH3_IRQ_FORCINT GTM_FIFO_0.CHANNEL[3].IRQ_FORCINT.R /* FIFO Channel Force Interrupt Register */
#define GTM_FIFO_0_CH3_IRQ_MODE  GTM_FIFO_0.CHANNEL[3].IRQ_MODE.R  /* FIFO Channel IRQ Mode Register */
#define GTM_FIFO_0_CH3_EIRQ_EN   GTM_FIFO_0.CHANNEL[3].EIRQ_EN.R   /* FIFO Channel Error Interrupt Request Register */
#define GTM_FIFO_0_CH4_CTRL      GTM_FIFO_0.CHANNEL[4].CTRL.R      /* FIFO Channel Control Register */
#define GTM_FIFO_0_CH4_END_ADDR  GTM_FIFO_0.CHANNEL[4].END_ADDR.R  /* FIFO Channel End Address Register */
#define GTM_FIFO_0_CH4_START_ADDR GTM_FIFO_0.CHANNEL[4].START_ADDR.R /* FIFO Channel Start Address Register */
#define GTM_FIFO_0_CH4_UPPER_WM  GTM_FIFO_0.CHANNEL[4].UPPER_WM.R  /* FIFO Channel Upper Watermark Register */
#define GTM_FIFO_0_CH4_LOWER_WM  GTM_FIFO_0.CHANNEL[4].LOWER_WM.R  /* FIFO Channel Lower Watermark Register */
#define GTM_FIFO_0_CH4_STATUS    GTM_FIFO_0.CHANNEL[4].STATUS.R    /* FIFO Channel Status Register */
#define GTM_FIFO_0_CH4_FILL_LEVEL GTM_FIFO_0.CHANNEL[4].FILL_LEVEL.R /* FIFO Channel Fill Level Register */
#define GTM_FIFO_0_CH4_WR_PTR    GTM_FIFO_0.CHANNEL[4].WR_PTR.R    /* FIFO Channel Write Pointer Register */
#define GTM_FIFO_0_CH4_RD_PTR    GTM_FIFO_0.CHANNEL[4].RD_PTR.R    /* FIFO Channel Read Pointer */
#define GTM_FIFO_0_CH4_IRQ_NOTIFY GTM_FIFO_0.CHANNEL[4].IRQ_NOTIFY.R /* FIFO Channel IRQ Notification Register */
#define GTM_FIFO_0_CH4_IRQ_EN    GTM_FIFO_0.CHANNEL[4].IRQ_EN.R    /* FIFO Channel IRQ Enable Register */
#define GTM_FIFO_0_CH4_IRQ_FORCINT GTM_FIFO_0.CHANNEL[4].IRQ_FORCINT.R /* FIFO Channel Force Interrupt Register */
#define GTM_FIFO_0_CH4_IRQ_MODE  GTM_FIFO_0.CHANNEL[4].IRQ_MODE.R  /* FIFO Channel IRQ Mode Register */
#define GTM_FIFO_0_CH4_EIRQ_EN   GTM_FIFO_0.CHANNEL[4].EIRQ_EN.R   /* FIFO Channel Error Interrupt Request Register */
#define GTM_FIFO_0_CH5_CTRL      GTM_FIFO_0.CHANNEL[5].CTRL.R      /* FIFO Channel Control Register */
#define GTM_FIFO_0_CH5_END_ADDR  GTM_FIFO_0.CHANNEL[5].END_ADDR.R  /* FIFO Channel End Address Register */
#define GTM_FIFO_0_CH5_START_ADDR GTM_FIFO_0.CHANNEL[5].START_ADDR.R /* FIFO Channel Start Address Register */
#define GTM_FIFO_0_CH5_UPPER_WM  GTM_FIFO_0.CHANNEL[5].UPPER_WM.R  /* FIFO Channel Upper Watermark Register */
#define GTM_FIFO_0_CH5_LOWER_WM  GTM_FIFO_0.CHANNEL[5].LOWER_WM.R  /* FIFO Channel Lower Watermark Register */
#define GTM_FIFO_0_CH5_STATUS    GTM_FIFO_0.CHANNEL[5].STATUS.R    /* FIFO Channel Status Register */
#define GTM_FIFO_0_CH5_FILL_LEVEL GTM_FIFO_0.CHANNEL[5].FILL_LEVEL.R /* FIFO Channel Fill Level Register */
#define GTM_FIFO_0_CH5_WR_PTR    GTM_FIFO_0.CHANNEL[5].WR_PTR.R    /* FIFO Channel Write Pointer Register */
#define GTM_FIFO_0_CH5_RD_PTR    GTM_FIFO_0.CHANNEL[5].RD_PTR.R    /* FIFO Channel Read Pointer */
#define GTM_FIFO_0_CH5_IRQ_NOTIFY GTM_FIFO_0.CHANNEL[5].IRQ_NOTIFY.R /* FIFO Channel IRQ Notification Register */
#define GTM_FIFO_0_CH5_IRQ_EN    GTM_FIFO_0.CHANNEL[5].IRQ_EN.R    /* FIFO Channel IRQ Enable Register */
#define GTM_FIFO_0_CH5_IRQ_FORCINT GTM_FIFO_0.CHANNEL[5].IRQ_FORCINT.R /* FIFO Channel Force Interrupt Register */
#define GTM_FIFO_0_CH5_IRQ_MODE  GTM_FIFO_0.CHANNEL[5].IRQ_MODE.R  /* FIFO Channel IRQ Mode Register */
#define GTM_FIFO_0_CH5_EIRQ_EN   GTM_FIFO_0.CHANNEL[5].EIRQ_EN.R   /* FIFO Channel Error Interrupt Request Register */
#define GTM_FIFO_0_CH6_CTRL      GTM_FIFO_0.CHANNEL[6].CTRL.R      /* FIFO Channel Control Register */
#define GTM_FIFO_0_CH6_END_ADDR  GTM_FIFO_0.CHANNEL[6].END_ADDR.R  /* FIFO Channel End Address Register */
#define GTM_FIFO_0_CH6_START_ADDR GTM_FIFO_0.CHANNEL[6].START_ADDR.R /* FIFO Channel Start Address Register */
#define GTM_FIFO_0_CH6_UPPER_WM  GTM_FIFO_0.CHANNEL[6].UPPER_WM.R  /* FIFO Channel Upper Watermark Register */
#define GTM_FIFO_0_CH6_LOWER_WM  GTM_FIFO_0.CHANNEL[6].LOWER_WM.R  /* FIFO Channel Lower Watermark Register */
#define GTM_FIFO_0_CH6_STATUS    GTM_FIFO_0.CHANNEL[6].STATUS.R    /* FIFO Channel Status Register */
#define GTM_FIFO_0_CH6_FILL_LEVEL GTM_FIFO_0.CHANNEL[6].FILL_LEVEL.R /* FIFO Channel Fill Level Register */
#define GTM_FIFO_0_CH6_WR_PTR    GTM_FIFO_0.CHANNEL[6].WR_PTR.R    /* FIFO Channel Write Pointer Register */
#define GTM_FIFO_0_CH6_RD_PTR    GTM_FIFO_0.CHANNEL[6].RD_PTR.R    /* FIFO Channel Read Pointer */
#define GTM_FIFO_0_CH6_IRQ_NOTIFY GTM_FIFO_0.CHANNEL[6].IRQ_NOTIFY.R /* FIFO Channel IRQ Notification Register */
#define GTM_FIFO_0_CH6_IRQ_EN    GTM_FIFO_0.CHANNEL[6].IRQ_EN.R    /* FIFO Channel IRQ Enable Register */
#define GTM_FIFO_0_CH6_IRQ_FORCINT GTM_FIFO_0.CHANNEL[6].IRQ_FORCINT.R /* FIFO Channel Force Interrupt Register */
#define GTM_FIFO_0_CH6_IRQ_MODE  GTM_FIFO_0.CHANNEL[6].IRQ_MODE.R  /* FIFO Channel IRQ Mode Register */
#define GTM_FIFO_0_CH6_EIRQ_EN   GTM_FIFO_0.CHANNEL[6].EIRQ_EN.R   /* FIFO Channel Error Interrupt Request Register */
#define GTM_FIFO_0_CH7_CTRL      GTM_FIFO_0.CHANNEL[7].CTRL.R      /* FIFO Channel Control Register */
#define GTM_FIFO_0_CH7_END_ADDR  GTM_FIFO_0.CHANNEL[7].END_ADDR.R  /* FIFO Channel End Address Register */
#define GTM_FIFO_0_CH7_START_ADDR GTM_FIFO_0.CHANNEL[7].START_ADDR.R /* FIFO Channel Start Address Register */
#define GTM_FIFO_0_CH7_UPPER_WM  GTM_FIFO_0.CHANNEL[7].UPPER_WM.R  /* FIFO Channel Upper Watermark Register */
#define GTM_FIFO_0_CH7_LOWER_WM  GTM_FIFO_0.CHANNEL[7].LOWER_WM.R  /* FIFO Channel Lower Watermark Register */
#define GTM_FIFO_0_CH7_STATUS    GTM_FIFO_0.CHANNEL[7].STATUS.R    /* FIFO Channel Status Register */
#define GTM_FIFO_0_CH7_FILL_LEVEL GTM_FIFO_0.CHANNEL[7].FILL_LEVEL.R /* FIFO Channel Fill Level Register */
#define GTM_FIFO_0_CH7_WR_PTR    GTM_FIFO_0.CHANNEL[7].WR_PTR.R    /* FIFO Channel Write Pointer Register */
#define GTM_FIFO_0_CH7_RD_PTR    GTM_FIFO_0.CHANNEL[7].RD_PTR.R    /* FIFO Channel Read Pointer */
#define GTM_FIFO_0_CH7_IRQ_NOTIFY GTM_FIFO_0.CHANNEL[7].IRQ_NOTIFY.R /* FIFO Channel IRQ Notification Register */
#define GTM_FIFO_0_CH7_IRQ_EN    GTM_FIFO_0.CHANNEL[7].IRQ_EN.R    /* FIFO Channel IRQ Enable Register */
#define GTM_FIFO_0_CH7_IRQ_FORCINT GTM_FIFO_0.CHANNEL[7].IRQ_FORCINT.R /* FIFO Channel Force Interrupt Register */
#define GTM_FIFO_0_CH7_IRQ_MODE  GTM_FIFO_0.CHANNEL[7].IRQ_MODE.R  /* FIFO Channel IRQ Mode Register */
#define GTM_FIFO_0_CH7_EIRQ_EN   GTM_FIFO_0.CHANNEL[7].EIRQ_EN.R   /* FIFO Channel Error Interrupt Request Register */

/* GTM_FIFO */
#define GTM_FIFO_1_CH0_CTRL      GTM_FIFO_1.CHANNEL[0].CTRL.R      /* FIFO Channel Control Register */
#define GTM_FIFO_1_CH0_END_ADDR  GTM_FIFO_1.CHANNEL[0].END_ADDR.R  /* FIFO Channel End Address Register */
#define GTM_FIFO_1_CH0_START_ADDR GTM_FIFO_1.CHANNEL[0].START_ADDR.R /* FIFO Channel Start Address Register */
#define GTM_FIFO_1_CH0_UPPER_WM  GTM_FIFO_1.CHANNEL[0].UPPER_WM.R  /* FIFO Channel Upper Watermark Register */
#define GTM_FIFO_1_CH0_LOWER_WM  GTM_FIFO_1.CHANNEL[0].LOWER_WM.R  /* FIFO Channel Lower Watermark Register */
#define GTM_FIFO_1_CH0_STATUS    GTM_FIFO_1.CHANNEL[0].STATUS.R    /* FIFO Channel Status Register */
#define GTM_FIFO_1_CH0_FILL_LEVEL GTM_FIFO_1.CHANNEL[0].FILL_LEVEL.R /* FIFO Channel Fill Level Register */
#define GTM_FIFO_1_CH0_WR_PTR    GTM_FIFO_1.CHANNEL[0].WR_PTR.R    /* FIFO Channel Write Pointer Register */
#define GTM_FIFO_1_CH0_RD_PTR    GTM_FIFO_1.CHANNEL[0].RD_PTR.R    /* FIFO Channel Read Pointer */
#define GTM_FIFO_1_CH0_IRQ_NOTIFY GTM_FIFO_1.CHANNEL[0].IRQ_NOTIFY.R /* FIFO Channel IRQ Notification Register */
#define GTM_FIFO_1_CH0_IRQ_EN    GTM_FIFO_1.CHANNEL[0].IRQ_EN.R    /* FIFO Channel IRQ Enable Register */
#define GTM_FIFO_1_CH0_IRQ_FORCINT GTM_FIFO_1.CHANNEL[0].IRQ_FORCINT.R /* FIFO Channel Force Interrupt Register */
#define GTM_FIFO_1_CH0_IRQ_MODE  GTM_FIFO_1.CHANNEL[0].IRQ_MODE.R  /* FIFO Channel IRQ Mode Register */
#define GTM_FIFO_1_CH0_EIRQ_EN   GTM_FIFO_1.CHANNEL[0].EIRQ_EN.R   /* FIFO Channel Error Interrupt Request Register */
#define GTM_FIFO_1_CH1_CTRL      GTM_FIFO_1.CHANNEL[1].CTRL.R      /* FIFO Channel Control Register */
#define GTM_FIFO_1_CH1_END_ADDR  GTM_FIFO_1.CHANNEL[1].END_ADDR.R  /* FIFO Channel End Address Register */
#define GTM_FIFO_1_CH1_START_ADDR GTM_FIFO_1.CHANNEL[1].START_ADDR.R /* FIFO Channel Start Address Register */
#define GTM_FIFO_1_CH1_UPPER_WM  GTM_FIFO_1.CHANNEL[1].UPPER_WM.R  /* FIFO Channel Upper Watermark Register */
#define GTM_FIFO_1_CH1_LOWER_WM  GTM_FIFO_1.CHANNEL[1].LOWER_WM.R  /* FIFO Channel Lower Watermark Register */
#define GTM_FIFO_1_CH1_STATUS    GTM_FIFO_1.CHANNEL[1].STATUS.R    /* FIFO Channel Status Register */
#define GTM_FIFO_1_CH1_FILL_LEVEL GTM_FIFO_1.CHANNEL[1].FILL_LEVEL.R /* FIFO Channel Fill Level Register */
#define GTM_FIFO_1_CH1_WR_PTR    GTM_FIFO_1.CHANNEL[1].WR_PTR.R    /* FIFO Channel Write Pointer Register */
#define GTM_FIFO_1_CH1_RD_PTR    GTM_FIFO_1.CHANNEL[1].RD_PTR.R    /* FIFO Channel Read Pointer */
#define GTM_FIFO_1_CH1_IRQ_NOTIFY GTM_FIFO_1.CHANNEL[1].IRQ_NOTIFY.R /* FIFO Channel IRQ Notification Register */
#define GTM_FIFO_1_CH1_IRQ_EN    GTM_FIFO_1.CHANNEL[1].IRQ_EN.R    /* FIFO Channel IRQ Enable Register */
#define GTM_FIFO_1_CH1_IRQ_FORCINT GTM_FIFO_1.CHANNEL[1].IRQ_FORCINT.R /* FIFO Channel Force Interrupt Register */
#define GTM_FIFO_1_CH1_IRQ_MODE  GTM_FIFO_1.CHANNEL[1].IRQ_MODE.R  /* FIFO Channel IRQ Mode Register */
#define GTM_FIFO_1_CH1_EIRQ_EN   GTM_FIFO_1.CHANNEL[1].EIRQ_EN.R   /* FIFO Channel Error Interrupt Request Register */
#define GTM_FIFO_1_CH2_CTRL      GTM_FIFO_1.CHANNEL[2].CTRL.R      /* FIFO Channel Control Register */
#define GTM_FIFO_1_CH2_END_ADDR  GTM_FIFO_1.CHANNEL[2].END_ADDR.R  /* FIFO Channel End Address Register */
#define GTM_FIFO_1_CH2_START_ADDR GTM_FIFO_1.CHANNEL[2].START_ADDR.R /* FIFO Channel Start Address Register */
#define GTM_FIFO_1_CH2_UPPER_WM  GTM_FIFO_1.CHANNEL[2].UPPER_WM.R  /* FIFO Channel Upper Watermark Register */
#define GTM_FIFO_1_CH2_LOWER_WM  GTM_FIFO_1.CHANNEL[2].LOWER_WM.R  /* FIFO Channel Lower Watermark Register */
#define GTM_FIFO_1_CH2_STATUS    GTM_FIFO_1.CHANNEL[2].STATUS.R    /* FIFO Channel Status Register */
#define GTM_FIFO_1_CH2_FILL_LEVEL GTM_FIFO_1.CHANNEL[2].FILL_LEVEL.R /* FIFO Channel Fill Level Register */
#define GTM_FIFO_1_CH2_WR_PTR    GTM_FIFO_1.CHANNEL[2].WR_PTR.R    /* FIFO Channel Write Pointer Register */
#define GTM_FIFO_1_CH2_RD_PTR    GTM_FIFO_1.CHANNEL[2].RD_PTR.R    /* FIFO Channel Read Pointer */
#define GTM_FIFO_1_CH2_IRQ_NOTIFY GTM_FIFO_1.CHANNEL[2].IRQ_NOTIFY.R /* FIFO Channel IRQ Notification Register */
#define GTM_FIFO_1_CH2_IRQ_EN    GTM_FIFO_1.CHANNEL[2].IRQ_EN.R    /* FIFO Channel IRQ Enable Register */
#define GTM_FIFO_1_CH2_IRQ_FORCINT GTM_FIFO_1.CHANNEL[2].IRQ_FORCINT.R /* FIFO Channel Force Interrupt Register */
#define GTM_FIFO_1_CH2_IRQ_MODE  GTM_FIFO_1.CHANNEL[2].IRQ_MODE.R  /* FIFO Channel IRQ Mode Register */
#define GTM_FIFO_1_CH2_EIRQ_EN   GTM_FIFO_1.CHANNEL[2].EIRQ_EN.R   /* FIFO Channel Error Interrupt Request Register */
#define GTM_FIFO_1_CH3_CTRL      GTM_FIFO_1.CHANNEL[3].CTRL.R      /* FIFO Channel Control Register */
#define GTM_FIFO_1_CH3_END_ADDR  GTM_FIFO_1.CHANNEL[3].END_ADDR.R  /* FIFO Channel End Address Register */
#define GTM_FIFO_1_CH3_START_ADDR GTM_FIFO_1.CHANNEL[3].START_ADDR.R /* FIFO Channel Start Address Register */
#define GTM_FIFO_1_CH3_UPPER_WM  GTM_FIFO_1.CHANNEL[3].UPPER_WM.R  /* FIFO Channel Upper Watermark Register */
#define GTM_FIFO_1_CH3_LOWER_WM  GTM_FIFO_1.CHANNEL[3].LOWER_WM.R  /* FIFO Channel Lower Watermark Register */
#define GTM_FIFO_1_CH3_STATUS    GTM_FIFO_1.CHANNEL[3].STATUS.R    /* FIFO Channel Status Register */
#define GTM_FIFO_1_CH3_FILL_LEVEL GTM_FIFO_1.CHANNEL[3].FILL_LEVEL.R /* FIFO Channel Fill Level Register */
#define GTM_FIFO_1_CH3_WR_PTR    GTM_FIFO_1.CHANNEL[3].WR_PTR.R    /* FIFO Channel Write Pointer Register */
#define GTM_FIFO_1_CH3_RD_PTR    GTM_FIFO_1.CHANNEL[3].RD_PTR.R    /* FIFO Channel Read Pointer */
#define GTM_FIFO_1_CH3_IRQ_NOTIFY GTM_FIFO_1.CHANNEL[3].IRQ_NOTIFY.R /* FIFO Channel IRQ Notification Register */
#define GTM_FIFO_1_CH3_IRQ_EN    GTM_FIFO_1.CHANNEL[3].IRQ_EN.R    /* FIFO Channel IRQ Enable Register */
#define GTM_FIFO_1_CH3_IRQ_FORCINT GTM_FIFO_1.CHANNEL[3].IRQ_FORCINT.R /* FIFO Channel Force Interrupt Register */
#define GTM_FIFO_1_CH3_IRQ_MODE  GTM_FIFO_1.CHANNEL[3].IRQ_MODE.R  /* FIFO Channel IRQ Mode Register */
#define GTM_FIFO_1_CH3_EIRQ_EN   GTM_FIFO_1.CHANNEL[3].EIRQ_EN.R   /* FIFO Channel Error Interrupt Request Register */
#define GTM_FIFO_1_CH4_CTRL      GTM_FIFO_1.CHANNEL[4].CTRL.R      /* FIFO Channel Control Register */
#define GTM_FIFO_1_CH4_END_ADDR  GTM_FIFO_1.CHANNEL[4].END_ADDR.R  /* FIFO Channel End Address Register */
#define GTM_FIFO_1_CH4_START_ADDR GTM_FIFO_1.CHANNEL[4].START_ADDR.R /* FIFO Channel Start Address Register */
#define GTM_FIFO_1_CH4_UPPER_WM  GTM_FIFO_1.CHANNEL[4].UPPER_WM.R  /* FIFO Channel Upper Watermark Register */
#define GTM_FIFO_1_CH4_LOWER_WM  GTM_FIFO_1.CHANNEL[4].LOWER_WM.R  /* FIFO Channel Lower Watermark Register */
#define GTM_FIFO_1_CH4_STATUS    GTM_FIFO_1.CHANNEL[4].STATUS.R    /* FIFO Channel Status Register */
#define GTM_FIFO_1_CH4_FILL_LEVEL GTM_FIFO_1.CHANNEL[4].FILL_LEVEL.R /* FIFO Channel Fill Level Register */
#define GTM_FIFO_1_CH4_WR_PTR    GTM_FIFO_1.CHANNEL[4].WR_PTR.R    /* FIFO Channel Write Pointer Register */
#define GTM_FIFO_1_CH4_RD_PTR    GTM_FIFO_1.CHANNEL[4].RD_PTR.R    /* FIFO Channel Read Pointer */
#define GTM_FIFO_1_CH4_IRQ_NOTIFY GTM_FIFO_1.CHANNEL[4].IRQ_NOTIFY.R /* FIFO Channel IRQ Notification Register */
#define GTM_FIFO_1_CH4_IRQ_EN    GTM_FIFO_1.CHANNEL[4].IRQ_EN.R    /* FIFO Channel IRQ Enable Register */
#define GTM_FIFO_1_CH4_IRQ_FORCINT GTM_FIFO_1.CHANNEL[4].IRQ_FORCINT.R /* FIFO Channel Force Interrupt Register */
#define GTM_FIFO_1_CH4_IRQ_MODE  GTM_FIFO_1.CHANNEL[4].IRQ_MODE.R  /* FIFO Channel IRQ Mode Register */
#define GTM_FIFO_1_CH4_EIRQ_EN   GTM_FIFO_1.CHANNEL[4].EIRQ_EN.R   /* FIFO Channel Error Interrupt Request Register */
#define GTM_FIFO_1_CH5_CTRL      GTM_FIFO_1.CHANNEL[5].CTRL.R      /* FIFO Channel Control Register */
#define GTM_FIFO_1_CH5_END_ADDR  GTM_FIFO_1.CHANNEL[5].END_ADDR.R  /* FIFO Channel End Address Register */
#define GTM_FIFO_1_CH5_START_ADDR GTM_FIFO_1.CHANNEL[5].START_ADDR.R /* FIFO Channel Start Address Register */
#define GTM_FIFO_1_CH5_UPPER_WM  GTM_FIFO_1.CHANNEL[5].UPPER_WM.R  /* FIFO Channel Upper Watermark Register */
#define GTM_FIFO_1_CH5_LOWER_WM  GTM_FIFO_1.CHANNEL[5].LOWER_WM.R  /* FIFO Channel Lower Watermark Register */
#define GTM_FIFO_1_CH5_STATUS    GTM_FIFO_1.CHANNEL[5].STATUS.R    /* FIFO Channel Status Register */
#define GTM_FIFO_1_CH5_FILL_LEVEL GTM_FIFO_1.CHANNEL[5].FILL_LEVEL.R /* FIFO Channel Fill Level Register */
#define GTM_FIFO_1_CH5_WR_PTR    GTM_FIFO_1.CHANNEL[5].WR_PTR.R    /* FIFO Channel Write Pointer Register */
#define GTM_FIFO_1_CH5_RD_PTR    GTM_FIFO_1.CHANNEL[5].RD_PTR.R    /* FIFO Channel Read Pointer */
#define GTM_FIFO_1_CH5_IRQ_NOTIFY GTM_FIFO_1.CHANNEL[5].IRQ_NOTIFY.R /* FIFO Channel IRQ Notification Register */
#define GTM_FIFO_1_CH5_IRQ_EN    GTM_FIFO_1.CHANNEL[5].IRQ_EN.R    /* FIFO Channel IRQ Enable Register */
#define GTM_FIFO_1_CH5_IRQ_FORCINT GTM_FIFO_1.CHANNEL[5].IRQ_FORCINT.R /* FIFO Channel Force Interrupt Register */
#define GTM_FIFO_1_CH5_IRQ_MODE  GTM_FIFO_1.CHANNEL[5].IRQ_MODE.R  /* FIFO Channel IRQ Mode Register */
#define GTM_FIFO_1_CH5_EIRQ_EN   GTM_FIFO_1.CHANNEL[5].EIRQ_EN.R   /* FIFO Channel Error Interrupt Request Register */
#define GTM_FIFO_1_CH6_CTRL      GTM_FIFO_1.CHANNEL[6].CTRL.R      /* FIFO Channel Control Register */
#define GTM_FIFO_1_CH6_END_ADDR  GTM_FIFO_1.CHANNEL[6].END_ADDR.R  /* FIFO Channel End Address Register */
#define GTM_FIFO_1_CH6_START_ADDR GTM_FIFO_1.CHANNEL[6].START_ADDR.R /* FIFO Channel Start Address Register */
#define GTM_FIFO_1_CH6_UPPER_WM  GTM_FIFO_1.CHANNEL[6].UPPER_WM.R  /* FIFO Channel Upper Watermark Register */
#define GTM_FIFO_1_CH6_LOWER_WM  GTM_FIFO_1.CHANNEL[6].LOWER_WM.R  /* FIFO Channel Lower Watermark Register */
#define GTM_FIFO_1_CH6_STATUS    GTM_FIFO_1.CHANNEL[6].STATUS.R    /* FIFO Channel Status Register */
#define GTM_FIFO_1_CH6_FILL_LEVEL GTM_FIFO_1.CHANNEL[6].FILL_LEVEL.R /* FIFO Channel Fill Level Register */
#define GTM_FIFO_1_CH6_WR_PTR    GTM_FIFO_1.CHANNEL[6].WR_PTR.R    /* FIFO Channel Write Pointer Register */
#define GTM_FIFO_1_CH6_RD_PTR    GTM_FIFO_1.CHANNEL[6].RD_PTR.R    /* FIFO Channel Read Pointer */
#define GTM_FIFO_1_CH6_IRQ_NOTIFY GTM_FIFO_1.CHANNEL[6].IRQ_NOTIFY.R /* FIFO Channel IRQ Notification Register */
#define GTM_FIFO_1_CH6_IRQ_EN    GTM_FIFO_1.CHANNEL[6].IRQ_EN.R    /* FIFO Channel IRQ Enable Register */
#define GTM_FIFO_1_CH6_IRQ_FORCINT GTM_FIFO_1.CHANNEL[6].IRQ_FORCINT.R /* FIFO Channel Force Interrupt Register */
#define GTM_FIFO_1_CH6_IRQ_MODE  GTM_FIFO_1.CHANNEL[6].IRQ_MODE.R  /* FIFO Channel IRQ Mode Register */
#define GTM_FIFO_1_CH6_EIRQ_EN   GTM_FIFO_1.CHANNEL[6].EIRQ_EN.R   /* FIFO Channel Error Interrupt Request Register */
#define GTM_FIFO_1_CH7_CTRL      GTM_FIFO_1.CHANNEL[7].CTRL.R      /* FIFO Channel Control Register */
#define GTM_FIFO_1_CH7_END_ADDR  GTM_FIFO_1.CHANNEL[7].END_ADDR.R  /* FIFO Channel End Address Register */
#define GTM_FIFO_1_CH7_START_ADDR GTM_FIFO_1.CHANNEL[7].START_ADDR.R /* FIFO Channel Start Address Register */
#define GTM_FIFO_1_CH7_UPPER_WM  GTM_FIFO_1.CHANNEL[7].UPPER_WM.R  /* FIFO Channel Upper Watermark Register */
#define GTM_FIFO_1_CH7_LOWER_WM  GTM_FIFO_1.CHANNEL[7].LOWER_WM.R  /* FIFO Channel Lower Watermark Register */
#define GTM_FIFO_1_CH7_STATUS    GTM_FIFO_1.CHANNEL[7].STATUS.R    /* FIFO Channel Status Register */
#define GTM_FIFO_1_CH7_FILL_LEVEL GTM_FIFO_1.CHANNEL[7].FILL_LEVEL.R /* FIFO Channel Fill Level Register */
#define GTM_FIFO_1_CH7_WR_PTR    GTM_FIFO_1.CHANNEL[7].WR_PTR.R    /* FIFO Channel Write Pointer Register */
#define GTM_FIFO_1_CH7_RD_PTR    GTM_FIFO_1.CHANNEL[7].RD_PTR.R    /* FIFO Channel Read Pointer */
#define GTM_FIFO_1_CH7_IRQ_NOTIFY GTM_FIFO_1.CHANNEL[7].IRQ_NOTIFY.R /* FIFO Channel IRQ Notification Register */
#define GTM_FIFO_1_CH7_IRQ_EN    GTM_FIFO_1.CHANNEL[7].IRQ_EN.R    /* FIFO Channel IRQ Enable Register */
#define GTM_FIFO_1_CH7_IRQ_FORCINT GTM_FIFO_1.CHANNEL[7].IRQ_FORCINT.R /* FIFO Channel Force Interrupt Register */
#define GTM_FIFO_1_CH7_IRQ_MODE  GTM_FIFO_1.CHANNEL[7].IRQ_MODE.R  /* FIFO Channel IRQ Mode Register */
#define GTM_FIFO_1_CH7_EIRQ_EN   GTM_FIFO_1.CHANNEL[7].EIRQ_EN.R   /* FIFO Channel Error Interrupt Request Register */

/* GTM_ICM */
#define GTM_ICM_IRQG_0           GTM_ICM.IRQG_0.R                  /* GTM Infrastructure Interrupt Group Register */
#define GTM_ICM_IRQG_1           GTM_ICM.IRQG_1.R                  /* DPLL Interrupt Group Register */
#define GTM_ICM_IRQG_2           GTM_ICM.IRQG_2.R                  /* TIM Interrupt Group 0 Register */
#define GTM_ICM_IRQG_3           GTM_ICM.IRQG_3.R                  /* TIM Interrupt Group 1 Register */
#define GTM_ICM_IRQG_4           GTM_ICM.IRQG_4.R                  /* MCS Interrupt Group 0 Register */
#define GTM_ICM_IRQG_5           GTM_ICM.IRQG_5.R                  /* MCS Interrupt Group 1 Register */
#define GTM_ICM_IRQG_6           GTM_ICM.IRQG_6.R                  /* TOM Interrupt Group 0 Register */
#define GTM_ICM_IRQG_7           GTM_ICM.IRQG_7.R                  /* TOM Interrupt Group 1 Register */
#define GTM_ICM_IRQG_8           GTM_ICM.IRQG_8.R                  /* TOM Interrupt Group 2 Register */
#define GTM_ICM_IRQG_9           GTM_ICM.IRQG_9.R                  /* ATOM Interrupt Group 0 Register */
#define GTM_ICM_IRQG_10          GTM_ICM.IRQG_10.R                 /* ATOM Interrupt Group 1 Register */
#define GTM_ICM_IRQG_11          GTM_ICM.IRQG_11.R                 /* ATOM Interrupt Group 2 Register */
#define GTM_ICM_IRQG_MEI         GTM_ICM.IRQG_MEI.R                /* ICM IRQG Module Error Interrupt register */
#define GTM_ICM_IRQG_CEI0        GTM_ICM.IRQG_CEI0.R               /* ICM Channel Error Interrupt Request Group 0 register */
#define GTM_ICM_IRQG_CEI1        GTM_ICM.IRQG_CEI1.R               /* Channel Error Interrupt Request Group 1 register */
#define GTM_ICM_IRQG_CEI2        GTM_ICM.IRQG_CEI2.R               /* Channel Error Interrupt Request Group 2 register */
#define GTM_ICM_IRQG_CEI3        GTM_ICM.IRQG_CEI3.R               /* Channel Error Interrupt Request Group 3 register */
#define GTM_ICM_IRQG_CEI4        GTM_ICM.IRQG_CEI4.R               /* Channel Error Interrupt Request Group 4 register */

/* GTM_MAP */
#define GTM_MAP_CTRL             GTM_MAP.CTRL.R                    /* TIM0 Input MAP Control Register */

/* GTM_MCFG */
#define GTM_MCFG_CTRL            GTM_MCFG.CTRL.R                   /* Memory Configuration Register */

/* GTM_MCS */
#define GTM_MCS_0_CH0_R0         GTM_MCS_0.CH0_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_0_CH0_R1         GTM_MCS_0.CH0_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_0_CH0_R2         GTM_MCS_0.CH0_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_0_CH0_R3         GTM_MCS_0.CH0_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_0_CH0_R4         GTM_MCS_0.CH0_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_0_CH0_R5         GTM_MCS_0.CH0_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_0_CH0_R6         GTM_MCS_0.CH0_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_0_CH0_R7         GTM_MCS_0.CH0_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_0_CH0_CTRL       GTM_MCS_0.CH0_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_0_CH0_ACB        GTM_MCS_0.CH0_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_0_CTRG           GTM_MCS_0.CTRG.R                  /* MCS Clear Trigger Control Register */
#define GTM_MCS_0_STRG           GTM_MCS_0.STRG.R                  /* MCS Set Trigger Control Register */
#define GTM_MCS_0_CH0_PC         GTM_MCS_0.CH0_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_0_CH0_IRQ_NOTIFY GTM_MCS_0.CH0_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_0_CH0_IRQ_EN     GTM_MCS_0.CH0_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_0_CH0_IRQ_FORCINT GTM_MCS_0.CH0_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_0_CH0_IRQ_MODE   GTM_MCS_0.CH0_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_0_CH0_EIRQ_EN    GTM_MCS_0.CH0_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_0_CTRL           GTM_MCS_0.CTRL.R                  /* MCS Control Register */
#define GTM_MCS_0_RST            GTM_MCS_0.RST.R                   /* MCS Reset Register */
#define GTM_MCS_0_ERR            GTM_MCS_0.ERR.R                   /* MCS Error Register */
#define GTM_MCS_0_CH1_R0         GTM_MCS_0.CH1_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_0_CH1_R1         GTM_MCS_0.CH1_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_0_CH1_R2         GTM_MCS_0.CH1_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_0_CH1_R3         GTM_MCS_0.CH1_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_0_CH1_R4         GTM_MCS_0.CH1_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_0_CH1_R5         GTM_MCS_0.CH1_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_0_CH1_R6         GTM_MCS_0.CH1_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_0_CH1_R7         GTM_MCS_0.CH1_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_0_CH1_CTRL       GTM_MCS_0.CH1_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_0_CH1_ACB        GTM_MCS_0.CH1_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_0_CH1_PC         GTM_MCS_0.CH1_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_0_CH1_IRQ_NOTIFY GTM_MCS_0.CH1_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_0_CH1_IRQ_EN     GTM_MCS_0.CH1_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_0_CH1_IRQ_FORCINT GTM_MCS_0.CH1_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_0_CH1_IRQ_MODE   GTM_MCS_0.CH1_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_0_CH1_EIRQ_EN    GTM_MCS_0.CH1_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_0_CH2_R0         GTM_MCS_0.CH2_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_0_CH2_R1         GTM_MCS_0.CH2_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_0_CH2_R2         GTM_MCS_0.CH2_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_0_CH2_R3         GTM_MCS_0.CH2_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_0_CH2_R4         GTM_MCS_0.CH2_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_0_CH2_R5         GTM_MCS_0.CH2_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_0_CH2_R6         GTM_MCS_0.CH2_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_0_CH2_R7         GTM_MCS_0.CH2_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_0_CH2_CTRL       GTM_MCS_0.CH2_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_0_CH2_ACB        GTM_MCS_0.CH2_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_0_CH2_PC         GTM_MCS_0.CH2_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_0_CH2_IRQ_NOTIFY GTM_MCS_0.CH2_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_0_CH2_IRQ_EN     GTM_MCS_0.CH2_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_0_CH2_IRQ_FORCINT GTM_MCS_0.CH2_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_0_CH2_IRQ_MODE   GTM_MCS_0.CH2_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_0_CH2_EIRQ_EN    GTM_MCS_0.CH2_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_0_CH3_R0         GTM_MCS_0.CH3_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_0_CH3_R1         GTM_MCS_0.CH3_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_0_CH3_R2         GTM_MCS_0.CH3_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_0_CH3_R3         GTM_MCS_0.CH3_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_0_CH3_R4         GTM_MCS_0.CH3_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_0_CH3_R5         GTM_MCS_0.CH3_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_0_CH3_R6         GTM_MCS_0.CH3_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_0_CH3_R7         GTM_MCS_0.CH3_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_0_CH3_CTRL       GTM_MCS_0.CH3_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_0_CH3_ACB        GTM_MCS_0.CH3_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_0_CH3_PC         GTM_MCS_0.CH3_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_0_CH3_IRQ_NOTIFY GTM_MCS_0.CH3_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_0_CH3_IRQ_EN     GTM_MCS_0.CH3_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_0_CH3_IRQ_FORCINT GTM_MCS_0.CH3_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_0_CH3_IRQ_MODE   GTM_MCS_0.CH3_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_0_CH3_EIRQ_EN    GTM_MCS_0.CH3_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_0_CH4_R0         GTM_MCS_0.CH4_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_0_CH4_R1         GTM_MCS_0.CH4_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_0_CH4_R2         GTM_MCS_0.CH4_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_0_CH4_R3         GTM_MCS_0.CH4_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_0_CH4_R4         GTM_MCS_0.CH4_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_0_CH4_R5         GTM_MCS_0.CH4_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_0_CH4_R6         GTM_MCS_0.CH4_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_0_CH4_R7         GTM_MCS_0.CH4_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_0_CH4_CTRL       GTM_MCS_0.CH4_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_0_CH4_ACB        GTM_MCS_0.CH4_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_0_CH4_PC         GTM_MCS_0.CH4_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_0_CH4_IRQ_NOTIFY GTM_MCS_0.CH4_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_0_CH4_IRQ_EN     GTM_MCS_0.CH4_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_0_CH4_IRQ_FORCINT GTM_MCS_0.CH4_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_0_CH4_IRQ_MODE   GTM_MCS_0.CH4_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_0_CH4_EIRQ_EN    GTM_MCS_0.CH4_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_0_CH5_R0         GTM_MCS_0.CH5_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_0_CH5_R1         GTM_MCS_0.CH5_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_0_CH5_R2         GTM_MCS_0.CH5_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_0_CH5_R3         GTM_MCS_0.CH5_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_0_CH5_R4         GTM_MCS_0.CH5_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_0_CH5_R5         GTM_MCS_0.CH5_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_0_CH5_R6         GTM_MCS_0.CH5_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_0_CH5_R7         GTM_MCS_0.CH5_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_0_CH5_CTRL       GTM_MCS_0.CH5_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_0_CH5_ACB        GTM_MCS_0.CH5_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_0_CH5_PC         GTM_MCS_0.CH5_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_0_CH5_IRQ_NOTIFY GTM_MCS_0.CH5_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_0_CH5_IRQ_EN     GTM_MCS_0.CH5_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_0_CH5_IRQ_FORCINT GTM_MCS_0.CH5_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_0_CH5_IRQ_MODE   GTM_MCS_0.CH5_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_0_CH5_EIRQ_EN    GTM_MCS_0.CH5_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_0_CH6_R0         GTM_MCS_0.CH6_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_0_CH6_R1         GTM_MCS_0.CH6_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_0_CH6_R2         GTM_MCS_0.CH6_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_0_CH6_R3         GTM_MCS_0.CH6_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_0_CH6_R4         GTM_MCS_0.CH6_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_0_CH6_R5         GTM_MCS_0.CH6_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_0_CH6_R6         GTM_MCS_0.CH6_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_0_CH6_R7         GTM_MCS_0.CH6_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_0_CH6_CTRL       GTM_MCS_0.CH6_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_0_CH6_ACB        GTM_MCS_0.CH6_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_0_CH6_PC         GTM_MCS_0.CH6_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_0_CH6_IRQ_NOTIFY GTM_MCS_0.CH6_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_0_CH6_IRQ_EN     GTM_MCS_0.CH6_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_0_CH6_IRQ_FORCINT GTM_MCS_0.CH6_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_0_CH6_IRQ_MODE   GTM_MCS_0.CH6_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_0_CH6_EIRQ_EN    GTM_MCS_0.CH6_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_0_CH7_R0         GTM_MCS_0.CH7_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_0_CH7_R1         GTM_MCS_0.CH7_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_0_CH7_R2         GTM_MCS_0.CH7_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_0_CH7_R3         GTM_MCS_0.CH7_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_0_CH7_R4         GTM_MCS_0.CH7_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_0_CH7_R5         GTM_MCS_0.CH7_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_0_CH7_R6         GTM_MCS_0.CH7_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_0_CH7_R7         GTM_MCS_0.CH7_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_0_CH7_CTRL       GTM_MCS_0.CH7_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_0_CH7_ACB        GTM_MCS_0.CH7_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_0_CH7_PC         GTM_MCS_0.CH7_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_0_CH7_IRQ_NOTIFY GTM_MCS_0.CH7_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_0_CH7_IRQ_EN     GTM_MCS_0.CH7_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_0_CH7_IRQ_FORCINT GTM_MCS_0.CH7_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_0_CH7_IRQ_MODE   GTM_MCS_0.CH7_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_0_CH7_EIRQ_EN    GTM_MCS_0.CH7_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */

/* GTM_MCS */
#define GTM_MCS_1_CH0_R0         GTM_MCS_1.CH0_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_1_CH0_R1         GTM_MCS_1.CH0_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_1_CH0_R2         GTM_MCS_1.CH0_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_1_CH0_R3         GTM_MCS_1.CH0_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_1_CH0_R4         GTM_MCS_1.CH0_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_1_CH0_R5         GTM_MCS_1.CH0_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_1_CH0_R6         GTM_MCS_1.CH0_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_1_CH0_R7         GTM_MCS_1.CH0_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_1_CH0_CTRL       GTM_MCS_1.CH0_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_1_CH0_ACB        GTM_MCS_1.CH0_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_1_CTRG           GTM_MCS_1.CTRG.R                  /* MCS Clear Trigger Control Register */
#define GTM_MCS_1_STRG           GTM_MCS_1.STRG.R                  /* MCS Set Trigger Control Register */
#define GTM_MCS_1_CH0_PC         GTM_MCS_1.CH0_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_1_CH0_IRQ_NOTIFY GTM_MCS_1.CH0_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_1_CH0_IRQ_EN     GTM_MCS_1.CH0_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_1_CH0_IRQ_FORCINT GTM_MCS_1.CH0_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_1_CH0_IRQ_MODE   GTM_MCS_1.CH0_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_1_CH0_EIRQ_EN    GTM_MCS_1.CH0_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_1_CTRL           GTM_MCS_1.CTRL.R                  /* MCS Control Register */
#define GTM_MCS_1_RST            GTM_MCS_1.RST.R                   /* MCS Reset Register */
#define GTM_MCS_1_ERR            GTM_MCS_1.ERR.R                   /* MCS Error Register */
#define GTM_MCS_1_CH1_R0         GTM_MCS_1.CH1_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_1_CH1_R1         GTM_MCS_1.CH1_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_1_CH1_R2         GTM_MCS_1.CH1_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_1_CH1_R3         GTM_MCS_1.CH1_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_1_CH1_R4         GTM_MCS_1.CH1_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_1_CH1_R5         GTM_MCS_1.CH1_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_1_CH1_R6         GTM_MCS_1.CH1_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_1_CH1_R7         GTM_MCS_1.CH1_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_1_CH1_CTRL       GTM_MCS_1.CH1_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_1_CH1_ACB        GTM_MCS_1.CH1_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_1_CH1_PC         GTM_MCS_1.CH1_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_1_CH1_IRQ_NOTIFY GTM_MCS_1.CH1_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_1_CH1_IRQ_EN     GTM_MCS_1.CH1_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_1_CH1_IRQ_FORCINT GTM_MCS_1.CH1_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_1_CH1_IRQ_MODE   GTM_MCS_1.CH1_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_1_CH1_EIRQ_EN    GTM_MCS_1.CH1_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_1_CH2_R0         GTM_MCS_1.CH2_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_1_CH2_R1         GTM_MCS_1.CH2_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_1_CH2_R2         GTM_MCS_1.CH2_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_1_CH2_R3         GTM_MCS_1.CH2_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_1_CH2_R4         GTM_MCS_1.CH2_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_1_CH2_R5         GTM_MCS_1.CH2_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_1_CH2_R6         GTM_MCS_1.CH2_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_1_CH2_R7         GTM_MCS_1.CH2_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_1_CH2_CTRL       GTM_MCS_1.CH2_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_1_CH2_ACB        GTM_MCS_1.CH2_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_1_CH2_PC         GTM_MCS_1.CH2_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_1_CH2_IRQ_NOTIFY GTM_MCS_1.CH2_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_1_CH2_IRQ_EN     GTM_MCS_1.CH2_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_1_CH2_IRQ_FORCINT GTM_MCS_1.CH2_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_1_CH2_IRQ_MODE   GTM_MCS_1.CH2_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_1_CH2_EIRQ_EN    GTM_MCS_1.CH2_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_1_CH3_R0         GTM_MCS_1.CH3_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_1_CH3_R1         GTM_MCS_1.CH3_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_1_CH3_R2         GTM_MCS_1.CH3_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_1_CH3_R3         GTM_MCS_1.CH3_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_1_CH3_R4         GTM_MCS_1.CH3_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_1_CH3_R5         GTM_MCS_1.CH3_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_1_CH3_R6         GTM_MCS_1.CH3_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_1_CH3_R7         GTM_MCS_1.CH3_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_1_CH3_CTRL       GTM_MCS_1.CH3_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_1_CH3_ACB        GTM_MCS_1.CH3_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_1_CH3_PC         GTM_MCS_1.CH3_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_1_CH3_IRQ_NOTIFY GTM_MCS_1.CH3_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_1_CH3_IRQ_EN     GTM_MCS_1.CH3_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_1_CH3_IRQ_FORCINT GTM_MCS_1.CH3_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_1_CH3_IRQ_MODE   GTM_MCS_1.CH3_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_1_CH3_EIRQ_EN    GTM_MCS_1.CH3_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_1_CH4_R0         GTM_MCS_1.CH4_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_1_CH4_R1         GTM_MCS_1.CH4_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_1_CH4_R2         GTM_MCS_1.CH4_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_1_CH4_R3         GTM_MCS_1.CH4_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_1_CH4_R4         GTM_MCS_1.CH4_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_1_CH4_R5         GTM_MCS_1.CH4_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_1_CH4_R6         GTM_MCS_1.CH4_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_1_CH4_R7         GTM_MCS_1.CH4_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_1_CH4_CTRL       GTM_MCS_1.CH4_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_1_CH4_ACB        GTM_MCS_1.CH4_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_1_CH4_PC         GTM_MCS_1.CH4_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_1_CH4_IRQ_NOTIFY GTM_MCS_1.CH4_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_1_CH4_IRQ_EN     GTM_MCS_1.CH4_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_1_CH4_IRQ_FORCINT GTM_MCS_1.CH4_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_1_CH4_IRQ_MODE   GTM_MCS_1.CH4_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_1_CH4_EIRQ_EN    GTM_MCS_1.CH4_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_1_CH5_R0         GTM_MCS_1.CH5_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_1_CH5_R1         GTM_MCS_1.CH5_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_1_CH5_R2         GTM_MCS_1.CH5_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_1_CH5_R3         GTM_MCS_1.CH5_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_1_CH5_R4         GTM_MCS_1.CH5_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_1_CH5_R5         GTM_MCS_1.CH5_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_1_CH5_R6         GTM_MCS_1.CH5_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_1_CH5_R7         GTM_MCS_1.CH5_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_1_CH5_CTRL       GTM_MCS_1.CH5_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_1_CH5_ACB        GTM_MCS_1.CH5_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_1_CH5_PC         GTM_MCS_1.CH5_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_1_CH5_IRQ_NOTIFY GTM_MCS_1.CH5_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_1_CH5_IRQ_EN     GTM_MCS_1.CH5_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_1_CH5_IRQ_FORCINT GTM_MCS_1.CH5_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_1_CH5_IRQ_MODE   GTM_MCS_1.CH5_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_1_CH5_EIRQ_EN    GTM_MCS_1.CH5_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_1_CH6_R0         GTM_MCS_1.CH6_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_1_CH6_R1         GTM_MCS_1.CH6_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_1_CH6_R2         GTM_MCS_1.CH6_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_1_CH6_R3         GTM_MCS_1.CH6_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_1_CH6_R4         GTM_MCS_1.CH6_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_1_CH6_R5         GTM_MCS_1.CH6_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_1_CH6_R6         GTM_MCS_1.CH6_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_1_CH6_R7         GTM_MCS_1.CH6_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_1_CH6_CTRL       GTM_MCS_1.CH6_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_1_CH6_ACB        GTM_MCS_1.CH6_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_1_CH6_PC         GTM_MCS_1.CH6_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_1_CH6_IRQ_NOTIFY GTM_MCS_1.CH6_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_1_CH6_IRQ_EN     GTM_MCS_1.CH6_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_1_CH6_IRQ_FORCINT GTM_MCS_1.CH6_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_1_CH6_IRQ_MODE   GTM_MCS_1.CH6_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_1_CH6_EIRQ_EN    GTM_MCS_1.CH6_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_1_CH7_R0         GTM_MCS_1.CH7_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_1_CH7_R1         GTM_MCS_1.CH7_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_1_CH7_R2         GTM_MCS_1.CH7_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_1_CH7_R3         GTM_MCS_1.CH7_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_1_CH7_R4         GTM_MCS_1.CH7_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_1_CH7_R5         GTM_MCS_1.CH7_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_1_CH7_R6         GTM_MCS_1.CH7_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_1_CH7_R7         GTM_MCS_1.CH7_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_1_CH7_CTRL       GTM_MCS_1.CH7_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_1_CH7_ACB        GTM_MCS_1.CH7_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_1_CH7_PC         GTM_MCS_1.CH7_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_1_CH7_IRQ_NOTIFY GTM_MCS_1.CH7_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_1_CH7_IRQ_EN     GTM_MCS_1.CH7_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_1_CH7_IRQ_FORCINT GTM_MCS_1.CH7_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_1_CH7_IRQ_MODE   GTM_MCS_1.CH7_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_1_CH7_EIRQ_EN    GTM_MCS_1.CH7_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */

/* GTM_MCS */
#define GTM_MCS_2_CH0_R0         GTM_MCS_2.CH0_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_2_CH0_R1         GTM_MCS_2.CH0_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_2_CH0_R2         GTM_MCS_2.CH0_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_2_CH0_R3         GTM_MCS_2.CH0_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_2_CH0_R4         GTM_MCS_2.CH0_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_2_CH0_R5         GTM_MCS_2.CH0_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_2_CH0_R6         GTM_MCS_2.CH0_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_2_CH0_R7         GTM_MCS_2.CH0_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_2_CH0_CTRL       GTM_MCS_2.CH0_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_2_CH0_ACB        GTM_MCS_2.CH0_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_2_CTRG           GTM_MCS_2.CTRG.R                  /* MCS Clear Trigger Control Register */
#define GTM_MCS_2_STRG           GTM_MCS_2.STRG.R                  /* MCS Set Trigger Control Register */
#define GTM_MCS_2_CH0_PC         GTM_MCS_2.CH0_PC.R                /* MCS Channel n Program Counter Register, n=0:8MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_2_CH0_IRQ_NOTIFY GTM_MCS_2.CH0_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_2_CH0_IRQ_EN     GTM_MCS_2.CH0_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_2_CH0_IRQ_FORCINT GTM_MCS_2.CH0_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_2_CH0_IRQ_MODE   GTM_MCS_2.CH0_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_2_CH0_EIRQ_EN    GTM_MCS_2.CH0_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_2_CTRL           GTM_MCS_2.CTRL.R                  /* MCS Control Register */
#define GTM_MCS_2_RST            GTM_MCS_2.RST.R                   /* MCS Reset Register */
#define GTM_MCS_2_ERR            GTM_MCS_2.ERR.R                   /* MCS Error Register */
#define GTM_MCS_2_CH1_R0         GTM_MCS_2.CH1_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_2_CH1_R1         GTM_MCS_2.CH1_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_2_CH1_R2         GTM_MCS_2.CH1_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_2_CH1_R3         GTM_MCS_2.CH1_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_2_CH1_R4         GTM_MCS_2.CH1_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_2_CH1_R5         GTM_MCS_2.CH1_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_2_CH1_R6         GTM_MCS_2.CH1_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_2_CH1_R7         GTM_MCS_2.CH1_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_2_CH1_CTRL       GTM_MCS_2.CH1_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_2_CH1_ACB        GTM_MCS_2.CH1_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_2_CH1_PC         GTM_MCS_2.CH1_PC.R                /* MCS Channel n Program Counter Register, n=0:8MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_2_CH1_IRQ_NOTIFY GTM_MCS_2.CH1_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_2_CH1_IRQ_EN     GTM_MCS_2.CH1_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_2_CH1_IRQ_FORCINT GTM_MCS_2.CH1_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_2_CH1_IRQ_MODE   GTM_MCS_2.CH1_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_2_CH1_EIRQ_EN    GTM_MCS_2.CH1_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_2_CH2_R0         GTM_MCS_2.CH2_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_2_CH2_R1         GTM_MCS_2.CH2_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_2_CH2_R2         GTM_MCS_2.CH2_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_2_CH2_R3         GTM_MCS_2.CH2_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_2_CH2_R4         GTM_MCS_2.CH2_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_2_CH2_R5         GTM_MCS_2.CH2_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_2_CH2_R6         GTM_MCS_2.CH2_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_2_CH2_R7         GTM_MCS_2.CH2_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_2_CH2_CTRL       GTM_MCS_2.CH2_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_2_CH2_ACB        GTM_MCS_2.CH2_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_2_CH2_PC         GTM_MCS_2.CH2_PC.R                /* MCS Channel n Program Counter Register, n=0:8MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_2_CH2_IRQ_NOTIFY GTM_MCS_2.CH2_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_2_CH2_IRQ_EN     GTM_MCS_2.CH2_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_2_CH2_IRQ_FORCINT GTM_MCS_2.CH2_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_2_CH2_IRQ_MODE   GTM_MCS_2.CH2_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_2_CH2_EIRQ_EN    GTM_MCS_2.CH2_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_2_CH3_R0         GTM_MCS_2.CH3_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_2_CH3_R1         GTM_MCS_2.CH3_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_2_CH3_R2         GTM_MCS_2.CH3_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_2_CH3_R3         GTM_MCS_2.CH3_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_2_CH3_R4         GTM_MCS_2.CH3_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_2_CH3_R5         GTM_MCS_2.CH3_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_2_CH3_R6         GTM_MCS_2.CH3_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_2_CH3_R7         GTM_MCS_2.CH3_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_2_CH3_CTRL       GTM_MCS_2.CH3_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_2_CH3_ACB        GTM_MCS_2.CH3_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_2_CH3_PC         GTM_MCS_2.CH3_PC.R                /* MCS Channel n Program Counter Register, n=0:8MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_2_CH3_IRQ_NOTIFY GTM_MCS_2.CH3_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_2_CH3_IRQ_EN     GTM_MCS_2.CH3_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_2_CH3_IRQ_FORCINT GTM_MCS_2.CH3_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_2_CH3_IRQ_MODE   GTM_MCS_2.CH3_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_2_CH3_EIRQ_EN    GTM_MCS_2.CH3_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_2_CH4_R0         GTM_MCS_2.CH4_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_2_CH4_R1         GTM_MCS_2.CH4_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_2_CH4_R2         GTM_MCS_2.CH4_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_2_CH4_R3         GTM_MCS_2.CH4_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_2_CH4_R4         GTM_MCS_2.CH4_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_2_CH4_R5         GTM_MCS_2.CH4_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_2_CH4_R6         GTM_MCS_2.CH4_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_2_CH4_R7         GTM_MCS_2.CH4_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_2_CH4_CTRL       GTM_MCS_2.CH4_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_2_CH4_ACB        GTM_MCS_2.CH4_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_2_CH4_PC         GTM_MCS_2.CH4_PC.R                /* MCS Channel n Program Counter Register, n=0:8MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_2_CH4_IRQ_NOTIFY GTM_MCS_2.CH4_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_2_CH4_IRQ_EN     GTM_MCS_2.CH4_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_2_CH4_IRQ_FORCINT GTM_MCS_2.CH4_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_2_CH4_IRQ_MODE   GTM_MCS_2.CH4_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_2_CH4_EIRQ_EN    GTM_MCS_2.CH4_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_2_CH5_R0         GTM_MCS_2.CH5_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_2_CH5_R1         GTM_MCS_2.CH5_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_2_CH5_R2         GTM_MCS_2.CH5_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_2_CH5_R3         GTM_MCS_2.CH5_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_2_CH5_R4         GTM_MCS_2.CH5_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_2_CH5_R5         GTM_MCS_2.CH5_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_2_CH5_R6         GTM_MCS_2.CH5_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_2_CH5_R7         GTM_MCS_2.CH5_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_2_CH5_CTRL       GTM_MCS_2.CH5_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_2_CH5_ACB        GTM_MCS_2.CH5_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_2_CH5_PC         GTM_MCS_2.CH5_PC.R                /* MCS Channel n Program Counter Register, n=0:8MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_2_CH5_IRQ_NOTIFY GTM_MCS_2.CH5_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_2_CH5_IRQ_EN     GTM_MCS_2.CH5_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_2_CH5_IRQ_FORCINT GTM_MCS_2.CH5_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_2_CH5_IRQ_MODE   GTM_MCS_2.CH5_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_2_CH5_EIRQ_EN    GTM_MCS_2.CH5_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_2_CH6_R0         GTM_MCS_2.CH6_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_2_CH6_R1         GTM_MCS_2.CH6_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_2_CH6_R2         GTM_MCS_2.CH6_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_2_CH6_R3         GTM_MCS_2.CH6_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_2_CH6_R4         GTM_MCS_2.CH6_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_2_CH6_R5         GTM_MCS_2.CH6_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_2_CH6_R6         GTM_MCS_2.CH6_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_2_CH6_R7         GTM_MCS_2.CH6_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_2_CH6_CTRL       GTM_MCS_2.CH6_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_2_CH6_ACB        GTM_MCS_2.CH6_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_2_CH6_PC         GTM_MCS_2.CH6_PC.R                /* MCS Channel n Program Counter Register, n=0:8MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_2_CH6_IRQ_NOTIFY GTM_MCS_2.CH6_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_2_CH6_IRQ_EN     GTM_MCS_2.CH6_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_2_CH6_IRQ_FORCINT GTM_MCS_2.CH6_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_2_CH6_IRQ_MODE   GTM_MCS_2.CH6_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_2_CH6_EIRQ_EN    GTM_MCS_2.CH6_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_2_CH7_R0         GTM_MCS_2.CH7_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_2_CH7_R1         GTM_MCS_2.CH7_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_2_CH7_R2         GTM_MCS_2.CH7_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_2_CH7_R3         GTM_MCS_2.CH7_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_2_CH7_R4         GTM_MCS_2.CH7_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_2_CH7_R5         GTM_MCS_2.CH7_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_2_CH7_R6         GTM_MCS_2.CH7_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_2_CH7_R7         GTM_MCS_2.CH7_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_2_CH7_CTRL       GTM_MCS_2.CH7_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_2_CH7_ACB        GTM_MCS_2.CH7_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_2_CH7_PC         GTM_MCS_2.CH7_PC.R                /* MCS Channel n Program Counter Register, n=0:8MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_2_CH7_IRQ_NOTIFY GTM_MCS_2.CH7_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_2_CH7_IRQ_EN     GTM_MCS_2.CH7_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_2_CH7_IRQ_FORCINT GTM_MCS_2.CH7_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_2_CH7_IRQ_MODE   GTM_MCS_2.CH7_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_2_CH7_EIRQ_EN    GTM_MCS_2.CH7_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */

/* GTM_MCS */
#define GTM_MCS_3_CH0_R0         GTM_MCS_3.CH0_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_3_CH0_R1         GTM_MCS_3.CH0_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_3_CH0_R2         GTM_MCS_3.CH0_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_3_CH0_R3         GTM_MCS_3.CH0_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_3_CH0_R4         GTM_MCS_3.CH0_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_3_CH0_R5         GTM_MCS_3.CH0_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_3_CH0_R6         GTM_MCS_3.CH0_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_3_CH0_R7         GTM_MCS_3.CH0_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_3_CH0_CTRL       GTM_MCS_3.CH0_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_3_CH0_ACB        GTM_MCS_3.CH0_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_3_CTRG           GTM_MCS_3.CTRG.R                  /* MCS Clear Trigger Control Register */
#define GTM_MCS_3_STRG           GTM_MCS_3.STRG.R                  /* MCS Set Trigger Control Register */
#define GTM_MCS_3_CH0_PC         GTM_MCS_3.CH0_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_3_CH0_IRQ_NOTIFY GTM_MCS_3.CH0_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_3_CH0_IRQ_EN     GTM_MCS_3.CH0_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_3_CH0_IRQ_FORCINT GTM_MCS_3.CH0_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_3_CH0_IRQ_MODE   GTM_MCS_3.CH0_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_3_CH0_EIRQ_EN    GTM_MCS_3.CH0_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_3_CTRL           GTM_MCS_3.CTRL.R                  /* MCS Control Register */
#define GTM_MCS_3_RST            GTM_MCS_3.RST.R                   /* MCS Reset Register */
#define GTM_MCS_3_ERR            GTM_MCS_3.ERR.R                   /* MCS Error Register */
#define GTM_MCS_3_CH1_R0         GTM_MCS_3.CH1_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_3_CH1_R1         GTM_MCS_3.CH1_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_3_CH1_R2         GTM_MCS_3.CH1_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_3_CH1_R3         GTM_MCS_3.CH1_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_3_CH1_R4         GTM_MCS_3.CH1_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_3_CH1_R5         GTM_MCS_3.CH1_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_3_CH1_R6         GTM_MCS_3.CH1_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_3_CH1_R7         GTM_MCS_3.CH1_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_3_CH1_CTRL       GTM_MCS_3.CH1_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_3_CH1_ACB        GTM_MCS_3.CH1_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_3_CH1_PC         GTM_MCS_3.CH1_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_3_CH1_IRQ_NOTIFY GTM_MCS_3.CH1_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_3_CH1_IRQ_EN     GTM_MCS_3.CH1_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_3_CH1_IRQ_FORCINT GTM_MCS_3.CH1_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_3_CH1_IRQ_MODE   GTM_MCS_3.CH1_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_3_CH1_EIRQ_EN    GTM_MCS_3.CH1_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_3_CH2_R0         GTM_MCS_3.CH2_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_3_CH2_R1         GTM_MCS_3.CH2_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_3_CH2_R2         GTM_MCS_3.CH2_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_3_CH2_R3         GTM_MCS_3.CH2_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_3_CH2_R4         GTM_MCS_3.CH2_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_3_CH2_R5         GTM_MCS_3.CH2_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_3_CH2_R6         GTM_MCS_3.CH2_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_3_CH2_R7         GTM_MCS_3.CH2_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_3_CH2_CTRL       GTM_MCS_3.CH2_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_3_CH2_ACB        GTM_MCS_3.CH2_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_3_CH2_PC         GTM_MCS_3.CH2_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_3_CH2_IRQ_NOTIFY GTM_MCS_3.CH2_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_3_CH2_IRQ_EN     GTM_MCS_3.CH2_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_3_CH2_IRQ_FORCINT GTM_MCS_3.CH2_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_3_CH2_IRQ_MODE   GTM_MCS_3.CH2_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_3_CH2_EIRQ_EN    GTM_MCS_3.CH2_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_3_CH3_R0         GTM_MCS_3.CH3_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_3_CH3_R1         GTM_MCS_3.CH3_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_3_CH3_R2         GTM_MCS_3.CH3_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_3_CH3_R3         GTM_MCS_3.CH3_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_3_CH3_R4         GTM_MCS_3.CH3_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_3_CH3_R5         GTM_MCS_3.CH3_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_3_CH3_R6         GTM_MCS_3.CH3_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_3_CH3_R7         GTM_MCS_3.CH3_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_3_CH3_CTRL       GTM_MCS_3.CH3_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_3_CH3_ACB        GTM_MCS_3.CH3_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_3_CH3_PC         GTM_MCS_3.CH3_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_3_CH3_IRQ_NOTIFY GTM_MCS_3.CH3_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_3_CH3_IRQ_EN     GTM_MCS_3.CH3_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_3_CH3_IRQ_FORCINT GTM_MCS_3.CH3_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_3_CH3_IRQ_MODE   GTM_MCS_3.CH3_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_3_CH3_EIRQ_EN    GTM_MCS_3.CH3_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_3_CH4_R0         GTM_MCS_3.CH4_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_3_CH4_R1         GTM_MCS_3.CH4_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_3_CH4_R2         GTM_MCS_3.CH4_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_3_CH4_R3         GTM_MCS_3.CH4_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_3_CH4_R4         GTM_MCS_3.CH4_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_3_CH4_R5         GTM_MCS_3.CH4_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_3_CH4_R6         GTM_MCS_3.CH4_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_3_CH4_R7         GTM_MCS_3.CH4_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_3_CH4_CTRL       GTM_MCS_3.CH4_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_3_CH4_ACB        GTM_MCS_3.CH4_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_3_CH4_PC         GTM_MCS_3.CH4_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_3_CH4_IRQ_NOTIFY GTM_MCS_3.CH4_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_3_CH4_IRQ_EN     GTM_MCS_3.CH4_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_3_CH4_IRQ_FORCINT GTM_MCS_3.CH4_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_3_CH4_IRQ_MODE   GTM_MCS_3.CH4_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_3_CH4_EIRQ_EN    GTM_MCS_3.CH4_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_3_CH5_R0         GTM_MCS_3.CH5_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_3_CH5_R1         GTM_MCS_3.CH5_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_3_CH5_R2         GTM_MCS_3.CH5_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_3_CH5_R3         GTM_MCS_3.CH5_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_3_CH5_R4         GTM_MCS_3.CH5_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_3_CH5_R5         GTM_MCS_3.CH5_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_3_CH5_R6         GTM_MCS_3.CH5_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_3_CH5_R7         GTM_MCS_3.CH5_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_3_CH5_CTRL       GTM_MCS_3.CH5_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_3_CH5_ACB        GTM_MCS_3.CH5_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_3_CH5_PC         GTM_MCS_3.CH5_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_3_CH5_IRQ_NOTIFY GTM_MCS_3.CH5_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_3_CH5_IRQ_EN     GTM_MCS_3.CH5_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_3_CH5_IRQ_FORCINT GTM_MCS_3.CH5_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_3_CH5_IRQ_MODE   GTM_MCS_3.CH5_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_3_CH5_EIRQ_EN    GTM_MCS_3.CH5_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_3_CH6_R0         GTM_MCS_3.CH6_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_3_CH6_R1         GTM_MCS_3.CH6_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_3_CH6_R2         GTM_MCS_3.CH6_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_3_CH6_R3         GTM_MCS_3.CH6_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_3_CH6_R4         GTM_MCS_3.CH6_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_3_CH6_R5         GTM_MCS_3.CH6_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_3_CH6_R6         GTM_MCS_3.CH6_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_3_CH6_R7         GTM_MCS_3.CH6_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_3_CH6_CTRL       GTM_MCS_3.CH6_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_3_CH6_ACB        GTM_MCS_3.CH6_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_3_CH6_PC         GTM_MCS_3.CH6_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_3_CH6_IRQ_NOTIFY GTM_MCS_3.CH6_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_3_CH6_IRQ_EN     GTM_MCS_3.CH6_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_3_CH6_IRQ_FORCINT GTM_MCS_3.CH6_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_3_CH6_IRQ_MODE   GTM_MCS_3.CH6_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_3_CH6_EIRQ_EN    GTM_MCS_3.CH6_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_3_CH7_R0         GTM_MCS_3.CH7_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_3_CH7_R1         GTM_MCS_3.CH7_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_3_CH7_R2         GTM_MCS_3.CH7_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_3_CH7_R3         GTM_MCS_3.CH7_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_3_CH7_R4         GTM_MCS_3.CH7_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_3_CH7_R5         GTM_MCS_3.CH7_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_3_CH7_R6         GTM_MCS_3.CH7_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_3_CH7_R7         GTM_MCS_3.CH7_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_3_CH7_CTRL       GTM_MCS_3.CH7_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_3_CH7_ACB        GTM_MCS_3.CH7_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_3_CH7_PC         GTM_MCS_3.CH7_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_3_CH7_IRQ_NOTIFY GTM_MCS_3.CH7_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_3_CH7_IRQ_EN     GTM_MCS_3.CH7_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_3_CH7_IRQ_FORCINT GTM_MCS_3.CH7_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_3_CH7_IRQ_MODE   GTM_MCS_3.CH7_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_3_CH7_EIRQ_EN    GTM_MCS_3.CH7_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */

/* GTM_MCS */
#define GTM_MCS_4_CH0_R0         GTM_MCS_4.CH0_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_4_CH0_R1         GTM_MCS_4.CH0_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_4_CH0_R2         GTM_MCS_4.CH0_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_4_CH0_R3         GTM_MCS_4.CH0_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_4_CH0_R4         GTM_MCS_4.CH0_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_4_CH0_R5         GTM_MCS_4.CH0_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_4_CH0_R6         GTM_MCS_4.CH0_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_4_CH0_R7         GTM_MCS_4.CH0_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_4_CH0_CTRL       GTM_MCS_4.CH0_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_4_CH0_ACB        GTM_MCS_4.CH0_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_4_CTRG           GTM_MCS_4.CTRG.R                  /* MCS Clear Trigger Control Register */
#define GTM_MCS_4_STRG           GTM_MCS_4.STRG.R                  /* MCS Set Trigger Control Register */
#define GTM_MCS_4_CH0_PC         GTM_MCS_4.CH0_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_4_CH0_IRQ_NOTIFY GTM_MCS_4.CH0_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_4_CH0_IRQ_EN     GTM_MCS_4.CH0_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_4_CH0_IRQ_FORCINT GTM_MCS_4.CH0_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_4_CH0_IRQ_MODE   GTM_MCS_4.CH0_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_4_CH0_EIRQ_EN    GTM_MCS_4.CH0_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_4_CTRL           GTM_MCS_4.CTRL.R                  /* MCS Control Register */
#define GTM_MCS_4_RST            GTM_MCS_4.RST.R                   /* MCS Reset Register */
#define GTM_MCS_4_ERR            GTM_MCS_4.ERR.R                   /* MCS Error Register */
#define GTM_MCS_4_CH1_R0         GTM_MCS_4.CH1_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_4_CH1_R1         GTM_MCS_4.CH1_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_4_CH1_R2         GTM_MCS_4.CH1_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_4_CH1_R3         GTM_MCS_4.CH1_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_4_CH1_R4         GTM_MCS_4.CH1_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_4_CH1_R5         GTM_MCS_4.CH1_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_4_CH1_R6         GTM_MCS_4.CH1_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_4_CH1_R7         GTM_MCS_4.CH1_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_4_CH1_CTRL       GTM_MCS_4.CH1_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_4_CH1_ACB        GTM_MCS_4.CH1_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_4_CH1_PC         GTM_MCS_4.CH1_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_4_CH1_IRQ_NOTIFY GTM_MCS_4.CH1_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_4_CH1_IRQ_EN     GTM_MCS_4.CH1_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_4_CH1_IRQ_FORCINT GTM_MCS_4.CH1_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_4_CH1_IRQ_MODE   GTM_MCS_4.CH1_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_4_CH1_EIRQ_EN    GTM_MCS_4.CH1_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_4_CH2_R0         GTM_MCS_4.CH2_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_4_CH2_R1         GTM_MCS_4.CH2_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_4_CH2_R2         GTM_MCS_4.CH2_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_4_CH2_R3         GTM_MCS_4.CH2_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_4_CH2_R4         GTM_MCS_4.CH2_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_4_CH2_R5         GTM_MCS_4.CH2_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_4_CH2_R6         GTM_MCS_4.CH2_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_4_CH2_R7         GTM_MCS_4.CH2_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_4_CH2_CTRL       GTM_MCS_4.CH2_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_4_CH2_ACB        GTM_MCS_4.CH2_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_4_CH2_PC         GTM_MCS_4.CH2_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_4_CH2_IRQ_NOTIFY GTM_MCS_4.CH2_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_4_CH2_IRQ_EN     GTM_MCS_4.CH2_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_4_CH2_IRQ_FORCINT GTM_MCS_4.CH2_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_4_CH2_IRQ_MODE   GTM_MCS_4.CH2_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_4_CH2_EIRQ_EN    GTM_MCS_4.CH2_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_4_CH3_R0         GTM_MCS_4.CH3_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_4_CH3_R1         GTM_MCS_4.CH3_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_4_CH3_R2         GTM_MCS_4.CH3_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_4_CH3_R3         GTM_MCS_4.CH3_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_4_CH3_R4         GTM_MCS_4.CH3_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_4_CH3_R5         GTM_MCS_4.CH3_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_4_CH3_R6         GTM_MCS_4.CH3_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_4_CH3_R7         GTM_MCS_4.CH3_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_4_CH3_CTRL       GTM_MCS_4.CH3_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_4_CH3_ACB        GTM_MCS_4.CH3_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_4_CH3_PC         GTM_MCS_4.CH3_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_4_CH3_IRQ_NOTIFY GTM_MCS_4.CH3_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_4_CH3_IRQ_EN     GTM_MCS_4.CH3_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_4_CH3_IRQ_FORCINT GTM_MCS_4.CH3_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_4_CH3_IRQ_MODE   GTM_MCS_4.CH3_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_4_CH3_EIRQ_EN    GTM_MCS_4.CH3_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_4_CH4_R0         GTM_MCS_4.CH4_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_4_CH4_R1         GTM_MCS_4.CH4_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_4_CH4_R2         GTM_MCS_4.CH4_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_4_CH4_R3         GTM_MCS_4.CH4_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_4_CH4_R4         GTM_MCS_4.CH4_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_4_CH4_R5         GTM_MCS_4.CH4_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_4_CH4_R6         GTM_MCS_4.CH4_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_4_CH4_R7         GTM_MCS_4.CH4_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_4_CH4_CTRL       GTM_MCS_4.CH4_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_4_CH4_ACB        GTM_MCS_4.CH4_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_4_CH4_PC         GTM_MCS_4.CH4_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_4_CH4_IRQ_NOTIFY GTM_MCS_4.CH4_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_4_CH4_IRQ_EN     GTM_MCS_4.CH4_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_4_CH4_IRQ_FORCINT GTM_MCS_4.CH4_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_4_CH4_IRQ_MODE   GTM_MCS_4.CH4_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_4_CH4_EIRQ_EN    GTM_MCS_4.CH4_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_4_CH5_R0         GTM_MCS_4.CH5_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_4_CH5_R1         GTM_MCS_4.CH5_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_4_CH5_R2         GTM_MCS_4.CH5_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_4_CH5_R3         GTM_MCS_4.CH5_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_4_CH5_R4         GTM_MCS_4.CH5_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_4_CH5_R5         GTM_MCS_4.CH5_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_4_CH5_R6         GTM_MCS_4.CH5_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_4_CH5_R7         GTM_MCS_4.CH5_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_4_CH5_CTRL       GTM_MCS_4.CH5_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_4_CH5_ACB        GTM_MCS_4.CH5_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_4_CH5_PC         GTM_MCS_4.CH5_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_4_CH5_IRQ_NOTIFY GTM_MCS_4.CH5_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_4_CH5_IRQ_EN     GTM_MCS_4.CH5_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_4_CH5_IRQ_FORCINT GTM_MCS_4.CH5_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_4_CH5_IRQ_MODE   GTM_MCS_4.CH5_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_4_CH5_EIRQ_EN    GTM_MCS_4.CH5_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_4_CH6_R0         GTM_MCS_4.CH6_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_4_CH6_R1         GTM_MCS_4.CH6_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_4_CH6_R2         GTM_MCS_4.CH6_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_4_CH6_R3         GTM_MCS_4.CH6_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_4_CH6_R4         GTM_MCS_4.CH6_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_4_CH6_R5         GTM_MCS_4.CH6_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_4_CH6_R6         GTM_MCS_4.CH6_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_4_CH6_R7         GTM_MCS_4.CH6_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_4_CH6_CTRL       GTM_MCS_4.CH6_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_4_CH6_ACB        GTM_MCS_4.CH6_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_4_CH6_PC         GTM_MCS_4.CH6_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_4_CH6_IRQ_NOTIFY GTM_MCS_4.CH6_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_4_CH6_IRQ_EN     GTM_MCS_4.CH6_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_4_CH6_IRQ_FORCINT GTM_MCS_4.CH6_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_4_CH6_IRQ_MODE   GTM_MCS_4.CH6_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_4_CH6_EIRQ_EN    GTM_MCS_4.CH6_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_4_CH7_R0         GTM_MCS_4.CH7_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_4_CH7_R1         GTM_MCS_4.CH7_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_4_CH7_R2         GTM_MCS_4.CH7_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_4_CH7_R3         GTM_MCS_4.CH7_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_4_CH7_R4         GTM_MCS_4.CH7_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_4_CH7_R5         GTM_MCS_4.CH7_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_4_CH7_R6         GTM_MCS_4.CH7_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_4_CH7_R7         GTM_MCS_4.CH7_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_4_CH7_CTRL       GTM_MCS_4.CH7_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_4_CH7_ACB        GTM_MCS_4.CH7_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_4_CH7_PC         GTM_MCS_4.CH7_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_4_CH7_IRQ_NOTIFY GTM_MCS_4.CH7_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_4_CH7_IRQ_EN     GTM_MCS_4.CH7_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_4_CH7_IRQ_FORCINT GTM_MCS_4.CH7_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_4_CH7_IRQ_MODE   GTM_MCS_4.CH7_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_4_CH7_EIRQ_EN    GTM_MCS_4.CH7_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */

/* GTM_MCS */
#define GTM_MCS_5_CH0_R0         GTM_MCS_5.CH0_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_5_CH0_R1         GTM_MCS_5.CH0_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_5_CH0_R2         GTM_MCS_5.CH0_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_5_CH0_R3         GTM_MCS_5.CH0_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_5_CH0_R4         GTM_MCS_5.CH0_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_5_CH0_R5         GTM_MCS_5.CH0_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_5_CH0_R6         GTM_MCS_5.CH0_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_5_CH0_R7         GTM_MCS_5.CH0_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_5_CH0_CTRL       GTM_MCS_5.CH0_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_5_CH0_ACB        GTM_MCS_5.CH0_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_5_CTRG           GTM_MCS_5.CTRG.R                  /* MCS Clear Trigger Control Register */
#define GTM_MCS_5_STRG           GTM_MCS_5.STRG.R                  /* MCS Set Trigger Control Register */
#define GTM_MCS_5_CH0_PC         GTM_MCS_5.CH0_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_5_CH0_IRQ_NOTIFY GTM_MCS_5.CH0_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_5_CH0_IRQ_EN     GTM_MCS_5.CH0_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_5_CH0_IRQ_FORCINT GTM_MCS_5.CH0_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_5_CH0_IRQ_MODE   GTM_MCS_5.CH0_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_5_CH0_EIRQ_EN    GTM_MCS_5.CH0_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_5_CTRL           GTM_MCS_5.CTRL.R                  /* MCS Control Register */
#define GTM_MCS_5_RST            GTM_MCS_5.RST.R                   /* MCS Reset Register */
#define GTM_MCS_5_ERR            GTM_MCS_5.ERR.R                   /* MCS Error Register */
#define GTM_MCS_5_CH1_R0         GTM_MCS_5.CH1_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_5_CH1_R1         GTM_MCS_5.CH1_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_5_CH1_R2         GTM_MCS_5.CH1_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_5_CH1_R3         GTM_MCS_5.CH1_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_5_CH1_R4         GTM_MCS_5.CH1_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_5_CH1_R5         GTM_MCS_5.CH1_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_5_CH1_R6         GTM_MCS_5.CH1_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_5_CH1_R7         GTM_MCS_5.CH1_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_5_CH1_CTRL       GTM_MCS_5.CH1_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_5_CH1_ACB        GTM_MCS_5.CH1_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_5_CH1_PC         GTM_MCS_5.CH1_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_5_CH1_IRQ_NOTIFY GTM_MCS_5.CH1_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_5_CH1_IRQ_EN     GTM_MCS_5.CH1_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_5_CH1_IRQ_FORCINT GTM_MCS_5.CH1_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_5_CH1_IRQ_MODE   GTM_MCS_5.CH1_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_5_CH1_EIRQ_EN    GTM_MCS_5.CH1_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_5_CH2_R0         GTM_MCS_5.CH2_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_5_CH2_R1         GTM_MCS_5.CH2_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_5_CH2_R2         GTM_MCS_5.CH2_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_5_CH2_R3         GTM_MCS_5.CH2_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_5_CH2_R4         GTM_MCS_5.CH2_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_5_CH2_R5         GTM_MCS_5.CH2_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_5_CH2_R6         GTM_MCS_5.CH2_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_5_CH2_R7         GTM_MCS_5.CH2_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_5_CH2_CTRL       GTM_MCS_5.CH2_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_5_CH2_ACB        GTM_MCS_5.CH2_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_5_CH2_PC         GTM_MCS_5.CH2_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_5_CH2_IRQ_NOTIFY GTM_MCS_5.CH2_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_5_CH2_IRQ_EN     GTM_MCS_5.CH2_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_5_CH2_IRQ_FORCINT GTM_MCS_5.CH2_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_5_CH2_IRQ_MODE   GTM_MCS_5.CH2_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_5_CH2_EIRQ_EN    GTM_MCS_5.CH2_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_5_CH3_R0         GTM_MCS_5.CH3_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_5_CH3_R1         GTM_MCS_5.CH3_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_5_CH3_R2         GTM_MCS_5.CH3_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_5_CH3_R3         GTM_MCS_5.CH3_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_5_CH3_R4         GTM_MCS_5.CH3_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_5_CH3_R5         GTM_MCS_5.CH3_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_5_CH3_R6         GTM_MCS_5.CH3_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_5_CH3_R7         GTM_MCS_5.CH3_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_5_CH3_CTRL       GTM_MCS_5.CH3_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_5_CH3_ACB        GTM_MCS_5.CH3_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_5_CH3_PC         GTM_MCS_5.CH3_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_5_CH3_IRQ_NOTIFY GTM_MCS_5.CH3_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_5_CH3_IRQ_EN     GTM_MCS_5.CH3_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_5_CH3_IRQ_FORCINT GTM_MCS_5.CH3_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_5_CH3_IRQ_MODE   GTM_MCS_5.CH3_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_5_CH3_EIRQ_EN    GTM_MCS_5.CH3_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_5_CH4_R0         GTM_MCS_5.CH4_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_5_CH4_R1         GTM_MCS_5.CH4_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_5_CH4_R2         GTM_MCS_5.CH4_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_5_CH4_R3         GTM_MCS_5.CH4_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_5_CH4_R4         GTM_MCS_5.CH4_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_5_CH4_R5         GTM_MCS_5.CH4_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_5_CH4_R6         GTM_MCS_5.CH4_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_5_CH4_R7         GTM_MCS_5.CH4_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_5_CH4_CTRL       GTM_MCS_5.CH4_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_5_CH4_ACB        GTM_MCS_5.CH4_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_5_CH4_PC         GTM_MCS_5.CH4_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_5_CH4_IRQ_NOTIFY GTM_MCS_5.CH4_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_5_CH4_IRQ_EN     GTM_MCS_5.CH4_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_5_CH4_IRQ_FORCINT GTM_MCS_5.CH4_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_5_CH4_IRQ_MODE   GTM_MCS_5.CH4_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_5_CH4_EIRQ_EN    GTM_MCS_5.CH4_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_5_CH5_R0         GTM_MCS_5.CH5_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_5_CH5_R1         GTM_MCS_5.CH5_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_5_CH5_R2         GTM_MCS_5.CH5_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_5_CH5_R3         GTM_MCS_5.CH5_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_5_CH5_R4         GTM_MCS_5.CH5_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_5_CH5_R5         GTM_MCS_5.CH5_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_5_CH5_R6         GTM_MCS_5.CH5_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_5_CH5_R7         GTM_MCS_5.CH5_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_5_CH5_CTRL       GTM_MCS_5.CH5_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_5_CH5_ACB        GTM_MCS_5.CH5_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_5_CH5_PC         GTM_MCS_5.CH5_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_5_CH5_IRQ_NOTIFY GTM_MCS_5.CH5_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_5_CH5_IRQ_EN     GTM_MCS_5.CH5_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_5_CH5_IRQ_FORCINT GTM_MCS_5.CH5_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_5_CH5_IRQ_MODE   GTM_MCS_5.CH5_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_5_CH5_EIRQ_EN    GTM_MCS_5.CH5_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_5_CH6_R0         GTM_MCS_5.CH6_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_5_CH6_R1         GTM_MCS_5.CH6_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_5_CH6_R2         GTM_MCS_5.CH6_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_5_CH6_R3         GTM_MCS_5.CH6_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_5_CH6_R4         GTM_MCS_5.CH6_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_5_CH6_R5         GTM_MCS_5.CH6_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_5_CH6_R6         GTM_MCS_5.CH6_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_5_CH6_R7         GTM_MCS_5.CH6_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_5_CH6_CTRL       GTM_MCS_5.CH6_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_5_CH6_ACB        GTM_MCS_5.CH6_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_5_CH6_PC         GTM_MCS_5.CH6_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_5_CH6_IRQ_NOTIFY GTM_MCS_5.CH6_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_5_CH6_IRQ_EN     GTM_MCS_5.CH6_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_5_CH6_IRQ_FORCINT GTM_MCS_5.CH6_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_5_CH6_IRQ_MODE   GTM_MCS_5.CH6_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_5_CH6_EIRQ_EN    GTM_MCS_5.CH6_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */
#define GTM_MCS_5_CH7_R0         GTM_MCS_5.CH7_R0.R                /* MCS Channel n General Purpose 0 Register, n=0:8 */
#define GTM_MCS_5_CH7_R1         GTM_MCS_5.CH7_R1.R                /* MCS Channel n General Purpose 1 Register, n=0:8 */
#define GTM_MCS_5_CH7_R2         GTM_MCS_5.CH7_R2.R                /* MCS Channel n General Purpose 2 Register, n=0:8 */
#define GTM_MCS_5_CH7_R3         GTM_MCS_5.CH7_R3.R                /* MCS Channel n General Purpose 3 Register, n=0:8 */
#define GTM_MCS_5_CH7_R4         GTM_MCS_5.CH7_R4.R                /* MCS Channel n General Purpose 4 Register, n=0:8 */
#define GTM_MCS_5_CH7_R5         GTM_MCS_5.CH7_R5.R                /* MCS Channel n General Purpose 5 Register, n=0:8 */
#define GTM_MCS_5_CH7_R6         GTM_MCS_5.CH7_R6.R                /* MCS Channel n General Purpose 6 Register, n=0:8 */
#define GTM_MCS_5_CH7_R7         GTM_MCS_5.CH7_R7.R                /* MCS Channel n General Purpose 7 Register, n=0:8 */
#define GTM_MCS_5_CH7_CTRL       GTM_MCS_5.CH7_CTRL.R              /* MCS Channel n Control Register, n=0:8 */
#define GTM_MCS_5_CH7_ACB        GTM_MCS_5.CH7_ACB.R               /* MCS Channel n ARU Control Bit Register, n=0:8 */
#define GTM_MCS_5_CH7_PC         GTM_MCS_5.CH7_PC.R                /* MCS Channel n Program Counter Register, n=0:8 */
#define GTM_MCS_5_CH7_IRQ_NOTIFY GTM_MCS_5.CH7_IRQ_NOTIFY.R        /* MCS Channel n Interrupt Request Notification Register, n=0:8 */
#define GTM_MCS_5_CH7_IRQ_EN     GTM_MCS_5.CH7_IRQ_EN.R            /* MCS Channel n Interrupt Request Enable Register, n=0:8 */
#define GTM_MCS_5_CH7_IRQ_FORCINT GTM_MCS_5.CH7_IRQ_FORCINT.R      /* MCS Channel n Force Interrupt Request Register, n=0:8 */
#define GTM_MCS_5_CH7_IRQ_MODE   GTM_MCS_5.CH7_IRQ_MODE.R          /* MCS Channel n Interrupt Request Mode Register, n=0:8 */
#define GTM_MCS_5_CH7_EIRQ_EN    GTM_MCS_5.CH7_EIRQ_EN.R           /* MCS Channel n Error Interrupt Request Enable register, n=0:8 */

/* GTM_MON */
#define GTM_MON_STATUS           GTM_MON.STATUS.R                  /* Monitor Status Register */
#define GTM_MON_ACTIVITY_0       GTM_MON.ACTIVITY_0.R              /* Monitor Acitivity 0 */
#define GTM_MON_ACTIVITY_1       GTM_MON.ACTIVITY_1.R              /* Monitor Acitivity 1 */

/* GTM_SPE */
#define GTM_SPE_0_CTRL_STAT      GTM_SPE_0.CTRL_STAT.R             /* SPE Control Status Register */
#define GTM_SPE_0_PAT            GTM_SPE_0.PAT.R                   /* SPE Input Pattern Register */
#define GTM_SPE_0_OUT_PAT0       GTM_SPE_0.OUT_PAT[0].R            /* SPE Output Pattern n Register */
#define GTM_SPE_0_OUT_PAT1       GTM_SPE_0.OUT_PAT[1].R            /* SPE Output Pattern n Register */
#define GTM_SPE_0_OUT_PAT2       GTM_SPE_0.OUT_PAT[2].R            /* SPE Output Pattern n Register */
#define GTM_SPE_0_OUT_PAT3       GTM_SPE_0.OUT_PAT[3].R            /* SPE Output Pattern n Register */
#define GTM_SPE_0_OUT_PAT4       GTM_SPE_0.OUT_PAT[4].R            /* SPE Output Pattern n Register */
#define GTM_SPE_0_OUT_PAT5       GTM_SPE_0.OUT_PAT[5].R            /* SPE Output Pattern n Register */
#define GTM_SPE_0_OUT_PAT6       GTM_SPE_0.OUT_PAT[6].R            /* SPE Output Pattern n Register */
#define GTM_SPE_0_OUT_PAT7       GTM_SPE_0.OUT_PAT[7].R            /* SPE Output Pattern n Register */
#define GTM_SPE_0_OUT_CTRL       GTM_SPE_0.OUT_CTRL.R              /* SPE Output Control Register */
#define GTM_SPE_0_IRQ_NOTIFY     GTM_SPE_0.IRQ_NOTIFY.R            /* SPE Interrupt Request Notify Register */
#define GTM_SPE_0_IRQ_EN         GTM_SPE_0.IRQ_EN.R                /* SPE Interrupt Request Enable Register */
#define GTM_SPE_0_IRQ_FORCINT    GTM_SPE_0.IRQ_FORCINT.R           /* SPE Interrupt Request Force Interrupt Register */
#define GTM_SPE_0_IRQ_MODE       GTM_SPE_0.IRQ_MODE.R              /* SPE Interrupt Request Mode Register */
#define GTM_SPE_0_EIRQ_EN        GTM_SPE_0.EIRQ_EN.R               /* SPE Error Interrupt Request Enable register */
#define GTM_SPE_0_REV_CNT        GTM_SPE_0.REV_CNT.R               /* SPE Revolution Counter register */
#define GTM_SPE_0_REV_CMP        GTM_SPE_0.REV_CMP.R               /* SPE Revolution Counter Compare register */

/* GTM_SPE */
#define GTM_SPE_1_CTRL_STAT      GTM_SPE_1.CTRL_STAT.R             /* SPE Control Status RegisterSPE Control Status Register */
#define GTM_SPE_1_PAT            GTM_SPE_1.PAT.R                   /* SPE Input Pattern Register */
#define GTM_SPE_1_OUT_PAT0       GTM_SPE_1.OUT_PAT[0].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_1_OUT_PAT1       GTM_SPE_1.OUT_PAT[1].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_1_OUT_PAT2       GTM_SPE_1.OUT_PAT[2].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_1_OUT_PAT3       GTM_SPE_1.OUT_PAT[3].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_1_OUT_PAT4       GTM_SPE_1.OUT_PAT[4].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_1_OUT_PAT5       GTM_SPE_1.OUT_PAT[5].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_1_OUT_PAT6       GTM_SPE_1.OUT_PAT[6].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_1_OUT_PAT7       GTM_SPE_1.OUT_PAT[7].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_1_OUT_CTRL       GTM_SPE_1.OUT_CTRL.R              /* SPE Output Control Register */
#define GTM_SPE_1_IRQ_NOTIFY     GTM_SPE_1.IRQ_NOTIFY.R            /* SPE Interrupt Request Notify Register */
#define GTM_SPE_1_IRQ_EN         GTM_SPE_1.IRQ_EN.R                /* SPE Interrupt Request Enable Register */
#define GTM_SPE_1_IRQ_FORCINT    GTM_SPE_1.IRQ_FORCINT.R           /* SPE Interrupt Request Force Interrupt Register */
#define GTM_SPE_1_IRQ_MODE       GTM_SPE_1.IRQ_MODE.R              /* SPE Interrupt Request Mode Register */
#define GTM_SPE_1_EIRQ_EN        GTM_SPE_1.EIRQ_EN.R               /* SPE Error Interrupt Request Enable register */
#define GTM_SPE_1_REV_CNT        GTM_SPE_1.REV_CNT.R               /* SPE Revolution Counter register */
#define GTM_SPE_1_REV_CMP        GTM_SPE_1.REV_CMP.R               /* SPE Revolution Counter Compare register */

/* GTM_SPE */
#define GTM_SPE_2_CTRL_STAT      GTM_SPE_2.CTRL_STAT.R             /* SPE Control Status Register */
#define GTM_SPE_2_PAT            GTM_SPE_2.PAT.R                   /* SPE Input Pattern Register */
#define GTM_SPE_2_OUT_PAT0       GTM_SPE_2.OUT_PAT[0].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_2_OUT_PAT1       GTM_SPE_2.OUT_PAT[1].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_2_OUT_PAT2       GTM_SPE_2.OUT_PAT[2].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_2_OUT_PAT3       GTM_SPE_2.OUT_PAT[3].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_2_OUT_PAT4       GTM_SPE_2.OUT_PAT[4].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_2_OUT_PAT5       GTM_SPE_2.OUT_PAT[5].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_2_OUT_PAT6       GTM_SPE_2.OUT_PAT[6].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_2_OUT_PAT7       GTM_SPE_2.OUT_PAT[7].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_2_OUT_CTRL       GTM_SPE_2.OUT_CTRL.R              /* SPE Output Control Register */
#define GTM_SPE_2_IRQ_NOTIFY     GTM_SPE_2.IRQ_NOTIFY.R            /* SPE Interrupt Request Notify Register */
#define GTM_SPE_2_IRQ_EN         GTM_SPE_2.IRQ_EN.R                /* SPE Interrupt Request Enable Register */
#define GTM_SPE_2_IRQ_FORCINT    GTM_SPE_2.IRQ_FORCINT.R           /* SPE Interrupt Request Force Interrupt Register */
#define GTM_SPE_2_IRQ_MODE       GTM_SPE_2.IRQ_MODE.R              /* SPE Interrupt Request Mode Register */
#define GTM_SPE_2_EIRQ_EN        GTM_SPE_2.EIRQ_EN.R               /* SPE Error Interrupt Request Enable register */
#define GTM_SPE_2_REV_CNT        GTM_SPE_2.REV_CNT.R               /* SPE Revolution Counter register */
#define GTM_SPE_2_REV_CMP        GTM_SPE_2.REV_CMP.R               /* SPE Revolution Counter Compare register */

/* GTM_SPE */
#define GTM_SPE_3_CTRL_STAT      GTM_SPE_3.CTRL_STAT.R             /* SPE Control Status Register */
#define GTM_SPE_3_PAT            GTM_SPE_3.PAT.R                   /* SPE Input Pattern Register */
#define GTM_SPE_3_OUT_PAT0       GTM_SPE_3.OUT_PAT[0].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_3_OUT_PAT1       GTM_SPE_3.OUT_PAT[1].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_3_OUT_PAT2       GTM_SPE_3.OUT_PAT[2].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_3_OUT_PAT3       GTM_SPE_3.OUT_PAT[3].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_3_OUT_PAT4       GTM_SPE_3.OUT_PAT[4].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_3_OUT_PAT5       GTM_SPE_3.OUT_PAT[5].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_3_OUT_PAT6       GTM_SPE_3.OUT_PAT[6].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_3_OUT_PAT7       GTM_SPE_3.OUT_PAT[7].R            /* SPE Output Pattern n Register, n=0:7 */
#define GTM_SPE_3_OUT_CTRL       GTM_SPE_3.OUT_CTRL.R              /* SPE Output Control Register */
#define GTM_SPE_3_IRQ_NOTIFY     GTM_SPE_3.IRQ_NOTIFY.R            /* SPE Interrupt Request Notify Register */
#define GTM_SPE_3_IRQ_EN         GTM_SPE_3.IRQ_EN.R                /* SPE Interrupt Request Enable Register */
#define GTM_SPE_3_IRQ_FORCINT    GTM_SPE_3.IRQ_FORCINT.R           /* SPE Interrupt Request Force Interrupt Register */
#define GTM_SPE_3_IRQ_MODE       GTM_SPE_3.IRQ_MODE.R              /* SPE Interrupt Request Mode Register */
#define GTM_SPE_3_EIRQ_EN        GTM_SPE_3.EIRQ_EN.R               /* SPE Error Interrupt Request Enable register */
#define GTM_SPE_3_REV_CNT        GTM_SPE_3.REV_CNT.R               /* SPE Revolution Counter register */
#define GTM_SPE_3_REV_CMP        GTM_SPE_3.REV_CMP.R               /* SPE Revolution Counter Compare register */

/* GTM_TBU */
#define GTM_TBU_CHEN             GTM_TBU.CHEN.R                    /* TBU Global Channel Enable Register */
#define GTM_TBU_CH0_CTRL         GTM_TBU.CH0_CTRL.R                /* TBU Channel 0 Control Register */
#define GTM_TBU_CH0_BASE         GTM_TBU.CH0_BASE.R                /* TBU Channel 0 Base Register */
#define GTM_TBU_CH1_CTRL         GTM_TBU.CH1_CTRL.R                /* TBU Channel 1 Control Register */
#define GTM_TBU_CH1_BASE         GTM_TBU.CH1_BASE.R                /* TBU Channel 1 Base Register */
#define GTM_TBU_CH2_CTRL         GTM_TBU.CH2_CTRL.R                /* TBU Channel 2 Control Register */
#define GTM_TBU_CH2_BASE         GTM_TBU.CH2_BASE.R                /* TBU Channel 2 Base Register */

/* GTM_TIM */
#define GTM_TIM_0_CH0_GPR0       GTM_TIM_0.CH0_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_0_CH0_GPR1       GTM_TIM_0.CH0_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_0_CH0_CNT        GTM_TIM_0.CH0_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_0_CH0_ECNT       GTM_TIM_0.CH0_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_0_CH0_CNTS       GTM_TIM_0.CH0_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_0_CH0_TDUC       GTM_TIM_0.CH0_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_0_CH0_TDUV       GTM_TIM_0.CH0_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_0_CH0_FLT_RE     GTM_TIM_0.CH0_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_0_CH0_FLT_FE     GTM_TIM_0.CH0_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_0_CH0_CTRL       GTM_TIM_0.CH0_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_0_CH0_ECTRL      GTM_TIM_0.CH0_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_0_CH0_IRQ_NOTIFY GTM_TIM_0.CH0_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_0_CH0_IRQ_EN     GTM_TIM_0.CH0_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_0_CH0_IRQ_FORCINT GTM_TIM_0.CH0_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_0_CH0_IRQ_MODE   GTM_TIM_0.CH0_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_0_CH0_EIRQ_EN    GTM_TIM_0.CH0_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_0_IN_SRC         GTM_TIM_0.IN_SRC.R                /* TIM Input Source Register */
#define GTM_TIM_0_RST            GTM_TIM_0.RST.R                   /* TIM Channel Reset Register */
#define GTM_TIM_0_CH1_GPR0       GTM_TIM_0.CH1_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_0_CH1_GPR1       GTM_TIM_0.CH1_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_0_CH1_CNT        GTM_TIM_0.CH1_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_0_CH1_ECNT       GTM_TIM_0.CH1_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_0_CH1_CNTS       GTM_TIM_0.CH1_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_0_CH1_TDUC       GTM_TIM_0.CH1_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_0_CH1_TDUV       GTM_TIM_0.CH1_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_0_CH1_FLT_RE     GTM_TIM_0.CH1_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_0_CH1_FLT_FE     GTM_TIM_0.CH1_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_0_CH1_CTRL       GTM_TIM_0.CH1_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_0_CH1_ECTRL      GTM_TIM_0.CH1_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_0_CH1_IRQ_NOTIFY GTM_TIM_0.CH1_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_0_CH1_IRQ_EN     GTM_TIM_0.CH1_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_0_CH1_IRQ_FORCINT GTM_TIM_0.CH1_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_0_CH1_IRQ_MODE   GTM_TIM_0.CH1_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_0_CH1_EIRQ_EN    GTM_TIM_0.CH1_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_0_CH2_GPR0       GTM_TIM_0.CH2_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_0_CH2_GPR1       GTM_TIM_0.CH2_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_0_CH2_CNT        GTM_TIM_0.CH2_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_0_CH2_ECNT       GTM_TIM_0.CH2_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_0_CH2_CNTS       GTM_TIM_0.CH2_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_0_CH2_TDUC       GTM_TIM_0.CH2_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_0_CH2_TDUV       GTM_TIM_0.CH2_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_0_CH2_FLT_RE     GTM_TIM_0.CH2_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_0_CH2_FLT_FE     GTM_TIM_0.CH2_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_0_CH2_CTRL       GTM_TIM_0.CH2_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_0_CH2_ECTRL      GTM_TIM_0.CH2_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_0_CH2_IRQ_NOTIFY GTM_TIM_0.CH2_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_0_CH2_IRQ_EN     GTM_TIM_0.CH2_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_0_CH2_IRQ_FORCINT GTM_TIM_0.CH2_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_0_CH2_IRQ_MODE   GTM_TIM_0.CH2_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_0_CH2_EIRQ_EN    GTM_TIM_0.CH2_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_0_CH3_GPR0       GTM_TIM_0.CH3_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_0_CH3_GPR1       GTM_TIM_0.CH3_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_0_CH3_CNT        GTM_TIM_0.CH3_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_0_CH3_ECNT       GTM_TIM_0.CH3_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_0_CH3_CNTS       GTM_TIM_0.CH3_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_0_CH3_TDUC       GTM_TIM_0.CH3_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_0_CH3_TDUV       GTM_TIM_0.CH3_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_0_CH3_FLT_RE     GTM_TIM_0.CH3_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_0_CH3_FLT_FE     GTM_TIM_0.CH3_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_0_CH3_CTRL       GTM_TIM_0.CH3_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_0_CH3_ECTRL      GTM_TIM_0.CH3_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_0_CH3_IRQ_NOTIFY GTM_TIM_0.CH3_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_0_CH3_IRQ_EN     GTM_TIM_0.CH3_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_0_CH3_IRQ_FORCINT GTM_TIM_0.CH3_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_0_CH3_IRQ_MODE   GTM_TIM_0.CH3_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_0_CH3_EIRQ_EN    GTM_TIM_0.CH3_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_0_CH4_GPR0       GTM_TIM_0.CH4_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_0_CH4_GPR1       GTM_TIM_0.CH4_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_0_CH4_CNT        GTM_TIM_0.CH4_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_0_CH4_ECNT       GTM_TIM_0.CH4_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_0_CH4_CNTS       GTM_TIM_0.CH4_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_0_CH4_TDUC       GTM_TIM_0.CH4_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_0_CH4_TDUV       GTM_TIM_0.CH4_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_0_CH4_FLT_RE     GTM_TIM_0.CH4_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_0_CH4_FLT_FE     GTM_TIM_0.CH4_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_0_CH4_CTRL       GTM_TIM_0.CH4_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_0_CH4_ECTRL      GTM_TIM_0.CH4_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_0_CH4_IRQ_NOTIFY GTM_TIM_0.CH4_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_0_CH4_IRQ_EN     GTM_TIM_0.CH4_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_0_CH4_IRQ_FORCINT GTM_TIM_0.CH4_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_0_CH4_IRQ_MODE   GTM_TIM_0.CH4_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_0_CH4_EIRQ_EN    GTM_TIM_0.CH4_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_0_CH5_GPR0       GTM_TIM_0.CH5_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_0_CH5_GPR1       GTM_TIM_0.CH5_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_0_CH5_CNT        GTM_TIM_0.CH5_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_0_CH5_ECNT       GTM_TIM_0.CH5_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_0_CH5_CNTS       GTM_TIM_0.CH5_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_0_CH5_TDUC       GTM_TIM_0.CH5_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_0_CH5_TDUV       GTM_TIM_0.CH5_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_0_CH5_FLT_RE     GTM_TIM_0.CH5_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_0_CH5_FLT_FE     GTM_TIM_0.CH5_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_0_CH5_CTRL       GTM_TIM_0.CH5_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_0_CH5_ECTRL      GTM_TIM_0.CH5_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_0_CH5_IRQ_NOTIFY GTM_TIM_0.CH5_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_0_CH5_IRQ_EN     GTM_TIM_0.CH5_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_0_CH5_IRQ_FORCINT GTM_TIM_0.CH5_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_0_CH5_IRQ_MODE   GTM_TIM_0.CH5_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_0_CH5_EIRQ_EN    GTM_TIM_0.CH5_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_0_CH6_GPR0       GTM_TIM_0.CH6_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_0_CH6_GPR1       GTM_TIM_0.CH6_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_0_CH6_CNT        GTM_TIM_0.CH6_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_0_CH6_ECNT       GTM_TIM_0.CH6_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_0_CH6_CNTS       GTM_TIM_0.CH6_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_0_CH6_TDUC       GTM_TIM_0.CH6_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_0_CH6_TDUV       GTM_TIM_0.CH6_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_0_CH6_FLT_RE     GTM_TIM_0.CH6_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_0_CH6_FLT_FE     GTM_TIM_0.CH6_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_0_CH6_CTRL       GTM_TIM_0.CH6_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_0_CH6_ECTRL      GTM_TIM_0.CH6_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_0_CH6_IRQ_NOTIFY GTM_TIM_0.CH6_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_0_CH6_IRQ_EN     GTM_TIM_0.CH6_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_0_CH6_IRQ_FORCINT GTM_TIM_0.CH6_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_0_CH6_IRQ_MODE   GTM_TIM_0.CH6_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_0_CH6_EIRQ_EN    GTM_TIM_0.CH6_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_0_CH7_GPR0       GTM_TIM_0.CH7_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_0_CH7_GPR1       GTM_TIM_0.CH7_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_0_CH7_CNT        GTM_TIM_0.CH7_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_0_CH7_ECNT       GTM_TIM_0.CH7_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_0_CH7_CNTS       GTM_TIM_0.CH7_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_0_CH7_TDUC       GTM_TIM_0.CH7_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_0_CH7_TDUV       GTM_TIM_0.CH7_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_0_CH7_FLT_RE     GTM_TIM_0.CH7_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_0_CH7_FLT_FE     GTM_TIM_0.CH7_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_0_CH7_CTRL       GTM_TIM_0.CH7_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_0_CH7_ECTRL      GTM_TIM_0.CH7_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_0_CH7_IRQ_NOTIFY GTM_TIM_0.CH7_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_0_CH7_IRQ_EN     GTM_TIM_0.CH7_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_0_CH7_IRQ_FORCINT GTM_TIM_0.CH7_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_0_CH7_IRQ_MODE   GTM_TIM_0.CH7_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_0_CH7_EIRQ_EN    GTM_TIM_0.CH7_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */

/* GTM_TIM */
#define GTM_TIM_1_CH0_GPR0       GTM_TIM_1.CH0_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_1_CH0_GPR1       GTM_TIM_1.CH0_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_1_CH0_CNT        GTM_TIM_1.CH0_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_1_CH0_ECNT       GTM_TIM_1.CH0_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_1_CH0_CNTS       GTM_TIM_1.CH0_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_1_CH0_TDUC       GTM_TIM_1.CH0_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_1_CH0_TDUV       GTM_TIM_1.CH0_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_1_CH0_FLT_RE     GTM_TIM_1.CH0_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_1_CH0_FLT_FE     GTM_TIM_1.CH0_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_1_CH0_CTRL       GTM_TIM_1.CH0_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_1_CH0_ECTRL      GTM_TIM_1.CH0_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_1_CH0_IRQ_NOTIFY GTM_TIM_1.CH0_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_1_CH0_IRQ_EN     GTM_TIM_1.CH0_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_1_CH0_IRQ_FORCINT GTM_TIM_1.CH0_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_1_CH0_IRQ_MODE   GTM_TIM_1.CH0_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_1_CH0_EIRQ_EN    GTM_TIM_1.CH0_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_1_IN_SRC         GTM_TIM_1.IN_SRC.R                /* TIM Input Source Register */
#define GTM_TIM_1_RST            GTM_TIM_1.RST.R                   /* TIM Channel Reset Register */
#define GTM_TIM_1_CH1_GPR0       GTM_TIM_1.CH1_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_1_CH1_GPR1       GTM_TIM_1.CH1_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_1_CH1_CNT        GTM_TIM_1.CH1_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_1_CH1_ECNT       GTM_TIM_1.CH1_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_1_CH1_CNTS       GTM_TIM_1.CH1_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_1_CH1_TDUC       GTM_TIM_1.CH1_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_1_CH1_TDUV       GTM_TIM_1.CH1_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_1_CH1_FLT_RE     GTM_TIM_1.CH1_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_1_CH1_FLT_FE     GTM_TIM_1.CH1_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_1_CH1_CTRL       GTM_TIM_1.CH1_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_1_CH1_ECTRL      GTM_TIM_1.CH1_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_1_CH1_IRQ_NOTIFY GTM_TIM_1.CH1_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_1_CH1_IRQ_EN     GTM_TIM_1.CH1_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_1_CH1_IRQ_FORCINT GTM_TIM_1.CH1_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_1_CH1_IRQ_MODE   GTM_TIM_1.CH1_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_1_CH1_EIRQ_EN    GTM_TIM_1.CH1_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_1_CH2_GPR0       GTM_TIM_1.CH2_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_1_CH2_GPR1       GTM_TIM_1.CH2_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_1_CH2_CNT        GTM_TIM_1.CH2_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_1_CH2_ECNT       GTM_TIM_1.CH2_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_1_CH2_CNTS       GTM_TIM_1.CH2_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_1_CH2_TDUC       GTM_TIM_1.CH2_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_1_CH2_TDUV       GTM_TIM_1.CH2_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_1_CH2_FLT_RE     GTM_TIM_1.CH2_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_1_CH2_FLT_FE     GTM_TIM_1.CH2_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_1_CH2_CTRL       GTM_TIM_1.CH2_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_1_CH2_ECTRL      GTM_TIM_1.CH2_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_1_CH2_IRQ_NOTIFY GTM_TIM_1.CH2_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_1_CH2_IRQ_EN     GTM_TIM_1.CH2_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_1_CH2_IRQ_FORCINT GTM_TIM_1.CH2_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_1_CH2_IRQ_MODE   GTM_TIM_1.CH2_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_1_CH2_EIRQ_EN    GTM_TIM_1.CH2_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_1_CH3_GPR0       GTM_TIM_1.CH3_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_1_CH3_GPR1       GTM_TIM_1.CH3_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_1_CH3_CNT        GTM_TIM_1.CH3_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_1_CH3_ECNT       GTM_TIM_1.CH3_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_1_CH3_CNTS       GTM_TIM_1.CH3_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_1_CH3_TDUC       GTM_TIM_1.CH3_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_1_CH3_TDUV       GTM_TIM_1.CH3_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_1_CH3_FLT_RE     GTM_TIM_1.CH3_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_1_CH3_FLT_FE     GTM_TIM_1.CH3_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_1_CH3_CTRL       GTM_TIM_1.CH3_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_1_CH3_ECTRL      GTM_TIM_1.CH3_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_1_CH3_IRQ_NOTIFY GTM_TIM_1.CH3_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_1_CH3_IRQ_EN     GTM_TIM_1.CH3_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_1_CH3_IRQ_FORCINT GTM_TIM_1.CH3_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_1_CH3_IRQ_MODE   GTM_TIM_1.CH3_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_1_CH3_EIRQ_EN    GTM_TIM_1.CH3_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_1_CH4_GPR0       GTM_TIM_1.CH4_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_1_CH4_GPR1       GTM_TIM_1.CH4_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_1_CH4_CNT        GTM_TIM_1.CH4_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_1_CH4_ECNT       GTM_TIM_1.CH4_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_1_CH4_CNTS       GTM_TIM_1.CH4_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_1_CH4_TDUC       GTM_TIM_1.CH4_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_1_CH4_TDUV       GTM_TIM_1.CH4_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_1_CH4_FLT_RE     GTM_TIM_1.CH4_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_1_CH4_FLT_FE     GTM_TIM_1.CH4_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_1_CH4_CTRL       GTM_TIM_1.CH4_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_1_CH4_ECTRL      GTM_TIM_1.CH4_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_1_CH4_IRQ_NOTIFY GTM_TIM_1.CH4_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_1_CH4_IRQ_EN     GTM_TIM_1.CH4_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_1_CH4_IRQ_FORCINT GTM_TIM_1.CH4_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_1_CH4_IRQ_MODE   GTM_TIM_1.CH4_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_1_CH4_EIRQ_EN    GTM_TIM_1.CH4_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_1_CH5_GPR0       GTM_TIM_1.CH5_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_1_CH5_GPR1       GTM_TIM_1.CH5_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_1_CH5_CNT        GTM_TIM_1.CH5_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_1_CH5_ECNT       GTM_TIM_1.CH5_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_1_CH5_CNTS       GTM_TIM_1.CH5_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_1_CH5_TDUC       GTM_TIM_1.CH5_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_1_CH5_TDUV       GTM_TIM_1.CH5_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_1_CH5_FLT_RE     GTM_TIM_1.CH5_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_1_CH5_FLT_FE     GTM_TIM_1.CH5_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_1_CH5_CTRL       GTM_TIM_1.CH5_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_1_CH5_ECTRL      GTM_TIM_1.CH5_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_1_CH5_IRQ_NOTIFY GTM_TIM_1.CH5_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_1_CH5_IRQ_EN     GTM_TIM_1.CH5_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_1_CH5_IRQ_FORCINT GTM_TIM_1.CH5_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_1_CH5_IRQ_MODE   GTM_TIM_1.CH5_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_1_CH5_EIRQ_EN    GTM_TIM_1.CH5_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_1_CH6_GPR0       GTM_TIM_1.CH6_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_1_CH6_GPR1       GTM_TIM_1.CH6_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_1_CH6_CNT        GTM_TIM_1.CH6_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_1_CH6_ECNT       GTM_TIM_1.CH6_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_1_CH6_CNTS       GTM_TIM_1.CH6_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_1_CH6_TDUC       GTM_TIM_1.CH6_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_1_CH6_TDUV       GTM_TIM_1.CH6_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_1_CH6_FLT_RE     GTM_TIM_1.CH6_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_1_CH6_FLT_FE     GTM_TIM_1.CH6_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_1_CH6_CTRL       GTM_TIM_1.CH6_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_1_CH6_ECTRL      GTM_TIM_1.CH6_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_1_CH6_IRQ_NOTIFY GTM_TIM_1.CH6_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_1_CH6_IRQ_EN     GTM_TIM_1.CH6_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_1_CH6_IRQ_FORCINT GTM_TIM_1.CH6_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_1_CH6_IRQ_MODE   GTM_TIM_1.CH6_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_1_CH6_EIRQ_EN    GTM_TIM_1.CH6_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_1_CH7_GPR0       GTM_TIM_1.CH7_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_1_CH7_GPR1       GTM_TIM_1.CH7_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_1_CH7_CNT        GTM_TIM_1.CH7_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_1_CH7_ECNT       GTM_TIM_1.CH7_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_1_CH7_CNTS       GTM_TIM_1.CH7_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_1_CH7_TDUC       GTM_TIM_1.CH7_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_1_CH7_TDUV       GTM_TIM_1.CH7_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_1_CH7_FLT_RE     GTM_TIM_1.CH7_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_1_CH7_FLT_FE     GTM_TIM_1.CH7_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_1_CH7_CTRL       GTM_TIM_1.CH7_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_1_CH7_ECTRL      GTM_TIM_1.CH7_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_1_CH7_IRQ_NOTIFY GTM_TIM_1.CH7_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_1_CH7_IRQ_EN     GTM_TIM_1.CH7_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_1_CH7_IRQ_FORCINT GTM_TIM_1.CH7_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_1_CH7_IRQ_MODE   GTM_TIM_1.CH7_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_1_CH7_EIRQ_EN    GTM_TIM_1.CH7_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */

/* GTM_TIM */
#define GTM_TIM_2_CH0_GPR0       GTM_TIM_2.CH0_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_2_CH0_GPR1       GTM_TIM_2.CH0_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_2_CH0_CNT        GTM_TIM_2.CH0_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_2_CH0_ECNT       GTM_TIM_2.CH0_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_2_CH0_CNTS       GTM_TIM_2.CH0_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_2_CH0_TDUC       GTM_TIM_2.CH0_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_2_CH0_TDUV       GTM_TIM_2.CH0_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_2_CH0_FLT_RE     GTM_TIM_2.CH0_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_2_CH0_FLT_FE     GTM_TIM_2.CH0_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_2_CH0_CTRL       GTM_TIM_2.CH0_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_2_CH0_ECTRL      GTM_TIM_2.CH0_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_2_CH0_IRQ_NOTIFY GTM_TIM_2.CH0_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_2_CH0_IRQ_EN     GTM_TIM_2.CH0_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_2_CH0_IRQ_FORCINT GTM_TIM_2.CH0_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_2_CH0_IRQ_MODE   GTM_TIM_2.CH0_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_2_CH0_EIRQ_EN    GTM_TIM_2.CH0_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_2_IN_SRC         GTM_TIM_2.IN_SRC.R                /* TIM Input Source Register */
#define GTM_TIM_2_RST            GTM_TIM_2.RST.R                   /* TIM Channel Reset Register */
#define GTM_TIM_2_CH1_GPR0       GTM_TIM_2.CH1_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_2_CH1_GPR1       GTM_TIM_2.CH1_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_2_CH1_CNT        GTM_TIM_2.CH1_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_2_CH1_ECNT       GTM_TIM_2.CH1_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_2_CH1_CNTS       GTM_TIM_2.CH1_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_2_CH1_TDUC       GTM_TIM_2.CH1_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_2_CH1_TDUV       GTM_TIM_2.CH1_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_2_CH1_FLT_RE     GTM_TIM_2.CH1_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_2_CH1_FLT_FE     GTM_TIM_2.CH1_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_2_CH1_CTRL       GTM_TIM_2.CH1_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_2_CH1_ECTRL      GTM_TIM_2.CH1_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_2_CH1_IRQ_NOTIFY GTM_TIM_2.CH1_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_2_CH1_IRQ_EN     GTM_TIM_2.CH1_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_2_CH1_IRQ_FORCINT GTM_TIM_2.CH1_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_2_CH1_IRQ_MODE   GTM_TIM_2.CH1_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_2_CH1_EIRQ_EN    GTM_TIM_2.CH1_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_2_CH2_GPR0       GTM_TIM_2.CH2_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_2_CH2_GPR1       GTM_TIM_2.CH2_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_2_CH2_CNT        GTM_TIM_2.CH2_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_2_CH2_ECNT       GTM_TIM_2.CH2_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_2_CH2_CNTS       GTM_TIM_2.CH2_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_2_CH2_TDUC       GTM_TIM_2.CH2_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_2_CH2_TDUV       GTM_TIM_2.CH2_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_2_CH2_FLT_RE     GTM_TIM_2.CH2_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_2_CH2_FLT_FE     GTM_TIM_2.CH2_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_2_CH2_CTRL       GTM_TIM_2.CH2_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_2_CH2_ECTRL      GTM_TIM_2.CH2_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_2_CH2_IRQ_NOTIFY GTM_TIM_2.CH2_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_2_CH2_IRQ_EN     GTM_TIM_2.CH2_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_2_CH2_IRQ_FORCINT GTM_TIM_2.CH2_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_2_CH2_IRQ_MODE   GTM_TIM_2.CH2_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_2_CH2_EIRQ_EN    GTM_TIM_2.CH2_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_2_CH3_GPR0       GTM_TIM_2.CH3_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_2_CH3_GPR1       GTM_TIM_2.CH3_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_2_CH3_CNT        GTM_TIM_2.CH3_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_2_CH3_ECNT       GTM_TIM_2.CH3_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_2_CH3_CNTS       GTM_TIM_2.CH3_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_2_CH3_TDUC       GTM_TIM_2.CH3_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_2_CH3_TDUV       GTM_TIM_2.CH3_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_2_CH3_FLT_RE     GTM_TIM_2.CH3_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_2_CH3_FLT_FE     GTM_TIM_2.CH3_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_2_CH3_CTRL       GTM_TIM_2.CH3_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_2_CH3_ECTRL      GTM_TIM_2.CH3_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_2_CH3_IRQ_NOTIFY GTM_TIM_2.CH3_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_2_CH3_IRQ_EN     GTM_TIM_2.CH3_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_2_CH3_IRQ_FORCINT GTM_TIM_2.CH3_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_2_CH3_IRQ_MODE   GTM_TIM_2.CH3_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_2_CH3_EIRQ_EN    GTM_TIM_2.CH3_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_2_CH4_GPR0       GTM_TIM_2.CH4_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_2_CH4_GPR1       GTM_TIM_2.CH4_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_2_CH4_CNT        GTM_TIM_2.CH4_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_2_CH4_ECNT       GTM_TIM_2.CH4_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_2_CH4_CNTS       GTM_TIM_2.CH4_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_2_CH4_TDUC       GTM_TIM_2.CH4_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_2_CH4_TDUV       GTM_TIM_2.CH4_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_2_CH4_FLT_RE     GTM_TIM_2.CH4_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_2_CH4_FLT_FE     GTM_TIM_2.CH4_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_2_CH4_CTRL       GTM_TIM_2.CH4_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_2_CH4_ECTRL      GTM_TIM_2.CH4_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_2_CH4_IRQ_NOTIFY GTM_TIM_2.CH4_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_2_CH4_IRQ_EN     GTM_TIM_2.CH4_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_2_CH4_IRQ_FORCINT GTM_TIM_2.CH4_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_2_CH4_IRQ_MODE   GTM_TIM_2.CH4_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_2_CH4_EIRQ_EN    GTM_TIM_2.CH4_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_2_CH5_GPR0       GTM_TIM_2.CH5_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_2_CH5_GPR1       GTM_TIM_2.CH5_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_2_CH5_CNT        GTM_TIM_2.CH5_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_2_CH5_ECNT       GTM_TIM_2.CH5_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_2_CH5_CNTS       GTM_TIM_2.CH5_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_2_CH5_TDUC       GTM_TIM_2.CH5_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_2_CH5_TDUV       GTM_TIM_2.CH5_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_2_CH5_FLT_RE     GTM_TIM_2.CH5_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_2_CH5_FLT_FE     GTM_TIM_2.CH5_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_2_CH5_CTRL       GTM_TIM_2.CH5_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_2_CH5_ECTRL      GTM_TIM_2.CH5_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_2_CH5_IRQ_NOTIFY GTM_TIM_2.CH5_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_2_CH5_IRQ_EN     GTM_TIM_2.CH5_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_2_CH5_IRQ_FORCINT GTM_TIM_2.CH5_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_2_CH5_IRQ_MODE   GTM_TIM_2.CH5_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_2_CH5_EIRQ_EN    GTM_TIM_2.CH5_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_2_CH6_GPR0       GTM_TIM_2.CH6_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_2_CH6_GPR1       GTM_TIM_2.CH6_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_2_CH6_CNT        GTM_TIM_2.CH6_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_2_CH6_ECNT       GTM_TIM_2.CH6_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_2_CH6_CNTS       GTM_TIM_2.CH6_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_2_CH6_TDUC       GTM_TIM_2.CH6_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_2_CH6_TDUV       GTM_TIM_2.CH6_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_2_CH6_FLT_RE     GTM_TIM_2.CH6_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_2_CH6_FLT_FE     GTM_TIM_2.CH6_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_2_CH6_CTRL       GTM_TIM_2.CH6_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_2_CH6_ECTRL      GTM_TIM_2.CH6_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_2_CH6_IRQ_NOTIFY GTM_TIM_2.CH6_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_2_CH6_IRQ_EN     GTM_TIM_2.CH6_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_2_CH6_IRQ_FORCINT GTM_TIM_2.CH6_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_2_CH6_IRQ_MODE   GTM_TIM_2.CH6_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_2_CH6_EIRQ_EN    GTM_TIM_2.CH6_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_2_CH7_GPR0       GTM_TIM_2.CH7_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_2_CH7_GPR1       GTM_TIM_2.CH7_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_2_CH7_CNT        GTM_TIM_2.CH7_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_2_CH7_ECNT       GTM_TIM_2.CH7_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_2_CH7_CNTS       GTM_TIM_2.CH7_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_2_CH7_TDUC       GTM_TIM_2.CH7_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_2_CH7_TDUV       GTM_TIM_2.CH7_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_2_CH7_FLT_RE     GTM_TIM_2.CH7_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_2_CH7_FLT_FE     GTM_TIM_2.CH7_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_2_CH7_CTRL       GTM_TIM_2.CH7_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_2_CH7_ECTRL      GTM_TIM_2.CH7_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_2_CH7_IRQ_NOTIFY GTM_TIM_2.CH7_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_2_CH7_IRQ_EN     GTM_TIM_2.CH7_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_2_CH7_IRQ_FORCINT GTM_TIM_2.CH7_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_2_CH7_IRQ_MODE   GTM_TIM_2.CH7_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_2_CH7_EIRQ_EN    GTM_TIM_2.CH7_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */

/* GTM_TIM */
#define GTM_TIM_3_CH0_GPR0       GTM_TIM_3.CH0_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_3_CH0_GPR1       GTM_TIM_3.CH0_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_3_CH0_CNT        GTM_TIM_3.CH0_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_3_CH0_ECNT       GTM_TIM_3.CH0_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_3_CH0_CNTS       GTM_TIM_3.CH0_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_3_CH0_TDUC       GTM_TIM_3.CH0_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_3_CH0_TDUV       GTM_TIM_3.CH0_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_3_CH0_FLT_RE     GTM_TIM_3.CH0_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_3_CH0_FLT_FE     GTM_TIM_3.CH0_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_3_CH0_CTRL       GTM_TIM_3.CH0_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_3_CH0_ECTRL      GTM_TIM_3.CH0_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_3_CH0_IRQ_NOTIFY GTM_TIM_3.CH0_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_3_CH0_IRQ_EN     GTM_TIM_3.CH0_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_3_CH0_IRQ_FORCINT GTM_TIM_3.CH0_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_3_CH0_IRQ_MODE   GTM_TIM_3.CH0_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_3_CH0_EIRQ_EN    GTM_TIM_3.CH0_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_3_IN_SRC         GTM_TIM_3.IN_SRC.R                /* TIM Input Source Register */
#define GTM_TIM_3_RST            GTM_TIM_3.RST.R                   /* TIM Channel Reset Register */
#define GTM_TIM_3_CH1_GPR0       GTM_TIM_3.CH1_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_3_CH1_GPR1       GTM_TIM_3.CH1_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_3_CH1_CNT        GTM_TIM_3.CH1_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_3_CH1_ECNT       GTM_TIM_3.CH1_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_3_CH1_CNTS       GTM_TIM_3.CH1_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_3_CH1_TDUC       GTM_TIM_3.CH1_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_3_CH1_TDUV       GTM_TIM_3.CH1_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_3_CH1_FLT_RE     GTM_TIM_3.CH1_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_3_CH1_FLT_FE     GTM_TIM_3.CH1_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_3_CH1_CTRL       GTM_TIM_3.CH1_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_3_CH1_ECTRL      GTM_TIM_3.CH1_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_3_CH1_IRQ_NOTIFY GTM_TIM_3.CH1_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_3_CH1_IRQ_EN     GTM_TIM_3.CH1_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_3_CH1_IRQ_FORCINT GTM_TIM_3.CH1_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_3_CH1_IRQ_MODE   GTM_TIM_3.CH1_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_3_CH1_EIRQ_EN    GTM_TIM_3.CH1_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_3_CH2_GPR0       GTM_TIM_3.CH2_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_3_CH2_GPR1       GTM_TIM_3.CH2_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_3_CH2_CNT        GTM_TIM_3.CH2_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_3_CH2_ECNT       GTM_TIM_3.CH2_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_3_CH2_CNTS       GTM_TIM_3.CH2_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_3_CH2_TDUC       GTM_TIM_3.CH2_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_3_CH2_TDUV       GTM_TIM_3.CH2_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_3_CH2_FLT_RE     GTM_TIM_3.CH2_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_3_CH2_FLT_FE     GTM_TIM_3.CH2_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_3_CH2_CTRL       GTM_TIM_3.CH2_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_3_CH2_ECTRL      GTM_TIM_3.CH2_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_3_CH2_IRQ_NOTIFY GTM_TIM_3.CH2_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_3_CH2_IRQ_EN     GTM_TIM_3.CH2_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_3_CH2_IRQ_FORCINT GTM_TIM_3.CH2_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_3_CH2_IRQ_MODE   GTM_TIM_3.CH2_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_3_CH2_EIRQ_EN    GTM_TIM_3.CH2_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_3_CH3_GPR0       GTM_TIM_3.CH3_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_3_CH3_GPR1       GTM_TIM_3.CH3_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_3_CH3_CNT        GTM_TIM_3.CH3_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_3_CH3_ECNT       GTM_TIM_3.CH3_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_3_CH3_CNTS       GTM_TIM_3.CH3_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_3_CH3_TDUC       GTM_TIM_3.CH3_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_3_CH3_TDUV       GTM_TIM_3.CH3_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_3_CH3_FLT_RE     GTM_TIM_3.CH3_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_3_CH3_FLT_FE     GTM_TIM_3.CH3_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_3_CH3_CTRL       GTM_TIM_3.CH3_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_3_CH3_ECTRL      GTM_TIM_3.CH3_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_3_CH3_IRQ_NOTIFY GTM_TIM_3.CH3_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_3_CH3_IRQ_EN     GTM_TIM_3.CH3_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_3_CH3_IRQ_FORCINT GTM_TIM_3.CH3_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_3_CH3_IRQ_MODE   GTM_TIM_3.CH3_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_3_CH3_EIRQ_EN    GTM_TIM_3.CH3_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_3_CH4_GPR0       GTM_TIM_3.CH4_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_3_CH4_GPR1       GTM_TIM_3.CH4_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_3_CH4_CNT        GTM_TIM_3.CH4_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_3_CH4_ECNT       GTM_TIM_3.CH4_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_3_CH4_CNTS       GTM_TIM_3.CH4_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_3_CH4_TDUC       GTM_TIM_3.CH4_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_3_CH4_TDUV       GTM_TIM_3.CH4_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_3_CH4_FLT_RE     GTM_TIM_3.CH4_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_3_CH4_FLT_FE     GTM_TIM_3.CH4_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_3_CH4_CTRL       GTM_TIM_3.CH4_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_3_CH4_ECTRL      GTM_TIM_3.CH4_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_3_CH4_IRQ_NOTIFY GTM_TIM_3.CH4_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_3_CH4_IRQ_EN     GTM_TIM_3.CH4_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_3_CH4_IRQ_FORCINT GTM_TIM_3.CH4_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_3_CH4_IRQ_MODE   GTM_TIM_3.CH4_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_3_CH4_EIRQ_EN    GTM_TIM_3.CH4_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_3_CH5_GPR0       GTM_TIM_3.CH5_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_3_CH5_GPR1       GTM_TIM_3.CH5_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_3_CH5_CNT        GTM_TIM_3.CH5_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_3_CH5_ECNT       GTM_TIM_3.CH5_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_3_CH5_CNTS       GTM_TIM_3.CH5_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_3_CH5_TDUC       GTM_TIM_3.CH5_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_3_CH5_TDUV       GTM_TIM_3.CH5_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_3_CH5_FLT_RE     GTM_TIM_3.CH5_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_3_CH5_FLT_FE     GTM_TIM_3.CH5_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_3_CH5_CTRL       GTM_TIM_3.CH5_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_3_CH5_ECTRL      GTM_TIM_3.CH5_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_3_CH5_IRQ_NOTIFY GTM_TIM_3.CH5_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_3_CH5_IRQ_EN     GTM_TIM_3.CH5_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_3_CH5_IRQ_FORCINT GTM_TIM_3.CH5_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_3_CH5_IRQ_MODE   GTM_TIM_3.CH5_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_3_CH5_EIRQ_EN    GTM_TIM_3.CH5_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_3_CH6_GPR0       GTM_TIM_3.CH6_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_3_CH6_GPR1       GTM_TIM_3.CH6_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_3_CH6_CNT        GTM_TIM_3.CH6_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_3_CH6_ECNT       GTM_TIM_3.CH6_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_3_CH6_CNTS       GTM_TIM_3.CH6_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_3_CH6_TDUC       GTM_TIM_3.CH6_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_3_CH6_TDUV       GTM_TIM_3.CH6_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_3_CH6_FLT_RE     GTM_TIM_3.CH6_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_3_CH6_FLT_FE     GTM_TIM_3.CH6_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_3_CH6_CTRL       GTM_TIM_3.CH6_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_3_CH6_ECTRL      GTM_TIM_3.CH6_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_3_CH6_IRQ_NOTIFY GTM_TIM_3.CH6_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_3_CH6_IRQ_EN     GTM_TIM_3.CH6_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_3_CH6_IRQ_FORCINT GTM_TIM_3.CH6_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_3_CH6_IRQ_MODE   GTM_TIM_3.CH6_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_3_CH6_EIRQ_EN    GTM_TIM_3.CH6_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_3_CH7_GPR0       GTM_TIM_3.CH7_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_3_CH7_GPR1       GTM_TIM_3.CH7_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_3_CH7_CNT        GTM_TIM_3.CH7_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_3_CH7_ECNT       GTM_TIM_3.CH7_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_3_CH7_CNTS       GTM_TIM_3.CH7_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_3_CH7_TDUC       GTM_TIM_3.CH7_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_3_CH7_TDUV       GTM_TIM_3.CH7_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_3_CH7_FLT_RE     GTM_TIM_3.CH7_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_3_CH7_FLT_FE     GTM_TIM_3.CH7_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_3_CH7_CTRL       GTM_TIM_3.CH7_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_3_CH7_ECTRL      GTM_TIM_3.CH7_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_3_CH7_IRQ_NOTIFY GTM_TIM_3.CH7_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_3_CH7_IRQ_EN     GTM_TIM_3.CH7_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_3_CH7_IRQ_FORCINT GTM_TIM_3.CH7_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_3_CH7_IRQ_MODE   GTM_TIM_3.CH7_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_3_CH7_EIRQ_EN    GTM_TIM_3.CH7_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */

/* GTM_TIM */
#define GTM_TIM_4_CH0_GPR0       GTM_TIM_4.CH0_GPR0.R              /* TIM Channel n General Purpose Register 0 */
#define GTM_TIM_4_CH0_GPR1       GTM_TIM_4.CH0_GPR1.R              /* TIM Channel n General Purpose Register 1 */
#define GTM_TIM_4_CH0_CNT        GTM_TIM_4.CH0_CNT.R               /* TIM Channel n Count Register */
#define GTM_TIM_4_CH0_ECNT       GTM_TIM_4.CH0_ECNT.R              /* TIM Channel Edge Counter register */
#define GTM_TIM_4_CH0_CNTS       GTM_TIM_4.CH0_CNTS.R              /* TIM Channel n Counter Shadow Register */
#define GTM_TIM_4_CH0_TDUC       GTM_TIM_4.CH0_TDUC.R              /* TIM Channel TDUC register */
#define GTM_TIM_4_CH0_TDUV       GTM_TIM_4.CH0_TDUV.R              /* TIM Channel TDUV register */
#define GTM_TIM_4_CH0_FLT_RE     GTM_TIM_4.CH0_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register */
#define GTM_TIM_4_CH0_FLT_FE     GTM_TIM_4.CH0_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register */
#define GTM_TIM_4_CH0_CTRL       GTM_TIM_4.CH0_CTRL.R              /* TIM Channel Control register */
#define GTM_TIM_4_CH0_ECTRL      GTM_TIM_4.CH0_ECTRL.R             /* TIM Channel External Control register */
#define GTM_TIM_4_CH0_IRQ_NOTIFY GTM_TIM_4.CH0_IRQ_NOTIFY.R        /* TIM Channel n IRQ Notification Register */
#define GTM_TIM_4_CH0_IRQ_EN     GTM_TIM_4.CH0_IRQ_EN.R            /* TIM Channel n IRQ Enable Register */
#define GTM_TIM_4_CH0_IRQ_FORCINT GTM_TIM_4.CH0_IRQ_FORCINT.R      /* TIM Channel n Force IRQ Register */
#define GTM_TIM_4_CH0_IRQ_MODE   GTM_TIM_4.CH0_IRQ_MODE.R          /* TIM Channel n IRQ Mode Register */
#define GTM_TIM_4_CH0_EIRQ_EN    GTM_TIM_4.CH0_EIRQ_EN.R           /* TIM Channel Error Interrupt Enable register */
#define GTM_TIM_4_IN_SRC         GTM_TIM_4.IN_SRC.R                /* TIM Input Source register */
#define GTM_TIM_4_RST            GTM_TIM_4.RST.R                   /* TIM Channel n Reset Register */
#define GTM_TIM_4_CH1_GPR0       GTM_TIM_4.CH1_GPR0.R              /* TIM Channel n General Purpose Register 0 */
#define GTM_TIM_4_CH1_GPR1       GTM_TIM_4.CH1_GPR1.R              /* TIM Channel n General Purpose Register 1 */
#define GTM_TIM_4_CH1_CNT        GTM_TIM_4.CH1_CNT.R               /* TIM Channel n Count Register */
#define GTM_TIM_4_CH1_ECNT       GTM_TIM_4.CH1_ECNT.R              /* TIM Channel Edge Counter register */
#define GTM_TIM_4_CH1_CNTS       GTM_TIM_4.CH1_CNTS.R              /* TIM Channel n Counter Shadow Register */
#define GTM_TIM_4_CH1_TDUC       GTM_TIM_4.CH1_TDUC.R              /* TIM Channel TDUC register */
#define GTM_TIM_4_CH1_TDUV       GTM_TIM_4.CH1_TDUV.R              /* TIM Channel TDUV register */
#define GTM_TIM_4_CH1_FLT_RE     GTM_TIM_4.CH1_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register */
#define GTM_TIM_4_CH1_FLT_FE     GTM_TIM_4.CH1_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register */
#define GTM_TIM_4_CH1_CTRL       GTM_TIM_4.CH1_CTRL.R              /* TIM Channel Control register */
#define GTM_TIM_4_CH1_ECTRL      GTM_TIM_4.CH1_ECTRL.R             /* TIM Channel External Control register */
#define GTM_TIM_4_CH1_IRQ_NOTIFY GTM_TIM_4.CH1_IRQ_NOTIFY.R        /* TIM Channel n IRQ Notification Register */
#define GTM_TIM_4_CH1_IRQ_EN     GTM_TIM_4.CH1_IRQ_EN.R            /* TIM Channel n IRQ Enable Register */
#define GTM_TIM_4_CH1_IRQ_FORCINT GTM_TIM_4.CH1_IRQ_FORCINT.R      /* TIM Channel n Force IRQ Register */
#define GTM_TIM_4_CH1_IRQ_MODE   GTM_TIM_4.CH1_IRQ_MODE.R          /* TIM Channel n IRQ Mode Register */
#define GTM_TIM_4_CH1_EIRQ_EN    GTM_TIM_4.CH1_EIRQ_EN.R           /* TIM Channel Error Interrupt Enable register */
#define GTM_TIM_4_CH2_GPR0       GTM_TIM_4.CH2_GPR0.R              /* TIM Channel n General Purpose Register 0 */
#define GTM_TIM_4_CH2_GPR1       GTM_TIM_4.CH2_GPR1.R              /* TIM Channel n General Purpose Register 1 */
#define GTM_TIM_4_CH2_CNT        GTM_TIM_4.CH2_CNT.R               /* TIM Channel n Count Register */
#define GTM_TIM_4_CH2_ECNT       GTM_TIM_4.CH2_ECNT.R              /* TIM Channel Edge Counter register */
#define GTM_TIM_4_CH2_CNTS       GTM_TIM_4.CH2_CNTS.R              /* TIM Channel n Counter Shadow Register */
#define GTM_TIM_4_CH2_TDUC       GTM_TIM_4.CH2_TDUC.R              /* TIM Channel TDUC register */
#define GTM_TIM_4_CH2_TDUV       GTM_TIM_4.CH2_TDUV.R              /* TIM Channel TDUV register */
#define GTM_TIM_4_CH2_FLT_RE     GTM_TIM_4.CH2_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register */
#define GTM_TIM_4_CH2_FLT_FE     GTM_TIM_4.CH2_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register */
#define GTM_TIM_4_CH2_CTRL       GTM_TIM_4.CH2_CTRL.R              /* TIM Channel Control register */
#define GTM_TIM_4_CH2_ECTRL      GTM_TIM_4.CH2_ECTRL.R             /* TIM Channel External Control register */
#define GTM_TIM_4_CH2_IRQ_NOTIFY GTM_TIM_4.CH2_IRQ_NOTIFY.R        /* TIM Channel n IRQ Notification Register */
#define GTM_TIM_4_CH2_IRQ_EN     GTM_TIM_4.CH2_IRQ_EN.R            /* TIM Channel n IRQ Enable Register */
#define GTM_TIM_4_CH2_IRQ_FORCINT GTM_TIM_4.CH2_IRQ_FORCINT.R      /* TIM Channel n Force IRQ Register */
#define GTM_TIM_4_CH2_IRQ_MODE   GTM_TIM_4.CH2_IRQ_MODE.R          /* TIM Channel n IRQ Mode Register */
#define GTM_TIM_4_CH2_EIRQ_EN    GTM_TIM_4.CH2_EIRQ_EN.R           /* TIM Channel Error Interrupt Enable register */
#define GTM_TIM_4_CH3_GPR0       GTM_TIM_4.CH3_GPR0.R              /* TIM Channel n General Purpose Register 0 */
#define GTM_TIM_4_CH3_GPR1       GTM_TIM_4.CH3_GPR1.R              /* TIM Channel n General Purpose Register 1 */
#define GTM_TIM_4_CH3_CNT        GTM_TIM_4.CH3_CNT.R               /* TIM Channel n Count Register */
#define GTM_TIM_4_CH3_ECNT       GTM_TIM_4.CH3_ECNT.R              /* TIM Channel Edge Counter register */
#define GTM_TIM_4_CH3_CNTS       GTM_TIM_4.CH3_CNTS.R              /* TIM Channel n Counter Shadow Register */
#define GTM_TIM_4_CH3_TDUC       GTM_TIM_4.CH3_TDUC.R              /* TIM Channel TDUC register */
#define GTM_TIM_4_CH3_TDUV       GTM_TIM_4.CH3_TDUV.R              /* TIM Channel TDUV register */
#define GTM_TIM_4_CH3_FLT_RE     GTM_TIM_4.CH3_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register */
#define GTM_TIM_4_CH3_FLT_FE     GTM_TIM_4.CH3_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register */
#define GTM_TIM_4_CH3_CTRL       GTM_TIM_4.CH3_CTRL.R              /* TIM Channel Control register */
#define GTM_TIM_4_CH3_ECTRL      GTM_TIM_4.CH3_ECTRL.R             /* TIM Channel External Control register */
#define GTM_TIM_4_CH3_IRQ_NOTIFY GTM_TIM_4.CH3_IRQ_NOTIFY.R        /* TIM Channel n IRQ Notification Register */
#define GTM_TIM_4_CH3_IRQ_EN     GTM_TIM_4.CH3_IRQ_EN.R            /* TIM Channel n IRQ Enable Register */
#define GTM_TIM_4_CH3_IRQ_FORCINT GTM_TIM_4.CH3_IRQ_FORCINT.R      /* TIM Channel n Force IRQ Register */
#define GTM_TIM_4_CH3_IRQ_MODE   GTM_TIM_4.CH3_IRQ_MODE.R          /* TIM Channel n IRQ Mode Register */
#define GTM_TIM_4_CH3_EIRQ_EN    GTM_TIM_4.CH3_EIRQ_EN.R           /* TIM Channel Error Interrupt Enable register */
#define GTM_TIM_4_CH4_GPR0       GTM_TIM_4.CH4_GPR0.R              /* TIM Channel n General Purpose Register 0 */
#define GTM_TIM_4_CH4_GPR1       GTM_TIM_4.CH4_GPR1.R              /* TIM Channel n General Purpose Register 1 */
#define GTM_TIM_4_CH4_CNT        GTM_TIM_4.CH4_CNT.R               /* TIM Channel n Count Register */
#define GTM_TIM_4_CH4_ECNT       GTM_TIM_4.CH4_ECNT.R              /* TIM Channel Edge Counter register */
#define GTM_TIM_4_CH4_CNTS       GTM_TIM_4.CH4_CNTS.R              /* TIM Channel n Counter Shadow Register */
#define GTM_TIM_4_CH4_TDUC       GTM_TIM_4.CH4_TDUC.R              /* TIM Channel TDUC register */
#define GTM_TIM_4_CH4_TDUV       GTM_TIM_4.CH4_TDUV.R              /* TIM Channel TDUV register */
#define GTM_TIM_4_CH4_FLT_RE     GTM_TIM_4.CH4_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register */
#define GTM_TIM_4_CH4_FLT_FE     GTM_TIM_4.CH4_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register */
#define GTM_TIM_4_CH4_CTRL       GTM_TIM_4.CH4_CTRL.R              /* TIM Channel Control register */
#define GTM_TIM_4_CH4_ECTRL      GTM_TIM_4.CH4_ECTRL.R             /* TIM Channel External Control register */
#define GTM_TIM_4_CH4_IRQ_NOTIFY GTM_TIM_4.CH4_IRQ_NOTIFY.R        /* TIM Channel n IRQ Notification Register */
#define GTM_TIM_4_CH4_IRQ_EN     GTM_TIM_4.CH4_IRQ_EN.R            /* TIM Channel n IRQ Enable Register */
#define GTM_TIM_4_CH4_IRQ_FORCINT GTM_TIM_4.CH4_IRQ_FORCINT.R      /* TIM Channel n Force IRQ Register */
#define GTM_TIM_4_CH4_IRQ_MODE   GTM_TIM_4.CH4_IRQ_MODE.R          /* TIM Channel n IRQ Mode Register */
#define GTM_TIM_4_CH4_EIRQ_EN    GTM_TIM_4.CH4_EIRQ_EN.R           /* TIM Channel Error Interrupt Enable register */
#define GTM_TIM_4_CH5_GPR0       GTM_TIM_4.CH5_GPR0.R              /* TIM Channel n General Purpose Register 0 */
#define GTM_TIM_4_CH5_GPR1       GTM_TIM_4.CH5_GPR1.R              /* TIM Channel n General Purpose Register 1 */
#define GTM_TIM_4_CH5_CNT        GTM_TIM_4.CH5_CNT.R               /* TIM Channel n Count Register */
#define GTM_TIM_4_CH5_ECNT       GTM_TIM_4.CH5_ECNT.R              /* TIM Channel Edge Counter register */
#define GTM_TIM_4_CH5_CNTS       GTM_TIM_4.CH5_CNTS.R              /* TIM Channel n Counter Shadow Register */
#define GTM_TIM_4_CH5_TDUC       GTM_TIM_4.CH5_TDUC.R              /* TIM Channel TDUC register */
#define GTM_TIM_4_CH5_TDUV       GTM_TIM_4.CH5_TDUV.R              /* TIM Channel TDUV register */
#define GTM_TIM_4_CH5_FLT_RE     GTM_TIM_4.CH5_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register */
#define GTM_TIM_4_CH5_FLT_FE     GTM_TIM_4.CH5_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register */
#define GTM_TIM_4_CH5_CTRL       GTM_TIM_4.CH5_CTRL.R              /* TIM Channel Control register */
#define GTM_TIM_4_CH5_ECTRL      GTM_TIM_4.CH5_ECTRL.R             /* TIM Channel External Control register */
#define GTM_TIM_4_CH5_IRQ_NOTIFY GTM_TIM_4.CH5_IRQ_NOTIFY.R        /* TIM Channel n IRQ Notification Register */
#define GTM_TIM_4_CH5_IRQ_EN     GTM_TIM_4.CH5_IRQ_EN.R            /* TIM Channel n IRQ Enable Register */
#define GTM_TIM_4_CH5_IRQ_FORCINT GTM_TIM_4.CH5_IRQ_FORCINT.R      /* TIM Channel n Force IRQ Register */
#define GTM_TIM_4_CH5_IRQ_MODE   GTM_TIM_4.CH5_IRQ_MODE.R          /* TIM Channel n IRQ Mode Register */
#define GTM_TIM_4_CH5_EIRQ_EN    GTM_TIM_4.CH5_EIRQ_EN.R           /* TIM Channel Error Interrupt Enable register */
#define GTM_TIM_4_CH6_GPR0       GTM_TIM_4.CH6_GPR0.R              /* TIM Channel n General Purpose Register 0 */
#define GTM_TIM_4_CH6_GPR1       GTM_TIM_4.CH6_GPR1.R              /* TIM Channel n General Purpose Register 1 */
#define GTM_TIM_4_CH6_CNT        GTM_TIM_4.CH6_CNT.R               /* TIM Channel n Count Register */
#define GTM_TIM_4_CH6_ECNT       GTM_TIM_4.CH6_ECNT.R              /* TIM Channel Edge Counter register */
#define GTM_TIM_4_CH6_CNTS       GTM_TIM_4.CH6_CNTS.R              /* TIM Channel n Counter Shadow Register */
#define GTM_TIM_4_CH6_TDUC       GTM_TIM_4.CH6_TDUC.R              /* TIM Channel TDUC register */
#define GTM_TIM_4_CH6_TDUV       GTM_TIM_4.CH6_TDUV.R              /* TIM Channel TDUV register */
#define GTM_TIM_4_CH6_FLT_RE     GTM_TIM_4.CH6_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register */
#define GTM_TIM_4_CH6_FLT_FE     GTM_TIM_4.CH6_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register */
#define GTM_TIM_4_CH6_CTRL       GTM_TIM_4.CH6_CTRL.R              /* TIM Channel Control register */
#define GTM_TIM_4_CH6_ECTRL      GTM_TIM_4.CH6_ECTRL.R             /* TIM Channel External Control register */
#define GTM_TIM_4_CH6_IRQ_NOTIFY GTM_TIM_4.CH6_IRQ_NOTIFY.R        /* TIM Channel n IRQ Notification Register */
#define GTM_TIM_4_CH6_IRQ_EN     GTM_TIM_4.CH6_IRQ_EN.R            /* TIM Channel n IRQ Enable Register */
#define GTM_TIM_4_CH6_IRQ_FORCINT GTM_TIM_4.CH6_IRQ_FORCINT.R      /* TIM Channel n Force IRQ Register */
#define GTM_TIM_4_CH6_IRQ_MODE   GTM_TIM_4.CH6_IRQ_MODE.R          /* TIM Channel n IRQ Mode Register */
#define GTM_TIM_4_CH6_EIRQ_EN    GTM_TIM_4.CH6_EIRQ_EN.R           /* TIM Channel Error Interrupt Enable register */
#define GTM_TIM_4_CH7_GPR0       GTM_TIM_4.CH7_GPR0.R              /* TIM Channel n General Purpose Register 0 */
#define GTM_TIM_4_CH7_GPR1       GTM_TIM_4.CH7_GPR1.R              /* TIM Channel n General Purpose Register 1 */
#define GTM_TIM_4_CH7_CNT        GTM_TIM_4.CH7_CNT.R               /* TIM Channel n Count Register */
#define GTM_TIM_4_CH7_ECNT       GTM_TIM_4.CH7_ECNT.R              /* TIM Channel Edge Counter register */
#define GTM_TIM_4_CH7_CNTS       GTM_TIM_4.CH7_CNTS.R              /* TIM Channel n Counter Shadow Register */
#define GTM_TIM_4_CH7_TDUC       GTM_TIM_4.CH7_TDUC.R              /* TIM Channel TDUC register */
#define GTM_TIM_4_CH7_TDUV       GTM_TIM_4.CH7_TDUV.R              /* TIM Channel TDUV register */
#define GTM_TIM_4_CH7_FLT_RE     GTM_TIM_4.CH7_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register */
#define GTM_TIM_4_CH7_FLT_FE     GTM_TIM_4.CH7_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register */
#define GTM_TIM_4_CH7_CTRL       GTM_TIM_4.CH7_CTRL.R              /* TIM Channel Control register */
#define GTM_TIM_4_CH7_ECTRL      GTM_TIM_4.CH7_ECTRL.R             /* TIM Channel External Control register */
#define GTM_TIM_4_CH7_IRQ_NOTIFY GTM_TIM_4.CH7_IRQ_NOTIFY.R        /* TIM Channel n IRQ Notification Register */
#define GTM_TIM_4_CH7_IRQ_EN     GTM_TIM_4.CH7_IRQ_EN.R            /* TIM Channel n IRQ Enable Register */
#define GTM_TIM_4_CH7_IRQ_FORCINT GTM_TIM_4.CH7_IRQ_FORCINT.R      /* TIM Channel n Force IRQ Register */
#define GTM_TIM_4_CH7_IRQ_MODE   GTM_TIM_4.CH7_IRQ_MODE.R          /* TIM Channel n IRQ Mode Register */
#define GTM_TIM_4_CH7_EIRQ_EN    GTM_TIM_4.CH7_EIRQ_EN.R           /* TIM Channel Error Interrupt Enable register */

/* GTM_TIM */
#define GTM_TIM_5_CH0_GPR0       GTM_TIM_5.CH0_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_5_CH0_GPR1       GTM_TIM_5.CH0_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_5_CH0_CNT        GTM_TIM_5.CH0_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_5_CH0_ECNT       GTM_TIM_5.CH0_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_5_CH0_CNTS       GTM_TIM_5.CH0_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_5_CH0_TDUC       GTM_TIM_5.CH0_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_5_CH0_TDUV       GTM_TIM_5.CH0_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_5_CH0_FLT_RE     GTM_TIM_5.CH0_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_5_CH0_FLT_FE     GTM_TIM_5.CH0_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_5_CH0_CTRL       GTM_TIM_5.CH0_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_5_CH0_ECTRL      GTM_TIM_5.CH0_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_5_CH0_IRQ_NOTIFY GTM_TIM_5.CH0_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_5_CH0_IRQ_EN     GTM_TIM_5.CH0_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_5_CH0_IRQ_FORCINT GTM_TIM_5.CH0_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_5_CH0_IRQ_MODE   GTM_TIM_5.CH0_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_5_CH0_EIRQ_EN    GTM_TIM_5.CH0_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_5_IN_SRC         GTM_TIM_5.IN_SRC.R                /* TIM0 Input Source Register */
#define GTM_TIM_5_RST            GTM_TIM_5.RST.R                   /* TIM Channel Reset Register */
#define GTM_TIM_5_CH1_GPR0       GTM_TIM_5.CH1_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_5_CH1_GPR1       GTM_TIM_5.CH1_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_5_CH1_CNT        GTM_TIM_5.CH1_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_5_CH1_ECNT       GTM_TIM_5.CH1_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_5_CH1_CNTS       GTM_TIM_5.CH1_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_5_CH1_TDUC       GTM_TIM_5.CH1_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_5_CH1_TDUV       GTM_TIM_5.CH1_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_5_CH1_FLT_RE     GTM_TIM_5.CH1_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_5_CH1_FLT_FE     GTM_TIM_5.CH1_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_5_CH1_CTRL       GTM_TIM_5.CH1_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_5_CH1_ECTRL      GTM_TIM_5.CH1_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_5_CH1_IRQ_NOTIFY GTM_TIM_5.CH1_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_5_CH1_IRQ_EN     GTM_TIM_5.CH1_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_5_CH1_IRQ_FORCINT GTM_TIM_5.CH1_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_5_CH1_IRQ_MODE   GTM_TIM_5.CH1_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_5_CH1_EIRQ_EN    GTM_TIM_5.CH1_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_5_CH2_GPR0       GTM_TIM_5.CH2_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_5_CH2_GPR1       GTM_TIM_5.CH2_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_5_CH2_CNT        GTM_TIM_5.CH2_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_5_CH2_ECNT       GTM_TIM_5.CH2_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_5_CH2_CNTS       GTM_TIM_5.CH2_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_5_CH2_TDUC       GTM_TIM_5.CH2_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_5_CH2_TDUV       GTM_TIM_5.CH2_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_5_CH2_FLT_RE     GTM_TIM_5.CH2_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_5_CH2_FLT_FE     GTM_TIM_5.CH2_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_5_CH2_CTRL       GTM_TIM_5.CH2_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_5_CH2_ECTRL      GTM_TIM_5.CH2_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_5_CH2_IRQ_NOTIFY GTM_TIM_5.CH2_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_5_CH2_IRQ_EN     GTM_TIM_5.CH2_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_5_CH2_IRQ_FORCINT GTM_TIM_5.CH2_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_5_CH2_IRQ_MODE   GTM_TIM_5.CH2_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_5_CH2_EIRQ_EN    GTM_TIM_5.CH2_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_5_CH3_GPR0       GTM_TIM_5.CH3_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_5_CH3_GPR1       GTM_TIM_5.CH3_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_5_CH3_CNT        GTM_TIM_5.CH3_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_5_CH3_ECNT       GTM_TIM_5.CH3_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_5_CH3_CNTS       GTM_TIM_5.CH3_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_5_CH3_TDUC       GTM_TIM_5.CH3_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_5_CH3_TDUV       GTM_TIM_5.CH3_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_5_CH3_FLT_RE     GTM_TIM_5.CH3_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_5_CH3_FLT_FE     GTM_TIM_5.CH3_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_5_CH3_CTRL       GTM_TIM_5.CH3_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_5_CH3_ECTRL      GTM_TIM_5.CH3_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_5_CH3_IRQ_NOTIFY GTM_TIM_5.CH3_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_5_CH3_IRQ_EN     GTM_TIM_5.CH3_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_5_CH3_IRQ_FORCINT GTM_TIM_5.CH3_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_5_CH3_IRQ_MODE   GTM_TIM_5.CH3_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_5_CH3_EIRQ_EN    GTM_TIM_5.CH3_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_5_CH4_GPR0       GTM_TIM_5.CH4_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_5_CH4_GPR1       GTM_TIM_5.CH4_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_5_CH4_CNT        GTM_TIM_5.CH4_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_5_CH4_ECNT       GTM_TIM_5.CH4_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_5_CH4_CNTS       GTM_TIM_5.CH4_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_5_CH4_TDUC       GTM_TIM_5.CH4_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_5_CH4_TDUV       GTM_TIM_5.CH4_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_5_CH4_FLT_RE     GTM_TIM_5.CH4_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_5_CH4_FLT_FE     GTM_TIM_5.CH4_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_5_CH4_CTRL       GTM_TIM_5.CH4_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_5_CH4_ECTRL      GTM_TIM_5.CH4_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_5_CH4_IRQ_NOTIFY GTM_TIM_5.CH4_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_5_CH4_IRQ_EN     GTM_TIM_5.CH4_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_5_CH4_IRQ_FORCINT GTM_TIM_5.CH4_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_5_CH4_IRQ_MODE   GTM_TIM_5.CH4_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_5_CH4_EIRQ_EN    GTM_TIM_5.CH4_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_5_CH5_GPR0       GTM_TIM_5.CH5_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_5_CH5_GPR1       GTM_TIM_5.CH5_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_5_CH5_CNT        GTM_TIM_5.CH5_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_5_CH5_ECNT       GTM_TIM_5.CH5_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_5_CH5_CNTS       GTM_TIM_5.CH5_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_5_CH5_TDUC       GTM_TIM_5.CH5_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_5_CH5_TDUV       GTM_TIM_5.CH5_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_5_CH5_FLT_RE     GTM_TIM_5.CH5_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_5_CH5_FLT_FE     GTM_TIM_5.CH5_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_5_CH5_CTRL       GTM_TIM_5.CH5_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_5_CH5_ECTRL      GTM_TIM_5.CH5_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_5_CH5_IRQ_NOTIFY GTM_TIM_5.CH5_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_5_CH5_IRQ_EN     GTM_TIM_5.CH5_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_5_CH5_IRQ_FORCINT GTM_TIM_5.CH5_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_5_CH5_IRQ_MODE   GTM_TIM_5.CH5_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_5_CH5_EIRQ_EN    GTM_TIM_5.CH5_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_5_CH6_GPR0       GTM_TIM_5.CH6_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_5_CH6_GPR1       GTM_TIM_5.CH6_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_5_CH6_CNT        GTM_TIM_5.CH6_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_5_CH6_ECNT       GTM_TIM_5.CH6_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_5_CH6_CNTS       GTM_TIM_5.CH6_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_5_CH6_TDUC       GTM_TIM_5.CH6_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_5_CH6_TDUV       GTM_TIM_5.CH6_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_5_CH6_FLT_RE     GTM_TIM_5.CH6_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_5_CH6_FLT_FE     GTM_TIM_5.CH6_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_5_CH6_CTRL       GTM_TIM_5.CH6_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_5_CH6_ECTRL      GTM_TIM_5.CH6_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_5_CH6_IRQ_NOTIFY GTM_TIM_5.CH6_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_5_CH6_IRQ_EN     GTM_TIM_5.CH6_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_5_CH6_IRQ_FORCINT GTM_TIM_5.CH6_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_5_CH6_IRQ_MODE   GTM_TIM_5.CH6_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_5_CH6_EIRQ_EN    GTM_TIM_5.CH6_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_5_CH7_GPR0       GTM_TIM_5.CH7_GPR0.R              /* TIM Channel n General Purpose Register 0, n=0:7 */
#define GTM_TIM_5_CH7_GPR1       GTM_TIM_5.CH7_GPR1.R              /* TIM Channel n General Purpose Register 1, n=0:7 */
#define GTM_TIM_5_CH7_CNT        GTM_TIM_5.CH7_CNT.R               /* TIM Channel n Count Register, n=0:7 */
#define GTM_TIM_5_CH7_ECNT       GTM_TIM_5.CH7_ECNT.R              /* TIM Channel n Edge Counter Register, n=0:7 */
#define GTM_TIM_5_CH7_CNTS       GTM_TIM_5.CH7_CNTS.R              /* TIM Channel n Counter Shadow Register, n=0:7 */
#define GTM_TIM_5_CH7_TDUC       GTM_TIM_5.CH7_TDUC.R              /* TIM Channel n TDUC Register, n=0:7 */
#define GTM_TIM_5_CH7_TDUV       GTM_TIM_5.CH7_TDUV.R              /* TIM Channel n TDUV Register, n=0:7 */
#define GTM_TIM_5_CH7_FLT_RE     GTM_TIM_5.CH7_FLT_RE.R            /* TIM Channel n Filter Parameter 0 Register, n=0:7 */
#define GTM_TIM_5_CH7_FLT_FE     GTM_TIM_5.CH7_FLT_FE.R            /* TIM Channel n Filter Parameter 1 Register, n=0:7 */
#define GTM_TIM_5_CH7_CTRL       GTM_TIM_5.CH7_CTRL.R              /* TIM Channel n Control Register, n=0:7 */
#define GTM_TIM_5_CH7_ECTRL      GTM_TIM_5.CH7_ECTRL.R             /* TIM Channel n External Control Register, n=0:7 */
#define GTM_TIM_5_CH7_IRQ_NOTIFY GTM_TIM_5.CH7_IRQ_NOTIFY.R        /* TIM Channel n Interrupt Request Notification Register, n=0:7 */
#define GTM_TIM_5_CH7_IRQ_EN     GTM_TIM_5.CH7_IRQ_EN.R            /* TIM Channel n Interrupt Request Enable Register, n=0:7 */
#define GTM_TIM_5_CH7_IRQ_FORCINT GTM_TIM_5.CH7_IRQ_FORCINT.R      /* TIM Channel n Force Interrupt Request Register, n=0:7 */
#define GTM_TIM_5_CH7_IRQ_MODE   GTM_TIM_5.CH7_IRQ_MODE.R          /* TIM Channel n Interrupt Request Mode Register, n=0:7 */
#define GTM_TIM_5_CH7_EIRQ_EN    GTM_TIM_5.CH7_EIRQ_EN.R           /* TIM Channel Error Interrupt Request Enable Register, n=0:7 */

/* GTM_TOM */
#define GTM_TOM_0_CH0_CTRL       GTM_TOM_0.CH0_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_0_CH0_SR0        GTM_TOM_0.CH0_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_0_CH0_SR1        GTM_TOM_0.CH0_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_0_CH0_CM0        GTM_TOM_0.CH0_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_0_CH0_CM1        GTM_TOM_0.CH0_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_0_CH0_CN0        GTM_TOM_0.CH0_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_0_CH0_STAT       GTM_TOM_0.CH0_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_0_CH0_IRQ_NOTIFY GTM_TOM_0.CH0_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_0_CH0_IRQ_EN     GTM_TOM_0.CH0_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_0_CH0_IRQ_FORCINT GTM_TOM_0.CH0_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_0_CH0_IRQ_MODE   GTM_TOM_0.CH0_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_0_TGC0_GLB_CTRL  GTM_TOM_0.TGC0_GLB_CTRL.R         /* TOM TGC0 Global Control Register */
#define GTM_TOM_0_TGC0_ACT_TB    GTM_TOM_0.TGC0_ACT_TB.R           /* TOM TGC0 Action Time Base Register */
#define GTM_TOM_0_TGC0_FUPD_CTRL GTM_TOM_0.TGC0_FUPD_CTRL.R        /* TOM TGC0 Force Update Control Register */
#define GTM_TOM_0_TGC0_INT_TRIG  GTM_TOM_0.TGC0_INT_TRIG.R         /* TOM TGC0 Interrupt Trigger Register */
#define GTM_TOM_0_CH1_CTRL       GTM_TOM_0.CH1_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_0_CH1_SR0        GTM_TOM_0.CH1_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_0_CH1_SR1        GTM_TOM_0.CH1_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_0_CH1_CM0        GTM_TOM_0.CH1_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_0_CH1_CM1        GTM_TOM_0.CH1_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_0_CH1_CN0        GTM_TOM_0.CH1_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_0_CH1_STAT       GTM_TOM_0.CH1_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_0_CH1_IRQ_NOTIFY GTM_TOM_0.CH1_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_0_CH1_IRQ_EN     GTM_TOM_0.CH1_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_0_CH1_IRQ_FORCINT GTM_TOM_0.CH1_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_0_CH1_IRQ_MODE   GTM_TOM_0.CH1_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_0_TGC0_ENDIS_CTRL GTM_TOM_0.TGC0_ENDIS_CTRL.R      /* TOM TGC0 Enable/Disable Control Register */
#define GTM_TOM_0_TGC0_ENDIS_STAT GTM_TOM_0.TGC0_ENDIS_STAT.R      /* TOM TGC0 Enable/Disable Status Register */
#define GTM_TOM_0_TGC0_OUTEN_CTRL GTM_TOM_0.TGC0_OUTEN_CTRL.R      /* TOM TGC0 Out Enable Control Register */
#define GTM_TOM_0_TGC0_OUTEN_STAT GTM_TOM_0.TGC0_OUTEN_STAT.R      /* TOM TGC0 Out Enable Control/Status Register */
#define GTM_TOM_0_CH2_CTRL       GTM_TOM_0.CH2_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_0_CH2_SR0        GTM_TOM_0.CH2_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_0_CH2_SR1        GTM_TOM_0.CH2_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_0_CH2_CM0        GTM_TOM_0.CH2_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_0_CH2_CM1        GTM_TOM_0.CH2_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_0_CH2_CN0        GTM_TOM_0.CH2_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_0_CH2_STAT       GTM_TOM_0.CH2_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_0_CH2_IRQ_NOTIFY GTM_TOM_0.CH2_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_0_CH2_IRQ_EN     GTM_TOM_0.CH2_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_0_CH2_IRQ_FORCINT GTM_TOM_0.CH2_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_0_CH2_IRQ_MODE   GTM_TOM_0.CH2_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_0_CH3_CTRL       GTM_TOM_0.CH3_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_0_CH3_SR0        GTM_TOM_0.CH3_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_0_CH3_SR1        GTM_TOM_0.CH3_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_0_CH3_CM0        GTM_TOM_0.CH3_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_0_CH3_CM1        GTM_TOM_0.CH3_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_0_CH3_CN0        GTM_TOM_0.CH3_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_0_CH3_STAT       GTM_TOM_0.CH3_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_0_CH3_IRQ_NOTIFY GTM_TOM_0.CH3_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_0_CH3_IRQ_EN     GTM_TOM_0.CH3_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_0_CH3_IRQ_FORCINT GTM_TOM_0.CH3_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_0_CH3_IRQ_MODE   GTM_TOM_0.CH3_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_0_CH4_CTRL       GTM_TOM_0.CH4_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_0_CH4_SR0        GTM_TOM_0.CH4_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_0_CH4_SR1        GTM_TOM_0.CH4_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_0_CH4_CM0        GTM_TOM_0.CH4_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_0_CH4_CM1        GTM_TOM_0.CH4_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_0_CH4_CN0        GTM_TOM_0.CH4_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_0_CH4_STAT       GTM_TOM_0.CH4_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_0_CH4_IRQ_NOTIFY GTM_TOM_0.CH4_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_0_CH4_IRQ_EN     GTM_TOM_0.CH4_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_0_CH4_IRQ_FORCINT GTM_TOM_0.CH4_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_0_CH4_IRQ_MODE   GTM_TOM_0.CH4_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_0_CH5_CTRL       GTM_TOM_0.CH5_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_0_CH5_SR0        GTM_TOM_0.CH5_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_0_CH5_SR1        GTM_TOM_0.CH5_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_0_CH5_CM0        GTM_TOM_0.CH5_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_0_CH5_CM1        GTM_TOM_0.CH5_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_0_CH5_CN0        GTM_TOM_0.CH5_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_0_CH5_STAT       GTM_TOM_0.CH5_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_0_CH5_IRQ_NOTIFY GTM_TOM_0.CH5_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_0_CH5_IRQ_EN     GTM_TOM_0.CH5_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_0_CH5_IRQ_FORCINT GTM_TOM_0.CH5_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_0_CH5_IRQ_MODE   GTM_TOM_0.CH5_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_0_CH6_CTRL       GTM_TOM_0.CH6_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_0_CH6_SR0        GTM_TOM_0.CH6_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_0_CH6_SR1        GTM_TOM_0.CH6_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_0_CH6_CM0        GTM_TOM_0.CH6_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_0_CH6_CM1        GTM_TOM_0.CH6_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_0_CH6_CN0        GTM_TOM_0.CH6_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_0_CH6_STAT       GTM_TOM_0.CH6_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_0_CH6_IRQ_NOTIFY GTM_TOM_0.CH6_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_0_CH6_IRQ_EN     GTM_TOM_0.CH6_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_0_CH6_IRQ_FORCINT GTM_TOM_0.CH6_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_0_CH6_IRQ_MODE   GTM_TOM_0.CH6_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_0_CH7_CTRL       GTM_TOM_0.CH7_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_0_CH7_SR0        GTM_TOM_0.CH7_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_0_CH7_SR1        GTM_TOM_0.CH7_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_0_CH7_CM0        GTM_TOM_0.CH7_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_0_CH7_CM1        GTM_TOM_0.CH7_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_0_CH7_CN0        GTM_TOM_0.CH7_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_0_CH7_STAT       GTM_TOM_0.CH7_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_0_CH7_IRQ_NOTIFY GTM_TOM_0.CH7_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_0_CH7_IRQ_EN     GTM_TOM_0.CH7_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_0_CH7_IRQ_FORCINT GTM_TOM_0.CH7_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_0_CH7_IRQ_MODE   GTM_TOM_0.CH7_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_0_CH8_CTRL       GTM_TOM_0.CH8_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_0_CH8_SR0        GTM_TOM_0.CH8_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_0_CH8_SR1        GTM_TOM_0.CH8_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_0_CH8_CM0        GTM_TOM_0.CH8_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_0_CH8_CM1        GTM_TOM_0.CH8_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_0_CH8_CN0        GTM_TOM_0.CH8_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_0_CH8_STAT       GTM_TOM_0.CH8_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_0_CH8_IRQ_NOTIFY GTM_TOM_0.CH8_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_0_CH8_IRQ_EN     GTM_TOM_0.CH8_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_0_CH8_IRQ_FORCINT GTM_TOM_0.CH8_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_0_CH8_IRQ_MODE   GTM_TOM_0.CH8_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_0_TGC1_GLB_CTRL  GTM_TOM_0.TGC1_GLB_CTRL.R         /* TOM TGC1 Global Control Register */
#define GTM_TOM_0_TGC1_ACT_TB    GTM_TOM_0.TGC1_ACT_TB.R           /* TOM TGC1 Action Time Base Register */
#define GTM_TOM_0_TGC1_FUPD_CTRL GTM_TOM_0.TGC1_FUPD_CTRL.R        /* TOM TGC1 Force Update Control Register */
#define GTM_TOM_0_TGC1_INT_TRIG  GTM_TOM_0.TGC1_INT_TRIG.R         /* TOM TGC1 Interrupt Trigger Register */
#define GTM_TOM_0_CH9_CTRL       GTM_TOM_0.CH9_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_0_CH9_SR0        GTM_TOM_0.CH9_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_0_CH9_SR1        GTM_TOM_0.CH9_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_0_CH9_CM0        GTM_TOM_0.CH9_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_0_CH9_CM1        GTM_TOM_0.CH9_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_0_CH9_CN0        GTM_TOM_0.CH9_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_0_CH9_STAT       GTM_TOM_0.CH9_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_0_CH9_IRQ_NOTIFY GTM_TOM_0.CH9_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_0_CH9_IRQ_EN     GTM_TOM_0.CH9_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_0_CH9_IRQ_FORCINT GTM_TOM_0.CH9_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_0_CH9_IRQ_MODE   GTM_TOM_0.CH9_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_0_TGC1_ENDIS_CTRL GTM_TOM_0.TGC1_ENDIS_CTRL.R      /* TOM TGC1 Enable/Disable Control Register */
#define GTM_TOM_0_TGC1_ENDIS_STAT GTM_TOM_0.TGC1_ENDIS_STAT.R      /* TOM TGC1 Enable/Disable Status Register */
#define GTM_TOM_0_TGC1_OUTEN_CTRL GTM_TOM_0.TGC1_OUTEN_CTRL.R      /* TOM TGC1 Out Enable Control Register */
#define GTM_TOM_0_TGC1_OUTEN_STAT GTM_TOM_0.TGC1_OUTEN_STAT.R      /* TOM TGC1 Out Enable Control/Status Register */
#define GTM_TOM_0_CH10_CTRL      GTM_TOM_0.CH10_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_0_CH10_SR0       GTM_TOM_0.CH10_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_0_CH10_SR1       GTM_TOM_0.CH10_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_0_CH10_CM0       GTM_TOM_0.CH10_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_0_CH10_CM1       GTM_TOM_0.CH10_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_0_CH10_CN0       GTM_TOM_0.CH10_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_0_CH10_STAT      GTM_TOM_0.CH10_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_0_CH10_IRQ_NOTIFY GTM_TOM_0.CH10_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_0_CH10_IRQ_EN    GTM_TOM_0.CH10_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_0_CH10_IRQ_FORCINT GTM_TOM_0.CH10_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_0_CH10_IRQ_MODE  GTM_TOM_0.CH10_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_0_CH11_CTRL      GTM_TOM_0.CH11_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_0_CH11_SR0       GTM_TOM_0.CH11_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_0_CH11_SR1       GTM_TOM_0.CH11_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_0_CH11_CM0       GTM_TOM_0.CH11_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_0_CH11_CM1       GTM_TOM_0.CH11_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_0_CH11_CN0       GTM_TOM_0.CH11_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_0_CH11_STAT      GTM_TOM_0.CH11_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_0_CH11_IRQ_NOTIFY GTM_TOM_0.CH11_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_0_CH11_IRQ_EN    GTM_TOM_0.CH11_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_0_CH11_IRQ_FORCINT GTM_TOM_0.CH11_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_0_CH11_IRQ_MODE  GTM_TOM_0.CH11_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_0_CH12_CTRL      GTM_TOM_0.CH12_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_0_CH12_SR0       GTM_TOM_0.CH12_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_0_CH12_SR1       GTM_TOM_0.CH12_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_0_CH12_CM0       GTM_TOM_0.CH12_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_0_CH12_CM1       GTM_TOM_0.CH12_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_0_CH12_CN0       GTM_TOM_0.CH12_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_0_CH12_STAT      GTM_TOM_0.CH12_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_0_CH12_IRQ_NOTIFY GTM_TOM_0.CH12_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_0_CH12_IRQ_EN    GTM_TOM_0.CH12_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_0_CH12_IRQ_FORCINT GTM_TOM_0.CH12_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_0_CH12_IRQ_MODE  GTM_TOM_0.CH12_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_0_CH13_CTRL      GTM_TOM_0.CH13_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_0_CH13_SR0       GTM_TOM_0.CH13_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_0_CH13_SR1       GTM_TOM_0.CH13_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_0_CH13_CM0       GTM_TOM_0.CH13_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_0_CH13_CM1       GTM_TOM_0.CH13_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_0_CH13_CN0       GTM_TOM_0.CH13_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_0_CH13_STAT      GTM_TOM_0.CH13_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_0_CH13_IRQ_NOTIFY GTM_TOM_0.CH13_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_0_CH13_IRQ_EN    GTM_TOM_0.CH13_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_0_CH13_IRQ_FORCINT GTM_TOM_0.CH13_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_0_CH13_IRQ_MODE  GTM_TOM_0.CH13_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_0_CH14_CTRL      GTM_TOM_0.CH14_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_0_CH14_SR0       GTM_TOM_0.CH14_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_0_CH14_SR1       GTM_TOM_0.CH14_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_0_CH14_CM0       GTM_TOM_0.CH14_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_0_CH14_CM1       GTM_TOM_0.CH14_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_0_CH14_CN0       GTM_TOM_0.CH14_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_0_CH14_STAT      GTM_TOM_0.CH14_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_0_CH14_IRQ_NOTIFY GTM_TOM_0.CH14_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_0_CH14_IRQ_EN    GTM_TOM_0.CH14_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_0_CH14_IRQ_FORCINT GTM_TOM_0.CH14_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_0_CH14_IRQ_MODE  GTM_TOM_0.CH14_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_0_CH15_CTRL      GTM_TOM_0.CH15_CTRL.R             /* TOM Channel 15 Control register */
#define GTM_TOM_0_CH15_SR0       GTM_TOM_0.CH15_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_0_CH15_SR1       GTM_TOM_0.CH15_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_0_CH15_CM0       GTM_TOM_0.CH15_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_0_CH15_CM1       GTM_TOM_0.CH15_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_0_CH15_CN0       GTM_TOM_0.CH15_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_0_CH15_STAT      GTM_TOM_0.CH15_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_0_CH15_IRQ_NOTIFY GTM_TOM_0.CH15_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_0_CH15_IRQ_EN    GTM_TOM_0.CH15_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_0_CH15_IRQ_FORCINT GTM_TOM_0.CH15_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_0_CH15_IRQ_MODE  GTM_TOM_0.CH15_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */

/* GTM_TOM */
#define GTM_TOM_1_CH0_CTRL       GTM_TOM_1.CH0_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_1_CH0_SR0        GTM_TOM_1.CH0_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_1_CH0_SR1        GTM_TOM_1.CH0_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_1_CH0_CM0        GTM_TOM_1.CH0_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_1_CH0_CM1        GTM_TOM_1.CH0_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_1_CH0_CN0        GTM_TOM_1.CH0_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_1_CH0_STAT       GTM_TOM_1.CH0_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_1_CH0_IRQ_NOTIFY GTM_TOM_1.CH0_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_1_CH0_IRQ_EN     GTM_TOM_1.CH0_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_1_CH0_IRQ_FORCINT GTM_TOM_1.CH0_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_1_CH0_IRQ_MODE   GTM_TOM_1.CH0_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_1_TGC0_GLB_CTRL  GTM_TOM_1.TGC0_GLB_CTRL.R         /* TOM TGC0 Global Control Register */
#define GTM_TOM_1_TGC0_ACT_TB    GTM_TOM_1.TGC0_ACT_TB.R           /* TOM TGC0 Action Time Base Register */
#define GTM_TOM_1_TGC0_FUPD_CTRL GTM_TOM_1.TGC0_FUPD_CTRL.R        /* TOM TGC0 Force Update Control Register */
#define GTM_TOM_1_TGC0_INT_TRIG  GTM_TOM_1.TGC0_INT_TRIG.R         /* TOM TGC0 Interrupt Trigger Register */
#define GTM_TOM_1_CH1_CTRL       GTM_TOM_1.CH1_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_1_CH1_SR0        GTM_TOM_1.CH1_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_1_CH1_SR1        GTM_TOM_1.CH1_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_1_CH1_CM0        GTM_TOM_1.CH1_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_1_CH1_CM1        GTM_TOM_1.CH1_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_1_CH1_CN0        GTM_TOM_1.CH1_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_1_CH1_STAT       GTM_TOM_1.CH1_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_1_CH1_IRQ_NOTIFY GTM_TOM_1.CH1_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_1_CH1_IRQ_EN     GTM_TOM_1.CH1_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_1_CH1_IRQ_FORCINT GTM_TOM_1.CH1_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_1_CH1_IRQ_MODE   GTM_TOM_1.CH1_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_1_TGC0_ENDIS_CTRL GTM_TOM_1.TGC0_ENDIS_CTRL.R      /* TOM TGC0 Enable/Disable Control Register */
#define GTM_TOM_1_TGC0_ENDIS_STAT GTM_TOM_1.TGC0_ENDIS_STAT.R      /* TOM TGC0 Enable/Disable Status Register */
#define GTM_TOM_1_TGC0_OUTEN_CTRL GTM_TOM_1.TGC0_OUTEN_CTRL.R      /* TOM TGC0 Out Enable Control Register */
#define GTM_TOM_1_TGC0_OUTEN_STAT GTM_TOM_1.TGC0_OUTEN_STAT.R      /* TOM TGC0 Out Enable Control/Status Register */
#define GTM_TOM_1_CH2_CTRL       GTM_TOM_1.CH2_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_1_CH2_SR0        GTM_TOM_1.CH2_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_1_CH2_SR1        GTM_TOM_1.CH2_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_1_CH2_CM0        GTM_TOM_1.CH2_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_1_CH2_CM1        GTM_TOM_1.CH2_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_1_CH2_CN0        GTM_TOM_1.CH2_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_1_CH2_STAT       GTM_TOM_1.CH2_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_1_CH2_IRQ_NOTIFY GTM_TOM_1.CH2_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_1_CH2_IRQ_EN     GTM_TOM_1.CH2_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_1_CH2_IRQ_FORCINT GTM_TOM_1.CH2_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_1_CH2_IRQ_MODE   GTM_TOM_1.CH2_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_1_CH3_CTRL       GTM_TOM_1.CH3_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_1_CH3_SR0        GTM_TOM_1.CH3_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_1_CH3_SR1        GTM_TOM_1.CH3_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_1_CH3_CM0        GTM_TOM_1.CH3_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_1_CH3_CM1        GTM_TOM_1.CH3_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_1_CH3_CN0        GTM_TOM_1.CH3_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_1_CH3_STAT       GTM_TOM_1.CH3_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_1_CH3_IRQ_NOTIFY GTM_TOM_1.CH3_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_1_CH3_IRQ_EN     GTM_TOM_1.CH3_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_1_CH3_IRQ_FORCINT GTM_TOM_1.CH3_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_1_CH3_IRQ_MODE   GTM_TOM_1.CH3_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_1_CH4_CTRL       GTM_TOM_1.CH4_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_1_CH4_SR0        GTM_TOM_1.CH4_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_1_CH4_SR1        GTM_TOM_1.CH4_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_1_CH4_CM0        GTM_TOM_1.CH4_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_1_CH4_CM1        GTM_TOM_1.CH4_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_1_CH4_CN0        GTM_TOM_1.CH4_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_1_CH4_STAT       GTM_TOM_1.CH4_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_1_CH4_IRQ_NOTIFY GTM_TOM_1.CH4_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_1_CH4_IRQ_EN     GTM_TOM_1.CH4_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_1_CH4_IRQ_FORCINT GTM_TOM_1.CH4_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_1_CH4_IRQ_MODE   GTM_TOM_1.CH4_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_1_CH5_CTRL       GTM_TOM_1.CH5_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_1_CH5_SR0        GTM_TOM_1.CH5_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_1_CH5_SR1        GTM_TOM_1.CH5_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_1_CH5_CM0        GTM_TOM_1.CH5_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_1_CH5_CM1        GTM_TOM_1.CH5_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_1_CH5_CN0        GTM_TOM_1.CH5_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_1_CH5_STAT       GTM_TOM_1.CH5_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_1_CH5_IRQ_NOTIFY GTM_TOM_1.CH5_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_1_CH5_IRQ_EN     GTM_TOM_1.CH5_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_1_CH5_IRQ_FORCINT GTM_TOM_1.CH5_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_1_CH5_IRQ_MODE   GTM_TOM_1.CH5_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_1_CH6_CTRL       GTM_TOM_1.CH6_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_1_CH6_SR0        GTM_TOM_1.CH6_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_1_CH6_SR1        GTM_TOM_1.CH6_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_1_CH6_CM0        GTM_TOM_1.CH6_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_1_CH6_CM1        GTM_TOM_1.CH6_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_1_CH6_CN0        GTM_TOM_1.CH6_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_1_CH6_STAT       GTM_TOM_1.CH6_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_1_CH6_IRQ_NOTIFY GTM_TOM_1.CH6_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_1_CH6_IRQ_EN     GTM_TOM_1.CH6_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_1_CH6_IRQ_FORCINT GTM_TOM_1.CH6_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_1_CH6_IRQ_MODE   GTM_TOM_1.CH6_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_1_CH7_CTRL       GTM_TOM_1.CH7_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_1_CH7_SR0        GTM_TOM_1.CH7_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_1_CH7_SR1        GTM_TOM_1.CH7_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_1_CH7_CM0        GTM_TOM_1.CH7_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_1_CH7_CM1        GTM_TOM_1.CH7_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_1_CH7_CN0        GTM_TOM_1.CH7_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_1_CH7_STAT       GTM_TOM_1.CH7_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_1_CH7_IRQ_NOTIFY GTM_TOM_1.CH7_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_1_CH7_IRQ_EN     GTM_TOM_1.CH7_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_1_CH7_IRQ_FORCINT GTM_TOM_1.CH7_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_1_CH7_IRQ_MODE   GTM_TOM_1.CH7_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_1_CH8_CTRL       GTM_TOM_1.CH8_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_1_CH8_SR0        GTM_TOM_1.CH8_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_1_CH8_SR1        GTM_TOM_1.CH8_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_1_CH8_CM0        GTM_TOM_1.CH8_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_1_CH8_CM1        GTM_TOM_1.CH8_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_1_CH8_CN0        GTM_TOM_1.CH8_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_1_CH8_STAT       GTM_TOM_1.CH8_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_1_CH8_IRQ_NOTIFY GTM_TOM_1.CH8_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_1_CH8_IRQ_EN     GTM_TOM_1.CH8_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_1_CH8_IRQ_FORCINT GTM_TOM_1.CH8_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_1_CH8_IRQ_MODE   GTM_TOM_1.CH8_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_1_TGC1_GLB_CTRL  GTM_TOM_1.TGC1_GLB_CTRL.R         /* TOM TGC1 Global Control Register */
#define GTM_TOM_1_TGC1_ACT_TB    GTM_TOM_1.TGC1_ACT_TB.R           /* TOM TGC1 Action Time Base Register */
#define GTM_TOM_1_TGC1_FUPD_CTRL GTM_TOM_1.TGC1_FUPD_CTRL.R        /* TOM TGC1 Force Update Control Register */
#define GTM_TOM_1_TGC1_INT_TRIG  GTM_TOM_1.TGC1_INT_TRIG.R         /* TOM TGC1 Interrupt Trigger Register */
#define GTM_TOM_1_CH9_CTRL       GTM_TOM_1.CH9_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_1_CH9_SR0        GTM_TOM_1.CH9_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_1_CH9_SR1        GTM_TOM_1.CH9_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_1_CH9_CM0        GTM_TOM_1.CH9_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_1_CH9_CM1        GTM_TOM_1.CH9_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_1_CH9_CN0        GTM_TOM_1.CH9_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_1_CH9_STAT       GTM_TOM_1.CH9_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_1_CH9_IRQ_NOTIFY GTM_TOM_1.CH9_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_1_CH9_IRQ_EN     GTM_TOM_1.CH9_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_1_CH9_IRQ_FORCINT GTM_TOM_1.CH9_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_1_CH9_IRQ_MODE   GTM_TOM_1.CH9_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_1_TGC1_ENDIS_CTRL GTM_TOM_1.TGC1_ENDIS_CTRL.R      /* TOM TGC1 Enable/Disable Control Register */
#define GTM_TOM_1_TGC1_ENDIS_STAT GTM_TOM_1.TGC1_ENDIS_STAT.R      /* TOM TGC1 Enable/Disable Status Register */
#define GTM_TOM_1_TGC1_OUTEN_CTRL GTM_TOM_1.TGC1_OUTEN_CTRL.R      /* TOM TGC1 Out Enable Control Register */
#define GTM_TOM_1_TGC1_OUTEN_STAT GTM_TOM_1.TGC1_OUTEN_STAT.R      /* TOM TGC1 Out Enable Control/Status Register */
#define GTM_TOM_1_CH10_CTRL      GTM_TOM_1.CH10_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_1_CH10_SR0       GTM_TOM_1.CH10_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_1_CH10_SR1       GTM_TOM_1.CH10_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_1_CH10_CM0       GTM_TOM_1.CH10_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_1_CH10_CM1       GTM_TOM_1.CH10_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_1_CH10_CN0       GTM_TOM_1.CH10_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_1_CH10_STAT      GTM_TOM_1.CH10_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_1_CH10_IRQ_NOTIFY GTM_TOM_1.CH10_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_1_CH10_IRQ_EN    GTM_TOM_1.CH10_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_1_CH10_IRQ_FORCINT GTM_TOM_1.CH10_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_1_CH10_IRQ_MODE  GTM_TOM_1.CH10_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_1_CH11_CTRL      GTM_TOM_1.CH11_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_1_CH11_SR0       GTM_TOM_1.CH11_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_1_CH11_SR1       GTM_TOM_1.CH11_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_1_CH11_CM0       GTM_TOM_1.CH11_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_1_CH11_CM1       GTM_TOM_1.CH11_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_1_CH11_CN0       GTM_TOM_1.CH11_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_1_CH11_STAT      GTM_TOM_1.CH11_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_1_CH11_IRQ_NOTIFY GTM_TOM_1.CH11_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_1_CH11_IRQ_EN    GTM_TOM_1.CH11_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_1_CH11_IRQ_FORCINT GTM_TOM_1.CH11_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_1_CH11_IRQ_MODE  GTM_TOM_1.CH11_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_1_CH12_CTRL      GTM_TOM_1.CH12_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_1_CH12_SR0       GTM_TOM_1.CH12_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_1_CH12_SR1       GTM_TOM_1.CH12_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_1_CH12_CM0       GTM_TOM_1.CH12_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_1_CH12_CM1       GTM_TOM_1.CH12_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_1_CH12_CN0       GTM_TOM_1.CH12_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_1_CH12_STAT      GTM_TOM_1.CH12_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_1_CH12_IRQ_NOTIFY GTM_TOM_1.CH12_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_1_CH12_IRQ_EN    GTM_TOM_1.CH12_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_1_CH12_IRQ_FORCINT GTM_TOM_1.CH12_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_1_CH12_IRQ_MODE  GTM_TOM_1.CH12_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_1_CH13_CTRL      GTM_TOM_1.CH13_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_1_CH13_SR0       GTM_TOM_1.CH13_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_1_CH13_SR1       GTM_TOM_1.CH13_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_1_CH13_CM0       GTM_TOM_1.CH13_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_1_CH13_CM1       GTM_TOM_1.CH13_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_1_CH13_CN0       GTM_TOM_1.CH13_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_1_CH13_STAT      GTM_TOM_1.CH13_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_1_CH13_IRQ_NOTIFY GTM_TOM_1.CH13_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_1_CH13_IRQ_EN    GTM_TOM_1.CH13_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_1_CH13_IRQ_FORCINT GTM_TOM_1.CH13_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_1_CH13_IRQ_MODE  GTM_TOM_1.CH13_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_1_CH14_CTRL      GTM_TOM_1.CH14_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_1_CH14_SR0       GTM_TOM_1.CH14_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_1_CH14_SR1       GTM_TOM_1.CH14_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_1_CH14_CM0       GTM_TOM_1.CH14_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_1_CH14_CM1       GTM_TOM_1.CH14_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_1_CH14_CN0       GTM_TOM_1.CH14_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_1_CH14_STAT      GTM_TOM_1.CH14_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_1_CH14_IRQ_NOTIFY GTM_TOM_1.CH14_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_1_CH14_IRQ_EN    GTM_TOM_1.CH14_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_1_CH14_IRQ_FORCINT GTM_TOM_1.CH14_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_1_CH14_IRQ_MODE  GTM_TOM_1.CH14_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_1_CH15_CTRL      GTM_TOM_1.CH15_CTRL.R             /* TOM Channel 15 Control register */
#define GTM_TOM_1_CH15_SR0       GTM_TOM_1.CH15_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_1_CH15_SR1       GTM_TOM_1.CH15_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_1_CH15_CM0       GTM_TOM_1.CH15_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_1_CH15_CM1       GTM_TOM_1.CH15_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_1_CH15_CN0       GTM_TOM_1.CH15_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_1_CH15_STAT      GTM_TOM_1.CH15_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_1_CH15_IRQ_NOTIFY GTM_TOM_1.CH15_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_1_CH15_IRQ_EN    GTM_TOM_1.CH15_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_1_CH15_IRQ_FORCINT GTM_TOM_1.CH15_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_1_CH15_IRQ_MODE  GTM_TOM_1.CH15_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */

/* GTM_TOM */
#define GTM_TOM_2_CH0_CTRL       GTM_TOM_2.CH0_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_2_CH0_SR0        GTM_TOM_2.CH0_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_2_CH0_SR1        GTM_TOM_2.CH0_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_2_CH0_CM0        GTM_TOM_2.CH0_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_2_CH0_CM1        GTM_TOM_2.CH0_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_2_CH0_CN0        GTM_TOM_2.CH0_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_2_CH0_STAT       GTM_TOM_2.CH0_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_2_CH0_IRQ_NOTIFY GTM_TOM_2.CH0_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_2_CH0_IRQ_EN     GTM_TOM_2.CH0_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_2_CH0_IRQ_FORCINT GTM_TOM_2.CH0_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_2_CH0_IRQ_MODE   GTM_TOM_2.CH0_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_2_TGC0_GLB_CTRL  GTM_TOM_2.TGC0_GLB_CTRL.R         /* TOM TGC0 Global Control Register */
#define GTM_TOM_2_TGC0_ACT_TB    GTM_TOM_2.TGC0_ACT_TB.R           /* TOM TGC0 Action Time Base Register */
#define GTM_TOM_2_TGC0_FUPD_CTRL GTM_TOM_2.TGC0_FUPD_CTRL.R        /* TOM TGC0 Force Update Control Register */
#define GTM_TOM_2_TGC0_INT_TRIG  GTM_TOM_2.TGC0_INT_TRIG.R         /* TOM TGC0 Interrupt Trigger Register */
#define GTM_TOM_2_CH1_CTRL       GTM_TOM_2.CH1_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_2_CH1_SR0        GTM_TOM_2.CH1_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_2_CH1_SR1        GTM_TOM_2.CH1_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_2_CH1_CM0        GTM_TOM_2.CH1_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_2_CH1_CM1        GTM_TOM_2.CH1_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_2_CH1_CN0        GTM_TOM_2.CH1_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_2_CH1_STAT       GTM_TOM_2.CH1_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_2_CH1_IRQ_NOTIFY GTM_TOM_2.CH1_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_2_CH1_IRQ_EN     GTM_TOM_2.CH1_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_2_CH1_IRQ_FORCINT GTM_TOM_2.CH1_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_2_CH1_IRQ_MODE   GTM_TOM_2.CH1_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_2_TGC0_ENDIS_CTRL GTM_TOM_2.TGC0_ENDIS_CTRL.R      /* TOM TGC0 Enable/Disable Control Register */
#define GTM_TOM_2_TGC0_ENDIS_STAT GTM_TOM_2.TGC0_ENDIS_STAT.R      /* TOM TGC0 Enable/Disable Status Register */
#define GTM_TOM_2_TGC0_OUTEN_CTRL GTM_TOM_2.TGC0_OUTEN_CTRL.R      /* TOM TGC0 Out Enable Control Register */
#define GTM_TOM_2_TGC0_OUTEN_STAT GTM_TOM_2.TGC0_OUTEN_STAT.R      /* TOM TGC0 Out Enable Control/Status Register */
#define GTM_TOM_2_CH2_CTRL       GTM_TOM_2.CH2_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_2_CH2_SR0        GTM_TOM_2.CH2_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_2_CH2_SR1        GTM_TOM_2.CH2_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_2_CH2_CM0        GTM_TOM_2.CH2_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_2_CH2_CM1        GTM_TOM_2.CH2_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_2_CH2_CN0        GTM_TOM_2.CH2_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_2_CH2_STAT       GTM_TOM_2.CH2_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_2_CH2_IRQ_NOTIFY GTM_TOM_2.CH2_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_2_CH2_IRQ_EN     GTM_TOM_2.CH2_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_2_CH2_IRQ_FORCINT GTM_TOM_2.CH2_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_2_CH2_IRQ_MODE   GTM_TOM_2.CH2_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_2_CH3_CTRL       GTM_TOM_2.CH3_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_2_CH3_SR0        GTM_TOM_2.CH3_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_2_CH3_SR1        GTM_TOM_2.CH3_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_2_CH3_CM0        GTM_TOM_2.CH3_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_2_CH3_CM1        GTM_TOM_2.CH3_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_2_CH3_CN0        GTM_TOM_2.CH3_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_2_CH3_STAT       GTM_TOM_2.CH3_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_2_CH3_IRQ_NOTIFY GTM_TOM_2.CH3_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_2_CH3_IRQ_EN     GTM_TOM_2.CH3_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_2_CH3_IRQ_FORCINT GTM_TOM_2.CH3_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_2_CH3_IRQ_MODE   GTM_TOM_2.CH3_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_2_CH4_CTRL       GTM_TOM_2.CH4_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_2_CH4_SR0        GTM_TOM_2.CH4_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_2_CH4_SR1        GTM_TOM_2.CH4_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_2_CH4_CM0        GTM_TOM_2.CH4_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_2_CH4_CM1        GTM_TOM_2.CH4_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_2_CH4_CN0        GTM_TOM_2.CH4_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_2_CH4_STAT       GTM_TOM_2.CH4_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_2_CH4_IRQ_NOTIFY GTM_TOM_2.CH4_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_2_CH4_IRQ_EN     GTM_TOM_2.CH4_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_2_CH4_IRQ_FORCINT GTM_TOM_2.CH4_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_2_CH4_IRQ_MODE   GTM_TOM_2.CH4_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_2_CH5_CTRL       GTM_TOM_2.CH5_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_2_CH5_SR0        GTM_TOM_2.CH5_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_2_CH5_SR1        GTM_TOM_2.CH5_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_2_CH5_CM0        GTM_TOM_2.CH5_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_2_CH5_CM1        GTM_TOM_2.CH5_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_2_CH5_CN0        GTM_TOM_2.CH5_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_2_CH5_STAT       GTM_TOM_2.CH5_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_2_CH5_IRQ_NOTIFY GTM_TOM_2.CH5_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_2_CH5_IRQ_EN     GTM_TOM_2.CH5_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_2_CH5_IRQ_FORCINT GTM_TOM_2.CH5_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_2_CH5_IRQ_MODE   GTM_TOM_2.CH5_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_2_CH6_CTRL       GTM_TOM_2.CH6_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_2_CH6_SR0        GTM_TOM_2.CH6_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_2_CH6_SR1        GTM_TOM_2.CH6_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_2_CH6_CM0        GTM_TOM_2.CH6_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_2_CH6_CM1        GTM_TOM_2.CH6_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_2_CH6_CN0        GTM_TOM_2.CH6_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_2_CH6_STAT       GTM_TOM_2.CH6_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_2_CH6_IRQ_NOTIFY GTM_TOM_2.CH6_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_2_CH6_IRQ_EN     GTM_TOM_2.CH6_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_2_CH6_IRQ_FORCINT GTM_TOM_2.CH6_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_2_CH6_IRQ_MODE   GTM_TOM_2.CH6_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_2_CH7_CTRL       GTM_TOM_2.CH7_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_2_CH7_SR0        GTM_TOM_2.CH7_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_2_CH7_SR1        GTM_TOM_2.CH7_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_2_CH7_CM0        GTM_TOM_2.CH7_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_2_CH7_CM1        GTM_TOM_2.CH7_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_2_CH7_CN0        GTM_TOM_2.CH7_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_2_CH7_STAT       GTM_TOM_2.CH7_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_2_CH7_IRQ_NOTIFY GTM_TOM_2.CH7_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_2_CH7_IRQ_EN     GTM_TOM_2.CH7_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_2_CH7_IRQ_FORCINT GTM_TOM_2.CH7_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_2_CH7_IRQ_MODE   GTM_TOM_2.CH7_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_2_CH8_CTRL       GTM_TOM_2.CH8_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_2_CH8_SR0        GTM_TOM_2.CH8_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_2_CH8_SR1        GTM_TOM_2.CH8_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_2_CH8_CM0        GTM_TOM_2.CH8_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_2_CH8_CM1        GTM_TOM_2.CH8_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_2_CH8_CN0        GTM_TOM_2.CH8_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_2_CH8_STAT       GTM_TOM_2.CH8_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_2_CH8_IRQ_NOTIFY GTM_TOM_2.CH8_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_2_CH8_IRQ_EN     GTM_TOM_2.CH8_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_2_CH8_IRQ_FORCINT GTM_TOM_2.CH8_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_2_CH8_IRQ_MODE   GTM_TOM_2.CH8_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_2_TGC1_GLB_CTRL  GTM_TOM_2.TGC1_GLB_CTRL.R         /* TOM TGC1 Global Control Register */
#define GTM_TOM_2_TGC1_ACT_TB    GTM_TOM_2.TGC1_ACT_TB.R           /* TOM TGC1 Action Time Base Register */
#define GTM_TOM_2_TGC1_FUPD_CTRL GTM_TOM_2.TGC1_FUPD_CTRL.R        /* TOM TGC1 Force Update Control Register */
#define GTM_TOM_2_TGC1_INT_TRIG  GTM_TOM_2.TGC1_INT_TRIG.R         /* TOM TGC1 Interrupt Trigger Register */
#define GTM_TOM_2_CH9_CTRL       GTM_TOM_2.CH9_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_2_CH9_SR0        GTM_TOM_2.CH9_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_2_CH9_SR1        GTM_TOM_2.CH9_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_2_CH9_CM0        GTM_TOM_2.CH9_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_2_CH9_CM1        GTM_TOM_2.CH9_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_2_CH9_CN0        GTM_TOM_2.CH9_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_2_CH9_STAT       GTM_TOM_2.CH9_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_2_CH9_IRQ_NOTIFY GTM_TOM_2.CH9_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_2_CH9_IRQ_EN     GTM_TOM_2.CH9_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_2_CH9_IRQ_FORCINT GTM_TOM_2.CH9_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_2_CH9_IRQ_MODE   GTM_TOM_2.CH9_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_2_TGC1_ENDIS_CTRL GTM_TOM_2.TGC1_ENDIS_CTRL.R      /* TOM TGC1 Enable/Disable Control Register */
#define GTM_TOM_2_TGC1_ENDIS_STAT GTM_TOM_2.TGC1_ENDIS_STAT.R      /* TOM TGC1 Enable/Disable Status Register */
#define GTM_TOM_2_TGC1_OUTEN_CTRL GTM_TOM_2.TGC1_OUTEN_CTRL.R      /* TOM TGC1 Out Enable Control Register */
#define GTM_TOM_2_TGC1_OUTEN_STAT GTM_TOM_2.TGC1_OUTEN_STAT.R      /* TOM TGC1 Out Enable Control/Status Register */
#define GTM_TOM_2_CH10_CTRL      GTM_TOM_2.CH10_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_2_CH10_SR0       GTM_TOM_2.CH10_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_2_CH10_SR1       GTM_TOM_2.CH10_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_2_CH10_CM0       GTM_TOM_2.CH10_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_2_CH10_CM1       GTM_TOM_2.CH10_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_2_CH10_CN0       GTM_TOM_2.CH10_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_2_CH10_STAT      GTM_TOM_2.CH10_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_2_CH10_IRQ_NOTIFY GTM_TOM_2.CH10_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_2_CH10_IRQ_EN    GTM_TOM_2.CH10_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_2_CH10_IRQ_FORCINT GTM_TOM_2.CH10_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_2_CH10_IRQ_MODE  GTM_TOM_2.CH10_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_2_CH11_CTRL      GTM_TOM_2.CH11_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_2_CH11_SR0       GTM_TOM_2.CH11_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_2_CH11_SR1       GTM_TOM_2.CH11_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_2_CH11_CM0       GTM_TOM_2.CH11_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_2_CH11_CM1       GTM_TOM_2.CH11_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_2_CH11_CN0       GTM_TOM_2.CH11_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_2_CH11_STAT      GTM_TOM_2.CH11_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_2_CH11_IRQ_NOTIFY GTM_TOM_2.CH11_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_2_CH11_IRQ_EN    GTM_TOM_2.CH11_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_2_CH11_IRQ_FORCINT GTM_TOM_2.CH11_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_2_CH11_IRQ_MODE  GTM_TOM_2.CH11_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_2_CH12_CTRL      GTM_TOM_2.CH12_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_2_CH12_SR0       GTM_TOM_2.CH12_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_2_CH12_SR1       GTM_TOM_2.CH12_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_2_CH12_CM0       GTM_TOM_2.CH12_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_2_CH12_CM1       GTM_TOM_2.CH12_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_2_CH12_CN0       GTM_TOM_2.CH12_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_2_CH12_STAT      GTM_TOM_2.CH12_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_2_CH12_IRQ_NOTIFY GTM_TOM_2.CH12_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_2_CH12_IRQ_EN    GTM_TOM_2.CH12_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_2_CH12_IRQ_FORCINT GTM_TOM_2.CH12_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_2_CH12_IRQ_MODE  GTM_TOM_2.CH12_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_2_CH13_CTRL      GTM_TOM_2.CH13_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_2_CH13_SR0       GTM_TOM_2.CH13_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_2_CH13_SR1       GTM_TOM_2.CH13_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_2_CH13_CM0       GTM_TOM_2.CH13_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_2_CH13_CM1       GTM_TOM_2.CH13_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_2_CH13_CN0       GTM_TOM_2.CH13_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_2_CH13_STAT      GTM_TOM_2.CH13_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_2_CH13_IRQ_NOTIFY GTM_TOM_2.CH13_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_2_CH13_IRQ_EN    GTM_TOM_2.CH13_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_2_CH13_IRQ_FORCINT GTM_TOM_2.CH13_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_2_CH13_IRQ_MODE  GTM_TOM_2.CH13_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_2_CH14_CTRL      GTM_TOM_2.CH14_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_2_CH14_SR0       GTM_TOM_2.CH14_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_2_CH14_SR1       GTM_TOM_2.CH14_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_2_CH14_CM0       GTM_TOM_2.CH14_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_2_CH14_CM1       GTM_TOM_2.CH14_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_2_CH14_CN0       GTM_TOM_2.CH14_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_2_CH14_STAT      GTM_TOM_2.CH14_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_2_CH14_IRQ_NOTIFY GTM_TOM_2.CH14_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_2_CH14_IRQ_EN    GTM_TOM_2.CH14_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_2_CH14_IRQ_FORCINT GTM_TOM_2.CH14_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_2_CH14_IRQ_MODE  GTM_TOM_2.CH14_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_2_CH15_CTRL      GTM_TOM_2.CH15_CTRL.R             /* TOM Channel 15 Control register */
#define GTM_TOM_2_CH15_SR0       GTM_TOM_2.CH15_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_2_CH15_SR1       GTM_TOM_2.CH15_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_2_CH15_CM0       GTM_TOM_2.CH15_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_2_CH15_CM1       GTM_TOM_2.CH15_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_2_CH15_CN0       GTM_TOM_2.CH15_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_2_CH15_STAT      GTM_TOM_2.CH15_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_2_CH15_IRQ_NOTIFY GTM_TOM_2.CH15_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_2_CH15_IRQ_EN    GTM_TOM_2.CH15_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_2_CH15_IRQ_FORCINT GTM_TOM_2.CH15_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_2_CH15_IRQ_MODE  GTM_TOM_2.CH15_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */

/* GTM_TOM */
#define GTM_TOM_3_CH0_CTRL       GTM_TOM_3.CH0_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_3_CH0_SR0        GTM_TOM_3.CH0_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_3_CH0_SR1        GTM_TOM_3.CH0_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_3_CH0_CM0        GTM_TOM_3.CH0_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_3_CH0_CM1        GTM_TOM_3.CH0_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_3_CH0_CN0        GTM_TOM_3.CH0_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_3_CH0_STAT       GTM_TOM_3.CH0_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_3_CH0_IRQ_NOTIFY GTM_TOM_3.CH0_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_3_CH0_IRQ_EN     GTM_TOM_3.CH0_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_3_CH0_IRQ_FORCINT GTM_TOM_3.CH0_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_3_CH0_IRQ_MODE   GTM_TOM_3.CH0_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_3_TGC0_GLB_CTRL  GTM_TOM_3.TGC0_GLB_CTRL.R         /* TOM TGC0 Global Control Register */
#define GTM_TOM_3_TGC0_ACT_TB    GTM_TOM_3.TGC0_ACT_TB.R           /* TOM TGC0 Action Time Base Register */
#define GTM_TOM_3_TGC0_FUPD_CTRL GTM_TOM_3.TGC0_FUPD_CTRL.R        /* TOM TGC0 Force Update Control Register */
#define GTM_TOM_3_TGC0_INT_TRIG  GTM_TOM_3.TGC0_INT_TRIG.R         /* TOM TGC0 Interrupt Trigger Register */
#define GTM_TOM_3_CH1_CTRL       GTM_TOM_3.CH1_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_3_CH1_SR0        GTM_TOM_3.CH1_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_3_CH1_SR1        GTM_TOM_3.CH1_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_3_CH1_CM0        GTM_TOM_3.CH1_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_3_CH1_CM1        GTM_TOM_3.CH1_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_3_CH1_CN0        GTM_TOM_3.CH1_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_3_CH1_STAT       GTM_TOM_3.CH1_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_3_CH1_IRQ_NOTIFY GTM_TOM_3.CH1_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_3_CH1_IRQ_EN     GTM_TOM_3.CH1_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_3_CH1_IRQ_FORCINT GTM_TOM_3.CH1_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_3_CH1_IRQ_MODE   GTM_TOM_3.CH1_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_3_TGC0_ENDIS_CTRL GTM_TOM_3.TGC0_ENDIS_CTRL.R      /* TOM TGC0 Enable/Disable Control Register */
#define GTM_TOM_3_TGC0_ENDIS_STAT GTM_TOM_3.TGC0_ENDIS_STAT.R      /* TOM TGC0 Enable/Disable Status Register */
#define GTM_TOM_3_TGC0_OUTEN_CTRL GTM_TOM_3.TGC0_OUTEN_CTRL.R      /* TOM TGC0 Out Enable Control Register */
#define GTM_TOM_3_TGC0_OUTEN_STAT GTM_TOM_3.TGC0_OUTEN_STAT.R      /* TOM TGC0 Out Enable Control/Status Register */
#define GTM_TOM_3_CH2_CTRL       GTM_TOM_3.CH2_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_3_CH2_SR0        GTM_TOM_3.CH2_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_3_CH2_SR1        GTM_TOM_3.CH2_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_3_CH2_CM0        GTM_TOM_3.CH2_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_3_CH2_CM1        GTM_TOM_3.CH2_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_3_CH2_CN0        GTM_TOM_3.CH2_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_3_CH2_STAT       GTM_TOM_3.CH2_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_3_CH2_IRQ_NOTIFY GTM_TOM_3.CH2_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_3_CH2_IRQ_EN     GTM_TOM_3.CH2_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_3_CH2_IRQ_FORCINT GTM_TOM_3.CH2_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_3_CH2_IRQ_MODE   GTM_TOM_3.CH2_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_3_CH3_CTRL       GTM_TOM_3.CH3_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_3_CH3_SR0        GTM_TOM_3.CH3_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_3_CH3_SR1        GTM_TOM_3.CH3_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_3_CH3_CM0        GTM_TOM_3.CH3_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_3_CH3_CM1        GTM_TOM_3.CH3_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_3_CH3_CN0        GTM_TOM_3.CH3_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_3_CH3_STAT       GTM_TOM_3.CH3_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_3_CH3_IRQ_NOTIFY GTM_TOM_3.CH3_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_3_CH3_IRQ_EN     GTM_TOM_3.CH3_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_3_CH3_IRQ_FORCINT GTM_TOM_3.CH3_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_3_CH3_IRQ_MODE   GTM_TOM_3.CH3_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_3_CH4_CTRL       GTM_TOM_3.CH4_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_3_CH4_SR0        GTM_TOM_3.CH4_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_3_CH4_SR1        GTM_TOM_3.CH4_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_3_CH4_CM0        GTM_TOM_3.CH4_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_3_CH4_CM1        GTM_TOM_3.CH4_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_3_CH4_CN0        GTM_TOM_3.CH4_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_3_CH4_STAT       GTM_TOM_3.CH4_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_3_CH4_IRQ_NOTIFY GTM_TOM_3.CH4_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_3_CH4_IRQ_EN     GTM_TOM_3.CH4_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_3_CH4_IRQ_FORCINT GTM_TOM_3.CH4_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_3_CH4_IRQ_MODE   GTM_TOM_3.CH4_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_3_CH5_CTRL       GTM_TOM_3.CH5_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_3_CH5_SR0        GTM_TOM_3.CH5_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_3_CH5_SR1        GTM_TOM_3.CH5_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_3_CH5_CM0        GTM_TOM_3.CH5_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_3_CH5_CM1        GTM_TOM_3.CH5_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_3_CH5_CN0        GTM_TOM_3.CH5_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_3_CH5_STAT       GTM_TOM_3.CH5_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_3_CH5_IRQ_NOTIFY GTM_TOM_3.CH5_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_3_CH5_IRQ_EN     GTM_TOM_3.CH5_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_3_CH5_IRQ_FORCINT GTM_TOM_3.CH5_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_3_CH5_IRQ_MODE   GTM_TOM_3.CH5_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_3_CH6_CTRL       GTM_TOM_3.CH6_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_3_CH6_SR0        GTM_TOM_3.CH6_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_3_CH6_SR1        GTM_TOM_3.CH6_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_3_CH6_CM0        GTM_TOM_3.CH6_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_3_CH6_CM1        GTM_TOM_3.CH6_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_3_CH6_CN0        GTM_TOM_3.CH6_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_3_CH6_STAT       GTM_TOM_3.CH6_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_3_CH6_IRQ_NOTIFY GTM_TOM_3.CH6_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_3_CH6_IRQ_EN     GTM_TOM_3.CH6_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_3_CH6_IRQ_FORCINT GTM_TOM_3.CH6_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_3_CH6_IRQ_MODE   GTM_TOM_3.CH6_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_3_CH7_CTRL       GTM_TOM_3.CH7_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_3_CH7_SR0        GTM_TOM_3.CH7_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_3_CH7_SR1        GTM_TOM_3.CH7_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_3_CH7_CM0        GTM_TOM_3.CH7_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_3_CH7_CM1        GTM_TOM_3.CH7_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_3_CH7_CN0        GTM_TOM_3.CH7_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_3_CH7_STAT       GTM_TOM_3.CH7_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_3_CH7_IRQ_NOTIFY GTM_TOM_3.CH7_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_3_CH7_IRQ_EN     GTM_TOM_3.CH7_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_3_CH7_IRQ_FORCINT GTM_TOM_3.CH7_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_3_CH7_IRQ_MODE   GTM_TOM_3.CH7_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_3_CH8_CTRL       GTM_TOM_3.CH8_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_3_CH8_SR0        GTM_TOM_3.CH8_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_3_CH8_SR1        GTM_TOM_3.CH8_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_3_CH8_CM0        GTM_TOM_3.CH8_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_3_CH8_CM1        GTM_TOM_3.CH8_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_3_CH8_CN0        GTM_TOM_3.CH8_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_3_CH8_STAT       GTM_TOM_3.CH8_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_3_CH8_IRQ_NOTIFY GTM_TOM_3.CH8_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_3_CH8_IRQ_EN     GTM_TOM_3.CH8_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_3_CH8_IRQ_FORCINT GTM_TOM_3.CH8_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_3_CH8_IRQ_MODE   GTM_TOM_3.CH8_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_3_TGC1_GLB_CTRL  GTM_TOM_3.TGC1_GLB_CTRL.R         /* TOM TGC1 Global Control Register */
#define GTM_TOM_3_TGC1_ACT_TB    GTM_TOM_3.TGC1_ACT_TB.R           /* TOM TGC1 Action Time Base Register */
#define GTM_TOM_3_TGC1_FUPD_CTRL GTM_TOM_3.TGC1_FUPD_CTRL.R        /* TOM TGC1 Force Update Control Register */
#define GTM_TOM_3_TGC1_INT_TRIG  GTM_TOM_3.TGC1_INT_TRIG.R         /* TOM TGC1 Interrupt Trigger Register */
#define GTM_TOM_3_CH9_CTRL       GTM_TOM_3.CH9_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_3_CH9_SR0        GTM_TOM_3.CH9_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_3_CH9_SR1        GTM_TOM_3.CH9_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_3_CH9_CM0        GTM_TOM_3.CH9_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_3_CH9_CM1        GTM_TOM_3.CH9_CM1.R               /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_3_CH9_CN0        GTM_TOM_3.CH9_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_3_CH9_STAT       GTM_TOM_3.CH9_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_3_CH9_IRQ_NOTIFY GTM_TOM_3.CH9_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_3_CH9_IRQ_EN     GTM_TOM_3.CH9_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_3_CH9_IRQ_FORCINT GTM_TOM_3.CH9_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_3_CH9_IRQ_MODE   GTM_TOM_3.CH9_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_3_TGC1_ENDIS_CTRL GTM_TOM_3.TGC1_ENDIS_CTRL.R      /* TOM TGC1 Enable/Disable Control Register */
#define GTM_TOM_3_TGC1_ENDIS_STAT GTM_TOM_3.TGC1_ENDIS_STAT.R      /* TOM TGC1 Enable/Disable Status Register */
#define GTM_TOM_3_TGC1_OUTEN_CTRL GTM_TOM_3.TGC1_OUTEN_CTRL.R      /* TOM TGC1 Out Enable Control Register */
#define GTM_TOM_3_TGC1_OUTEN_STAT GTM_TOM_3.TGC1_OUTEN_STAT.R      /* TOM TGC1 Out Enable Control/Status Register */
#define GTM_TOM_3_CH10_CTRL      GTM_TOM_3.CH10_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_3_CH10_SR0       GTM_TOM_3.CH10_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_3_CH10_SR1       GTM_TOM_3.CH10_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_3_CH10_CM0       GTM_TOM_3.CH10_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_3_CH10_CM1       GTM_TOM_3.CH10_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_3_CH10_CN0       GTM_TOM_3.CH10_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_3_CH10_STAT      GTM_TOM_3.CH10_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_3_CH10_IRQ_NOTIFY GTM_TOM_3.CH10_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_3_CH10_IRQ_EN    GTM_TOM_3.CH10_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_3_CH10_IRQ_FORCINT GTM_TOM_3.CH10_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_3_CH10_IRQ_MODE  GTM_TOM_3.CH10_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_3_CH11_CTRL      GTM_TOM_3.CH11_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_3_CH11_SR0       GTM_TOM_3.CH11_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_3_CH11_SR1       GTM_TOM_3.CH11_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_3_CH11_CM0       GTM_TOM_3.CH11_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_3_CH11_CM1       GTM_TOM_3.CH11_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_3_CH11_CN0       GTM_TOM_3.CH11_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_3_CH11_STAT      GTM_TOM_3.CH11_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_3_CH11_IRQ_NOTIFY GTM_TOM_3.CH11_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_3_CH11_IRQ_EN    GTM_TOM_3.CH11_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_3_CH11_IRQ_FORCINT GTM_TOM_3.CH11_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_3_CH11_IRQ_MODE  GTM_TOM_3.CH11_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_3_CH12_CTRL      GTM_TOM_3.CH12_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_3_CH12_SR0       GTM_TOM_3.CH12_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_3_CH12_SR1       GTM_TOM_3.CH12_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_3_CH12_CM0       GTM_TOM_3.CH12_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_3_CH12_CM1       GTM_TOM_3.CH12_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_3_CH12_CN0       GTM_TOM_3.CH12_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_3_CH12_STAT      GTM_TOM_3.CH12_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_3_CH12_IRQ_NOTIFY GTM_TOM_3.CH12_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_3_CH12_IRQ_EN    GTM_TOM_3.CH12_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_3_CH12_IRQ_FORCINT GTM_TOM_3.CH12_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_3_CH12_IRQ_MODE  GTM_TOM_3.CH12_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_3_CH13_CTRL      GTM_TOM_3.CH13_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_3_CH13_SR0       GTM_TOM_3.CH13_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_3_CH13_SR1       GTM_TOM_3.CH13_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_3_CH13_CM0       GTM_TOM_3.CH13_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_3_CH13_CM1       GTM_TOM_3.CH13_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_3_CH13_CN0       GTM_TOM_3.CH13_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_3_CH13_STAT      GTM_TOM_3.CH13_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_3_CH13_IRQ_NOTIFY GTM_TOM_3.CH13_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_3_CH13_IRQ_EN    GTM_TOM_3.CH13_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_3_CH13_IRQ_FORCINT GTM_TOM_3.CH13_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_3_CH13_IRQ_MODE  GTM_TOM_3.CH13_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_3_CH14_CTRL      GTM_TOM_3.CH14_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_3_CH14_SR0       GTM_TOM_3.CH14_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_3_CH14_SR1       GTM_TOM_3.CH14_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_3_CH14_CM0       GTM_TOM_3.CH14_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_3_CH14_CM1       GTM_TOM_3.CH14_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_3_CH14_CN0       GTM_TOM_3.CH14_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_3_CH14_STAT      GTM_TOM_3.CH14_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_3_CH14_IRQ_NOTIFY GTM_TOM_3.CH14_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_3_CH14_IRQ_EN    GTM_TOM_3.CH14_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_3_CH14_IRQ_FORCINT GTM_TOM_3.CH14_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_3_CH14_IRQ_MODE  GTM_TOM_3.CH14_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_3_CH15_CTRL      GTM_TOM_3.CH15_CTRL.R             /* TOM Channel 15 Control register */
#define GTM_TOM_3_CH15_SR0       GTM_TOM_3.CH15_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_3_CH15_SR1       GTM_TOM_3.CH15_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_3_CH15_CM0       GTM_TOM_3.CH15_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_3_CH15_CM1       GTM_TOM_3.CH15_CM1.R              /* TOM Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_3_CH15_CN0       GTM_TOM_3.CH15_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_3_CH15_STAT      GTM_TOM_3.CH15_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_3_CH15_IRQ_NOTIFY GTM_TOM_3.CH15_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_3_CH15_IRQ_EN    GTM_TOM_3.CH15_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_3_CH15_IRQ_FORCINT GTM_TOM_3.CH15_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_3_CH15_IRQ_MODE  GTM_TOM_3.CH15_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */

/* GTM_TOM */
#define GTM_TOM_4_CH0_CTRL       GTM_TOM_4.CH0_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_4_CH0_SR0        GTM_TOM_4.CH0_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_4_CH0_SR1        GTM_TOM_4.CH0_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_4_CH0_CM0        GTM_TOM_4.CH0_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_4_CH0_CM1        GTM_TOM_4.CH0_CM1.R               /* TOM04 Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_4_CH0_CN0        GTM_TOM_4.CH0_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_4_CH0_STAT       GTM_TOM_4.CH0_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_4_CH0_IRQ_NOTIFY GTM_TOM_4.CH0_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_4_CH0_IRQ_EN     GTM_TOM_4.CH0_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_4_CH0_IRQ_FORCINT GTM_TOM_4.CH0_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_4_CH0_IRQ_MODE   GTM_TOM_4.CH0_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_4_TGC0_GLB_CTRL  GTM_TOM_4.TGC0_GLB_CTRL.R         /* TOM TGC0 Global Control Register */
#define GTM_TOM_4_TGC0_ACT_TB    GTM_TOM_4.TGC0_ACT_TB.R           /* TOM TGC0 Action Time Base Register */
#define GTM_TOM_4_TGC0_FUPD_CTRL GTM_TOM_4.TGC0_FUPD_CTRL.R        /* TOM TGC0 Force Update Control Register */
#define GTM_TOM_4_TGC0_INT_TRIG  GTM_TOM_4.TGC0_INT_TRIG.R         /* TOM TGC0 Interrupt Trigger Register */
#define GTM_TOM_4_CH1_CTRL       GTM_TOM_4.CH1_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_4_CH1_SR0        GTM_TOM_4.CH1_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_4_CH1_SR1        GTM_TOM_4.CH1_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_4_CH1_CM0        GTM_TOM_4.CH1_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_4_CH1_CM1        GTM_TOM_4.CH1_CM1.R               /* TOM04 Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_4_CH1_CN0        GTM_TOM_4.CH1_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_4_CH1_STAT       GTM_TOM_4.CH1_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_4_CH1_IRQ_NOTIFY GTM_TOM_4.CH1_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_4_CH1_IRQ_EN     GTM_TOM_4.CH1_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_4_CH1_IRQ_FORCINT GTM_TOM_4.CH1_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_4_CH1_IRQ_MODE   GTM_TOM_4.CH1_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_4_TGC0_ENDIS_CTRL GTM_TOM_4.TGC0_ENDIS_CTRL.R      /* TOM TGC0 Enable/Disable Control Register */
#define GTM_TOM_4_TGC0_ENDIS_STAT GTM_TOM_4.TGC0_ENDIS_STAT.R      /* TOM TGC0 Enable/Disable Status Register */
#define GTM_TOM_4_TGC0_OUTEN_CTRL GTM_TOM_4.TGC0_OUTEN_CTRL.R      /* TOM TGC0 Out Enable Control Register */
#define GTM_TOM_4_TGC0_OUTEN_STAT GTM_TOM_4.TGC0_OUTEN_STAT.R      /* TOM TGC0 Out Enable Control/Status Register */
#define GTM_TOM_4_CH2_CTRL       GTM_TOM_4.CH2_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_4_CH2_SR0        GTM_TOM_4.CH2_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_4_CH2_SR1        GTM_TOM_4.CH2_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_4_CH2_CM0        GTM_TOM_4.CH2_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_4_CH2_CM1        GTM_TOM_4.CH2_CM1.R               /* TOM04 Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_4_CH2_CN0        GTM_TOM_4.CH2_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_4_CH2_STAT       GTM_TOM_4.CH2_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_4_CH2_IRQ_NOTIFY GTM_TOM_4.CH2_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_4_CH2_IRQ_EN     GTM_TOM_4.CH2_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_4_CH2_IRQ_FORCINT GTM_TOM_4.CH2_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_4_CH2_IRQ_MODE   GTM_TOM_4.CH2_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_4_CH3_CTRL       GTM_TOM_4.CH3_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_4_CH3_SR0        GTM_TOM_4.CH3_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_4_CH3_SR1        GTM_TOM_4.CH3_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_4_CH3_CM0        GTM_TOM_4.CH3_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_4_CH3_CM1        GTM_TOM_4.CH3_CM1.R               /* TOM04 Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_4_CH3_CN0        GTM_TOM_4.CH3_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_4_CH3_STAT       GTM_TOM_4.CH3_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_4_CH3_IRQ_NOTIFY GTM_TOM_4.CH3_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_4_CH3_IRQ_EN     GTM_TOM_4.CH3_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_4_CH3_IRQ_FORCINT GTM_TOM_4.CH3_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_4_CH3_IRQ_MODE   GTM_TOM_4.CH3_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_4_CH4_CTRL       GTM_TOM_4.CH4_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_4_CH4_SR0        GTM_TOM_4.CH4_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_4_CH4_SR1        GTM_TOM_4.CH4_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_4_CH4_CM0        GTM_TOM_4.CH4_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_4_CH4_CM1        GTM_TOM_4.CH4_CM1.R               /* TOM04 Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_4_CH4_CN0        GTM_TOM_4.CH4_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_4_CH4_STAT       GTM_TOM_4.CH4_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_4_CH4_IRQ_NOTIFY GTM_TOM_4.CH4_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_4_CH4_IRQ_EN     GTM_TOM_4.CH4_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_4_CH4_IRQ_FORCINT GTM_TOM_4.CH4_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_4_CH4_IRQ_MODE   GTM_TOM_4.CH4_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_4_CH5_CTRL       GTM_TOM_4.CH5_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_4_CH5_SR0        GTM_TOM_4.CH5_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_4_CH5_SR1        GTM_TOM_4.CH5_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_4_CH5_CM0        GTM_TOM_4.CH5_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_4_CH5_CM1        GTM_TOM_4.CH5_CM1.R               /* TOM04 Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_4_CH5_CN0        GTM_TOM_4.CH5_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_4_CH5_STAT       GTM_TOM_4.CH5_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_4_CH5_IRQ_NOTIFY GTM_TOM_4.CH5_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_4_CH5_IRQ_EN     GTM_TOM_4.CH5_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_4_CH5_IRQ_FORCINT GTM_TOM_4.CH5_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_4_CH5_IRQ_MODE   GTM_TOM_4.CH5_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_4_CH6_CTRL       GTM_TOM_4.CH6_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_4_CH6_SR0        GTM_TOM_4.CH6_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_4_CH6_SR1        GTM_TOM_4.CH6_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_4_CH6_CM0        GTM_TOM_4.CH6_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_4_CH6_CM1        GTM_TOM_4.CH6_CM1.R               /* TOM04 Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_4_CH6_CN0        GTM_TOM_4.CH6_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_4_CH6_STAT       GTM_TOM_4.CH6_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_4_CH6_IRQ_NOTIFY GTM_TOM_4.CH6_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_4_CH6_IRQ_EN     GTM_TOM_4.CH6_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_4_CH6_IRQ_FORCINT GTM_TOM_4.CH6_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_4_CH6_IRQ_MODE   GTM_TOM_4.CH6_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_4_CH7_CTRL       GTM_TOM_4.CH7_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_4_CH7_SR0        GTM_TOM_4.CH7_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_4_CH7_SR1        GTM_TOM_4.CH7_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_4_CH7_CM0        GTM_TOM_4.CH7_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_4_CH7_CM1        GTM_TOM_4.CH7_CM1.R               /* TOM04 Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_4_CH7_CN0        GTM_TOM_4.CH7_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_4_CH7_STAT       GTM_TOM_4.CH7_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_4_CH7_IRQ_NOTIFY GTM_TOM_4.CH7_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_4_CH7_IRQ_EN     GTM_TOM_4.CH7_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_4_CH7_IRQ_FORCINT GTM_TOM_4.CH7_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_4_CH7_IRQ_MODE   GTM_TOM_4.CH7_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_4_CH8_CTRL       GTM_TOM_4.CH8_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_4_CH8_SR0        GTM_TOM_4.CH8_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_4_CH8_SR1        GTM_TOM_4.CH8_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_4_CH8_CM0        GTM_TOM_4.CH8_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_4_CH8_CM1        GTM_TOM_4.CH8_CM1.R               /* TOM04 Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_4_CH8_CN0        GTM_TOM_4.CH8_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_4_CH8_STAT       GTM_TOM_4.CH8_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_4_CH8_IRQ_NOTIFY GTM_TOM_4.CH8_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_4_CH8_IRQ_EN     GTM_TOM_4.CH8_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_4_CH8_IRQ_FORCINT GTM_TOM_4.CH8_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_4_CH8_IRQ_MODE   GTM_TOM_4.CH8_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_4_TGC1_GLB_CTRL  GTM_TOM_4.TGC1_GLB_CTRL.R         /* TOM TGC1 Global Control Register */
#define GTM_TOM_4_TGC1_ACT_TB    GTM_TOM_4.TGC1_ACT_TB.R           /* TOM TGC1 Action Time Base Register */
#define GTM_TOM_4_TGC1_FUPD_CTRL GTM_TOM_4.TGC1_FUPD_CTRL.R        /* TOM TGC1 Force Update Control Register */
#define GTM_TOM_4_TGC1_INT_TRIG  GTM_TOM_4.TGC1_INT_TRIG.R         /* TOM TGC1 Interrupt Trigger Register */
#define GTM_TOM_4_CH9_CTRL       GTM_TOM_4.CH9_CTRL.R              /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_4_CH9_SR0        GTM_TOM_4.CH9_SR0.R               /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_4_CH9_SR1        GTM_TOM_4.CH9_SR1.R               /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_4_CH9_CM0        GTM_TOM_4.CH9_CM0.R               /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_4_CH9_CM1        GTM_TOM_4.CH9_CM1.R               /* TOM04 Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_4_CH9_CN0        GTM_TOM_4.CH9_CN0.R               /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_4_CH9_STAT       GTM_TOM_4.CH9_STAT.R              /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_4_CH9_IRQ_NOTIFY GTM_TOM_4.CH9_IRQ_NOTIFY.R        /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_4_CH9_IRQ_EN     GTM_TOM_4.CH9_IRQ_EN.R            /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_4_CH9_IRQ_FORCINT GTM_TOM_4.CH9_IRQ_FORCINT.R      /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_4_CH9_IRQ_MODE   GTM_TOM_4.CH9_IRQ_MODE.R          /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_4_TGC1_ENDIS_CTRL GTM_TOM_4.TGC1_ENDIS_CTRL.R      /* TOM TGC1 Enable/Disable Control Register */
#define GTM_TOM_4_TGC1_ENDIS_STAT GTM_TOM_4.TGC1_ENDIS_STAT.R      /* TOM TGC1 Enable/Disable Status Register */
#define GTM_TOM_4_TGC1_OUTEN_CTRL GTM_TOM_4.TGC1_OUTEN_CTRL.R      /* TOM TGC1 Out Enable Control Register */
#define GTM_TOM_4_TGC1_OUTEN_STAT GTM_TOM_4.TGC1_OUTEN_STAT.R      /* TOM TGC1 Out Enable Control/Status Register */
#define GTM_TOM_4_CH10_CTRL      GTM_TOM_4.CH10_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_4_CH10_SR0       GTM_TOM_4.CH10_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_4_CH10_SR1       GTM_TOM_4.CH10_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_4_CH10_CM0       GTM_TOM_4.CH10_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_4_CH10_CM1       GTM_TOM_4.CH10_CM1.R              /* TOM04 Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_4_CH10_CN0       GTM_TOM_4.CH10_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_4_CH10_STAT      GTM_TOM_4.CH10_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_4_CH10_IRQ_NOTIFY GTM_TOM_4.CH10_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_4_CH10_IRQ_EN    GTM_TOM_4.CH10_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_4_CH10_IRQ_FORCINT GTM_TOM_4.CH10_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_4_CH10_IRQ_MODE  GTM_TOM_4.CH10_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_4_CH11_CTRL      GTM_TOM_4.CH11_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_4_CH11_SR0       GTM_TOM_4.CH11_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_4_CH11_SR1       GTM_TOM_4.CH11_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_4_CH11_CM0       GTM_TOM_4.CH11_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_4_CH11_CM1       GTM_TOM_4.CH11_CM1.R              /* TOM04 Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_4_CH11_CN0       GTM_TOM_4.CH11_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_4_CH11_STAT      GTM_TOM_4.CH11_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_4_CH11_IRQ_NOTIFY GTM_TOM_4.CH11_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_4_CH11_IRQ_EN    GTM_TOM_4.CH11_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_4_CH11_IRQ_FORCINT GTM_TOM_4.CH11_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_4_CH11_IRQ_MODE  GTM_TOM_4.CH11_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_4_CH12_CTRL      GTM_TOM_4.CH12_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_4_CH12_SR0       GTM_TOM_4.CH12_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_4_CH12_SR1       GTM_TOM_4.CH12_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_4_CH12_CM0       GTM_TOM_4.CH12_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_4_CH12_CM1       GTM_TOM_4.CH12_CM1.R              /* TOM04 Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_4_CH12_CN0       GTM_TOM_4.CH12_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_4_CH12_STAT      GTM_TOM_4.CH12_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_4_CH12_IRQ_NOTIFY GTM_TOM_4.CH12_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_4_CH12_IRQ_EN    GTM_TOM_4.CH12_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_4_CH12_IRQ_FORCINT GTM_TOM_4.CH12_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_4_CH12_IRQ_MODE  GTM_TOM_4.CH12_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_4_CH13_CTRL      GTM_TOM_4.CH13_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_4_CH13_SR0       GTM_TOM_4.CH13_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_4_CH13_SR1       GTM_TOM_4.CH13_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_4_CH13_CM0       GTM_TOM_4.CH13_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_4_CH13_CM1       GTM_TOM_4.CH13_CM1.R              /* TOM04 Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_4_CH13_CN0       GTM_TOM_4.CH13_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_4_CH13_STAT      GTM_TOM_4.CH13_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_4_CH13_IRQ_NOTIFY GTM_TOM_4.CH13_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_4_CH13_IRQ_EN    GTM_TOM_4.CH13_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_4_CH13_IRQ_FORCINT GTM_TOM_4.CH13_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_4_CH13_IRQ_MODE  GTM_TOM_4.CH13_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_4_CH14_CTRL      GTM_TOM_4.CH14_CTRL.R             /* TOM Channel n Control Register, n[0:14] */
#define GTM_TOM_4_CH14_SR0       GTM_TOM_4.CH14_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_4_CH14_SR1       GTM_TOM_4.CH14_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_4_CH14_CM0       GTM_TOM_4.CH14_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_4_CH14_CM1       GTM_TOM_4.CH14_CM1.R              /* TOM04 Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_4_CH14_CN0       GTM_TOM_4.CH14_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_4_CH14_STAT      GTM_TOM_4.CH14_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_4_CH14_IRQ_NOTIFY GTM_TOM_4.CH14_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_4_CH14_IRQ_EN    GTM_TOM_4.CH14_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_4_CH14_IRQ_FORCINT GTM_TOM_4.CH14_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_4_CH14_IRQ_MODE  GTM_TOM_4.CH14_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */
#define GTM_TOM_4_CH15_CTRL      GTM_TOM_4.CH15_CTRL.R             /* TOM Channel 15 Control register */
#define GTM_TOM_4_CH15_SR0       GTM_TOM_4.CH15_SR0.R              /* TOM Channel n Shadow 0 Register, n[0:15] */
#define GTM_TOM_4_CH15_SR1       GTM_TOM_4.CH15_SR1.R              /* TOM Channel n Shadow 1 Register, n[0:15] */
#define GTM_TOM_4_CH15_CM0       GTM_TOM_4.CH15_CM0.R              /* TOM Channel n Compare 0 Register, n[0:15] */
#define GTM_TOM_4_CH15_CM1       GTM_TOM_4.CH15_CM1.R              /* TOM04 Channel n Compare 1 Register, n[0:15] */
#define GTM_TOM_4_CH15_CN0       GTM_TOM_4.CH15_CN0.R              /* TOM Channel n CN0 Register, n[0:15] */
#define GTM_TOM_4_CH15_STAT      GTM_TOM_4.CH15_STAT.R             /* TOM Channel n Status Register, n[0:15] */
#define GTM_TOM_4_CH15_IRQ_NOTIFY GTM_TOM_4.CH15_IRQ_NOTIFY.R      /* TOM Channel n Interrupt Request Notification Register, n[0:15] */
#define GTM_TOM_4_CH15_IRQ_EN    GTM_TOM_4.CH15_IRQ_EN.R           /* TOM Channel n Interrupt Request Enable Register, n[0:15] */
#define GTM_TOM_4_CH15_IRQ_FORCINT GTM_TOM_4.CH15_IRQ_FORCINT.R    /* TOM Channel n Force Interrupt Request Register, n[0:15] */
#define GTM_TOM_4_CH15_IRQ_MODE  GTM_TOM_4.CH15_IRQ_MODE.R         /* TOM Channel n Interrupt Request Mode Register, n[0:15] */

/* I2C */
#define I2C_0_IBAD           I2C_0.IBAD.R                  /* I2C Bus Address Register */
#define I2C_0_IBFD           I2C_0.IBFD.R                  /* I2C Bus Frequency Divider Register */
#define I2C_0_IBCR           I2C_0.IBCR.R                  /* I2C Bus Control Register */
#define I2C_0_IBSR           I2C_0.IBSR.R                  /* I2C Bus Status Register */
#define I2C_0_IBDR           I2C_0.IBDR.R                  /* I2C Bus Data I/O Register */
#define I2C_0_IBIC           I2C_0.IBIC.R                  /* I2C Bus Interrupt Config Register */
#define I2C_0_IBDBG          I2C_0.IBDBG.R                 /* I2C Bus Debug Register */

/* I2C */
#define I2C_1_IBAD           I2C_1.IBAD.R                  /* I2C Bus Address Register */
#define I2C_1_IBFD           I2C_1.IBFD.R                  /* I2C Bus Frequency Divider Register */
#define I2C_1_IBCR           I2C_1.IBCR.R                  /* I2C Bus Control Register */
#define I2C_1_IBSR           I2C_1.IBSR.R                  /* I2C Bus Status Register */
#define I2C_1_IBDR           I2C_1.IBDR.R                  /* I2C Bus Data I/O Register */
#define I2C_1_IBIC           I2C_1.IBIC.R                  /* I2C Bus Interrupt Config Register */
#define I2C_1_IBDBG          I2C_1.IBDBG.R                 /* I2C Bus Debug Register */

/* IMA */
#define IMA_CTRL             IMA.CTRL.R                    /* Control Register */
#define IMA_ENABLE           IMA.ENABLE.R                  /* Enable Access Register */
#define IMA_STATUS           IMA.STATUS.R                  /* Status Register */
#define IMA_SLCT             IMA.SLCT.R                    /* RAM Select Register */
#define IMA_WRITE_UNLOCK     IMA.WRITE_UNLOCK.R            /* Write Unlock Register */
#define IMA_READ_UNLOCK      IMA.READ_UNLOCK.R             /* Read Unlock Register */
#define IMA_WRITE_DATA_4     IMA.WRITE_DATA_4.R            /* RAM Write Data Register 4 */
#define IMA_WRITE_DATA_3     IMA.WRITE_DATA_3.R            /* RAM Write Data Register 3 */
#define IMA_WRITE_DATA_2     IMA.WRITE_DATA_2.R            /* RAM Write Data Register 2 */
#define IMA_WRITE_DATA_1     IMA.WRITE_DATA_1.R            /* RAM Write Data Register 1 */
#define IMA_WRITE_DATA_0     IMA.WRITE_DATA_0.R            /* RAM Write Data Register 0 */
#define IMA_READ_DATA_4      IMA.READ_DATA_4.R             /* RAM Read Data Register 4 */
#define IMA_READ_DATA_3      IMA.READ_DATA_3.R             /* RAM Read Data Register 3 */
#define IMA_READ_DATA_2      IMA.READ_DATA_2.R             /* RAM Read Data Register 2 */
#define IMA_READ_DATA_1      IMA.READ_DATA_1.R             /* RAM Read Data Register 1 */
#define IMA_READ_DATA_0      IMA.READ_DATA_0.R             /* RAM Read Data Register 0 */

/* INTC */
#define INTC_0_BCR           INTC_0.BCR.R                  /* INTC Block Configuration Register */
#define INTC_0_MPROT         INTC_0.MPROT.R                /* INTC Master Protection Register */
#define INTC_0_CPR0          INTC_0.CPR[0].R               /* INTC Current Priority Register for Processor n */
#define INTC_0_CPR1          INTC_0.CPR[1].R               /* INTC Current Priority Register for Processor n */
#define INTC_0_CPR2          INTC_0.CPR[2].R               /* INTC Current Priority Register for Processor n */
#define INTC_0_CPR3          INTC_0.CPR[3].R               /* INTC Current Priority Register for Processor n */
#define INTC_0_IACKR0        INTC_0.IACKR[0].R             /* INTC Interrupt Acknowledge Register for Processor n */
#define INTC_0_IACKR1        INTC_0.IACKR[1].R             /* INTC Interrupt Acknowledge Register for Processor n */
#define INTC_0_IACKR2        INTC_0.IACKR[2].R             /* INTC Interrupt Acknowledge Register for Processor n */
#define INTC_0_IACKR3        INTC_0.IACKR[3].R             /* INTC Interrupt Acknowledge Register for Processor n */
#define INTC_0_EOIR0         INTC_0.EOIR[0].R              /* INTC End Of Interrupt Register for Processor n */
#define INTC_0_EOIR1         INTC_0.EOIR[1].R              /* INTC End Of Interrupt Register for Processor n */
#define INTC_0_EOIR2         INTC_0.EOIR[2].R              /* INTC End Of Interrupt Register for Processor n */
#define INTC_0_EOIR3         INTC_0.EOIR[3].R              /* INTC End Of Interrupt Register for Processor n */
#define INTC_0_SSCIR0        INTC_0.SSCIR[0].R             /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR1        INTC_0.SSCIR[1].R             /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR2        INTC_0.SSCIR[2].R             /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR3        INTC_0.SSCIR[3].R             /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR4        INTC_0.SSCIR[4].R             /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR5        INTC_0.SSCIR[5].R             /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR6        INTC_0.SSCIR[6].R             /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR7        INTC_0.SSCIR[7].R             /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR8        INTC_0.SSCIR[8].R             /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR9        INTC_0.SSCIR[9].R             /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR10       INTC_0.SSCIR[10].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR11       INTC_0.SSCIR[11].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR12       INTC_0.SSCIR[12].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR13       INTC_0.SSCIR[13].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR14       INTC_0.SSCIR[14].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR15       INTC_0.SSCIR[15].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR16       INTC_0.SSCIR[16].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR17       INTC_0.SSCIR[17].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR18       INTC_0.SSCIR[18].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR19       INTC_0.SSCIR[19].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR20       INTC_0.SSCIR[20].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR21       INTC_0.SSCIR[21].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR22       INTC_0.SSCIR[22].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR23       INTC_0.SSCIR[23].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR24       INTC_0.SSCIR[24].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR25       INTC_0.SSCIR[25].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR26       INTC_0.SSCIR[26].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR27       INTC_0.SSCIR[27].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR28       INTC_0.SSCIR[28].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR29       INTC_0.SSCIR[29].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR30       INTC_0.SSCIR[30].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_SSCIR31       INTC_0.SSCIR[31].R            /* INTC Software Set/Clear Interrupt Register */
#define INTC_0_PSR0          INTC_0.PSR[0].R               /* INTC Priority Select Register */
#define INTC_0_PSR1          INTC_0.PSR[1].R               /* INTC Priority Select Register */
#define INTC_0_PSR2          INTC_0.PSR[2].R               /* INTC Priority Select Register */
#define INTC_0_PSR3          INTC_0.PSR[3].R               /* INTC Priority Select Register */
#define INTC_0_PSR4          INTC_0.PSR[4].R               /* INTC Priority Select Register */
#define INTC_0_PSR5          INTC_0.PSR[5].R               /* INTC Priority Select Register */
#define INTC_0_PSR6          INTC_0.PSR[6].R               /* INTC Priority Select Register */
#define INTC_0_PSR7          INTC_0.PSR[7].R               /* INTC Priority Select Register */
#define INTC_0_PSR8          INTC_0.PSR[8].R               /* INTC Priority Select Register */
#define INTC_0_PSR9          INTC_0.PSR[9].R               /* INTC Priority Select Register */
#define INTC_0_PSR10         INTC_0.PSR[10].R              /* INTC Priority Select Register */
#define INTC_0_PSR11         INTC_0.PSR[11].R              /* INTC Priority Select Register */
#define INTC_0_PSR12         INTC_0.PSR[12].R              /* INTC Priority Select Register */
#define INTC_0_PSR13         INTC_0.PSR[13].R              /* INTC Priority Select Register */
#define INTC_0_PSR14         INTC_0.PSR[14].R              /* INTC Priority Select Register */
#define INTC_0_PSR15         INTC_0.PSR[15].R              /* INTC Priority Select Register */
#define INTC_0_PSR16         INTC_0.PSR[16].R              /* INTC Priority Select Register */
#define INTC_0_PSR17         INTC_0.PSR[17].R              /* INTC Priority Select Register */
#define INTC_0_PSR18         INTC_0.PSR[18].R              /* INTC Priority Select Register */
#define INTC_0_PSR19         INTC_0.PSR[19].R              /* INTC Priority Select Register */
#define INTC_0_PSR20         INTC_0.PSR[20].R              /* INTC Priority Select Register */
#define INTC_0_PSR21         INTC_0.PSR[21].R              /* INTC Priority Select Register */
#define INTC_0_PSR22         INTC_0.PSR[22].R              /* INTC Priority Select Register */
#define INTC_0_PSR23         INTC_0.PSR[23].R              /* INTC Priority Select Register */
#define INTC_0_PSR24         INTC_0.PSR[24].R              /* INTC Priority Select Register */
#define INTC_0_PSR25         INTC_0.PSR[25].R              /* INTC Priority Select Register */
#define INTC_0_PSR26         INTC_0.PSR[26].R              /* INTC Priority Select Register */
#define INTC_0_PSR27         INTC_0.PSR[27].R              /* INTC Priority Select Register */
#define INTC_0_PSR28         INTC_0.PSR[28].R              /* INTC Priority Select Register */
#define INTC_0_PSR29         INTC_0.PSR[29].R              /* INTC Priority Select Register */
#define INTC_0_PSR30         INTC_0.PSR[30].R              /* INTC Priority Select Register */
#define INTC_0_PSR31         INTC_0.PSR[31].R              /* INTC Priority Select Register */
#define INTC_0_PSR32         INTC_0.PSR[32].R              /* INTC Priority Select Register */
#define INTC_0_PSR33         INTC_0.PSR[33].R              /* INTC Priority Select Register */
#define INTC_0_PSR34         INTC_0.PSR[34].R              /* INTC Priority Select Register */
#define INTC_0_PSR35         INTC_0.PSR[35].R              /* INTC Priority Select Register */
#define INTC_0_PSR36         INTC_0.PSR[36].R              /* INTC Priority Select Register */
#define INTC_0_PSR37         INTC_0.PSR[37].R              /* INTC Priority Select Register */
#define INTC_0_PSR38         INTC_0.PSR[38].R              /* INTC Priority Select Register */
#define INTC_0_PSR39         INTC_0.PSR[39].R              /* INTC Priority Select Register */
#define INTC_0_PSR40         INTC_0.PSR[40].R              /* INTC Priority Select Register */
#define INTC_0_PSR41         INTC_0.PSR[41].R              /* INTC Priority Select Register */
#define INTC_0_PSR42         INTC_0.PSR[42].R              /* INTC Priority Select Register */
#define INTC_0_PSR43         INTC_0.PSR[43].R              /* INTC Priority Select Register */
#define INTC_0_PSR44         INTC_0.PSR[44].R              /* INTC Priority Select Register */
#define INTC_0_PSR45         INTC_0.PSR[45].R              /* INTC Priority Select Register */
#define INTC_0_PSR46         INTC_0.PSR[46].R              /* INTC Priority Select Register */
#define INTC_0_PSR47         INTC_0.PSR[47].R              /* INTC Priority Select Register */
#define INTC_0_PSR48         INTC_0.PSR[48].R              /* INTC Priority Select Register */
#define INTC_0_PSR49         INTC_0.PSR[49].R              /* INTC Priority Select Register */
#define INTC_0_PSR50         INTC_0.PSR[50].R              /* INTC Priority Select Register */
#define INTC_0_PSR51         INTC_0.PSR[51].R              /* INTC Priority Select Register */
#define INTC_0_PSR52         INTC_0.PSR[52].R              /* INTC Priority Select Register */
#define INTC_0_PSR53         INTC_0.PSR[53].R              /* INTC Priority Select Register */
#define INTC_0_PSR54         INTC_0.PSR[54].R              /* INTC Priority Select Register */
#define INTC_0_PSR55         INTC_0.PSR[55].R              /* INTC Priority Select Register */
#define INTC_0_PSR56         INTC_0.PSR[56].R              /* INTC Priority Select Register */
#define INTC_0_PSR57         INTC_0.PSR[57].R              /* INTC Priority Select Register */
#define INTC_0_PSR58         INTC_0.PSR[58].R              /* INTC Priority Select Register */
#define INTC_0_PSR59         INTC_0.PSR[59].R              /* INTC Priority Select Register */
#define INTC_0_PSR60         INTC_0.PSR[60].R              /* INTC Priority Select Register */
#define INTC_0_PSR61         INTC_0.PSR[61].R              /* INTC Priority Select Register */
#define INTC_0_PSR62         INTC_0.PSR[62].R              /* INTC Priority Select Register */
#define INTC_0_PSR63         INTC_0.PSR[63].R              /* INTC Priority Select Register */
#define INTC_0_PSR64         INTC_0.PSR[64].R              /* INTC Priority Select Register */
#define INTC_0_PSR65         INTC_0.PSR[65].R              /* INTC Priority Select Register */
#define INTC_0_PSR66         INTC_0.PSR[66].R              /* INTC Priority Select Register */
#define INTC_0_PSR67         INTC_0.PSR[67].R              /* INTC Priority Select Register */
#define INTC_0_PSR68         INTC_0.PSR[68].R              /* INTC Priority Select Register */
#define INTC_0_PSR69         INTC_0.PSR[69].R              /* INTC Priority Select Register */
#define INTC_0_PSR70         INTC_0.PSR[70].R              /* INTC Priority Select Register */
#define INTC_0_PSR71         INTC_0.PSR[71].R              /* INTC Priority Select Register */
#define INTC_0_PSR72         INTC_0.PSR[72].R              /* INTC Priority Select Register */
#define INTC_0_PSR73         INTC_0.PSR[73].R              /* INTC Priority Select Register */
#define INTC_0_PSR74         INTC_0.PSR[74].R              /* INTC Priority Select Register */
#define INTC_0_PSR75         INTC_0.PSR[75].R              /* INTC Priority Select Register */
#define INTC_0_PSR76         INTC_0.PSR[76].R              /* INTC Priority Select Register */
#define INTC_0_PSR77         INTC_0.PSR[77].R              /* INTC Priority Select Register */
#define INTC_0_PSR78         INTC_0.PSR[78].R              /* INTC Priority Select Register */
#define INTC_0_PSR79         INTC_0.PSR[79].R              /* INTC Priority Select Register */
#define INTC_0_PSR80         INTC_0.PSR[80].R              /* INTC Priority Select Register */
#define INTC_0_PSR81         INTC_0.PSR[81].R              /* INTC Priority Select Register */
#define INTC_0_PSR82         INTC_0.PSR[82].R              /* INTC Priority Select Register */
#define INTC_0_PSR83         INTC_0.PSR[83].R              /* INTC Priority Select Register */
#define INTC_0_PSR84         INTC_0.PSR[84].R              /* INTC Priority Select Register */
#define INTC_0_PSR85         INTC_0.PSR[85].R              /* INTC Priority Select Register */
#define INTC_0_PSR86         INTC_0.PSR[86].R              /* INTC Priority Select Register */
#define INTC_0_PSR87         INTC_0.PSR[87].R              /* INTC Priority Select Register */
#define INTC_0_PSR88         INTC_0.PSR[88].R              /* INTC Priority Select Register */
#define INTC_0_PSR89         INTC_0.PSR[89].R              /* INTC Priority Select Register */
#define INTC_0_PSR90         INTC_0.PSR[90].R              /* INTC Priority Select Register */
#define INTC_0_PSR91         INTC_0.PSR[91].R              /* INTC Priority Select Register */
#define INTC_0_PSR92         INTC_0.PSR[92].R              /* INTC Priority Select Register */
#define INTC_0_PSR93         INTC_0.PSR[93].R              /* INTC Priority Select Register */
#define INTC_0_PSR94         INTC_0.PSR[94].R              /* INTC Priority Select Register */
#define INTC_0_PSR95         INTC_0.PSR[95].R              /* INTC Priority Select Register */
#define INTC_0_PSR96         INTC_0.PSR[96].R              /* INTC Priority Select Register */
#define INTC_0_PSR97         INTC_0.PSR[97].R              /* INTC Priority Select Register */
#define INTC_0_PSR98         INTC_0.PSR[98].R              /* INTC Priority Select Register */
#define INTC_0_PSR99         INTC_0.PSR[99].R              /* INTC Priority Select Register */
#define INTC_0_PSR100        INTC_0.PSR[100].R             /* INTC Priority Select Register */
#define INTC_0_PSR101        INTC_0.PSR[101].R             /* INTC Priority Select Register */
#define INTC_0_PSR102        INTC_0.PSR[102].R             /* INTC Priority Select Register */
#define INTC_0_PSR103        INTC_0.PSR[103].R             /* INTC Priority Select Register */
#define INTC_0_PSR104        INTC_0.PSR[104].R             /* INTC Priority Select Register */
#define INTC_0_PSR105        INTC_0.PSR[105].R             /* INTC Priority Select Register */
#define INTC_0_PSR106        INTC_0.PSR[106].R             /* INTC Priority Select Register */
#define INTC_0_PSR107        INTC_0.PSR[107].R             /* INTC Priority Select Register */
#define INTC_0_PSR108        INTC_0.PSR[108].R             /* INTC Priority Select Register */
#define INTC_0_PSR109        INTC_0.PSR[109].R             /* INTC Priority Select Register */
#define INTC_0_PSR110        INTC_0.PSR[110].R             /* INTC Priority Select Register */
#define INTC_0_PSR111        INTC_0.PSR[111].R             /* INTC Priority Select Register */
#define INTC_0_PSR112        INTC_0.PSR[112].R             /* INTC Priority Select Register */
#define INTC_0_PSR113        INTC_0.PSR[113].R             /* INTC Priority Select Register */
#define INTC_0_PSR114        INTC_0.PSR[114].R             /* INTC Priority Select Register */
#define INTC_0_PSR115        INTC_0.PSR[115].R             /* INTC Priority Select Register */
#define INTC_0_PSR116        INTC_0.PSR[116].R             /* INTC Priority Select Register */
#define INTC_0_PSR117        INTC_0.PSR[117].R             /* INTC Priority Select Register */
#define INTC_0_PSR118        INTC_0.PSR[118].R             /* INTC Priority Select Register */
#define INTC_0_PSR119        INTC_0.PSR[119].R             /* INTC Priority Select Register */
#define INTC_0_PSR120        INTC_0.PSR[120].R             /* INTC Priority Select Register */
#define INTC_0_PSR121        INTC_0.PSR[121].R             /* INTC Priority Select Register */
#define INTC_0_PSR122        INTC_0.PSR[122].R             /* INTC Priority Select Register */
#define INTC_0_PSR123        INTC_0.PSR[123].R             /* INTC Priority Select Register */
#define INTC_0_PSR124        INTC_0.PSR[124].R             /* INTC Priority Select Register */
#define INTC_0_PSR125        INTC_0.PSR[125].R             /* INTC Priority Select Register */
#define INTC_0_PSR126        INTC_0.PSR[126].R             /* INTC Priority Select Register */
#define INTC_0_PSR127        INTC_0.PSR[127].R             /* INTC Priority Select Register */
#define INTC_0_PSR128        INTC_0.PSR[128].R             /* INTC Priority Select Register */
#define INTC_0_PSR129        INTC_0.PSR[129].R             /* INTC Priority Select Register */
#define INTC_0_PSR130        INTC_0.PSR[130].R             /* INTC Priority Select Register */
#define INTC_0_PSR131        INTC_0.PSR[131].R             /* INTC Priority Select Register */
#define INTC_0_PSR132        INTC_0.PSR[132].R             /* INTC Priority Select Register */
#define INTC_0_PSR133        INTC_0.PSR[133].R             /* INTC Priority Select Register */
#define INTC_0_PSR134        INTC_0.PSR[134].R             /* INTC Priority Select Register */
#define INTC_0_PSR135        INTC_0.PSR[135].R             /* INTC Priority Select Register */
#define INTC_0_PSR136        INTC_0.PSR[136].R             /* INTC Priority Select Register */
#define INTC_0_PSR137        INTC_0.PSR[137].R             /* INTC Priority Select Register */
#define INTC_0_PSR138        INTC_0.PSR[138].R             /* INTC Priority Select Register */
#define INTC_0_PSR139        INTC_0.PSR[139].R             /* INTC Priority Select Register */
#define INTC_0_PSR140        INTC_0.PSR[140].R             /* INTC Priority Select Register */
#define INTC_0_PSR141        INTC_0.PSR[141].R             /* INTC Priority Select Register */
#define INTC_0_PSR142        INTC_0.PSR[142].R             /* INTC Priority Select Register */
#define INTC_0_PSR143        INTC_0.PSR[143].R             /* INTC Priority Select Register */
#define INTC_0_PSR144        INTC_0.PSR[144].R             /* INTC Priority Select Register */
#define INTC_0_PSR145        INTC_0.PSR[145].R             /* INTC Priority Select Register */
#define INTC_0_PSR146        INTC_0.PSR[146].R             /* INTC Priority Select Register */
#define INTC_0_PSR147        INTC_0.PSR[147].R             /* INTC Priority Select Register */
#define INTC_0_PSR148        INTC_0.PSR[148].R             /* INTC Priority Select Register */
#define INTC_0_PSR149        INTC_0.PSR[149].R             /* INTC Priority Select Register */
#define INTC_0_PSR150        INTC_0.PSR[150].R             /* INTC Priority Select Register */
#define INTC_0_PSR151        INTC_0.PSR[151].R             /* INTC Priority Select Register */
#define INTC_0_PSR152        INTC_0.PSR[152].R             /* INTC Priority Select Register */
#define INTC_0_PSR153        INTC_0.PSR[153].R             /* INTC Priority Select Register */
#define INTC_0_PSR154        INTC_0.PSR[154].R             /* INTC Priority Select Register */
#define INTC_0_PSR155        INTC_0.PSR[155].R             /* INTC Priority Select Register */
#define INTC_0_PSR156        INTC_0.PSR[156].R             /* INTC Priority Select Register */
#define INTC_0_PSR157        INTC_0.PSR[157].R             /* INTC Priority Select Register */
#define INTC_0_PSR158        INTC_0.PSR[158].R             /* INTC Priority Select Register */
#define INTC_0_PSR159        INTC_0.PSR[159].R             /* INTC Priority Select Register */
#define INTC_0_PSR160        INTC_0.PSR[160].R             /* INTC Priority Select Register */
#define INTC_0_PSR161        INTC_0.PSR[161].R             /* INTC Priority Select Register */
#define INTC_0_PSR162        INTC_0.PSR[162].R             /* INTC Priority Select Register */
#define INTC_0_PSR163        INTC_0.PSR[163].R             /* INTC Priority Select Register */
#define INTC_0_PSR164        INTC_0.PSR[164].R             /* INTC Priority Select Register */
#define INTC_0_PSR165        INTC_0.PSR[165].R             /* INTC Priority Select Register */
#define INTC_0_PSR166        INTC_0.PSR[166].R             /* INTC Priority Select Register */
#define INTC_0_PSR167        INTC_0.PSR[167].R             /* INTC Priority Select Register */
#define INTC_0_PSR168        INTC_0.PSR[168].R             /* INTC Priority Select Register */
#define INTC_0_PSR169        INTC_0.PSR[169].R             /* INTC Priority Select Register */
#define INTC_0_PSR170        INTC_0.PSR[170].R             /* INTC Priority Select Register */
#define INTC_0_PSR171        INTC_0.PSR[171].R             /* INTC Priority Select Register */
#define INTC_0_PSR172        INTC_0.PSR[172].R             /* INTC Priority Select Register */
#define INTC_0_PSR173        INTC_0.PSR[173].R             /* INTC Priority Select Register */
#define INTC_0_PSR174        INTC_0.PSR[174].R             /* INTC Priority Select Register */
#define INTC_0_PSR175        INTC_0.PSR[175].R             /* INTC Priority Select Register */
#define INTC_0_PSR176        INTC_0.PSR[176].R             /* INTC Priority Select Register */
#define INTC_0_PSR177        INTC_0.PSR[177].R             /* INTC Priority Select Register */
#define INTC_0_PSR178        INTC_0.PSR[178].R             /* INTC Priority Select Register */
#define INTC_0_PSR179        INTC_0.PSR[179].R             /* INTC Priority Select Register */
#define INTC_0_PSR180        INTC_0.PSR[180].R             /* INTC Priority Select Register */
#define INTC_0_PSR181        INTC_0.PSR[181].R             /* INTC Priority Select Register */
#define INTC_0_PSR182        INTC_0.PSR[182].R             /* INTC Priority Select Register */
#define INTC_0_PSR183        INTC_0.PSR[183].R             /* INTC Priority Select Register */
#define INTC_0_PSR184        INTC_0.PSR[184].R             /* INTC Priority Select Register */
#define INTC_0_PSR185        INTC_0.PSR[185].R             /* INTC Priority Select Register */
#define INTC_0_PSR186        INTC_0.PSR[186].R             /* INTC Priority Select Register */
#define INTC_0_PSR187        INTC_0.PSR[187].R             /* INTC Priority Select Register */
#define INTC_0_PSR188        INTC_0.PSR[188].R             /* INTC Priority Select Register */
#define INTC_0_PSR189        INTC_0.PSR[189].R             /* INTC Priority Select Register */
#define INTC_0_PSR190        INTC_0.PSR[190].R             /* INTC Priority Select Register */
#define INTC_0_PSR191        INTC_0.PSR[191].R             /* INTC Priority Select Register */
#define INTC_0_PSR192        INTC_0.PSR[192].R             /* INTC Priority Select Register */
#define INTC_0_PSR193        INTC_0.PSR[193].R             /* INTC Priority Select Register */
#define INTC_0_PSR194        INTC_0.PSR[194].R             /* INTC Priority Select Register */
#define INTC_0_PSR195        INTC_0.PSR[195].R             /* INTC Priority Select Register */
#define INTC_0_PSR196        INTC_0.PSR[196].R             /* INTC Priority Select Register */
#define INTC_0_PSR197        INTC_0.PSR[197].R             /* INTC Priority Select Register */
#define INTC_0_PSR198        INTC_0.PSR[198].R             /* INTC Priority Select Register */
#define INTC_0_PSR199        INTC_0.PSR[199].R             /* INTC Priority Select Register */
#define INTC_0_PSR200        INTC_0.PSR[200].R             /* INTC Priority Select Register */
#define INTC_0_PSR201        INTC_0.PSR[201].R             /* INTC Priority Select Register */
#define INTC_0_PSR202        INTC_0.PSR[202].R             /* INTC Priority Select Register */
#define INTC_0_PSR203        INTC_0.PSR[203].R             /* INTC Priority Select Register */
#define INTC_0_PSR204        INTC_0.PSR[204].R             /* INTC Priority Select Register */
#define INTC_0_PSR205        INTC_0.PSR[205].R             /* INTC Priority Select Register */
#define INTC_0_PSR206        INTC_0.PSR[206].R             /* INTC Priority Select Register */
#define INTC_0_PSR207        INTC_0.PSR[207].R             /* INTC Priority Select Register */
#define INTC_0_PSR208        INTC_0.PSR[208].R             /* INTC Priority Select Register */
#define INTC_0_PSR209        INTC_0.PSR[209].R             /* INTC Priority Select Register */
#define INTC_0_PSR210        INTC_0.PSR[210].R             /* INTC Priority Select Register */
#define INTC_0_PSR211        INTC_0.PSR[211].R             /* INTC Priority Select Register */
#define INTC_0_PSR212        INTC_0.PSR[212].R             /* INTC Priority Select Register */
#define INTC_0_PSR213        INTC_0.PSR[213].R             /* INTC Priority Select Register */
#define INTC_0_PSR214        INTC_0.PSR[214].R             /* INTC Priority Select Register */
#define INTC_0_PSR215        INTC_0.PSR[215].R             /* INTC Priority Select Register */
#define INTC_0_PSR216        INTC_0.PSR[216].R             /* INTC Priority Select Register */
#define INTC_0_PSR217        INTC_0.PSR[217].R             /* INTC Priority Select Register */
#define INTC_0_PSR218        INTC_0.PSR[218].R             /* INTC Priority Select Register */
#define INTC_0_PSR219        INTC_0.PSR[219].R             /* INTC Priority Select Register */
#define INTC_0_PSR220        INTC_0.PSR[220].R             /* INTC Priority Select Register */
#define INTC_0_PSR221        INTC_0.PSR[221].R             /* INTC Priority Select Register */
#define INTC_0_PSR222        INTC_0.PSR[222].R             /* INTC Priority Select Register */
#define INTC_0_PSR223        INTC_0.PSR[223].R             /* INTC Priority Select Register */
#define INTC_0_PSR224        INTC_0.PSR[224].R             /* INTC Priority Select Register */
#define INTC_0_PSR225        INTC_0.PSR[225].R             /* INTC Priority Select Register */
#define INTC_0_PSR226        INTC_0.PSR[226].R             /* INTC Priority Select Register */
#define INTC_0_PSR227        INTC_0.PSR[227].R             /* INTC Priority Select Register */
#define INTC_0_PSR228        INTC_0.PSR[228].R             /* INTC Priority Select Register */
#define INTC_0_PSR229        INTC_0.PSR[229].R             /* INTC Priority Select Register */
#define INTC_0_PSR230        INTC_0.PSR[230].R             /* INTC Priority Select Register */
#define INTC_0_PSR231        INTC_0.PSR[231].R             /* INTC Priority Select Register */
#define INTC_0_PSR232        INTC_0.PSR[232].R             /* INTC Priority Select Register */
#define INTC_0_PSR233        INTC_0.PSR[233].R             /* INTC Priority Select Register */
#define INTC_0_PSR234        INTC_0.PSR[234].R             /* INTC Priority Select Register */
#define INTC_0_PSR235        INTC_0.PSR[235].R             /* INTC Priority Select Register */
#define INTC_0_PSR236        INTC_0.PSR[236].R             /* INTC Priority Select Register */
#define INTC_0_PSR237        INTC_0.PSR[237].R             /* INTC Priority Select Register */
#define INTC_0_PSR238        INTC_0.PSR[238].R             /* INTC Priority Select Register */
#define INTC_0_PSR239        INTC_0.PSR[239].R             /* INTC Priority Select Register */
#define INTC_0_PSR240        INTC_0.PSR[240].R             /* INTC Priority Select Register */
#define INTC_0_PSR241        INTC_0.PSR[241].R             /* INTC Priority Select Register */
#define INTC_0_PSR242        INTC_0.PSR[242].R             /* INTC Priority Select Register */
#define INTC_0_PSR243        INTC_0.PSR[243].R             /* INTC Priority Select Register */
#define INTC_0_PSR244        INTC_0.PSR[244].R             /* INTC Priority Select Register */
#define INTC_0_PSR245        INTC_0.PSR[245].R             /* INTC Priority Select Register */
#define INTC_0_PSR246        INTC_0.PSR[246].R             /* INTC Priority Select Register */
#define INTC_0_PSR247        INTC_0.PSR[247].R             /* INTC Priority Select Register */
#define INTC_0_PSR248        INTC_0.PSR[248].R             /* INTC Priority Select Register */
#define INTC_0_PSR249        INTC_0.PSR[249].R             /* INTC Priority Select Register */
#define INTC_0_PSR250        INTC_0.PSR[250].R             /* INTC Priority Select Register */
#define INTC_0_PSR251        INTC_0.PSR[251].R             /* INTC Priority Select Register */
#define INTC_0_PSR252        INTC_0.PSR[252].R             /* INTC Priority Select Register */
#define INTC_0_PSR253        INTC_0.PSR[253].R             /* INTC Priority Select Register */
#define INTC_0_PSR254        INTC_0.PSR[254].R             /* INTC Priority Select Register */
#define INTC_0_PSR255        INTC_0.PSR[255].R             /* INTC Priority Select Register */
#define INTC_0_PSR256        INTC_0.PSR[256].R             /* INTC Priority Select Register */
#define INTC_0_PSR257        INTC_0.PSR[257].R             /* INTC Priority Select Register */
#define INTC_0_PSR258        INTC_0.PSR[258].R             /* INTC Priority Select Register */
#define INTC_0_PSR259        INTC_0.PSR[259].R             /* INTC Priority Select Register */
#define INTC_0_PSR260        INTC_0.PSR[260].R             /* INTC Priority Select Register */
#define INTC_0_PSR261        INTC_0.PSR[261].R             /* INTC Priority Select Register */
#define INTC_0_PSR262        INTC_0.PSR[262].R             /* INTC Priority Select Register */
#define INTC_0_PSR263        INTC_0.PSR[263].R             /* INTC Priority Select Register */
#define INTC_0_PSR264        INTC_0.PSR[264].R             /* INTC Priority Select Register */
#define INTC_0_PSR265        INTC_0.PSR[265].R             /* INTC Priority Select Register */
#define INTC_0_PSR266        INTC_0.PSR[266].R             /* INTC Priority Select Register */
#define INTC_0_PSR267        INTC_0.PSR[267].R             /* INTC Priority Select Register */
#define INTC_0_PSR268        INTC_0.PSR[268].R             /* INTC Priority Select Register */
#define INTC_0_PSR269        INTC_0.PSR[269].R             /* INTC Priority Select Register */
#define INTC_0_PSR270        INTC_0.PSR[270].R             /* INTC Priority Select Register */
#define INTC_0_PSR271        INTC_0.PSR[271].R             /* INTC Priority Select Register */
#define INTC_0_PSR272        INTC_0.PSR[272].R             /* INTC Priority Select Register */
#define INTC_0_PSR273        INTC_0.PSR[273].R             /* INTC Priority Select Register */
#define INTC_0_PSR274        INTC_0.PSR[274].R             /* INTC Priority Select Register */
#define INTC_0_PSR275        INTC_0.PSR[275].R             /* INTC Priority Select Register */
#define INTC_0_PSR276        INTC_0.PSR[276].R             /* INTC Priority Select Register */
#define INTC_0_PSR277        INTC_0.PSR[277].R             /* INTC Priority Select Register */
#define INTC_0_PSR278        INTC_0.PSR[278].R             /* INTC Priority Select Register */
#define INTC_0_PSR279        INTC_0.PSR[279].R             /* INTC Priority Select Register */
#define INTC_0_PSR280        INTC_0.PSR[280].R             /* INTC Priority Select Register */
#define INTC_0_PSR281        INTC_0.PSR[281].R             /* INTC Priority Select Register */
#define INTC_0_PSR282        INTC_0.PSR[282].R             /* INTC Priority Select Register */
#define INTC_0_PSR283        INTC_0.PSR[283].R             /* INTC Priority Select Register */
#define INTC_0_PSR284        INTC_0.PSR[284].R             /* INTC Priority Select Register */
#define INTC_0_PSR285        INTC_0.PSR[285].R             /* INTC Priority Select Register */
#define INTC_0_PSR286        INTC_0.PSR[286].R             /* INTC Priority Select Register */
#define INTC_0_PSR287        INTC_0.PSR[287].R             /* INTC Priority Select Register */
#define INTC_0_PSR288        INTC_0.PSR[288].R             /* INTC Priority Select Register */
#define INTC_0_PSR289        INTC_0.PSR[289].R             /* INTC Priority Select Register */
#define INTC_0_PSR290        INTC_0.PSR[290].R             /* INTC Priority Select Register */
#define INTC_0_PSR291        INTC_0.PSR[291].R             /* INTC Priority Select Register */
#define INTC_0_PSR292        INTC_0.PSR[292].R             /* INTC Priority Select Register */
#define INTC_0_PSR293        INTC_0.PSR[293].R             /* INTC Priority Select Register */
#define INTC_0_PSR294        INTC_0.PSR[294].R             /* INTC Priority Select Register */
#define INTC_0_PSR295        INTC_0.PSR[295].R             /* INTC Priority Select Register */
#define INTC_0_PSR296        INTC_0.PSR[296].R             /* INTC Priority Select Register */
#define INTC_0_PSR297        INTC_0.PSR[297].R             /* INTC Priority Select Register */
#define INTC_0_PSR298        INTC_0.PSR[298].R             /* INTC Priority Select Register */
#define INTC_0_PSR299        INTC_0.PSR[299].R             /* INTC Priority Select Register */
#define INTC_0_PSR300        INTC_0.PSR[300].R             /* INTC Priority Select Register */
#define INTC_0_PSR301        INTC_0.PSR[301].R             /* INTC Priority Select Register */
#define INTC_0_PSR302        INTC_0.PSR[302].R             /* INTC Priority Select Register */
#define INTC_0_PSR303        INTC_0.PSR[303].R             /* INTC Priority Select Register */
#define INTC_0_PSR304        INTC_0.PSR[304].R             /* INTC Priority Select Register */
#define INTC_0_PSR305        INTC_0.PSR[305].R             /* INTC Priority Select Register */
#define INTC_0_PSR306        INTC_0.PSR[306].R             /* INTC Priority Select Register */
#define INTC_0_PSR307        INTC_0.PSR[307].R             /* INTC Priority Select Register */
#define INTC_0_PSR308        INTC_0.PSR[308].R             /* INTC Priority Select Register */
#define INTC_0_PSR309        INTC_0.PSR[309].R             /* INTC Priority Select Register */
#define INTC_0_PSR310        INTC_0.PSR[310].R             /* INTC Priority Select Register */
#define INTC_0_PSR311        INTC_0.PSR[311].R             /* INTC Priority Select Register */
#define INTC_0_PSR312        INTC_0.PSR[312].R             /* INTC Priority Select Register */
#define INTC_0_PSR313        INTC_0.PSR[313].R             /* INTC Priority Select Register */
#define INTC_0_PSR314        INTC_0.PSR[314].R             /* INTC Priority Select Register */
#define INTC_0_PSR315        INTC_0.PSR[315].R             /* INTC Priority Select Register */
#define INTC_0_PSR316        INTC_0.PSR[316].R             /* INTC Priority Select Register */
#define INTC_0_PSR317        INTC_0.PSR[317].R             /* INTC Priority Select Register */
#define INTC_0_PSR318        INTC_0.PSR[318].R             /* INTC Priority Select Register */
#define INTC_0_PSR319        INTC_0.PSR[319].R             /* INTC Priority Select Register */
#define INTC_0_PSR320        INTC_0.PSR[320].R             /* INTC Priority Select Register */
#define INTC_0_PSR321        INTC_0.PSR[321].R             /* INTC Priority Select Register */
#define INTC_0_PSR322        INTC_0.PSR[322].R             /* INTC Priority Select Register */
#define INTC_0_PSR323        INTC_0.PSR[323].R             /* INTC Priority Select Register */
#define INTC_0_PSR324        INTC_0.PSR[324].R             /* INTC Priority Select Register */
#define INTC_0_PSR325        INTC_0.PSR[325].R             /* INTC Priority Select Register */
#define INTC_0_PSR326        INTC_0.PSR[326].R             /* INTC Priority Select Register */
#define INTC_0_PSR327        INTC_0.PSR[327].R             /* INTC Priority Select Register */
#define INTC_0_PSR328        INTC_0.PSR[328].R             /* INTC Priority Select Register */
#define INTC_0_PSR329        INTC_0.PSR[329].R             /* INTC Priority Select Register */
#define INTC_0_PSR330        INTC_0.PSR[330].R             /* INTC Priority Select Register */
#define INTC_0_PSR331        INTC_0.PSR[331].R             /* INTC Priority Select Register */
#define INTC_0_PSR332        INTC_0.PSR[332].R             /* INTC Priority Select Register */
#define INTC_0_PSR333        INTC_0.PSR[333].R             /* INTC Priority Select Register */
#define INTC_0_PSR334        INTC_0.PSR[334].R             /* INTC Priority Select Register */
#define INTC_0_PSR335        INTC_0.PSR[335].R             /* INTC Priority Select Register */
#define INTC_0_PSR336        INTC_0.PSR[336].R             /* INTC Priority Select Register */
#define INTC_0_PSR337        INTC_0.PSR[337].R             /* INTC Priority Select Register */
#define INTC_0_PSR338        INTC_0.PSR[338].R             /* INTC Priority Select Register */
#define INTC_0_PSR339        INTC_0.PSR[339].R             /* INTC Priority Select Register */
#define INTC_0_PSR340        INTC_0.PSR[340].R             /* INTC Priority Select Register */
#define INTC_0_PSR341        INTC_0.PSR[341].R             /* INTC Priority Select Register */
#define INTC_0_PSR342        INTC_0.PSR[342].R             /* INTC Priority Select Register */
#define INTC_0_PSR343        INTC_0.PSR[343].R             /* INTC Priority Select Register */
#define INTC_0_PSR344        INTC_0.PSR[344].R             /* INTC Priority Select Register */
#define INTC_0_PSR345        INTC_0.PSR[345].R             /* INTC Priority Select Register */
#define INTC_0_PSR346        INTC_0.PSR[346].R             /* INTC Priority Select Register */
#define INTC_0_PSR347        INTC_0.PSR[347].R             /* INTC Priority Select Register */
#define INTC_0_PSR348        INTC_0.PSR[348].R             /* INTC Priority Select Register */
#define INTC_0_PSR349        INTC_0.PSR[349].R             /* INTC Priority Select Register */
#define INTC_0_PSR350        INTC_0.PSR[350].R             /* INTC Priority Select Register */
#define INTC_0_PSR351        INTC_0.PSR[351].R             /* INTC Priority Select Register */
#define INTC_0_PSR352        INTC_0.PSR[352].R             /* INTC Priority Select Register */
#define INTC_0_PSR353        INTC_0.PSR[353].R             /* INTC Priority Select Register */
#define INTC_0_PSR354        INTC_0.PSR[354].R             /* INTC Priority Select Register */
#define INTC_0_PSR355        INTC_0.PSR[355].R             /* INTC Priority Select Register */
#define INTC_0_PSR356        INTC_0.PSR[356].R             /* INTC Priority Select Register */
#define INTC_0_PSR357        INTC_0.PSR[357].R             /* INTC Priority Select Register */
#define INTC_0_PSR358        INTC_0.PSR[358].R             /* INTC Priority Select Register */
#define INTC_0_PSR359        INTC_0.PSR[359].R             /* INTC Priority Select Register */
#define INTC_0_PSR360        INTC_0.PSR[360].R             /* INTC Priority Select Register */
#define INTC_0_PSR361        INTC_0.PSR[361].R             /* INTC Priority Select Register */
#define INTC_0_PSR362        INTC_0.PSR[362].R             /* INTC Priority Select Register */
#define INTC_0_PSR363        INTC_0.PSR[363].R             /* INTC Priority Select Register */
#define INTC_0_PSR364        INTC_0.PSR[364].R             /* INTC Priority Select Register */
#define INTC_0_PSR365        INTC_0.PSR[365].R             /* INTC Priority Select Register */
#define INTC_0_PSR366        INTC_0.PSR[366].R             /* INTC Priority Select Register */
#define INTC_0_PSR367        INTC_0.PSR[367].R             /* INTC Priority Select Register */
#define INTC_0_PSR368        INTC_0.PSR[368].R             /* INTC Priority Select Register */
#define INTC_0_PSR369        INTC_0.PSR[369].R             /* INTC Priority Select Register */
#define INTC_0_PSR370        INTC_0.PSR[370].R             /* INTC Priority Select Register */
#define INTC_0_PSR371        INTC_0.PSR[371].R             /* INTC Priority Select Register */
#define INTC_0_PSR372        INTC_0.PSR[372].R             /* INTC Priority Select Register */
#define INTC_0_PSR373        INTC_0.PSR[373].R             /* INTC Priority Select Register */
#define INTC_0_PSR374        INTC_0.PSR[374].R             /* INTC Priority Select Register */
#define INTC_0_PSR375        INTC_0.PSR[375].R             /* INTC Priority Select Register */
#define INTC_0_PSR376        INTC_0.PSR[376].R             /* INTC Priority Select Register */
#define INTC_0_PSR377        INTC_0.PSR[377].R             /* INTC Priority Select Register */
#define INTC_0_PSR378        INTC_0.PSR[378].R             /* INTC Priority Select Register */
#define INTC_0_PSR379        INTC_0.PSR[379].R             /* INTC Priority Select Register */
#define INTC_0_PSR380        INTC_0.PSR[380].R             /* INTC Priority Select Register */
#define INTC_0_PSR381        INTC_0.PSR[381].R             /* INTC Priority Select Register */
#define INTC_0_PSR382        INTC_0.PSR[382].R             /* INTC Priority Select Register */
#define INTC_0_PSR383        INTC_0.PSR[383].R             /* INTC Priority Select Register */
#define INTC_0_PSR384        INTC_0.PSR[384].R             /* INTC Priority Select Register */
#define INTC_0_PSR385        INTC_0.PSR[385].R             /* INTC Priority Select Register */
#define INTC_0_PSR386        INTC_0.PSR[386].R             /* INTC Priority Select Register */
#define INTC_0_PSR387        INTC_0.PSR[387].R             /* INTC Priority Select Register */
#define INTC_0_PSR388        INTC_0.PSR[388].R             /* INTC Priority Select Register */
#define INTC_0_PSR389        INTC_0.PSR[389].R             /* INTC Priority Select Register */
#define INTC_0_PSR390        INTC_0.PSR[390].R             /* INTC Priority Select Register */
#define INTC_0_PSR391        INTC_0.PSR[391].R             /* INTC Priority Select Register */
#define INTC_0_PSR392        INTC_0.PSR[392].R             /* INTC Priority Select Register */
#define INTC_0_PSR393        INTC_0.PSR[393].R             /* INTC Priority Select Register */
#define INTC_0_PSR394        INTC_0.PSR[394].R             /* INTC Priority Select Register */
#define INTC_0_PSR395        INTC_0.PSR[395].R             /* INTC Priority Select Register */
#define INTC_0_PSR396        INTC_0.PSR[396].R             /* INTC Priority Select Register */
#define INTC_0_PSR397        INTC_0.PSR[397].R             /* INTC Priority Select Register */
#define INTC_0_PSR398        INTC_0.PSR[398].R             /* INTC Priority Select Register */
#define INTC_0_PSR399        INTC_0.PSR[399].R             /* INTC Priority Select Register */
#define INTC_0_PSR400        INTC_0.PSR[400].R             /* INTC Priority Select Register */
#define INTC_0_PSR401        INTC_0.PSR[401].R             /* INTC Priority Select Register */
#define INTC_0_PSR402        INTC_0.PSR[402].R             /* INTC Priority Select Register */
#define INTC_0_PSR403        INTC_0.PSR[403].R             /* INTC Priority Select Register */
#define INTC_0_PSR404        INTC_0.PSR[404].R             /* INTC Priority Select Register */
#define INTC_0_PSR405        INTC_0.PSR[405].R             /* INTC Priority Select Register */
#define INTC_0_PSR406        INTC_0.PSR[406].R             /* INTC Priority Select Register */
#define INTC_0_PSR407        INTC_0.PSR[407].R             /* INTC Priority Select Register */
#define INTC_0_PSR408        INTC_0.PSR[408].R             /* INTC Priority Select Register */
#define INTC_0_PSR409        INTC_0.PSR[409].R             /* INTC Priority Select Register */
#define INTC_0_PSR410        INTC_0.PSR[410].R             /* INTC Priority Select Register */
#define INTC_0_PSR411        INTC_0.PSR[411].R             /* INTC Priority Select Register */
#define INTC_0_PSR412        INTC_0.PSR[412].R             /* INTC Priority Select Register */
#define INTC_0_PSR413        INTC_0.PSR[413].R             /* INTC Priority Select Register */
#define INTC_0_PSR414        INTC_0.PSR[414].R             /* INTC Priority Select Register */
#define INTC_0_PSR415        INTC_0.PSR[415].R             /* INTC Priority Select Register */
#define INTC_0_PSR416        INTC_0.PSR[416].R             /* INTC Priority Select Register */
#define INTC_0_PSR417        INTC_0.PSR[417].R             /* INTC Priority Select Register */
#define INTC_0_PSR418        INTC_0.PSR[418].R             /* INTC Priority Select Register */
#define INTC_0_PSR419        INTC_0.PSR[419].R             /* INTC Priority Select Register */
#define INTC_0_PSR420        INTC_0.PSR[420].R             /* INTC Priority Select Register */
#define INTC_0_PSR421        INTC_0.PSR[421].R             /* INTC Priority Select Register */
#define INTC_0_PSR422        INTC_0.PSR[422].R             /* INTC Priority Select Register */
#define INTC_0_PSR423        INTC_0.PSR[423].R             /* INTC Priority Select Register */
#define INTC_0_PSR424        INTC_0.PSR[424].R             /* INTC Priority Select Register */
#define INTC_0_PSR425        INTC_0.PSR[425].R             /* INTC Priority Select Register */
#define INTC_0_PSR426        INTC_0.PSR[426].R             /* INTC Priority Select Register */
#define INTC_0_PSR427        INTC_0.PSR[427].R             /* INTC Priority Select Register */
#define INTC_0_PSR428        INTC_0.PSR[428].R             /* INTC Priority Select Register */
#define INTC_0_PSR429        INTC_0.PSR[429].R             /* INTC Priority Select Register */
#define INTC_0_PSR430        INTC_0.PSR[430].R             /* INTC Priority Select Register */
#define INTC_0_PSR431        INTC_0.PSR[431].R             /* INTC Priority Select Register */
#define INTC_0_PSR432        INTC_0.PSR[432].R             /* INTC Priority Select Register */
#define INTC_0_PSR433        INTC_0.PSR[433].R             /* INTC Priority Select Register */
#define INTC_0_PSR434        INTC_0.PSR[434].R             /* INTC Priority Select Register */
#define INTC_0_PSR435        INTC_0.PSR[435].R             /* INTC Priority Select Register */
#define INTC_0_PSR436        INTC_0.PSR[436].R             /* INTC Priority Select Register */
#define INTC_0_PSR437        INTC_0.PSR[437].R             /* INTC Priority Select Register */
#define INTC_0_PSR438        INTC_0.PSR[438].R             /* INTC Priority Select Register */
#define INTC_0_PSR439        INTC_0.PSR[439].R             /* INTC Priority Select Register */
#define INTC_0_PSR440        INTC_0.PSR[440].R             /* INTC Priority Select Register */
#define INTC_0_PSR441        INTC_0.PSR[441].R             /* INTC Priority Select Register */
#define INTC_0_PSR442        INTC_0.PSR[442].R             /* INTC Priority Select Register */
#define INTC_0_PSR443        INTC_0.PSR[443].R             /* INTC Priority Select Register */
#define INTC_0_PSR444        INTC_0.PSR[444].R             /* INTC Priority Select Register */
#define INTC_0_PSR445        INTC_0.PSR[445].R             /* INTC Priority Select Register */
#define INTC_0_PSR446        INTC_0.PSR[446].R             /* INTC Priority Select Register */
#define INTC_0_PSR447        INTC_0.PSR[447].R             /* INTC Priority Select Register */
#define INTC_0_PSR448        INTC_0.PSR[448].R             /* INTC Priority Select Register */
#define INTC_0_PSR449        INTC_0.PSR[449].R             /* INTC Priority Select Register */
#define INTC_0_PSR450        INTC_0.PSR[450].R             /* INTC Priority Select Register */
#define INTC_0_PSR451        INTC_0.PSR[451].R             /* INTC Priority Select Register */
#define INTC_0_PSR452        INTC_0.PSR[452].R             /* INTC Priority Select Register */
#define INTC_0_PSR453        INTC_0.PSR[453].R             /* INTC Priority Select Register */
#define INTC_0_PSR454        INTC_0.PSR[454].R             /* INTC Priority Select Register */
#define INTC_0_PSR455        INTC_0.PSR[455].R             /* INTC Priority Select Register */
#define INTC_0_PSR456        INTC_0.PSR[456].R             /* INTC Priority Select Register */
#define INTC_0_PSR457        INTC_0.PSR[457].R             /* INTC Priority Select Register */
#define INTC_0_PSR458        INTC_0.PSR[458].R             /* INTC Priority Select Register */
#define INTC_0_PSR459        INTC_0.PSR[459].R             /* INTC Priority Select Register */
#define INTC_0_PSR460        INTC_0.PSR[460].R             /* INTC Priority Select Register */
#define INTC_0_PSR461        INTC_0.PSR[461].R             /* INTC Priority Select Register */
#define INTC_0_PSR462        INTC_0.PSR[462].R             /* INTC Priority Select Register */
#define INTC_0_PSR463        INTC_0.PSR[463].R             /* INTC Priority Select Register */
#define INTC_0_PSR464        INTC_0.PSR[464].R             /* INTC Priority Select Register */
#define INTC_0_PSR465        INTC_0.PSR[465].R             /* INTC Priority Select Register */
#define INTC_0_PSR466        INTC_0.PSR[466].R             /* INTC Priority Select Register */
#define INTC_0_PSR467        INTC_0.PSR[467].R             /* INTC Priority Select Register */
#define INTC_0_PSR468        INTC_0.PSR[468].R             /* INTC Priority Select Register */
#define INTC_0_PSR469        INTC_0.PSR[469].R             /* INTC Priority Select Register */
#define INTC_0_PSR470        INTC_0.PSR[470].R             /* INTC Priority Select Register */
#define INTC_0_PSR471        INTC_0.PSR[471].R             /* INTC Priority Select Register */
#define INTC_0_PSR472        INTC_0.PSR[472].R             /* INTC Priority Select Register */
#define INTC_0_PSR473        INTC_0.PSR[473].R             /* INTC Priority Select Register */
#define INTC_0_PSR474        INTC_0.PSR[474].R             /* INTC Priority Select Register */
#define INTC_0_PSR475        INTC_0.PSR[475].R             /* INTC Priority Select Register */
#define INTC_0_PSR476        INTC_0.PSR[476].R             /* INTC Priority Select Register */
#define INTC_0_PSR477        INTC_0.PSR[477].R             /* INTC Priority Select Register */
#define INTC_0_PSR478        INTC_0.PSR[478].R             /* INTC Priority Select Register */
#define INTC_0_PSR479        INTC_0.PSR[479].R             /* INTC Priority Select Register */
#define INTC_0_PSR480        INTC_0.PSR[480].R             /* INTC Priority Select Register */
#define INTC_0_PSR481        INTC_0.PSR[481].R             /* INTC Priority Select Register */
#define INTC_0_PSR482        INTC_0.PSR[482].R             /* INTC Priority Select Register */
#define INTC_0_PSR483        INTC_0.PSR[483].R             /* INTC Priority Select Register */
#define INTC_0_PSR484        INTC_0.PSR[484].R             /* INTC Priority Select Register */
#define INTC_0_PSR485        INTC_0.PSR[485].R             /* INTC Priority Select Register */
#define INTC_0_PSR486        INTC_0.PSR[486].R             /* INTC Priority Select Register */
#define INTC_0_PSR487        INTC_0.PSR[487].R             /* INTC Priority Select Register */
#define INTC_0_PSR488        INTC_0.PSR[488].R             /* INTC Priority Select Register */
#define INTC_0_PSR489        INTC_0.PSR[489].R             /* INTC Priority Select Register */
#define INTC_0_PSR490        INTC_0.PSR[490].R             /* INTC Priority Select Register */
#define INTC_0_PSR491        INTC_0.PSR[491].R             /* INTC Priority Select Register */
#define INTC_0_PSR492        INTC_0.PSR[492].R             /* INTC Priority Select Register */
#define INTC_0_PSR493        INTC_0.PSR[493].R             /* INTC Priority Select Register */
#define INTC_0_PSR494        INTC_0.PSR[494].R             /* INTC Priority Select Register */
#define INTC_0_PSR495        INTC_0.PSR[495].R             /* INTC Priority Select Register */
#define INTC_0_PSR496        INTC_0.PSR[496].R             /* INTC Priority Select Register */
#define INTC_0_PSR497        INTC_0.PSR[497].R             /* INTC Priority Select Register */
#define INTC_0_PSR498        INTC_0.PSR[498].R             /* INTC Priority Select Register */
#define INTC_0_PSR499        INTC_0.PSR[499].R             /* INTC Priority Select Register */
#define INTC_0_PSR500        INTC_0.PSR[500].R             /* INTC Priority Select Register */
#define INTC_0_PSR501        INTC_0.PSR[501].R             /* INTC Priority Select Register */
#define INTC_0_PSR502        INTC_0.PSR[502].R             /* INTC Priority Select Register */
#define INTC_0_PSR503        INTC_0.PSR[503].R             /* INTC Priority Select Register */
#define INTC_0_PSR504        INTC_0.PSR[504].R             /* INTC Priority Select Register */
#define INTC_0_PSR505        INTC_0.PSR[505].R             /* INTC Priority Select Register */
#define INTC_0_PSR506        INTC_0.PSR[506].R             /* INTC Priority Select Register */
#define INTC_0_PSR507        INTC_0.PSR[507].R             /* INTC Priority Select Register */
#define INTC_0_PSR508        INTC_0.PSR[508].R             /* INTC Priority Select Register */
#define INTC_0_PSR509        INTC_0.PSR[509].R             /* INTC Priority Select Register */
#define INTC_0_PSR510        INTC_0.PSR[510].R             /* INTC Priority Select Register */
#define INTC_0_PSR511        INTC_0.PSR[511].R             /* INTC Priority Select Register */
#define INTC_0_PSR512        INTC_0.PSR[512].R             /* INTC Priority Select Register */
#define INTC_0_PSR513        INTC_0.PSR[513].R             /* INTC Priority Select Register */
#define INTC_0_PSR514        INTC_0.PSR[514].R             /* INTC Priority Select Register */
#define INTC_0_PSR515        INTC_0.PSR[515].R             /* INTC Priority Select Register */
#define INTC_0_PSR516        INTC_0.PSR[516].R             /* INTC Priority Select Register */
#define INTC_0_PSR517        INTC_0.PSR[517].R             /* INTC Priority Select Register */
#define INTC_0_PSR518        INTC_0.PSR[518].R             /* INTC Priority Select Register */
#define INTC_0_PSR519        INTC_0.PSR[519].R             /* INTC Priority Select Register */
#define INTC_0_PSR520        INTC_0.PSR[520].R             /* INTC Priority Select Register */
#define INTC_0_PSR521        INTC_0.PSR[521].R             /* INTC Priority Select Register */
#define INTC_0_PSR522        INTC_0.PSR[522].R             /* INTC Priority Select Register */
#define INTC_0_PSR523        INTC_0.PSR[523].R             /* INTC Priority Select Register */
#define INTC_0_PSR524        INTC_0.PSR[524].R             /* INTC Priority Select Register */
#define INTC_0_PSR525        INTC_0.PSR[525].R             /* INTC Priority Select Register */
#define INTC_0_PSR526        INTC_0.PSR[526].R             /* INTC Priority Select Register */
#define INTC_0_PSR527        INTC_0.PSR[527].R             /* INTC Priority Select Register */
#define INTC_0_PSR528        INTC_0.PSR[528].R             /* INTC Priority Select Register */
#define INTC_0_PSR529        INTC_0.PSR[529].R             /* INTC Priority Select Register */
#define INTC_0_PSR530        INTC_0.PSR[530].R             /* INTC Priority Select Register */
#define INTC_0_PSR531        INTC_0.PSR[531].R             /* INTC Priority Select Register */
#define INTC_0_PSR532        INTC_0.PSR[532].R             /* INTC Priority Select Register */
#define INTC_0_PSR533        INTC_0.PSR[533].R             /* INTC Priority Select Register */
#define INTC_0_PSR534        INTC_0.PSR[534].R             /* INTC Priority Select Register */
#define INTC_0_PSR535        INTC_0.PSR[535].R             /* INTC Priority Select Register */
#define INTC_0_PSR536        INTC_0.PSR[536].R             /* INTC Priority Select Register */
#define INTC_0_PSR537        INTC_0.PSR[537].R             /* INTC Priority Select Register */
#define INTC_0_PSR538        INTC_0.PSR[538].R             /* INTC Priority Select Register */
#define INTC_0_PSR539        INTC_0.PSR[539].R             /* INTC Priority Select Register */
#define INTC_0_PSR540        INTC_0.PSR[540].R             /* INTC Priority Select Register */
#define INTC_0_PSR541        INTC_0.PSR[541].R             /* INTC Priority Select Register */
#define INTC_0_PSR542        INTC_0.PSR[542].R             /* INTC Priority Select Register */
#define INTC_0_PSR543        INTC_0.PSR[543].R             /* INTC Priority Select Register */
#define INTC_0_PSR544        INTC_0.PSR[544].R             /* INTC Priority Select Register */
#define INTC_0_PSR545        INTC_0.PSR[545].R             /* INTC Priority Select Register */
#define INTC_0_PSR546        INTC_0.PSR[546].R             /* INTC Priority Select Register */
#define INTC_0_PSR547        INTC_0.PSR[547].R             /* INTC Priority Select Register */
#define INTC_0_PSR548        INTC_0.PSR[548].R             /* INTC Priority Select Register */
#define INTC_0_PSR549        INTC_0.PSR[549].R             /* INTC Priority Select Register */
#define INTC_0_PSR550        INTC_0.PSR[550].R             /* INTC Priority Select Register */
#define INTC_0_PSR551        INTC_0.PSR[551].R             /* INTC Priority Select Register */
#define INTC_0_PSR552        INTC_0.PSR[552].R             /* INTC Priority Select Register */
#define INTC_0_PSR553        INTC_0.PSR[553].R             /* INTC Priority Select Register */
#define INTC_0_PSR554        INTC_0.PSR[554].R             /* INTC Priority Select Register */
#define INTC_0_PSR555        INTC_0.PSR[555].R             /* INTC Priority Select Register */
#define INTC_0_PSR556        INTC_0.PSR[556].R             /* INTC Priority Select Register */
#define INTC_0_PSR557        INTC_0.PSR[557].R             /* INTC Priority Select Register */
#define INTC_0_PSR558        INTC_0.PSR[558].R             /* INTC Priority Select Register */
#define INTC_0_PSR559        INTC_0.PSR[559].R             /* INTC Priority Select Register */
#define INTC_0_PSR560        INTC_0.PSR[560].R             /* INTC Priority Select Register */
#define INTC_0_PSR561        INTC_0.PSR[561].R             /* INTC Priority Select Register */
#define INTC_0_PSR562        INTC_0.PSR[562].R             /* INTC Priority Select Register */
#define INTC_0_PSR563        INTC_0.PSR[563].R             /* INTC Priority Select Register */
#define INTC_0_PSR564        INTC_0.PSR[564].R             /* INTC Priority Select Register */
#define INTC_0_PSR565        INTC_0.PSR[565].R             /* INTC Priority Select Register */
#define INTC_0_PSR566        INTC_0.PSR[566].R             /* INTC Priority Select Register */
#define INTC_0_PSR567        INTC_0.PSR[567].R             /* INTC Priority Select Register */
#define INTC_0_PSR568        INTC_0.PSR[568].R             /* INTC Priority Select Register */
#define INTC_0_PSR569        INTC_0.PSR[569].R             /* INTC Priority Select Register */
#define INTC_0_PSR570        INTC_0.PSR[570].R             /* INTC Priority Select Register */
#define INTC_0_PSR571        INTC_0.PSR[571].R             /* INTC Priority Select Register */
#define INTC_0_PSR572        INTC_0.PSR[572].R             /* INTC Priority Select Register */
#define INTC_0_PSR573        INTC_0.PSR[573].R             /* INTC Priority Select Register */
#define INTC_0_PSR574        INTC_0.PSR[574].R             /* INTC Priority Select Register */
#define INTC_0_PSR575        INTC_0.PSR[575].R             /* INTC Priority Select Register */
#define INTC_0_PSR576        INTC_0.PSR[576].R             /* INTC Priority Select Register */
#define INTC_0_PSR577        INTC_0.PSR[577].R             /* INTC Priority Select Register */
#define INTC_0_PSR578        INTC_0.PSR[578].R             /* INTC Priority Select Register */
#define INTC_0_PSR579        INTC_0.PSR[579].R             /* INTC Priority Select Register */
#define INTC_0_PSR580        INTC_0.PSR[580].R             /* INTC Priority Select Register */
#define INTC_0_PSR581        INTC_0.PSR[581].R             /* INTC Priority Select Register */
#define INTC_0_PSR582        INTC_0.PSR[582].R             /* INTC Priority Select Register */
#define INTC_0_PSR583        INTC_0.PSR[583].R             /* INTC Priority Select Register */
#define INTC_0_PSR584        INTC_0.PSR[584].R             /* INTC Priority Select Register */
#define INTC_0_PSR585        INTC_0.PSR[585].R             /* INTC Priority Select Register */
#define INTC_0_PSR586        INTC_0.PSR[586].R             /* INTC Priority Select Register */
#define INTC_0_PSR587        INTC_0.PSR[587].R             /* INTC Priority Select Register */
#define INTC_0_PSR588        INTC_0.PSR[588].R             /* INTC Priority Select Register */
#define INTC_0_PSR589        INTC_0.PSR[589].R             /* INTC Priority Select Register */
#define INTC_0_PSR590        INTC_0.PSR[590].R             /* INTC Priority Select Register */
#define INTC_0_PSR591        INTC_0.PSR[591].R             /* INTC Priority Select Register */
#define INTC_0_PSR592        INTC_0.PSR[592].R             /* INTC Priority Select Register */
#define INTC_0_PSR593        INTC_0.PSR[593].R             /* INTC Priority Select Register */
#define INTC_0_PSR594        INTC_0.PSR[594].R             /* INTC Priority Select Register */
#define INTC_0_PSR595        INTC_0.PSR[595].R             /* INTC Priority Select Register */
#define INTC_0_PSR596        INTC_0.PSR[596].R             /* INTC Priority Select Register */
#define INTC_0_PSR597        INTC_0.PSR[597].R             /* INTC Priority Select Register */
#define INTC_0_PSR598        INTC_0.PSR[598].R             /* INTC Priority Select Register */
#define INTC_0_PSR599        INTC_0.PSR[599].R             /* INTC Priority Select Register */
#define INTC_0_PSR600        INTC_0.PSR[600].R             /* INTC Priority Select Register */
#define INTC_0_PSR601        INTC_0.PSR[601].R             /* INTC Priority Select Register */
#define INTC_0_PSR602        INTC_0.PSR[602].R             /* INTC Priority Select Register */
#define INTC_0_PSR603        INTC_0.PSR[603].R             /* INTC Priority Select Register */
#define INTC_0_PSR604        INTC_0.PSR[604].R             /* INTC Priority Select Register */
#define INTC_0_PSR605        INTC_0.PSR[605].R             /* INTC Priority Select Register */
#define INTC_0_PSR606        INTC_0.PSR[606].R             /* INTC Priority Select Register */
#define INTC_0_PSR607        INTC_0.PSR[607].R             /* INTC Priority Select Register */
#define INTC_0_PSR608        INTC_0.PSR[608].R             /* INTC Priority Select Register */
#define INTC_0_PSR609        INTC_0.PSR[609].R             /* INTC Priority Select Register */
#define INTC_0_PSR610        INTC_0.PSR[610].R             /* INTC Priority Select Register */
#define INTC_0_PSR611        INTC_0.PSR[611].R             /* INTC Priority Select Register */
#define INTC_0_PSR612        INTC_0.PSR[612].R             /* INTC Priority Select Register */
#define INTC_0_PSR613        INTC_0.PSR[613].R             /* INTC Priority Select Register */
#define INTC_0_PSR614        INTC_0.PSR[614].R             /* INTC Priority Select Register */
#define INTC_0_PSR615        INTC_0.PSR[615].R             /* INTC Priority Select Register */
#define INTC_0_PSR616        INTC_0.PSR[616].R             /* INTC Priority Select Register */
#define INTC_0_PSR617        INTC_0.PSR[617].R             /* INTC Priority Select Register */
#define INTC_0_PSR618        INTC_0.PSR[618].R             /* INTC Priority Select Register */
#define INTC_0_PSR619        INTC_0.PSR[619].R             /* INTC Priority Select Register */
#define INTC_0_PSR620        INTC_0.PSR[620].R             /* INTC Priority Select Register */
#define INTC_0_PSR621        INTC_0.PSR[621].R             /* INTC Priority Select Register */
#define INTC_0_PSR622        INTC_0.PSR[622].R             /* INTC Priority Select Register */
#define INTC_0_PSR623        INTC_0.PSR[623].R             /* INTC Priority Select Register */
#define INTC_0_PSR624        INTC_0.PSR[624].R             /* INTC Priority Select Register */
#define INTC_0_PSR625        INTC_0.PSR[625].R             /* INTC Priority Select Register */
#define INTC_0_PSR626        INTC_0.PSR[626].R             /* INTC Priority Select Register */
#define INTC_0_PSR627        INTC_0.PSR[627].R             /* INTC Priority Select Register */
#define INTC_0_PSR628        INTC_0.PSR[628].R             /* INTC Priority Select Register */
#define INTC_0_PSR629        INTC_0.PSR[629].R             /* INTC Priority Select Register */
#define INTC_0_PSR630        INTC_0.PSR[630].R             /* INTC Priority Select Register */
#define INTC_0_PSR631        INTC_0.PSR[631].R             /* INTC Priority Select Register */
#define INTC_0_PSR632        INTC_0.PSR[632].R             /* INTC Priority Select Register */
#define INTC_0_PSR633        INTC_0.PSR[633].R             /* INTC Priority Select Register */
#define INTC_0_PSR634        INTC_0.PSR[634].R             /* INTC Priority Select Register */
#define INTC_0_PSR635        INTC_0.PSR[635].R             /* INTC Priority Select Register */
#define INTC_0_PSR636        INTC_0.PSR[636].R             /* INTC Priority Select Register */
#define INTC_0_PSR637        INTC_0.PSR[637].R             /* INTC Priority Select Register */
#define INTC_0_PSR638        INTC_0.PSR[638].R             /* INTC Priority Select Register */
#define INTC_0_PSR639        INTC_0.PSR[639].R             /* INTC Priority Select Register */
#define INTC_0_PSR640        INTC_0.PSR[640].R             /* INTC Priority Select Register */
#define INTC_0_PSR641        INTC_0.PSR[641].R             /* INTC Priority Select Register */
#define INTC_0_PSR642        INTC_0.PSR[642].R             /* INTC Priority Select Register */
#define INTC_0_PSR643        INTC_0.PSR[643].R             /* INTC Priority Select Register */
#define INTC_0_PSR644        INTC_0.PSR[644].R             /* INTC Priority Select Register */
#define INTC_0_PSR645        INTC_0.PSR[645].R             /* INTC Priority Select Register */
#define INTC_0_PSR646        INTC_0.PSR[646].R             /* INTC Priority Select Register */
#define INTC_0_PSR647        INTC_0.PSR[647].R             /* INTC Priority Select Register */
#define INTC_0_PSR648        INTC_0.PSR[648].R             /* INTC Priority Select Register */
#define INTC_0_PSR649        INTC_0.PSR[649].R             /* INTC Priority Select Register */
#define INTC_0_PSR650        INTC_0.PSR[650].R             /* INTC Priority Select Register */
#define INTC_0_PSR651        INTC_0.PSR[651].R             /* INTC Priority Select Register */
#define INTC_0_PSR652        INTC_0.PSR[652].R             /* INTC Priority Select Register */
#define INTC_0_PSR653        INTC_0.PSR[653].R             /* INTC Priority Select Register */
#define INTC_0_PSR654        INTC_0.PSR[654].R             /* INTC Priority Select Register */
#define INTC_0_PSR655        INTC_0.PSR[655].R             /* INTC Priority Select Register */
#define INTC_0_PSR656        INTC_0.PSR[656].R             /* INTC Priority Select Register */
#define INTC_0_PSR657        INTC_0.PSR[657].R             /* INTC Priority Select Register */
#define INTC_0_PSR658        INTC_0.PSR[658].R             /* INTC Priority Select Register */
#define INTC_0_PSR659        INTC_0.PSR[659].R             /* INTC Priority Select Register */
#define INTC_0_PSR660        INTC_0.PSR[660].R             /* INTC Priority Select Register */
#define INTC_0_PSR661        INTC_0.PSR[661].R             /* INTC Priority Select Register */
#define INTC_0_PSR662        INTC_0.PSR[662].R             /* INTC Priority Select Register */
#define INTC_0_PSR663        INTC_0.PSR[663].R             /* INTC Priority Select Register */
#define INTC_0_PSR664        INTC_0.PSR[664].R             /* INTC Priority Select Register */
#define INTC_0_PSR665        INTC_0.PSR[665].R             /* INTC Priority Select Register */
#define INTC_0_PSR666        INTC_0.PSR[666].R             /* INTC Priority Select Register */
#define INTC_0_PSR667        INTC_0.PSR[667].R             /* INTC Priority Select Register */
#define INTC_0_PSR668        INTC_0.PSR[668].R             /* INTC Priority Select Register */
#define INTC_0_PSR669        INTC_0.PSR[669].R             /* INTC Priority Select Register */
#define INTC_0_PSR670        INTC_0.PSR[670].R             /* INTC Priority Select Register */
#define INTC_0_PSR671        INTC_0.PSR[671].R             /* INTC Priority Select Register */
#define INTC_0_PSR672        INTC_0.PSR[672].R             /* INTC Priority Select Register */
#define INTC_0_PSR673        INTC_0.PSR[673].R             /* INTC Priority Select Register */
#define INTC_0_PSR674        INTC_0.PSR[674].R             /* INTC Priority Select Register */
#define INTC_0_PSR675        INTC_0.PSR[675].R             /* INTC Priority Select Register */
#define INTC_0_PSR676        INTC_0.PSR[676].R             /* INTC Priority Select Register */
#define INTC_0_PSR677        INTC_0.PSR[677].R             /* INTC Priority Select Register */
#define INTC_0_PSR678        INTC_0.PSR[678].R             /* INTC Priority Select Register */
#define INTC_0_PSR679        INTC_0.PSR[679].R             /* INTC Priority Select Register */
#define INTC_0_PSR680        INTC_0.PSR[680].R             /* INTC Priority Select Register */
#define INTC_0_PSR681        INTC_0.PSR[681].R             /* INTC Priority Select Register */
#define INTC_0_PSR682        INTC_0.PSR[682].R             /* INTC Priority Select Register */
#define INTC_0_PSR683        INTC_0.PSR[683].R             /* INTC Priority Select Register */
#define INTC_0_PSR684        INTC_0.PSR[684].R             /* INTC Priority Select Register */
#define INTC_0_PSR685        INTC_0.PSR[685].R             /* INTC Priority Select Register */
#define INTC_0_PSR686        INTC_0.PSR[686].R             /* INTC Priority Select Register */
#define INTC_0_PSR687        INTC_0.PSR[687].R             /* INTC Priority Select Register */
#define INTC_0_PSR688        INTC_0.PSR[688].R             /* INTC Priority Select Register */
#define INTC_0_PSR689        INTC_0.PSR[689].R             /* INTC Priority Select Register */
#define INTC_0_PSR690        INTC_0.PSR[690].R             /* INTC Priority Select Register */
#define INTC_0_PSR691        INTC_0.PSR[691].R             /* INTC Priority Select Register */
#define INTC_0_PSR692        INTC_0.PSR[692].R             /* INTC Priority Select Register */
#define INTC_0_PSR693        INTC_0.PSR[693].R             /* INTC Priority Select Register */
#define INTC_0_PSR694        INTC_0.PSR[694].R             /* INTC Priority Select Register */
#define INTC_0_PSR695        INTC_0.PSR[695].R             /* INTC Priority Select Register */
#define INTC_0_PSR696        INTC_0.PSR[696].R             /* INTC Priority Select Register */
#define INTC_0_PSR697        INTC_0.PSR[697].R             /* INTC Priority Select Register */
#define INTC_0_PSR698        INTC_0.PSR[698].R             /* INTC Priority Select Register */
#define INTC_0_PSR699        INTC_0.PSR[699].R             /* INTC Priority Select Register */
#define INTC_0_PSR700        INTC_0.PSR[700].R             /* INTC Priority Select Register */
#define INTC_0_PSR701        INTC_0.PSR[701].R             /* INTC Priority Select Register */
#define INTC_0_PSR702        INTC_0.PSR[702].R             /* INTC Priority Select Register */
#define INTC_0_PSR703        INTC_0.PSR[703].R             /* INTC Priority Select Register */
#define INTC_0_PSR704        INTC_0.PSR[704].R             /* INTC Priority Select Register */
#define INTC_0_PSR705        INTC_0.PSR[705].R             /* INTC Priority Select Register */
#define INTC_0_PSR706        INTC_0.PSR[706].R             /* INTC Priority Select Register */
#define INTC_0_PSR707        INTC_0.PSR[707].R             /* INTC Priority Select Register */
#define INTC_0_PSR708        INTC_0.PSR[708].R             /* INTC Priority Select Register */
#define INTC_0_PSR709        INTC_0.PSR[709].R             /* INTC Priority Select Register */
#define INTC_0_PSR710        INTC_0.PSR[710].R             /* INTC Priority Select Register */
#define INTC_0_PSR711        INTC_0.PSR[711].R             /* INTC Priority Select Register */
#define INTC_0_PSR712        INTC_0.PSR[712].R             /* INTC Priority Select Register */
#define INTC_0_PSR713        INTC_0.PSR[713].R             /* INTC Priority Select Register */
#define INTC_0_PSR714        INTC_0.PSR[714].R             /* INTC Priority Select Register */
#define INTC_0_PSR715        INTC_0.PSR[715].R             /* INTC Priority Select Register */
#define INTC_0_PSR716        INTC_0.PSR[716].R             /* INTC Priority Select Register */
#define INTC_0_PSR717        INTC_0.PSR[717].R             /* INTC Priority Select Register */
#define INTC_0_PSR718        INTC_0.PSR[718].R             /* INTC Priority Select Register */
#define INTC_0_PSR719        INTC_0.PSR[719].R             /* INTC Priority Select Register */
#define INTC_0_PSR720        INTC_0.PSR[720].R             /* INTC Priority Select Register */
#define INTC_0_PSR721        INTC_0.PSR[721].R             /* INTC Priority Select Register */
#define INTC_0_PSR722        INTC_0.PSR[722].R             /* INTC Priority Select Register */
#define INTC_0_PSR723        INTC_0.PSR[723].R             /* INTC Priority Select Register */
#define INTC_0_PSR724        INTC_0.PSR[724].R             /* INTC Priority Select Register */
#define INTC_0_PSR725        INTC_0.PSR[725].R             /* INTC Priority Select Register */
#define INTC_0_PSR726        INTC_0.PSR[726].R             /* INTC Priority Select Register */
#define INTC_0_PSR727        INTC_0.PSR[727].R             /* INTC Priority Select Register */
#define INTC_0_PSR728        INTC_0.PSR[728].R             /* INTC Priority Select Register */
#define INTC_0_PSR729        INTC_0.PSR[729].R             /* INTC Priority Select Register */
#define INTC_0_PSR730        INTC_0.PSR[730].R             /* INTC Priority Select Register */
#define INTC_0_PSR731        INTC_0.PSR[731].R             /* INTC Priority Select Register */
#define INTC_0_PSR732        INTC_0.PSR[732].R             /* INTC Priority Select Register */
#define INTC_0_PSR733        INTC_0.PSR[733].R             /* INTC Priority Select Register */
#define INTC_0_PSR734        INTC_0.PSR[734].R             /* INTC Priority Select Register */
#define INTC_0_PSR735        INTC_0.PSR[735].R             /* INTC Priority Select Register */
#define INTC_0_PSR736        INTC_0.PSR[736].R             /* INTC Priority Select Register */
#define INTC_0_PSR737        INTC_0.PSR[737].R             /* INTC Priority Select Register */
#define INTC_0_PSR738        INTC_0.PSR[738].R             /* INTC Priority Select Register */
#define INTC_0_PSR739        INTC_0.PSR[739].R             /* INTC Priority Select Register */
#define INTC_0_PSR740        INTC_0.PSR[740].R             /* INTC Priority Select Register */
#define INTC_0_PSR741        INTC_0.PSR[741].R             /* INTC Priority Select Register */
#define INTC_0_PSR742        INTC_0.PSR[742].R             /* INTC Priority Select Register */
#define INTC_0_PSR743        INTC_0.PSR[743].R             /* INTC Priority Select Register */
#define INTC_0_PSR744        INTC_0.PSR[744].R             /* INTC Priority Select Register */
#define INTC_0_PSR745        INTC_0.PSR[745].R             /* INTC Priority Select Register */
#define INTC_0_PSR746        INTC_0.PSR[746].R             /* INTC Priority Select Register */
#define INTC_0_PSR747        INTC_0.PSR[747].R             /* INTC Priority Select Register */
#define INTC_0_PSR748        INTC_0.PSR[748].R             /* INTC Priority Select Register */
#define INTC_0_PSR749        INTC_0.PSR[749].R             /* INTC Priority Select Register */
#define INTC_0_PSR750        INTC_0.PSR[750].R             /* INTC Priority Select Register */
#define INTC_0_PSR751        INTC_0.PSR[751].R             /* INTC Priority Select Register */
#define INTC_0_PSR752        INTC_0.PSR[752].R             /* INTC Priority Select Register */
#define INTC_0_PSR753        INTC_0.PSR[753].R             /* INTC Priority Select Register */
#define INTC_0_PSR754        INTC_0.PSR[754].R             /* INTC Priority Select Register */
#define INTC_0_PSR755        INTC_0.PSR[755].R             /* INTC Priority Select Register */
#define INTC_0_PSR756        INTC_0.PSR[756].R             /* INTC Priority Select Register */
#define INTC_0_PSR757        INTC_0.PSR[757].R             /* INTC Priority Select Register */
#define INTC_0_PSR758        INTC_0.PSR[758].R             /* INTC Priority Select Register */
#define INTC_0_PSR759        INTC_0.PSR[759].R             /* INTC Priority Select Register */
#define INTC_0_PSR760        INTC_0.PSR[760].R             /* INTC Priority Select Register */
#define INTC_0_PSR761        INTC_0.PSR[761].R             /* INTC Priority Select Register */
#define INTC_0_PSR762        INTC_0.PSR[762].R             /* INTC Priority Select Register */
#define INTC_0_PSR763        INTC_0.PSR[763].R             /* INTC Priority Select Register */
#define INTC_0_PSR764        INTC_0.PSR[764].R             /* INTC Priority Select Register */
#define INTC_0_PSR765        INTC_0.PSR[765].R             /* INTC Priority Select Register */
#define INTC_0_PSR766        INTC_0.PSR[766].R             /* INTC Priority Select Register */
#define INTC_0_PSR767        INTC_0.PSR[767].R             /* INTC Priority Select Register */
#define INTC_0_PSR768        INTC_0.PSR[768].R             /* INTC Priority Select Register */
#define INTC_0_PSR769        INTC_0.PSR[769].R             /* INTC Priority Select Register */
#define INTC_0_PSR770        INTC_0.PSR[770].R             /* INTC Priority Select Register */
#define INTC_0_PSR771        INTC_0.PSR[771].R             /* INTC Priority Select Register */
#define INTC_0_PSR772        INTC_0.PSR[772].R             /* INTC Priority Select Register */
#define INTC_0_PSR773        INTC_0.PSR[773].R             /* INTC Priority Select Register */
#define INTC_0_PSR774        INTC_0.PSR[774].R             /* INTC Priority Select Register */
#define INTC_0_PSR775        INTC_0.PSR[775].R             /* INTC Priority Select Register */
#define INTC_0_PSR776        INTC_0.PSR[776].R             /* INTC Priority Select Register */
#define INTC_0_PSR777        INTC_0.PSR[777].R             /* INTC Priority Select Register */
#define INTC_0_PSR778        INTC_0.PSR[778].R             /* INTC Priority Select Register */
#define INTC_0_PSR779        INTC_0.PSR[779].R             /* INTC Priority Select Register */
#define INTC_0_PSR780        INTC_0.PSR[780].R             /* INTC Priority Select Register */
#define INTC_0_PSR781        INTC_0.PSR[781].R             /* INTC Priority Select Register */
#define INTC_0_PSR782        INTC_0.PSR[782].R             /* INTC Priority Select Register */
#define INTC_0_PSR783        INTC_0.PSR[783].R             /* INTC Priority Select Register */
#define INTC_0_PSR784        INTC_0.PSR[784].R             /* INTC Priority Select Register */
#define INTC_0_PSR785        INTC_0.PSR[785].R             /* INTC Priority Select Register */
#define INTC_0_PSR786        INTC_0.PSR[786].R             /* INTC Priority Select Register */
#define INTC_0_PSR787        INTC_0.PSR[787].R             /* INTC Priority Select Register */
#define INTC_0_PSR788        INTC_0.PSR[788].R             /* INTC Priority Select Register */
#define INTC_0_PSR789        INTC_0.PSR[789].R             /* INTC Priority Select Register */
#define INTC_0_PSR790        INTC_0.PSR[790].R             /* INTC Priority Select Register */
#define INTC_0_PSR791        INTC_0.PSR[791].R             /* INTC Priority Select Register */
#define INTC_0_PSR792        INTC_0.PSR[792].R             /* INTC Priority Select Register */
#define INTC_0_PSR793        INTC_0.PSR[793].R             /* INTC Priority Select Register */
#define INTC_0_PSR794        INTC_0.PSR[794].R             /* INTC Priority Select Register */
#define INTC_0_PSR795        INTC_0.PSR[795].R             /* INTC Priority Select Register */
#define INTC_0_PSR796        INTC_0.PSR[796].R             /* INTC Priority Select Register */
#define INTC_0_PSR797        INTC_0.PSR[797].R             /* INTC Priority Select Register */
#define INTC_0_PSR798        INTC_0.PSR[798].R             /* INTC Priority Select Register */
#define INTC_0_PSR799        INTC_0.PSR[799].R             /* INTC Priority Select Register */
#define INTC_0_PSR800        INTC_0.PSR[800].R             /* INTC Priority Select Register */
#define INTC_0_PSR801        INTC_0.PSR[801].R             /* INTC Priority Select Register */
#define INTC_0_PSR802        INTC_0.PSR[802].R             /* INTC Priority Select Register */
#define INTC_0_PSR803        INTC_0.PSR[803].R             /* INTC Priority Select Register */
#define INTC_0_PSR804        INTC_0.PSR[804].R             /* INTC Priority Select Register */
#define INTC_0_PSR805        INTC_0.PSR[805].R             /* INTC Priority Select Register */
#define INTC_0_PSR806        INTC_0.PSR[806].R             /* INTC Priority Select Register */
#define INTC_0_PSR807        INTC_0.PSR[807].R             /* INTC Priority Select Register */
#define INTC_0_PSR808        INTC_0.PSR[808].R             /* INTC Priority Select Register */
#define INTC_0_PSR809        INTC_0.PSR[809].R             /* INTC Priority Select Register */
#define INTC_0_PSR810        INTC_0.PSR[810].R             /* INTC Priority Select Register */
#define INTC_0_PSR811        INTC_0.PSR[811].R             /* INTC Priority Select Register */
#define INTC_0_PSR812        INTC_0.PSR[812].R             /* INTC Priority Select Register */
#define INTC_0_PSR813        INTC_0.PSR[813].R             /* INTC Priority Select Register */
#define INTC_0_PSR814        INTC_0.PSR[814].R             /* INTC Priority Select Register */
#define INTC_0_PSR815        INTC_0.PSR[815].R             /* INTC Priority Select Register */
#define INTC_0_PSR816        INTC_0.PSR[816].R             /* INTC Priority Select Register */
#define INTC_0_PSR817        INTC_0.PSR[817].R             /* INTC Priority Select Register */
#define INTC_0_PSR818        INTC_0.PSR[818].R             /* INTC Priority Select Register */
#define INTC_0_PSR819        INTC_0.PSR[819].R             /* INTC Priority Select Register */
#define INTC_0_PSR820        INTC_0.PSR[820].R             /* INTC Priority Select Register */
#define INTC_0_PSR821        INTC_0.PSR[821].R             /* INTC Priority Select Register */
#define INTC_0_PSR822        INTC_0.PSR[822].R             /* INTC Priority Select Register */
#define INTC_0_PSR823        INTC_0.PSR[823].R             /* INTC Priority Select Register */
#define INTC_0_PSR824        INTC_0.PSR[824].R             /* INTC Priority Select Register */
#define INTC_0_PSR825        INTC_0.PSR[825].R             /* INTC Priority Select Register */
#define INTC_0_PSR826        INTC_0.PSR[826].R             /* INTC Priority Select Register */
#define INTC_0_PSR827        INTC_0.PSR[827].R             /* INTC Priority Select Register */
#define INTC_0_PSR828        INTC_0.PSR[828].R             /* INTC Priority Select Register */
#define INTC_0_PSR829        INTC_0.PSR[829].R             /* INTC Priority Select Register */
#define INTC_0_PSR830        INTC_0.PSR[830].R             /* INTC Priority Select Register */
#define INTC_0_PSR831        INTC_0.PSR[831].R             /* INTC Priority Select Register */
#define INTC_0_PSR832        INTC_0.PSR[832].R             /* INTC Priority Select Register */
#define INTC_0_PSR833        INTC_0.PSR[833].R             /* INTC Priority Select Register */
#define INTC_0_PSR834        INTC_0.PSR[834].R             /* INTC Priority Select Register */
#define INTC_0_PSR835        INTC_0.PSR[835].R             /* INTC Priority Select Register */
#define INTC_0_PSR836        INTC_0.PSR[836].R             /* INTC Priority Select Register */
#define INTC_0_PSR837        INTC_0.PSR[837].R             /* INTC Priority Select Register */
#define INTC_0_PSR838        INTC_0.PSR[838].R             /* INTC Priority Select Register */
#define INTC_0_PSR839        INTC_0.PSR[839].R             /* INTC Priority Select Register */
#define INTC_0_PSR840        INTC_0.PSR[840].R             /* INTC Priority Select Register */
#define INTC_0_PSR841        INTC_0.PSR[841].R             /* INTC Priority Select Register */
#define INTC_0_PSR842        INTC_0.PSR[842].R             /* INTC Priority Select Register */
#define INTC_0_PSR843        INTC_0.PSR[843].R             /* INTC Priority Select Register */
#define INTC_0_PSR844        INTC_0.PSR[844].R             /* INTC Priority Select Register */
#define INTC_0_PSR845        INTC_0.PSR[845].R             /* INTC Priority Select Register */
#define INTC_0_PSR846        INTC_0.PSR[846].R             /* INTC Priority Select Register */
#define INTC_0_PSR847        INTC_0.PSR[847].R             /* INTC Priority Select Register */
#define INTC_0_PSR848        INTC_0.PSR[848].R             /* INTC Priority Select Register */
#define INTC_0_PSR849        INTC_0.PSR[849].R             /* INTC Priority Select Register */
#define INTC_0_PSR850        INTC_0.PSR[850].R             /* INTC Priority Select Register */
#define INTC_0_PSR851        INTC_0.PSR[851].R             /* INTC Priority Select Register */
#define INTC_0_PSR852        INTC_0.PSR[852].R             /* INTC Priority Select Register */
#define INTC_0_PSR853        INTC_0.PSR[853].R             /* INTC Priority Select Register */
#define INTC_0_PSR854        INTC_0.PSR[854].R             /* INTC Priority Select Register */
#define INTC_0_PSR855        INTC_0.PSR[855].R             /* INTC Priority Select Register */
#define INTC_0_PSR856        INTC_0.PSR[856].R             /* INTC Priority Select Register */
#define INTC_0_PSR857        INTC_0.PSR[857].R             /* INTC Priority Select Register */
#define INTC_0_PSR858        INTC_0.PSR[858].R             /* INTC Priority Select Register */
#define INTC_0_PSR859        INTC_0.PSR[859].R             /* INTC Priority Select Register */
#define INTC_0_PSR860        INTC_0.PSR[860].R             /* INTC Priority Select Register */
#define INTC_0_PSR861        INTC_0.PSR[861].R             /* INTC Priority Select Register */
#define INTC_0_PSR862        INTC_0.PSR[862].R             /* INTC Priority Select Register */
#define INTC_0_PSR863        INTC_0.PSR[863].R             /* INTC Priority Select Register */
#define INTC_0_PSR864        INTC_0.PSR[864].R             /* INTC Priority Select Register */
#define INTC_0_PSR865        INTC_0.PSR[865].R             /* INTC Priority Select Register */
#define INTC_0_PSR866        INTC_0.PSR[866].R             /* INTC Priority Select Register */
#define INTC_0_PSR867        INTC_0.PSR[867].R             /* INTC Priority Select Register */
#define INTC_0_PSR868        INTC_0.PSR[868].R             /* INTC Priority Select Register */
#define INTC_0_PSR869        INTC_0.PSR[869].R             /* INTC Priority Select Register */
#define INTC_0_PSR870        INTC_0.PSR[870].R             /* INTC Priority Select Register */
#define INTC_0_PSR871        INTC_0.PSR[871].R             /* INTC Priority Select Register */
#define INTC_0_PSR872        INTC_0.PSR[872].R             /* INTC Priority Select Register */
#define INTC_0_PSR873        INTC_0.PSR[873].R             /* INTC Priority Select Register */
#define INTC_0_PSR874        INTC_0.PSR[874].R             /* INTC Priority Select Register */
#define INTC_0_PSR875        INTC_0.PSR[875].R             /* INTC Priority Select Register */
#define INTC_0_PSR876        INTC_0.PSR[876].R             /* INTC Priority Select Register */
#define INTC_0_PSR877        INTC_0.PSR[877].R             /* INTC Priority Select Register */
#define INTC_0_PSR878        INTC_0.PSR[878].R             /* INTC Priority Select Register */
#define INTC_0_PSR879        INTC_0.PSR[879].R             /* INTC Priority Select Register */
#define INTC_0_PSR880        INTC_0.PSR[880].R             /* INTC Priority Select Register */
#define INTC_0_PSR881        INTC_0.PSR[881].R             /* INTC Priority Select Register */
#define INTC_0_PSR882        INTC_0.PSR[882].R             /* INTC Priority Select Register */
#define INTC_0_PSR883        INTC_0.PSR[883].R             /* INTC Priority Select Register */
#define INTC_0_PSR884        INTC_0.PSR[884].R             /* INTC Priority Select Register */
#define INTC_0_PSR885        INTC_0.PSR[885].R             /* INTC Priority Select Register */
#define INTC_0_PSR886        INTC_0.PSR[886].R             /* INTC Priority Select Register */
#define INTC_0_PSR887        INTC_0.PSR[887].R             /* INTC Priority Select Register */
#define INTC_0_PSR888        INTC_0.PSR[888].R             /* INTC Priority Select Register */
#define INTC_0_PSR889        INTC_0.PSR[889].R             /* INTC Priority Select Register */
#define INTC_0_PSR890        INTC_0.PSR[890].R             /* INTC Priority Select Register */
#define INTC_0_PSR891        INTC_0.PSR[891].R             /* INTC Priority Select Register */
#define INTC_0_PSR892        INTC_0.PSR[892].R             /* INTC Priority Select Register */
#define INTC_0_PSR893        INTC_0.PSR[893].R             /* INTC Priority Select Register */
#define INTC_0_PSR894        INTC_0.PSR[894].R             /* INTC Priority Select Register */
#define INTC_0_PSR895        INTC_0.PSR[895].R             /* INTC Priority Select Register */
#define INTC_0_PSR896        INTC_0.PSR[896].R             /* INTC Priority Select Register */
#define INTC_0_PSR897        INTC_0.PSR[897].R             /* INTC Priority Select Register */
#define INTC_0_PSR898        INTC_0.PSR[898].R             /* INTC Priority Select Register */
#define INTC_0_PSR899        INTC_0.PSR[899].R             /* INTC Priority Select Register */
#define INTC_0_PSR900        INTC_0.PSR[900].R             /* INTC Priority Select Register */
#define INTC_0_PSR901        INTC_0.PSR[901].R             /* INTC Priority Select Register */
#define INTC_0_PSR902        INTC_0.PSR[902].R             /* INTC Priority Select Register */
#define INTC_0_PSR903        INTC_0.PSR[903].R             /* INTC Priority Select Register */
#define INTC_0_PSR904        INTC_0.PSR[904].R             /* INTC Priority Select Register */
#define INTC_0_PSR905        INTC_0.PSR[905].R             /* INTC Priority Select Register */
#define INTC_0_PSR906        INTC_0.PSR[906].R             /* INTC Priority Select Register */
#define INTC_0_PSR907        INTC_0.PSR[907].R             /* INTC Priority Select Register */
#define INTC_0_PSR908        INTC_0.PSR[908].R             /* INTC Priority Select Register */
#define INTC_0_PSR909        INTC_0.PSR[909].R             /* INTC Priority Select Register */
#define INTC_0_PSR910        INTC_0.PSR[910].R             /* INTC Priority Select Register */
#define INTC_0_PSR911        INTC_0.PSR[911].R             /* INTC Priority Select Register */
#define INTC_0_PSR912        INTC_0.PSR[912].R             /* INTC Priority Select Register */
#define INTC_0_PSR913        INTC_0.PSR[913].R             /* INTC Priority Select Register */
#define INTC_0_PSR914        INTC_0.PSR[914].R             /* INTC Priority Select Register */
#define INTC_0_PSR915        INTC_0.PSR[915].R             /* INTC Priority Select Register */
#define INTC_0_PSR916        INTC_0.PSR[916].R             /* INTC Priority Select Register */
#define INTC_0_PSR917        INTC_0.PSR[917].R             /* INTC Priority Select Register */
#define INTC_0_PSR918        INTC_0.PSR[918].R             /* INTC Priority Select Register */
#define INTC_0_PSR919        INTC_0.PSR[919].R             /* INTC Priority Select Register */
#define INTC_0_PSR920        INTC_0.PSR[920].R             /* INTC Priority Select Register */
#define INTC_0_PSR921        INTC_0.PSR[921].R             /* INTC Priority Select Register */
#define INTC_0_PSR922        INTC_0.PSR[922].R             /* INTC Priority Select Register */
#define INTC_0_PSR923        INTC_0.PSR[923].R             /* INTC Priority Select Register */
#define INTC_0_PSR924        INTC_0.PSR[924].R             /* INTC Priority Select Register */
#define INTC_0_PSR925        INTC_0.PSR[925].R             /* INTC Priority Select Register */
#define INTC_0_PSR926        INTC_0.PSR[926].R             /* INTC Priority Select Register */
#define INTC_0_PSR927        INTC_0.PSR[927].R             /* INTC Priority Select Register */
#define INTC_0_PSR928        INTC_0.PSR[928].R             /* INTC Priority Select Register */
#define INTC_0_PSR929        INTC_0.PSR[929].R             /* INTC Priority Select Register */
#define INTC_0_PSR930        INTC_0.PSR[930].R             /* INTC Priority Select Register */
#define INTC_0_PSR931        INTC_0.PSR[931].R             /* INTC Priority Select Register */
#define INTC_0_PSR932        INTC_0.PSR[932].R             /* INTC Priority Select Register */
#define INTC_0_PSR933        INTC_0.PSR[933].R             /* INTC Priority Select Register */
#define INTC_0_PSR934        INTC_0.PSR[934].R             /* INTC Priority Select Register */
#define INTC_0_PSR935        INTC_0.PSR[935].R             /* INTC Priority Select Register */
#define INTC_0_PSR936        INTC_0.PSR[936].R             /* INTC Priority Select Register */
#define INTC_0_PSR937        INTC_0.PSR[937].R             /* INTC Priority Select Register */
#define INTC_0_PSR938        INTC_0.PSR[938].R             /* INTC Priority Select Register */
#define INTC_0_PSR939        INTC_0.PSR[939].R             /* INTC Priority Select Register */
#define INTC_0_PSR940        INTC_0.PSR[940].R             /* INTC Priority Select Register */
#define INTC_0_PSR941        INTC_0.PSR[941].R             /* INTC Priority Select Register */
#define INTC_0_PSR942        INTC_0.PSR[942].R             /* INTC Priority Select Register */
#define INTC_0_PSR943        INTC_0.PSR[943].R             /* INTC Priority Select Register */
#define INTC_0_PSR944        INTC_0.PSR[944].R             /* INTC Priority Select Register */
#define INTC_0_PSR945        INTC_0.PSR[945].R             /* INTC Priority Select Register */
#define INTC_0_PSR946        INTC_0.PSR[946].R             /* INTC Priority Select Register */
#define INTC_0_PSR947        INTC_0.PSR[947].R             /* INTC Priority Select Register */
#define INTC_0_PSR948        INTC_0.PSR[948].R             /* INTC Priority Select Register */
#define INTC_0_PSR949        INTC_0.PSR[949].R             /* INTC Priority Select Register */
#define INTC_0_PSR950        INTC_0.PSR[950].R             /* INTC Priority Select Register */
#define INTC_0_PSR951        INTC_0.PSR[951].R             /* INTC Priority Select Register */
#define INTC_0_PSR952        INTC_0.PSR[952].R             /* INTC Priority Select Register */
#define INTC_0_PSR953        INTC_0.PSR[953].R             /* INTC Priority Select Register */
#define INTC_0_PSR954        INTC_0.PSR[954].R             /* INTC Priority Select Register */
#define INTC_0_PSR955        INTC_0.PSR[955].R             /* INTC Priority Select Register */
#define INTC_0_PSR956        INTC_0.PSR[956].R             /* INTC Priority Select Register */
#define INTC_0_PSR957        INTC_0.PSR[957].R             /* INTC Priority Select Register */
#define INTC_0_PSR958        INTC_0.PSR[958].R             /* INTC Priority Select Register */
#define INTC_0_PSR959        INTC_0.PSR[959].R             /* INTC Priority Select Register */
#define INTC_0_PSR960        INTC_0.PSR[960].R             /* INTC Priority Select Register */
#define INTC_0_PSR961        INTC_0.PSR[961].R             /* INTC Priority Select Register */
#define INTC_0_PSR962        INTC_0.PSR[962].R             /* INTC Priority Select Register */
#define INTC_0_PSR963        INTC_0.PSR[963].R             /* INTC Priority Select Register */
#define INTC_0_PSR964        INTC_0.PSR[964].R             /* INTC Priority Select Register */
#define INTC_0_PSR965        INTC_0.PSR[965].R             /* INTC Priority Select Register */
#define INTC_0_PSR966        INTC_0.PSR[966].R             /* INTC Priority Select Register */
#define INTC_0_PSR967        INTC_0.PSR[967].R             /* INTC Priority Select Register */
#define INTC_0_PSR968        INTC_0.PSR[968].R             /* INTC Priority Select Register */
#define INTC_0_PSR969        INTC_0.PSR[969].R             /* INTC Priority Select Register */
#define INTC_0_PSR970        INTC_0.PSR[970].R             /* INTC Priority Select Register */
#define INTC_0_PSR971        INTC_0.PSR[971].R             /* INTC Priority Select Register */
#define INTC_0_PSR972        INTC_0.PSR[972].R             /* INTC Priority Select Register */
#define INTC_0_PSR973        INTC_0.PSR[973].R             /* INTC Priority Select Register */
#define INTC_0_PSR974        INTC_0.PSR[974].R             /* INTC Priority Select Register */
#define INTC_0_PSR975        INTC_0.PSR[975].R             /* INTC Priority Select Register */
#define INTC_0_PSR976        INTC_0.PSR[976].R             /* INTC Priority Select Register */
#define INTC_0_PSR977        INTC_0.PSR[977].R             /* INTC Priority Select Register */
#define INTC_0_PSR978        INTC_0.PSR[978].R             /* INTC Priority Select Register */
#define INTC_0_PSR979        INTC_0.PSR[979].R             /* INTC Priority Select Register */
#define INTC_0_PSR980        INTC_0.PSR[980].R             /* INTC Priority Select Register */
#define INTC_0_PSR981        INTC_0.PSR[981].R             /* INTC Priority Select Register */
#define INTC_0_PSR982        INTC_0.PSR[982].R             /* INTC Priority Select Register */
#define INTC_0_PSR983        INTC_0.PSR[983].R             /* INTC Priority Select Register */
#define INTC_0_PSR984        INTC_0.PSR[984].R             /* INTC Priority Select Register */
#define INTC_0_PSR985        INTC_0.PSR[985].R             /* INTC Priority Select Register */
#define INTC_0_PSR986        INTC_0.PSR[986].R             /* INTC Priority Select Register */
#define INTC_0_PSR987        INTC_0.PSR[987].R             /* INTC Priority Select Register */
#define INTC_0_PSR988        INTC_0.PSR[988].R             /* INTC Priority Select Register */
#define INTC_0_PSR989        INTC_0.PSR[989].R             /* INTC Priority Select Register */
#define INTC_0_PSR990        INTC_0.PSR[990].R             /* INTC Priority Select Register */
#define INTC_0_PSR991        INTC_0.PSR[991].R             /* INTC Priority Select Register */
#define INTC_0_PSR992        INTC_0.PSR[992].R             /* INTC Priority Select Register */
#define INTC_0_PSR993        INTC_0.PSR[993].R             /* INTC Priority Select Register */
#define INTC_0_PSR994        INTC_0.PSR[994].R             /* INTC Priority Select Register */
#define INTC_0_PSR995        INTC_0.PSR[995].R             /* INTC Priority Select Register */
#define INTC_0_PSR996        INTC_0.PSR[996].R             /* INTC Priority Select Register */
#define INTC_0_PSR997        INTC_0.PSR[997].R             /* INTC Priority Select Register */
#define INTC_0_PSR998        INTC_0.PSR[998].R             /* INTC Priority Select Register */
#define INTC_0_PSR999        INTC_0.PSR[999].R             /* INTC Priority Select Register */
#define INTC_0_PSR1000       INTC_0.PSR[1000].R            /* INTC Priority Select Register */
#define INTC_0_PSR1001       INTC_0.PSR[1001].R            /* INTC Priority Select Register */
#define INTC_0_PSR1002       INTC_0.PSR[1002].R            /* INTC Priority Select Register */
#define INTC_0_PSR1003       INTC_0.PSR[1003].R            /* INTC Priority Select Register */
#define INTC_0_PSR1004       INTC_0.PSR[1004].R            /* INTC Priority Select Register */
#define INTC_0_PSR1005       INTC_0.PSR[1005].R            /* INTC Priority Select Register */
#define INTC_0_PSR1006       INTC_0.PSR[1006].R            /* INTC Priority Select Register */
#define INTC_0_PSR1007       INTC_0.PSR[1007].R            /* INTC Priority Select Register */
#define INTC_0_PSR1008       INTC_0.PSR[1008].R            /* INTC Priority Select Register */
#define INTC_0_PSR1009       INTC_0.PSR[1009].R            /* INTC Priority Select Register */
#define INTC_0_PSR1010       INTC_0.PSR[1010].R            /* INTC Priority Select Register */
#define INTC_0_PSR1011       INTC_0.PSR[1011].R            /* INTC Priority Select Register */
#define INTC_0_PSR1012       INTC_0.PSR[1012].R            /* INTC Priority Select Register */
#define INTC_0_PSR1013       INTC_0.PSR[1013].R            /* INTC Priority Select Register */
#define INTC_0_PSR1014       INTC_0.PSR[1014].R            /* INTC Priority Select Register */
#define INTC_0_PSR1015       INTC_0.PSR[1015].R            /* INTC Priority Select Register */
#define INTC_0_PSR1016       INTC_0.PSR[1016].R            /* INTC Priority Select Register */
#define INTC_0_PSR1017       INTC_0.PSR[1017].R            /* INTC Priority Select Register */
#define INTC_0_PSR1018       INTC_0.PSR[1018].R            /* INTC Priority Select Register */
#define INTC_0_PSR1019       INTC_0.PSR[1019].R            /* INTC Priority Select Register */
#define INTC_0_PSR1020       INTC_0.PSR[1020].R            /* INTC Priority Select Register */
#define INTC_0_PSR1021       INTC_0.PSR[1021].R            /* INTC Priority Select Register */
#define INTC_0_PSR1022       INTC_0.PSR[1022].R            /* INTC Priority Select Register */
#define INTC_0_PSR1023       INTC_0.PSR[1023].R            /* INTC Priority Select Register */

/* IRCOSC */
#define IRCOSC_CTL           IRCOSC.CTL.R                  /* IRCOSC Control Register */

/* JDC */
#define JDC_MCR              JDC.MCR.R                     /* Module Configuration Register */
#define JDC_MSR              JDC.MSR.R                     /* Module Status Register */
#define JDC_JOUT_IPS         JDC.JOUT_IPS.R                /* JTAG Output Data Register */
#define JDC_JIN_IPS          JDC.JIN_IPS.R                 /* JTAG Input Data Register */

/* JTAGM */
#define JTAGM_MCR            JTAGM.MCR.R                   /* Module Configuration Register */
#define JTAGM_SR             JTAGM.SR.R                    /* Status Register */
#define JTAGM_DOR0           JTAGM.DOR0.R                  /* Data Out Register 0 */
#define JTAGM_DOR1           JTAGM.DOR1.R                  /* Data Out Register 1 */
#define JTAGM_DOR2           JTAGM.DOR2.R                  /* Data Out Register 2 */
#define JTAGM_DOR3           JTAGM.DOR3.R                  /* Data Out Register 3 */
#define JTAGM_RxCRC          JTAGM.RxCRC.R                 /* Receive CRC Register */
#define JTAGM_DIR0           JTAGM.DIR0.R                  /* Data Input Register 0 */
#define JTAGM_DIR1           JTAGM.DIR1.R                  /* Data Input Register 1 */

/* LFAST */
#define LFAST_0_MCR          LFAST_0.MCR.R                 /* LFAST Mode Configuration Register */
#define LFAST_0_SCR          LFAST_0.SCR.R                 /* LFAST Speed Control Register */
#define LFAST_0_COCR         LFAST_0.COCR.R                /* LFAST Correlator Control Register */
#define LFAST_0_TMCR         LFAST_0.TMCR.R                /* LFAST Test Mode Control Register */
#define LFAST_0_ALCR         LFAST_0.ALCR.R                /* LFAST Auto Loopback Control Register */
#define LFAST_0_RCDCR        LFAST_0.RCDCR.R               /* LFAST Rate Change Delay Control Register */
#define LFAST_0_SLCR         LFAST_0.SLCR.R                /* LFAST Wakeup Delay Control Register */
#define LFAST_0_ICR          LFAST_0.ICR.R                 /* LFAST ICLC Control Register */
#define LFAST_0_PICR         LFAST_0.PICR.R                /* LFAST Ping Control Register */
#define LFAST_0_RFCR         LFAST_0.RFCR.R                /* LFAST Rx FIFO CTS Control Register */
#define LFAST_0_TIER         LFAST_0.TIER.R                /* LFAST Tx Interrupt Enable Register */
#define LFAST_0_RIER         LFAST_0.RIER.R                /* LFAST Rx Interrupt Enable Register */
#define LFAST_0_RIIER        LFAST_0.RIIER.R               /* LFAST Rx ICLC Interrupt Enable Register */
#define LFAST_0_PLLCR        LFAST_0.PLLCR.R               /* LFAST PLL Control Register */
#define LFAST_0_LCR          LFAST_0.LCR.R                 /* LFAST LVDS Control Register */
#define LFAST_0_UNSTCR       LFAST_0.UNSTCR.R              /* LFAST Unsolicited Tx Control Register */
#define LFAST_0_UNSTDR0      LFAST_0.UNSTDR[0].R           /* LFAST Unsolicited Tx Data Registers */
#define LFAST_0_UNSTDR1      LFAST_0.UNSTDR[1].R           /* LFAST Unsolicited Tx Data Registers */
#define LFAST_0_UNSTDR2      LFAST_0.UNSTDR[2].R           /* LFAST Unsolicited Tx Data Registers */
#define LFAST_0_UNSTDR3      LFAST_0.UNSTDR[3].R           /* LFAST Unsolicited Tx Data Registers */
#define LFAST_0_UNSTDR4      LFAST_0.UNSTDR[4].R           /* LFAST Unsolicited Tx Data Registers */
#define LFAST_0_UNSTDR5      LFAST_0.UNSTDR[5].R           /* LFAST Unsolicited Tx Data Registers */
#define LFAST_0_UNSTDR6      LFAST_0.UNSTDR[6].R           /* LFAST Unsolicited Tx Data Registers */
#define LFAST_0_UNSTDR7      LFAST_0.UNSTDR[7].R           /* LFAST Unsolicited Tx Data Registers */
#define LFAST_0_UNSTDR8      LFAST_0.UNSTDR[8].R           /* LFAST Unsolicited Tx Data Registers */
#define LFAST_0_GSR          LFAST_0.GSR.R                 /* LFAST Global Status Register */
#define LFAST_0_PISR         LFAST_0.PISR.R                /* LFAST Ping Status Register */
#define LFAST_0_DFSR         LFAST_0.DFSR.R                /* LFAST Data Frame Status Register */
#define LFAST_0_TISR         LFAST_0.TISR.R                /* LFAST Tx Interrupt Status Register */
#define LFAST_0_RISR         LFAST_0.RISR.R                /* LFAST Rx Interrupt Status Register */
#define LFAST_0_RIISR        LFAST_0.RIISR.R               /* LFAST Rx ICLC Interrupt Status Register */
#define LFAST_0_PLLLSR       LFAST_0.PLLLSR.R              /* LFAST PLL and LVDS Status Register */
#define LFAST_0_UNSRSR       LFAST_0.UNSRSR.R              /* LFAST Unsolicited Rx Status Register */
#define LFAST_0_UNSRDR0      LFAST_0.UNSRDR[0].R           /* LFAST Unsolicited Rx Data Register */
#define LFAST_0_UNSRDR1      LFAST_0.UNSRDR[1].R           /* LFAST Unsolicited Rx Data Register */
#define LFAST_0_UNSRDR2      LFAST_0.UNSRDR[2].R           /* LFAST Unsolicited Rx Data Register */
#define LFAST_0_UNSRDR3      LFAST_0.UNSRDR[3].R           /* LFAST Unsolicited Rx Data Register */
#define LFAST_0_UNSRDR4      LFAST_0.UNSRDR[4].R           /* LFAST Unsolicited Rx Data Register */
#define LFAST_0_UNSRDR5      LFAST_0.UNSRDR[5].R           /* LFAST Unsolicited Rx Data Register */
#define LFAST_0_UNSRDR6      LFAST_0.UNSRDR[6].R           /* LFAST Unsolicited Rx Data Register */
#define LFAST_0_UNSRDR7      LFAST_0.UNSRDR[7].R           /* LFAST Unsolicited Rx Data Register */
#define LFAST_0_UNSRDR8      LFAST_0.UNSRDR[8].R           /* LFAST Unsolicited Rx Data Register */

/* LINFlexD */
#define LINFlexD_0_LINCR1    LINFlexD_0.LINCR1.R           /* LIN Control Register 1 */
#define LINFlexD_0_LINIER    LINFlexD_0.LINIER.R           /* LIN Interrupt enable register */
#define LINFlexD_0_LINSR     LINFlexD_0.LINSR.R            /* LIN Status Register */
#define LINFlexD_0_LINESR    LINFlexD_0.LINESR.R           /* LIN Error Status Register */
#define LINFlexD_0_UARTCR    LINFlexD_0.UARTCR.R           /* UART Mode Control Register */
#define LINFlexD_0_UARTSR    LINFlexD_0.UARTSR.R           /* UART Mode Status Register */
#define LINFlexD_0_LINTCSR   LINFlexD_0.LINTCSR.R          /* LIN Time-Out Control Status Register */
#define LINFlexD_0_LINOCR    LINFlexD_0.LINOCR.R           /* LIN Output Compare Register */
#define LINFlexD_0_LINTOCR   LINFlexD_0.LINTOCR.R          /* LIN Time-Out Control Register */
#define LINFlexD_0_LINFBRR   LINFlexD_0.LINFBRR.R          /* LIN Fractional Baud Rate Register */
#define LINFlexD_0_LINIBRR   LINFlexD_0.LINIBRR.R          /* LIN Integer Baud Rate Register */
#define LINFlexD_0_LINCFR    LINFlexD_0.LINCFR.R           /* LIN Checksum Field Register */
#define LINFlexD_0_LINCR2    LINFlexD_0.LINCR2.R           /* LIN Control Register 2 */
#define LINFlexD_0_BIDR      LINFlexD_0.BIDR.R             /* Buffer Identifier Register */
#define LINFlexD_0_BDRL      LINFlexD_0.BDRL.R             /* Buffer Data Register Least Significant */
#define LINFlexD_0_BDRM      LINFlexD_0.BDRM.R             /* Buffer Data Register Most Significant */
#define LINFlexD_0_IFER      LINFlexD_0.IFER.R             /* Identifier Filter Enable Register */
#define LINFlexD_0_IFMI      LINFlexD_0.IFMI.R             /* Identifier Filter Match Index */
#define LINFlexD_0_IFMR      LINFlexD_0.IFMR.R             /* Identifier Filter Mode Register */
#define LINFlexD_0_IFCR0     LINFlexD_0.IFCR[0].R          /* Identifier Filter Control Register */
#define LINFlexD_0_IFCR1     LINFlexD_0.IFCR[1].R          /* Identifier Filter Control Register */
#define LINFlexD_0_IFCR2     LINFlexD_0.IFCR[2].R          /* Identifier Filter Control Register */
#define LINFlexD_0_IFCR3     LINFlexD_0.IFCR[3].R          /* Identifier Filter Control Register */
#define LINFlexD_0_IFCR4     LINFlexD_0.IFCR[4].R          /* Identifier Filter Control Register */
#define LINFlexD_0_IFCR5     LINFlexD_0.IFCR[5].R          /* Identifier Filter Control Register */
#define LINFlexD_0_IFCR6     LINFlexD_0.IFCR[6].R          /* Identifier Filter Control Register */
#define LINFlexD_0_IFCR7     LINFlexD_0.IFCR[7].R          /* Identifier Filter Control Register */
#define LINFlexD_0_IFCR8     LINFlexD_0.IFCR[8].R          /* Identifier Filter Control Register */
#define LINFlexD_0_IFCR9     LINFlexD_0.IFCR[9].R          /* Identifier Filter Control Register */
#define LINFlexD_0_IFCR10    LINFlexD_0.IFCR[10].R         /* Identifier Filter Control Register */
#define LINFlexD_0_IFCR11    LINFlexD_0.IFCR[11].R         /* Identifier Filter Control Register */
#define LINFlexD_0_IFCR12    LINFlexD_0.IFCR[12].R         /* Identifier Filter Control Register */
#define LINFlexD_0_IFCR13    LINFlexD_0.IFCR[13].R         /* Identifier Filter Control Register */
#define LINFlexD_0_IFCR14    LINFlexD_0.IFCR[14].R         /* Identifier Filter Control Register */
#define LINFlexD_0_IFCR15    LINFlexD_0.IFCR[15].R         /* Identifier Filter Control Register */
#define LINFlexD_0_GCR       LINFlexD_0.GCR.R              /* Global Control Register */
#define LINFlexD_0_UARTPTO   LINFlexD_0.UARTPTO.R          /* UART Preset Timeout Register */
#define LINFlexD_0_UARTCTO   LINFlexD_0.UARTCTO.R          /* UART Current Timeout Register */
#define LINFlexD_0_DMATXE    LINFlexD_0.DMATXE.R           /* DMA Tx Enable Register */
#define LINFlexD_0_DMARXE    LINFlexD_0.DMARXE.R           /* DMA Rx Enable Register */
#define LINFlexD_0_PTD       LINFlexD_0.PTD.R              /* PSI5-S Tx Delay register */

/* LINFlexD */
#define LINFlexD_1_LINCR1    LINFlexD_1.LINCR1.R           /* LIN Control Register 1 */
#define LINFlexD_1_LINIER    LINFlexD_1.LINIER.R           /* LIN Interrupt enable register */
#define LINFlexD_1_LINSR     LINFlexD_1.LINSR.R            /* LIN Status Register */
#define LINFlexD_1_LINESR    LINFlexD_1.LINESR.R           /* LIN Error Status Register */
#define LINFlexD_1_UARTCR    LINFlexD_1.UARTCR.R           /* UART Mode Control Register */
#define LINFlexD_1_UARTSR    LINFlexD_1.UARTSR.R           /* UART Mode Status Register */
#define LINFlexD_1_LINTCSR   LINFlexD_1.LINTCSR.R          /* LIN Time-Out Control Status Register */
#define LINFlexD_1_LINOCR    LINFlexD_1.LINOCR.R           /* LIN Output Compare Register */
#define LINFlexD_1_LINTOCR   LINFlexD_1.LINTOCR.R          /* LIN Time-Out Control Register */
#define LINFlexD_1_LINFBRR   LINFlexD_1.LINFBRR.R          /* LIN Fractional Baud Rate Register */
#define LINFlexD_1_LINIBRR   LINFlexD_1.LINIBRR.R          /* LIN Integer Baud Rate Register */
#define LINFlexD_1_LINCFR    LINFlexD_1.LINCFR.R           /* LIN Checksum Field Register */
#define LINFlexD_1_LINCR2    LINFlexD_1.LINCR2.R           /* LIN Control Register 2 */
#define LINFlexD_1_BIDR      LINFlexD_1.BIDR.R             /* Buffer Identifier Register */
#define LINFlexD_1_BDRL      LINFlexD_1.BDRL.R             /* Buffer Data Register Least Significant */
#define LINFlexD_1_BDRM      LINFlexD_1.BDRM.R             /* Buffer Data Register Most Significant */
#define LINFlexD_1_IFER      LINFlexD_1.IFER.R             /* Identifier Filter Enable Register */
#define LINFlexD_1_IFMI      LINFlexD_1.IFMI.R             /* Identifier Filter Match Index */
#define LINFlexD_1_IFMR      LINFlexD_1.IFMR.R             /* Identifier Filter Mode Register */
#define LINFlexD_1_IFCR0     LINFlexD_1.IFCR[0].R          /* Identifier Filter Control Register */
#define LINFlexD_1_IFCR1     LINFlexD_1.IFCR[1].R          /* Identifier Filter Control Register */
#define LINFlexD_1_IFCR2     LINFlexD_1.IFCR[2].R          /* Identifier Filter Control Register */
#define LINFlexD_1_IFCR3     LINFlexD_1.IFCR[3].R          /* Identifier Filter Control Register */
#define LINFlexD_1_IFCR4     LINFlexD_1.IFCR[4].R          /* Identifier Filter Control Register */
#define LINFlexD_1_IFCR5     LINFlexD_1.IFCR[5].R          /* Identifier Filter Control Register */
#define LINFlexD_1_IFCR6     LINFlexD_1.IFCR[6].R          /* Identifier Filter Control Register */
#define LINFlexD_1_IFCR7     LINFlexD_1.IFCR[7].R          /* Identifier Filter Control Register */
#define LINFlexD_1_IFCR8     LINFlexD_1.IFCR[8].R          /* Identifier Filter Control Register */
#define LINFlexD_1_IFCR9     LINFlexD_1.IFCR[9].R          /* Identifier Filter Control Register */
#define LINFlexD_1_IFCR10    LINFlexD_1.IFCR[10].R         /* Identifier Filter Control Register */
#define LINFlexD_1_IFCR11    LINFlexD_1.IFCR[11].R         /* Identifier Filter Control Register */
#define LINFlexD_1_IFCR12    LINFlexD_1.IFCR[12].R         /* Identifier Filter Control Register */
#define LINFlexD_1_IFCR13    LINFlexD_1.IFCR[13].R         /* Identifier Filter Control Register */
#define LINFlexD_1_IFCR14    LINFlexD_1.IFCR[14].R         /* Identifier Filter Control Register */
#define LINFlexD_1_IFCR15    LINFlexD_1.IFCR[15].R         /* Identifier Filter Control Register */
#define LINFlexD_1_GCR       LINFlexD_1.GCR.R              /* Global Control Register */
#define LINFlexD_1_UARTPTO   LINFlexD_1.UARTPTO.R          /* UART Preset Timeout Register */
#define LINFlexD_1_UARTCTO   LINFlexD_1.UARTCTO.R          /* UART Current Timeout Register */
#define LINFlexD_1_DMATXE    LINFlexD_1.DMATXE.R           /* DMA Tx Enable Register */
#define LINFlexD_1_DMARXE    LINFlexD_1.DMARXE.R           /* DMA Rx Enable Register */
#define LINFlexD_1_PTD       LINFlexD_1.PTD.R              /* PSI5-S Tx Delay register */

/* LINFlexD */
#define LINFlexD_14_LINCR1   LINFlexD_14.LINCR1.R          /* LIN Control Register 1 */
#define LINFlexD_14_LINIER   LINFlexD_14.LINIER.R          /* LIN Interrupt enable register */
#define LINFlexD_14_LINSR    LINFlexD_14.LINSR.R           /* LIN Status Register */
#define LINFlexD_14_LINESR   LINFlexD_14.LINESR.R          /* LIN Error Status Register */
#define LINFlexD_14_UARTCR   LINFlexD_14.UARTCR.R          /* UART Mode Control Register */
#define LINFlexD_14_UARTSR   LINFlexD_14.UARTSR.R          /* UART Mode Status Register */
#define LINFlexD_14_LINTCSR  LINFlexD_14.LINTCSR.R         /* LIN Time-Out Control Status Register */
#define LINFlexD_14_LINOCR   LINFlexD_14.LINOCR.R          /* LIN Output Compare Register */
#define LINFlexD_14_LINTOCR  LINFlexD_14.LINTOCR.R         /* LIN Time-Out Control Register */
#define LINFlexD_14_LINFBRR  LINFlexD_14.LINFBRR.R         /* LIN Fractional Baud Rate Register */
#define LINFlexD_14_LINIBRR  LINFlexD_14.LINIBRR.R         /* LIN Integer Baud Rate Register */
#define LINFlexD_14_LINCFR   LINFlexD_14.LINCFR.R          /* LIN Checksum Field Register */
#define LINFlexD_14_LINCR2   LINFlexD_14.LINCR2.R          /* LIN Control Register 2 */
#define LINFlexD_14_BIDR     LINFlexD_14.BIDR.R            /* Buffer Identifier Register */
#define LINFlexD_14_BDRL     LINFlexD_14.BDRL.R            /* Buffer Data Register Least Significant */
#define LINFlexD_14_BDRM     LINFlexD_14.BDRM.R            /* Buffer Data Register Most Significant */
#define LINFlexD_14_IFER     LINFlexD_14.IFER.R            /* Identifier Filter Enable Register */
#define LINFlexD_14_IFMI     LINFlexD_14.IFMI.R            /* Identifier Filter Match Index */
#define LINFlexD_14_IFMR     LINFlexD_14.IFMR.R            /* Identifier Filter Mode Register */
#define LINFlexD_14_IFCR0    LINFlexD_14.IFCR[0].R         /* Identifier Filter Control Register */
#define LINFlexD_14_IFCR1    LINFlexD_14.IFCR[1].R         /* Identifier Filter Control Register */
#define LINFlexD_14_IFCR2    LINFlexD_14.IFCR[2].R         /* Identifier Filter Control Register */
#define LINFlexD_14_IFCR3    LINFlexD_14.IFCR[3].R         /* Identifier Filter Control Register */
#define LINFlexD_14_IFCR4    LINFlexD_14.IFCR[4].R         /* Identifier Filter Control Register */
#define LINFlexD_14_IFCR5    LINFlexD_14.IFCR[5].R         /* Identifier Filter Control Register */
#define LINFlexD_14_IFCR6    LINFlexD_14.IFCR[6].R         /* Identifier Filter Control Register */
#define LINFlexD_14_IFCR7    LINFlexD_14.IFCR[7].R         /* Identifier Filter Control Register */
#define LINFlexD_14_IFCR8    LINFlexD_14.IFCR[8].R         /* Identifier Filter Control Register */
#define LINFlexD_14_IFCR9    LINFlexD_14.IFCR[9].R         /* Identifier Filter Control Register */
#define LINFlexD_14_IFCR10   LINFlexD_14.IFCR[10].R        /* Identifier Filter Control Register */
#define LINFlexD_14_IFCR11   LINFlexD_14.IFCR[11].R        /* Identifier Filter Control Register */
#define LINFlexD_14_IFCR12   LINFlexD_14.IFCR[12].R        /* Identifier Filter Control Register */
#define LINFlexD_14_IFCR13   LINFlexD_14.IFCR[13].R        /* Identifier Filter Control Register */
#define LINFlexD_14_IFCR14   LINFlexD_14.IFCR[14].R        /* Identifier Filter Control Register */
#define LINFlexD_14_IFCR15   LINFlexD_14.IFCR[15].R        /* Identifier Filter Control Register */
#define LINFlexD_14_GCR      LINFlexD_14.GCR.R             /* Global Control Register */
#define LINFlexD_14_UARTPTO  LINFlexD_14.UARTPTO.R         /* UART Preset Timeout Register */
#define LINFlexD_14_UARTCTO  LINFlexD_14.UARTCTO.R         /* UART Current Timeout Register */
#define LINFlexD_14_DMATXE   LINFlexD_14.DMATXE.R          /* DMA Tx Enable Register */
#define LINFlexD_14_DMARXE   LINFlexD_14.DMARXE.R          /* DMA Rx Enable Register */
#define LINFlexD_14_PTD      LINFlexD_14.PTD.R             /* PSI5-S Tx Delay register */

/* LINFlexD */
#define LINFlexD_15_LINCR1   LINFlexD_15.LINCR1.R          /* LIN Control Register 1 */
#define LINFlexD_15_LINIER   LINFlexD_15.LINIER.R          /* LIN Interrupt enable register */
#define LINFlexD_15_LINSR    LINFlexD_15.LINSR.R           /* LIN Status Register */
#define LINFlexD_15_LINESR   LINFlexD_15.LINESR.R          /* LIN Error Status Register */
#define LINFlexD_15_UARTCR   LINFlexD_15.UARTCR.R          /* UART Mode Control Register */
#define LINFlexD_15_UARTSR   LINFlexD_15.UARTSR.R          /* UART Mode Status Register */
#define LINFlexD_15_LINTCSR  LINFlexD_15.LINTCSR.R         /* LIN Time-Out Control Status Register */
#define LINFlexD_15_LINOCR   LINFlexD_15.LINOCR.R          /* LIN Output Compare Register */
#define LINFlexD_15_LINTOCR  LINFlexD_15.LINTOCR.R         /* LIN Time-Out Control Register */
#define LINFlexD_15_LINFBRR  LINFlexD_15.LINFBRR.R         /* LIN Fractional Baud Rate Register */
#define LINFlexD_15_LINIBRR  LINFlexD_15.LINIBRR.R         /* LIN Integer Baud Rate Register */
#define LINFlexD_15_LINCFR   LINFlexD_15.LINCFR.R          /* LIN Checksum Field Register */
#define LINFlexD_15_LINCR2   LINFlexD_15.LINCR2.R          /* LIN Control Register 2 */
#define LINFlexD_15_BIDR     LINFlexD_15.BIDR.R            /* Buffer Identifier Register */
#define LINFlexD_15_BDRL     LINFlexD_15.BDRL.R            /* Buffer Data Register Least Significant */
#define LINFlexD_15_BDRM     LINFlexD_15.BDRM.R            /* Buffer Data Register Most Significant */
#define LINFlexD_15_IFER     LINFlexD_15.IFER.R            /* Identifier Filter Enable Register */
#define LINFlexD_15_IFMI     LINFlexD_15.IFMI.R            /* Identifier Filter Match Index */
#define LINFlexD_15_IFMR     LINFlexD_15.IFMR.R            /* Identifier Filter Mode Register */
#define LINFlexD_15_IFCR0    LINFlexD_15.IFCR[0].R         /* Identifier Filter Control Register */
#define LINFlexD_15_IFCR1    LINFlexD_15.IFCR[1].R         /* Identifier Filter Control Register */
#define LINFlexD_15_IFCR2    LINFlexD_15.IFCR[2].R         /* Identifier Filter Control Register */
#define LINFlexD_15_IFCR3    LINFlexD_15.IFCR[3].R         /* Identifier Filter Control Register */
#define LINFlexD_15_IFCR4    LINFlexD_15.IFCR[4].R         /* Identifier Filter Control Register */
#define LINFlexD_15_IFCR5    LINFlexD_15.IFCR[5].R         /* Identifier Filter Control Register */
#define LINFlexD_15_IFCR6    LINFlexD_15.IFCR[6].R         /* Identifier Filter Control Register */
#define LINFlexD_15_IFCR7    LINFlexD_15.IFCR[7].R         /* Identifier Filter Control Register */
#define LINFlexD_15_IFCR8    LINFlexD_15.IFCR[8].R         /* Identifier Filter Control Register */
#define LINFlexD_15_IFCR9    LINFlexD_15.IFCR[9].R         /* Identifier Filter Control Register */
#define LINFlexD_15_IFCR10   LINFlexD_15.IFCR[10].R        /* Identifier Filter Control Register */
#define LINFlexD_15_IFCR11   LINFlexD_15.IFCR[11].R        /* Identifier Filter Control Register */
#define LINFlexD_15_IFCR12   LINFlexD_15.IFCR[12].R        /* Identifier Filter Control Register */
#define LINFlexD_15_IFCR13   LINFlexD_15.IFCR[13].R        /* Identifier Filter Control Register */
#define LINFlexD_15_IFCR14   LINFlexD_15.IFCR[14].R        /* Identifier Filter Control Register */
#define LINFlexD_15_IFCR15   LINFlexD_15.IFCR[15].R        /* Identifier Filter Control Register */
#define LINFlexD_15_GCR      LINFlexD_15.GCR.R             /* Global Control Register */
#define LINFlexD_15_UARTPTO  LINFlexD_15.UARTPTO.R         /* UART Preset Timeout Register */
#define LINFlexD_15_UARTCTO  LINFlexD_15.UARTCTO.R         /* UART Current Timeout Register */
#define LINFlexD_15_DMATXE   LINFlexD_15.DMATXE.R          /* DMA Tx Enable Register */
#define LINFlexD_15_DMARXE   LINFlexD_15.DMARXE.R          /* DMA Rx Enable Register */
#define LINFlexD_15_PTD      LINFlexD_15.PTD.R             /* PSI5-S Tx Delay register */

/* LINFlexD */
#define LINFlexD_16_LINCR1   LINFlexD_16.LINCR1.R          /* LIN Control Register 1 */
#define LINFlexD_16_LINIER   LINFlexD_16.LINIER.R          /* LIN Interrupt enable register */
#define LINFlexD_16_LINSR    LINFlexD_16.LINSR.R           /* LIN Status Register */
#define LINFlexD_16_LINESR   LINFlexD_16.LINESR.R          /* LIN Error Status Register */
#define LINFlexD_16_UARTCR   LINFlexD_16.UARTCR.R          /* UART Mode Control Register */
#define LINFlexD_16_UARTSR   LINFlexD_16.UARTSR.R          /* UART Mode Status Register */
#define LINFlexD_16_LINTCSR  LINFlexD_16.LINTCSR.R         /* LIN Time-Out Control Status Register */
#define LINFlexD_16_LINOCR   LINFlexD_16.LINOCR.R          /* LIN Output Compare Register */
#define LINFlexD_16_LINTOCR  LINFlexD_16.LINTOCR.R         /* LIN Time-Out Control Register */
#define LINFlexD_16_LINFBRR  LINFlexD_16.LINFBRR.R         /* LIN Fractional Baud Rate Register */
#define LINFlexD_16_LINIBRR  LINFlexD_16.LINIBRR.R         /* LIN Integer Baud Rate Register */
#define LINFlexD_16_LINCFR   LINFlexD_16.LINCFR.R          /* LIN Checksum Field Register */
#define LINFlexD_16_LINCR2   LINFlexD_16.LINCR2.R          /* LIN Control Register 2 */
#define LINFlexD_16_BIDR     LINFlexD_16.BIDR.R            /* Buffer Identifier Register */
#define LINFlexD_16_BDRL     LINFlexD_16.BDRL.R            /* Buffer Data Register Least Significant */
#define LINFlexD_16_BDRM     LINFlexD_16.BDRM.R            /* Buffer Data Register Most Significant */
#define LINFlexD_16_IFER     LINFlexD_16.IFER.R            /* Identifier Filter Enable Register */
#define LINFlexD_16_IFMI     LINFlexD_16.IFMI.R            /* Identifier Filter Match Index */
#define LINFlexD_16_IFMR     LINFlexD_16.IFMR.R            /* Identifier Filter Mode Register */
#define LINFlexD_16_IFCR0    LINFlexD_16.IFCR[0].R         /* Identifier Filter Control Register */
#define LINFlexD_16_IFCR1    LINFlexD_16.IFCR[1].R         /* Identifier Filter Control Register */
#define LINFlexD_16_IFCR2    LINFlexD_16.IFCR[2].R         /* Identifier Filter Control Register */
#define LINFlexD_16_IFCR3    LINFlexD_16.IFCR[3].R         /* Identifier Filter Control Register */
#define LINFlexD_16_IFCR4    LINFlexD_16.IFCR[4].R         /* Identifier Filter Control Register */
#define LINFlexD_16_IFCR5    LINFlexD_16.IFCR[5].R         /* Identifier Filter Control Register */
#define LINFlexD_16_IFCR6    LINFlexD_16.IFCR[6].R         /* Identifier Filter Control Register */
#define LINFlexD_16_IFCR7    LINFlexD_16.IFCR[7].R         /* Identifier Filter Control Register */
#define LINFlexD_16_IFCR8    LINFlexD_16.IFCR[8].R         /* Identifier Filter Control Register */
#define LINFlexD_16_IFCR9    LINFlexD_16.IFCR[9].R         /* Identifier Filter Control Register */
#define LINFlexD_16_IFCR10   LINFlexD_16.IFCR[10].R        /* Identifier Filter Control Register */
#define LINFlexD_16_IFCR11   LINFlexD_16.IFCR[11].R        /* Identifier Filter Control Register */
#define LINFlexD_16_IFCR12   LINFlexD_16.IFCR[12].R        /* Identifier Filter Control Register */
#define LINFlexD_16_IFCR13   LINFlexD_16.IFCR[13].R        /* Identifier Filter Control Register */
#define LINFlexD_16_IFCR14   LINFlexD_16.IFCR[14].R        /* Identifier Filter Control Register */
#define LINFlexD_16_IFCR15   LINFlexD_16.IFCR[15].R        /* Identifier Filter Control Register */
#define LINFlexD_16_GCR      LINFlexD_16.GCR.R             /* Global Control Register */
#define LINFlexD_16_UARTPTO  LINFlexD_16.UARTPTO.R         /* UART Preset Timeout Register */
#define LINFlexD_16_UARTCTO  LINFlexD_16.UARTCTO.R         /* UART Current Timeout Register */
#define LINFlexD_16_DMATXE   LINFlexD_16.DMATXE.R          /* DMA Tx Enable Register */
#define LINFlexD_16_DMARXE   LINFlexD_16.DMARXE.R          /* DMA Rx Enable Register */
#define LINFlexD_16_PTD      LINFlexD_16.PTD.R             /* PSI5-S Tx Delay register */

/* LINFlexD */
#define LINFlexD_2_LINCR1    LINFlexD_2.LINCR1.R           /* LIN Control Register 1 */
#define LINFlexD_2_LINIER    LINFlexD_2.LINIER.R           /* LIN Interrupt enable register */
#define LINFlexD_2_LINSR     LINFlexD_2.LINSR.R            /* LIN Status Register */
#define LINFlexD_2_LINESR    LINFlexD_2.LINESR.R           /* LIN Error Status Register */
#define LINFlexD_2_UARTCR    LINFlexD_2.UARTCR.R           /* UART Mode Control Register */
#define LINFlexD_2_UARTSR    LINFlexD_2.UARTSR.R           /* UART Mode Status Register */
#define LINFlexD_2_LINTCSR   LINFlexD_2.LINTCSR.R          /* LIN Time-Out Control Status Register */
#define LINFlexD_2_LINOCR    LINFlexD_2.LINOCR.R           /* LIN Output Compare Register */
#define LINFlexD_2_LINTOCR   LINFlexD_2.LINTOCR.R          /* LIN Time-Out Control Register */
#define LINFlexD_2_LINFBRR   LINFlexD_2.LINFBRR.R          /* LIN Fractional Baud Rate Register */
#define LINFlexD_2_LINIBRR   LINFlexD_2.LINIBRR.R          /* LIN Integer Baud Rate Register */
#define LINFlexD_2_LINCFR    LINFlexD_2.LINCFR.R           /* LIN Checksum Field Register */
#define LINFlexD_2_LINCR2    LINFlexD_2.LINCR2.R           /* LIN Control Register 2 */
#define LINFlexD_2_BIDR      LINFlexD_2.BIDR.R             /* Buffer Identifier Register */
#define LINFlexD_2_BDRL      LINFlexD_2.BDRL.R             /* Buffer Data Register Least Significant */
#define LINFlexD_2_BDRM      LINFlexD_2.BDRM.R             /* Buffer Data Register Most Significant */
#define LINFlexD_2_IFER      LINFlexD_2.IFER.R             /* Identifier Filter Enable Register */
#define LINFlexD_2_IFMI      LINFlexD_2.IFMI.R             /* Identifier Filter Match Index */
#define LINFlexD_2_IFMR      LINFlexD_2.IFMR.R             /* Identifier Filter Mode Register */
#define LINFlexD_2_IFCR0     LINFlexD_2.IFCR[0].R          /* Identifier Filter Control Register */
#define LINFlexD_2_IFCR1     LINFlexD_2.IFCR[1].R          /* Identifier Filter Control Register */
#define LINFlexD_2_IFCR2     LINFlexD_2.IFCR[2].R          /* Identifier Filter Control Register */
#define LINFlexD_2_IFCR3     LINFlexD_2.IFCR[3].R          /* Identifier Filter Control Register */
#define LINFlexD_2_IFCR4     LINFlexD_2.IFCR[4].R          /* Identifier Filter Control Register */
#define LINFlexD_2_IFCR5     LINFlexD_2.IFCR[5].R          /* Identifier Filter Control Register */
#define LINFlexD_2_IFCR6     LINFlexD_2.IFCR[6].R          /* Identifier Filter Control Register */
#define LINFlexD_2_IFCR7     LINFlexD_2.IFCR[7].R          /* Identifier Filter Control Register */
#define LINFlexD_2_IFCR8     LINFlexD_2.IFCR[8].R          /* Identifier Filter Control Register */
#define LINFlexD_2_IFCR9     LINFlexD_2.IFCR[9].R          /* Identifier Filter Control Register */
#define LINFlexD_2_IFCR10    LINFlexD_2.IFCR[10].R         /* Identifier Filter Control Register */
#define LINFlexD_2_IFCR11    LINFlexD_2.IFCR[11].R         /* Identifier Filter Control Register */
#define LINFlexD_2_IFCR12    LINFlexD_2.IFCR[12].R         /* Identifier Filter Control Register */
#define LINFlexD_2_IFCR13    LINFlexD_2.IFCR[13].R         /* Identifier Filter Control Register */
#define LINFlexD_2_IFCR14    LINFlexD_2.IFCR[14].R         /* Identifier Filter Control Register */
#define LINFlexD_2_IFCR15    LINFlexD_2.IFCR[15].R         /* Identifier Filter Control Register */
#define LINFlexD_2_GCR       LINFlexD_2.GCR.R              /* Global Control Register */
#define LINFlexD_2_UARTPTO   LINFlexD_2.UARTPTO.R          /* UART Preset Timeout Register */
#define LINFlexD_2_UARTCTO   LINFlexD_2.UARTCTO.R          /* UART Current Timeout Register */
#define LINFlexD_2_DMATXE    LINFlexD_2.DMATXE.R           /* DMA Tx Enable Register */
#define LINFlexD_2_DMARXE    LINFlexD_2.DMARXE.R           /* DMA Rx Enable Register */
#define LINFlexD_2_PTD       LINFlexD_2.PTD.R              /* PSI5-S Tx Delay register */

/* MC_CGM */
#define MC_CGM_AC5_CDC0      MC_CGM.AC5_CDC0.R             /* Auxiliary Clock 5 Cascaded Divider 0 Configuration Register */
#define MC_CGM_AC5_CDC1      MC_CGM.AC5_CDC1.R             /* Auxiliary Clock 5 Cascaded Divider 1 Configuration Register */
#define MC_CGM_AC5_CDC2      MC_CGM.AC5_CDC2.R             /* Auxiliary Clock 5 Cascaded Divider 2 Configuration Register */
#define MC_CGM_AC5_CDC10     MC_CGM.AC5_CDC10.R            /* Auxiliary Clock 5 Cascaded Divider 10 Configuration Register */
#define MC_CGM_AC5_CDC11     MC_CGM.AC5_CDC11.R            /* Auxiliary Clock 5 Cascaded Divider 11 Configuration Register */
#define MC_CGM_AC5_CDC12     MC_CGM.AC5_CDC12.R            /* Auxiliary Clock 5 Cascaded Divider 12 Configuration Register */
#define MC_CGM_AC5_CDC13     MC_CGM.AC5_CDC13.R            /* Auxiliary Clock 5 Cascaded Divider 13 Configuration Register */
#define MC_CGM_AC5_CDC20     MC_CGM.AC5_CDC20.R            /* Auxiliary Clock 5 Cascaded Divider 20 Configuration Register */
#define MC_CGM_AC5_CDC21     MC_CGM.AC5_CDC21.R            /* Auxiliary Clock 5 Cascaded Divider 21 Configuration Register */
#define MC_CGM_AC5_CDC22     MC_CGM.AC5_CDC22.R            /* Auxiliary Clock 5 Cascaded Divider 22 Configuration Register */
#define MC_CGM_PCS_SDUR      MC_CGM.PCS_SDUR.R             /* PCS Switch Duration Register */
#define MC_CGM_PCS_DIVC1     MC_CGM.PCS_DIVC1.R            /* PCS Divider Change Register 1 */
#define MC_CGM_PCS_DIVE1     MC_CGM.PCS_DIVE1.R            /* PCS Divider End Register 1 */
#define MC_CGM_PCS_DIVS1     MC_CGM.PCS_DIVS1.R            /* PCS Divider Start Register 1 */
#define MC_CGM_PCS_DIVC2     MC_CGM.PCS_DIVC2.R            /* PCS Divider Change Register 2 */
#define MC_CGM_PCS_DIVE2     MC_CGM.PCS_DIVE2.R            /* PCS Divider End Register 2 */
#define MC_CGM_PCS_DIVS2     MC_CGM.PCS_DIVS2.R            /* PCS Divider Start Register 2 */
#define MC_CGM_PCS_DIVC4     MC_CGM.PCS_DIVC4.R            /* PCS Divider Change Register 4 */
#define MC_CGM_PCS_DIVE4     MC_CGM.PCS_DIVE4.R            /* PCS Divider End Register 4 */
#define MC_CGM_PCS_DIVS4     MC_CGM.PCS_DIVS4.R            /* PCS Divider Start Register 4 */
#define MC_CGM_SC_DIV_RC     MC_CGM.SC_DIV_RC.R            /* System Clock Divider Ratio Change Register */
#define MC_CGM_DIV_UPD_TYPE  MC_CGM.DIV_UPD_TYPE.R         /* Divider Update Type Register */
#define MC_CGM_DIV_UPD_TRIG  MC_CGM.DIV_UPD_TRIG.R         /* Divider Update Trigger Register */
#define MC_CGM_DIV_UPD_STAT  MC_CGM.DIV_UPD_STAT.R         /* Divider Update Status Register */
#define MC_CGM_SC_SS         MC_CGM.SC_SS.R                /* System Clock Select Status Register */
#define MC_CGM_SC_DC0        MC_CGM.SC_DC0.R               /* System Clock Divider 0 Configuration Register */
#define MC_CGM_SC_DC1        MC_CGM.SC_DC1.R               /* System Clock Divider 1 Configuration Register */
#define MC_CGM_SC_DC2        MC_CGM.SC_DC2.R               /* System Clock Divider 2 Configuration Register */
#define MC_CGM_SC_DC3        MC_CGM.SC_DC3.R               /* System Clock Divider 3 Configuration Register */
#define MC_CGM_SC_DC4        MC_CGM.SC_DC4.R               /* System Clock Divider 4 Configuration Register */
#define MC_CGM_AC0_SC        MC_CGM.AC0_SC.R               /* Auxiliary Clock 0 Select Control Register */
#define MC_CGM_AC0_SS        MC_CGM.AC0_SS.R               /* Auxiliary Clock 0 Select Status Register */
#define MC_CGM_AC0_DC0       MC_CGM.AC0_DC0.R              /* Auxiliary Clock 0 Divider 0 Configuration Register */
#define MC_CGM_AC0_DC1       MC_CGM.AC0_DC1.R              /* Auxiliary Clock 0 Divider 1 Configuration Register */
#define MC_CGM_AC0_DC2       MC_CGM.AC0_DC2.R              /* Auxiliary Clock 0 Divider 2 Configuration Register */
#define MC_CGM_AC0_DC3       MC_CGM.AC0_DC3.R              /* Auxiliary Clock 0 Divider 3 Configuration Register */
#define MC_CGM_AC0_DC4       MC_CGM.AC0_DC4.R              /* Auxiliary Clock 0 Divider 4 Configuration Register */
#define MC_CGM_AC1_SC        MC_CGM.AC1_SC.R               /* Auxiliary Clock 1 Select Control Register */
#define MC_CGM_AC1_SS        MC_CGM.AC1_SS.R               /* Auxiliary Clock 1 Select Status Register */
#define MC_CGM_AC1_DC0       MC_CGM.AC1_DC0.R              /* Auxiliary Clock 1 Divider 0 Configuration Register */
#define MC_CGM_AC2_DC0       MC_CGM.AC2_DC0.R              /* Auxiliary Clock 2 Divider 0 Configuration Register */
#define MC_CGM_AC2_DC1       MC_CGM.AC2_DC1.R              /* Auxiliary Clock 2 Divider 1 Configuration Register */
#define MC_CGM_AC3_SC        MC_CGM.AC3_SC.R               /* Auxiliary Clock 3 Select Control Register */
#define MC_CGM_AC3_SS        MC_CGM.AC3_SS.R               /* Auxiliary Clock 3 Select Status Register */
#define MC_CGM_AC4_SC        MC_CGM.AC4_SC.R               /* Auxiliary Clock 4 Select Control Register */
#define MC_CGM_AC4_SS        MC_CGM.AC4_SS.R               /* Auxiliary Clock 4 Select Status Register */
#define MC_CGM_AC5_DC0       MC_CGM.AC5_DC0.R              /* Auxiliary Clock 5 Divider 0 Configuration Register */
#define MC_CGM_AC5_DC1       MC_CGM.AC5_DC1.R              /* Auxiliary Clock 5 Divider 1 Configuration Register */
#define MC_CGM_AC5_DC2       MC_CGM.AC5_DC2.R              /* Auxiliary Clock 5 Divider 2 Configuration Register */
#define MC_CGM_AC6_SC        MC_CGM.AC6_SC.R               /* Auxiliary Clock 6 Select Control Register */
#define MC_CGM_AC6_SS        MC_CGM.AC6_SS.R               /* Auxiliary Clock 6 Select Status Register */
#define MC_CGM_AC6_DC0       MC_CGM.AC6_DC0.R              /* Auxiliary Clock 6 Divider 0 Configuration Register */
#define MC_CGM_AC7_SC        MC_CGM.AC7_SC.R               /* Auxiliary Clock 7 Select Control Register */
#define MC_CGM_AC7_SS        MC_CGM.AC7_SS.R               /* Auxiliary Clock 7 Select Status Register */
#define MC_CGM_AC7_DC0       MC_CGM.AC7_DC0.R              /* Auxiliary Clock 7 Divider 0 Configuration Register */
#define MC_CGM_AC8_SC        MC_CGM.AC8_SC.R               /* Auxiliary Clock 8 Select Control Register */
#define MC_CGM_AC8_SS        MC_CGM.AC8_SS.R               /* Auxiliary Clock 8 Select Status Register */
#define MC_CGM_AC8_DC0       MC_CGM.AC8_DC0.R              /* Auxiliary Clock 8 Divider 0 Configuration Register */
#define MC_CGM_AC9_SC        MC_CGM.AC9_SC.R               /* Auxiliary Clock 9 Select Control Register */
#define MC_CGM_AC9_SS        MC_CGM.AC9_SS.R               /* Auxiliary Clock 9 Select Status Register */
#define MC_CGM_AC9_DC0       MC_CGM.AC9_DC0.R              /* Auxiliary Clock 9 Divider 0 Configuration Register */
#define MC_CGM_AC10_SC       MC_CGM.AC10_SC.R              /* Auxiliary Clock 10 Select Control Register */
#define MC_CGM_AC10_SS       MC_CGM.AC10_SS.R              /* Auxiliary Clock 10 Select Status Register */
#define MC_CGM_AC10_DC0      MC_CGM.AC10_DC0.R             /* Auxiliary Clock 10 Divider 0 Configuration Register */

/* MC_ME */
#define MC_ME_GS             MC_ME.GS.R                    /* Global Status Register */
#define MC_ME_MCTL           MC_ME.MCTL.R                  /* Mode Control Register */
#define MC_ME_ME             MC_ME.ME.R                    /* Mode Enable Register */
#define MC_ME_IS             MC_ME.IS.R                    /* Interrupt Status Register */
#define MC_ME_IM             MC_ME.IM.R                    /* Interrupt Mask Register */
#define MC_ME_IMTS           MC_ME.IMTS.R                  /* Invalid Mode Transition Status Register */
#define MC_ME_DMTS           MC_ME.DMTS.R                  /* Debug Mode Transition Status Register */
#define MC_ME_RESET_MC       MC_ME.RESET_MC.R              /* RESET Mode Configuration Register */
#define MC_ME_TEST_MC        MC_ME.TEST_MC.R               /* TEST Mode Configuration Register */
#define MC_ME_SAFE_MC        MC_ME.SAFE_MC.R               /* SAFE Mode Configuration Register */
#define MC_ME_DRUN_MC        MC_ME.DRUN_MC.R               /* DRUN Mode Configuration Register */
#define MC_ME_RUN0_MC        MC_ME.RUN_MC[0].R             /* RUN0 Mode Configuration Register */
#define MC_ME_RUN1_MC        MC_ME.RUN_MC[1].R             /* RUN1 Mode Configuration Register */
#define MC_ME_RUN2_MC        MC_ME.RUN_MC[2].R             /* RUN2 Mode Configuration Register */
#define MC_ME_RUN3_MC        MC_ME.RUN_MC[3].R             /* RUN3 Mode Configuration Register */
#define MC_ME_HALT0_MC       MC_ME.HALT0_MC.R              /* HALT0 Mode Configuration Register */
#define MC_ME_STOP0_MC       MC_ME.STOP0_MC.R              /* STOP0 Mode Configuration Register */
#define MC_ME_PS0            MC_ME.PS0.R                   /* Peripheral Status Register 0 */
#define MC_ME_PS1            MC_ME.PS1.R                   /* Peripheral Status Register 1 */
#define MC_ME_PS2            MC_ME.PS2.R                   /* Peripheral Status Register 2 */
#define MC_ME_PS3            MC_ME.PS3.R                   /* Peripheral Status Register 3 */
#define MC_ME_PS4            MC_ME.PS4.R                   /* Peripheral Status Register 4 */
#define MC_ME_PS5            MC_ME.PS5.R                   /* Peripheral Status Register 5 */
#define MC_ME_PS6            MC_ME.PS6.R                   /* Peripheral Status Register 6 */
#define MC_ME_PS7            MC_ME.PS7.R                   /* Peripheral Status Register 7 */
#define MC_ME_RUN_PC0        MC_ME.RUN_PC[0].R             /* Run Peripheral Configuration Register */
#define MC_ME_RUN_PC1        MC_ME.RUN_PC[1].R             /* Run Peripheral Configuration Register */
#define MC_ME_RUN_PC2        MC_ME.RUN_PC[2].R             /* Run Peripheral Configuration Register */
#define MC_ME_RUN_PC3        MC_ME.RUN_PC[3].R             /* Run Peripheral Configuration Register */
#define MC_ME_RUN_PC4        MC_ME.RUN_PC[4].R             /* Run Peripheral Configuration Register */
#define MC_ME_RUN_PC5        MC_ME.RUN_PC[5].R             /* Run Peripheral Configuration Register */
#define MC_ME_RUN_PC6        MC_ME.RUN_PC[6].R             /* Run Peripheral Configuration Register */
#define MC_ME_RUN_PC7        MC_ME.RUN_PC[7].R             /* Run Peripheral Configuration Register */
#define MC_ME_LP_PC0         MC_ME.LP_PC[0].R              /* Low-Power Peripheral Configuration Register */
#define MC_ME_LP_PC1         MC_ME.LP_PC[1].R              /* Low-Power Peripheral Configuration Register */
#define MC_ME_LP_PC2         MC_ME.LP_PC[2].R              /* Low-Power Peripheral Configuration Register */
#define MC_ME_LP_PC3         MC_ME.LP_PC[3].R              /* Low-Power Peripheral Configuration Register */
#define MC_ME_LP_PC4         MC_ME.LP_PC[4].R              /* Low-Power Peripheral Configuration Register */
#define MC_ME_LP_PC5         MC_ME.LP_PC[5].R              /* Low-Power Peripheral Configuration Register */
#define MC_ME_LP_PC6         MC_ME.LP_PC[6].R              /* Low-Power Peripheral Configuration Register */
#define MC_ME_LP_PC7         MC_ME.LP_PC[7].R              /* Low-Power Peripheral Configuration Register */
#define MC_ME_PCTL3          MC_ME.PCTL3.R                 /* EBI_0 Peripheral Control Register */
#define MC_ME_PCTL9          MC_ME.PCTL9.R                 /* LFAST_0 Peripheral Control Register */
#define MC_ME_PCTL11         MC_ME.PCTL11.R                /* SIPI_0 Peripheral Control Register */
#define MC_ME_PCTL15         MC_ME.PCTL15.R                /* SIUL Peripheral Control Register */
#define MC_ME_PCTL30         MC_ME.PCTL30.R                /* PIT_RTC_0 Peripheral Control Register */
#define MC_ME_PCTL31         MC_ME.PCTL31.R                /* PIT_RTC_1 Peripheral Control Register */
#define MC_ME_PCTL36         MC_ME.PCTL36.R                /* DMAMUX_0 Peripheral Control Register */
#define MC_ME_PCTL38         MC_ME.PCTL38.R                /* CRC_0 Peripheral Control Register */
#define MC_ME_PCTL56         MC_ME.PCTL56.R                /* ADCSD_8 Peripheral Control Register */
#define MC_ME_PCTL57         MC_ME.PCTL57.R                /* ADCSD_6 Peripheral Control Register */
#define MC_ME_PCTL58         MC_ME.PCTL58.R                /* ADCSD_4 Peripheral Control Register */
#define MC_ME_PCTL59         MC_ME.PCTL59.R                /* ADCSD_2 Peripheral Control Register */
#define MC_ME_PCTL60         MC_ME.PCTL60.R                /* ADCSD_0 Peripheral Control Register */
#define MC_ME_PCTL67         MC_ME.PCTL67.R                /* MCAN_4 Peripheral Control Register */
#define MC_ME_PCTL68         MC_ME.PCTL68.R                /* MCAN_3 Peripheral Control Register */
#define MC_ME_PCTL69         MC_ME.PCTL69.R                /* MCAN_2 Peripheral Control Register */
#define MC_ME_PCTL70         MC_ME.PCTL70.R                /* MCAN_1 Peripheral Control Register */
#define MC_ME_PCTL72         MC_ME.PCTL72.R                /* TTCAN Peripheral Control Register */
#define MC_ME_PCTL74         MC_ME.PCTL74.R                /* CAN_RAM_CTRL Peripheral Control Register */
#define MC_ME_PCTL84         MC_ME.PCTL84.R                /* LINFlexD_16 Peripheral Control Register */
#define MC_ME_PCTL85         MC_ME.PCTL85.R                /* LINFlexD_14 Peripheral Control Register */
#define MC_ME_PCTL91         MC_ME.PCTL91.R                /* LINFlexD_1 Peripheral Control Register */
#define MC_ME_PCTL92         MC_ME.PCTL92.R                /* LINFlexD_0 Peripheral Control Register */
#define MC_ME_PCTL93         MC_ME.PCTL93.R                /* DSPI_12 Peripheral Control Register */
#define MC_ME_PCTL96         MC_ME.PCTL96.R                /* DSPI_6 Peripheral Control Register */
#define MC_ME_PCTL97         MC_ME.PCTL97.R                /* DSPI_4 Peripheral Control Register */
#define MC_ME_PCTL98         MC_ME.PCTL98.R                /* DSPI_1 Peripheral Control Register */
#define MC_ME_PCTL99         MC_ME.PCTL99.R                /* DSPI_0 Peripheral Control Register */
#define MC_ME_PCTL101        MC_ME.PCTL101.R               /* IIC_0 Peripheral Control Register */
#define MC_ME_PCTL104        MC_ME.PCTL104.R               /* SENT_0 Peripheral Control Register */
#define MC_ME_PCTL107        MC_ME.PCTL107.R               /* FLEXRAY_0 Peripheral Control Register */
#define MC_ME_PCTL111        MC_ME.PCTL111.R               /* PSI5_0 Peripheral Control Register */
#define MC_ME_PCTL112        MC_ME.PCTL112.R               /* ADCSAR_b Peripheral Control Register */
#define MC_ME_PCTL123        MC_ME.PCTL123.R               /* ADCSAR_4 Peripheral Control Register */
#define MC_ME_PCTL127        MC_ME.PCTL127.R               /* ADCSAR_0 Peripheral Control Register */
#define MC_ME_PCTL128        MC_ME.PCTL128.R               /* GTMINT Peripheral Control Register */
#define MC_ME_PCTL162        MC_ME.PCTL162.R               /* PSI5_S_0 Peripheral Control Register */
#define MC_ME_PCTL166        MC_ME.PCTL166.R               /* CRC_1 Peripheral Control Register */
#define MC_ME_PCTL184        MC_ME.PCTL184.R               /* ADCSD_9 Peripheral Control Register */
#define MC_ME_PCTL185        MC_ME.PCTL185.R               /* ADCSD_7 Peripheral Control Register */
#define MC_ME_PCTL186        MC_ME.PCTL186.R               /* ADCSD_5 Peripheral Control Register */
#define MC_ME_PCTL187        MC_ME.PCTL187.R               /* ADCSD_3 Peripheral Control Register */
#define MC_ME_PCTL188        MC_ME.PCTL188.R               /* ADCSD_1 Peripheral Control Register */
#define MC_ME_PCTL213        MC_ME.PCTL213.R               /* LINFlexD_15 Peripheral Control Register */
#define MC_ME_PCTL220        MC_ME.PCTL220.R               /* LINFlexD_2 Peripheral Control Register */
#define MC_ME_PCTL225        MC_ME.PCTL225.R               /* DSPI_5 Peripheral Control Register */
#define MC_ME_PCTL226        MC_ME.PCTL226.R               /* DSPI_3 Peripheral Control Register */
#define MC_ME_PCTL227        MC_ME.PCTL227.R               /* DSPI_2 Peripheral Control Register */
#define MC_ME_PCTL229        MC_ME.PCTL229.R               /* IIC_1 Peripheral Control Register */
#define MC_ME_PCTL232        MC_ME.PCTL232.R               /* SENT_1 Peripheral Control Register */
#define MC_ME_PCTL235        MC_ME.PCTL235.R               /* FLEXRAY_1 Peripheral Control Register */
#define MC_ME_PCTL239        MC_ME.PCTL239.R               /* PSI5_1 Peripheral Control Register */
#define MC_ME_PCTL245        MC_ME.PCTL245.R               /* ADCSAR_10 Peripheral Control Register */
#define MC_ME_PCTL246        MC_ME.PCTL246.R               /* ADCSAR_9 Peripheral Control Register */
#define MC_ME_PCTL247        MC_ME.PCTL247.R               /* ADCSAR_8 Peripheral Control Register */
#define MC_ME_PCTL248        MC_ME.PCTL248.R               /* ADCSAR_7 Peripheral Control Register */
#define MC_ME_PCTL249        MC_ME.PCTL249.R               /* ADCSAR_6 Peripheral Control Register */
#define MC_ME_PCTL250        MC_ME.PCTL250.R               /* ADCSAR_5 Peripheral Control Register */
#define MC_ME_PCTL252        MC_ME.PCTL252.R               /* ADCSAR_3 Peripheral Control Register */
#define MC_ME_PCTL253        MC_ME.PCTL253.R               /* ADCSAR_2 Peripheral Control Register */
#define MC_ME_PCTL254        MC_ME.PCTL254.R               /* ADCSAR_1 Peripheral Control Register */
#define MC_ME_CS             MC_ME.CS.R                    /* Core Status Register */
#define MC_ME_CCTL0          MC_ME.CCTL0.R                 /* CORE0 Core Control Register */
#define MC_ME_CCTL1          MC_ME.CCTL1.R                 /* CORE1 Core Control Register */
#define MC_ME_CCTL2          MC_ME.CCTL2.R                 /* CORE2 Core Control Register */
#define MC_ME_CCTL3          MC_ME.CCTL3.R                 /* CORE3 Core Control Register */
#define MC_ME_CCTL4          MC_ME.CCTL4.R                 /* CORE4 Core Control Register */
#define MC_ME_CADDR0         MC_ME.CADDR0.R                /* CORE0 Core Address Register */
#define MC_ME_CADDR1         MC_ME.CADDR1.R                /* CORE1 Core Address Register */
#define MC_ME_CADDR2         MC_ME.CADDR2.R                /* CORE2 Core Address Register */
#define MC_ME_CADDR3         MC_ME.CADDR3.R                /* CORE3 Core Address Register */
#define MC_ME_CADDR4         MC_ME.CADDR4.R                /* CORE4 Core Address Register */

/* MC_PCU */
#define MC_PCU_PSTAT         MC_PCU.PSTAT.R                /* Power Domain Status Register */

/* MC_RGM */
#define MC_RGM_DES           MC_RGM.DES.R                  /* 'Destructive' Event Status Register */
#define MC_RGM_DERD          MC_RGM.DERD.R                 /* 'Destructive' Event Reset Disable Register */
#define MC_RGM_DEAR          MC_RGM.DEAR.R                 /* 'Destructive' Event Alternate Request Register */
#define MC_RGM_DBRE          MC_RGM.DBRE.R                 /* 'Destructive' Bidirectional Reset Enable Register */
#define MC_RGM_FES           MC_RGM.FES.R                  /* 'Functional' Event Status Register */
#define MC_RGM_FERD          MC_RGM.FERD.R                 /* 'Functional' Event Reset Disable Register */
#define MC_RGM_FEAR          MC_RGM.FEAR.R                 /* 'Functional' Event Alternate Request Register */
#define MC_RGM_FBRE          MC_RGM.FBRE.R                 /* 'Functional' Bidirectional Reset Enable Register */
#define MC_RGM_FESS          MC_RGM.FESS.R                 /* 'Functional' Event Short Sequence Register */
#define MC_RGM_FRET          MC_RGM.FRET.R                 /* 'Functional' Reset Escalation Threshold Register */
#define MC_RGM_DRET          MC_RGM.DRET.R                 /* 'Destructive' Reset Escalation Threshold Register */
#define MC_RGM_EROEC         MC_RGM.EROEC.R                /* External Reset Output Extension Control Register */
#define MC_RGM_PRST0         MC_RGM.PRST0.R                /* Peripheral Reset Register 0 */
#define MC_RGM_PRST1         MC_RGM.PRST1.R                /* Peripheral Reset Register 1 */
#define MC_RGM_PRST2         MC_RGM.PRST2.R                /* Peripheral Reset Register 2 */
#define MC_RGM_PRST3         MC_RGM.PRST3.R                /* Peripheral Reset Register 3 */
#define MC_RGM_PRST4         MC_RGM.PRST4.R                /* Peripheral Reset Register 4 */
#define MC_RGM_PRST5         MC_RGM.PRST5.R                /* Peripheral Reset Register 5 */
#define MC_RGM_PRST6         MC_RGM.PRST6.R                /* Peripheral Reset Register 6 */
#define MC_RGM_PRST7         MC_RGM.PRST7.R                /* Peripheral Reset Register 7 */

/* MEMU */
#define MEMU_CTRL            MEMU.CTRL.R                   /* Control register */
#define MEMU_ERR_FLAG        MEMU.ERR_FLAG.R               /* Error flag register */
#define MEMU_DEBUG           MEMU.DEBUG.R                  /* Debug register */
#define MEMU_SYS_RAM_CERR_STS0 MEMU.SYS_RAM_CERR[0].STS.R  /* System RAM correctable error reporting table status register */
#define MEMU_SYS_RAM_CERR_ADDR0 MEMU.SYS_RAM_CERR[0].ADDR.R /* System RAM correctable error reporting table address register */
#define MEMU_SYS_RAM_CERR_STS1 MEMU.SYS_RAM_CERR[1].STS.R  /* System RAM correctable error reporting table status register */
#define MEMU_SYS_RAM_CERR_ADDR1 MEMU.SYS_RAM_CERR[1].ADDR.R /* System RAM correctable error reporting table address register */
#define MEMU_SYS_RAM_CERR_STS2 MEMU.SYS_RAM_CERR[2].STS.R  /* System RAM correctable error reporting table status register */
#define MEMU_SYS_RAM_CERR_ADDR2 MEMU.SYS_RAM_CERR[2].ADDR.R /* System RAM correctable error reporting table address register */
#define MEMU_SYS_RAM_CERR_STS3 MEMU.SYS_RAM_CERR[3].STS.R  /* System RAM correctable error reporting table status register */
#define MEMU_SYS_RAM_CERR_ADDR3 MEMU.SYS_RAM_CERR[3].ADDR.R /* System RAM correctable error reporting table address register */
#define MEMU_SYS_RAM_CERR_STS4 MEMU.SYS_RAM_CERR[4].STS.R  /* System RAM correctable error reporting table status register */
#define MEMU_SYS_RAM_CERR_ADDR4 MEMU.SYS_RAM_CERR[4].ADDR.R /* System RAM correctable error reporting table address register */
#define MEMU_SYS_RAM_CERR_STS5 MEMU.SYS_RAM_CERR[5].STS.R  /* System RAM correctable error reporting table status register */
#define MEMU_SYS_RAM_CERR_ADDR5 MEMU.SYS_RAM_CERR[5].ADDR.R /* System RAM correctable error reporting table address register */
#define MEMU_SYS_RAM_CERR_STS6 MEMU.SYS_RAM_CERR[6].STS.R  /* System RAM correctable error reporting table status register */
#define MEMU_SYS_RAM_CERR_ADDR6 MEMU.SYS_RAM_CERR[6].ADDR.R /* System RAM correctable error reporting table address register */
#define MEMU_SYS_RAM_CERR_STS7 MEMU.SYS_RAM_CERR[7].STS.R  /* System RAM correctable error reporting table status register */
#define MEMU_SYS_RAM_CERR_ADDR7 MEMU.SYS_RAM_CERR[7].ADDR.R /* System RAM correctable error reporting table address register */
#define MEMU_SYS_RAM_CERR_STS8 MEMU.SYS_RAM_CERR[8].STS.R  /* System RAM correctable error reporting table status register */
#define MEMU_SYS_RAM_CERR_ADDR8 MEMU.SYS_RAM_CERR[8].ADDR.R /* System RAM correctable error reporting table address register */
#define MEMU_SYS_RAM_CERR_STS9 MEMU.SYS_RAM_CERR[9].STS.R  /* System RAM correctable error reporting table status register */
#define MEMU_SYS_RAM_CERR_ADDR9 MEMU.SYS_RAM_CERR[9].ADDR.R /* System RAM correctable error reporting table address register */
#define MEMU_SYS_RAM_UNCERR_STS MEMU.SYS_RAM_UNCERR_STS.R  /* System RAM uncorrectable error reporting table status register */
#define MEMU_SYS_RAM_UNCERR_ADDR MEMU.SYS_RAM_UNCERR_ADDR.R /* System RAM uncorrectable error reporting table address register */
#define MEMU_SYS_RAM_OFLW0   MEMU.SYS_RAM_OFLW[0].R        /* System RAM concurrent overflow register */
#define MEMU_SYS_RAM_OFLW1   MEMU.SYS_RAM_OFLW[1].R        /* System RAM concurrent overflow register */
#define MEMU_SYS_RAM_OFLW2   MEMU.SYS_RAM_OFLW[2].R        /* System RAM concurrent overflow register */
#define MEMU_PERIPH_RAM_CERR_STS0 MEMU.PERIPH_RAM_CERR[0].STS.R /* Peripheral RAM correctable error reporting table status register */
#define MEMU_PERIPH_RAM_CERR_ADDR0 MEMU.PERIPH_RAM_CERR[0].ADDR.R /* Peripheral RAM correctable error reporting table address register */
#define MEMU_PERIPH_RAM_CERR_STS1 MEMU.PERIPH_RAM_CERR[1].STS.R /* Peripheral RAM correctable error reporting table status register */
#define MEMU_PERIPH_RAM_CERR_ADDR1 MEMU.PERIPH_RAM_CERR[1].ADDR.R /* Peripheral RAM correctable error reporting table address register */
#define MEMU_PERIPH_RAM_UNCERR_STS MEMU.PERIPH_RAM_UNCERR_STS.R /* Peripheral RAM uncorrectable error reporting table status register */
#define MEMU_PERIPH_RAM_UNCERR_ADDR MEMU.PERIPH_RAM_UNCERR_ADDR.R /* Peripheral RAM uncorrectable error reporting table address register */
#define MEMU_PERIPH_RAM_OFLW0 MEMU.PERIPH_RAM_OFLW0.R      /* Peripheral RAM concurrent overflow register */
#define MEMU_FLASH_CERR_STS0 MEMU.FLASH_CERR[0].STS.R      /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR0 MEMU.FLASH_CERR[0].ADDR.R    /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_CERR_STS1 MEMU.FLASH_CERR[1].STS.R      /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR1 MEMU.FLASH_CERR[1].ADDR.R    /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_CERR_STS2 MEMU.FLASH_CERR[2].STS.R      /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR2 MEMU.FLASH_CERR[2].ADDR.R    /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_CERR_STS3 MEMU.FLASH_CERR[3].STS.R      /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR3 MEMU.FLASH_CERR[3].ADDR.R    /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_CERR_STS4 MEMU.FLASH_CERR[4].STS.R      /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR4 MEMU.FLASH_CERR[4].ADDR.R    /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_CERR_STS5 MEMU.FLASH_CERR[5].STS.R      /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR5 MEMU.FLASH_CERR[5].ADDR.R    /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_CERR_STS6 MEMU.FLASH_CERR[6].STS.R      /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR6 MEMU.FLASH_CERR[6].ADDR.R    /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_CERR_STS7 MEMU.FLASH_CERR[7].STS.R      /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR7 MEMU.FLASH_CERR[7].ADDR.R    /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_CERR_STS8 MEMU.FLASH_CERR[8].STS.R      /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR8 MEMU.FLASH_CERR[8].ADDR.R    /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_CERR_STS9 MEMU.FLASH_CERR[9].STS.R      /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR9 MEMU.FLASH_CERR[9].ADDR.R    /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_CERR_STS10 MEMU.FLASH_CERR[10].STS.R    /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR10 MEMU.FLASH_CERR[10].ADDR.R  /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_CERR_STS11 MEMU.FLASH_CERR[11].STS.R    /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR11 MEMU.FLASH_CERR[11].ADDR.R  /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_CERR_STS12 MEMU.FLASH_CERR[12].STS.R    /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR12 MEMU.FLASH_CERR[12].ADDR.R  /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_CERR_STS13 MEMU.FLASH_CERR[13].STS.R    /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR13 MEMU.FLASH_CERR[13].ADDR.R  /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_CERR_STS14 MEMU.FLASH_CERR[14].STS.R    /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR14 MEMU.FLASH_CERR[14].ADDR.R  /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_CERR_STS15 MEMU.FLASH_CERR[15].STS.R    /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR15 MEMU.FLASH_CERR[15].ADDR.R  /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_CERR_STS16 MEMU.FLASH_CERR[16].STS.R    /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR16 MEMU.FLASH_CERR[16].ADDR.R  /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_CERR_STS17 MEMU.FLASH_CERR[17].STS.R    /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR17 MEMU.FLASH_CERR[17].ADDR.R  /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_CERR_STS18 MEMU.FLASH_CERR[18].STS.R    /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR18 MEMU.FLASH_CERR[18].ADDR.R  /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_CERR_STS19 MEMU.FLASH_CERR[19].STS.R    /* Flash memory correctable error reporting table status register */
#define MEMU_FLASH_CERR_ADDR19 MEMU.FLASH_CERR[19].ADDR.R  /* Flash memory correctable error reporting table address register */
#define MEMU_FLASH_UNCERR_STS MEMU.FLASH_UNCERR_STS.R      /* Flash memory uncorrectable error reporting table status register */
#define MEMU_FLASH_UNCERR_ADDR MEMU.FLASH_UNCERR_ADDR.R    /* Flash memory uncorrectable error reporting table address register */
#define MEMU_FLASH_OFLW0     MEMU.FLASH_OFLW0.R            /* Flash memory concurrent overflow register */

/* M_CAN */
#define M_CAN_1_CREL         M_CAN_1.CREL.R                /* Core Release Register */
#define M_CAN_1_ENDN         M_CAN_1.ENDN.R                /* Endian Register */
#define M_CAN_1_FBTP         M_CAN_1.FBTP.R                /* Fast Bit Timing and Prescaler Register */
#define M_CAN_1_TEST         M_CAN_1.TEST.R                /* Test Register */
#define M_CAN_1_RWD          M_CAN_1.RWD.R                 /* RAM Watchdog Register */
#define M_CAN_1_CCCR         M_CAN_1.CCCR.R                /* CC Control Register */
#define M_CAN_1_BTP          M_CAN_1.BTP.R                 /* Bit Timing and Prescaler Register */
#define M_CAN_1_TSCC         M_CAN_1.TSCC.R                /* Timestamp Counter Configuration Register */
#define M_CAN_1_TSCV         M_CAN_1.TSCV.R                /* Timestamp Counter Value Register */
#define M_CAN_1_TOCC         M_CAN_1.TOCC.R                /* Timeout Counter Configuration Register */
#define M_CAN_1_TOCV         M_CAN_1.TOCV.R                /* Timeout Counter Value Register */
#define M_CAN_1_ECR          M_CAN_1.ECR.R                 /* Error Counter Register */
#define M_CAN_1_PSR          M_CAN_1.PSR.R                 /* Protocol Status Register */
#define M_CAN_1_IR           M_CAN_1.IR.R                  /* Interrupt Register */
#define M_CAN_1_IE           M_CAN_1.IE.R                  /* Interrupt Enable Register */
#define M_CAN_1_ILS          M_CAN_1.ILS.R                 /* Interrupt Line Select Register */
#define M_CAN_1_ILE          M_CAN_1.ILE.R                 /* Interrupt Line Enable Register */
#define M_CAN_1_GFC          M_CAN_1.GFC.R                 /* Global Filter Configuration Register */
#define M_CAN_1_SIDFC        M_CAN_1.SIDFC.R               /* Standard ID Filter Configuration Register */
#define M_CAN_1_XIDFC        M_CAN_1.XIDFC.R               /* Extended ID Filter Configuration Register */
#define M_CAN_1_XIDAM        M_CAN_1.XIDAM.R               /* Extended ID and Mask Register */
#define M_CAN_1_HPMS         M_CAN_1.HPMS.R                /* High Priority Message Status Register */
#define M_CAN_1_NDAT1        M_CAN_1.NDAT1.R               /* New Data 1 Register */
#define M_CAN_1_NDAT2        M_CAN_1.NDAT2.R               /* New Data 2 Register */
#define M_CAN_1_RXF0C        M_CAN_1.RXF0C.R               /* Rx FIFO 0 Configuration */
#define M_CAN_1_RXF0S        M_CAN_1.RXF0S.R               /* Rx FIFO 0 Status Register */
#define M_CAN_1_RXF0A        M_CAN_1.RXF0A.R               /* Rx FIFO 0 Acknowledge Register */
#define M_CAN_1_RXBC         M_CAN_1.RXBC.R                /* Rx Buffer Configuration Register */
#define M_CAN_1_RXF1C        M_CAN_1.RXF1C.R               /* Rx FIFO 1 Configuration Register */
#define M_CAN_1_RXF1S        M_CAN_1.RXF1S.R               /* Rx FIFO 1 Status Register */
#define M_CAN_1_RXF1A        M_CAN_1.RXF1A.R               /* Rx FIFO 1 Acknowledge Register */
#define M_CAN_1_RXESC        M_CAN_1.RXESC.R               /* Rx Buffer / FIFO Element Size Configuration Register */
#define M_CAN_1_TXBC         M_CAN_1.TXBC.R                /* Tx Buffer Configuration Register */
#define M_CAN_1_TXFQS        M_CAN_1.TXFQS.R               /* Tx FIFO/Queue Status Register */
#define M_CAN_1_TXESC        M_CAN_1.TXESC.R               /* Tx Buffer Element Size Configuration */
#define M_CAN_1_TXBRP        M_CAN_1.TXBRP.R               /* Tx Buffer Request Pending Register */
#define M_CAN_1_TXBAR        M_CAN_1.TXBAR.R               /* Tx Buffer Add Request register */
#define M_CAN_1_TXBCR        M_CAN_1.TXBCR.R               /* Tx Buffer Cancellation Request register */
#define M_CAN_1_TXBTO        M_CAN_1.TXBTO.R               /* Tx Buffer Transmission Occurred register */
#define M_CAN_1_TXBCF        M_CAN_1.TXBCF.R               /* Tx Buffer Cancellation Finished register */
#define M_CAN_1_TXBTIE       M_CAN_1.TXBTIE.R              /* Tx Buffer Transmission Interrupt Enable register */
#define M_CAN_1_TXBCIE       M_CAN_1.TXBCIE.R              /* Tx Buffer Cancellation Finished Interrupt Enable register */
#define M_CAN_1_TXEFC        M_CAN_1.TXEFC.R               /* Tx Event FIFO Configuration Register */
#define M_CAN_1_TXEFS        M_CAN_1.TXEFS.R               /* Tx Event FIFO Status register */
#define M_CAN_1_TXEFA        M_CAN_1.TXEFA.R               /* Tx Event FIFO Acknowledge register */

/* M_CAN */
#define M_CAN_2_CREL         M_CAN_2.CREL.R                /* Core Release Register */
#define M_CAN_2_ENDN         M_CAN_2.ENDN.R                /* Endian Register */
#define M_CAN_2_FBTP         M_CAN_2.FBTP.R                /* Fast Bit Timing and Prescaler Register */
#define M_CAN_2_TEST         M_CAN_2.TEST.R                /* Test Register */
#define M_CAN_2_RWD          M_CAN_2.RWD.R                 /* RAM Watchdog Register */
#define M_CAN_2_CCCR         M_CAN_2.CCCR.R                /* CC Control Register */
#define M_CAN_2_BTP          M_CAN_2.BTP.R                 /* Bit Timing and Prescaler Register */
#define M_CAN_2_TSCC         M_CAN_2.TSCC.R                /* Timestamp Counter Configuration Register */
#define M_CAN_2_TSCV         M_CAN_2.TSCV.R                /* Timestamp Counter Value Register */
#define M_CAN_2_TOCC         M_CAN_2.TOCC.R                /* Timeout Counter Configuration Register */
#define M_CAN_2_TOCV         M_CAN_2.TOCV.R                /* Timeout Counter Value Register */
#define M_CAN_2_ECR          M_CAN_2.ECR.R                 /* Error Counter Register */
#define M_CAN_2_PSR          M_CAN_2.PSR.R                 /* Protocol Status Register */
#define M_CAN_2_IR           M_CAN_2.IR.R                  /* Interrupt Register */
#define M_CAN_2_IE           M_CAN_2.IE.R                  /* Interrupt Enable Register */
#define M_CAN_2_ILS          M_CAN_2.ILS.R                 /* Interrupt Line Select Register */
#define M_CAN_2_ILE          M_CAN_2.ILE.R                 /* Interrupt Line Enable Register */
#define M_CAN_2_GFC          M_CAN_2.GFC.R                 /* Global Filter Configuration Register */
#define M_CAN_2_SIDFC        M_CAN_2.SIDFC.R               /* Standard ID Filter Configuration Register */
#define M_CAN_2_XIDFC        M_CAN_2.XIDFC.R               /* Extended ID Filter Configuration Register */
#define M_CAN_2_XIDAM        M_CAN_2.XIDAM.R               /* Extended ID and Mask Register */
#define M_CAN_2_HPMS         M_CAN_2.HPMS.R                /* High Priority Message Status Register */
#define M_CAN_2_NDAT1        M_CAN_2.NDAT1.R               /* New Data 1 Register */
#define M_CAN_2_NDAT2        M_CAN_2.NDAT2.R               /* New Data 2 Register */
#define M_CAN_2_RXF0C        M_CAN_2.RXF0C.R               /* Rx FIFO 0 Configuration */
#define M_CAN_2_RXF0S        M_CAN_2.RXF0S.R               /* Rx FIFO 0 Status Register */
#define M_CAN_2_RXF0A        M_CAN_2.RXF0A.R               /* Rx FIFO 0 Acknowledge Register */
#define M_CAN_2_RXBC         M_CAN_2.RXBC.R                /* Rx Buffer Configuration Register */
#define M_CAN_2_RXF1C        M_CAN_2.RXF1C.R               /* Rx FIFO 1 Configuration Register */
#define M_CAN_2_RXF1S        M_CAN_2.RXF1S.R               /* Rx FIFO 1 Status Register */
#define M_CAN_2_RXF1A        M_CAN_2.RXF1A.R               /* Rx FIFO 1 Acknowledge Register */
#define M_CAN_2_RXESC        M_CAN_2.RXESC.R               /* Rx Buffer / FIFO Element Size Configuration Register */
#define M_CAN_2_TXBC         M_CAN_2.TXBC.R                /* Tx Buffer Configuration Register */
#define M_CAN_2_TXFQS        M_CAN_2.TXFQS.R               /* Tx FIFO/Queue Status Register */
#define M_CAN_2_TXESC        M_CAN_2.TXESC.R               /* Tx Buffer Element Size Configuration */
#define M_CAN_2_TXBRP        M_CAN_2.TXBRP.R               /* Tx Buffer Request Pending Register */
#define M_CAN_2_TXBAR        M_CAN_2.TXBAR.R               /* Tx Buffer Add Request register */
#define M_CAN_2_TXBCR        M_CAN_2.TXBCR.R               /* Tx Buffer Cancellation Request register */
#define M_CAN_2_TXBTO        M_CAN_2.TXBTO.R               /* Tx Buffer Transmission Occurred register */
#define M_CAN_2_TXBCF        M_CAN_2.TXBCF.R               /* Tx Buffer Cancellation Finished register */
#define M_CAN_2_TXBTIE       M_CAN_2.TXBTIE.R              /* Tx Buffer Transmission Interrupt Enable register */
#define M_CAN_2_TXBCIE       M_CAN_2.TXBCIE.R              /* Tx Buffer Cancellation Finished Interrupt Enable register */
#define M_CAN_2_TXEFC        M_CAN_2.TXEFC.R               /* Tx Event FIFO Configuration Register */
#define M_CAN_2_TXEFS        M_CAN_2.TXEFS.R               /* Tx Event FIFO Status register */
#define M_CAN_2_TXEFA        M_CAN_2.TXEFA.R               /* Tx Event FIFO Acknowledge register */

/* M_CAN */
#define M_CAN_3_CREL         M_CAN_3.CREL.R                /* Core Release Register */
#define M_CAN_3_ENDN         M_CAN_3.ENDN.R                /* Endian Register */
#define M_CAN_3_FBTP         M_CAN_3.FBTP.R                /* Fast Bit Timing and Prescaler Register */
#define M_CAN_3_TEST         M_CAN_3.TEST.R                /* Test Register */
#define M_CAN_3_RWD          M_CAN_3.RWD.R                 /* RAM Watchdog Register */
#define M_CAN_3_CCCR         M_CAN_3.CCCR.R                /* CC Control Register */
#define M_CAN_3_BTP          M_CAN_3.BTP.R                 /* Bit Timing and Prescaler Register */
#define M_CAN_3_TSCC         M_CAN_3.TSCC.R                /* Timestamp Counter Configuration Register */
#define M_CAN_3_TSCV         M_CAN_3.TSCV.R                /* Timestamp Counter Value Register */
#define M_CAN_3_TOCC         M_CAN_3.TOCC.R                /* Timeout Counter Configuration Register */
#define M_CAN_3_TOCV         M_CAN_3.TOCV.R                /* Timeout Counter Value Register */
#define M_CAN_3_ECR          M_CAN_3.ECR.R                 /* Error Counter Register */
#define M_CAN_3_PSR          M_CAN_3.PSR.R                 /* Protocol Status Register */
#define M_CAN_3_IR           M_CAN_3.IR.R                  /* Interrupt Register */
#define M_CAN_3_IE           M_CAN_3.IE.R                  /* Interrupt Enable Register */
#define M_CAN_3_ILS          M_CAN_3.ILS.R                 /* Interrupt Line Select Register */
#define M_CAN_3_ILE          M_CAN_3.ILE.R                 /* Interrupt Line Enable Register */
#define M_CAN_3_GFC          M_CAN_3.GFC.R                 /* Global Filter Configuration Register */
#define M_CAN_3_SIDFC        M_CAN_3.SIDFC.R               /* Standard ID Filter Configuration Register */
#define M_CAN_3_XIDFC        M_CAN_3.XIDFC.R               /* Extended ID Filter Configuration Register */
#define M_CAN_3_XIDAM        M_CAN_3.XIDAM.R               /* Extended ID and Mask Register */
#define M_CAN_3_HPMS         M_CAN_3.HPMS.R                /* High Priority Message Status Register */
#define M_CAN_3_NDAT1        M_CAN_3.NDAT1.R               /* New Data 1 Register */
#define M_CAN_3_NDAT2        M_CAN_3.NDAT2.R               /* New Data 2 Register */
#define M_CAN_3_RXF0C        M_CAN_3.RXF0C.R               /* Rx FIFO 0 Configuration */
#define M_CAN_3_RXF0S        M_CAN_3.RXF0S.R               /* Rx FIFO 0 Status Register */
#define M_CAN_3_RXF0A        M_CAN_3.RXF0A.R               /* Rx FIFO 0 Acknowledge Register */
#define M_CAN_3_RXBC         M_CAN_3.RXBC.R                /* Rx Buffer Configuration Register */
#define M_CAN_3_RXF1C        M_CAN_3.RXF1C.R               /* Rx FIFO 1 Configuration Register */
#define M_CAN_3_RXF1S        M_CAN_3.RXF1S.R               /* Rx FIFO 1 Status Register */
#define M_CAN_3_RXF1A        M_CAN_3.RXF1A.R               /* Rx FIFO 1 Acknowledge Register */
#define M_CAN_3_RXESC        M_CAN_3.RXESC.R               /* Rx Buffer / FIFO Element Size Configuration Register */
#define M_CAN_3_TXBC         M_CAN_3.TXBC.R                /* Tx Buffer Configuration Register */
#define M_CAN_3_TXFQS        M_CAN_3.TXFQS.R               /* Tx FIFO/Queue Status Register */
#define M_CAN_3_TXESC        M_CAN_3.TXESC.R               /* Tx Buffer Element Size Configuration */
#define M_CAN_3_TXBRP        M_CAN_3.TXBRP.R               /* Tx Buffer Request Pending Register */
#define M_CAN_3_TXBAR        M_CAN_3.TXBAR.R               /* Tx Buffer Add Request register */
#define M_CAN_3_TXBCR        M_CAN_3.TXBCR.R               /* Tx Buffer Cancellation Request register */
#define M_CAN_3_TXBTO        M_CAN_3.TXBTO.R               /* Tx Buffer Transmission Occurred register */
#define M_CAN_3_TXBCF        M_CAN_3.TXBCF.R               /* Tx Buffer Cancellation Finished register */
#define M_CAN_3_TXBTIE       M_CAN_3.TXBTIE.R              /* Tx Buffer Transmission Interrupt Enable register */
#define M_CAN_3_TXBCIE       M_CAN_3.TXBCIE.R              /* Tx Buffer Cancellation Finished Interrupt Enable register */
#define M_CAN_3_TXEFC        M_CAN_3.TXEFC.R               /* Tx Event FIFO Configuration Register */
#define M_CAN_3_TXEFS        M_CAN_3.TXEFS.R               /* Tx Event FIFO Status register */
#define M_CAN_3_TXEFA        M_CAN_3.TXEFA.R               /* Tx Event FIFO Acknowledge register */

/* M_CAN */
#define M_CAN_4_CREL         M_CAN_4.CREL.R                /* Core Release Register */
#define M_CAN_4_ENDN         M_CAN_4.ENDN.R                /* Endian Register */
#define M_CAN_4_FBTP         M_CAN_4.FBTP.R                /* Fast Bit Timing and Prescaler Register */
#define M_CAN_4_TEST         M_CAN_4.TEST.R                /* Test Register */
#define M_CAN_4_RWD          M_CAN_4.RWD.R                 /* RAM Watchdog Register */
#define M_CAN_4_CCCR         M_CAN_4.CCCR.R                /* CC Control Register */
#define M_CAN_4_BTP          M_CAN_4.BTP.R                 /* Bit Timing and Prescaler Register */
#define M_CAN_4_TSCC         M_CAN_4.TSCC.R                /* Timestamp Counter Configuration Register */
#define M_CAN_4_TSCV         M_CAN_4.TSCV.R                /* Timestamp Counter Value Register */
#define M_CAN_4_TOCC         M_CAN_4.TOCC.R                /* Timeout Counter Configuration Register */
#define M_CAN_4_TOCV         M_CAN_4.TOCV.R                /* Timeout Counter Value Register */
#define M_CAN_4_ECR          M_CAN_4.ECR.R                 /* Error Counter Register */
#define M_CAN_4_PSR          M_CAN_4.PSR.R                 /* Protocol Status Register */
#define M_CAN_4_IR           M_CAN_4.IR.R                  /* Interrupt Register */
#define M_CAN_4_IE           M_CAN_4.IE.R                  /* Interrupt Enable Register */
#define M_CAN_4_ILS          M_CAN_4.ILS.R                 /* Interrupt Line Select Register */
#define M_CAN_4_ILE          M_CAN_4.ILE.R                 /* Interrupt Line Enable Register */
#define M_CAN_4_GFC          M_CAN_4.GFC.R                 /* Global Filter Configuration Register */
#define M_CAN_4_SIDFC        M_CAN_4.SIDFC.R               /* Standard ID Filter Configuration Register */
#define M_CAN_4_XIDFC        M_CAN_4.XIDFC.R               /* Extended ID Filter Configuration Register */
#define M_CAN_4_XIDAM        M_CAN_4.XIDAM.R               /* Extended ID and Mask Register */
#define M_CAN_4_HPMS         M_CAN_4.HPMS.R                /* High Priority Message Status Register */
#define M_CAN_4_NDAT1        M_CAN_4.NDAT1.R               /* New Data 1 Register */
#define M_CAN_4_NDAT2        M_CAN_4.NDAT2.R               /* New Data 2 Register */
#define M_CAN_4_RXF0C        M_CAN_4.RXF0C.R               /* Rx FIFO 0 Configuration */
#define M_CAN_4_RXF0S        M_CAN_4.RXF0S.R               /* Rx FIFO 0 Status Register */
#define M_CAN_4_RXF0A        M_CAN_4.RXF0A.R               /* Rx FIFO 0 Acknowledge Register */
#define M_CAN_4_RXBC         M_CAN_4.RXBC.R                /* Rx Buffer Configuration Register */
#define M_CAN_4_RXF1C        M_CAN_4.RXF1C.R               /* Rx FIFO 1 Configuration Register */
#define M_CAN_4_RXF1S        M_CAN_4.RXF1S.R               /* Rx FIFO 1 Status Register */
#define M_CAN_4_RXF1A        M_CAN_4.RXF1A.R               /* Rx FIFO 1 Acknowledge Register */
#define M_CAN_4_RXESC        M_CAN_4.RXESC.R               /* Rx Buffer / FIFO Element Size Configuration Register */
#define M_CAN_4_TXBC         M_CAN_4.TXBC.R                /* Tx Buffer Configuration Register */
#define M_CAN_4_TXFQS        M_CAN_4.TXFQS.R               /* Tx FIFO/Queue Status Register */
#define M_CAN_4_TXESC        M_CAN_4.TXESC.R               /* Tx Buffer Element Size Configuration */
#define M_CAN_4_TXBRP        M_CAN_4.TXBRP.R               /* Tx Buffer Request Pending Register */
#define M_CAN_4_TXBAR        M_CAN_4.TXBAR.R               /* Tx Buffer Add Request register */
#define M_CAN_4_TXBCR        M_CAN_4.TXBCR.R               /* Tx Buffer Cancellation Request register */
#define M_CAN_4_TXBTO        M_CAN_4.TXBTO.R               /* Tx Buffer Transmission Occurred register */
#define M_CAN_4_TXBCF        M_CAN_4.TXBCF.R               /* Tx Buffer Cancellation Finished register */
#define M_CAN_4_TXBTIE       M_CAN_4.TXBTIE.R              /* Tx Buffer Transmission Interrupt Enable register */
#define M_CAN_4_TXBCIE       M_CAN_4.TXBCIE.R              /* Tx Buffer Cancellation Finished Interrupt Enable register */
#define M_CAN_4_TXEFC        M_CAN_4.TXEFC.R               /* Tx Event FIFO Configuration Register */
#define M_CAN_4_TXEFS        M_CAN_4.TXEFS.R               /* Tx Event FIFO Status register */
#define M_CAN_4_TXEFA        M_CAN_4.TXEFA.R               /* Tx Event FIFO Acknowledge register */

/* M_TTCAN */
#define M_TTCAN_CREL         M_TTCAN.CREL.R                /* Core Release Register */
#define M_TTCAN_ENDN         M_TTCAN.ENDN.R                /* Endian Register */
#define M_TTCAN_FBTP         M_TTCAN.FBTP.R                /* Fast Bit Timing and Prescaler Register */
#define M_TTCAN_TEST         M_TTCAN.TEST.R                /* Test Register */
#define M_TTCAN_RWD          M_TTCAN.RWD.R                 /* RAM Watchdog Register */
#define M_TTCAN_CCCR         M_TTCAN.CCCR.R                /* CC Control Register */
#define M_TTCAN_BTP          M_TTCAN.BTP.R                 /* Bit Timing and Prescaler Register */
#define M_TTCAN_TSCC         M_TTCAN.TSCC.R                /* Timestamp Counter Configuration Register */
#define M_TTCAN_TSCV         M_TTCAN.TSCV.R                /* Timestamp Counter Value Register */
#define M_TTCAN_TOCC         M_TTCAN.TOCC.R                /* Timeout Counter Configuration Register */
#define M_TTCAN_TOCV         M_TTCAN.TOCV.R                /* Timeout Counter Value Register */
#define M_TTCAN_ECR          M_TTCAN.ECR.R                 /* Error Counter Register */
#define M_TTCAN_PSR          M_TTCAN.PSR.R                 /* Protocol Status Register */
#define M_TTCAN_IR           M_TTCAN.IR.R                  /* Interrupt Register */
#define M_TTCAN_IE           M_TTCAN.IE.R                  /* Interrupt Enable Register */
#define M_TTCAN_ILS          M_TTCAN.ILS.R                 /* Interrupt Line Select Register */
#define M_TTCAN_ILE          M_TTCAN.ILE.R                 /* Interrupt Line Enable Register */
#define M_TTCAN_GFC          M_TTCAN.GFC.R                 /* Global Filter Configuration Register */
#define M_TTCAN_SIDFC        M_TTCAN.SIDFC.R               /* Standard ID Filter Configuration Register */
#define M_TTCAN_XIDFC        M_TTCAN.XIDFC.R               /* Extended ID Filter Configuration Register */
#define M_TTCAN_XIDAM        M_TTCAN.XIDAM.R               /* Extended ID and Mask Register */
#define M_TTCAN_HPMS         M_TTCAN.HPMS.R                /* High Priority Message Status Register */
#define M_TTCAN_NDAT1        M_TTCAN.NDAT1.R               /* New Data 1 Register */
#define M_TTCAN_NDAT2        M_TTCAN.NDAT2.R               /* New Data 2 Register */
#define M_TTCAN_RXF0C        M_TTCAN.RXF0C.R               /* Rx FIFO 0 Configuration Register */
#define M_TTCAN_RXF0S        M_TTCAN.RXF0S.R               /* Rx FIFO 0 Status Register */
#define M_TTCAN_RXF0A        M_TTCAN.RXF0A.R               /* Rx FIFO 0 Acknowledge Register */
#define M_TTCAN_RXBC         M_TTCAN.RXBC.R                /* Rx Buffer Configuration Register */
#define M_TTCAN_RXF1C        M_TTCAN.RXF1C.R               /* Rx FIFO 1 Configuration Register */
#define M_TTCAN_RXF1S        M_TTCAN.RXF1S.R               /* Rx FIFO 1 Status Register */
#define M_TTCAN_RXF1A        M_TTCAN.RXF1A.R               /* Rx FIFO 1 Acknowledge register */
#define M_TTCAN_TXBC         M_TTCAN.TXBC.R                /* Tx Buffer Configuration register */
#define M_TTCAN_TXFQS        M_TTCAN.TXFQS.R               /* Tx FIFO/Queue Status register */
#define M_TTCAN_TXBRP        M_TTCAN.TXBRP.R               /* Tx Buffer Request Pending register */
#define M_TTCAN_TXBAR        M_TTCAN.TXBAR.R               /* Tx Buffer Add Request register */
#define M_TTCAN_TXBCR        M_TTCAN.TXBCR.R               /* Tx Buffer Cancellation Request register */
#define M_TTCAN_TXBTO        M_TTCAN.TXBTO.R               /* Tx Buffer Transmission Occurred register */
#define M_TTCAN_TXBCF        M_TTCAN.TXBCF.R               /* Tx Buffer Cancellation Finished register */
#define M_TTCAN_TXBTIE       M_TTCAN.TXBTIE.R              /* Tx Buffer Transmission Interrupt Enable register */
#define M_TTCAN_TXBCIE       M_TTCAN.TXBCIE.R              /* Tx Buffer Cancellation Finished Interrupt Enable register */
#define M_TTCAN_TXEFC        M_TTCAN.TXEFC.R               /* Tx Event FIFO Configuration register */
#define M_TTCAN_TXEFS        M_TTCAN.TXEFS.R               /* Tx Event FIFO Status register */
#define M_TTCAN_TXEFA        M_TTCAN.TXEFA.R               /* Tx Event FIFO Acknowledge register */
#define M_TTCAN_TTTMC        M_TTCAN.TTTMC.R               /* TT Trigger Memory Configuration register */
#define M_TTCAN_TTRMC        M_TTCAN.TTRMC.R               /* TT Reference Message Configuration register */
#define M_TTCAN_TTOCF        M_TTCAN.TTOCF.R               /* TT Operation Configuration register */
#define M_TTCAN_TTMLM        M_TTCAN.TTMLM.R               /* TT Matrix Limits register */
#define M_TTCAN_TURCF        M_TTCAN.TURCF.R               /* TUR Configuration register */
#define M_TTCAN_TTOCN        M_TTCAN.TTOCN.R               /* TT Operation Control register */
#define M_TTCAN_TTGTP        M_TTCAN.TTGTP.R               /* TT Global Time Preset register */
#define M_TTCAN_TTTMK        M_TTCAN.TTTMK.R               /* TT Time Mark register */
#define M_TTCAN_TTIR         M_TTCAN.TTIR.R                /* TT Interrupt Register */
#define M_TTCAN_TTIE         M_TTCAN.TTIE.R                /* TT Interrupt Enable register */
#define M_TTCAN_TTILS        M_TTCAN.TTILS.R               /* TT Interrupt Line Select register */
#define M_TTCAN_TTOST        M_TTCAN.TTOST.R               /* TT Operation Status register */
#define M_TTCAN_TURNA        M_TTCAN.TURNA.R               /* TUR Numerator Actual register */
#define M_TTCAN_TTLGT        M_TTCAN.TTLGT.R               /* TT Local and Global Time register */
#define M_TTCAN_TTCTC        M_TTCAN.TTCTC.R               /* TT Cycle Time and Count register */
#define M_TTCAN_TTCPT        M_TTCAN.TTCPT.R               /* TT Capture Time register */
#define M_TTCAN_TTCSM        M_TTCAN.TTCSM.R               /* TT Cycle Sync Mark register */

/* PASS */
#define PASS_LCSTAT          PASS.LCSTAT.R                 /* Life Cycle Status Register */
#define PASS_CHSEL           PASS.CHSEL.R                  /* Challenge Selector Register */
#define PASS_CSTAT           PASS.CSTAT.R                  /* Challenge Status Register */
#define PASS_CIN0            PASS.CIN[0].R                 /* Challenge Input Register */
#define PASS_CIN1            PASS.CIN[1].R                 /* Challenge Input Register */
#define PASS_CIN2            PASS.CIN[2].R                 /* Challenge Input Register */
#define PASS_CIN3            PASS.CIN[3].R                 /* Challenge Input Register */
#define PASS_CIN4            PASS.CIN[4].R                 /* Challenge Input Register */
#define PASS_CIN5            PASS.CIN[5].R                 /* Challenge Input Register */
#define PASS_CIN6            PASS.CIN[6].R                 /* Challenge Input Register */
#define PASS_CIN7            PASS.CIN[7].R                 /* Challenge Input Register */
#define PASS_CJE             PASS.CJE.R                    /* Clock Jitter Enable */
#define PASS_LOCK0_PG0       PASS.PG[0].LOCK0.R            /* Password Group n - Lock 0 Status Register */
#define PASS_LOCK1_PG0       PASS.PG[0].LOCK1.R            /* Password Group n - Lock 1 Status Register */
#define PASS_LOCK2_PG0       PASS.PG[0].LOCK2.R            /* Password Group n - Lock 2 Status Register */
#define PASS_LOCK3_PG0       PASS.PG[0].LOCK3.R            /* Password Group n - Lock 3 Status Register */
#define PASS_LOCK0_PG1       PASS.PG[1].LOCK0.R            /* Password Group n - Lock 0 Status Register */
#define PASS_LOCK1_PG1       PASS.PG[1].LOCK1.R            /* Password Group n - Lock 1 Status Register */
#define PASS_LOCK2_PG1       PASS.PG[1].LOCK2.R            /* Password Group n - Lock 2 Status Register */
#define PASS_LOCK3_PG1       PASS.PG[1].LOCK3.R            /* Password Group n - Lock 3 Status Register */
#define PASS_LOCK0_PG2       PASS.PG[2].LOCK0.R            /* Password Group n - Lock 0 Status Register */
#define PASS_LOCK1_PG2       PASS.PG[2].LOCK1.R            /* Password Group n - Lock 1 Status Register */
#define PASS_LOCK2_PG2       PASS.PG[2].LOCK2.R            /* Password Group n - Lock 2 Status Register */
#define PASS_LOCK3_PG2       PASS.PG[2].LOCK3.R            /* Password Group n - Lock 3 Status Register */
#define PASS_LOCK0_PG3       PASS.PG[3].LOCK0.R            /* Password Group n - Lock 0 Status Register */
#define PASS_LOCK1_PG3       PASS.PG[3].LOCK1.R            /* Password Group n - Lock 1 Status Register */
#define PASS_LOCK2_PG3       PASS.PG[3].LOCK2.R            /* Password Group n - Lock 2 Status Register */
#define PASS_LOCK3_PG3       PASS.PG[3].LOCK3.R            /* Password Group n - Lock 3 Status Register */

/* PBRIDGE */
#define PBRIDGE_A_MPRA       PBRIDGE_A.MPRA.R              /* Master Privilege Register A */
#define PBRIDGE_A_MPRB       PBRIDGE_A.MPRB.R              /* Master Privilege Register B */
#define PBRIDGE_A_PACRA      PBRIDGE_A.PACR[0].R           /* Peripheral Access Control Register */
#define PBRIDGE_A_PACRB      PBRIDGE_A.PACR[1].R           /* Peripheral Access Control Register */
#define PBRIDGE_A_PACRC      PBRIDGE_A.PACR[2].R           /* Peripheral Access Control Register */
#define PBRIDGE_A_PACRD      PBRIDGE_A.PACR[3].R           /* Peripheral Access Control Register */
#define PBRIDGE_A_PACRE      PBRIDGE_A.PACR[4].R           /* Peripheral Access Control Register */
#define PBRIDGE_A_PACRF      PBRIDGE_A.PACR[5].R           /* Peripheral Access Control Register */
#define PBRIDGE_A_PACRG      PBRIDGE_A.PACR[6].R           /* Peripheral Access Control Register */
#define PBRIDGE_A_PACRH      PBRIDGE_A.PACR[7].R           /* Peripheral Access Control Register */
#define PBRIDGE_A_OPACRA     PBRIDGE_A.OPACR[0].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRB     PBRIDGE_A.OPACR[1].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRC     PBRIDGE_A.OPACR[2].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRD     PBRIDGE_A.OPACR[3].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRE     PBRIDGE_A.OPACR[4].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRF     PBRIDGE_A.OPACR[5].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRG     PBRIDGE_A.OPACR[6].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRH     PBRIDGE_A.OPACR[7].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRI     PBRIDGE_A.OPACR[8].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRJ     PBRIDGE_A.OPACR[9].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRK     PBRIDGE_A.OPACR[10].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRL     PBRIDGE_A.OPACR[11].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRM     PBRIDGE_A.OPACR[12].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRN     PBRIDGE_A.OPACR[13].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRO     PBRIDGE_A.OPACR[14].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRP     PBRIDGE_A.OPACR[15].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRQ     PBRIDGE_A.OPACR[16].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRR     PBRIDGE_A.OPACR[17].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRS     PBRIDGE_A.OPACR[18].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRT     PBRIDGE_A.OPACR[19].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRU     PBRIDGE_A.OPACR[20].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRV     PBRIDGE_A.OPACR[21].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRW     PBRIDGE_A.OPACR[22].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRX     PBRIDGE_A.OPACR[23].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRY     PBRIDGE_A.OPACR[24].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRZ     PBRIDGE_A.OPACR[25].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRAA    PBRIDGE_A.OPACR[26].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRAB    PBRIDGE_A.OPACR[27].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRAC    PBRIDGE_A.OPACR[28].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRAD    PBRIDGE_A.OPACR[29].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRAE    PBRIDGE_A.OPACR[30].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_A_OPACRAF    PBRIDGE_A.OPACR[31].R         /* Off-platform Peripheral Access Control Register */

/* PBRIDGE */
#define PBRIDGE_B_MPRA       PBRIDGE_B.MPRA.R              /* Master Privilege Register A */
#define PBRIDGE_B_MPRB       PBRIDGE_B.MPRB.R              /* Master Privilege Register B */
#define PBRIDGE_B_PACRA      PBRIDGE_B.PACR[0].R           /* Peripheral Access Control Register */
#define PBRIDGE_B_PACRB      PBRIDGE_B.PACR[1].R           /* Peripheral Access Control Register */
#define PBRIDGE_B_PACRC      PBRIDGE_B.PACR[2].R           /* Peripheral Access Control Register */
#define PBRIDGE_B_PACRD      PBRIDGE_B.PACR[3].R           /* Peripheral Access Control Register */
#define PBRIDGE_B_PACRE      PBRIDGE_B.PACR[4].R           /* Peripheral Access Control Register */
#define PBRIDGE_B_PACRF      PBRIDGE_B.PACR[5].R           /* Peripheral Access Control Register */
#define PBRIDGE_B_PACRG      PBRIDGE_B.PACR[6].R           /* Peripheral Access Control Register */
#define PBRIDGE_B_PACRH      PBRIDGE_B.PACR[7].R           /* Peripheral Access Control Register */
#define PBRIDGE_B_OPACRA     PBRIDGE_B.OPACR[0].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRB     PBRIDGE_B.OPACR[1].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRC     PBRIDGE_B.OPACR[2].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRD     PBRIDGE_B.OPACR[3].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRE     PBRIDGE_B.OPACR[4].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRF     PBRIDGE_B.OPACR[5].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRG     PBRIDGE_B.OPACR[6].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRH     PBRIDGE_B.OPACR[7].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRI     PBRIDGE_B.OPACR[8].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRJ     PBRIDGE_B.OPACR[9].R          /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRK     PBRIDGE_B.OPACR[10].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRL     PBRIDGE_B.OPACR[11].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRM     PBRIDGE_B.OPACR[12].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRN     PBRIDGE_B.OPACR[13].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRO     PBRIDGE_B.OPACR[14].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRP     PBRIDGE_B.OPACR[15].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRQ     PBRIDGE_B.OPACR[16].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRR     PBRIDGE_B.OPACR[17].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRS     PBRIDGE_B.OPACR[18].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRT     PBRIDGE_B.OPACR[19].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRU     PBRIDGE_B.OPACR[20].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRV     PBRIDGE_B.OPACR[21].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRW     PBRIDGE_B.OPACR[22].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRX     PBRIDGE_B.OPACR[23].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRY     PBRIDGE_B.OPACR[24].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRZ     PBRIDGE_B.OPACR[25].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRAA    PBRIDGE_B.OPACR[26].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRAB    PBRIDGE_B.OPACR[27].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRAC    PBRIDGE_B.OPACR[28].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRAD    PBRIDGE_B.OPACR[29].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRAE    PBRIDGE_B.OPACR[30].R         /* Off-platform Peripheral Access Control Register */
#define PBRIDGE_B_OPACRAF    PBRIDGE_B.OPACR[31].R         /* Off-platform Peripheral Access Control Register */

/* PCM */
#define PCM_FBOMCR           PCM.FBOMCR.R                  /* FEC Burst Optimization Master Control Register */
#define PCM_IAHB_BE1         PCM.IAHB_BE1.R                /* IAHB Burst Enable 1 Register */
#define PCM_IAHB_BE2         PCM.IAHB_BE2.R                /* IAHB Burst Enable 2 Register */

/* PFLASH */
#define PFLASH_PFCR1         PFLASH.PFCR1.R                /* Platform Flash Configuration Register 1 */
#define PFLASH_PFCR2         PFLASH.PFCR2.R                /* Platform Flash Configuration Register 2 */
#define PFLASH_PFCR3         PFLASH.PFCR3.R                /* Platform Flash Configuration Register 3 */
#define PFLASH_PFAPR         PFLASH.PFAPR.R                /* Platform Flash Access Protection Register */
#define PFLASH_PFCRCR        PFLASH.PFCRCR.R               /* Platform Flash Remap Control Register */
#define PFLASH_PFCRDE        PFLASH.PFCRDE.R               /* Platform Flash Remap Descriptor Enable Register */
#define PFLASH_PFCRD0_Word0  PFLASH.PFCRD[0].Word0.R       /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD0_Word1  PFLASH.PFCRD[0].Word1.R       /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD0_Word2  PFLASH.PFCRD[0].Word2.R       /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD1_Word0  PFLASH.PFCRD[1].Word0.R       /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD1_Word1  PFLASH.PFCRD[1].Word1.R       /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD1_Word2  PFLASH.PFCRD[1].Word2.R       /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD2_Word0  PFLASH.PFCRD[2].Word0.R       /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD2_Word1  PFLASH.PFCRD[2].Word1.R       /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD2_Word2  PFLASH.PFCRD[2].Word2.R       /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD3_Word0  PFLASH.PFCRD[3].Word0.R       /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD3_Word1  PFLASH.PFCRD[3].Word1.R       /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD3_Word2  PFLASH.PFCRD[3].Word2.R       /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD4_Word0  PFLASH.PFCRD[4].Word0.R       /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD4_Word1  PFLASH.PFCRD[4].Word1.R       /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD4_Word2  PFLASH.PFCRD[4].Word2.R       /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD5_Word0  PFLASH.PFCRD[5].Word0.R       /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD5_Word1  PFLASH.PFCRD[5].Word1.R       /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD5_Word2  PFLASH.PFCRD[5].Word2.R       /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD6_Word0  PFLASH.PFCRD[6].Word0.R       /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD6_Word1  PFLASH.PFCRD[6].Word1.R       /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD6_Word2  PFLASH.PFCRD[6].Word2.R       /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD7_Word0  PFLASH.PFCRD[7].Word0.R       /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD7_Word1  PFLASH.PFCRD[7].Word1.R       /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD7_Word2  PFLASH.PFCRD[7].Word2.R       /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD8_Word0  PFLASH.PFCRD[8].Word0.R       /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD8_Word1  PFLASH.PFCRD[8].Word1.R       /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD8_Word2  PFLASH.PFCRD[8].Word2.R       /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD9_Word0  PFLASH.PFCRD[9].Word0.R       /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD9_Word1  PFLASH.PFCRD[9].Word1.R       /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD9_Word2  PFLASH.PFCRD[9].Word2.R       /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD10_Word0 PFLASH.PFCRD[10].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD10_Word1 PFLASH.PFCRD[10].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD10_Word2 PFLASH.PFCRD[10].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD11_Word0 PFLASH.PFCRD[11].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD11_Word1 PFLASH.PFCRD[11].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD11_Word2 PFLASH.PFCRD[11].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD12_Word0 PFLASH.PFCRD[12].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD12_Word1 PFLASH.PFCRD[12].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD12_Word2 PFLASH.PFCRD[12].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD13_Word0 PFLASH.PFCRD[13].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD13_Word1 PFLASH.PFCRD[13].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD13_Word2 PFLASH.PFCRD[13].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD14_Word0 PFLASH.PFCRD[14].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD14_Word1 PFLASH.PFCRD[14].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD14_Word2 PFLASH.PFCRD[14].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD15_Word0 PFLASH.PFCRD[15].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD15_Word1 PFLASH.PFCRD[15].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD15_Word2 PFLASH.PFCRD[15].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD16_Word0 PFLASH.PFCRD[16].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD16_Word1 PFLASH.PFCRD[16].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD16_Word2 PFLASH.PFCRD[16].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD17_Word0 PFLASH.PFCRD[17].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD17_Word1 PFLASH.PFCRD[17].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD17_Word2 PFLASH.PFCRD[17].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD18_Word0 PFLASH.PFCRD[18].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD18_Word1 PFLASH.PFCRD[18].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD18_Word2 PFLASH.PFCRD[18].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD19_Word0 PFLASH.PFCRD[19].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD19_Word1 PFLASH.PFCRD[19].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD19_Word2 PFLASH.PFCRD[19].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD20_Word0 PFLASH.PFCRD[20].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD20_Word1 PFLASH.PFCRD[20].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD20_Word2 PFLASH.PFCRD[20].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD21_Word0 PFLASH.PFCRD[21].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD21_Word1 PFLASH.PFCRD[21].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD21_Word2 PFLASH.PFCRD[21].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD22_Word0 PFLASH.PFCRD[22].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD22_Word1 PFLASH.PFCRD[22].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD22_Word2 PFLASH.PFCRD[22].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD23_Word0 PFLASH.PFCRD[23].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD23_Word1 PFLASH.PFCRD[23].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD23_Word2 PFLASH.PFCRD[23].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD24_Word0 PFLASH.PFCRD[24].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD24_Word1 PFLASH.PFCRD[24].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD24_Word2 PFLASH.PFCRD[24].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD25_Word0 PFLASH.PFCRD[25].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD25_Word1 PFLASH.PFCRD[25].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD25_Word2 PFLASH.PFCRD[25].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD26_Word0 PFLASH.PFCRD[26].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD26_Word1 PFLASH.PFCRD[26].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD26_Word2 PFLASH.PFCRD[26].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD27_Word0 PFLASH.PFCRD[27].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD27_Word1 PFLASH.PFCRD[27].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD27_Word2 PFLASH.PFCRD[27].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD28_Word0 PFLASH.PFCRD[28].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD28_Word1 PFLASH.PFCRD[28].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD28_Word2 PFLASH.PFCRD[28].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD29_Word0 PFLASH.PFCRD[29].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD29_Word1 PFLASH.PFCRD[29].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD29_Word2 PFLASH.PFCRD[29].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD30_Word0 PFLASH.PFCRD[30].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD30_Word1 PFLASH.PFCRD[30].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD30_Word2 PFLASH.PFCRD[30].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */
#define PFLASH_PFCRD31_Word0 PFLASH.PFCRD[31].Word0.R      /* Platform Flash Calibration Region Descriptor n Word0 */
#define PFLASH_PFCRD31_Word1 PFLASH.PFCRD[31].Word1.R      /* Platform Flash Calibration Region Descriptor n Word1 */
#define PFLASH_PFCRD31_Word2 PFLASH.PFCRD[31].Word2.R      /* Platform Flash Calibration Region Descriptor n Word2 */

/* PIT */
#define PIT_0_MCR            PIT_0.MCR.R                   /* PIT Module Control Register */
#define PIT_0_LTMR64H        PIT_0.LTMR64H.R               /* PIT Upper Lifetime Timer Register */
#define PIT_0_LTMR64L        PIT_0.LTMR64L.R               /* PIT Lower Lifetime Timer Register */
#define PIT_0_RTI_LDVAL      PIT_0.RTI_LDVAL.R             /* PIT RTI Timer Load Value Register */
#define PIT_0_RTI_CVAL       PIT_0.RTI_CVAL.R              /* PIT RTI Current Timer Value Register */
#define PIT_0_RTI_TCTRL      PIT_0.RTI_TCTRL.R             /* PIT RTI Timer Control Register */
#define PIT_0_RTI_TFLG       PIT_0.RTI_TFLG.R              /* PIT RTI Timer Flag Register */
#define PIT_0_LDVAL0         PIT_0.TIMER[0].LDVAL.R        /* PIT Timer Load Value Register n */
#define PIT_0_CVAL0          PIT_0.TIMER[0].CVAL.R         /* PIT Current Timer Value Register n */
#define PIT_0_TCTRL0         PIT_0.TIMER[0].TCTRL.R        /* PIT Timer Control Register n */
#define PIT_0_TFLG0          PIT_0.TIMER[0].TFLG.R         /* PIT Timer Flag Register n */
#define PIT_0_LDVAL1         PIT_0.TIMER[1].LDVAL.R        /* PIT Timer Load Value Register n */
#define PIT_0_CVAL1          PIT_0.TIMER[1].CVAL.R         /* PIT Current Timer Value Register n */
#define PIT_0_TCTRL1         PIT_0.TIMER[1].TCTRL.R        /* PIT Timer Control Register n */
#define PIT_0_TFLG1          PIT_0.TIMER[1].TFLG.R         /* PIT Timer Flag Register n */
#define PIT_0_LDVAL2         PIT_0.TIMER[2].LDVAL.R        /* PIT Timer Load Value Register n */
#define PIT_0_CVAL2          PIT_0.TIMER[2].CVAL.R         /* PIT Current Timer Value Register n */
#define PIT_0_TCTRL2         PIT_0.TIMER[2].TCTRL.R        /* PIT Timer Control Register n */
#define PIT_0_TFLG2          PIT_0.TIMER[2].TFLG.R         /* PIT Timer Flag Register n */
#define PIT_0_LDVAL3         PIT_0.TIMER[3].LDVAL.R        /* PIT Timer Load Value Register n */
#define PIT_0_CVAL3          PIT_0.TIMER[3].CVAL.R         /* PIT Current Timer Value Register n */
#define PIT_0_TCTRL3         PIT_0.TIMER[3].TCTRL.R        /* PIT Timer Control Register n */
#define PIT_0_TFLG3          PIT_0.TIMER[3].TFLG.R         /* PIT Timer Flag Register n */
#define PIT_0_LDVAL4         PIT_0.TIMER[4].LDVAL.R        /* PIT Timer Load Value Register n */
#define PIT_0_CVAL4          PIT_0.TIMER[4].CVAL.R         /* PIT Current Timer Value Register n */
#define PIT_0_TCTRL4         PIT_0.TIMER[4].TCTRL.R        /* PIT Timer Control Register n */
#define PIT_0_TFLG4          PIT_0.TIMER[4].TFLG.R         /* PIT Timer Flag Register n */
#define PIT_0_LDVAL5         PIT_0.TIMER[5].LDVAL.R        /* PIT Timer Load Value Register n */
#define PIT_0_CVAL5          PIT_0.TIMER[5].CVAL.R         /* PIT Current Timer Value Register n */
#define PIT_0_TCTRL5         PIT_0.TIMER[5].TCTRL.R        /* PIT Timer Control Register n */
#define PIT_0_TFLG5          PIT_0.TIMER[5].TFLG.R         /* PIT Timer Flag Register n */
#define PIT_0_LDVAL6         PIT_0.TIMER[6].LDVAL.R        /* PIT Timer Load Value Register n */
#define PIT_0_CVAL6          PIT_0.TIMER[6].CVAL.R         /* PIT Current Timer Value Register n */
#define PIT_0_TCTRL6         PIT_0.TIMER[6].TCTRL.R        /* PIT Timer Control Register n */
#define PIT_0_TFLG6          PIT_0.TIMER[6].TFLG.R         /* PIT Timer Flag Register n */
#define PIT_0_LDVAL7         PIT_0.TIMER[7].LDVAL.R        /* PIT Timer Load Value Register n */
#define PIT_0_CVAL7          PIT_0.TIMER[7].CVAL.R         /* PIT Current Timer Value Register n */
#define PIT_0_TCTRL7         PIT_0.TIMER[7].TCTRL.R        /* PIT Timer Control Register n */
#define PIT_0_TFLG7          PIT_0.TIMER[7].TFLG.R         /* PIT Timer Flag Register n */

/* PIT */
#define PIT_1_MCR            PIT_1.MCR.R                   /* PIT Module Control Register */
#define PIT_1_LTMR64H        PIT_1.LTMR64H.R               /* PIT Upper Lifetime Timer Register */
#define PIT_1_LTMR64L        PIT_1.LTMR64L.R               /* PIT Lower Lifetime Timer Register */
#define PIT_1_RTI_LDVAL      PIT_1.RTI_LDVAL.R             /* PIT RTI Timer Load Value Register */
#define PIT_1_RTI_CVAL       PIT_1.RTI_CVAL.R              /* PIT RTI Current Timer Value Register */
#define PIT_1_RTI_TCTRL      PIT_1.RTI_TCTRL.R             /* PIT RTI Timer Control Register */
#define PIT_1_RTI_TFLG       PIT_1.RTI_TFLG.R              /* PIT RTI Timer Flag Register */
#define PIT_1_LDVAL0         PIT_1.TIMER[0].LDVAL.R        /* PIT Timer Load Value Register n */
#define PIT_1_CVAL0          PIT_1.TIMER[0].CVAL.R         /* PIT Current Timer Value Register n */
#define PIT_1_TCTRL0         PIT_1.TIMER[0].TCTRL.R        /* PIT Timer Control Register n */
#define PIT_1_TFLG0          PIT_1.TIMER[0].TFLG.R         /* PIT Timer Flag Register n */
#define PIT_1_LDVAL1         PIT_1.TIMER[1].LDVAL.R        /* PIT Timer Load Value Register n */
#define PIT_1_CVAL1          PIT_1.TIMER[1].CVAL.R         /* PIT Current Timer Value Register n */
#define PIT_1_TCTRL1         PIT_1.TIMER[1].TCTRL.R        /* PIT Timer Control Register n */
#define PIT_1_TFLG1          PIT_1.TIMER[1].TFLG.R         /* PIT Timer Flag Register n */
#define PIT_1_LDVAL2         PIT_1.TIMER[2].LDVAL.R        /* PIT Timer Load Value Register n */
#define PIT_1_CVAL2          PIT_1.TIMER[2].CVAL.R         /* PIT Current Timer Value Register n */
#define PIT_1_TCTRL2         PIT_1.TIMER[2].TCTRL.R        /* PIT Timer Control Register n */
#define PIT_1_TFLG2          PIT_1.TIMER[2].TFLG.R         /* PIT Timer Flag Register n */
#define PIT_1_LDVAL3         PIT_1.TIMER[3].LDVAL.R        /* PIT Timer Load Value Register n */
#define PIT_1_CVAL3          PIT_1.TIMER[3].CVAL.R         /* PIT Current Timer Value Register n */
#define PIT_1_TCTRL3         PIT_1.TIMER[3].TCTRL.R        /* PIT Timer Control Register n */
#define PIT_1_TFLG3          PIT_1.TIMER[3].TFLG.R         /* PIT Timer Flag Register n */
#define PIT_1_LDVAL4         PIT_1.TIMER[4].LDVAL.R        /* PIT Timer Load Value Register n */
#define PIT_1_CVAL4          PIT_1.TIMER[4].CVAL.R         /* PIT Current Timer Value Register n */
#define PIT_1_TCTRL4         PIT_1.TIMER[4].TCTRL.R        /* PIT Timer Control Register n */
#define PIT_1_TFLG4          PIT_1.TIMER[4].TFLG.R         /* PIT Timer Flag Register n */
#define PIT_1_LDVAL5         PIT_1.TIMER[5].LDVAL.R        /* PIT Timer Load Value Register n */
#define PIT_1_CVAL5          PIT_1.TIMER[5].CVAL.R         /* PIT Current Timer Value Register n */
#define PIT_1_TCTRL5         PIT_1.TIMER[5].TCTRL.R        /* PIT Timer Control Register n */
#define PIT_1_TFLG5          PIT_1.TIMER[5].TFLG.R         /* PIT Timer Flag Register n */
#define PIT_1_LDVAL6         PIT_1.TIMER[6].LDVAL.R        /* PIT Timer Load Value Register n */
#define PIT_1_CVAL6          PIT_1.TIMER[6].CVAL.R         /* PIT Current Timer Value Register n */
#define PIT_1_TCTRL6         PIT_1.TIMER[6].TCTRL.R        /* PIT Timer Control Register n */
#define PIT_1_TFLG6          PIT_1.TIMER[6].TFLG.R         /* PIT Timer Flag Register n */
#define PIT_1_LDVAL7         PIT_1.TIMER[7].LDVAL.R        /* PIT Timer Load Value Register n */
#define PIT_1_CVAL7          PIT_1.TIMER[7].CVAL.R         /* PIT Current Timer Value Register n */
#define PIT_1_TCTRL7         PIT_1.TIMER[7].TCTRL.R        /* PIT Timer Control Register n */
#define PIT_1_TFLG7          PIT_1.TIMER[7].TFLG.R         /* PIT Timer Flag Register n */

/* PLLDIG */
#define PLLDIG_PLL0CR        PLLDIG.PLL0CR.R               /* PLLDIG PLL0 Control Register */
#define PLLDIG_PLL0SR        PLLDIG.PLL0SR.R               /* PLLDIG PLL0 Status Register */
#define PLLDIG_PLL0DV        PLLDIG.PLL0DV.R               /* PLLDIG PLL0 Divider Register */
#define PLLDIG_PLL1CR        PLLDIG.PLL1CR.R               /* PLLDIG PLL1 Control Register */
#define PLLDIG_PLL1SR        PLLDIG.PLL1SR.R               /* PLLDIG PLL1 Status Register */
#define PLLDIG_PLL1DV        PLLDIG.PLL1DV.R               /* PLLDIG PLL1 Divider Register */
#define PLLDIG_PLL1FM        PLLDIG.PLL1FM.R               /* PLLDIG PLL1 Frequency Modulation Register */
#define PLLDIG_PLL1FD        PLLDIG.PLL1FD.R               /* PLLDIG PLL1 Fractional Divide Register */

/* PMCDIG */
#define PMCDIG_GR_S          PMCDIG.GR_S.R                 /* Supply Gauge Status Register */
#define PMCDIG_GR_P          PMCDIG.GR_P.R                 /* Pending Gauge Status Register */
#define PMCDIG_IE_P          PMCDIG.IE_P.R                 /* Interrupt Enable Pending Register */
#define PMCDIG_EPR_VD3       PMCDIG.EPR_VD3.R              /* Event Pending Register */
#define PMCDIG_REE_VD3       PMCDIG.REE_VD3.R              /* Reset Event Enable Register */
#define PMCDIG_RES_VD3       PMCDIG.RES_VD3.R              /* Reset Event Select Register */
#define PMCDIG_FEE_VD3       PMCDIG.FEE_VD3.R              /* FCCU Event Enable Register */
#define PMCDIG_EPR_VD4       PMCDIG.EPR_VD4.R              /* LVD108 Event Pending Register */
#define PMCDIG_REE_VD4       PMCDIG.REE_VD4.R              /* Reset Event Select Register */
#define PMCDIG_RES_VD4       PMCDIG.RES_VD4.R              /* Reset Event Select Register */
#define PMCDIG_FEE_VD4       PMCDIG.FEE_VD4.R              /* FCCU Event Enable Register */
#define PMCDIG_EPR_VD7       PMCDIG.EPR_VD7.R              /* Event Pending Register */
#define PMCDIG_REE_VD7       PMCDIG.REE_VD7.R              /* Reset Event Enable VD7 Register */
#define PMCDIG_RES_VD7       PMCDIG.RES_VD7.R              /* Reset Event Select Register */
#define PMCDIG_FEE_VD7       PMCDIG.FEE_VD7.R              /* FCCU Event Enable Register */
#define PMCDIG_EPR_VD8       PMCDIG.EPR_VD8.R              /* Event Pending Register */
#define PMCDIG_REE_VD8       PMCDIG.REE_VD8.R              /* Reset Event Enable Register */
#define PMCDIG_RES_VD8       PMCDIG.RES_VD8.R              /* Reset Event Select Registerr */
#define PMCDIG_FEE_VD8       PMCDIG.FEE_VD8.R              /* FCCU Event Enable Register */
#define PMCDIG_EPR_VD9       PMCDIG.EPR_VD9.R              /* LVD270 Event Pending Register */
#define PMCDIG_REE_VD9       PMCDIG.REE_VD9.R              /* Reset Event Enable Register */
#define PMCDIG_RES_VD9       PMCDIG.RES_VD9.R              /* Reset Event Select Register */
#define PMCDIG_FEE_VD9       PMCDIG.FEE_VD9.R              /* FCCU Event Enable VD9 */
#define PMCDIG_EPR_VD10      PMCDIG.EPR_VD10.R             /* LVD295 Event Pending Register */
#define PMCDIG_REE_VD10      PMCDIG.REE_VD10.R             /* Reset Event Enable Register */
#define PMCDIG_FEE_VD10      PMCDIG.FEE_VD10.R             /* FCCU Event Enable Register */
#define PMCDIG_EPR_VD12      PMCDIG.EPR_VD12.R             /* HVD360 Event Pending Register */
#define PMCDIG_REE_VD12      PMCDIG.REE_VD12.R             /* Reset Event Enable Register */
#define PMCDIG_RES_VD12      PMCDIG.RES_VD12.R             /* Reset Event Select Register */
#define PMCDIG_FEE_VD12      PMCDIG.FEE_VD12.R             /* FCCU Event Enable Register */
#define PMCDIG_EPR_VD13      PMCDIG.EPR_VD13.R             /* Event Pending Register */
#define PMCDIG_REE_VD13      PMCDIG.REE_VD13.R             /* Reset Event Enable Register */
#define PMCDIG_RES_VD13      PMCDIG.RES_VD13.R             /* Reset Event Select Register */
#define PMCDIG_FEE_VD13      PMCDIG.FEE_VD13.R             /* FCCU Event Enable Register */
#define PMCDIG_EPR_VD14      PMCDIG.EPR_VD14.R             /* Event Pending Register */
#define PMCDIG_REE_VD14      PMCDIG.REE_VD14.R             /* Reset Event Enable Register */
#define PMCDIG_RES_VD14      PMCDIG.RES_VD14.R             /* Reset Event Select Register */
#define PMCDIG_FEE_VD14      PMCDIG.FEE_VD14.R             /* FCCU Event Enable Register */
#define PMCDIG_EPR_VD15      PMCDIG.EPR_VD15.R             /* Event Pending Register */
#define PMCDIG_REE_VD15      PMCDIG.REE_VD15.R             /* Reset Event Enable Register */
#define PMCDIG_RES_VD15      PMCDIG.RES_VD15.R             /* Reset Event Select Register */
#define PMCDIG_FEE_VD15      PMCDIG.FEE_VD15.R             /* FCCU Event Enable Register */
#define PMCDIG_VSIO          PMCDIG.VSIO.R                 /* Voltage Supply for I/O Segment Register */
#define PMCDIG_EPR_TD        PMCDIG.EPR_TD.R               /* Event Pending Register */
#define PMCDIG_REE_TD        PMCDIG.REE_TD.R               /* Reset Event Enable Register */
#define PMCDIG_RES_TD        PMCDIG.RES_TD.R               /* Reset Event Select Register */
#define PMCDIG_CTL_TD        PMCDIG.CTL_TD.R               /* Temperature Sensor Configuration Register */
#define PMCDIG_FEE_TD        PMCDIG.FEE_TD.R               /* Temp Sensor FCCU Event Enable Register */
#define PMCDIG_VD_UTST       PMCDIG.VD_UTST.R              /* Voltage Detect User Mode Test Register */
#define PMCDIG_ADC_CH        PMCDIG.ADC_CH.R               /* ADC Channel Select Register */
#define PMCDIG_VREG1P2_CTRL  PMCDIG.VREG1P2_CTRL.R         /* Voltage Regulator 1.2V Control Register */
#define PMCDIG_MCR           PMCDIG.MCR.R                  /* Module Control Register */

/* PRAMC */
#define PRAMC_PRCR1          PRAMC.PRCR1.R                 /* Platform RAM Configuration Register 1 */

/* PSI5 */
#define PSI5_0_GCR           PSI5_0.GCR.R                  /* Global Control Register */
#define PSI5_0_CH0_PCCR      PSI5_0.CH0_PCCR.R             /* PSI5 Channel Control Register */
#define PSI5_0_CH0_DCR       PSI5_0.CH0_DCR.R              /* DMA Control Register */
#define PSI5_0_CH0_DSR       PSI5_0.CH0_DSR.R              /* DMA Status Register */
#define PSI5_0_CH0_GICR      PSI5_0.CH0_GICR.R             /* General Interrupt Control Register */
#define PSI5_0_CH0_NDICR     PSI5_0.CH0_NDICR.R            /* New Data Interrupt Control Register */
#define PSI5_0_CH0_OWICR     PSI5_0.CH0_OWICR.R            /* Overwrite Interrupt Control Register */
#define PSI5_0_CH0_EICR      PSI5_0.CH0_EICR.R             /* Error Interrupt Control Register */
#define PSI5_0_CH0_GISR      PSI5_0.CH0_GISR.R             /* General Interrupt Status Register */
#define PSI5_0_CH0_DPMR      PSI5_0.CH0_DPMR.R             /* DMA PSI5 Message Register */
#define PSI5_0_CH0_DSFR      PSI5_0.CH0_DSFR.R             /* DMA SMC Frame Register */
#define PSI5_0_CH0_DDSR      PSI5_0.CH0_DDSR.R             /* DMA Diagnostic Status Register */
#define PSI5_0_CH0_PMRRL     PSI5_0.CH0_PMRRL.R            /* PSI5 Message Receive Register Low */
#define PSI5_0_CH0_PMRRH     PSI5_0.CH0_PMRRH.R            /* PSI5 Message Receive Register High */
#define PSI5_0_CH0_PMRL0     PSI5_0.CH0[0].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH0     PSI5_0.CH0[0].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL1     PSI5_0.CH0[1].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH1     PSI5_0.CH0[1].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL2     PSI5_0.CH0[2].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH2     PSI5_0.CH0[2].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL3     PSI5_0.CH0[3].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH3     PSI5_0.CH0[3].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL4     PSI5_0.CH0[4].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH4     PSI5_0.CH0[4].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL5     PSI5_0.CH0[5].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH5     PSI5_0.CH0[5].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL6     PSI5_0.CH0[6].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH6     PSI5_0.CH0[6].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL7     PSI5_0.CH0[7].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH7     PSI5_0.CH0[7].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL8     PSI5_0.CH0[8].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH8     PSI5_0.CH0[8].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL9     PSI5_0.CH0[9].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH9     PSI5_0.CH0[9].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL10    PSI5_0.CH0[10].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH10    PSI5_0.CH0[10].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL11    PSI5_0.CH0[11].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH11    PSI5_0.CH0[11].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL12    PSI5_0.CH0[12].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH12    PSI5_0.CH0[12].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL13    PSI5_0.CH0[13].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH13    PSI5_0.CH0[13].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL14    PSI5_0.CH0[14].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH14    PSI5_0.CH0[14].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL15    PSI5_0.CH0[15].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH15    PSI5_0.CH0[15].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL16    PSI5_0.CH0[16].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH16    PSI5_0.CH0[16].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL17    PSI5_0.CH0[17].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH17    PSI5_0.CH0[17].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL18    PSI5_0.CH0[18].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH18    PSI5_0.CH0[18].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL19    PSI5_0.CH0[19].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH19    PSI5_0.CH0[19].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL20    PSI5_0.CH0[20].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH20    PSI5_0.CH0[20].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL21    PSI5_0.CH0[21].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH21    PSI5_0.CH0[21].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL22    PSI5_0.CH0[22].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH22    PSI5_0.CH0[22].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL23    PSI5_0.CH0[23].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH23    PSI5_0.CH0[23].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL24    PSI5_0.CH0[24].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH24    PSI5_0.CH0[24].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL25    PSI5_0.CH0[25].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH25    PSI5_0.CH0[25].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL26    PSI5_0.CH0[26].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH26    PSI5_0.CH0[26].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL27    PSI5_0.CH0[27].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH27    PSI5_0.CH0[27].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL28    PSI5_0.CH0[28].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH28    PSI5_0.CH0[28].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL29    PSI5_0.CH0[29].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH29    PSI5_0.CH0[29].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL30    PSI5_0.CH0[30].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH30    PSI5_0.CH0[30].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_PMRL31    PSI5_0.CH0[31].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH0_PMRH31    PSI5_0.CH0[31].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH0_SFR1      PSI5_0.CH0_SFR[0].R           /* SMC Frame Register n */
#define PSI5_0_CH0_SFR2      PSI5_0.CH0_SFR[1].R           /* SMC Frame Register n */
#define PSI5_0_CH0_SFR3      PSI5_0.CH0_SFR[2].R           /* SMC Frame Register n */
#define PSI5_0_CH0_SFR4      PSI5_0.CH0_SFR[3].R           /* SMC Frame Register n */
#define PSI5_0_CH0_SFR5      PSI5_0.CH0_SFR[4].R           /* SMC Frame Register n */
#define PSI5_0_CH0_SFR6      PSI5_0.CH0_SFR[5].R           /* SMC Frame Register n */
#define PSI5_0_CH0_NDSR      PSI5_0.CH0_NDSR.R             /* New Data Status Register */
#define PSI5_0_CH0_OWSR      PSI5_0.CH0_OWSR.R             /* Overwrite Status Register */
#define PSI5_0_CH0_EISR      PSI5_0.CH0_EISR.R             /* Error Indication Status Register */
#define PSI5_0_CH0_SNDSR     PSI5_0.CH0_SNDSR.R            /* Set New Data Status Register */
#define PSI5_0_CH0_SOWSR     PSI5_0.CH0_SOWSR.R            /* Set Overwrite Status Register */
#define PSI5_0_CH0_SEISR     PSI5_0.CH0_SEISR.R            /* Set Error Status Register */
#define PSI5_0_CH0_SSESR     PSI5_0.CH0_SSESR.R            /* Set SMC Error Status Register */
#define PSI5_0_CH0_STSRR     PSI5_0.CH0_STSRR.R            /* Sync Time Stamp Read Register */
#define PSI5_0_CH0_DTSRR     PSI5_0.CH0_DTSRR.R            /* Data Time Stamp Read Register */
#define PSI5_0_CH0_S1FCR     PSI5_0.CH0_SFCR[0].R          /* Slot n Frame Configuration Register */
#define PSI5_0_CH0_S2FCR     PSI5_0.CH0_SFCR[1].R          /* Slot n Frame Configuration Register */
#define PSI5_0_CH0_S3FCR     PSI5_0.CH0_SFCR[2].R          /* Slot n Frame Configuration Register */
#define PSI5_0_CH0_S4FCR     PSI5_0.CH0_SFCR[3].R          /* Slot n Frame Configuration Register */
#define PSI5_0_CH0_S5FCR     PSI5_0.CH0_SFCR[4].R          /* Slot n Frame Configuration Register */
#define PSI5_0_CH0_S6FCR     PSI5_0.CH0_SFCR[5].R          /* Slot n Frame Configuration Register */
#define PSI5_0_CH0_S1SBR     PSI5_0.CH0_S1SBR.R            /* Slot 1 Start Boundary Register */
#define PSI5_0_CH0_S2SBR     PSI5_0.CH0_S2SBR.R            /* Slot 2 Start Boundary Register */
#define PSI5_0_CH0_S3SBR     PSI5_0.CH0_S3SBR.R            /* Slot 3 Start Boundary Register */
#define PSI5_0_CH0_S4SBR     PSI5_0.CH0_S4SBR.R            /* Slot 4 Start Boundary Register */
#define PSI5_0_CH0_S5SBR     PSI5_0.CH0_S5SBR.R            /* Slot 5 Start Boundary Register */
#define PSI5_0_CH0_S6SBR     PSI5_0.CH0_S6SBR.R            /* Slot 6 Start Boundary Register */
#define PSI5_0_CH0_SnEBR     PSI5_0.CH0_SnEBR.R            /* Slot n End Boundary Register */
#define PSI5_0_CH0_DOBCR     PSI5_0.CH0_DOBCR.R            /* Data Output Block Configuration Register */
#define PSI5_0_CH0_MDDIS_OFF PSI5_0.CH0_MDDIS_OFF.R        /* Manchestor Decoder Disable Offset */
#define PSI5_0_CH0_PW0D      PSI5_0.CH0_PW0D.R             /* Pulse Width for Data Bit Value 0 */
#define PSI5_0_CH0_PW1D      PSI5_0.CH0_PW1D.R             /* Pulse Width for Data Bit Value 1 */
#define PSI5_0_CH0_CTPR      PSI5_0.CH0_CTPR.R             /* Counter Target Pulse Register */
#define PSI5_0_CH0_CIPR      PSI5_0.CH0_CIPR.R             /* Counter Initialize Pulse Register */
#define PSI5_0_CH0_DPRL      PSI5_0.CH0_DPRL.R             /* Data Preparation Register Low */
#define PSI5_0_CH0_DPRH      PSI5_0.CH0_DPRH.R             /* Data Preparation Register High */
#define PSI5_0_CH0_DBRL      PSI5_0.CH0_DBRL.R             /* Data Buffer Register Low */
#define PSI5_0_CH0_DBRH      PSI5_0.CH0_DBRH.R             /* Data Buffer Register High */
#define PSI5_0_CH0_DSRL      PSI5_0.CH0_DSRL.R             /* Data Shift Register Low */
#define PSI5_0_CH0_DSRH      PSI5_0.CH0_DSRH.R             /* Data Shift Register High */
#define PSI5_0_CH1_PCCR      PSI5_0.CH1_PCCR.R             /* PSI5 Channel Control Register */
#define PSI5_0_CH1_DCR       PSI5_0.CH1_DCR.R              /* DMA Control Register */
#define PSI5_0_CH1_DSR       PSI5_0.CH1_DSR.R              /* DMA Status Register */
#define PSI5_0_CH1_GICR      PSI5_0.CH1_GICR.R             /* General Interrupt Control Register */
#define PSI5_0_CH1_NDICR     PSI5_0.CH1_NDICR.R            /* New Data Interrupt Control Register */
#define PSI5_0_CH1_OWICR     PSI5_0.CH1_OWICR.R            /* Overwrite Interrupt Control Register */
#define PSI5_0_CH1_EICR      PSI5_0.CH1_EICR.R             /* Error Interrupt Control Register */
#define PSI5_0_CH1_GISR      PSI5_0.CH1_GISR.R             /* General Interrupt Status Register */
#define PSI5_0_CH1_DPMR      PSI5_0.CH1_DPMR.R             /* DMA PSI5 Message Register */
#define PSI5_0_CH1_DSFR      PSI5_0.CH1_DSFR.R             /* DMA SMC Frame Register */
#define PSI5_0_CH1_DDSR      PSI5_0.CH1_DDSR.R             /* DMA Diagnostic Status Register */
#define PSI5_0_CH1_PMRRL     PSI5_0.CH1_PMRRL.R            /* PSI5 Message Receive Register Low */
#define PSI5_0_CH1_PMRRH     PSI5_0.CH1_PMRRH.R            /* PSI5 Message Receive Register High */
#define PSI5_0_CH1_PMRL0     PSI5_0.CH1[0].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH0     PSI5_0.CH1[0].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL1     PSI5_0.CH1[1].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH1     PSI5_0.CH1[1].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL2     PSI5_0.CH1[2].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH2     PSI5_0.CH1[2].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL3     PSI5_0.CH1[3].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH3     PSI5_0.CH1[3].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL4     PSI5_0.CH1[4].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH4     PSI5_0.CH1[4].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL5     PSI5_0.CH1[5].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH5     PSI5_0.CH1[5].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL6     PSI5_0.CH1[6].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH6     PSI5_0.CH1[6].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL7     PSI5_0.CH1[7].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH7     PSI5_0.CH1[7].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL8     PSI5_0.CH1[8].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH8     PSI5_0.CH1[8].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL9     PSI5_0.CH1[9].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH9     PSI5_0.CH1[9].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL10    PSI5_0.CH1[10].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH10    PSI5_0.CH1[10].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL11    PSI5_0.CH1[11].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH11    PSI5_0.CH1[11].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL12    PSI5_0.CH1[12].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH12    PSI5_0.CH1[12].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL13    PSI5_0.CH1[13].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH13    PSI5_0.CH1[13].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL14    PSI5_0.CH1[14].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH14    PSI5_0.CH1[14].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL15    PSI5_0.CH1[15].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH15    PSI5_0.CH1[15].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL16    PSI5_0.CH1[16].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH16    PSI5_0.CH1[16].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL17    PSI5_0.CH1[17].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH17    PSI5_0.CH1[17].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL18    PSI5_0.CH1[18].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH18    PSI5_0.CH1[18].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL19    PSI5_0.CH1[19].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH19    PSI5_0.CH1[19].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL20    PSI5_0.CH1[20].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH20    PSI5_0.CH1[20].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL21    PSI5_0.CH1[21].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH21    PSI5_0.CH1[21].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL22    PSI5_0.CH1[22].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH22    PSI5_0.CH1[22].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL23    PSI5_0.CH1[23].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH23    PSI5_0.CH1[23].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL24    PSI5_0.CH1[24].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH24    PSI5_0.CH1[24].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL25    PSI5_0.CH1[25].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH25    PSI5_0.CH1[25].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL26    PSI5_0.CH1[26].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH26    PSI5_0.CH1[26].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL27    PSI5_0.CH1[27].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH27    PSI5_0.CH1[27].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL28    PSI5_0.CH1[28].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH28    PSI5_0.CH1[28].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL29    PSI5_0.CH1[29].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH29    PSI5_0.CH1[29].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL30    PSI5_0.CH1[30].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH30    PSI5_0.CH1[30].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_PMRL31    PSI5_0.CH1[31].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH1_PMRH31    PSI5_0.CH1[31].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH1_SFR1      PSI5_0.CH1_SFR[0].R           /* SMC Frame Register n */
#define PSI5_0_CH1_SFR2      PSI5_0.CH1_SFR[1].R           /* SMC Frame Register n */
#define PSI5_0_CH1_SFR3      PSI5_0.CH1_SFR[2].R           /* SMC Frame Register n */
#define PSI5_0_CH1_SFR4      PSI5_0.CH1_SFR[3].R           /* SMC Frame Register n */
#define PSI5_0_CH1_SFR5      PSI5_0.CH1_SFR[4].R           /* SMC Frame Register n */
#define PSI5_0_CH1_SFR6      PSI5_0.CH1_SFR[5].R           /* SMC Frame Register n */
#define PSI5_0_CH1_NDSR      PSI5_0.CH1_NDSR.R             /* New Data Status Register */
#define PSI5_0_CH1_OWSR      PSI5_0.CH1_OWSR.R             /* Overwrite Status Register */
#define PSI5_0_CH1_EISR      PSI5_0.CH1_EISR.R             /* Error Indication Status Register */
#define PSI5_0_CH1_SNDSR     PSI5_0.CH1_SNDSR.R            /* Set New Data Status Register */
#define PSI5_0_CH1_SOWSR     PSI5_0.CH1_SOWSR.R            /* Set Overwrite Status Register */
#define PSI5_0_CH1_SEISR     PSI5_0.CH1_SEISR.R            /* Set Error Status Register */
#define PSI5_0_CH1_SSESR     PSI5_0.CH1_SSESR.R            /* Set SMC Error Status Register */
#define PSI5_0_CH1_STSRR     PSI5_0.CH1_STSRR.R            /* Sync Time Stamp Read Register */
#define PSI5_0_CH1_DTSRR     PSI5_0.CH1_DTSRR.R            /* Data Time Stamp Read Register */
#define PSI5_0_CH1_S1FCR     PSI5_0.CH1_SFCR[0].R          /* Slot n Frame Configuration Register */
#define PSI5_0_CH1_S2FCR     PSI5_0.CH1_SFCR[1].R          /* Slot n Frame Configuration Register */
#define PSI5_0_CH1_S3FCR     PSI5_0.CH1_SFCR[2].R          /* Slot n Frame Configuration Register */
#define PSI5_0_CH1_S4FCR     PSI5_0.CH1_SFCR[3].R          /* Slot n Frame Configuration Register */
#define PSI5_0_CH1_S5FCR     PSI5_0.CH1_SFCR[4].R          /* Slot n Frame Configuration Register */
#define PSI5_0_CH1_S6FCR     PSI5_0.CH1_SFCR[5].R          /* Slot n Frame Configuration Register */
#define PSI5_0_CH1_S1SBR     PSI5_0.CH1_S1SBR.R            /* Slot 1 Start Boundary Register */
#define PSI5_0_CH1_S2SBR     PSI5_0.CH1_S2SBR.R            /* Slot 2 Start Boundary Register */
#define PSI5_0_CH1_S3SBR     PSI5_0.CH1_S3SBR.R            /* Slot 3 Start Boundary Register */
#define PSI5_0_CH1_S4SBR     PSI5_0.CH1_S4SBR.R            /* Slot 4 Start Boundary Register */
#define PSI5_0_CH1_S5SBR     PSI5_0.CH1_S5SBR.R            /* Slot 5 Start Boundary Register */
#define PSI5_0_CH1_S6SBR     PSI5_0.CH1_S6SBR.R            /* Slot 6 Start Boundary Register */
#define PSI5_0_CH1_SnEBR     PSI5_0.CH1_SnEBR.R            /* Slot n End Boundary Register */
#define PSI5_0_CH1_DOBCR     PSI5_0.CH1_DOBCR.R            /* Data Output Block Configuration Register */
#define PSI5_0_CH1_MDDIS_OFF PSI5_0.CH1_MDDIS_OFF.R        /* Manchestor Decoder Disable Offset */
#define PSI5_0_CH1_PW0D      PSI5_0.CH1_PW0D.R             /* Pulse Width for Data Bit Value 0 */
#define PSI5_0_CH1_PW1D      PSI5_0.CH1_PW1D.R             /* Pulse Width for Data Bit Value 1 */
#define PSI5_0_CH1_CTPR      PSI5_0.CH1_CTPR.R             /* Counter Target Pulse Register */
#define PSI5_0_CH1_CIPR      PSI5_0.CH1_CIPR.R             /* Counter Initialize Pulse Register */
#define PSI5_0_CH1_DPRL      PSI5_0.CH1_DPRL.R             /* Data Preparation Register Low */
#define PSI5_0_CH1_DPRH      PSI5_0.CH1_DPRH.R             /* Data Preparation Register High */
#define PSI5_0_CH1_DBRL      PSI5_0.CH1_DBRL.R             /* Data Buffer Register Low */
#define PSI5_0_CH1_DBRH      PSI5_0.CH1_DBRH.R             /* Data Buffer Register High */
#define PSI5_0_CH1_DSRL      PSI5_0.CH1_DSRL.R             /* Data Shift Register Low */
#define PSI5_0_CH1_DSRH      PSI5_0.CH1_DSRH.R             /* Data Shift Register High */
#define PSI5_0_CH2_PCCR      PSI5_0.CH2_PCCR.R             /* PSI5 Channel Control Register */
#define PSI5_0_CH2_DCR       PSI5_0.CH2_DCR.R              /* DMA Control Register */
#define PSI5_0_CH2_DSR       PSI5_0.CH2_DSR.R              /* DMA Status Register */
#define PSI5_0_CH2_GICR      PSI5_0.CH2_GICR.R             /* General Interrupt Control Register */
#define PSI5_0_CH2_NDICR     PSI5_0.CH2_NDICR.R            /* New Data Interrupt Control Register */
#define PSI5_0_CH2_OWICR     PSI5_0.CH2_OWICR.R            /* Overwrite Interrupt Control Register */
#define PSI5_0_CH2_EICR      PSI5_0.CH2_EICR.R             /* Error Interrupt Control Register */
#define PSI5_0_CH2_GISR      PSI5_0.CH2_GISR.R             /* General Interrupt Status Register */
#define PSI5_0_CH2_DPMR      PSI5_0.CH2_DPMR.R             /* DMA PSI5 Message Register */
#define PSI5_0_CH2_DSFR      PSI5_0.CH2_DSFR.R             /* DMA SMC Frame Register */
#define PSI5_0_CH2_DDSR      PSI5_0.CH2_DDSR.R             /* DMA Diagnostic Status Register */
#define PSI5_0_CH2_PMRRL     PSI5_0.CH2_PMRRL.R            /* PSI5 Message Receive Register Low */
#define PSI5_0_CH2_PMRRH     PSI5_0.CH2_PMRRH.R            /* PSI5 Message Receive Register High */
#define PSI5_0_CH2_PMRL0     PSI5_0.CH2[0].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH0     PSI5_0.CH2[0].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL1     PSI5_0.CH2[1].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH1     PSI5_0.CH2[1].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL2     PSI5_0.CH2[2].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH2     PSI5_0.CH2[2].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL3     PSI5_0.CH2[3].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH3     PSI5_0.CH2[3].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL4     PSI5_0.CH2[4].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH4     PSI5_0.CH2[4].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL5     PSI5_0.CH2[5].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH5     PSI5_0.CH2[5].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL6     PSI5_0.CH2[6].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH6     PSI5_0.CH2[6].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL7     PSI5_0.CH2[7].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH7     PSI5_0.CH2[7].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL8     PSI5_0.CH2[8].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH8     PSI5_0.CH2[8].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL9     PSI5_0.CH2[9].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH9     PSI5_0.CH2[9].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL10    PSI5_0.CH2[10].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH10    PSI5_0.CH2[10].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL11    PSI5_0.CH2[11].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH11    PSI5_0.CH2[11].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL12    PSI5_0.CH2[12].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH12    PSI5_0.CH2[12].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL13    PSI5_0.CH2[13].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH13    PSI5_0.CH2[13].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL14    PSI5_0.CH2[14].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH14    PSI5_0.CH2[14].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL15    PSI5_0.CH2[15].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH15    PSI5_0.CH2[15].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL16    PSI5_0.CH2[16].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH16    PSI5_0.CH2[16].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL17    PSI5_0.CH2[17].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH17    PSI5_0.CH2[17].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL18    PSI5_0.CH2[18].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH18    PSI5_0.CH2[18].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL19    PSI5_0.CH2[19].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH19    PSI5_0.CH2[19].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL20    PSI5_0.CH2[20].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH20    PSI5_0.CH2[20].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL21    PSI5_0.CH2[21].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH21    PSI5_0.CH2[21].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL22    PSI5_0.CH2[22].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH22    PSI5_0.CH2[22].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL23    PSI5_0.CH2[23].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH23    PSI5_0.CH2[23].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL24    PSI5_0.CH2[24].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH24    PSI5_0.CH2[24].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL25    PSI5_0.CH2[25].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH25    PSI5_0.CH2[25].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL26    PSI5_0.CH2[26].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH26    PSI5_0.CH2[26].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL27    PSI5_0.CH2[27].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH27    PSI5_0.CH2[27].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL28    PSI5_0.CH2[28].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH28    PSI5_0.CH2[28].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL29    PSI5_0.CH2[29].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH29    PSI5_0.CH2[29].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL30    PSI5_0.CH2[30].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH30    PSI5_0.CH2[30].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_PMRL31    PSI5_0.CH2[31].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_0_CH2_PMRH31    PSI5_0.CH2[31].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_0_CH2_SFR1      PSI5_0.CH2_SFR[0].R           /* SMC Frame Register n */
#define PSI5_0_CH2_SFR2      PSI5_0.CH2_SFR[1].R           /* SMC Frame Register n */
#define PSI5_0_CH2_SFR3      PSI5_0.CH2_SFR[2].R           /* SMC Frame Register n */
#define PSI5_0_CH2_SFR4      PSI5_0.CH2_SFR[3].R           /* SMC Frame Register n */
#define PSI5_0_CH2_SFR5      PSI5_0.CH2_SFR[4].R           /* SMC Frame Register n */
#define PSI5_0_CH2_SFR6      PSI5_0.CH2_SFR[5].R           /* SMC Frame Register n */
#define PSI5_0_CH2_NDSR      PSI5_0.CH2_NDSR.R             /* New Data Status Register */
#define PSI5_0_CH2_OWSR      PSI5_0.CH2_OWSR.R             /* Overwrite Status Register */
#define PSI5_0_CH2_EISR      PSI5_0.CH2_EISR.R             /* Error Indication Status Register */
#define PSI5_0_CH2_SNDSR     PSI5_0.CH2_SNDSR.R            /* Set New Data Status Register */
#define PSI5_0_CH2_SOWSR     PSI5_0.CH2_SOWSR.R            /* Set Overwrite Status Register */
#define PSI5_0_CH2_SEISR     PSI5_0.CH2_SEISR.R            /* Set Error Status Register */
#define PSI5_0_CH2_SSESR     PSI5_0.CH2_SSESR.R            /* Set SMC Error Status Register */
#define PSI5_0_CH2_STSRR     PSI5_0.CH2_STSRR.R            /* Sync Time Stamp Read Register */
#define PSI5_0_CH2_DTSRR     PSI5_0.CH2_DTSRR.R            /* Data Time Stamp Read Register */
#define PSI5_0_CH2_S1FCR     PSI5_0.CH2_SFCR[0].R          /* Slot n Frame Configuration Register */
#define PSI5_0_CH2_S2FCR     PSI5_0.CH2_SFCR[1].R          /* Slot n Frame Configuration Register */
#define PSI5_0_CH2_S3FCR     PSI5_0.CH2_SFCR[2].R          /* Slot n Frame Configuration Register */
#define PSI5_0_CH2_S4FCR     PSI5_0.CH2_SFCR[3].R          /* Slot n Frame Configuration Register */
#define PSI5_0_CH2_S5FCR     PSI5_0.CH2_SFCR[4].R          /* Slot n Frame Configuration Register */
#define PSI5_0_CH2_S6FCR     PSI5_0.CH2_SFCR[5].R          /* Slot n Frame Configuration Register */
#define PSI5_0_CH2_S1SBR     PSI5_0.CH2_S1SBR.R            /* Slot 1 Start Boundary Register */
#define PSI5_0_CH2_S2SBR     PSI5_0.CH2_S2SBR.R            /* Slot 2 Start Boundary Register */
#define PSI5_0_CH2_S3SBR     PSI5_0.CH2_S3SBR.R            /* Slot 3 Start Boundary Register */
#define PSI5_0_CH2_S4SBR     PSI5_0.CH2_S4SBR.R            /* Slot 4 Start Boundary Register */
#define PSI5_0_CH2_S5SBR     PSI5_0.CH2_S5SBR.R            /* Slot 5 Start Boundary Register */
#define PSI5_0_CH2_S6SBR     PSI5_0.CH2_S6SBR.R            /* Slot 6 Start Boundary Register */
#define PSI5_0_CH2_SnEBR     PSI5_0.CH2_SnEBR.R            /* Slot n End Boundary Register */
#define PSI5_0_CH2_DOBCR     PSI5_0.CH2_DOBCR.R            /* Data Output Block Configuration Register */
#define PSI5_0_CH2_MDDIS_OFF PSI5_0.CH2_MDDIS_OFF.R        /* Manchestor Decoder Disable Offset */
#define PSI5_0_CH2_PW0D      PSI5_0.CH2_PW0D.R             /* Pulse Width for Data Bit Value 0 */
#define PSI5_0_CH2_PW1D      PSI5_0.CH2_PW1D.R             /* Pulse Width for Data Bit Value 1 */
#define PSI5_0_CH2_CTPR      PSI5_0.CH2_CTPR.R             /* Counter Target Pulse Register */
#define PSI5_0_CH2_CIPR      PSI5_0.CH2_CIPR.R             /* Counter Initialize Pulse Register */
#define PSI5_0_CH2_DPRL      PSI5_0.CH2_DPRL.R             /* Data Preparation Register Low */
#define PSI5_0_CH2_DPRH      PSI5_0.CH2_DPRH.R             /* Data Preparation Register High */
#define PSI5_0_CH2_DBRL      PSI5_0.CH2_DBRL.R             /* Data Buffer Register Low */
#define PSI5_0_CH2_DBRH      PSI5_0.CH2_DBRH.R             /* Data Buffer Register High */
#define PSI5_0_CH2_DSRL      PSI5_0.CH2_DSRL.R             /* Data Shift Register Low */
#define PSI5_0_CH2_DSRH      PSI5_0.CH2_DSRH.R             /* Data Shift Register High */

/* PSI5 */
#define PSI5_1_GCR           PSI5_1.GCR.R                  /* Global Control Register */
#define PSI5_1_CH0_PCCR      PSI5_1.CH0_PCCR.R             /* PSI5 Channel Control Register */
#define PSI5_1_CH0_DCR       PSI5_1.CH0_DCR.R              /* DMA Control Register */
#define PSI5_1_CH0_DSR       PSI5_1.CH0_DSR.R              /* DMA Status Register */
#define PSI5_1_CH0_GICR      PSI5_1.CH0_GICR.R             /* General Interrupt Control Register */
#define PSI5_1_CH0_NDICR     PSI5_1.CH0_NDICR.R            /* New Data Interrupt Control Register */
#define PSI5_1_CH0_OWICR     PSI5_1.CH0_OWICR.R            /* Overwrite Interrupt Control Register */
#define PSI5_1_CH0_EICR      PSI5_1.CH0_EICR.R             /* Error Interrupt Control Register */
#define PSI5_1_CH0_GISR      PSI5_1.CH0_GISR.R             /* General Interrupt Status Register */
#define PSI5_1_CH0_DPMR      PSI5_1.CH0_DPMR.R             /* DMA PSI5 Message Register */
#define PSI5_1_CH0_DSFR      PSI5_1.CH0_DSFR.R             /* DMA SMC Frame Register */
#define PSI5_1_CH0_DDSR      PSI5_1.CH0_DDSR.R             /* DMA Diagnostic Status Register */
#define PSI5_1_CH0_PMRRL     PSI5_1.CH0_PMRRL.R            /* PSI5 Message Receive Register Low */
#define PSI5_1_CH0_PMRRH     PSI5_1.CH0_PMRRH.R            /* PSI5 Message Receive Register High */
#define PSI5_1_CH0_PMRL0     PSI5_1.CH0[0].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH0     PSI5_1.CH0[0].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL1     PSI5_1.CH0[1].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH1     PSI5_1.CH0[1].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL2     PSI5_1.CH0[2].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH2     PSI5_1.CH0[2].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL3     PSI5_1.CH0[3].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH3     PSI5_1.CH0[3].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL4     PSI5_1.CH0[4].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH4     PSI5_1.CH0[4].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL5     PSI5_1.CH0[5].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH5     PSI5_1.CH0[5].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL6     PSI5_1.CH0[6].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH6     PSI5_1.CH0[6].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL7     PSI5_1.CH0[7].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH7     PSI5_1.CH0[7].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL8     PSI5_1.CH0[8].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH8     PSI5_1.CH0[8].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL9     PSI5_1.CH0[9].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH9     PSI5_1.CH0[9].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL10    PSI5_1.CH0[10].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH10    PSI5_1.CH0[10].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL11    PSI5_1.CH0[11].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH11    PSI5_1.CH0[11].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL12    PSI5_1.CH0[12].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH12    PSI5_1.CH0[12].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL13    PSI5_1.CH0[13].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH13    PSI5_1.CH0[13].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL14    PSI5_1.CH0[14].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH14    PSI5_1.CH0[14].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL15    PSI5_1.CH0[15].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH15    PSI5_1.CH0[15].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL16    PSI5_1.CH0[16].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH16    PSI5_1.CH0[16].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL17    PSI5_1.CH0[17].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH17    PSI5_1.CH0[17].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL18    PSI5_1.CH0[18].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH18    PSI5_1.CH0[18].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL19    PSI5_1.CH0[19].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH19    PSI5_1.CH0[19].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL20    PSI5_1.CH0[20].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH20    PSI5_1.CH0[20].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL21    PSI5_1.CH0[21].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH21    PSI5_1.CH0[21].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL22    PSI5_1.CH0[22].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH22    PSI5_1.CH0[22].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL23    PSI5_1.CH0[23].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH23    PSI5_1.CH0[23].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL24    PSI5_1.CH0[24].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH24    PSI5_1.CH0[24].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL25    PSI5_1.CH0[25].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH25    PSI5_1.CH0[25].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL26    PSI5_1.CH0[26].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH26    PSI5_1.CH0[26].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL27    PSI5_1.CH0[27].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH27    PSI5_1.CH0[27].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL28    PSI5_1.CH0[28].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH28    PSI5_1.CH0[28].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL29    PSI5_1.CH0[29].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH29    PSI5_1.CH0[29].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL30    PSI5_1.CH0[30].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH30    PSI5_1.CH0[30].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_PMRL31    PSI5_1.CH0[31].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH0_PMRH31    PSI5_1.CH0[31].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH0_SFR1      PSI5_1.CH0_SFR[0].R           /* SMC Frame Register n */
#define PSI5_1_CH0_SFR2      PSI5_1.CH0_SFR[1].R           /* SMC Frame Register n */
#define PSI5_1_CH0_SFR3      PSI5_1.CH0_SFR[2].R           /* SMC Frame Register n */
#define PSI5_1_CH0_SFR4      PSI5_1.CH0_SFR[3].R           /* SMC Frame Register n */
#define PSI5_1_CH0_SFR5      PSI5_1.CH0_SFR[4].R           /* SMC Frame Register n */
#define PSI5_1_CH0_SFR6      PSI5_1.CH0_SFR[5].R           /* SMC Frame Register n */
#define PSI5_1_CH0_NDSR      PSI5_1.CH0_NDSR.R             /* New Data Status Register */
#define PSI5_1_CH0_OWSR      PSI5_1.CH0_OWSR.R             /* Overwrite Status Register */
#define PSI5_1_CH0_EISR      PSI5_1.CH0_EISR.R             /* Error Indication Status Register */
#define PSI5_1_CH0_SNDSR     PSI5_1.CH0_SNDSR.R            /* Set New Data Status Register */
#define PSI5_1_CH0_SOWSR     PSI5_1.CH0_SOWSR.R            /* Set Overwrite Status Register */
#define PSI5_1_CH0_SEISR     PSI5_1.CH0_SEISR.R            /* Set Error Status Register */
#define PSI5_1_CH0_SSESR     PSI5_1.CH0_SSESR.R            /* Set SMC Error Status Register */
#define PSI5_1_CH0_STSRR     PSI5_1.CH0_STSRR.R            /* Sync Time Stamp Read Register */
#define PSI5_1_CH0_DTSRR     PSI5_1.CH0_DTSRR.R            /* Data Time Stamp Read Register */
#define PSI5_1_CH0_S1FCR     PSI5_1.CH0_SFCR[0].R          /* Slot n Frame Configuration Register */
#define PSI5_1_CH0_S2FCR     PSI5_1.CH0_SFCR[1].R          /* Slot n Frame Configuration Register */
#define PSI5_1_CH0_S3FCR     PSI5_1.CH0_SFCR[2].R          /* Slot n Frame Configuration Register */
#define PSI5_1_CH0_S4FCR     PSI5_1.CH0_SFCR[3].R          /* Slot n Frame Configuration Register */
#define PSI5_1_CH0_S5FCR     PSI5_1.CH0_SFCR[4].R          /* Slot n Frame Configuration Register */
#define PSI5_1_CH0_S6FCR     PSI5_1.CH0_SFCR[5].R          /* Slot n Frame Configuration Register */
#define PSI5_1_CH0_S1SBR     PSI5_1.CH0_S1SBR.R            /* Slot 1 Start Boundary Register */
#define PSI5_1_CH0_S2SBR     PSI5_1.CH0_S2SBR.R            /* Slot 2 Start Boundary Register */
#define PSI5_1_CH0_S3SBR     PSI5_1.CH0_S3SBR.R            /* Slot 3 Start Boundary Register */
#define PSI5_1_CH0_S4SBR     PSI5_1.CH0_S4SBR.R            /* Slot 4 Start Boundary Register */
#define PSI5_1_CH0_S5SBR     PSI5_1.CH0_S5SBR.R            /* Slot 5 Start Boundary Register */
#define PSI5_1_CH0_S6SBR     PSI5_1.CH0_S6SBR.R            /* Slot 6 Start Boundary Register */
#define PSI5_1_CH0_SnEBR     PSI5_1.CH0_SnEBR.R            /* Slot n End Boundary Register */
#define PSI5_1_CH0_DOBCR     PSI5_1.CH0_DOBCR.R            /* Data Output Block Configuration Register */
#define PSI5_1_CH0_MDDIS_OFF PSI5_1.CH0_MDDIS_OFF.R        /* Manchestor Decoder Disable Offset */
#define PSI5_1_CH0_PW0D      PSI5_1.CH0_PW0D.R             /* Pulse Width for Data Bit Value 0 */
#define PSI5_1_CH0_PW1D      PSI5_1.CH0_PW1D.R             /* Pulse Width for Data Bit Value 1 */
#define PSI5_1_CH0_CTPR      PSI5_1.CH0_CTPR.R             /* Counter Target Pulse Register */
#define PSI5_1_CH0_CIPR      PSI5_1.CH0_CIPR.R             /* Counter Initialize Pulse Register */
#define PSI5_1_CH0_DPRL      PSI5_1.CH0_DPRL.R             /* Data Preparation Register Low */
#define PSI5_1_CH0_DPRH      PSI5_1.CH0_DPRH.R             /* Data Preparation Register High */
#define PSI5_1_CH0_DBRL      PSI5_1.CH0_DBRL.R             /* Data Buffer Register Low */
#define PSI5_1_CH0_DBRH      PSI5_1.CH0_DBRH.R             /* Data Buffer Register High */
#define PSI5_1_CH0_DSRL      PSI5_1.CH0_DSRL.R             /* Data Shift Register Low */
#define PSI5_1_CH0_DSRH      PSI5_1.CH0_DSRH.R             /* Data Shift Register High */
#define PSI5_1_CH1_PCCR      PSI5_1.CH1_PCCR.R             /* PSI5 Channel Control Register */
#define PSI5_1_CH1_DCR       PSI5_1.CH1_DCR.R              /* DMA Control Register */
#define PSI5_1_CH1_DSR       PSI5_1.CH1_DSR.R              /* DMA Status Register */
#define PSI5_1_CH1_GICR      PSI5_1.CH1_GICR.R             /* General Interrupt Control Register */
#define PSI5_1_CH1_NDICR     PSI5_1.CH1_NDICR.R            /* New Data Interrupt Control Register */
#define PSI5_1_CH1_OWICR     PSI5_1.CH1_OWICR.R            /* Overwrite Interrupt Control Register */
#define PSI5_1_CH1_EICR      PSI5_1.CH1_EICR.R             /* Error Interrupt Control Register */
#define PSI5_1_CH1_GISR      PSI5_1.CH1_GISR.R             /* General Interrupt Status Register */
#define PSI5_1_CH1_DPMR      PSI5_1.CH1_DPMR.R             /* DMA PSI5 Message Register */
#define PSI5_1_CH1_DSFR      PSI5_1.CH1_DSFR.R             /* DMA SMC Frame Register */
#define PSI5_1_CH1_DDSR      PSI5_1.CH1_DDSR.R             /* DMA Diagnostic Status Register */
#define PSI5_1_CH1_PMRRL     PSI5_1.CH1_PMRRL.R            /* PSI5 Message Receive Register Low */
#define PSI5_1_CH1_PMRRH     PSI5_1.CH1_PMRRH.R            /* PSI5 Message Receive Register High */
#define PSI5_1_CH1_PMRL0     PSI5_1.CH1[0].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH0     PSI5_1.CH1[0].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL1     PSI5_1.CH1[1].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH1     PSI5_1.CH1[1].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL2     PSI5_1.CH1[2].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH2     PSI5_1.CH1[2].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL3     PSI5_1.CH1[3].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH3     PSI5_1.CH1[3].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL4     PSI5_1.CH1[4].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH4     PSI5_1.CH1[4].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL5     PSI5_1.CH1[5].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH5     PSI5_1.CH1[5].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL6     PSI5_1.CH1[6].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH6     PSI5_1.CH1[6].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL7     PSI5_1.CH1[7].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH7     PSI5_1.CH1[7].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL8     PSI5_1.CH1[8].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH8     PSI5_1.CH1[8].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL9     PSI5_1.CH1[9].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH9     PSI5_1.CH1[9].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL10    PSI5_1.CH1[10].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH10    PSI5_1.CH1[10].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL11    PSI5_1.CH1[11].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH11    PSI5_1.CH1[11].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL12    PSI5_1.CH1[12].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH12    PSI5_1.CH1[12].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL13    PSI5_1.CH1[13].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH13    PSI5_1.CH1[13].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL14    PSI5_1.CH1[14].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH14    PSI5_1.CH1[14].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL15    PSI5_1.CH1[15].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH15    PSI5_1.CH1[15].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL16    PSI5_1.CH1[16].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH16    PSI5_1.CH1[16].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL17    PSI5_1.CH1[17].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH17    PSI5_1.CH1[17].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL18    PSI5_1.CH1[18].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH18    PSI5_1.CH1[18].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL19    PSI5_1.CH1[19].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH19    PSI5_1.CH1[19].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL20    PSI5_1.CH1[20].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH20    PSI5_1.CH1[20].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL21    PSI5_1.CH1[21].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH21    PSI5_1.CH1[21].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL22    PSI5_1.CH1[22].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH22    PSI5_1.CH1[22].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL23    PSI5_1.CH1[23].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH23    PSI5_1.CH1[23].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL24    PSI5_1.CH1[24].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH24    PSI5_1.CH1[24].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL25    PSI5_1.CH1[25].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH25    PSI5_1.CH1[25].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL26    PSI5_1.CH1[26].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH26    PSI5_1.CH1[26].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL27    PSI5_1.CH1[27].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH27    PSI5_1.CH1[27].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL28    PSI5_1.CH1[28].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH28    PSI5_1.CH1[28].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL29    PSI5_1.CH1[29].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH29    PSI5_1.CH1[29].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL30    PSI5_1.CH1[30].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH30    PSI5_1.CH1[30].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_PMRL31    PSI5_1.CH1[31].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH1_PMRH31    PSI5_1.CH1[31].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH1_SFR1      PSI5_1.CH1_SFR[0].R           /* SMC Frame Register n */
#define PSI5_1_CH1_SFR2      PSI5_1.CH1_SFR[1].R           /* SMC Frame Register n */
#define PSI5_1_CH1_SFR3      PSI5_1.CH1_SFR[2].R           /* SMC Frame Register n */
#define PSI5_1_CH1_SFR4      PSI5_1.CH1_SFR[3].R           /* SMC Frame Register n */
#define PSI5_1_CH1_SFR5      PSI5_1.CH1_SFR[4].R           /* SMC Frame Register n */
#define PSI5_1_CH1_SFR6      PSI5_1.CH1_SFR[5].R           /* SMC Frame Register n */
#define PSI5_1_CH1_NDSR      PSI5_1.CH1_NDSR.R             /* New Data Status Register */
#define PSI5_1_CH1_OWSR      PSI5_1.CH1_OWSR.R             /* Overwrite Status Register */
#define PSI5_1_CH1_EISR      PSI5_1.CH1_EISR.R             /* Error Indication Status Register */
#define PSI5_1_CH1_SNDSR     PSI5_1.CH1_SNDSR.R            /* Set New Data Status Register */
#define PSI5_1_CH1_SOWSR     PSI5_1.CH1_SOWSR.R            /* Set Overwrite Status Register */
#define PSI5_1_CH1_SEISR     PSI5_1.CH1_SEISR.R            /* Set Error Status Register */
#define PSI5_1_CH1_SSESR     PSI5_1.CH1_SSESR.R            /* Set SMC Error Status Register */
#define PSI5_1_CH1_STSRR     PSI5_1.CH1_STSRR.R            /* Sync Time Stamp Read Register */
#define PSI5_1_CH1_DTSRR     PSI5_1.CH1_DTSRR.R            /* Data Time Stamp Read Register */
#define PSI5_1_CH1_S1FCR     PSI5_1.CH1_SFCR[0].R          /* Slot n Frame Configuration Register */
#define PSI5_1_CH1_S2FCR     PSI5_1.CH1_SFCR[1].R          /* Slot n Frame Configuration Register */
#define PSI5_1_CH1_S3FCR     PSI5_1.CH1_SFCR[2].R          /* Slot n Frame Configuration Register */
#define PSI5_1_CH1_S4FCR     PSI5_1.CH1_SFCR[3].R          /* Slot n Frame Configuration Register */
#define PSI5_1_CH1_S5FCR     PSI5_1.CH1_SFCR[4].R          /* Slot n Frame Configuration Register */
#define PSI5_1_CH1_S6FCR     PSI5_1.CH1_SFCR[5].R          /* Slot n Frame Configuration Register */
#define PSI5_1_CH1_S1SBR     PSI5_1.CH1_S1SBR.R            /* Slot 1 Start Boundary Register */
#define PSI5_1_CH1_S2SBR     PSI5_1.CH1_S2SBR.R            /* Slot 2 Start Boundary Register */
#define PSI5_1_CH1_S3SBR     PSI5_1.CH1_S3SBR.R            /* Slot 3 Start Boundary Register */
#define PSI5_1_CH1_S4SBR     PSI5_1.CH1_S4SBR.R            /* Slot 4 Start Boundary Register */
#define PSI5_1_CH1_S5SBR     PSI5_1.CH1_S5SBR.R            /* Slot 5 Start Boundary Register */
#define PSI5_1_CH1_S6SBR     PSI5_1.CH1_S6SBR.R            /* Slot 6 Start Boundary Register */
#define PSI5_1_CH1_SnEBR     PSI5_1.CH1_SnEBR.R            /* Slot n End Boundary Register */
#define PSI5_1_CH1_DOBCR     PSI5_1.CH1_DOBCR.R            /* Data Output Block Configuration Register */
#define PSI5_1_CH1_MDDIS_OFF PSI5_1.CH1_MDDIS_OFF.R        /* Manchestor Decoder Disable Offset */
#define PSI5_1_CH1_PW0D      PSI5_1.CH1_PW0D.R             /* Pulse Width for Data Bit Value 0 */
#define PSI5_1_CH1_PW1D      PSI5_1.CH1_PW1D.R             /* Pulse Width for Data Bit Value 1 */
#define PSI5_1_CH1_CTPR      PSI5_1.CH1_CTPR.R             /* Counter Target Pulse Register */
#define PSI5_1_CH1_CIPR      PSI5_1.CH1_CIPR.R             /* Counter Initialize Pulse Register */
#define PSI5_1_CH1_DPRL      PSI5_1.CH1_DPRL.R             /* Data Preparation Register Low */
#define PSI5_1_CH1_DPRH      PSI5_1.CH1_DPRH.R             /* Data Preparation Register High */
#define PSI5_1_CH1_DBRL      PSI5_1.CH1_DBRL.R             /* Data Buffer Register Low */
#define PSI5_1_CH1_DBRH      PSI5_1.CH1_DBRH.R             /* Data Buffer Register High */
#define PSI5_1_CH1_DSRL      PSI5_1.CH1_DSRL.R             /* Data Shift Register Low */
#define PSI5_1_CH1_DSRH      PSI5_1.CH1_DSRH.R             /* Data Shift Register High */
#define PSI5_1_CH2_PCCR      PSI5_1.CH2_PCCR.R             /* PSI5 Channel Control Register */
#define PSI5_1_CH2_DCR       PSI5_1.CH2_DCR.R              /* DMA Control Register */
#define PSI5_1_CH2_DSR       PSI5_1.CH2_DSR.R              /* DMA Status Register */
#define PSI5_1_CH2_GICR      PSI5_1.CH2_GICR.R             /* General Interrupt Control Register */
#define PSI5_1_CH2_NDICR     PSI5_1.CH2_NDICR.R            /* New Data Interrupt Control Register */
#define PSI5_1_CH2_OWICR     PSI5_1.CH2_OWICR.R            /* Overwrite Interrupt Control Register */
#define PSI5_1_CH2_EICR      PSI5_1.CH2_EICR.R             /* Error Interrupt Control Register */
#define PSI5_1_CH2_GISR      PSI5_1.CH2_GISR.R             /* General Interrupt Status Register */
#define PSI5_1_CH2_DPMR      PSI5_1.CH2_DPMR.R             /* DMA PSI5 Message Register */
#define PSI5_1_CH2_DSFR      PSI5_1.CH2_DSFR.R             /* DMA SMC Frame Register */
#define PSI5_1_CH2_DDSR      PSI5_1.CH2_DDSR.R             /* DMA Diagnostic Status Register */
#define PSI5_1_CH2_PMRRL     PSI5_1.CH2_PMRRL.R            /* PSI5 Message Receive Register Low */
#define PSI5_1_CH2_PMRRH     PSI5_1.CH2_PMRRH.R            /* PSI5 Message Receive Register High */
#define PSI5_1_CH2_PMRL0     PSI5_1.CH2[0].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH0     PSI5_1.CH2[0].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL1     PSI5_1.CH2[1].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH1     PSI5_1.CH2[1].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL2     PSI5_1.CH2[2].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH2     PSI5_1.CH2[2].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL3     PSI5_1.CH2[3].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH3     PSI5_1.CH2[3].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL4     PSI5_1.CH2[4].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH4     PSI5_1.CH2[4].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL5     PSI5_1.CH2[5].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH5     PSI5_1.CH2[5].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL6     PSI5_1.CH2[6].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH6     PSI5_1.CH2[6].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL7     PSI5_1.CH2[7].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH7     PSI5_1.CH2[7].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL8     PSI5_1.CH2[8].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH8     PSI5_1.CH2[8].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL9     PSI5_1.CH2[9].PMRL.R          /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH9     PSI5_1.CH2[9].PMRH.R          /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL10    PSI5_1.CH2[10].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH10    PSI5_1.CH2[10].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL11    PSI5_1.CH2[11].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH11    PSI5_1.CH2[11].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL12    PSI5_1.CH2[12].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH12    PSI5_1.CH2[12].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL13    PSI5_1.CH2[13].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH13    PSI5_1.CH2[13].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL14    PSI5_1.CH2[14].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH14    PSI5_1.CH2[14].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL15    PSI5_1.CH2[15].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH15    PSI5_1.CH2[15].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL16    PSI5_1.CH2[16].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH16    PSI5_1.CH2[16].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL17    PSI5_1.CH2[17].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH17    PSI5_1.CH2[17].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL18    PSI5_1.CH2[18].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH18    PSI5_1.CH2[18].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL19    PSI5_1.CH2[19].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH19    PSI5_1.CH2[19].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL20    PSI5_1.CH2[20].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH20    PSI5_1.CH2[20].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL21    PSI5_1.CH2[21].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH21    PSI5_1.CH2[21].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL22    PSI5_1.CH2[22].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH22    PSI5_1.CH2[22].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL23    PSI5_1.CH2[23].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH23    PSI5_1.CH2[23].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL24    PSI5_1.CH2[24].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH24    PSI5_1.CH2[24].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL25    PSI5_1.CH2[25].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH25    PSI5_1.CH2[25].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL26    PSI5_1.CH2[26].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH26    PSI5_1.CH2[26].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL27    PSI5_1.CH2[27].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH27    PSI5_1.CH2[27].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL28    PSI5_1.CH2[28].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH28    PSI5_1.CH2[28].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL29    PSI5_1.CH2[29].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH29    PSI5_1.CH2[29].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL30    PSI5_1.CH2[30].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH30    PSI5_1.CH2[30].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_PMRL31    PSI5_1.CH2[31].PMRL.R         /* PSI5 Message Register Low i */
#define PSI5_1_CH2_PMRH31    PSI5_1.CH2[31].PMRH.R         /* PSI5 Message Register High i */
#define PSI5_1_CH2_SFR1      PSI5_1.CH2_SFR[0].R           /* SMC Frame Register n */
#define PSI5_1_CH2_SFR2      PSI5_1.CH2_SFR[1].R           /* SMC Frame Register n */
#define PSI5_1_CH2_SFR3      PSI5_1.CH2_SFR[2].R           /* SMC Frame Register n */
#define PSI5_1_CH2_SFR4      PSI5_1.CH2_SFR[3].R           /* SMC Frame Register n */
#define PSI5_1_CH2_SFR5      PSI5_1.CH2_SFR[4].R           /* SMC Frame Register n */
#define PSI5_1_CH2_SFR6      PSI5_1.CH2_SFR[5].R           /* SMC Frame Register n */
#define PSI5_1_CH2_NDSR      PSI5_1.CH2_NDSR.R             /* New Data Status Register */
#define PSI5_1_CH2_OWSR      PSI5_1.CH2_OWSR.R             /* Overwrite Status Register */
#define PSI5_1_CH2_EISR      PSI5_1.CH2_EISR.R             /* Error Indication Status Register */
#define PSI5_1_CH2_SNDSR     PSI5_1.CH2_SNDSR.R            /* Set New Data Status Register */
#define PSI5_1_CH2_SOWSR     PSI5_1.CH2_SOWSR.R            /* Set Overwrite Status Register */
#define PSI5_1_CH2_SEISR     PSI5_1.CH2_SEISR.R            /* Set Error Status Register */
#define PSI5_1_CH2_SSESR     PSI5_1.CH2_SSESR.R            /* Set SMC Error Status Register */
#define PSI5_1_CH2_STSRR     PSI5_1.CH2_STSRR.R            /* Sync Time Stamp Read Register */
#define PSI5_1_CH2_DTSRR     PSI5_1.CH2_DTSRR.R            /* Data Time Stamp Read Register */
#define PSI5_1_CH2_S1FCR     PSI5_1.CH2_SFCR[0].R          /* Slot n Frame Configuration Register */
#define PSI5_1_CH2_S2FCR     PSI5_1.CH2_SFCR[1].R          /* Slot n Frame Configuration Register */
#define PSI5_1_CH2_S3FCR     PSI5_1.CH2_SFCR[2].R          /* Slot n Frame Configuration Register */
#define PSI5_1_CH2_S4FCR     PSI5_1.CH2_SFCR[3].R          /* Slot n Frame Configuration Register */
#define PSI5_1_CH2_S5FCR     PSI5_1.CH2_SFCR[4].R          /* Slot n Frame Configuration Register */
#define PSI5_1_CH2_S6FCR     PSI5_1.CH2_SFCR[5].R          /* Slot n Frame Configuration Register */
#define PSI5_1_CH2_S1SBR     PSI5_1.CH2_S1SBR.R            /* Slot 1 Start Boundary Register */
#define PSI5_1_CH2_S2SBR     PSI5_1.CH2_S2SBR.R            /* Slot 2 Start Boundary Register */
#define PSI5_1_CH2_S3SBR     PSI5_1.CH2_S3SBR.R            /* Slot 3 Start Boundary Register */
#define PSI5_1_CH2_S4SBR     PSI5_1.CH2_S4SBR.R            /* Slot 4 Start Boundary Register */
#define PSI5_1_CH2_S5SBR     PSI5_1.CH2_S5SBR.R            /* Slot 5 Start Boundary Register */
#define PSI5_1_CH2_S6SBR     PSI5_1.CH2_S6SBR.R            /* Slot 6 Start Boundary Register */
#define PSI5_1_CH2_SnEBR     PSI5_1.CH2_SnEBR.R            /* Slot n End Boundary Register */
#define PSI5_1_CH2_DOBCR     PSI5_1.CH2_DOBCR.R            /* Data Output Block Configuration Register */
#define PSI5_1_CH2_MDDIS_OFF PSI5_1.CH2_MDDIS_OFF.R        /* Manchestor Decoder Disable Offset */
#define PSI5_1_CH2_PW0D      PSI5_1.CH2_PW0D.R             /* Pulse Width for Data Bit Value 0 */
#define PSI5_1_CH2_PW1D      PSI5_1.CH2_PW1D.R             /* Pulse Width for Data Bit Value 1 */
#define PSI5_1_CH2_CTPR      PSI5_1.CH2_CTPR.R             /* Counter Target Pulse Register */
#define PSI5_1_CH2_CIPR      PSI5_1.CH2_CIPR.R             /* Counter Initialize Pulse Register */
#define PSI5_1_CH2_DPRL      PSI5_1.CH2_DPRL.R             /* Data Preparation Register Low */
#define PSI5_1_CH2_DPRH      PSI5_1.CH2_DPRH.R             /* Data Preparation Register High */
#define PSI5_1_CH2_DBRL      PSI5_1.CH2_DBRL.R             /* Data Buffer Register Low */
#define PSI5_1_CH2_DBRH      PSI5_1.CH2_DBRH.R             /* Data Buffer Register High */
#define PSI5_1_CH2_DSRL      PSI5_1.CH2_DSRL.R             /* Data Shift Register Low */
#define PSI5_1_CH2_DSRH      PSI5_1.CH2_DSRH.R             /* Data Shift Register High */

/* PSI5S */
#define PSI5S_LINCR1         PSI5S.LINCR1.R                /* PSI5-S LIN Control Register 1 */
#define PSI5S_LINIER         PSI5S.LINIER.R                /* PSI5-S LIN Interrupt enable register */
#define PSI5S_LINSR          PSI5S.LINSR.R                 /* PSI5-S LIN Status Register */
#define PSI5S_UARTCR         PSI5S.UARTCR.R                /* PSI5-S UART Mode Control Register */
#define PSI5S_UARTSR         PSI5S.UARTSR.R                /* PSI5-S UART Mode Status Register */
#define PSI5S_LINFBRR        PSI5S.LINFBRR.R               /* PSI5-S LIN Fractional Baud Rate Register */
#define PSI5S_LINIBRR        PSI5S.LINIBRR.R               /* PSI5-S LIN Integer Baud Rate Register */
#define PSI5S_LINCR2         PSI5S.LINCR2.R                /* PSI5-S LIN Control Register 2 */
#define PSI5S_BDRL           PSI5S.BDRL.R                  /* PSI5-S Buffer Data Register Least Significant */
#define PSI5S_BDRM           PSI5S.BDRM.R                  /* PSI5-S Buffer Data Register Most Significant */
#define PSI5S_GCR            PSI5S.GCR.R                   /* PSI5-S Global Control register */
#define PSI5S_UARTPTO        PSI5S.UARTPTO.R               /* PSI5-S UART Preset Timeout Register */
#define PSI5S_UARTCTO        PSI5S.UARTCTO.R               /* UPSI5-S ART Current Timeout register */
#define PSI5S_DMATXE         PSI5S.DMATXE.R                /* DMA Tx Enable Register */
#define PSI5S_DMARXE         PSI5S.DMARXE.R                /* DMA Rx Enable Register */
#define PSI5S_PTD            PSI5S.PTD.R                   /* PSI5-S UART Tx Idle Delay Time Register */
#define PSI5S_GLCR           PSI5S.GLCR.R                  /* PSI5-S Global Control Register */
#define PSI5S_GLSR           PSI5S.GLSR.R                  /* PSI5-S Global Status Register */
#define PSI5S_CH_BASE_ADDR   PSI5S.CH_BASE_ADDR.R          /* PSI5-S CHANNEL_BASE_ADDRESS */
#define PSI5S_MRU_BUF2_REG0  PSI5S.MRU_BUF2_REG0.R         /* PSI5-S MRU OUTPUT BUFFER2 REGISTER0 */
#define PSI5S_MRU_BUF2_REG1  PSI5S.MRU_BUF2_REG1.R         /* PSI5-S MRU OUTPUT BUFFER2 REGISTER1 */
#define PSI5S_MRU_BUF2_REG2  PSI5S.MRU_BUF2_REG2.R         /* PSI5-S MRU OUTPUT BUFFER2 REGISTER2 */
#define PSI5S_MRU_BUF2_REG3  PSI5S.MRU_BUF2_REG3.R         /* PSI5-S MRU OUTPUT BUFFER2 REGISTER3 */
#define PSI5S_WD_DDTRIG_CLKDIV0 PSI5S.WD_DDTRIG_CLKDIV0.R  /* PSI5-S Clock Divider "0" for WatchDog and DownStream Data Shift Register Trigger Counters. Used for Channel1 and Channel2 */
#define PSI5S_WD_DDTRIG_CLKDIV1 PSI5S.WD_DDTRIG_CLKDIV1.R  /* PSI5-S Clock Divider "1" for WatchDog and DownStream Data Shift Register Trigger Counters. Used for Channel3 and Channel4 */
#define PSI5S_WD_DDTRIG_CLKDIV2 PSI5S.WD_DDTRIG_CLKDIV2.R  /* PSI5-S Clock Divider "2" for WatchDog and DownStream Data Shift Register Trigger Counters. Used for Channel5 and Channel6 */
#define PSI5S_WD_DDTRIG_CLKDIV3 PSI5S.WD_DDTRIG_CLKDIV3.R  /* PSI5-S Clock Divider "3" for WatchDog and DownStream Data Shift Register Trigger Counters. Used for Channel7 */
#define PSI5S_MBOX_SR_IRQ    PSI5S.MBOX_SR_IRQ.R           /* PSI5-S Mbox Status Irq */
#define PSI5S_ERR_SR_IRQ     PSI5S.ERR_SR_IRQ.R            /* PSI5-S Error Status Irq */
#define PSI5S_MBOX_SEL_IRQ0  PSI5S.SEL_IRQ[0].MBOX.R       /* PSI5-S Mailbox select IRQ[irq_n] */
#define PSI5S_ERR_SEL_IRQ0   PSI5S.SEL_IRQ[0].ERR.R        /* PSI5-S Error Select IRQ[iq_n] */
#define PSI5S_MBOX_SEL_IRQ1  PSI5S.SEL_IRQ[1].MBOX.R       /* PSI5-S Mailbox select IRQ[irq_n] */
#define PSI5S_ERR_SEL_IRQ1   PSI5S.SEL_IRQ[1].ERR.R        /* PSI5-S Error Select IRQ[iq_n] */
#define PSI5S_MBOX_SEL_IRQ2  PSI5S.SEL_IRQ[2].MBOX.R       /* PSI5-S Mailbox select IRQ[irq_n] */
#define PSI5S_ERR_SEL_IRQ2   PSI5S.SEL_IRQ[2].ERR.R        /* PSI5-S Error Select IRQ[iq_n] */
#define PSI5S_MBOX_SEL_IRQ3  PSI5S.SEL_IRQ[3].MBOX.R       /* PSI5-S Mailbox select IRQ[irq_n] */
#define PSI5S_ERR_SEL_IRQ3   PSI5S.SEL_IRQ[3].ERR.R        /* PSI5-S Error Select IRQ[iq_n] */
#define PSI5S_MBOX_SEL_IRQ4  PSI5S.SEL_IRQ[4].MBOX.R       /* PSI5-S Mailbox select IRQ[irq_n] */
#define PSI5S_ERR_SEL_IRQ4   PSI5S.SEL_IRQ[4].ERR.R        /* PSI5-S Error Select IRQ[iq_n] */
#define PSI5S_MBOX_SEL_IRQ5  PSI5S.SEL_IRQ[5].MBOX.R       /* PSI5-S Mailbox select IRQ[irq_n] */
#define PSI5S_ERR_SEL_IRQ5   PSI5S.SEL_IRQ[5].ERR.R        /* PSI5-S Error Select IRQ[iq_n] */
#define PSI5S_MBOX_SEL_IRQ6  PSI5S.SEL_IRQ[6].MBOX.R       /* PSI5-S Mailbox select IRQ[irq_n] */
#define PSI5S_ERR_SEL_IRQ6   PSI5S.SEL_IRQ[6].ERR.R        /* PSI5-S Error Select IRQ[iq_n] */
#define PSI5S_MBOX_SEL_IRQ7  PSI5S.SEL_IRQ[7].MBOX.R       /* PSI5-S Mailbox select IRQ[irq_n] */
#define PSI5S_ERR_SEL_IRQ7   PSI5S.SEL_IRQ[7].ERR.R        /* PSI5-S Error Select IRQ[iq_n] */
#define PSI5S_WDGTSSR        PSI5S.WDGTSSR.R               /* PSI5-S Watchdog Error Status and Watchdog Timestamp status register */
#define PSI5S_MSGA_CH0       PSI5S.MSGA_CH0.R              /* PSI5-S channel 0 message configuration register A */
#define PSI5S_MSGB_CH0       PSI5S.MSGB_CH0.R              /* PSI5-S channel 0 message configuration register B */
#define PSI5S_MBOX_SR_CH0    PSI5S.MBOX_SR_CH0.R           /* PSI5-S Mailbox status register channel0 */
#define PSI5S_MSGA_CH1       PSI5S.MSGA_CH1.R              /* PSI5-S channel message configuration register A */
#define PSI5S_MSGB_CH1       PSI5S.MSGB_CH1.R              /* PSI5-S channel message configuration register B */
#define PSI5S_MBOX_SR_CH1    PSI5S.MBOX_SR_CH1.R           /* PSI5-S Mailbox status register channel */
#define PSI5S_WD_CFGR_CH1    PSI5S.WD_CFGR_CH1.R           /* PSI5-S channel watchdog configuration register */
#define PSI5S_DDTRIG_OFFR_CH1 PSI5S.DDTRIG_OFFR_CH1.R      /* PSI5-S DDSR Trigger offset register channel */
#define PSI5S_DDTRIG_PERR_CH1 PSI5S.DDTRIG_PERR_CH1.R      /* PSI5-S DDSR Trigger period register channel */
#define PSI5S_E2SCR_CH1      PSI5S.E2SCR_CH1.R             /* PSI5-S ECU to Sensor Control Register */
#define PSI5S_E2SSR_CH1      PSI5S.E2SSR_CH1.R             /* PSI5-S ECU to Sensor Status Register */
#define PSI5S_DDSR_H_CH1     PSI5S.DDSR_H_CH1.R            /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
#define PSI5S_DDSR_L_CH1     PSI5S.DDSR_L_CH1.R            /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
#define PSI5S_MSGA_CH2       PSI5S.MSGA_CH2.R              /* PSI5-S channel message configuration register A */
#define PSI5S_MSGB_CH2       PSI5S.MSGB_CH2.R              /* PSI5-S channel message configuration register B */
#define PSI5S_MBOX_SR_CH2    PSI5S.MBOX_SR_CH2.R           /* PSI5-S Mailbox status register channel */
#define PSI5S_WD_CFGR_CH2    PSI5S.WD_CFGR_CH2.R           /* PSI5-S channel watchdog configuration register */
#define PSI5S_DDTRIG_OFFR_CH2 PSI5S.DDTRIG_OFFR_CH2.R      /* PSI5-S DDSR Trigger offset register channel */
#define PSI5S_DDTRIG_PERR_CH2 PSI5S.DDTRIG_PERR_CH2.R      /* PSI5-S DDSR Trigger period register channel */
#define PSI5S_E2SCR_CH2      PSI5S.E2SCR_CH2.R             /* PSI5-S ECU to Sensor Control Register */
#define PSI5S_E2SSR_CH2      PSI5S.E2SSR_CH2.R             /* PSI5-S ECU to Sensor Status Register */
#define PSI5S_DDSR_H_CH2     PSI5S.DDSR_H_CH2.R            /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
#define PSI5S_DDSR_L_CH2     PSI5S.DDSR_L_CH2.R            /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
#define PSI5S_MSGA_CH3       PSI5S.MSGA_CH3.R              /* PSI5-S channel message configuration register A */
#define PSI5S_MSGB_CH3       PSI5S.MSGB_CH3.R              /* PSI5-S channel message configuration register B */
#define PSI5S_MBOX_SR_CH3    PSI5S.MBOX_SR_CH3.R           /* PSI5-S Mailbox status register channel */
#define PSI5S_WD_CFGR_CH3    PSI5S.WD_CFGR_CH3.R           /* PSI5-S channel watchdog configuration register */
#define PSI5S_DDTRIG_OFFR_CH3 PSI5S.DDTRIG_OFFR_CH3.R      /* PSI5-S DDSR Trigger offset register channel */
#define PSI5S_DDTRIG_PERR_CH3 PSI5S.DDTRIG_PERR_CH3.R      /* PSI5-S DDSR Trigger period register channel */
#define PSI5S_E2SCR_CH3      PSI5S.E2SCR_CH3.R             /* PSI5-S ECU to Sensor Control Register */
#define PSI5S_E2SSR_CH3      PSI5S.E2SSR_CH3.R             /* PSI5-S ECU to Sensor Status Register */
#define PSI5S_DDSR_H_CH3     PSI5S.DDSR_H_CH3.R            /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
#define PSI5S_DDSR_L_CH3     PSI5S.DDSR_L_CH3.R            /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
#define PSI5S_MSGA_CH4       PSI5S.MSGA_CH4.R              /* PSI5-S channel message configuration register A */
#define PSI5S_MSGB_CH4       PSI5S.MSGB_CH4.R              /* PSI5-S channel message configuration register B */
#define PSI5S_MBOX_SR_CH4    PSI5S.MBOX_SR_CH4.R           /* PSI5-S Mailbox status register channel */
#define PSI5S_WD_CFGR_CH4    PSI5S.WD_CFGR_CH4.R           /* PSI5-S channel watchdog configuration register */
#define PSI5S_DDTRIG_OFFR_CH4 PSI5S.DDTRIG_OFFR_CH4.R      /* PSI5-S DDSR Trigger offset register channel */
#define PSI5S_DDTRIG_PERR_CH4 PSI5S.DDTRIG_PERR_CH4.R      /* PSI5-S DDSR Trigger period register channel */
#define PSI5S_E2SCR_CH4      PSI5S.E2SCR_CH4.R             /* PSI5-S ECU to Sensor Control Register */
#define PSI5S_E2SSR_CH4      PSI5S.E2SSR_CH4.R             /* PSI5-S ECU to Sensor Status Register */
#define PSI5S_DDSR_H_CH4     PSI5S.DDSR_H_CH4.R            /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
#define PSI5S_DDSR_L_CH4     PSI5S.DDSR_L_CH4.R            /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
#define PSI5S_MSGA_CH5       PSI5S.MSGA_CH5.R              /* PSI5-S channel message configuration register A */
#define PSI5S_MSGB_CH5       PSI5S.MSGB_CH5.R              /* PSI5-S channel message configuration register B */
#define PSI5S_MBOX_SR_CH5    PSI5S.MBOX_SR_CH5.R           /* PSI5-S Mailbox status register channel */
#define PSI5S_WD_CFGR_CH5    PSI5S.WD_CFGR_CH5.R           /* PSI5-S channel watchdog configuration register */
#define PSI5S_DDTRIG_OFFR_CH5 PSI5S.DDTRIG_OFFR_CH5.R      /* PSI5-S DDSR Trigger offset register channel */
#define PSI5S_DDTRIG_PERR_CH5 PSI5S.DDTRIG_PERR_CH5.R      /* PSI5-S DDSR Trigger period register channel */
#define PSI5S_E2SCR_CH5      PSI5S.E2SCR_CH5.R             /* PSI5-S ECU to Sensor Control Register */
#define PSI5S_E2SSR_CH5      PSI5S.E2SSR_CH5.R             /* PSI5-S ECU to Sensor Status Register */
#define PSI5S_DDSR_H_CH5     PSI5S.DDSR_H_CH5.R            /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
#define PSI5S_DDSR_L_CH5     PSI5S.DDSR_L_CH5.R            /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
#define PSI5S_MSGA_CH6       PSI5S.MSGA_CH6.R              /* PSI5-S channel message configuration register A */
#define PSI5S_MSGB_CH6       PSI5S.MSGB_CH6.R              /* PSI5-S channel message configuration register B */
#define PSI5S_MBOX_SR_CH6    PSI5S.MBOX_SR_CH6.R           /* PSI5-S Mailbox status register channel */
#define PSI5S_WD_CFGR_CH6    PSI5S.WD_CFGR_CH6.R           /* PSI5-S channel watchdog configuration register */
#define PSI5S_DDTRIG_OFFR_CH6 PSI5S.DDTRIG_OFFR_CH6.R      /* PSI5-S DDSR Trigger offset register channel */
#define PSI5S_DDTRIG_PERR_CH6 PSI5S.DDTRIG_PERR_CH6.R      /* PSI5-S DDSR Trigger period register channel */
#define PSI5S_E2SCR_CH6      PSI5S.E2SCR_CH6.R             /* PSI5-S ECU to Sensor Control Register */
#define PSI5S_E2SSR_CH6      PSI5S.E2SSR_CH6.R             /* PSI5-S ECU to Sensor Status Register */
#define PSI5S_DDSR_H_CH6     PSI5S.DDSR_H_CH6.R            /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
#define PSI5S_DDSR_L_CH6     PSI5S.DDSR_L_CH6.R            /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
#define PSI5S_MSGA_CH7       PSI5S.MSGA_CH7.R              /* PSI5-S channel message configuration register A */
#define PSI5S_MSGB_CH7       PSI5S.MSGB_CH7.R              /* PSI5-S channel message configuration register B */
#define PSI5S_MBOX_SR_CH7    PSI5S.MBOX_SR_CH7.R           /* PSI5-S Mailbox status register channel */
#define PSI5S_WD_CFGR_CH7    PSI5S.WD_CFGR_CH7.R           /* PSI5-S channel watchdog configuration register */
#define PSI5S_DDTRIG_OFFR_CH7 PSI5S.DDTRIG_OFFR_CH7.R      /* PSI5-S DDSR Trigger offset register channel */
#define PSI5S_DDTRIG_PERR_CH7 PSI5S.DDTRIG_PERR_CH7.R      /* PSI5-S DDSR Trigger period register channel */
#define PSI5S_E2SCR_CH7      PSI5S.E2SCR_CH7.R             /* PSI5-S ECU to Sensor Control Register */
#define PSI5S_E2SSR_CH7      PSI5S.E2SSR_CH7.R             /* PSI5-S ECU to Sensor Status Register */
#define PSI5S_DDSR_H_CH7     PSI5S.DDSR_H_CH7.R            /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
#define PSI5S_DDSR_L_CH7     PSI5S.DDSR_L_CH7.R            /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */

/* REG_PROT */
#define REG_PROT_SLBRn       REG_PROT.SLBRn.R              /* Soft Lock Bit Register n */
#define REG_PROT_GCR         REG_PROT.GCR.R                /* Global Configuration Register */

/* SARADC */
#define SARADC_0_MCR         SARADC_0.MCR.R                /* Main Configuration Register */
#define SARADC_0_MSR         SARADC_0.MSR.R                /* Main Status Register */
#define SARADC_0_ISR         SARADC_0.ISR.R                /* Interrupt Status Register */
#define SARADC_0_ICIPR0      SARADC_0.ICIPR[0].R           /* Internal channel Interrupt Pending Register */
#define SARADC_0_ICIPR1      SARADC_0.ICIPR[1].R           /* Internal channel Interrupt Pending Register */
#define SARADC_0_ICIPR2      SARADC_0.ICIPR[2].R           /* Internal channel Interrupt Pending Register */
#define SARADC_0_IMR         SARADC_0.IMR.R                /* Interrupt Mask Register */
#define SARADC_0_ICIMR0      SARADC_0.ICIMR[0].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_0_ICIMR1      SARADC_0.ICIMR[1].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_0_ICIMR2      SARADC_0.ICIMR[2].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_0_WTISR       SARADC_0.WTISR.R              /* Watchdog Threshold Interrupt Status Register */
#define SARADC_0_WTIMR       SARADC_0.WTIMR.R              /* Watchdog Threshold Interrupt Mask Register */
#define SARADC_0_DMAE        SARADC_0.DMAE.R               /* DMA Enable Register */
#define SARADC_0_ICDSR0      SARADC_0.ICDSR[0].R           /* Internal Channel DMA Select Register */
#define SARADC_0_ICDSR1      SARADC_0.ICDSR[1].R           /* Internal Channel DMA Select Register */
#define SARADC_0_ICDSR2      SARADC_0.ICDSR[2].R           /* Internal Channel DMA Select Register */
#define SARADC_0_WTHRHLR0    SARADC_0.WTHRHLR[0].R         /* Watchdog Threshold Register */
#define SARADC_0_WTHRHLR1    SARADC_0.WTHRHLR[1].R         /* Watchdog Threshold Register */
#define SARADC_0_WTHRHLR2    SARADC_0.WTHRHLR[2].R         /* Watchdog Threshold Register */
#define SARADC_0_WTHRHLR3    SARADC_0.WTHRHLR[3].R         /* Watchdog Threshold Register */
#define SARADC_0_CTR0        SARADC_0.CTR[0].R             /* Conversion Timing Register */
#define SARADC_0_CTR1        SARADC_0.CTR[1].R             /* Conversion Timing Register */
#define SARADC_0_CTR2        SARADC_0.CTR[2].R             /* Conversion Timing Register */
#define SARADC_0_CTR3        SARADC_0.CTR[3].R             /* Conversion Timing Register */
#define SARADC_0_ICNCMR0     SARADC_0.ICNCMR[0].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_0_ICNCMR1     SARADC_0.ICNCMR[1].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_0_ICNCMR2     SARADC_0.ICNCMR[2].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_0_ICJCMR0     SARADC_0.ICJCMR[0].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_0_ICJCMR1     SARADC_0.ICJCMR[1].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_0_ICJCMR2     SARADC_0.ICJCMR[2].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_0_PDEDR       SARADC_0.PDEDR.R              /* Power Down Exit Delay Register */
#define SARADC_0_ICDR0       SARADC_0.ICDR[0].R            /* Internal Channel Data Register */
#define SARADC_0_ICDR1       SARADC_0.ICDR[1].R            /* Internal Channel Data Register */
#define SARADC_0_ICDR2       SARADC_0.ICDR[2].R            /* Internal Channel Data Register */
#define SARADC_0_ICDR3       SARADC_0.ICDR[3].R            /* Internal Channel Data Register */
#define SARADC_0_ICDR4       SARADC_0.ICDR[4].R            /* Internal Channel Data Register */
#define SARADC_0_ICDR5       SARADC_0.ICDR[5].R            /* Internal Channel Data Register */
#define SARADC_0_ICDR6       SARADC_0.ICDR[6].R            /* Internal Channel Data Register */
#define SARADC_0_ICDR7       SARADC_0.ICDR[7].R            /* Internal Channel Data Register */
#define SARADC_0_ICDR8       SARADC_0.ICDR[8].R            /* Internal Channel Data Register */
#define SARADC_0_ICDR9       SARADC_0.ICDR[9].R            /* Internal Channel Data Register */
#define SARADC_0_ICDR10      SARADC_0.ICDR[10].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR11      SARADC_0.ICDR[11].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR12      SARADC_0.ICDR[12].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR13      SARADC_0.ICDR[13].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR14      SARADC_0.ICDR[14].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR15      SARADC_0.ICDR[15].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR16      SARADC_0.ICDR[16].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR17      SARADC_0.ICDR[17].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR18      SARADC_0.ICDR[18].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR19      SARADC_0.ICDR[19].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR20      SARADC_0.ICDR[20].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR21      SARADC_0.ICDR[21].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR22      SARADC_0.ICDR[22].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR23      SARADC_0.ICDR[23].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR24      SARADC_0.ICDR[24].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR25      SARADC_0.ICDR[25].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR26      SARADC_0.ICDR[26].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR27      SARADC_0.ICDR[27].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR28      SARADC_0.ICDR[28].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR29      SARADC_0.ICDR[29].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR30      SARADC_0.ICDR[30].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR31      SARADC_0.ICDR[31].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR32      SARADC_0.ICDR[32].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR33      SARADC_0.ICDR[33].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR34      SARADC_0.ICDR[34].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR35      SARADC_0.ICDR[35].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR36      SARADC_0.ICDR[36].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR37      SARADC_0.ICDR[37].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR38      SARADC_0.ICDR[38].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR39      SARADC_0.ICDR[39].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR40      SARADC_0.ICDR[40].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR41      SARADC_0.ICDR[41].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR42      SARADC_0.ICDR[42].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR43      SARADC_0.ICDR[43].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR44      SARADC_0.ICDR[44].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR45      SARADC_0.ICDR[45].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR46      SARADC_0.ICDR[46].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR47      SARADC_0.ICDR[47].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR48      SARADC_0.ICDR[48].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR49      SARADC_0.ICDR[49].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR50      SARADC_0.ICDR[50].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR51      SARADC_0.ICDR[51].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR52      SARADC_0.ICDR[52].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR53      SARADC_0.ICDR[53].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR54      SARADC_0.ICDR[54].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR55      SARADC_0.ICDR[55].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR56      SARADC_0.ICDR[56].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR57      SARADC_0.ICDR[57].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR58      SARADC_0.ICDR[58].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR59      SARADC_0.ICDR[59].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR60      SARADC_0.ICDR[60].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR61      SARADC_0.ICDR[61].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR62      SARADC_0.ICDR[62].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR63      SARADC_0.ICDR[63].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR64      SARADC_0.ICDR[64].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR65      SARADC_0.ICDR[65].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR66      SARADC_0.ICDR[66].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR67      SARADC_0.ICDR[67].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR68      SARADC_0.ICDR[68].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR69      SARADC_0.ICDR[69].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR70      SARADC_0.ICDR[70].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR71      SARADC_0.ICDR[71].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR72      SARADC_0.ICDR[72].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR73      SARADC_0.ICDR[73].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR74      SARADC_0.ICDR[74].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR75      SARADC_0.ICDR[75].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR76      SARADC_0.ICDR[76].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR77      SARADC_0.ICDR[77].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR78      SARADC_0.ICDR[78].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR79      SARADC_0.ICDR[79].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR80      SARADC_0.ICDR[80].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR81      SARADC_0.ICDR[81].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR82      SARADC_0.ICDR[82].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR83      SARADC_0.ICDR[83].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR84      SARADC_0.ICDR[84].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR85      SARADC_0.ICDR[85].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR86      SARADC_0.ICDR[86].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR87      SARADC_0.ICDR[87].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR88      SARADC_0.ICDR[88].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR89      SARADC_0.ICDR[89].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR90      SARADC_0.ICDR[90].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR91      SARADC_0.ICDR[91].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR92      SARADC_0.ICDR[92].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR93      SARADC_0.ICDR[93].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR94      SARADC_0.ICDR[94].R           /* Internal Channel Data Register */
#define SARADC_0_ICDR95      SARADC_0.ICDR[95].R           /* Internal Channel Data Register */
#define SARADC_0_ICWSELR0    SARADC_0.ICWSELR[0].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_0_ICWSELR1    SARADC_0.ICWSELR[1].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_0_ICWSELR2    SARADC_0.ICWSELR[2].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_0_ICWSELR3    SARADC_0.ICWSELR[3].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_0_ICWSELR4    SARADC_0.ICWSELR[4].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_0_ICWSELR5    SARADC_0.ICWSELR[5].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_0_ICWSELR6    SARADC_0.ICWSELR[6].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_0_ICWSELR7    SARADC_0.ICWSELR[7].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_0_ICWSELR8    SARADC_0.ICWSELR[8].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_0_ICWSELR9    SARADC_0.ICWSELR[9].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_0_ICWSELR10   SARADC_0.ICWSELR[10].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_0_ICWSELR11   SARADC_0.ICWSELR[11].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_0_ICWENR0     SARADC_0.ICWENR[0].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_0_ICWENR1     SARADC_0.ICWENR[1].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_0_ICWENR2     SARADC_0.ICWENR[2].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_0_ICAWORR0    SARADC_0.ICAWORR[0].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_0_ICAWORR1    SARADC_0.ICAWORR[1].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_0_ICAWORR2    SARADC_0.ICAWORR[2].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_0_TCIPR       SARADC_0.TCIPR.R              /* Test Channel Interrupt Pending Register */
#define SARADC_0_TCIMR       SARADC_0.TCIMR.R              /* Test Channel Interrupt Mask Register */
#define SARADC_0_TCDSR       SARADC_0.TCDSR.R              /* Test Channel DMA Select Register */
#define SARADC_0_TCNCMR      SARADC_0.TCNCMR.R             /* Test Channel Normal Conversion Mask Register */
#define SARADC_0_TCJCMR      SARADC_0.TCJCMR.R             /* Test Channel Injected Conversion Mask Register */
#define SARADC_0_TCWSELR0    SARADC_0.TCWSELR[0].R         /* Test Channel Watchdog Selection Register */
#define SARADC_0_TCWSELR1    SARADC_0.TCWSELR[1].R         /* Test Channel Watchdog Selection Register */
#define SARADC_0_TCWSELR2    SARADC_0.TCWSELR[2].R         /* Test Channel Watchdog Selection Register */
#define SARADC_0_TCWSELR3    SARADC_0.TCWSELR[3].R         /* Test Channel Watchdog Selection Register */
#define SARADC_0_TCWENR      SARADC_0.TCWENR.R             /* Test Channel Watchdog Enable Register */
#define SARADC_0_TCAWORR     SARADC_0.TCAWORR.R            /* Test Channel Analog Watchdog Out of Range Register */
#define SARADC_0_TCCAPR0     SARADC_0.TCCAPR[0].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_0_TCCAPR1     SARADC_0.TCCAPR[1].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_0_TCCAPR2     SARADC_0.TCCAPR[2].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_0_TCCAPR3     SARADC_0.TCCAPR[3].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_0_TCCAPR4     SARADC_0.TCCAPR[4].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_0_TCCAPR5     SARADC_0.TCCAPR[5].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_0_TCCAPR6     SARADC_0.TCCAPR[6].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_0_TCCAPR7     SARADC_0.TCCAPR[7].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_0_TCDR96      SARADC_0.TCDR[0].R            /* Test Channel Data Register */
#define SARADC_0_TCDR97      SARADC_0.TCDR[1].R            /* Test Channel Data Register */
#define SARADC_0_TCDR98      SARADC_0.TCDR[2].R            /* Test Channel Data Register */
#define SARADC_0_TCDR99      SARADC_0.TCDR[3].R            /* Test Channel Data Register */
#define SARADC_0_TCDR100     SARADC_0.TCDR[4].R            /* Test Channel Data Register */
#define SARADC_0_TCDR101     SARADC_0.TCDR[5].R            /* Test Channel Data Register */
#define SARADC_0_TCDR102     SARADC_0.TCDR[6].R            /* Test Channel Data Register */
#define SARADC_0_TCDR103     SARADC_0.TCDR[7].R            /* Test Channel Data Register */
#define SARADC_0_TCDR104     SARADC_0.TCDR[8].R            /* Test Channel Data Register */
#define SARADC_0_TCDR105     SARADC_0.TCDR[9].R            /* Test Channel Data Register */
#define SARADC_0_TCDR106     SARADC_0.TCDR[10].R           /* Test Channel Data Register */
#define SARADC_0_TCDR107     SARADC_0.TCDR[11].R           /* Test Channel Data Register */
#define SARADC_0_TCDR108     SARADC_0.TCDR[12].R           /* Test Channel Data Register */
#define SARADC_0_TCDR109     SARADC_0.TCDR[13].R           /* Test Channel Data Register */
#define SARADC_0_TCDR110     SARADC_0.TCDR[14].R           /* Test Channel Data Register */
#define SARADC_0_TCDR111     SARADC_0.TCDR[15].R           /* Test Channel Data Register */
#define SARADC_0_TCDR112     SARADC_0.TCDR[16].R           /* Test Channel Data Register */
#define SARADC_0_TCDR113     SARADC_0.TCDR[17].R           /* Test Channel Data Register */
#define SARADC_0_TCDR114     SARADC_0.TCDR[18].R           /* Test Channel Data Register */
#define SARADC_0_TCDR115     SARADC_0.TCDR[19].R           /* Test Channel Data Register */
#define SARADC_0_TCDR116     SARADC_0.TCDR[20].R           /* Test Channel Data Register */
#define SARADC_0_TCDR117     SARADC_0.TCDR[21].R           /* Test Channel Data Register */
#define SARADC_0_TCDR118     SARADC_0.TCDR[22].R           /* Test Channel Data Register */
#define SARADC_0_TCDR119     SARADC_0.TCDR[23].R           /* Test Channel Data Register */
#define SARADC_0_TCDR120     SARADC_0.TCDR[24].R           /* Test Channel Data Register */
#define SARADC_0_TCDR121     SARADC_0.TCDR[25].R           /* Test Channel Data Register */
#define SARADC_0_TCDR122     SARADC_0.TCDR[26].R           /* Test Channel Data Register */
#define SARADC_0_TCDR123     SARADC_0.TCDR[27].R           /* Test Channel Data Register */
#define SARADC_0_TCDR124     SARADC_0.TCDR[28].R           /* Test Channel Data Register */
#define SARADC_0_TCDR125     SARADC_0.TCDR[29].R           /* Test Channel Data Register */
#define SARADC_0_TCDR126     SARADC_0.TCDR[30].R           /* Test Channel Data Register */
#define SARADC_0_TCDR127     SARADC_0.TCDR[31].R           /* Test Channel Data Register */
#define SARADC_0_ECDSDR      SARADC_0.ECDSDR.R             /* External Channel Decode Signals Delay Register */
#define SARADC_0_ECIPR0      SARADC_0.ECIPR[0].R           /* External Channel Interrupt Pending Register */
#define SARADC_0_ECIPR1      SARADC_0.ECIPR[1].R           /* External Channel Interrupt Pending Register */
#define SARADC_0_ECIPR2      SARADC_0.ECIPR[2].R           /* External Channel Interrupt Pending Register */
#define SARADC_0_ECIPR3      SARADC_0.ECIPR[3].R           /* External Channel Interrupt Pending Register */
#define SARADC_0_ECIMR0      SARADC_0.ECIMR[0].R           /* External Channel Interrupt Mask Register */
#define SARADC_0_ECIMR1      SARADC_0.ECIMR[1].R           /* External Channel Interrupt Mask Register */
#define SARADC_0_ECIMR2      SARADC_0.ECIMR[2].R           /* External Channel Interrupt Mask Register */
#define SARADC_0_ECIMR3      SARADC_0.ECIMR[3].R           /* External Channel Interrupt Mask Register */
#define SARADC_0_ECDSR0      SARADC_0.ECDSR[0].R           /* External Channel DMA Select Register */
#define SARADC_0_ECDSR1      SARADC_0.ECDSR[1].R           /* External Channel DMA Select Register */
#define SARADC_0_ECDSR2      SARADC_0.ECDSR[2].R           /* External Channel DMA Select Register */
#define SARADC_0_ECDSR3      SARADC_0.ECDSR[3].R           /* External Channel DMA Select Register */
#define SARADC_0_ECNCMR0     SARADC_0.ECNCMR[0].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_0_ECNCMR1     SARADC_0.ECNCMR[1].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_0_ECNCMR2     SARADC_0.ECNCMR[2].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_0_ECNCMR3     SARADC_0.ECNCMR[3].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_0_ECJCMR0     SARADC_0.ECJCMR[0].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_0_ECJCMR1     SARADC_0.ECJCMR[1].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_0_ECJCMR2     SARADC_0.ECJCMR[2].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_0_ECJCMR3     SARADC_0.ECJCMR[3].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_0_ECWSELR0    SARADC_0.ECWSELR[0].R         /* External Channel Watchdog Selection Register */
#define SARADC_0_ECWSELR1    SARADC_0.ECWSELR[1].R         /* External Channel Watchdog Selection Register */
#define SARADC_0_ECWSELR2    SARADC_0.ECWSELR[2].R         /* External Channel Watchdog Selection Register */
#define SARADC_0_ECWSELR3    SARADC_0.ECWSELR[3].R         /* External Channel Watchdog Selection Register */
#define SARADC_0_ECWSELR4    SARADC_0.ECWSELR[4].R         /* External Channel Watchdog Selection Register */
#define SARADC_0_ECWSELR5    SARADC_0.ECWSELR[5].R         /* External Channel Watchdog Selection Register */
#define SARADC_0_ECWSELR6    SARADC_0.ECWSELR[6].R         /* External Channel Watchdog Selection Register */
#define SARADC_0_ECWSELR7    SARADC_0.ECWSELR[7].R         /* External Channel Watchdog Selection Register */
#define SARADC_0_ECWSELR8    SARADC_0.ECWSELR[8].R         /* External Channel Watchdog Selection Register */
#define SARADC_0_ECWSELR9    SARADC_0.ECWSELR[9].R         /* External Channel Watchdog Selection Register */
#define SARADC_0_ECWSELR10   SARADC_0.ECWSELR[10].R        /* External Channel Watchdog Selection Register */
#define SARADC_0_ECWSELR11   SARADC_0.ECWSELR[11].R        /* External Channel Watchdog Selection Register */
#define SARADC_0_ECWSELR12   SARADC_0.ECWSELR[12].R        /* External Channel Watchdog Selection Register */
#define SARADC_0_ECWSELR13   SARADC_0.ECWSELR[13].R        /* External Channel Watchdog Selection Register */
#define SARADC_0_ECWSELR14   SARADC_0.ECWSELR[14].R        /* External Channel Watchdog Selection Register */
#define SARADC_0_ECWSELR15   SARADC_0.ECWSELR[15].R        /* External Channel Watchdog Selection Register */
#define SARADC_0_ECWENR0     SARADC_0.ECWENR[0].R          /* External Channel Watchdog Enable Register */
#define SARADC_0_ECWENR1     SARADC_0.ECWENR[1].R          /* External Channel Watchdog Enable Register */
#define SARADC_0_ECWENR2     SARADC_0.ECWENR[2].R          /* External Channel Watchdog Enable Register */
#define SARADC_0_ECWENR3     SARADC_0.ECWENR[3].R          /* External Channel Watchdog Enable Register */
#define SARADC_0_ECAWORR0    SARADC_0.ECAWORR[0].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_0_ECAWORR1    SARADC_0.ECAWORR[1].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_0_ECAWORR2    SARADC_0.ECAWORR[2].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_0_ECAWORR3    SARADC_0.ECAWORR[3].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_0_ECMICR0     SARADC_0.ECMICR[0].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_0_ECMICR1     SARADC_0.ECMICR[1].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_0_ECMICR2     SARADC_0.ECMICR[2].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_0_ECMICR3     SARADC_0.ECMICR[3].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_0_ECDR128     SARADC_0.ECDR[0].R            /* External Channel Data Register */
#define SARADC_0_ECDR129     SARADC_0.ECDR[1].R            /* External Channel Data Register */
#define SARADC_0_ECDR130     SARADC_0.ECDR[2].R            /* External Channel Data Register */
#define SARADC_0_ECDR131     SARADC_0.ECDR[3].R            /* External Channel Data Register */
#define SARADC_0_ECDR132     SARADC_0.ECDR[4].R            /* External Channel Data Register */
#define SARADC_0_ECDR133     SARADC_0.ECDR[5].R            /* External Channel Data Register */
#define SARADC_0_ECDR134     SARADC_0.ECDR[6].R            /* External Channel Data Register */
#define SARADC_0_ECDR135     SARADC_0.ECDR[7].R            /* External Channel Data Register */
#define SARADC_0_ECDR136     SARADC_0.ECDR[8].R            /* External Channel Data Register */
#define SARADC_0_ECDR137     SARADC_0.ECDR[9].R            /* External Channel Data Register */
#define SARADC_0_ECDR138     SARADC_0.ECDR[10].R           /* External Channel Data Register */
#define SARADC_0_ECDR139     SARADC_0.ECDR[11].R           /* External Channel Data Register */
#define SARADC_0_ECDR140     SARADC_0.ECDR[12].R           /* External Channel Data Register */
#define SARADC_0_ECDR141     SARADC_0.ECDR[13].R           /* External Channel Data Register */
#define SARADC_0_ECDR142     SARADC_0.ECDR[14].R           /* External Channel Data Register */
#define SARADC_0_ECDR143     SARADC_0.ECDR[15].R           /* External Channel Data Register */
#define SARADC_0_ECDR144     SARADC_0.ECDR[16].R           /* External Channel Data Register */
#define SARADC_0_ECDR145     SARADC_0.ECDR[17].R           /* External Channel Data Register */
#define SARADC_0_ECDR146     SARADC_0.ECDR[18].R           /* External Channel Data Register */
#define SARADC_0_ECDR147     SARADC_0.ECDR[19].R           /* External Channel Data Register */
#define SARADC_0_ECDR148     SARADC_0.ECDR[20].R           /* External Channel Data Register */
#define SARADC_0_ECDR149     SARADC_0.ECDR[21].R           /* External Channel Data Register */
#define SARADC_0_ECDR150     SARADC_0.ECDR[22].R           /* External Channel Data Register */
#define SARADC_0_ECDR151     SARADC_0.ECDR[23].R           /* External Channel Data Register */
#define SARADC_0_ECDR152     SARADC_0.ECDR[24].R           /* External Channel Data Register */
#define SARADC_0_ECDR153     SARADC_0.ECDR[25].R           /* External Channel Data Register */
#define SARADC_0_ECDR154     SARADC_0.ECDR[26].R           /* External Channel Data Register */
#define SARADC_0_ECDR155     SARADC_0.ECDR[27].R           /* External Channel Data Register */
#define SARADC_0_ECDR156     SARADC_0.ECDR[28].R           /* External Channel Data Register */
#define SARADC_0_ECDR157     SARADC_0.ECDR[29].R           /* External Channel Data Register */
#define SARADC_0_ECDR158     SARADC_0.ECDR[30].R           /* External Channel Data Register */
#define SARADC_0_ECDR159     SARADC_0.ECDR[31].R           /* External Channel Data Register */
#define SARADC_0_ECDR160     SARADC_0.ECDR[32].R           /* External Channel Data Register */
#define SARADC_0_ECDR161     SARADC_0.ECDR[33].R           /* External Channel Data Register */
#define SARADC_0_ECDR162     SARADC_0.ECDR[34].R           /* External Channel Data Register */
#define SARADC_0_ECDR163     SARADC_0.ECDR[35].R           /* External Channel Data Register */
#define SARADC_0_ECDR164     SARADC_0.ECDR[36].R           /* External Channel Data Register */
#define SARADC_0_ECDR165     SARADC_0.ECDR[37].R           /* External Channel Data Register */
#define SARADC_0_ECDR166     SARADC_0.ECDR[38].R           /* External Channel Data Register */
#define SARADC_0_ECDR167     SARADC_0.ECDR[39].R           /* External Channel Data Register */
#define SARADC_0_ECDR168     SARADC_0.ECDR[40].R           /* External Channel Data Register */
#define SARADC_0_ECDR169     SARADC_0.ECDR[41].R           /* External Channel Data Register */
#define SARADC_0_ECDR170     SARADC_0.ECDR[42].R           /* External Channel Data Register */
#define SARADC_0_ECDR171     SARADC_0.ECDR[43].R           /* External Channel Data Register */
#define SARADC_0_ECDR172     SARADC_0.ECDR[44].R           /* External Channel Data Register */
#define SARADC_0_ECDR173     SARADC_0.ECDR[45].R           /* External Channel Data Register */
#define SARADC_0_ECDR174     SARADC_0.ECDR[46].R           /* External Channel Data Register */
#define SARADC_0_ECDR175     SARADC_0.ECDR[47].R           /* External Channel Data Register */
#define SARADC_0_ECDR176     SARADC_0.ECDR[48].R           /* External Channel Data Register */
#define SARADC_0_ECDR177     SARADC_0.ECDR[49].R           /* External Channel Data Register */
#define SARADC_0_ECDR178     SARADC_0.ECDR[50].R           /* External Channel Data Register */
#define SARADC_0_ECDR179     SARADC_0.ECDR[51].R           /* External Channel Data Register */
#define SARADC_0_ECDR180     SARADC_0.ECDR[52].R           /* External Channel Data Register */
#define SARADC_0_ECDR181     SARADC_0.ECDR[53].R           /* External Channel Data Register */
#define SARADC_0_ECDR182     SARADC_0.ECDR[54].R           /* External Channel Data Register */
#define SARADC_0_ECDR183     SARADC_0.ECDR[55].R           /* External Channel Data Register */
#define SARADC_0_ECDR184     SARADC_0.ECDR[56].R           /* External Channel Data Register */
#define SARADC_0_ECDR185     SARADC_0.ECDR[57].R           /* External Channel Data Register */
#define SARADC_0_ECDR186     SARADC_0.ECDR[58].R           /* External Channel Data Register */
#define SARADC_0_ECDR187     SARADC_0.ECDR[59].R           /* External Channel Data Register */
#define SARADC_0_ECDR188     SARADC_0.ECDR[60].R           /* External Channel Data Register */
#define SARADC_0_ECDR189     SARADC_0.ECDR[61].R           /* External Channel Data Register */
#define SARADC_0_ECDR190     SARADC_0.ECDR[62].R           /* External Channel Data Register */
#define SARADC_0_ECDR191     SARADC_0.ECDR[63].R           /* External Channel Data Register */
#define SARADC_0_ECDR192     SARADC_0.ECDR[64].R           /* External Channel Data Register */
#define SARADC_0_ECDR193     SARADC_0.ECDR[65].R           /* External Channel Data Register */
#define SARADC_0_ECDR194     SARADC_0.ECDR[66].R           /* External Channel Data Register */
#define SARADC_0_ECDR195     SARADC_0.ECDR[67].R           /* External Channel Data Register */
#define SARADC_0_ECDR196     SARADC_0.ECDR[68].R           /* External Channel Data Register */
#define SARADC_0_ECDR197     SARADC_0.ECDR[69].R           /* External Channel Data Register */
#define SARADC_0_ECDR198     SARADC_0.ECDR[70].R           /* External Channel Data Register */
#define SARADC_0_ECDR199     SARADC_0.ECDR[71].R           /* External Channel Data Register */
#define SARADC_0_ECDR200     SARADC_0.ECDR[72].R           /* External Channel Data Register */
#define SARADC_0_ECDR201     SARADC_0.ECDR[73].R           /* External Channel Data Register */
#define SARADC_0_ECDR202     SARADC_0.ECDR[74].R           /* External Channel Data Register */
#define SARADC_0_ECDR203     SARADC_0.ECDR[75].R           /* External Channel Data Register */
#define SARADC_0_ECDR204     SARADC_0.ECDR[76].R           /* External Channel Data Register */
#define SARADC_0_ECDR205     SARADC_0.ECDR[77].R           /* External Channel Data Register */
#define SARADC_0_ECDR206     SARADC_0.ECDR[78].R           /* External Channel Data Register */
#define SARADC_0_ECDR207     SARADC_0.ECDR[79].R           /* External Channel Data Register */
#define SARADC_0_ECDR208     SARADC_0.ECDR[80].R           /* External Channel Data Register */
#define SARADC_0_ECDR209     SARADC_0.ECDR[81].R           /* External Channel Data Register */
#define SARADC_0_ECDR210     SARADC_0.ECDR[82].R           /* External Channel Data Register */
#define SARADC_0_ECDR211     SARADC_0.ECDR[83].R           /* External Channel Data Register */
#define SARADC_0_ECDR212     SARADC_0.ECDR[84].R           /* External Channel Data Register */
#define SARADC_0_ECDR213     SARADC_0.ECDR[85].R           /* External Channel Data Register */
#define SARADC_0_ECDR214     SARADC_0.ECDR[86].R           /* External Channel Data Register */
#define SARADC_0_ECDR215     SARADC_0.ECDR[87].R           /* External Channel Data Register */
#define SARADC_0_ECDR216     SARADC_0.ECDR[88].R           /* External Channel Data Register */
#define SARADC_0_ECDR217     SARADC_0.ECDR[89].R           /* External Channel Data Register */
#define SARADC_0_ECDR218     SARADC_0.ECDR[90].R           /* External Channel Data Register */
#define SARADC_0_ECDR219     SARADC_0.ECDR[91].R           /* External Channel Data Register */
#define SARADC_0_ECDR220     SARADC_0.ECDR[92].R           /* External Channel Data Register */
#define SARADC_0_ECDR221     SARADC_0.ECDR[93].R           /* External Channel Data Register */
#define SARADC_0_ECDR222     SARADC_0.ECDR[94].R           /* External Channel Data Register */
#define SARADC_0_ECDR223     SARADC_0.ECDR[95].R           /* External Channel Data Register */
#define SARADC_0_ECDR224     SARADC_0.ECDR[96].R           /* External Channel Data Register */
#define SARADC_0_ECDR225     SARADC_0.ECDR[97].R           /* External Channel Data Register */
#define SARADC_0_ECDR226     SARADC_0.ECDR[98].R           /* External Channel Data Register */
#define SARADC_0_ECDR227     SARADC_0.ECDR[99].R           /* External Channel Data Register */
#define SARADC_0_ECDR228     SARADC_0.ECDR[100].R          /* External Channel Data Register */
#define SARADC_0_ECDR229     SARADC_0.ECDR[101].R          /* External Channel Data Register */
#define SARADC_0_ECDR230     SARADC_0.ECDR[102].R          /* External Channel Data Register */
#define SARADC_0_ECDR231     SARADC_0.ECDR[103].R          /* External Channel Data Register */
#define SARADC_0_ECDR232     SARADC_0.ECDR[104].R          /* External Channel Data Register */
#define SARADC_0_ECDR233     SARADC_0.ECDR[105].R          /* External Channel Data Register */
#define SARADC_0_ECDR234     SARADC_0.ECDR[106].R          /* External Channel Data Register */
#define SARADC_0_ECDR235     SARADC_0.ECDR[107].R          /* External Channel Data Register */
#define SARADC_0_ECDR236     SARADC_0.ECDR[108].R          /* External Channel Data Register */
#define SARADC_0_ECDR237     SARADC_0.ECDR[109].R          /* External Channel Data Register */
#define SARADC_0_ECDR238     SARADC_0.ECDR[110].R          /* External Channel Data Register */
#define SARADC_0_ECDR239     SARADC_0.ECDR[111].R          /* External Channel Data Register */
#define SARADC_0_ECDR240     SARADC_0.ECDR[112].R          /* External Channel Data Register */
#define SARADC_0_ECDR241     SARADC_0.ECDR[113].R          /* External Channel Data Register */
#define SARADC_0_ECDR242     SARADC_0.ECDR[114].R          /* External Channel Data Register */
#define SARADC_0_ECDR243     SARADC_0.ECDR[115].R          /* External Channel Data Register */
#define SARADC_0_ECDR244     SARADC_0.ECDR[116].R          /* External Channel Data Register */
#define SARADC_0_ECDR245     SARADC_0.ECDR[117].R          /* External Channel Data Register */
#define SARADC_0_ECDR246     SARADC_0.ECDR[118].R          /* External Channel Data Register */
#define SARADC_0_ECDR247     SARADC_0.ECDR[119].R          /* External Channel Data Register */
#define SARADC_0_ECDR248     SARADC_0.ECDR[120].R          /* External Channel Data Register */
#define SARADC_0_ECDR249     SARADC_0.ECDR[121].R          /* External Channel Data Register */
#define SARADC_0_ECDR250     SARADC_0.ECDR[122].R          /* External Channel Data Register */
#define SARADC_0_ECDR251     SARADC_0.ECDR[123].R          /* External Channel Data Register */
#define SARADC_0_ECDR252     SARADC_0.ECDR[124].R          /* External Channel Data Register */
#define SARADC_0_ECDR253     SARADC_0.ECDR[125].R          /* External Channel Data Register */
#define SARADC_0_ECDR254     SARADC_0.ECDR[126].R          /* External Channel Data Register */
#define SARADC_0_ECDR255     SARADC_0.ECDR[127].R          /* External Channel Data Register */

/* SARADC */
#define SARADC_1_MCR         SARADC_1.MCR.R                /* Main Configuration Register */
#define SARADC_1_MSR         SARADC_1.MSR.R                /* Main Status Register */
#define SARADC_1_ISR         SARADC_1.ISR.R                /* Interrupt Status Register */
#define SARADC_1_ICIPR0      SARADC_1.ICIPR[0].R           /* Internal channel Interrupt Pending Register */
#define SARADC_1_ICIPR1      SARADC_1.ICIPR[1].R           /* Internal channel Interrupt Pending Register */
#define SARADC_1_ICIPR2      SARADC_1.ICIPR[2].R           /* Internal channel Interrupt Pending Register */
#define SARADC_1_IMR         SARADC_1.IMR.R                /* Interrupt Mask Register */
#define SARADC_1_ICIMR0      SARADC_1.ICIMR[0].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_1_ICIMR1      SARADC_1.ICIMR[1].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_1_ICIMR2      SARADC_1.ICIMR[2].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_1_WTISR       SARADC_1.WTISR.R              /* Watchdog Threshold Interrupt Status Register */
#define SARADC_1_WTIMR       SARADC_1.WTIMR.R              /* Watchdog Threshold Interrupt Mask Register */
#define SARADC_1_DMAE        SARADC_1.DMAE.R               /* DMA Enable Register */
#define SARADC_1_ICDSR0      SARADC_1.ICDSR[0].R           /* Internal Channel DMA Select Register */
#define SARADC_1_ICDSR1      SARADC_1.ICDSR[1].R           /* Internal Channel DMA Select Register */
#define SARADC_1_ICDSR2      SARADC_1.ICDSR[2].R           /* Internal Channel DMA Select Register */
#define SARADC_1_WTHRHLR0    SARADC_1.WTHRHLR[0].R         /* Watchdog Threshold Register */
#define SARADC_1_WTHRHLR1    SARADC_1.WTHRHLR[1].R         /* Watchdog Threshold Register */
#define SARADC_1_WTHRHLR2    SARADC_1.WTHRHLR[2].R         /* Watchdog Threshold Register */
#define SARADC_1_WTHRHLR3    SARADC_1.WTHRHLR[3].R         /* Watchdog Threshold Register */
#define SARADC_1_CTR0        SARADC_1.CTR[0].R             /* Conversion Timing Register */
#define SARADC_1_CTR1        SARADC_1.CTR[1].R             /* Conversion Timing Register */
#define SARADC_1_CTR2        SARADC_1.CTR[2].R             /* Conversion Timing Register */
#define SARADC_1_CTR3        SARADC_1.CTR[3].R             /* Conversion Timing Register */
#define SARADC_1_ICNCMR0     SARADC_1.ICNCMR[0].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_1_ICNCMR1     SARADC_1.ICNCMR[1].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_1_ICNCMR2     SARADC_1.ICNCMR[2].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_1_ICJCMR0     SARADC_1.ICJCMR[0].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_1_ICJCMR1     SARADC_1.ICJCMR[1].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_1_ICJCMR2     SARADC_1.ICJCMR[2].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_1_PDEDR       SARADC_1.PDEDR.R              /* Power Down Exit Delay Register */
#define SARADC_1_ICDR0       SARADC_1.ICDR[0].R            /* Internal Channel Data Register */
#define SARADC_1_ICDR1       SARADC_1.ICDR[1].R            /* Internal Channel Data Register */
#define SARADC_1_ICDR2       SARADC_1.ICDR[2].R            /* Internal Channel Data Register */
#define SARADC_1_ICDR3       SARADC_1.ICDR[3].R            /* Internal Channel Data Register */
#define SARADC_1_ICDR4       SARADC_1.ICDR[4].R            /* Internal Channel Data Register */
#define SARADC_1_ICDR5       SARADC_1.ICDR[5].R            /* Internal Channel Data Register */
#define SARADC_1_ICDR6       SARADC_1.ICDR[6].R            /* Internal Channel Data Register */
#define SARADC_1_ICDR7       SARADC_1.ICDR[7].R            /* Internal Channel Data Register */
#define SARADC_1_ICDR8       SARADC_1.ICDR[8].R            /* Internal Channel Data Register */
#define SARADC_1_ICDR9       SARADC_1.ICDR[9].R            /* Internal Channel Data Register */
#define SARADC_1_ICDR10      SARADC_1.ICDR[10].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR11      SARADC_1.ICDR[11].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR12      SARADC_1.ICDR[12].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR13      SARADC_1.ICDR[13].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR14      SARADC_1.ICDR[14].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR15      SARADC_1.ICDR[15].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR16      SARADC_1.ICDR[16].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR17      SARADC_1.ICDR[17].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR18      SARADC_1.ICDR[18].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR19      SARADC_1.ICDR[19].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR20      SARADC_1.ICDR[20].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR21      SARADC_1.ICDR[21].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR22      SARADC_1.ICDR[22].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR23      SARADC_1.ICDR[23].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR24      SARADC_1.ICDR[24].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR25      SARADC_1.ICDR[25].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR26      SARADC_1.ICDR[26].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR27      SARADC_1.ICDR[27].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR28      SARADC_1.ICDR[28].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR29      SARADC_1.ICDR[29].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR30      SARADC_1.ICDR[30].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR31      SARADC_1.ICDR[31].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR32      SARADC_1.ICDR[32].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR33      SARADC_1.ICDR[33].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR34      SARADC_1.ICDR[34].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR35      SARADC_1.ICDR[35].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR36      SARADC_1.ICDR[36].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR37      SARADC_1.ICDR[37].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR38      SARADC_1.ICDR[38].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR39      SARADC_1.ICDR[39].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR40      SARADC_1.ICDR[40].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR41      SARADC_1.ICDR[41].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR42      SARADC_1.ICDR[42].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR43      SARADC_1.ICDR[43].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR44      SARADC_1.ICDR[44].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR45      SARADC_1.ICDR[45].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR46      SARADC_1.ICDR[46].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR47      SARADC_1.ICDR[47].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR48      SARADC_1.ICDR[48].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR49      SARADC_1.ICDR[49].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR50      SARADC_1.ICDR[50].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR51      SARADC_1.ICDR[51].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR52      SARADC_1.ICDR[52].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR53      SARADC_1.ICDR[53].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR54      SARADC_1.ICDR[54].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR55      SARADC_1.ICDR[55].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR56      SARADC_1.ICDR[56].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR57      SARADC_1.ICDR[57].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR58      SARADC_1.ICDR[58].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR59      SARADC_1.ICDR[59].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR60      SARADC_1.ICDR[60].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR61      SARADC_1.ICDR[61].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR62      SARADC_1.ICDR[62].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR63      SARADC_1.ICDR[63].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR64      SARADC_1.ICDR[64].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR65      SARADC_1.ICDR[65].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR66      SARADC_1.ICDR[66].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR67      SARADC_1.ICDR[67].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR68      SARADC_1.ICDR[68].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR69      SARADC_1.ICDR[69].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR70      SARADC_1.ICDR[70].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR71      SARADC_1.ICDR[71].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR72      SARADC_1.ICDR[72].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR73      SARADC_1.ICDR[73].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR74      SARADC_1.ICDR[74].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR75      SARADC_1.ICDR[75].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR76      SARADC_1.ICDR[76].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR77      SARADC_1.ICDR[77].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR78      SARADC_1.ICDR[78].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR79      SARADC_1.ICDR[79].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR80      SARADC_1.ICDR[80].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR81      SARADC_1.ICDR[81].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR82      SARADC_1.ICDR[82].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR83      SARADC_1.ICDR[83].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR84      SARADC_1.ICDR[84].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR85      SARADC_1.ICDR[85].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR86      SARADC_1.ICDR[86].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR87      SARADC_1.ICDR[87].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR88      SARADC_1.ICDR[88].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR89      SARADC_1.ICDR[89].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR90      SARADC_1.ICDR[90].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR91      SARADC_1.ICDR[91].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR92      SARADC_1.ICDR[92].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR93      SARADC_1.ICDR[93].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR94      SARADC_1.ICDR[94].R           /* Internal Channel Data Register */
#define SARADC_1_ICDR95      SARADC_1.ICDR[95].R           /* Internal Channel Data Register */
#define SARADC_1_ICWSELR0    SARADC_1.ICWSELR[0].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_1_ICWSELR1    SARADC_1.ICWSELR[1].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_1_ICWSELR2    SARADC_1.ICWSELR[2].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_1_ICWSELR3    SARADC_1.ICWSELR[3].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_1_ICWSELR4    SARADC_1.ICWSELR[4].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_1_ICWSELR5    SARADC_1.ICWSELR[5].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_1_ICWSELR6    SARADC_1.ICWSELR[6].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_1_ICWSELR7    SARADC_1.ICWSELR[7].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_1_ICWSELR8    SARADC_1.ICWSELR[8].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_1_ICWSELR9    SARADC_1.ICWSELR[9].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_1_ICWSELR10   SARADC_1.ICWSELR[10].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_1_ICWSELR11   SARADC_1.ICWSELR[11].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_1_ICWENR0     SARADC_1.ICWENR[0].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_1_ICWENR1     SARADC_1.ICWENR[1].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_1_ICWENR2     SARADC_1.ICWENR[2].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_1_ICAWORR0    SARADC_1.ICAWORR[0].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_1_ICAWORR1    SARADC_1.ICAWORR[1].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_1_ICAWORR2    SARADC_1.ICAWORR[2].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_1_TCIPR       SARADC_1.TCIPR.R              /* Test Channel Interrupt Pending Register */
#define SARADC_1_TCIMR       SARADC_1.TCIMR.R              /* Test Channel Interrupt Mask Register */
#define SARADC_1_TCDSR       SARADC_1.TCDSR.R              /* Test Channel DMA Select Register */
#define SARADC_1_TCNCMR      SARADC_1.TCNCMR.R             /* Test Channel Normal Conversion Mask Register */
#define SARADC_1_TCJCMR      SARADC_1.TCJCMR.R             /* Test Channel Injected Conversion Mask Register */
#define SARADC_1_TCWSELR0    SARADC_1.TCWSELR[0].R         /* Test Channel Watchdog Selection Register */
#define SARADC_1_TCWSELR1    SARADC_1.TCWSELR[1].R         /* Test Channel Watchdog Selection Register */
#define SARADC_1_TCWSELR2    SARADC_1.TCWSELR[2].R         /* Test Channel Watchdog Selection Register */
#define SARADC_1_TCWSELR3    SARADC_1.TCWSELR[3].R         /* Test Channel Watchdog Selection Register */
#define SARADC_1_TCWENR      SARADC_1.TCWENR.R             /* Test Channel Watchdog Enable Register */
#define SARADC_1_TCAWORR     SARADC_1.TCAWORR.R            /* Test Channel Analog Watchdog Out of Range Register */
#define SARADC_1_TCCAPR0     SARADC_1.TCCAPR[0].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_1_TCCAPR1     SARADC_1.TCCAPR[1].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_1_TCCAPR2     SARADC_1.TCCAPR[2].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_1_TCCAPR3     SARADC_1.TCCAPR[3].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_1_TCCAPR4     SARADC_1.TCCAPR[4].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_1_TCCAPR5     SARADC_1.TCCAPR[5].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_1_TCCAPR6     SARADC_1.TCCAPR[6].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_1_TCCAPR7     SARADC_1.TCCAPR[7].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_1_TCDR96      SARADC_1.TCDR[0].R            /* Test Channel Data Register */
#define SARADC_1_TCDR97      SARADC_1.TCDR[1].R            /* Test Channel Data Register */
#define SARADC_1_TCDR98      SARADC_1.TCDR[2].R            /* Test Channel Data Register */
#define SARADC_1_TCDR99      SARADC_1.TCDR[3].R            /* Test Channel Data Register */
#define SARADC_1_TCDR100     SARADC_1.TCDR[4].R            /* Test Channel Data Register */
#define SARADC_1_TCDR101     SARADC_1.TCDR[5].R            /* Test Channel Data Register */
#define SARADC_1_TCDR102     SARADC_1.TCDR[6].R            /* Test Channel Data Register */
#define SARADC_1_TCDR103     SARADC_1.TCDR[7].R            /* Test Channel Data Register */
#define SARADC_1_TCDR104     SARADC_1.TCDR[8].R            /* Test Channel Data Register */
#define SARADC_1_TCDR105     SARADC_1.TCDR[9].R            /* Test Channel Data Register */
#define SARADC_1_TCDR106     SARADC_1.TCDR[10].R           /* Test Channel Data Register */
#define SARADC_1_TCDR107     SARADC_1.TCDR[11].R           /* Test Channel Data Register */
#define SARADC_1_TCDR108     SARADC_1.TCDR[12].R           /* Test Channel Data Register */
#define SARADC_1_TCDR109     SARADC_1.TCDR[13].R           /* Test Channel Data Register */
#define SARADC_1_TCDR110     SARADC_1.TCDR[14].R           /* Test Channel Data Register */
#define SARADC_1_TCDR111     SARADC_1.TCDR[15].R           /* Test Channel Data Register */
#define SARADC_1_TCDR112     SARADC_1.TCDR[16].R           /* Test Channel Data Register */
#define SARADC_1_TCDR113     SARADC_1.TCDR[17].R           /* Test Channel Data Register */
#define SARADC_1_TCDR114     SARADC_1.TCDR[18].R           /* Test Channel Data Register */
#define SARADC_1_TCDR115     SARADC_1.TCDR[19].R           /* Test Channel Data Register */
#define SARADC_1_TCDR116     SARADC_1.TCDR[20].R           /* Test Channel Data Register */
#define SARADC_1_TCDR117     SARADC_1.TCDR[21].R           /* Test Channel Data Register */
#define SARADC_1_TCDR118     SARADC_1.TCDR[22].R           /* Test Channel Data Register */
#define SARADC_1_TCDR119     SARADC_1.TCDR[23].R           /* Test Channel Data Register */
#define SARADC_1_TCDR120     SARADC_1.TCDR[24].R           /* Test Channel Data Register */
#define SARADC_1_TCDR121     SARADC_1.TCDR[25].R           /* Test Channel Data Register */
#define SARADC_1_TCDR122     SARADC_1.TCDR[26].R           /* Test Channel Data Register */
#define SARADC_1_TCDR123     SARADC_1.TCDR[27].R           /* Test Channel Data Register */
#define SARADC_1_TCDR124     SARADC_1.TCDR[28].R           /* Test Channel Data Register */
#define SARADC_1_TCDR125     SARADC_1.TCDR[29].R           /* Test Channel Data Register */
#define SARADC_1_TCDR126     SARADC_1.TCDR[30].R           /* Test Channel Data Register */
#define SARADC_1_TCDR127     SARADC_1.TCDR[31].R           /* Test Channel Data Register */
#define SARADC_1_ECDSDR      SARADC_1.ECDSDR.R             /* External Channel Decode Signals Delay Register */
#define SARADC_1_ECIPR0      SARADC_1.ECIPR[0].R           /* External Channel Interrupt Pending Register */
#define SARADC_1_ECIPR1      SARADC_1.ECIPR[1].R           /* External Channel Interrupt Pending Register */
#define SARADC_1_ECIPR2      SARADC_1.ECIPR[2].R           /* External Channel Interrupt Pending Register */
#define SARADC_1_ECIPR3      SARADC_1.ECIPR[3].R           /* External Channel Interrupt Pending Register */
#define SARADC_1_ECIMR0      SARADC_1.ECIMR[0].R           /* External Channel Interrupt Mask Register */
#define SARADC_1_ECIMR1      SARADC_1.ECIMR[1].R           /* External Channel Interrupt Mask Register */
#define SARADC_1_ECIMR2      SARADC_1.ECIMR[2].R           /* External Channel Interrupt Mask Register */
#define SARADC_1_ECIMR3      SARADC_1.ECIMR[3].R           /* External Channel Interrupt Mask Register */
#define SARADC_1_ECDSR0      SARADC_1.ECDSR[0].R           /* External Channel DMA Select Register */
#define SARADC_1_ECDSR1      SARADC_1.ECDSR[1].R           /* External Channel DMA Select Register */
#define SARADC_1_ECDSR2      SARADC_1.ECDSR[2].R           /* External Channel DMA Select Register */
#define SARADC_1_ECDSR3      SARADC_1.ECDSR[3].R           /* External Channel DMA Select Register */
#define SARADC_1_ECNCMR0     SARADC_1.ECNCMR[0].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_1_ECNCMR1     SARADC_1.ECNCMR[1].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_1_ECNCMR2     SARADC_1.ECNCMR[2].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_1_ECNCMR3     SARADC_1.ECNCMR[3].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_1_ECJCMR0     SARADC_1.ECJCMR[0].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_1_ECJCMR1     SARADC_1.ECJCMR[1].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_1_ECJCMR2     SARADC_1.ECJCMR[2].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_1_ECJCMR3     SARADC_1.ECJCMR[3].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_1_ECWSELR0    SARADC_1.ECWSELR[0].R         /* External Channel Watchdog Selection Register */
#define SARADC_1_ECWSELR1    SARADC_1.ECWSELR[1].R         /* External Channel Watchdog Selection Register */
#define SARADC_1_ECWSELR2    SARADC_1.ECWSELR[2].R         /* External Channel Watchdog Selection Register */
#define SARADC_1_ECWSELR3    SARADC_1.ECWSELR[3].R         /* External Channel Watchdog Selection Register */
#define SARADC_1_ECWSELR4    SARADC_1.ECWSELR[4].R         /* External Channel Watchdog Selection Register */
#define SARADC_1_ECWSELR5    SARADC_1.ECWSELR[5].R         /* External Channel Watchdog Selection Register */
#define SARADC_1_ECWSELR6    SARADC_1.ECWSELR[6].R         /* External Channel Watchdog Selection Register */
#define SARADC_1_ECWSELR7    SARADC_1.ECWSELR[7].R         /* External Channel Watchdog Selection Register */
#define SARADC_1_ECWSELR8    SARADC_1.ECWSELR[8].R         /* External Channel Watchdog Selection Register */
#define SARADC_1_ECWSELR9    SARADC_1.ECWSELR[9].R         /* External Channel Watchdog Selection Register */
#define SARADC_1_ECWSELR10   SARADC_1.ECWSELR[10].R        /* External Channel Watchdog Selection Register */
#define SARADC_1_ECWSELR11   SARADC_1.ECWSELR[11].R        /* External Channel Watchdog Selection Register */
#define SARADC_1_ECWSELR12   SARADC_1.ECWSELR[12].R        /* External Channel Watchdog Selection Register */
#define SARADC_1_ECWSELR13   SARADC_1.ECWSELR[13].R        /* External Channel Watchdog Selection Register */
#define SARADC_1_ECWSELR14   SARADC_1.ECWSELR[14].R        /* External Channel Watchdog Selection Register */
#define SARADC_1_ECWSELR15   SARADC_1.ECWSELR[15].R        /* External Channel Watchdog Selection Register */
#define SARADC_1_ECWENR0     SARADC_1.ECWENR[0].R          /* External Channel Watchdog Enable Register */
#define SARADC_1_ECWENR1     SARADC_1.ECWENR[1].R          /* External Channel Watchdog Enable Register */
#define SARADC_1_ECWENR2     SARADC_1.ECWENR[2].R          /* External Channel Watchdog Enable Register */
#define SARADC_1_ECWENR3     SARADC_1.ECWENR[3].R          /* External Channel Watchdog Enable Register */
#define SARADC_1_ECAWORR0    SARADC_1.ECAWORR[0].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_1_ECAWORR1    SARADC_1.ECAWORR[1].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_1_ECAWORR2    SARADC_1.ECAWORR[2].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_1_ECAWORR3    SARADC_1.ECAWORR[3].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_1_ECMICR0     SARADC_1.ECMICR[0].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_1_ECMICR1     SARADC_1.ECMICR[1].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_1_ECMICR2     SARADC_1.ECMICR[2].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_1_ECMICR3     SARADC_1.ECMICR[3].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_1_ECDR128     SARADC_1.ECDR[0].R            /* External Channel Data Register */
#define SARADC_1_ECDR129     SARADC_1.ECDR[1].R            /* External Channel Data Register */
#define SARADC_1_ECDR130     SARADC_1.ECDR[2].R            /* External Channel Data Register */
#define SARADC_1_ECDR131     SARADC_1.ECDR[3].R            /* External Channel Data Register */
#define SARADC_1_ECDR132     SARADC_1.ECDR[4].R            /* External Channel Data Register */
#define SARADC_1_ECDR133     SARADC_1.ECDR[5].R            /* External Channel Data Register */
#define SARADC_1_ECDR134     SARADC_1.ECDR[6].R            /* External Channel Data Register */
#define SARADC_1_ECDR135     SARADC_1.ECDR[7].R            /* External Channel Data Register */
#define SARADC_1_ECDR136     SARADC_1.ECDR[8].R            /* External Channel Data Register */
#define SARADC_1_ECDR137     SARADC_1.ECDR[9].R            /* External Channel Data Register */
#define SARADC_1_ECDR138     SARADC_1.ECDR[10].R           /* External Channel Data Register */
#define SARADC_1_ECDR139     SARADC_1.ECDR[11].R           /* External Channel Data Register */
#define SARADC_1_ECDR140     SARADC_1.ECDR[12].R           /* External Channel Data Register */
#define SARADC_1_ECDR141     SARADC_1.ECDR[13].R           /* External Channel Data Register */
#define SARADC_1_ECDR142     SARADC_1.ECDR[14].R           /* External Channel Data Register */
#define SARADC_1_ECDR143     SARADC_1.ECDR[15].R           /* External Channel Data Register */
#define SARADC_1_ECDR144     SARADC_1.ECDR[16].R           /* External Channel Data Register */
#define SARADC_1_ECDR145     SARADC_1.ECDR[17].R           /* External Channel Data Register */
#define SARADC_1_ECDR146     SARADC_1.ECDR[18].R           /* External Channel Data Register */
#define SARADC_1_ECDR147     SARADC_1.ECDR[19].R           /* External Channel Data Register */
#define SARADC_1_ECDR148     SARADC_1.ECDR[20].R           /* External Channel Data Register */
#define SARADC_1_ECDR149     SARADC_1.ECDR[21].R           /* External Channel Data Register */
#define SARADC_1_ECDR150     SARADC_1.ECDR[22].R           /* External Channel Data Register */
#define SARADC_1_ECDR151     SARADC_1.ECDR[23].R           /* External Channel Data Register */
#define SARADC_1_ECDR152     SARADC_1.ECDR[24].R           /* External Channel Data Register */
#define SARADC_1_ECDR153     SARADC_1.ECDR[25].R           /* External Channel Data Register */
#define SARADC_1_ECDR154     SARADC_1.ECDR[26].R           /* External Channel Data Register */
#define SARADC_1_ECDR155     SARADC_1.ECDR[27].R           /* External Channel Data Register */
#define SARADC_1_ECDR156     SARADC_1.ECDR[28].R           /* External Channel Data Register */
#define SARADC_1_ECDR157     SARADC_1.ECDR[29].R           /* External Channel Data Register */
#define SARADC_1_ECDR158     SARADC_1.ECDR[30].R           /* External Channel Data Register */
#define SARADC_1_ECDR159     SARADC_1.ECDR[31].R           /* External Channel Data Register */
#define SARADC_1_ECDR160     SARADC_1.ECDR[32].R           /* External Channel Data Register */
#define SARADC_1_ECDR161     SARADC_1.ECDR[33].R           /* External Channel Data Register */
#define SARADC_1_ECDR162     SARADC_1.ECDR[34].R           /* External Channel Data Register */
#define SARADC_1_ECDR163     SARADC_1.ECDR[35].R           /* External Channel Data Register */
#define SARADC_1_ECDR164     SARADC_1.ECDR[36].R           /* External Channel Data Register */
#define SARADC_1_ECDR165     SARADC_1.ECDR[37].R           /* External Channel Data Register */
#define SARADC_1_ECDR166     SARADC_1.ECDR[38].R           /* External Channel Data Register */
#define SARADC_1_ECDR167     SARADC_1.ECDR[39].R           /* External Channel Data Register */
#define SARADC_1_ECDR168     SARADC_1.ECDR[40].R           /* External Channel Data Register */
#define SARADC_1_ECDR169     SARADC_1.ECDR[41].R           /* External Channel Data Register */
#define SARADC_1_ECDR170     SARADC_1.ECDR[42].R           /* External Channel Data Register */
#define SARADC_1_ECDR171     SARADC_1.ECDR[43].R           /* External Channel Data Register */
#define SARADC_1_ECDR172     SARADC_1.ECDR[44].R           /* External Channel Data Register */
#define SARADC_1_ECDR173     SARADC_1.ECDR[45].R           /* External Channel Data Register */
#define SARADC_1_ECDR174     SARADC_1.ECDR[46].R           /* External Channel Data Register */
#define SARADC_1_ECDR175     SARADC_1.ECDR[47].R           /* External Channel Data Register */
#define SARADC_1_ECDR176     SARADC_1.ECDR[48].R           /* External Channel Data Register */
#define SARADC_1_ECDR177     SARADC_1.ECDR[49].R           /* External Channel Data Register */
#define SARADC_1_ECDR178     SARADC_1.ECDR[50].R           /* External Channel Data Register */
#define SARADC_1_ECDR179     SARADC_1.ECDR[51].R           /* External Channel Data Register */
#define SARADC_1_ECDR180     SARADC_1.ECDR[52].R           /* External Channel Data Register */
#define SARADC_1_ECDR181     SARADC_1.ECDR[53].R           /* External Channel Data Register */
#define SARADC_1_ECDR182     SARADC_1.ECDR[54].R           /* External Channel Data Register */
#define SARADC_1_ECDR183     SARADC_1.ECDR[55].R           /* External Channel Data Register */
#define SARADC_1_ECDR184     SARADC_1.ECDR[56].R           /* External Channel Data Register */
#define SARADC_1_ECDR185     SARADC_1.ECDR[57].R           /* External Channel Data Register */
#define SARADC_1_ECDR186     SARADC_1.ECDR[58].R           /* External Channel Data Register */
#define SARADC_1_ECDR187     SARADC_1.ECDR[59].R           /* External Channel Data Register */
#define SARADC_1_ECDR188     SARADC_1.ECDR[60].R           /* External Channel Data Register */
#define SARADC_1_ECDR189     SARADC_1.ECDR[61].R           /* External Channel Data Register */
#define SARADC_1_ECDR190     SARADC_1.ECDR[62].R           /* External Channel Data Register */
#define SARADC_1_ECDR191     SARADC_1.ECDR[63].R           /* External Channel Data Register */
#define SARADC_1_ECDR192     SARADC_1.ECDR[64].R           /* External Channel Data Register */
#define SARADC_1_ECDR193     SARADC_1.ECDR[65].R           /* External Channel Data Register */
#define SARADC_1_ECDR194     SARADC_1.ECDR[66].R           /* External Channel Data Register */
#define SARADC_1_ECDR195     SARADC_1.ECDR[67].R           /* External Channel Data Register */
#define SARADC_1_ECDR196     SARADC_1.ECDR[68].R           /* External Channel Data Register */
#define SARADC_1_ECDR197     SARADC_1.ECDR[69].R           /* External Channel Data Register */
#define SARADC_1_ECDR198     SARADC_1.ECDR[70].R           /* External Channel Data Register */
#define SARADC_1_ECDR199     SARADC_1.ECDR[71].R           /* External Channel Data Register */
#define SARADC_1_ECDR200     SARADC_1.ECDR[72].R           /* External Channel Data Register */
#define SARADC_1_ECDR201     SARADC_1.ECDR[73].R           /* External Channel Data Register */
#define SARADC_1_ECDR202     SARADC_1.ECDR[74].R           /* External Channel Data Register */
#define SARADC_1_ECDR203     SARADC_1.ECDR[75].R           /* External Channel Data Register */
#define SARADC_1_ECDR204     SARADC_1.ECDR[76].R           /* External Channel Data Register */
#define SARADC_1_ECDR205     SARADC_1.ECDR[77].R           /* External Channel Data Register */
#define SARADC_1_ECDR206     SARADC_1.ECDR[78].R           /* External Channel Data Register */
#define SARADC_1_ECDR207     SARADC_1.ECDR[79].R           /* External Channel Data Register */
#define SARADC_1_ECDR208     SARADC_1.ECDR[80].R           /* External Channel Data Register */
#define SARADC_1_ECDR209     SARADC_1.ECDR[81].R           /* External Channel Data Register */
#define SARADC_1_ECDR210     SARADC_1.ECDR[82].R           /* External Channel Data Register */
#define SARADC_1_ECDR211     SARADC_1.ECDR[83].R           /* External Channel Data Register */
#define SARADC_1_ECDR212     SARADC_1.ECDR[84].R           /* External Channel Data Register */
#define SARADC_1_ECDR213     SARADC_1.ECDR[85].R           /* External Channel Data Register */
#define SARADC_1_ECDR214     SARADC_1.ECDR[86].R           /* External Channel Data Register */
#define SARADC_1_ECDR215     SARADC_1.ECDR[87].R           /* External Channel Data Register */
#define SARADC_1_ECDR216     SARADC_1.ECDR[88].R           /* External Channel Data Register */
#define SARADC_1_ECDR217     SARADC_1.ECDR[89].R           /* External Channel Data Register */
#define SARADC_1_ECDR218     SARADC_1.ECDR[90].R           /* External Channel Data Register */
#define SARADC_1_ECDR219     SARADC_1.ECDR[91].R           /* External Channel Data Register */
#define SARADC_1_ECDR220     SARADC_1.ECDR[92].R           /* External Channel Data Register */
#define SARADC_1_ECDR221     SARADC_1.ECDR[93].R           /* External Channel Data Register */
#define SARADC_1_ECDR222     SARADC_1.ECDR[94].R           /* External Channel Data Register */
#define SARADC_1_ECDR223     SARADC_1.ECDR[95].R           /* External Channel Data Register */
#define SARADC_1_ECDR224     SARADC_1.ECDR[96].R           /* External Channel Data Register */
#define SARADC_1_ECDR225     SARADC_1.ECDR[97].R           /* External Channel Data Register */
#define SARADC_1_ECDR226     SARADC_1.ECDR[98].R           /* External Channel Data Register */
#define SARADC_1_ECDR227     SARADC_1.ECDR[99].R           /* External Channel Data Register */
#define SARADC_1_ECDR228     SARADC_1.ECDR[100].R          /* External Channel Data Register */
#define SARADC_1_ECDR229     SARADC_1.ECDR[101].R          /* External Channel Data Register */
#define SARADC_1_ECDR230     SARADC_1.ECDR[102].R          /* External Channel Data Register */
#define SARADC_1_ECDR231     SARADC_1.ECDR[103].R          /* External Channel Data Register */
#define SARADC_1_ECDR232     SARADC_1.ECDR[104].R          /* External Channel Data Register */
#define SARADC_1_ECDR233     SARADC_1.ECDR[105].R          /* External Channel Data Register */
#define SARADC_1_ECDR234     SARADC_1.ECDR[106].R          /* External Channel Data Register */
#define SARADC_1_ECDR235     SARADC_1.ECDR[107].R          /* External Channel Data Register */
#define SARADC_1_ECDR236     SARADC_1.ECDR[108].R          /* External Channel Data Register */
#define SARADC_1_ECDR237     SARADC_1.ECDR[109].R          /* External Channel Data Register */
#define SARADC_1_ECDR238     SARADC_1.ECDR[110].R          /* External Channel Data Register */
#define SARADC_1_ECDR239     SARADC_1.ECDR[111].R          /* External Channel Data Register */
#define SARADC_1_ECDR240     SARADC_1.ECDR[112].R          /* External Channel Data Register */
#define SARADC_1_ECDR241     SARADC_1.ECDR[113].R          /* External Channel Data Register */
#define SARADC_1_ECDR242     SARADC_1.ECDR[114].R          /* External Channel Data Register */
#define SARADC_1_ECDR243     SARADC_1.ECDR[115].R          /* External Channel Data Register */
#define SARADC_1_ECDR244     SARADC_1.ECDR[116].R          /* External Channel Data Register */
#define SARADC_1_ECDR245     SARADC_1.ECDR[117].R          /* External Channel Data Register */
#define SARADC_1_ECDR246     SARADC_1.ECDR[118].R          /* External Channel Data Register */
#define SARADC_1_ECDR247     SARADC_1.ECDR[119].R          /* External Channel Data Register */
#define SARADC_1_ECDR248     SARADC_1.ECDR[120].R          /* External Channel Data Register */
#define SARADC_1_ECDR249     SARADC_1.ECDR[121].R          /* External Channel Data Register */
#define SARADC_1_ECDR250     SARADC_1.ECDR[122].R          /* External Channel Data Register */
#define SARADC_1_ECDR251     SARADC_1.ECDR[123].R          /* External Channel Data Register */
#define SARADC_1_ECDR252     SARADC_1.ECDR[124].R          /* External Channel Data Register */
#define SARADC_1_ECDR253     SARADC_1.ECDR[125].R          /* External Channel Data Register */
#define SARADC_1_ECDR254     SARADC_1.ECDR[126].R          /* External Channel Data Register */
#define SARADC_1_ECDR255     SARADC_1.ECDR[127].R          /* External Channel Data Register */

/* SARADC */
#define SARADC_10_MCR        SARADC_10.MCR.R               /* Main Configuration Register */
#define SARADC_10_MSR        SARADC_10.MSR.R               /* Main Status Register */
#define SARADC_10_ISR        SARADC_10.ISR.R               /* Interrupt Status Register */
#define SARADC_10_ICIPR0     SARADC_10.ICIPR[0].R          /* Internal channel Interrupt Pending Register */
#define SARADC_10_ICIPR1     SARADC_10.ICIPR[1].R          /* Internal channel Interrupt Pending Register */
#define SARADC_10_ICIPR2     SARADC_10.ICIPR[2].R          /* Internal channel Interrupt Pending Register */
#define SARADC_10_IMR        SARADC_10.IMR.R               /* Interrupt Mask Register */
#define SARADC_10_ICIMR0     SARADC_10.ICIMR[0].R          /* Internal Channel Interrupt Mask Register */
#define SARADC_10_ICIMR1     SARADC_10.ICIMR[1].R          /* Internal Channel Interrupt Mask Register */
#define SARADC_10_ICIMR2     SARADC_10.ICIMR[2].R          /* Internal Channel Interrupt Mask Register */
#define SARADC_10_WTISR      SARADC_10.WTISR.R             /* Watchdog Threshold Interrupt Status Register */
#define SARADC_10_WTIMR      SARADC_10.WTIMR.R             /* Watchdog Threshold Interrupt Mask Register */
#define SARADC_10_DMAE       SARADC_10.DMAE.R              /* DMA Enable Register */
#define SARADC_10_ICDSR0     SARADC_10.ICDSR[0].R          /* Internal Channel DMA Select Register */
#define SARADC_10_ICDSR1     SARADC_10.ICDSR[1].R          /* Internal Channel DMA Select Register */
#define SARADC_10_ICDSR2     SARADC_10.ICDSR[2].R          /* Internal Channel DMA Select Register */
#define SARADC_10_WTHRHLR0   SARADC_10.WTHRHLR[0].R        /* Watchdog Threshold Register */
#define SARADC_10_WTHRHLR1   SARADC_10.WTHRHLR[1].R        /* Watchdog Threshold Register */
#define SARADC_10_WTHRHLR2   SARADC_10.WTHRHLR[2].R        /* Watchdog Threshold Register */
#define SARADC_10_WTHRHLR3   SARADC_10.WTHRHLR[3].R        /* Watchdog Threshold Register */
#define SARADC_10_CTR0       SARADC_10.CTR[0].R            /* Conversion Timing Register */
#define SARADC_10_CTR1       SARADC_10.CTR[1].R            /* Conversion Timing Register */
#define SARADC_10_CTR2       SARADC_10.CTR[2].R            /* Conversion Timing Register */
#define SARADC_10_CTR3       SARADC_10.CTR[3].R            /* Conversion Timing Register */
#define SARADC_10_ICNCMR0    SARADC_10.ICNCMR[0].R         /* Internal Channel Normal Conversion Mask Register */
#define SARADC_10_ICNCMR1    SARADC_10.ICNCMR[1].R         /* Internal Channel Normal Conversion Mask Register */
#define SARADC_10_ICNCMR2    SARADC_10.ICNCMR[2].R         /* Internal Channel Normal Conversion Mask Register */
#define SARADC_10_ICJCMR0    SARADC_10.ICJCMR[0].R         /* Internal Channel Injected Conversion Mask Register */
#define SARADC_10_ICJCMR1    SARADC_10.ICJCMR[1].R         /* Internal Channel Injected Conversion Mask Register */
#define SARADC_10_ICJCMR2    SARADC_10.ICJCMR[2].R         /* Internal Channel Injected Conversion Mask Register */
#define SARADC_10_PDEDR      SARADC_10.PDEDR.R             /* Power Down Exit Delay Register */
#define SARADC_10_ICDR0      SARADC_10.ICDR[0].R           /* Internal Channel Data Register */
#define SARADC_10_ICDR1      SARADC_10.ICDR[1].R           /* Internal Channel Data Register */
#define SARADC_10_ICDR2      SARADC_10.ICDR[2].R           /* Internal Channel Data Register */
#define SARADC_10_ICDR3      SARADC_10.ICDR[3].R           /* Internal Channel Data Register */
#define SARADC_10_ICDR4      SARADC_10.ICDR[4].R           /* Internal Channel Data Register */
#define SARADC_10_ICDR5      SARADC_10.ICDR[5].R           /* Internal Channel Data Register */
#define SARADC_10_ICDR6      SARADC_10.ICDR[6].R           /* Internal Channel Data Register */
#define SARADC_10_ICDR7      SARADC_10.ICDR[7].R           /* Internal Channel Data Register */
#define SARADC_10_ICDR8      SARADC_10.ICDR[8].R           /* Internal Channel Data Register */
#define SARADC_10_ICDR9      SARADC_10.ICDR[9].R           /* Internal Channel Data Register */
#define SARADC_10_ICDR10     SARADC_10.ICDR[10].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR11     SARADC_10.ICDR[11].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR12     SARADC_10.ICDR[12].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR13     SARADC_10.ICDR[13].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR14     SARADC_10.ICDR[14].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR15     SARADC_10.ICDR[15].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR16     SARADC_10.ICDR[16].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR17     SARADC_10.ICDR[17].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR18     SARADC_10.ICDR[18].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR19     SARADC_10.ICDR[19].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR20     SARADC_10.ICDR[20].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR21     SARADC_10.ICDR[21].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR22     SARADC_10.ICDR[22].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR23     SARADC_10.ICDR[23].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR24     SARADC_10.ICDR[24].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR25     SARADC_10.ICDR[25].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR26     SARADC_10.ICDR[26].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR27     SARADC_10.ICDR[27].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR28     SARADC_10.ICDR[28].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR29     SARADC_10.ICDR[29].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR30     SARADC_10.ICDR[30].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR31     SARADC_10.ICDR[31].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR32     SARADC_10.ICDR[32].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR33     SARADC_10.ICDR[33].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR34     SARADC_10.ICDR[34].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR35     SARADC_10.ICDR[35].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR36     SARADC_10.ICDR[36].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR37     SARADC_10.ICDR[37].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR38     SARADC_10.ICDR[38].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR39     SARADC_10.ICDR[39].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR40     SARADC_10.ICDR[40].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR41     SARADC_10.ICDR[41].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR42     SARADC_10.ICDR[42].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR43     SARADC_10.ICDR[43].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR44     SARADC_10.ICDR[44].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR45     SARADC_10.ICDR[45].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR46     SARADC_10.ICDR[46].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR47     SARADC_10.ICDR[47].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR48     SARADC_10.ICDR[48].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR49     SARADC_10.ICDR[49].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR50     SARADC_10.ICDR[50].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR51     SARADC_10.ICDR[51].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR52     SARADC_10.ICDR[52].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR53     SARADC_10.ICDR[53].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR54     SARADC_10.ICDR[54].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR55     SARADC_10.ICDR[55].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR56     SARADC_10.ICDR[56].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR57     SARADC_10.ICDR[57].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR58     SARADC_10.ICDR[58].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR59     SARADC_10.ICDR[59].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR60     SARADC_10.ICDR[60].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR61     SARADC_10.ICDR[61].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR62     SARADC_10.ICDR[62].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR63     SARADC_10.ICDR[63].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR64     SARADC_10.ICDR[64].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR65     SARADC_10.ICDR[65].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR66     SARADC_10.ICDR[66].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR67     SARADC_10.ICDR[67].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR68     SARADC_10.ICDR[68].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR69     SARADC_10.ICDR[69].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR70     SARADC_10.ICDR[70].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR71     SARADC_10.ICDR[71].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR72     SARADC_10.ICDR[72].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR73     SARADC_10.ICDR[73].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR74     SARADC_10.ICDR[74].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR75     SARADC_10.ICDR[75].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR76     SARADC_10.ICDR[76].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR77     SARADC_10.ICDR[77].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR78     SARADC_10.ICDR[78].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR79     SARADC_10.ICDR[79].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR80     SARADC_10.ICDR[80].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR81     SARADC_10.ICDR[81].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR82     SARADC_10.ICDR[82].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR83     SARADC_10.ICDR[83].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR84     SARADC_10.ICDR[84].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR85     SARADC_10.ICDR[85].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR86     SARADC_10.ICDR[86].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR87     SARADC_10.ICDR[87].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR88     SARADC_10.ICDR[88].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR89     SARADC_10.ICDR[89].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR90     SARADC_10.ICDR[90].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR91     SARADC_10.ICDR[91].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR92     SARADC_10.ICDR[92].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR93     SARADC_10.ICDR[93].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR94     SARADC_10.ICDR[94].R          /* Internal Channel Data Register */
#define SARADC_10_ICDR95     SARADC_10.ICDR[95].R          /* Internal Channel Data Register */
#define SARADC_10_ICWSELR0   SARADC_10.ICWSELR[0].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_10_ICWSELR1   SARADC_10.ICWSELR[1].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_10_ICWSELR2   SARADC_10.ICWSELR[2].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_10_ICWSELR3   SARADC_10.ICWSELR[3].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_10_ICWSELR4   SARADC_10.ICWSELR[4].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_10_ICWSELR5   SARADC_10.ICWSELR[5].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_10_ICWSELR6   SARADC_10.ICWSELR[6].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_10_ICWSELR7   SARADC_10.ICWSELR[7].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_10_ICWSELR8   SARADC_10.ICWSELR[8].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_10_ICWSELR9   SARADC_10.ICWSELR[9].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_10_ICWSELR10  SARADC_10.ICWSELR[10].R       /* Internal Channel Watchdog Selection Register */
#define SARADC_10_ICWSELR11  SARADC_10.ICWSELR[11].R       /* Internal Channel Watchdog Selection Register */
#define SARADC_10_ICWENR0    SARADC_10.ICWENR[0].R         /* Internal Channel Watchdog Enable Register */
#define SARADC_10_ICWENR1    SARADC_10.ICWENR[1].R         /* Internal Channel Watchdog Enable Register */
#define SARADC_10_ICWENR2    SARADC_10.ICWENR[2].R         /* Internal Channel Watchdog Enable Register */
#define SARADC_10_ICAWORR0   SARADC_10.ICAWORR[0].R        /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_10_ICAWORR1   SARADC_10.ICAWORR[1].R        /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_10_ICAWORR2   SARADC_10.ICAWORR[2].R        /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_10_TCIPR      SARADC_10.TCIPR.R             /* Test Channel Interrupt Pending Register */
#define SARADC_10_TCIMR      SARADC_10.TCIMR.R             /* Test Channel Interrupt Mask Register */
#define SARADC_10_TCDSR      SARADC_10.TCDSR.R             /* Test Channel DMA Select Register */
#define SARADC_10_TCNCMR     SARADC_10.TCNCMR.R            /* Test Channel Normal Conversion Mask Register */
#define SARADC_10_TCJCMR     SARADC_10.TCJCMR.R            /* Test Channel Injected Conversion Mask Register */
#define SARADC_10_TCWSELR0   SARADC_10.TCWSELR[0].R        /* Test Channel Watchdog Selection Register */
#define SARADC_10_TCWSELR1   SARADC_10.TCWSELR[1].R        /* Test Channel Watchdog Selection Register */
#define SARADC_10_TCWSELR2   SARADC_10.TCWSELR[2].R        /* Test Channel Watchdog Selection Register */
#define SARADC_10_TCWSELR3   SARADC_10.TCWSELR[3].R        /* Test Channel Watchdog Selection Register */
#define SARADC_10_TCWENR     SARADC_10.TCWENR.R            /* Test Channel Watchdog Enable Register */
#define SARADC_10_TCAWORR    SARADC_10.TCAWORR.R           /* Test Channel Analog Watchdog Out of Range Register */
#define SARADC_10_TCCAPR0    SARADC_10.TCCAPR[0].R         /* Test Channel Connection with Analog Pin Register */
#define SARADC_10_TCCAPR1    SARADC_10.TCCAPR[1].R         /* Test Channel Connection with Analog Pin Register */
#define SARADC_10_TCCAPR2    SARADC_10.TCCAPR[2].R         /* Test Channel Connection with Analog Pin Register */
#define SARADC_10_TCCAPR3    SARADC_10.TCCAPR[3].R         /* Test Channel Connection with Analog Pin Register */
#define SARADC_10_TCCAPR4    SARADC_10.TCCAPR[4].R         /* Test Channel Connection with Analog Pin Register */
#define SARADC_10_TCCAPR5    SARADC_10.TCCAPR[5].R         /* Test Channel Connection with Analog Pin Register */
#define SARADC_10_TCCAPR6    SARADC_10.TCCAPR[6].R         /* Test Channel Connection with Analog Pin Register */
#define SARADC_10_TCCAPR7    SARADC_10.TCCAPR[7].R         /* Test Channel Connection with Analog Pin Register */
#define SARADC_10_TCDR96     SARADC_10.TCDR[0].R           /* Test Channel Data Register */
#define SARADC_10_TCDR97     SARADC_10.TCDR[1].R           /* Test Channel Data Register */
#define SARADC_10_TCDR98     SARADC_10.TCDR[2].R           /* Test Channel Data Register */
#define SARADC_10_TCDR99     SARADC_10.TCDR[3].R           /* Test Channel Data Register */
#define SARADC_10_TCDR100    SARADC_10.TCDR[4].R           /* Test Channel Data Register */
#define SARADC_10_TCDR101    SARADC_10.TCDR[5].R           /* Test Channel Data Register */
#define SARADC_10_TCDR102    SARADC_10.TCDR[6].R           /* Test Channel Data Register */
#define SARADC_10_TCDR103    SARADC_10.TCDR[7].R           /* Test Channel Data Register */
#define SARADC_10_TCDR104    SARADC_10.TCDR[8].R           /* Test Channel Data Register */
#define SARADC_10_TCDR105    SARADC_10.TCDR[9].R           /* Test Channel Data Register */
#define SARADC_10_TCDR106    SARADC_10.TCDR[10].R          /* Test Channel Data Register */
#define SARADC_10_TCDR107    SARADC_10.TCDR[11].R          /* Test Channel Data Register */
#define SARADC_10_TCDR108    SARADC_10.TCDR[12].R          /* Test Channel Data Register */
#define SARADC_10_TCDR109    SARADC_10.TCDR[13].R          /* Test Channel Data Register */
#define SARADC_10_TCDR110    SARADC_10.TCDR[14].R          /* Test Channel Data Register */
#define SARADC_10_TCDR111    SARADC_10.TCDR[15].R          /* Test Channel Data Register */
#define SARADC_10_TCDR112    SARADC_10.TCDR[16].R          /* Test Channel Data Register */
#define SARADC_10_TCDR113    SARADC_10.TCDR[17].R          /* Test Channel Data Register */
#define SARADC_10_TCDR114    SARADC_10.TCDR[18].R          /* Test Channel Data Register */
#define SARADC_10_TCDR115    SARADC_10.TCDR[19].R          /* Test Channel Data Register */
#define SARADC_10_TCDR116    SARADC_10.TCDR[20].R          /* Test Channel Data Register */
#define SARADC_10_TCDR117    SARADC_10.TCDR[21].R          /* Test Channel Data Register */
#define SARADC_10_TCDR118    SARADC_10.TCDR[22].R          /* Test Channel Data Register */
#define SARADC_10_TCDR119    SARADC_10.TCDR[23].R          /* Test Channel Data Register */
#define SARADC_10_TCDR120    SARADC_10.TCDR[24].R          /* Test Channel Data Register */
#define SARADC_10_TCDR121    SARADC_10.TCDR[25].R          /* Test Channel Data Register */
#define SARADC_10_TCDR122    SARADC_10.TCDR[26].R          /* Test Channel Data Register */
#define SARADC_10_TCDR123    SARADC_10.TCDR[27].R          /* Test Channel Data Register */
#define SARADC_10_TCDR124    SARADC_10.TCDR[28].R          /* Test Channel Data Register */
#define SARADC_10_TCDR125    SARADC_10.TCDR[29].R          /* Test Channel Data Register */
#define SARADC_10_TCDR126    SARADC_10.TCDR[30].R          /* Test Channel Data Register */
#define SARADC_10_TCDR127    SARADC_10.TCDR[31].R          /* Test Channel Data Register */
#define SARADC_10_ECDSDR     SARADC_10.ECDSDR.R            /* External Channel Decode Signals Delay Register */
#define SARADC_10_ECIPR0     SARADC_10.ECIPR[0].R          /* External Channel Interrupt Pending Register */
#define SARADC_10_ECIPR1     SARADC_10.ECIPR[1].R          /* External Channel Interrupt Pending Register */
#define SARADC_10_ECIPR2     SARADC_10.ECIPR[2].R          /* External Channel Interrupt Pending Register */
#define SARADC_10_ECIPR3     SARADC_10.ECIPR[3].R          /* External Channel Interrupt Pending Register */
#define SARADC_10_ECIMR0     SARADC_10.ECIMR[0].R          /* External Channel Interrupt Mask Register */
#define SARADC_10_ECIMR1     SARADC_10.ECIMR[1].R          /* External Channel Interrupt Mask Register */
#define SARADC_10_ECIMR2     SARADC_10.ECIMR[2].R          /* External Channel Interrupt Mask Register */
#define SARADC_10_ECIMR3     SARADC_10.ECIMR[3].R          /* External Channel Interrupt Mask Register */
#define SARADC_10_ECDSR0     SARADC_10.ECDSR[0].R          /* External Channel DMA Select Register */
#define SARADC_10_ECDSR1     SARADC_10.ECDSR[1].R          /* External Channel DMA Select Register */
#define SARADC_10_ECDSR2     SARADC_10.ECDSR[2].R          /* External Channel DMA Select Register */
#define SARADC_10_ECDSR3     SARADC_10.ECDSR[3].R          /* External Channel DMA Select Register */
#define SARADC_10_ECNCMR0    SARADC_10.ECNCMR[0].R         /* External Channel Normal Conversion Mask Register */
#define SARADC_10_ECNCMR1    SARADC_10.ECNCMR[1].R         /* External Channel Normal Conversion Mask Register */
#define SARADC_10_ECNCMR2    SARADC_10.ECNCMR[2].R         /* External Channel Normal Conversion Mask Register */
#define SARADC_10_ECNCMR3    SARADC_10.ECNCMR[3].R         /* External Channel Normal Conversion Mask Register */
#define SARADC_10_ECJCMR0    SARADC_10.ECJCMR[0].R         /* External Channel Injected Conversion Mask Register */
#define SARADC_10_ECJCMR1    SARADC_10.ECJCMR[1].R         /* External Channel Injected Conversion Mask Register */
#define SARADC_10_ECJCMR2    SARADC_10.ECJCMR[2].R         /* External Channel Injected Conversion Mask Register */
#define SARADC_10_ECJCMR3    SARADC_10.ECJCMR[3].R         /* External Channel Injected Conversion Mask Register */
#define SARADC_10_ECWSELR0   SARADC_10.ECWSELR[0].R        /* External Channel Watchdog Selection Register */
#define SARADC_10_ECWSELR1   SARADC_10.ECWSELR[1].R        /* External Channel Watchdog Selection Register */
#define SARADC_10_ECWSELR2   SARADC_10.ECWSELR[2].R        /* External Channel Watchdog Selection Register */
#define SARADC_10_ECWSELR3   SARADC_10.ECWSELR[3].R        /* External Channel Watchdog Selection Register */
#define SARADC_10_ECWSELR4   SARADC_10.ECWSELR[4].R        /* External Channel Watchdog Selection Register */
#define SARADC_10_ECWSELR5   SARADC_10.ECWSELR[5].R        /* External Channel Watchdog Selection Register */
#define SARADC_10_ECWSELR6   SARADC_10.ECWSELR[6].R        /* External Channel Watchdog Selection Register */
#define SARADC_10_ECWSELR7   SARADC_10.ECWSELR[7].R        /* External Channel Watchdog Selection Register */
#define SARADC_10_ECWSELR8   SARADC_10.ECWSELR[8].R        /* External Channel Watchdog Selection Register */
#define SARADC_10_ECWSELR9   SARADC_10.ECWSELR[9].R        /* External Channel Watchdog Selection Register */
#define SARADC_10_ECWSELR10  SARADC_10.ECWSELR[10].R       /* External Channel Watchdog Selection Register */
#define SARADC_10_ECWSELR11  SARADC_10.ECWSELR[11].R       /* External Channel Watchdog Selection Register */
#define SARADC_10_ECWSELR12  SARADC_10.ECWSELR[12].R       /* External Channel Watchdog Selection Register */
#define SARADC_10_ECWSELR13  SARADC_10.ECWSELR[13].R       /* External Channel Watchdog Selection Register */
#define SARADC_10_ECWSELR14  SARADC_10.ECWSELR[14].R       /* External Channel Watchdog Selection Register */
#define SARADC_10_ECWSELR15  SARADC_10.ECWSELR[15].R       /* External Channel Watchdog Selection Register */
#define SARADC_10_ECWENR0    SARADC_10.ECWENR[0].R         /* External Channel Watchdog Enable Register */
#define SARADC_10_ECWENR1    SARADC_10.ECWENR[1].R         /* External Channel Watchdog Enable Register */
#define SARADC_10_ECWENR2    SARADC_10.ECWENR[2].R         /* External Channel Watchdog Enable Register */
#define SARADC_10_ECWENR3    SARADC_10.ECWENR[3].R         /* External Channel Watchdog Enable Register */
#define SARADC_10_ECAWORR0   SARADC_10.ECAWORR[0].R        /* External Channel Analog Watchdog Out of Range register */
#define SARADC_10_ECAWORR1   SARADC_10.ECAWORR[1].R        /* External Channel Analog Watchdog Out of Range register */
#define SARADC_10_ECAWORR2   SARADC_10.ECAWORR[2].R        /* External Channel Analog Watchdog Out of Range register */
#define SARADC_10_ECAWORR3   SARADC_10.ECAWORR[3].R        /* External Channel Analog Watchdog Out of Range register */
#define SARADC_10_ECMICR0    SARADC_10.ECMICR[0].R         /* External Channel Mapping to Internal Channel Register */
#define SARADC_10_ECMICR1    SARADC_10.ECMICR[1].R         /* External Channel Mapping to Internal Channel Register */
#define SARADC_10_ECMICR2    SARADC_10.ECMICR[2].R         /* External Channel Mapping to Internal Channel Register */
#define SARADC_10_ECMICR3    SARADC_10.ECMICR[3].R         /* External Channel Mapping to Internal Channel Register */
#define SARADC_10_ECDR128    SARADC_10.ECDR[0].R           /* External Channel Data Register */
#define SARADC_10_ECDR129    SARADC_10.ECDR[1].R           /* External Channel Data Register */
#define SARADC_10_ECDR130    SARADC_10.ECDR[2].R           /* External Channel Data Register */
#define SARADC_10_ECDR131    SARADC_10.ECDR[3].R           /* External Channel Data Register */
#define SARADC_10_ECDR132    SARADC_10.ECDR[4].R           /* External Channel Data Register */
#define SARADC_10_ECDR133    SARADC_10.ECDR[5].R           /* External Channel Data Register */
#define SARADC_10_ECDR134    SARADC_10.ECDR[6].R           /* External Channel Data Register */
#define SARADC_10_ECDR135    SARADC_10.ECDR[7].R           /* External Channel Data Register */
#define SARADC_10_ECDR136    SARADC_10.ECDR[8].R           /* External Channel Data Register */
#define SARADC_10_ECDR137    SARADC_10.ECDR[9].R           /* External Channel Data Register */
#define SARADC_10_ECDR138    SARADC_10.ECDR[10].R          /* External Channel Data Register */
#define SARADC_10_ECDR139    SARADC_10.ECDR[11].R          /* External Channel Data Register */
#define SARADC_10_ECDR140    SARADC_10.ECDR[12].R          /* External Channel Data Register */
#define SARADC_10_ECDR141    SARADC_10.ECDR[13].R          /* External Channel Data Register */
#define SARADC_10_ECDR142    SARADC_10.ECDR[14].R          /* External Channel Data Register */
#define SARADC_10_ECDR143    SARADC_10.ECDR[15].R          /* External Channel Data Register */
#define SARADC_10_ECDR144    SARADC_10.ECDR[16].R          /* External Channel Data Register */
#define SARADC_10_ECDR145    SARADC_10.ECDR[17].R          /* External Channel Data Register */
#define SARADC_10_ECDR146    SARADC_10.ECDR[18].R          /* External Channel Data Register */
#define SARADC_10_ECDR147    SARADC_10.ECDR[19].R          /* External Channel Data Register */
#define SARADC_10_ECDR148    SARADC_10.ECDR[20].R          /* External Channel Data Register */
#define SARADC_10_ECDR149    SARADC_10.ECDR[21].R          /* External Channel Data Register */
#define SARADC_10_ECDR150    SARADC_10.ECDR[22].R          /* External Channel Data Register */
#define SARADC_10_ECDR151    SARADC_10.ECDR[23].R          /* External Channel Data Register */
#define SARADC_10_ECDR152    SARADC_10.ECDR[24].R          /* External Channel Data Register */
#define SARADC_10_ECDR153    SARADC_10.ECDR[25].R          /* External Channel Data Register */
#define SARADC_10_ECDR154    SARADC_10.ECDR[26].R          /* External Channel Data Register */
#define SARADC_10_ECDR155    SARADC_10.ECDR[27].R          /* External Channel Data Register */
#define SARADC_10_ECDR156    SARADC_10.ECDR[28].R          /* External Channel Data Register */
#define SARADC_10_ECDR157    SARADC_10.ECDR[29].R          /* External Channel Data Register */
#define SARADC_10_ECDR158    SARADC_10.ECDR[30].R          /* External Channel Data Register */
#define SARADC_10_ECDR159    SARADC_10.ECDR[31].R          /* External Channel Data Register */
#define SARADC_10_ECDR160    SARADC_10.ECDR[32].R          /* External Channel Data Register */
#define SARADC_10_ECDR161    SARADC_10.ECDR[33].R          /* External Channel Data Register */
#define SARADC_10_ECDR162    SARADC_10.ECDR[34].R          /* External Channel Data Register */
#define SARADC_10_ECDR163    SARADC_10.ECDR[35].R          /* External Channel Data Register */
#define SARADC_10_ECDR164    SARADC_10.ECDR[36].R          /* External Channel Data Register */
#define SARADC_10_ECDR165    SARADC_10.ECDR[37].R          /* External Channel Data Register */
#define SARADC_10_ECDR166    SARADC_10.ECDR[38].R          /* External Channel Data Register */
#define SARADC_10_ECDR167    SARADC_10.ECDR[39].R          /* External Channel Data Register */
#define SARADC_10_ECDR168    SARADC_10.ECDR[40].R          /* External Channel Data Register */
#define SARADC_10_ECDR169    SARADC_10.ECDR[41].R          /* External Channel Data Register */
#define SARADC_10_ECDR170    SARADC_10.ECDR[42].R          /* External Channel Data Register */
#define SARADC_10_ECDR171    SARADC_10.ECDR[43].R          /* External Channel Data Register */
#define SARADC_10_ECDR172    SARADC_10.ECDR[44].R          /* External Channel Data Register */
#define SARADC_10_ECDR173    SARADC_10.ECDR[45].R          /* External Channel Data Register */
#define SARADC_10_ECDR174    SARADC_10.ECDR[46].R          /* External Channel Data Register */
#define SARADC_10_ECDR175    SARADC_10.ECDR[47].R          /* External Channel Data Register */
#define SARADC_10_ECDR176    SARADC_10.ECDR[48].R          /* External Channel Data Register */
#define SARADC_10_ECDR177    SARADC_10.ECDR[49].R          /* External Channel Data Register */
#define SARADC_10_ECDR178    SARADC_10.ECDR[50].R          /* External Channel Data Register */
#define SARADC_10_ECDR179    SARADC_10.ECDR[51].R          /* External Channel Data Register */
#define SARADC_10_ECDR180    SARADC_10.ECDR[52].R          /* External Channel Data Register */
#define SARADC_10_ECDR181    SARADC_10.ECDR[53].R          /* External Channel Data Register */
#define SARADC_10_ECDR182    SARADC_10.ECDR[54].R          /* External Channel Data Register */
#define SARADC_10_ECDR183    SARADC_10.ECDR[55].R          /* External Channel Data Register */
#define SARADC_10_ECDR184    SARADC_10.ECDR[56].R          /* External Channel Data Register */
#define SARADC_10_ECDR185    SARADC_10.ECDR[57].R          /* External Channel Data Register */
#define SARADC_10_ECDR186    SARADC_10.ECDR[58].R          /* External Channel Data Register */
#define SARADC_10_ECDR187    SARADC_10.ECDR[59].R          /* External Channel Data Register */
#define SARADC_10_ECDR188    SARADC_10.ECDR[60].R          /* External Channel Data Register */
#define SARADC_10_ECDR189    SARADC_10.ECDR[61].R          /* External Channel Data Register */
#define SARADC_10_ECDR190    SARADC_10.ECDR[62].R          /* External Channel Data Register */
#define SARADC_10_ECDR191    SARADC_10.ECDR[63].R          /* External Channel Data Register */
#define SARADC_10_ECDR192    SARADC_10.ECDR[64].R          /* External Channel Data Register */
#define SARADC_10_ECDR193    SARADC_10.ECDR[65].R          /* External Channel Data Register */
#define SARADC_10_ECDR194    SARADC_10.ECDR[66].R          /* External Channel Data Register */
#define SARADC_10_ECDR195    SARADC_10.ECDR[67].R          /* External Channel Data Register */
#define SARADC_10_ECDR196    SARADC_10.ECDR[68].R          /* External Channel Data Register */
#define SARADC_10_ECDR197    SARADC_10.ECDR[69].R          /* External Channel Data Register */
#define SARADC_10_ECDR198    SARADC_10.ECDR[70].R          /* External Channel Data Register */
#define SARADC_10_ECDR199    SARADC_10.ECDR[71].R          /* External Channel Data Register */
#define SARADC_10_ECDR200    SARADC_10.ECDR[72].R          /* External Channel Data Register */
#define SARADC_10_ECDR201    SARADC_10.ECDR[73].R          /* External Channel Data Register */
#define SARADC_10_ECDR202    SARADC_10.ECDR[74].R          /* External Channel Data Register */
#define SARADC_10_ECDR203    SARADC_10.ECDR[75].R          /* External Channel Data Register */
#define SARADC_10_ECDR204    SARADC_10.ECDR[76].R          /* External Channel Data Register */
#define SARADC_10_ECDR205    SARADC_10.ECDR[77].R          /* External Channel Data Register */
#define SARADC_10_ECDR206    SARADC_10.ECDR[78].R          /* External Channel Data Register */
#define SARADC_10_ECDR207    SARADC_10.ECDR[79].R          /* External Channel Data Register */
#define SARADC_10_ECDR208    SARADC_10.ECDR[80].R          /* External Channel Data Register */
#define SARADC_10_ECDR209    SARADC_10.ECDR[81].R          /* External Channel Data Register */
#define SARADC_10_ECDR210    SARADC_10.ECDR[82].R          /* External Channel Data Register */
#define SARADC_10_ECDR211    SARADC_10.ECDR[83].R          /* External Channel Data Register */
#define SARADC_10_ECDR212    SARADC_10.ECDR[84].R          /* External Channel Data Register */
#define SARADC_10_ECDR213    SARADC_10.ECDR[85].R          /* External Channel Data Register */
#define SARADC_10_ECDR214    SARADC_10.ECDR[86].R          /* External Channel Data Register */
#define SARADC_10_ECDR215    SARADC_10.ECDR[87].R          /* External Channel Data Register */
#define SARADC_10_ECDR216    SARADC_10.ECDR[88].R          /* External Channel Data Register */
#define SARADC_10_ECDR217    SARADC_10.ECDR[89].R          /* External Channel Data Register */
#define SARADC_10_ECDR218    SARADC_10.ECDR[90].R          /* External Channel Data Register */
#define SARADC_10_ECDR219    SARADC_10.ECDR[91].R          /* External Channel Data Register */
#define SARADC_10_ECDR220    SARADC_10.ECDR[92].R          /* External Channel Data Register */
#define SARADC_10_ECDR221    SARADC_10.ECDR[93].R          /* External Channel Data Register */
#define SARADC_10_ECDR222    SARADC_10.ECDR[94].R          /* External Channel Data Register */
#define SARADC_10_ECDR223    SARADC_10.ECDR[95].R          /* External Channel Data Register */
#define SARADC_10_ECDR224    SARADC_10.ECDR[96].R          /* External Channel Data Register */
#define SARADC_10_ECDR225    SARADC_10.ECDR[97].R          /* External Channel Data Register */
#define SARADC_10_ECDR226    SARADC_10.ECDR[98].R          /* External Channel Data Register */
#define SARADC_10_ECDR227    SARADC_10.ECDR[99].R          /* External Channel Data Register */
#define SARADC_10_ECDR228    SARADC_10.ECDR[100].R         /* External Channel Data Register */
#define SARADC_10_ECDR229    SARADC_10.ECDR[101].R         /* External Channel Data Register */
#define SARADC_10_ECDR230    SARADC_10.ECDR[102].R         /* External Channel Data Register */
#define SARADC_10_ECDR231    SARADC_10.ECDR[103].R         /* External Channel Data Register */
#define SARADC_10_ECDR232    SARADC_10.ECDR[104].R         /* External Channel Data Register */
#define SARADC_10_ECDR233    SARADC_10.ECDR[105].R         /* External Channel Data Register */
#define SARADC_10_ECDR234    SARADC_10.ECDR[106].R         /* External Channel Data Register */
#define SARADC_10_ECDR235    SARADC_10.ECDR[107].R         /* External Channel Data Register */
#define SARADC_10_ECDR236    SARADC_10.ECDR[108].R         /* External Channel Data Register */
#define SARADC_10_ECDR237    SARADC_10.ECDR[109].R         /* External Channel Data Register */
#define SARADC_10_ECDR238    SARADC_10.ECDR[110].R         /* External Channel Data Register */
#define SARADC_10_ECDR239    SARADC_10.ECDR[111].R         /* External Channel Data Register */
#define SARADC_10_ECDR240    SARADC_10.ECDR[112].R         /* External Channel Data Register */
#define SARADC_10_ECDR241    SARADC_10.ECDR[113].R         /* External Channel Data Register */
#define SARADC_10_ECDR242    SARADC_10.ECDR[114].R         /* External Channel Data Register */
#define SARADC_10_ECDR243    SARADC_10.ECDR[115].R         /* External Channel Data Register */
#define SARADC_10_ECDR244    SARADC_10.ECDR[116].R         /* External Channel Data Register */
#define SARADC_10_ECDR245    SARADC_10.ECDR[117].R         /* External Channel Data Register */
#define SARADC_10_ECDR246    SARADC_10.ECDR[118].R         /* External Channel Data Register */
#define SARADC_10_ECDR247    SARADC_10.ECDR[119].R         /* External Channel Data Register */
#define SARADC_10_ECDR248    SARADC_10.ECDR[120].R         /* External Channel Data Register */
#define SARADC_10_ECDR249    SARADC_10.ECDR[121].R         /* External Channel Data Register */
#define SARADC_10_ECDR250    SARADC_10.ECDR[122].R         /* External Channel Data Register */
#define SARADC_10_ECDR251    SARADC_10.ECDR[123].R         /* External Channel Data Register */
#define SARADC_10_ECDR252    SARADC_10.ECDR[124].R         /* External Channel Data Register */
#define SARADC_10_ECDR253    SARADC_10.ECDR[125].R         /* External Channel Data Register */
#define SARADC_10_ECDR254    SARADC_10.ECDR[126].R         /* External Channel Data Register */
#define SARADC_10_ECDR255    SARADC_10.ECDR[127].R         /* External Channel Data Register */

/* SARADC */
#define SARADC_2_MCR         SARADC_2.MCR.R                /* Main Configuration Register */
#define SARADC_2_MSR         SARADC_2.MSR.R                /* Main Status Register */
#define SARADC_2_ISR         SARADC_2.ISR.R                /* Interrupt Status Register */
#define SARADC_2_ICIPR0      SARADC_2.ICIPR[0].R           /* Internal channel Interrupt Pending Register */
#define SARADC_2_ICIPR1      SARADC_2.ICIPR[1].R           /* Internal channel Interrupt Pending Register */
#define SARADC_2_ICIPR2      SARADC_2.ICIPR[2].R           /* Internal channel Interrupt Pending Register */
#define SARADC_2_IMR         SARADC_2.IMR.R                /* Interrupt Mask Register */
#define SARADC_2_ICIMR0      SARADC_2.ICIMR[0].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_2_ICIMR1      SARADC_2.ICIMR[1].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_2_ICIMR2      SARADC_2.ICIMR[2].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_2_WTISR       SARADC_2.WTISR.R              /* Watchdog Threshold Interrupt Status Register */
#define SARADC_2_WTIMR       SARADC_2.WTIMR.R              /* Watchdog Threshold Interrupt Mask Register */
#define SARADC_2_DMAE        SARADC_2.DMAE.R               /* DMA Enable Register */
#define SARADC_2_ICDSR0      SARADC_2.ICDSR[0].R           /* Internal Channel DMA Select Register */
#define SARADC_2_ICDSR1      SARADC_2.ICDSR[1].R           /* Internal Channel DMA Select Register */
#define SARADC_2_ICDSR2      SARADC_2.ICDSR[2].R           /* Internal Channel DMA Select Register */
#define SARADC_2_WTHRHLR0    SARADC_2.WTHRHLR[0].R         /* Watchdog Threshold Register */
#define SARADC_2_WTHRHLR1    SARADC_2.WTHRHLR[1].R         /* Watchdog Threshold Register */
#define SARADC_2_WTHRHLR2    SARADC_2.WTHRHLR[2].R         /* Watchdog Threshold Register */
#define SARADC_2_WTHRHLR3    SARADC_2.WTHRHLR[3].R         /* Watchdog Threshold Register */
#define SARADC_2_CTR0        SARADC_2.CTR[0].R             /* Conversion Timing Register */
#define SARADC_2_CTR1        SARADC_2.CTR[1].R             /* Conversion Timing Register */
#define SARADC_2_CTR2        SARADC_2.CTR[2].R             /* Conversion Timing Register */
#define SARADC_2_CTR3        SARADC_2.CTR[3].R             /* Conversion Timing Register */
#define SARADC_2_ICNCMR0     SARADC_2.ICNCMR[0].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_2_ICNCMR1     SARADC_2.ICNCMR[1].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_2_ICNCMR2     SARADC_2.ICNCMR[2].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_2_ICJCMR0     SARADC_2.ICJCMR[0].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_2_ICJCMR1     SARADC_2.ICJCMR[1].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_2_ICJCMR2     SARADC_2.ICJCMR[2].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_2_PDEDR       SARADC_2.PDEDR.R              /* Power Down Exit Delay Register */
#define SARADC_2_ICDR0       SARADC_2.ICDR[0].R            /* Internal Channel Data Register */
#define SARADC_2_ICDR1       SARADC_2.ICDR[1].R            /* Internal Channel Data Register */
#define SARADC_2_ICDR2       SARADC_2.ICDR[2].R            /* Internal Channel Data Register */
#define SARADC_2_ICDR3       SARADC_2.ICDR[3].R            /* Internal Channel Data Register */
#define SARADC_2_ICDR4       SARADC_2.ICDR[4].R            /* Internal Channel Data Register */
#define SARADC_2_ICDR5       SARADC_2.ICDR[5].R            /* Internal Channel Data Register */
#define SARADC_2_ICDR6       SARADC_2.ICDR[6].R            /* Internal Channel Data Register */
#define SARADC_2_ICDR7       SARADC_2.ICDR[7].R            /* Internal Channel Data Register */
#define SARADC_2_ICDR8       SARADC_2.ICDR[8].R            /* Internal Channel Data Register */
#define SARADC_2_ICDR9       SARADC_2.ICDR[9].R            /* Internal Channel Data Register */
#define SARADC_2_ICDR10      SARADC_2.ICDR[10].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR11      SARADC_2.ICDR[11].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR12      SARADC_2.ICDR[12].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR13      SARADC_2.ICDR[13].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR14      SARADC_2.ICDR[14].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR15      SARADC_2.ICDR[15].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR16      SARADC_2.ICDR[16].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR17      SARADC_2.ICDR[17].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR18      SARADC_2.ICDR[18].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR19      SARADC_2.ICDR[19].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR20      SARADC_2.ICDR[20].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR21      SARADC_2.ICDR[21].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR22      SARADC_2.ICDR[22].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR23      SARADC_2.ICDR[23].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR24      SARADC_2.ICDR[24].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR25      SARADC_2.ICDR[25].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR26      SARADC_2.ICDR[26].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR27      SARADC_2.ICDR[27].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR28      SARADC_2.ICDR[28].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR29      SARADC_2.ICDR[29].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR30      SARADC_2.ICDR[30].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR31      SARADC_2.ICDR[31].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR32      SARADC_2.ICDR[32].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR33      SARADC_2.ICDR[33].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR34      SARADC_2.ICDR[34].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR35      SARADC_2.ICDR[35].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR36      SARADC_2.ICDR[36].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR37      SARADC_2.ICDR[37].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR38      SARADC_2.ICDR[38].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR39      SARADC_2.ICDR[39].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR40      SARADC_2.ICDR[40].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR41      SARADC_2.ICDR[41].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR42      SARADC_2.ICDR[42].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR43      SARADC_2.ICDR[43].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR44      SARADC_2.ICDR[44].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR45      SARADC_2.ICDR[45].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR46      SARADC_2.ICDR[46].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR47      SARADC_2.ICDR[47].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR48      SARADC_2.ICDR[48].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR49      SARADC_2.ICDR[49].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR50      SARADC_2.ICDR[50].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR51      SARADC_2.ICDR[51].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR52      SARADC_2.ICDR[52].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR53      SARADC_2.ICDR[53].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR54      SARADC_2.ICDR[54].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR55      SARADC_2.ICDR[55].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR56      SARADC_2.ICDR[56].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR57      SARADC_2.ICDR[57].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR58      SARADC_2.ICDR[58].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR59      SARADC_2.ICDR[59].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR60      SARADC_2.ICDR[60].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR61      SARADC_2.ICDR[61].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR62      SARADC_2.ICDR[62].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR63      SARADC_2.ICDR[63].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR64      SARADC_2.ICDR[64].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR65      SARADC_2.ICDR[65].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR66      SARADC_2.ICDR[66].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR67      SARADC_2.ICDR[67].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR68      SARADC_2.ICDR[68].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR69      SARADC_2.ICDR[69].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR70      SARADC_2.ICDR[70].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR71      SARADC_2.ICDR[71].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR72      SARADC_2.ICDR[72].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR73      SARADC_2.ICDR[73].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR74      SARADC_2.ICDR[74].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR75      SARADC_2.ICDR[75].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR76      SARADC_2.ICDR[76].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR77      SARADC_2.ICDR[77].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR78      SARADC_2.ICDR[78].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR79      SARADC_2.ICDR[79].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR80      SARADC_2.ICDR[80].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR81      SARADC_2.ICDR[81].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR82      SARADC_2.ICDR[82].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR83      SARADC_2.ICDR[83].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR84      SARADC_2.ICDR[84].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR85      SARADC_2.ICDR[85].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR86      SARADC_2.ICDR[86].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR87      SARADC_2.ICDR[87].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR88      SARADC_2.ICDR[88].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR89      SARADC_2.ICDR[89].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR90      SARADC_2.ICDR[90].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR91      SARADC_2.ICDR[91].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR92      SARADC_2.ICDR[92].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR93      SARADC_2.ICDR[93].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR94      SARADC_2.ICDR[94].R           /* Internal Channel Data Register */
#define SARADC_2_ICDR95      SARADC_2.ICDR[95].R           /* Internal Channel Data Register */
#define SARADC_2_ICWSELR0    SARADC_2.ICWSELR[0].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_2_ICWSELR1    SARADC_2.ICWSELR[1].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_2_ICWSELR2    SARADC_2.ICWSELR[2].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_2_ICWSELR3    SARADC_2.ICWSELR[3].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_2_ICWSELR4    SARADC_2.ICWSELR[4].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_2_ICWSELR5    SARADC_2.ICWSELR[5].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_2_ICWSELR6    SARADC_2.ICWSELR[6].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_2_ICWSELR7    SARADC_2.ICWSELR[7].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_2_ICWSELR8    SARADC_2.ICWSELR[8].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_2_ICWSELR9    SARADC_2.ICWSELR[9].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_2_ICWSELR10   SARADC_2.ICWSELR[10].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_2_ICWSELR11   SARADC_2.ICWSELR[11].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_2_ICWENR0     SARADC_2.ICWENR[0].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_2_ICWENR1     SARADC_2.ICWENR[1].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_2_ICWENR2     SARADC_2.ICWENR[2].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_2_ICAWORR0    SARADC_2.ICAWORR[0].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_2_ICAWORR1    SARADC_2.ICAWORR[1].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_2_ICAWORR2    SARADC_2.ICAWORR[2].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_2_TCIPR       SARADC_2.TCIPR.R              /* Test Channel Interrupt Pending Register */
#define SARADC_2_TCIMR       SARADC_2.TCIMR.R              /* Test Channel Interrupt Mask Register */
#define SARADC_2_TCDSR       SARADC_2.TCDSR.R              /* Test Channel DMA Select Register */
#define SARADC_2_TCNCMR      SARADC_2.TCNCMR.R             /* Test Channel Normal Conversion Mask Register */
#define SARADC_2_TCJCMR      SARADC_2.TCJCMR.R             /* Test Channel Injected Conversion Mask Register */
#define SARADC_2_TCWSELR0    SARADC_2.TCWSELR[0].R         /* Test Channel Watchdog Selection Register */
#define SARADC_2_TCWSELR1    SARADC_2.TCWSELR[1].R         /* Test Channel Watchdog Selection Register */
#define SARADC_2_TCWSELR2    SARADC_2.TCWSELR[2].R         /* Test Channel Watchdog Selection Register */
#define SARADC_2_TCWSELR3    SARADC_2.TCWSELR[3].R         /* Test Channel Watchdog Selection Register */
#define SARADC_2_TCWENR      SARADC_2.TCWENR.R             /* Test Channel Watchdog Enable Register */
#define SARADC_2_TCAWORR     SARADC_2.TCAWORR.R            /* Test Channel Analog Watchdog Out of Range Register */
#define SARADC_2_TCCAPR0     SARADC_2.TCCAPR[0].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_2_TCCAPR1     SARADC_2.TCCAPR[1].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_2_TCCAPR2     SARADC_2.TCCAPR[2].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_2_TCCAPR3     SARADC_2.TCCAPR[3].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_2_TCCAPR4     SARADC_2.TCCAPR[4].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_2_TCCAPR5     SARADC_2.TCCAPR[5].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_2_TCCAPR6     SARADC_2.TCCAPR[6].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_2_TCCAPR7     SARADC_2.TCCAPR[7].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_2_TCDR96      SARADC_2.TCDR[0].R            /* Test Channel Data Register */
#define SARADC_2_TCDR97      SARADC_2.TCDR[1].R            /* Test Channel Data Register */
#define SARADC_2_TCDR98      SARADC_2.TCDR[2].R            /* Test Channel Data Register */
#define SARADC_2_TCDR99      SARADC_2.TCDR[3].R            /* Test Channel Data Register */
#define SARADC_2_TCDR100     SARADC_2.TCDR[4].R            /* Test Channel Data Register */
#define SARADC_2_TCDR101     SARADC_2.TCDR[5].R            /* Test Channel Data Register */
#define SARADC_2_TCDR102     SARADC_2.TCDR[6].R            /* Test Channel Data Register */
#define SARADC_2_TCDR103     SARADC_2.TCDR[7].R            /* Test Channel Data Register */
#define SARADC_2_TCDR104     SARADC_2.TCDR[8].R            /* Test Channel Data Register */
#define SARADC_2_TCDR105     SARADC_2.TCDR[9].R            /* Test Channel Data Register */
#define SARADC_2_TCDR106     SARADC_2.TCDR[10].R           /* Test Channel Data Register */
#define SARADC_2_TCDR107     SARADC_2.TCDR[11].R           /* Test Channel Data Register */
#define SARADC_2_TCDR108     SARADC_2.TCDR[12].R           /* Test Channel Data Register */
#define SARADC_2_TCDR109     SARADC_2.TCDR[13].R           /* Test Channel Data Register */
#define SARADC_2_TCDR110     SARADC_2.TCDR[14].R           /* Test Channel Data Register */
#define SARADC_2_TCDR111     SARADC_2.TCDR[15].R           /* Test Channel Data Register */
#define SARADC_2_TCDR112     SARADC_2.TCDR[16].R           /* Test Channel Data Register */
#define SARADC_2_TCDR113     SARADC_2.TCDR[17].R           /* Test Channel Data Register */
#define SARADC_2_TCDR114     SARADC_2.TCDR[18].R           /* Test Channel Data Register */
#define SARADC_2_TCDR115     SARADC_2.TCDR[19].R           /* Test Channel Data Register */
#define SARADC_2_TCDR116     SARADC_2.TCDR[20].R           /* Test Channel Data Register */
#define SARADC_2_TCDR117     SARADC_2.TCDR[21].R           /* Test Channel Data Register */
#define SARADC_2_TCDR118     SARADC_2.TCDR[22].R           /* Test Channel Data Register */
#define SARADC_2_TCDR119     SARADC_2.TCDR[23].R           /* Test Channel Data Register */
#define SARADC_2_TCDR120     SARADC_2.TCDR[24].R           /* Test Channel Data Register */
#define SARADC_2_TCDR121     SARADC_2.TCDR[25].R           /* Test Channel Data Register */
#define SARADC_2_TCDR122     SARADC_2.TCDR[26].R           /* Test Channel Data Register */
#define SARADC_2_TCDR123     SARADC_2.TCDR[27].R           /* Test Channel Data Register */
#define SARADC_2_TCDR124     SARADC_2.TCDR[28].R           /* Test Channel Data Register */
#define SARADC_2_TCDR125     SARADC_2.TCDR[29].R           /* Test Channel Data Register */
#define SARADC_2_TCDR126     SARADC_2.TCDR[30].R           /* Test Channel Data Register */
#define SARADC_2_TCDR127     SARADC_2.TCDR[31].R           /* Test Channel Data Register */
#define SARADC_2_ECDSDR      SARADC_2.ECDSDR.R             /* External Channel Decode Signals Delay Register */
#define SARADC_2_ECIPR0      SARADC_2.ECIPR[0].R           /* External Channel Interrupt Pending Register */
#define SARADC_2_ECIPR1      SARADC_2.ECIPR[1].R           /* External Channel Interrupt Pending Register */
#define SARADC_2_ECIPR2      SARADC_2.ECIPR[2].R           /* External Channel Interrupt Pending Register */
#define SARADC_2_ECIPR3      SARADC_2.ECIPR[3].R           /* External Channel Interrupt Pending Register */
#define SARADC_2_ECIMR0      SARADC_2.ECIMR[0].R           /* External Channel Interrupt Mask Register */
#define SARADC_2_ECIMR1      SARADC_2.ECIMR[1].R           /* External Channel Interrupt Mask Register */
#define SARADC_2_ECIMR2      SARADC_2.ECIMR[2].R           /* External Channel Interrupt Mask Register */
#define SARADC_2_ECIMR3      SARADC_2.ECIMR[3].R           /* External Channel Interrupt Mask Register */
#define SARADC_2_ECDSR0      SARADC_2.ECDSR[0].R           /* External Channel DMA Select Register */
#define SARADC_2_ECDSR1      SARADC_2.ECDSR[1].R           /* External Channel DMA Select Register */
#define SARADC_2_ECDSR2      SARADC_2.ECDSR[2].R           /* External Channel DMA Select Register */
#define SARADC_2_ECDSR3      SARADC_2.ECDSR[3].R           /* External Channel DMA Select Register */
#define SARADC_2_ECNCMR0     SARADC_2.ECNCMR[0].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_2_ECNCMR1     SARADC_2.ECNCMR[1].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_2_ECNCMR2     SARADC_2.ECNCMR[2].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_2_ECNCMR3     SARADC_2.ECNCMR[3].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_2_ECJCMR0     SARADC_2.ECJCMR[0].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_2_ECJCMR1     SARADC_2.ECJCMR[1].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_2_ECJCMR2     SARADC_2.ECJCMR[2].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_2_ECJCMR3     SARADC_2.ECJCMR[3].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_2_ECWSELR0    SARADC_2.ECWSELR[0].R         /* External Channel Watchdog Selection Register */
#define SARADC_2_ECWSELR1    SARADC_2.ECWSELR[1].R         /* External Channel Watchdog Selection Register */
#define SARADC_2_ECWSELR2    SARADC_2.ECWSELR[2].R         /* External Channel Watchdog Selection Register */
#define SARADC_2_ECWSELR3    SARADC_2.ECWSELR[3].R         /* External Channel Watchdog Selection Register */
#define SARADC_2_ECWSELR4    SARADC_2.ECWSELR[4].R         /* External Channel Watchdog Selection Register */
#define SARADC_2_ECWSELR5    SARADC_2.ECWSELR[5].R         /* External Channel Watchdog Selection Register */
#define SARADC_2_ECWSELR6    SARADC_2.ECWSELR[6].R         /* External Channel Watchdog Selection Register */
#define SARADC_2_ECWSELR7    SARADC_2.ECWSELR[7].R         /* External Channel Watchdog Selection Register */
#define SARADC_2_ECWSELR8    SARADC_2.ECWSELR[8].R         /* External Channel Watchdog Selection Register */
#define SARADC_2_ECWSELR9    SARADC_2.ECWSELR[9].R         /* External Channel Watchdog Selection Register */
#define SARADC_2_ECWSELR10   SARADC_2.ECWSELR[10].R        /* External Channel Watchdog Selection Register */
#define SARADC_2_ECWSELR11   SARADC_2.ECWSELR[11].R        /* External Channel Watchdog Selection Register */
#define SARADC_2_ECWSELR12   SARADC_2.ECWSELR[12].R        /* External Channel Watchdog Selection Register */
#define SARADC_2_ECWSELR13   SARADC_2.ECWSELR[13].R        /* External Channel Watchdog Selection Register */
#define SARADC_2_ECWSELR14   SARADC_2.ECWSELR[14].R        /* External Channel Watchdog Selection Register */
#define SARADC_2_ECWSELR15   SARADC_2.ECWSELR[15].R        /* External Channel Watchdog Selection Register */
#define SARADC_2_ECWENR0     SARADC_2.ECWENR[0].R          /* External Channel Watchdog Enable Register */
#define SARADC_2_ECWENR1     SARADC_2.ECWENR[1].R          /* External Channel Watchdog Enable Register */
#define SARADC_2_ECWENR2     SARADC_2.ECWENR[2].R          /* External Channel Watchdog Enable Register */
#define SARADC_2_ECWENR3     SARADC_2.ECWENR[3].R          /* External Channel Watchdog Enable Register */
#define SARADC_2_ECAWORR0    SARADC_2.ECAWORR[0].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_2_ECAWORR1    SARADC_2.ECAWORR[1].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_2_ECAWORR2    SARADC_2.ECAWORR[2].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_2_ECAWORR3    SARADC_2.ECAWORR[3].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_2_ECMICR0     SARADC_2.ECMICR[0].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_2_ECMICR1     SARADC_2.ECMICR[1].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_2_ECMICR2     SARADC_2.ECMICR[2].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_2_ECMICR3     SARADC_2.ECMICR[3].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_2_ECDR128     SARADC_2.ECDR[0].R            /* External Channel Data Register */
#define SARADC_2_ECDR129     SARADC_2.ECDR[1].R            /* External Channel Data Register */
#define SARADC_2_ECDR130     SARADC_2.ECDR[2].R            /* External Channel Data Register */
#define SARADC_2_ECDR131     SARADC_2.ECDR[3].R            /* External Channel Data Register */
#define SARADC_2_ECDR132     SARADC_2.ECDR[4].R            /* External Channel Data Register */
#define SARADC_2_ECDR133     SARADC_2.ECDR[5].R            /* External Channel Data Register */
#define SARADC_2_ECDR134     SARADC_2.ECDR[6].R            /* External Channel Data Register */
#define SARADC_2_ECDR135     SARADC_2.ECDR[7].R            /* External Channel Data Register */
#define SARADC_2_ECDR136     SARADC_2.ECDR[8].R            /* External Channel Data Register */
#define SARADC_2_ECDR137     SARADC_2.ECDR[9].R            /* External Channel Data Register */
#define SARADC_2_ECDR138     SARADC_2.ECDR[10].R           /* External Channel Data Register */
#define SARADC_2_ECDR139     SARADC_2.ECDR[11].R           /* External Channel Data Register */
#define SARADC_2_ECDR140     SARADC_2.ECDR[12].R           /* External Channel Data Register */
#define SARADC_2_ECDR141     SARADC_2.ECDR[13].R           /* External Channel Data Register */
#define SARADC_2_ECDR142     SARADC_2.ECDR[14].R           /* External Channel Data Register */
#define SARADC_2_ECDR143     SARADC_2.ECDR[15].R           /* External Channel Data Register */
#define SARADC_2_ECDR144     SARADC_2.ECDR[16].R           /* External Channel Data Register */
#define SARADC_2_ECDR145     SARADC_2.ECDR[17].R           /* External Channel Data Register */
#define SARADC_2_ECDR146     SARADC_2.ECDR[18].R           /* External Channel Data Register */
#define SARADC_2_ECDR147     SARADC_2.ECDR[19].R           /* External Channel Data Register */
#define SARADC_2_ECDR148     SARADC_2.ECDR[20].R           /* External Channel Data Register */
#define SARADC_2_ECDR149     SARADC_2.ECDR[21].R           /* External Channel Data Register */
#define SARADC_2_ECDR150     SARADC_2.ECDR[22].R           /* External Channel Data Register */
#define SARADC_2_ECDR151     SARADC_2.ECDR[23].R           /* External Channel Data Register */
#define SARADC_2_ECDR152     SARADC_2.ECDR[24].R           /* External Channel Data Register */
#define SARADC_2_ECDR153     SARADC_2.ECDR[25].R           /* External Channel Data Register */
#define SARADC_2_ECDR154     SARADC_2.ECDR[26].R           /* External Channel Data Register */
#define SARADC_2_ECDR155     SARADC_2.ECDR[27].R           /* External Channel Data Register */
#define SARADC_2_ECDR156     SARADC_2.ECDR[28].R           /* External Channel Data Register */
#define SARADC_2_ECDR157     SARADC_2.ECDR[29].R           /* External Channel Data Register */
#define SARADC_2_ECDR158     SARADC_2.ECDR[30].R           /* External Channel Data Register */
#define SARADC_2_ECDR159     SARADC_2.ECDR[31].R           /* External Channel Data Register */
#define SARADC_2_ECDR160     SARADC_2.ECDR[32].R           /* External Channel Data Register */
#define SARADC_2_ECDR161     SARADC_2.ECDR[33].R           /* External Channel Data Register */
#define SARADC_2_ECDR162     SARADC_2.ECDR[34].R           /* External Channel Data Register */
#define SARADC_2_ECDR163     SARADC_2.ECDR[35].R           /* External Channel Data Register */
#define SARADC_2_ECDR164     SARADC_2.ECDR[36].R           /* External Channel Data Register */
#define SARADC_2_ECDR165     SARADC_2.ECDR[37].R           /* External Channel Data Register */
#define SARADC_2_ECDR166     SARADC_2.ECDR[38].R           /* External Channel Data Register */
#define SARADC_2_ECDR167     SARADC_2.ECDR[39].R           /* External Channel Data Register */
#define SARADC_2_ECDR168     SARADC_2.ECDR[40].R           /* External Channel Data Register */
#define SARADC_2_ECDR169     SARADC_2.ECDR[41].R           /* External Channel Data Register */
#define SARADC_2_ECDR170     SARADC_2.ECDR[42].R           /* External Channel Data Register */
#define SARADC_2_ECDR171     SARADC_2.ECDR[43].R           /* External Channel Data Register */
#define SARADC_2_ECDR172     SARADC_2.ECDR[44].R           /* External Channel Data Register */
#define SARADC_2_ECDR173     SARADC_2.ECDR[45].R           /* External Channel Data Register */
#define SARADC_2_ECDR174     SARADC_2.ECDR[46].R           /* External Channel Data Register */
#define SARADC_2_ECDR175     SARADC_2.ECDR[47].R           /* External Channel Data Register */
#define SARADC_2_ECDR176     SARADC_2.ECDR[48].R           /* External Channel Data Register */
#define SARADC_2_ECDR177     SARADC_2.ECDR[49].R           /* External Channel Data Register */
#define SARADC_2_ECDR178     SARADC_2.ECDR[50].R           /* External Channel Data Register */
#define SARADC_2_ECDR179     SARADC_2.ECDR[51].R           /* External Channel Data Register */
#define SARADC_2_ECDR180     SARADC_2.ECDR[52].R           /* External Channel Data Register */
#define SARADC_2_ECDR181     SARADC_2.ECDR[53].R           /* External Channel Data Register */
#define SARADC_2_ECDR182     SARADC_2.ECDR[54].R           /* External Channel Data Register */
#define SARADC_2_ECDR183     SARADC_2.ECDR[55].R           /* External Channel Data Register */
#define SARADC_2_ECDR184     SARADC_2.ECDR[56].R           /* External Channel Data Register */
#define SARADC_2_ECDR185     SARADC_2.ECDR[57].R           /* External Channel Data Register */
#define SARADC_2_ECDR186     SARADC_2.ECDR[58].R           /* External Channel Data Register */
#define SARADC_2_ECDR187     SARADC_2.ECDR[59].R           /* External Channel Data Register */
#define SARADC_2_ECDR188     SARADC_2.ECDR[60].R           /* External Channel Data Register */
#define SARADC_2_ECDR189     SARADC_2.ECDR[61].R           /* External Channel Data Register */
#define SARADC_2_ECDR190     SARADC_2.ECDR[62].R           /* External Channel Data Register */
#define SARADC_2_ECDR191     SARADC_2.ECDR[63].R           /* External Channel Data Register */
#define SARADC_2_ECDR192     SARADC_2.ECDR[64].R           /* External Channel Data Register */
#define SARADC_2_ECDR193     SARADC_2.ECDR[65].R           /* External Channel Data Register */
#define SARADC_2_ECDR194     SARADC_2.ECDR[66].R           /* External Channel Data Register */
#define SARADC_2_ECDR195     SARADC_2.ECDR[67].R           /* External Channel Data Register */
#define SARADC_2_ECDR196     SARADC_2.ECDR[68].R           /* External Channel Data Register */
#define SARADC_2_ECDR197     SARADC_2.ECDR[69].R           /* External Channel Data Register */
#define SARADC_2_ECDR198     SARADC_2.ECDR[70].R           /* External Channel Data Register */
#define SARADC_2_ECDR199     SARADC_2.ECDR[71].R           /* External Channel Data Register */
#define SARADC_2_ECDR200     SARADC_2.ECDR[72].R           /* External Channel Data Register */
#define SARADC_2_ECDR201     SARADC_2.ECDR[73].R           /* External Channel Data Register */
#define SARADC_2_ECDR202     SARADC_2.ECDR[74].R           /* External Channel Data Register */
#define SARADC_2_ECDR203     SARADC_2.ECDR[75].R           /* External Channel Data Register */
#define SARADC_2_ECDR204     SARADC_2.ECDR[76].R           /* External Channel Data Register */
#define SARADC_2_ECDR205     SARADC_2.ECDR[77].R           /* External Channel Data Register */
#define SARADC_2_ECDR206     SARADC_2.ECDR[78].R           /* External Channel Data Register */
#define SARADC_2_ECDR207     SARADC_2.ECDR[79].R           /* External Channel Data Register */
#define SARADC_2_ECDR208     SARADC_2.ECDR[80].R           /* External Channel Data Register */
#define SARADC_2_ECDR209     SARADC_2.ECDR[81].R           /* External Channel Data Register */
#define SARADC_2_ECDR210     SARADC_2.ECDR[82].R           /* External Channel Data Register */
#define SARADC_2_ECDR211     SARADC_2.ECDR[83].R           /* External Channel Data Register */
#define SARADC_2_ECDR212     SARADC_2.ECDR[84].R           /* External Channel Data Register */
#define SARADC_2_ECDR213     SARADC_2.ECDR[85].R           /* External Channel Data Register */
#define SARADC_2_ECDR214     SARADC_2.ECDR[86].R           /* External Channel Data Register */
#define SARADC_2_ECDR215     SARADC_2.ECDR[87].R           /* External Channel Data Register */
#define SARADC_2_ECDR216     SARADC_2.ECDR[88].R           /* External Channel Data Register */
#define SARADC_2_ECDR217     SARADC_2.ECDR[89].R           /* External Channel Data Register */
#define SARADC_2_ECDR218     SARADC_2.ECDR[90].R           /* External Channel Data Register */
#define SARADC_2_ECDR219     SARADC_2.ECDR[91].R           /* External Channel Data Register */
#define SARADC_2_ECDR220     SARADC_2.ECDR[92].R           /* External Channel Data Register */
#define SARADC_2_ECDR221     SARADC_2.ECDR[93].R           /* External Channel Data Register */
#define SARADC_2_ECDR222     SARADC_2.ECDR[94].R           /* External Channel Data Register */
#define SARADC_2_ECDR223     SARADC_2.ECDR[95].R           /* External Channel Data Register */
#define SARADC_2_ECDR224     SARADC_2.ECDR[96].R           /* External Channel Data Register */
#define SARADC_2_ECDR225     SARADC_2.ECDR[97].R           /* External Channel Data Register */
#define SARADC_2_ECDR226     SARADC_2.ECDR[98].R           /* External Channel Data Register */
#define SARADC_2_ECDR227     SARADC_2.ECDR[99].R           /* External Channel Data Register */
#define SARADC_2_ECDR228     SARADC_2.ECDR[100].R          /* External Channel Data Register */
#define SARADC_2_ECDR229     SARADC_2.ECDR[101].R          /* External Channel Data Register */
#define SARADC_2_ECDR230     SARADC_2.ECDR[102].R          /* External Channel Data Register */
#define SARADC_2_ECDR231     SARADC_2.ECDR[103].R          /* External Channel Data Register */
#define SARADC_2_ECDR232     SARADC_2.ECDR[104].R          /* External Channel Data Register */
#define SARADC_2_ECDR233     SARADC_2.ECDR[105].R          /* External Channel Data Register */
#define SARADC_2_ECDR234     SARADC_2.ECDR[106].R          /* External Channel Data Register */
#define SARADC_2_ECDR235     SARADC_2.ECDR[107].R          /* External Channel Data Register */
#define SARADC_2_ECDR236     SARADC_2.ECDR[108].R          /* External Channel Data Register */
#define SARADC_2_ECDR237     SARADC_2.ECDR[109].R          /* External Channel Data Register */
#define SARADC_2_ECDR238     SARADC_2.ECDR[110].R          /* External Channel Data Register */
#define SARADC_2_ECDR239     SARADC_2.ECDR[111].R          /* External Channel Data Register */
#define SARADC_2_ECDR240     SARADC_2.ECDR[112].R          /* External Channel Data Register */
#define SARADC_2_ECDR241     SARADC_2.ECDR[113].R          /* External Channel Data Register */
#define SARADC_2_ECDR242     SARADC_2.ECDR[114].R          /* External Channel Data Register */
#define SARADC_2_ECDR243     SARADC_2.ECDR[115].R          /* External Channel Data Register */
#define SARADC_2_ECDR244     SARADC_2.ECDR[116].R          /* External Channel Data Register */
#define SARADC_2_ECDR245     SARADC_2.ECDR[117].R          /* External Channel Data Register */
#define SARADC_2_ECDR246     SARADC_2.ECDR[118].R          /* External Channel Data Register */
#define SARADC_2_ECDR247     SARADC_2.ECDR[119].R          /* External Channel Data Register */
#define SARADC_2_ECDR248     SARADC_2.ECDR[120].R          /* External Channel Data Register */
#define SARADC_2_ECDR249     SARADC_2.ECDR[121].R          /* External Channel Data Register */
#define SARADC_2_ECDR250     SARADC_2.ECDR[122].R          /* External Channel Data Register */
#define SARADC_2_ECDR251     SARADC_2.ECDR[123].R          /* External Channel Data Register */
#define SARADC_2_ECDR252     SARADC_2.ECDR[124].R          /* External Channel Data Register */
#define SARADC_2_ECDR253     SARADC_2.ECDR[125].R          /* External Channel Data Register */
#define SARADC_2_ECDR254     SARADC_2.ECDR[126].R          /* External Channel Data Register */
#define SARADC_2_ECDR255     SARADC_2.ECDR[127].R          /* External Channel Data Register */

/* SARADC */
#define SARADC_3_MCR         SARADC_3.MCR.R                /* Main Configuration Register */
#define SARADC_3_MSR         SARADC_3.MSR.R                /* Main Status Register */
#define SARADC_3_ISR         SARADC_3.ISR.R                /* Interrupt Status Register */
#define SARADC_3_ICIPR0      SARADC_3.ICIPR[0].R           /* Internal channel Interrupt Pending Register */
#define SARADC_3_ICIPR1      SARADC_3.ICIPR[1].R           /* Internal channel Interrupt Pending Register */
#define SARADC_3_ICIPR2      SARADC_3.ICIPR[2].R           /* Internal channel Interrupt Pending Register */
#define SARADC_3_IMR         SARADC_3.IMR.R                /* Interrupt Mask Register */
#define SARADC_3_ICIMR0      SARADC_3.ICIMR[0].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_3_ICIMR1      SARADC_3.ICIMR[1].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_3_ICIMR2      SARADC_3.ICIMR[2].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_3_WTISR       SARADC_3.WTISR.R              /* Watchdog Threshold Interrupt Status Register */
#define SARADC_3_WTIMR       SARADC_3.WTIMR.R              /* Watchdog Threshold Interrupt Mask Register */
#define SARADC_3_DMAE        SARADC_3.DMAE.R               /* DMA Enable Register */
#define SARADC_3_ICDSR0      SARADC_3.ICDSR[0].R           /* Internal Channel DMA Select Register */
#define SARADC_3_ICDSR1      SARADC_3.ICDSR[1].R           /* Internal Channel DMA Select Register */
#define SARADC_3_ICDSR2      SARADC_3.ICDSR[2].R           /* Internal Channel DMA Select Register */
#define SARADC_3_WTHRHLR0    SARADC_3.WTHRHLR[0].R         /* Watchdog Threshold Register */
#define SARADC_3_WTHRHLR1    SARADC_3.WTHRHLR[1].R         /* Watchdog Threshold Register */
#define SARADC_3_WTHRHLR2    SARADC_3.WTHRHLR[2].R         /* Watchdog Threshold Register */
#define SARADC_3_WTHRHLR3    SARADC_3.WTHRHLR[3].R         /* Watchdog Threshold Register */
#define SARADC_3_CTR0        SARADC_3.CTR[0].R             /* Conversion Timing Register */
#define SARADC_3_CTR1        SARADC_3.CTR[1].R             /* Conversion Timing Register */
#define SARADC_3_CTR2        SARADC_3.CTR[2].R             /* Conversion Timing Register */
#define SARADC_3_CTR3        SARADC_3.CTR[3].R             /* Conversion Timing Register */
#define SARADC_3_ICNCMR0     SARADC_3.ICNCMR[0].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_3_ICNCMR1     SARADC_3.ICNCMR[1].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_3_ICNCMR2     SARADC_3.ICNCMR[2].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_3_ICJCMR0     SARADC_3.ICJCMR[0].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_3_ICJCMR1     SARADC_3.ICJCMR[1].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_3_ICJCMR2     SARADC_3.ICJCMR[2].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_3_PDEDR       SARADC_3.PDEDR.R              /* Power Down Exit Delay Register */
#define SARADC_3_ICDR0       SARADC_3.ICDR[0].R            /* Internal Channel Data Register */
#define SARADC_3_ICDR1       SARADC_3.ICDR[1].R            /* Internal Channel Data Register */
#define SARADC_3_ICDR2       SARADC_3.ICDR[2].R            /* Internal Channel Data Register */
#define SARADC_3_ICDR3       SARADC_3.ICDR[3].R            /* Internal Channel Data Register */
#define SARADC_3_ICDR4       SARADC_3.ICDR[4].R            /* Internal Channel Data Register */
#define SARADC_3_ICDR5       SARADC_3.ICDR[5].R            /* Internal Channel Data Register */
#define SARADC_3_ICDR6       SARADC_3.ICDR[6].R            /* Internal Channel Data Register */
#define SARADC_3_ICDR7       SARADC_3.ICDR[7].R            /* Internal Channel Data Register */
#define SARADC_3_ICDR8       SARADC_3.ICDR[8].R            /* Internal Channel Data Register */
#define SARADC_3_ICDR9       SARADC_3.ICDR[9].R            /* Internal Channel Data Register */
#define SARADC_3_ICDR10      SARADC_3.ICDR[10].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR11      SARADC_3.ICDR[11].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR12      SARADC_3.ICDR[12].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR13      SARADC_3.ICDR[13].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR14      SARADC_3.ICDR[14].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR15      SARADC_3.ICDR[15].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR16      SARADC_3.ICDR[16].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR17      SARADC_3.ICDR[17].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR18      SARADC_3.ICDR[18].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR19      SARADC_3.ICDR[19].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR20      SARADC_3.ICDR[20].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR21      SARADC_3.ICDR[21].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR22      SARADC_3.ICDR[22].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR23      SARADC_3.ICDR[23].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR24      SARADC_3.ICDR[24].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR25      SARADC_3.ICDR[25].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR26      SARADC_3.ICDR[26].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR27      SARADC_3.ICDR[27].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR28      SARADC_3.ICDR[28].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR29      SARADC_3.ICDR[29].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR30      SARADC_3.ICDR[30].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR31      SARADC_3.ICDR[31].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR32      SARADC_3.ICDR[32].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR33      SARADC_3.ICDR[33].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR34      SARADC_3.ICDR[34].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR35      SARADC_3.ICDR[35].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR36      SARADC_3.ICDR[36].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR37      SARADC_3.ICDR[37].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR38      SARADC_3.ICDR[38].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR39      SARADC_3.ICDR[39].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR40      SARADC_3.ICDR[40].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR41      SARADC_3.ICDR[41].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR42      SARADC_3.ICDR[42].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR43      SARADC_3.ICDR[43].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR44      SARADC_3.ICDR[44].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR45      SARADC_3.ICDR[45].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR46      SARADC_3.ICDR[46].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR47      SARADC_3.ICDR[47].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR48      SARADC_3.ICDR[48].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR49      SARADC_3.ICDR[49].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR50      SARADC_3.ICDR[50].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR51      SARADC_3.ICDR[51].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR52      SARADC_3.ICDR[52].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR53      SARADC_3.ICDR[53].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR54      SARADC_3.ICDR[54].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR55      SARADC_3.ICDR[55].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR56      SARADC_3.ICDR[56].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR57      SARADC_3.ICDR[57].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR58      SARADC_3.ICDR[58].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR59      SARADC_3.ICDR[59].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR60      SARADC_3.ICDR[60].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR61      SARADC_3.ICDR[61].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR62      SARADC_3.ICDR[62].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR63      SARADC_3.ICDR[63].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR64      SARADC_3.ICDR[64].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR65      SARADC_3.ICDR[65].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR66      SARADC_3.ICDR[66].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR67      SARADC_3.ICDR[67].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR68      SARADC_3.ICDR[68].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR69      SARADC_3.ICDR[69].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR70      SARADC_3.ICDR[70].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR71      SARADC_3.ICDR[71].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR72      SARADC_3.ICDR[72].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR73      SARADC_3.ICDR[73].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR74      SARADC_3.ICDR[74].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR75      SARADC_3.ICDR[75].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR76      SARADC_3.ICDR[76].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR77      SARADC_3.ICDR[77].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR78      SARADC_3.ICDR[78].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR79      SARADC_3.ICDR[79].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR80      SARADC_3.ICDR[80].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR81      SARADC_3.ICDR[81].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR82      SARADC_3.ICDR[82].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR83      SARADC_3.ICDR[83].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR84      SARADC_3.ICDR[84].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR85      SARADC_3.ICDR[85].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR86      SARADC_3.ICDR[86].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR87      SARADC_3.ICDR[87].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR88      SARADC_3.ICDR[88].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR89      SARADC_3.ICDR[89].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR90      SARADC_3.ICDR[90].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR91      SARADC_3.ICDR[91].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR92      SARADC_3.ICDR[92].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR93      SARADC_3.ICDR[93].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR94      SARADC_3.ICDR[94].R           /* Internal Channel Data Register */
#define SARADC_3_ICDR95      SARADC_3.ICDR[95].R           /* Internal Channel Data Register */
#define SARADC_3_ICWSELR0    SARADC_3.ICWSELR[0].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_3_ICWSELR1    SARADC_3.ICWSELR[1].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_3_ICWSELR2    SARADC_3.ICWSELR[2].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_3_ICWSELR3    SARADC_3.ICWSELR[3].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_3_ICWSELR4    SARADC_3.ICWSELR[4].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_3_ICWSELR5    SARADC_3.ICWSELR[5].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_3_ICWSELR6    SARADC_3.ICWSELR[6].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_3_ICWSELR7    SARADC_3.ICWSELR[7].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_3_ICWSELR8    SARADC_3.ICWSELR[8].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_3_ICWSELR9    SARADC_3.ICWSELR[9].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_3_ICWSELR10   SARADC_3.ICWSELR[10].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_3_ICWSELR11   SARADC_3.ICWSELR[11].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_3_ICWENR0     SARADC_3.ICWENR[0].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_3_ICWENR1     SARADC_3.ICWENR[1].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_3_ICWENR2     SARADC_3.ICWENR[2].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_3_ICAWORR0    SARADC_3.ICAWORR[0].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_3_ICAWORR1    SARADC_3.ICAWORR[1].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_3_ICAWORR2    SARADC_3.ICAWORR[2].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_3_TCIPR       SARADC_3.TCIPR.R              /* Test Channel Interrupt Pending Register */
#define SARADC_3_TCIMR       SARADC_3.TCIMR.R              /* Test Channel Interrupt Mask Register */
#define SARADC_3_TCDSR       SARADC_3.TCDSR.R              /* Test Channel DMA Select Register */
#define SARADC_3_TCNCMR      SARADC_3.TCNCMR.R             /* Test Channel Normal Conversion Mask Register */
#define SARADC_3_TCJCMR      SARADC_3.TCJCMR.R             /* Test Channel Injected Conversion Mask Register */
#define SARADC_3_TCWSELR0    SARADC_3.TCWSELR[0].R         /* Test Channel Watchdog Selection Register */
#define SARADC_3_TCWSELR1    SARADC_3.TCWSELR[1].R         /* Test Channel Watchdog Selection Register */
#define SARADC_3_TCWSELR2    SARADC_3.TCWSELR[2].R         /* Test Channel Watchdog Selection Register */
#define SARADC_3_TCWSELR3    SARADC_3.TCWSELR[3].R         /* Test Channel Watchdog Selection Register */
#define SARADC_3_TCWENR      SARADC_3.TCWENR.R             /* Test Channel Watchdog Enable Register */
#define SARADC_3_TCAWORR     SARADC_3.TCAWORR.R            /* Test Channel Analog Watchdog Out of Range Register */
#define SARADC_3_TCCAPR0     SARADC_3.TCCAPR[0].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_3_TCCAPR1     SARADC_3.TCCAPR[1].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_3_TCCAPR2     SARADC_3.TCCAPR[2].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_3_TCCAPR3     SARADC_3.TCCAPR[3].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_3_TCCAPR4     SARADC_3.TCCAPR[4].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_3_TCCAPR5     SARADC_3.TCCAPR[5].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_3_TCCAPR6     SARADC_3.TCCAPR[6].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_3_TCCAPR7     SARADC_3.TCCAPR[7].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_3_TCDR96      SARADC_3.TCDR[0].R            /* Test Channel Data Register */
#define SARADC_3_TCDR97      SARADC_3.TCDR[1].R            /* Test Channel Data Register */
#define SARADC_3_TCDR98      SARADC_3.TCDR[2].R            /* Test Channel Data Register */
#define SARADC_3_TCDR99      SARADC_3.TCDR[3].R            /* Test Channel Data Register */
#define SARADC_3_TCDR100     SARADC_3.TCDR[4].R            /* Test Channel Data Register */
#define SARADC_3_TCDR101     SARADC_3.TCDR[5].R            /* Test Channel Data Register */
#define SARADC_3_TCDR102     SARADC_3.TCDR[6].R            /* Test Channel Data Register */
#define SARADC_3_TCDR103     SARADC_3.TCDR[7].R            /* Test Channel Data Register */
#define SARADC_3_TCDR104     SARADC_3.TCDR[8].R            /* Test Channel Data Register */
#define SARADC_3_TCDR105     SARADC_3.TCDR[9].R            /* Test Channel Data Register */
#define SARADC_3_TCDR106     SARADC_3.TCDR[10].R           /* Test Channel Data Register */
#define SARADC_3_TCDR107     SARADC_3.TCDR[11].R           /* Test Channel Data Register */
#define SARADC_3_TCDR108     SARADC_3.TCDR[12].R           /* Test Channel Data Register */
#define SARADC_3_TCDR109     SARADC_3.TCDR[13].R           /* Test Channel Data Register */
#define SARADC_3_TCDR110     SARADC_3.TCDR[14].R           /* Test Channel Data Register */
#define SARADC_3_TCDR111     SARADC_3.TCDR[15].R           /* Test Channel Data Register */
#define SARADC_3_TCDR112     SARADC_3.TCDR[16].R           /* Test Channel Data Register */
#define SARADC_3_TCDR113     SARADC_3.TCDR[17].R           /* Test Channel Data Register */
#define SARADC_3_TCDR114     SARADC_3.TCDR[18].R           /* Test Channel Data Register */
#define SARADC_3_TCDR115     SARADC_3.TCDR[19].R           /* Test Channel Data Register */
#define SARADC_3_TCDR116     SARADC_3.TCDR[20].R           /* Test Channel Data Register */
#define SARADC_3_TCDR117     SARADC_3.TCDR[21].R           /* Test Channel Data Register */
#define SARADC_3_TCDR118     SARADC_3.TCDR[22].R           /* Test Channel Data Register */
#define SARADC_3_TCDR119     SARADC_3.TCDR[23].R           /* Test Channel Data Register */
#define SARADC_3_TCDR120     SARADC_3.TCDR[24].R           /* Test Channel Data Register */
#define SARADC_3_TCDR121     SARADC_3.TCDR[25].R           /* Test Channel Data Register */
#define SARADC_3_TCDR122     SARADC_3.TCDR[26].R           /* Test Channel Data Register */
#define SARADC_3_TCDR123     SARADC_3.TCDR[27].R           /* Test Channel Data Register */
#define SARADC_3_TCDR124     SARADC_3.TCDR[28].R           /* Test Channel Data Register */
#define SARADC_3_TCDR125     SARADC_3.TCDR[29].R           /* Test Channel Data Register */
#define SARADC_3_TCDR126     SARADC_3.TCDR[30].R           /* Test Channel Data Register */
#define SARADC_3_TCDR127     SARADC_3.TCDR[31].R           /* Test Channel Data Register */
#define SARADC_3_ECDSDR      SARADC_3.ECDSDR.R             /* External Channel Decode Signals Delay Register */
#define SARADC_3_ECIPR0      SARADC_3.ECIPR[0].R           /* External Channel Interrupt Pending Register */
#define SARADC_3_ECIPR1      SARADC_3.ECIPR[1].R           /* External Channel Interrupt Pending Register */
#define SARADC_3_ECIPR2      SARADC_3.ECIPR[2].R           /* External Channel Interrupt Pending Register */
#define SARADC_3_ECIPR3      SARADC_3.ECIPR[3].R           /* External Channel Interrupt Pending Register */
#define SARADC_3_ECIMR0      SARADC_3.ECIMR[0].R           /* External Channel Interrupt Mask Register */
#define SARADC_3_ECIMR1      SARADC_3.ECIMR[1].R           /* External Channel Interrupt Mask Register */
#define SARADC_3_ECIMR2      SARADC_3.ECIMR[2].R           /* External Channel Interrupt Mask Register */
#define SARADC_3_ECIMR3      SARADC_3.ECIMR[3].R           /* External Channel Interrupt Mask Register */
#define SARADC_3_ECDSR0      SARADC_3.ECDSR[0].R           /* External Channel DMA Select Register */
#define SARADC_3_ECDSR1      SARADC_3.ECDSR[1].R           /* External Channel DMA Select Register */
#define SARADC_3_ECDSR2      SARADC_3.ECDSR[2].R           /* External Channel DMA Select Register */
#define SARADC_3_ECDSR3      SARADC_3.ECDSR[3].R           /* External Channel DMA Select Register */
#define SARADC_3_ECNCMR0     SARADC_3.ECNCMR[0].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_3_ECNCMR1     SARADC_3.ECNCMR[1].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_3_ECNCMR2     SARADC_3.ECNCMR[2].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_3_ECNCMR3     SARADC_3.ECNCMR[3].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_3_ECJCMR0     SARADC_3.ECJCMR[0].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_3_ECJCMR1     SARADC_3.ECJCMR[1].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_3_ECJCMR2     SARADC_3.ECJCMR[2].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_3_ECJCMR3     SARADC_3.ECJCMR[3].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_3_ECWSELR0    SARADC_3.ECWSELR[0].R         /* External Channel Watchdog Selection Register */
#define SARADC_3_ECWSELR1    SARADC_3.ECWSELR[1].R         /* External Channel Watchdog Selection Register */
#define SARADC_3_ECWSELR2    SARADC_3.ECWSELR[2].R         /* External Channel Watchdog Selection Register */
#define SARADC_3_ECWSELR3    SARADC_3.ECWSELR[3].R         /* External Channel Watchdog Selection Register */
#define SARADC_3_ECWSELR4    SARADC_3.ECWSELR[4].R         /* External Channel Watchdog Selection Register */
#define SARADC_3_ECWSELR5    SARADC_3.ECWSELR[5].R         /* External Channel Watchdog Selection Register */
#define SARADC_3_ECWSELR6    SARADC_3.ECWSELR[6].R         /* External Channel Watchdog Selection Register */
#define SARADC_3_ECWSELR7    SARADC_3.ECWSELR[7].R         /* External Channel Watchdog Selection Register */
#define SARADC_3_ECWSELR8    SARADC_3.ECWSELR[8].R         /* External Channel Watchdog Selection Register */
#define SARADC_3_ECWSELR9    SARADC_3.ECWSELR[9].R         /* External Channel Watchdog Selection Register */
#define SARADC_3_ECWSELR10   SARADC_3.ECWSELR[10].R        /* External Channel Watchdog Selection Register */
#define SARADC_3_ECWSELR11   SARADC_3.ECWSELR[11].R        /* External Channel Watchdog Selection Register */
#define SARADC_3_ECWSELR12   SARADC_3.ECWSELR[12].R        /* External Channel Watchdog Selection Register */
#define SARADC_3_ECWSELR13   SARADC_3.ECWSELR[13].R        /* External Channel Watchdog Selection Register */
#define SARADC_3_ECWSELR14   SARADC_3.ECWSELR[14].R        /* External Channel Watchdog Selection Register */
#define SARADC_3_ECWSELR15   SARADC_3.ECWSELR[15].R        /* External Channel Watchdog Selection Register */
#define SARADC_3_ECWENR0     SARADC_3.ECWENR[0].R          /* External Channel Watchdog Enable Register */
#define SARADC_3_ECWENR1     SARADC_3.ECWENR[1].R          /* External Channel Watchdog Enable Register */
#define SARADC_3_ECWENR2     SARADC_3.ECWENR[2].R          /* External Channel Watchdog Enable Register */
#define SARADC_3_ECWENR3     SARADC_3.ECWENR[3].R          /* External Channel Watchdog Enable Register */
#define SARADC_3_ECAWORR0    SARADC_3.ECAWORR[0].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_3_ECAWORR1    SARADC_3.ECAWORR[1].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_3_ECAWORR2    SARADC_3.ECAWORR[2].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_3_ECAWORR3    SARADC_3.ECAWORR[3].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_3_ECMICR0     SARADC_3.ECMICR[0].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_3_ECMICR1     SARADC_3.ECMICR[1].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_3_ECMICR2     SARADC_3.ECMICR[2].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_3_ECMICR3     SARADC_3.ECMICR[3].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_3_ECDR128     SARADC_3.ECDR[0].R            /* External Channel Data Register */
#define SARADC_3_ECDR129     SARADC_3.ECDR[1].R            /* External Channel Data Register */
#define SARADC_3_ECDR130     SARADC_3.ECDR[2].R            /* External Channel Data Register */
#define SARADC_3_ECDR131     SARADC_3.ECDR[3].R            /* External Channel Data Register */
#define SARADC_3_ECDR132     SARADC_3.ECDR[4].R            /* External Channel Data Register */
#define SARADC_3_ECDR133     SARADC_3.ECDR[5].R            /* External Channel Data Register */
#define SARADC_3_ECDR134     SARADC_3.ECDR[6].R            /* External Channel Data Register */
#define SARADC_3_ECDR135     SARADC_3.ECDR[7].R            /* External Channel Data Register */
#define SARADC_3_ECDR136     SARADC_3.ECDR[8].R            /* External Channel Data Register */
#define SARADC_3_ECDR137     SARADC_3.ECDR[9].R            /* External Channel Data Register */
#define SARADC_3_ECDR138     SARADC_3.ECDR[10].R           /* External Channel Data Register */
#define SARADC_3_ECDR139     SARADC_3.ECDR[11].R           /* External Channel Data Register */
#define SARADC_3_ECDR140     SARADC_3.ECDR[12].R           /* External Channel Data Register */
#define SARADC_3_ECDR141     SARADC_3.ECDR[13].R           /* External Channel Data Register */
#define SARADC_3_ECDR142     SARADC_3.ECDR[14].R           /* External Channel Data Register */
#define SARADC_3_ECDR143     SARADC_3.ECDR[15].R           /* External Channel Data Register */
#define SARADC_3_ECDR144     SARADC_3.ECDR[16].R           /* External Channel Data Register */
#define SARADC_3_ECDR145     SARADC_3.ECDR[17].R           /* External Channel Data Register */
#define SARADC_3_ECDR146     SARADC_3.ECDR[18].R           /* External Channel Data Register */
#define SARADC_3_ECDR147     SARADC_3.ECDR[19].R           /* External Channel Data Register */
#define SARADC_3_ECDR148     SARADC_3.ECDR[20].R           /* External Channel Data Register */
#define SARADC_3_ECDR149     SARADC_3.ECDR[21].R           /* External Channel Data Register */
#define SARADC_3_ECDR150     SARADC_3.ECDR[22].R           /* External Channel Data Register */
#define SARADC_3_ECDR151     SARADC_3.ECDR[23].R           /* External Channel Data Register */
#define SARADC_3_ECDR152     SARADC_3.ECDR[24].R           /* External Channel Data Register */
#define SARADC_3_ECDR153     SARADC_3.ECDR[25].R           /* External Channel Data Register */
#define SARADC_3_ECDR154     SARADC_3.ECDR[26].R           /* External Channel Data Register */
#define SARADC_3_ECDR155     SARADC_3.ECDR[27].R           /* External Channel Data Register */
#define SARADC_3_ECDR156     SARADC_3.ECDR[28].R           /* External Channel Data Register */
#define SARADC_3_ECDR157     SARADC_3.ECDR[29].R           /* External Channel Data Register */
#define SARADC_3_ECDR158     SARADC_3.ECDR[30].R           /* External Channel Data Register */
#define SARADC_3_ECDR159     SARADC_3.ECDR[31].R           /* External Channel Data Register */
#define SARADC_3_ECDR160     SARADC_3.ECDR[32].R           /* External Channel Data Register */
#define SARADC_3_ECDR161     SARADC_3.ECDR[33].R           /* External Channel Data Register */
#define SARADC_3_ECDR162     SARADC_3.ECDR[34].R           /* External Channel Data Register */
#define SARADC_3_ECDR163     SARADC_3.ECDR[35].R           /* External Channel Data Register */
#define SARADC_3_ECDR164     SARADC_3.ECDR[36].R           /* External Channel Data Register */
#define SARADC_3_ECDR165     SARADC_3.ECDR[37].R           /* External Channel Data Register */
#define SARADC_3_ECDR166     SARADC_3.ECDR[38].R           /* External Channel Data Register */
#define SARADC_3_ECDR167     SARADC_3.ECDR[39].R           /* External Channel Data Register */
#define SARADC_3_ECDR168     SARADC_3.ECDR[40].R           /* External Channel Data Register */
#define SARADC_3_ECDR169     SARADC_3.ECDR[41].R           /* External Channel Data Register */
#define SARADC_3_ECDR170     SARADC_3.ECDR[42].R           /* External Channel Data Register */
#define SARADC_3_ECDR171     SARADC_3.ECDR[43].R           /* External Channel Data Register */
#define SARADC_3_ECDR172     SARADC_3.ECDR[44].R           /* External Channel Data Register */
#define SARADC_3_ECDR173     SARADC_3.ECDR[45].R           /* External Channel Data Register */
#define SARADC_3_ECDR174     SARADC_3.ECDR[46].R           /* External Channel Data Register */
#define SARADC_3_ECDR175     SARADC_3.ECDR[47].R           /* External Channel Data Register */
#define SARADC_3_ECDR176     SARADC_3.ECDR[48].R           /* External Channel Data Register */
#define SARADC_3_ECDR177     SARADC_3.ECDR[49].R           /* External Channel Data Register */
#define SARADC_3_ECDR178     SARADC_3.ECDR[50].R           /* External Channel Data Register */
#define SARADC_3_ECDR179     SARADC_3.ECDR[51].R           /* External Channel Data Register */
#define SARADC_3_ECDR180     SARADC_3.ECDR[52].R           /* External Channel Data Register */
#define SARADC_3_ECDR181     SARADC_3.ECDR[53].R           /* External Channel Data Register */
#define SARADC_3_ECDR182     SARADC_3.ECDR[54].R           /* External Channel Data Register */
#define SARADC_3_ECDR183     SARADC_3.ECDR[55].R           /* External Channel Data Register */
#define SARADC_3_ECDR184     SARADC_3.ECDR[56].R           /* External Channel Data Register */
#define SARADC_3_ECDR185     SARADC_3.ECDR[57].R           /* External Channel Data Register */
#define SARADC_3_ECDR186     SARADC_3.ECDR[58].R           /* External Channel Data Register */
#define SARADC_3_ECDR187     SARADC_3.ECDR[59].R           /* External Channel Data Register */
#define SARADC_3_ECDR188     SARADC_3.ECDR[60].R           /* External Channel Data Register */
#define SARADC_3_ECDR189     SARADC_3.ECDR[61].R           /* External Channel Data Register */
#define SARADC_3_ECDR190     SARADC_3.ECDR[62].R           /* External Channel Data Register */
#define SARADC_3_ECDR191     SARADC_3.ECDR[63].R           /* External Channel Data Register */
#define SARADC_3_ECDR192     SARADC_3.ECDR[64].R           /* External Channel Data Register */
#define SARADC_3_ECDR193     SARADC_3.ECDR[65].R           /* External Channel Data Register */
#define SARADC_3_ECDR194     SARADC_3.ECDR[66].R           /* External Channel Data Register */
#define SARADC_3_ECDR195     SARADC_3.ECDR[67].R           /* External Channel Data Register */
#define SARADC_3_ECDR196     SARADC_3.ECDR[68].R           /* External Channel Data Register */
#define SARADC_3_ECDR197     SARADC_3.ECDR[69].R           /* External Channel Data Register */
#define SARADC_3_ECDR198     SARADC_3.ECDR[70].R           /* External Channel Data Register */
#define SARADC_3_ECDR199     SARADC_3.ECDR[71].R           /* External Channel Data Register */
#define SARADC_3_ECDR200     SARADC_3.ECDR[72].R           /* External Channel Data Register */
#define SARADC_3_ECDR201     SARADC_3.ECDR[73].R           /* External Channel Data Register */
#define SARADC_3_ECDR202     SARADC_3.ECDR[74].R           /* External Channel Data Register */
#define SARADC_3_ECDR203     SARADC_3.ECDR[75].R           /* External Channel Data Register */
#define SARADC_3_ECDR204     SARADC_3.ECDR[76].R           /* External Channel Data Register */
#define SARADC_3_ECDR205     SARADC_3.ECDR[77].R           /* External Channel Data Register */
#define SARADC_3_ECDR206     SARADC_3.ECDR[78].R           /* External Channel Data Register */
#define SARADC_3_ECDR207     SARADC_3.ECDR[79].R           /* External Channel Data Register */
#define SARADC_3_ECDR208     SARADC_3.ECDR[80].R           /* External Channel Data Register */
#define SARADC_3_ECDR209     SARADC_3.ECDR[81].R           /* External Channel Data Register */
#define SARADC_3_ECDR210     SARADC_3.ECDR[82].R           /* External Channel Data Register */
#define SARADC_3_ECDR211     SARADC_3.ECDR[83].R           /* External Channel Data Register */
#define SARADC_3_ECDR212     SARADC_3.ECDR[84].R           /* External Channel Data Register */
#define SARADC_3_ECDR213     SARADC_3.ECDR[85].R           /* External Channel Data Register */
#define SARADC_3_ECDR214     SARADC_3.ECDR[86].R           /* External Channel Data Register */
#define SARADC_3_ECDR215     SARADC_3.ECDR[87].R           /* External Channel Data Register */
#define SARADC_3_ECDR216     SARADC_3.ECDR[88].R           /* External Channel Data Register */
#define SARADC_3_ECDR217     SARADC_3.ECDR[89].R           /* External Channel Data Register */
#define SARADC_3_ECDR218     SARADC_3.ECDR[90].R           /* External Channel Data Register */
#define SARADC_3_ECDR219     SARADC_3.ECDR[91].R           /* External Channel Data Register */
#define SARADC_3_ECDR220     SARADC_3.ECDR[92].R           /* External Channel Data Register */
#define SARADC_3_ECDR221     SARADC_3.ECDR[93].R           /* External Channel Data Register */
#define SARADC_3_ECDR222     SARADC_3.ECDR[94].R           /* External Channel Data Register */
#define SARADC_3_ECDR223     SARADC_3.ECDR[95].R           /* External Channel Data Register */
#define SARADC_3_ECDR224     SARADC_3.ECDR[96].R           /* External Channel Data Register */
#define SARADC_3_ECDR225     SARADC_3.ECDR[97].R           /* External Channel Data Register */
#define SARADC_3_ECDR226     SARADC_3.ECDR[98].R           /* External Channel Data Register */
#define SARADC_3_ECDR227     SARADC_3.ECDR[99].R           /* External Channel Data Register */
#define SARADC_3_ECDR228     SARADC_3.ECDR[100].R          /* External Channel Data Register */
#define SARADC_3_ECDR229     SARADC_3.ECDR[101].R          /* External Channel Data Register */
#define SARADC_3_ECDR230     SARADC_3.ECDR[102].R          /* External Channel Data Register */
#define SARADC_3_ECDR231     SARADC_3.ECDR[103].R          /* External Channel Data Register */
#define SARADC_3_ECDR232     SARADC_3.ECDR[104].R          /* External Channel Data Register */
#define SARADC_3_ECDR233     SARADC_3.ECDR[105].R          /* External Channel Data Register */
#define SARADC_3_ECDR234     SARADC_3.ECDR[106].R          /* External Channel Data Register */
#define SARADC_3_ECDR235     SARADC_3.ECDR[107].R          /* External Channel Data Register */
#define SARADC_3_ECDR236     SARADC_3.ECDR[108].R          /* External Channel Data Register */
#define SARADC_3_ECDR237     SARADC_3.ECDR[109].R          /* External Channel Data Register */
#define SARADC_3_ECDR238     SARADC_3.ECDR[110].R          /* External Channel Data Register */
#define SARADC_3_ECDR239     SARADC_3.ECDR[111].R          /* External Channel Data Register */
#define SARADC_3_ECDR240     SARADC_3.ECDR[112].R          /* External Channel Data Register */
#define SARADC_3_ECDR241     SARADC_3.ECDR[113].R          /* External Channel Data Register */
#define SARADC_3_ECDR242     SARADC_3.ECDR[114].R          /* External Channel Data Register */
#define SARADC_3_ECDR243     SARADC_3.ECDR[115].R          /* External Channel Data Register */
#define SARADC_3_ECDR244     SARADC_3.ECDR[116].R          /* External Channel Data Register */
#define SARADC_3_ECDR245     SARADC_3.ECDR[117].R          /* External Channel Data Register */
#define SARADC_3_ECDR246     SARADC_3.ECDR[118].R          /* External Channel Data Register */
#define SARADC_3_ECDR247     SARADC_3.ECDR[119].R          /* External Channel Data Register */
#define SARADC_3_ECDR248     SARADC_3.ECDR[120].R          /* External Channel Data Register */
#define SARADC_3_ECDR249     SARADC_3.ECDR[121].R          /* External Channel Data Register */
#define SARADC_3_ECDR250     SARADC_3.ECDR[122].R          /* External Channel Data Register */
#define SARADC_3_ECDR251     SARADC_3.ECDR[123].R          /* External Channel Data Register */
#define SARADC_3_ECDR252     SARADC_3.ECDR[124].R          /* External Channel Data Register */
#define SARADC_3_ECDR253     SARADC_3.ECDR[125].R          /* External Channel Data Register */
#define SARADC_3_ECDR254     SARADC_3.ECDR[126].R          /* External Channel Data Register */
#define SARADC_3_ECDR255     SARADC_3.ECDR[127].R          /* External Channel Data Register */

/* SARADC */
#define SARADC_4_MCR         SARADC_4.MCR.R                /* Main Configuration Register */
#define SARADC_4_MSR         SARADC_4.MSR.R                /* Main Status Register */
#define SARADC_4_ISR         SARADC_4.ISR.R                /* Interrupt Status Register */
#define SARADC_4_ICIPR0      SARADC_4.ICIPR[0].R           /* Internal channel Interrupt Pending Register */
#define SARADC_4_ICIPR1      SARADC_4.ICIPR[1].R           /* Internal channel Interrupt Pending Register */
#define SARADC_4_ICIPR2      SARADC_4.ICIPR[2].R           /* Internal channel Interrupt Pending Register */
#define SARADC_4_IMR         SARADC_4.IMR.R                /* Interrupt Mask Register */
#define SARADC_4_ICIMR0      SARADC_4.ICIMR[0].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_4_ICIMR1      SARADC_4.ICIMR[1].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_4_ICIMR2      SARADC_4.ICIMR[2].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_4_WTISR       SARADC_4.WTISR.R              /* Watchdog Threshold Interrupt Status Register */
#define SARADC_4_WTIMR       SARADC_4.WTIMR.R              /* Watchdog Threshold Interrupt Mask Register */
#define SARADC_4_DMAE        SARADC_4.DMAE.R               /* DMA Enable Register */
#define SARADC_4_ICDSR0      SARADC_4.ICDSR[0].R           /* Internal Channel DMA Select Register */
#define SARADC_4_ICDSR1      SARADC_4.ICDSR[1].R           /* Internal Channel DMA Select Register */
#define SARADC_4_ICDSR2      SARADC_4.ICDSR[2].R           /* Internal Channel DMA Select Register */
#define SARADC_4_WTHRHLR0    SARADC_4.WTHRHLR[0].R         /* Watchdog Threshold Register */
#define SARADC_4_WTHRHLR1    SARADC_4.WTHRHLR[1].R         /* Watchdog Threshold Register */
#define SARADC_4_WTHRHLR2    SARADC_4.WTHRHLR[2].R         /* Watchdog Threshold Register */
#define SARADC_4_WTHRHLR3    SARADC_4.WTHRHLR[3].R         /* Watchdog Threshold Register */
#define SARADC_4_CTR0        SARADC_4.CTR[0].R             /* Conversion Timing Register */
#define SARADC_4_CTR1        SARADC_4.CTR[1].R             /* Conversion Timing Register */
#define SARADC_4_CTR2        SARADC_4.CTR[2].R             /* Conversion Timing Register */
#define SARADC_4_CTR3        SARADC_4.CTR[3].R             /* Conversion Timing Register */
#define SARADC_4_ICNCMR0     SARADC_4.ICNCMR[0].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_4_ICNCMR1     SARADC_4.ICNCMR[1].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_4_ICNCMR2     SARADC_4.ICNCMR[2].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_4_ICJCMR0     SARADC_4.ICJCMR[0].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_4_ICJCMR1     SARADC_4.ICJCMR[1].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_4_ICJCMR2     SARADC_4.ICJCMR[2].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_4_PDEDR       SARADC_4.PDEDR.R              /* Power Down Exit Delay Register */
#define SARADC_4_ICDR0       SARADC_4.ICDR[0].R            /* Internal Channel Data Register */
#define SARADC_4_ICDR1       SARADC_4.ICDR[1].R            /* Internal Channel Data Register */
#define SARADC_4_ICDR2       SARADC_4.ICDR[2].R            /* Internal Channel Data Register */
#define SARADC_4_ICDR3       SARADC_4.ICDR[3].R            /* Internal Channel Data Register */
#define SARADC_4_ICDR4       SARADC_4.ICDR[4].R            /* Internal Channel Data Register */
#define SARADC_4_ICDR5       SARADC_4.ICDR[5].R            /* Internal Channel Data Register */
#define SARADC_4_ICDR6       SARADC_4.ICDR[6].R            /* Internal Channel Data Register */
#define SARADC_4_ICDR7       SARADC_4.ICDR[7].R            /* Internal Channel Data Register */
#define SARADC_4_ICDR8       SARADC_4.ICDR[8].R            /* Internal Channel Data Register */
#define SARADC_4_ICDR9       SARADC_4.ICDR[9].R            /* Internal Channel Data Register */
#define SARADC_4_ICDR10      SARADC_4.ICDR[10].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR11      SARADC_4.ICDR[11].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR12      SARADC_4.ICDR[12].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR13      SARADC_4.ICDR[13].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR14      SARADC_4.ICDR[14].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR15      SARADC_4.ICDR[15].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR16      SARADC_4.ICDR[16].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR17      SARADC_4.ICDR[17].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR18      SARADC_4.ICDR[18].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR19      SARADC_4.ICDR[19].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR20      SARADC_4.ICDR[20].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR21      SARADC_4.ICDR[21].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR22      SARADC_4.ICDR[22].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR23      SARADC_4.ICDR[23].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR24      SARADC_4.ICDR[24].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR25      SARADC_4.ICDR[25].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR26      SARADC_4.ICDR[26].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR27      SARADC_4.ICDR[27].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR28      SARADC_4.ICDR[28].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR29      SARADC_4.ICDR[29].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR30      SARADC_4.ICDR[30].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR31      SARADC_4.ICDR[31].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR32      SARADC_4.ICDR[32].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR33      SARADC_4.ICDR[33].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR34      SARADC_4.ICDR[34].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR35      SARADC_4.ICDR[35].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR36      SARADC_4.ICDR[36].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR37      SARADC_4.ICDR[37].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR38      SARADC_4.ICDR[38].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR39      SARADC_4.ICDR[39].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR40      SARADC_4.ICDR[40].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR41      SARADC_4.ICDR[41].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR42      SARADC_4.ICDR[42].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR43      SARADC_4.ICDR[43].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR44      SARADC_4.ICDR[44].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR45      SARADC_4.ICDR[45].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR46      SARADC_4.ICDR[46].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR47      SARADC_4.ICDR[47].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR48      SARADC_4.ICDR[48].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR49      SARADC_4.ICDR[49].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR50      SARADC_4.ICDR[50].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR51      SARADC_4.ICDR[51].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR52      SARADC_4.ICDR[52].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR53      SARADC_4.ICDR[53].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR54      SARADC_4.ICDR[54].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR55      SARADC_4.ICDR[55].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR56      SARADC_4.ICDR[56].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR57      SARADC_4.ICDR[57].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR58      SARADC_4.ICDR[58].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR59      SARADC_4.ICDR[59].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR60      SARADC_4.ICDR[60].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR61      SARADC_4.ICDR[61].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR62      SARADC_4.ICDR[62].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR63      SARADC_4.ICDR[63].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR64      SARADC_4.ICDR[64].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR65      SARADC_4.ICDR[65].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR66      SARADC_4.ICDR[66].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR67      SARADC_4.ICDR[67].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR68      SARADC_4.ICDR[68].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR69      SARADC_4.ICDR[69].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR70      SARADC_4.ICDR[70].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR71      SARADC_4.ICDR[71].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR72      SARADC_4.ICDR[72].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR73      SARADC_4.ICDR[73].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR74      SARADC_4.ICDR[74].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR75      SARADC_4.ICDR[75].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR76      SARADC_4.ICDR[76].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR77      SARADC_4.ICDR[77].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR78      SARADC_4.ICDR[78].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR79      SARADC_4.ICDR[79].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR80      SARADC_4.ICDR[80].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR81      SARADC_4.ICDR[81].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR82      SARADC_4.ICDR[82].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR83      SARADC_4.ICDR[83].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR84      SARADC_4.ICDR[84].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR85      SARADC_4.ICDR[85].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR86      SARADC_4.ICDR[86].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR87      SARADC_4.ICDR[87].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR88      SARADC_4.ICDR[88].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR89      SARADC_4.ICDR[89].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR90      SARADC_4.ICDR[90].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR91      SARADC_4.ICDR[91].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR92      SARADC_4.ICDR[92].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR93      SARADC_4.ICDR[93].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR94      SARADC_4.ICDR[94].R           /* Internal Channel Data Register */
#define SARADC_4_ICDR95      SARADC_4.ICDR[95].R           /* Internal Channel Data Register */
#define SARADC_4_ICWSELR0    SARADC_4.ICWSELR[0].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_4_ICWSELR1    SARADC_4.ICWSELR[1].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_4_ICWSELR2    SARADC_4.ICWSELR[2].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_4_ICWSELR3    SARADC_4.ICWSELR[3].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_4_ICWSELR4    SARADC_4.ICWSELR[4].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_4_ICWSELR5    SARADC_4.ICWSELR[5].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_4_ICWSELR6    SARADC_4.ICWSELR[6].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_4_ICWSELR7    SARADC_4.ICWSELR[7].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_4_ICWSELR8    SARADC_4.ICWSELR[8].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_4_ICWSELR9    SARADC_4.ICWSELR[9].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_4_ICWSELR10   SARADC_4.ICWSELR[10].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_4_ICWSELR11   SARADC_4.ICWSELR[11].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_4_ICWENR0     SARADC_4.ICWENR[0].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_4_ICWENR1     SARADC_4.ICWENR[1].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_4_ICWENR2     SARADC_4.ICWENR[2].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_4_ICAWORR0    SARADC_4.ICAWORR[0].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_4_ICAWORR1    SARADC_4.ICAWORR[1].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_4_ICAWORR2    SARADC_4.ICAWORR[2].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_4_TCIPR       SARADC_4.TCIPR.R              /* Test Channel Interrupt Pending Register */
#define SARADC_4_TCIMR       SARADC_4.TCIMR.R              /* Test Channel Interrupt Mask Register */
#define SARADC_4_TCDSR       SARADC_4.TCDSR.R              /* Test Channel DMA Select Register */
#define SARADC_4_TCNCMR      SARADC_4.TCNCMR.R             /* Test Channel Normal Conversion Mask Register */
#define SARADC_4_TCJCMR      SARADC_4.TCJCMR.R             /* Test Channel Injected Conversion Mask Register */
#define SARADC_4_TCWSELR0    SARADC_4.TCWSELR[0].R         /* Test Channel Watchdog Selection Register */
#define SARADC_4_TCWSELR1    SARADC_4.TCWSELR[1].R         /* Test Channel Watchdog Selection Register */
#define SARADC_4_TCWSELR2    SARADC_4.TCWSELR[2].R         /* Test Channel Watchdog Selection Register */
#define SARADC_4_TCWSELR3    SARADC_4.TCWSELR[3].R         /* Test Channel Watchdog Selection Register */
#define SARADC_4_TCWENR      SARADC_4.TCWENR.R             /* Test Channel Watchdog Enable Register */
#define SARADC_4_TCAWORR     SARADC_4.TCAWORR.R            /* Test Channel Analog Watchdog Out of Range Register */
#define SARADC_4_TCCAPR0     SARADC_4.TCCAPR[0].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_4_TCCAPR1     SARADC_4.TCCAPR[1].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_4_TCCAPR2     SARADC_4.TCCAPR[2].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_4_TCCAPR3     SARADC_4.TCCAPR[3].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_4_TCCAPR4     SARADC_4.TCCAPR[4].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_4_TCCAPR5     SARADC_4.TCCAPR[5].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_4_TCCAPR6     SARADC_4.TCCAPR[6].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_4_TCCAPR7     SARADC_4.TCCAPR[7].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_4_TCDR96      SARADC_4.TCDR[0].R            /* Test Channel Data Register */
#define SARADC_4_TCDR97      SARADC_4.TCDR[1].R            /* Test Channel Data Register */
#define SARADC_4_TCDR98      SARADC_4.TCDR[2].R            /* Test Channel Data Register */
#define SARADC_4_TCDR99      SARADC_4.TCDR[3].R            /* Test Channel Data Register */
#define SARADC_4_TCDR100     SARADC_4.TCDR[4].R            /* Test Channel Data Register */
#define SARADC_4_TCDR101     SARADC_4.TCDR[5].R            /* Test Channel Data Register */
#define SARADC_4_TCDR102     SARADC_4.TCDR[6].R            /* Test Channel Data Register */
#define SARADC_4_TCDR103     SARADC_4.TCDR[7].R            /* Test Channel Data Register */
#define SARADC_4_TCDR104     SARADC_4.TCDR[8].R            /* Test Channel Data Register */
#define SARADC_4_TCDR105     SARADC_4.TCDR[9].R            /* Test Channel Data Register */
#define SARADC_4_TCDR106     SARADC_4.TCDR[10].R           /* Test Channel Data Register */
#define SARADC_4_TCDR107     SARADC_4.TCDR[11].R           /* Test Channel Data Register */
#define SARADC_4_TCDR108     SARADC_4.TCDR[12].R           /* Test Channel Data Register */
#define SARADC_4_TCDR109     SARADC_4.TCDR[13].R           /* Test Channel Data Register */
#define SARADC_4_TCDR110     SARADC_4.TCDR[14].R           /* Test Channel Data Register */
#define SARADC_4_TCDR111     SARADC_4.TCDR[15].R           /* Test Channel Data Register */
#define SARADC_4_TCDR112     SARADC_4.TCDR[16].R           /* Test Channel Data Register */
#define SARADC_4_TCDR113     SARADC_4.TCDR[17].R           /* Test Channel Data Register */
#define SARADC_4_TCDR114     SARADC_4.TCDR[18].R           /* Test Channel Data Register */
#define SARADC_4_TCDR115     SARADC_4.TCDR[19].R           /* Test Channel Data Register */
#define SARADC_4_TCDR116     SARADC_4.TCDR[20].R           /* Test Channel Data Register */
#define SARADC_4_TCDR117     SARADC_4.TCDR[21].R           /* Test Channel Data Register */
#define SARADC_4_TCDR118     SARADC_4.TCDR[22].R           /* Test Channel Data Register */
#define SARADC_4_TCDR119     SARADC_4.TCDR[23].R           /* Test Channel Data Register */
#define SARADC_4_TCDR120     SARADC_4.TCDR[24].R           /* Test Channel Data Register */
#define SARADC_4_TCDR121     SARADC_4.TCDR[25].R           /* Test Channel Data Register */
#define SARADC_4_TCDR122     SARADC_4.TCDR[26].R           /* Test Channel Data Register */
#define SARADC_4_TCDR123     SARADC_4.TCDR[27].R           /* Test Channel Data Register */
#define SARADC_4_TCDR124     SARADC_4.TCDR[28].R           /* Test Channel Data Register */
#define SARADC_4_TCDR125     SARADC_4.TCDR[29].R           /* Test Channel Data Register */
#define SARADC_4_TCDR126     SARADC_4.TCDR[30].R           /* Test Channel Data Register */
#define SARADC_4_TCDR127     SARADC_4.TCDR[31].R           /* Test Channel Data Register */
#define SARADC_4_ECDSDR      SARADC_4.ECDSDR.R             /* External Channel Decode Signals Delay Register */
#define SARADC_4_ECIPR0      SARADC_4.ECIPR[0].R           /* External Channel Interrupt Pending Register */
#define SARADC_4_ECIPR1      SARADC_4.ECIPR[1].R           /* External Channel Interrupt Pending Register */
#define SARADC_4_ECIPR2      SARADC_4.ECIPR[2].R           /* External Channel Interrupt Pending Register */
#define SARADC_4_ECIPR3      SARADC_4.ECIPR[3].R           /* External Channel Interrupt Pending Register */
#define SARADC_4_ECIMR0      SARADC_4.ECIMR[0].R           /* External Channel Interrupt Mask Register */
#define SARADC_4_ECIMR1      SARADC_4.ECIMR[1].R           /* External Channel Interrupt Mask Register */
#define SARADC_4_ECIMR2      SARADC_4.ECIMR[2].R           /* External Channel Interrupt Mask Register */
#define SARADC_4_ECIMR3      SARADC_4.ECIMR[3].R           /* External Channel Interrupt Mask Register */
#define SARADC_4_ECDSR0      SARADC_4.ECDSR[0].R           /* External Channel DMA Select Register */
#define SARADC_4_ECDSR1      SARADC_4.ECDSR[1].R           /* External Channel DMA Select Register */
#define SARADC_4_ECDSR2      SARADC_4.ECDSR[2].R           /* External Channel DMA Select Register */
#define SARADC_4_ECDSR3      SARADC_4.ECDSR[3].R           /* External Channel DMA Select Register */
#define SARADC_4_ECNCMR0     SARADC_4.ECNCMR[0].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_4_ECNCMR1     SARADC_4.ECNCMR[1].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_4_ECNCMR2     SARADC_4.ECNCMR[2].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_4_ECNCMR3     SARADC_4.ECNCMR[3].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_4_ECJCMR0     SARADC_4.ECJCMR[0].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_4_ECJCMR1     SARADC_4.ECJCMR[1].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_4_ECJCMR2     SARADC_4.ECJCMR[2].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_4_ECJCMR3     SARADC_4.ECJCMR[3].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_4_ECWSELR0    SARADC_4.ECWSELR[0].R         /* External Channel Watchdog Selection Register */
#define SARADC_4_ECWSELR1    SARADC_4.ECWSELR[1].R         /* External Channel Watchdog Selection Register */
#define SARADC_4_ECWSELR2    SARADC_4.ECWSELR[2].R         /* External Channel Watchdog Selection Register */
#define SARADC_4_ECWSELR3    SARADC_4.ECWSELR[3].R         /* External Channel Watchdog Selection Register */
#define SARADC_4_ECWSELR4    SARADC_4.ECWSELR[4].R         /* External Channel Watchdog Selection Register */
#define SARADC_4_ECWSELR5    SARADC_4.ECWSELR[5].R         /* External Channel Watchdog Selection Register */
#define SARADC_4_ECWSELR6    SARADC_4.ECWSELR[6].R         /* External Channel Watchdog Selection Register */
#define SARADC_4_ECWSELR7    SARADC_4.ECWSELR[7].R         /* External Channel Watchdog Selection Register */
#define SARADC_4_ECWSELR8    SARADC_4.ECWSELR[8].R         /* External Channel Watchdog Selection Register */
#define SARADC_4_ECWSELR9    SARADC_4.ECWSELR[9].R         /* External Channel Watchdog Selection Register */
#define SARADC_4_ECWSELR10   SARADC_4.ECWSELR[10].R        /* External Channel Watchdog Selection Register */
#define SARADC_4_ECWSELR11   SARADC_4.ECWSELR[11].R        /* External Channel Watchdog Selection Register */
#define SARADC_4_ECWSELR12   SARADC_4.ECWSELR[12].R        /* External Channel Watchdog Selection Register */
#define SARADC_4_ECWSELR13   SARADC_4.ECWSELR[13].R        /* External Channel Watchdog Selection Register */
#define SARADC_4_ECWSELR14   SARADC_4.ECWSELR[14].R        /* External Channel Watchdog Selection Register */
#define SARADC_4_ECWSELR15   SARADC_4.ECWSELR[15].R        /* External Channel Watchdog Selection Register */
#define SARADC_4_ECWENR0     SARADC_4.ECWENR[0].R          /* External Channel Watchdog Enable Register */
#define SARADC_4_ECWENR1     SARADC_4.ECWENR[1].R          /* External Channel Watchdog Enable Register */
#define SARADC_4_ECWENR2     SARADC_4.ECWENR[2].R          /* External Channel Watchdog Enable Register */
#define SARADC_4_ECWENR3     SARADC_4.ECWENR[3].R          /* External Channel Watchdog Enable Register */
#define SARADC_4_ECAWORR0    SARADC_4.ECAWORR[0].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_4_ECAWORR1    SARADC_4.ECAWORR[1].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_4_ECAWORR2    SARADC_4.ECAWORR[2].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_4_ECAWORR3    SARADC_4.ECAWORR[3].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_4_ECMICR0     SARADC_4.ECMICR[0].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_4_ECMICR1     SARADC_4.ECMICR[1].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_4_ECMICR2     SARADC_4.ECMICR[2].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_4_ECMICR3     SARADC_4.ECMICR[3].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_4_ECDR128     SARADC_4.ECDR[0].R            /* External Channel Data Register */
#define SARADC_4_ECDR129     SARADC_4.ECDR[1].R            /* External Channel Data Register */
#define SARADC_4_ECDR130     SARADC_4.ECDR[2].R            /* External Channel Data Register */
#define SARADC_4_ECDR131     SARADC_4.ECDR[3].R            /* External Channel Data Register */
#define SARADC_4_ECDR132     SARADC_4.ECDR[4].R            /* External Channel Data Register */
#define SARADC_4_ECDR133     SARADC_4.ECDR[5].R            /* External Channel Data Register */
#define SARADC_4_ECDR134     SARADC_4.ECDR[6].R            /* External Channel Data Register */
#define SARADC_4_ECDR135     SARADC_4.ECDR[7].R            /* External Channel Data Register */
#define SARADC_4_ECDR136     SARADC_4.ECDR[8].R            /* External Channel Data Register */
#define SARADC_4_ECDR137     SARADC_4.ECDR[9].R            /* External Channel Data Register */
#define SARADC_4_ECDR138     SARADC_4.ECDR[10].R           /* External Channel Data Register */
#define SARADC_4_ECDR139     SARADC_4.ECDR[11].R           /* External Channel Data Register */
#define SARADC_4_ECDR140     SARADC_4.ECDR[12].R           /* External Channel Data Register */
#define SARADC_4_ECDR141     SARADC_4.ECDR[13].R           /* External Channel Data Register */
#define SARADC_4_ECDR142     SARADC_4.ECDR[14].R           /* External Channel Data Register */
#define SARADC_4_ECDR143     SARADC_4.ECDR[15].R           /* External Channel Data Register */
#define SARADC_4_ECDR144     SARADC_4.ECDR[16].R           /* External Channel Data Register */
#define SARADC_4_ECDR145     SARADC_4.ECDR[17].R           /* External Channel Data Register */
#define SARADC_4_ECDR146     SARADC_4.ECDR[18].R           /* External Channel Data Register */
#define SARADC_4_ECDR147     SARADC_4.ECDR[19].R           /* External Channel Data Register */
#define SARADC_4_ECDR148     SARADC_4.ECDR[20].R           /* External Channel Data Register */
#define SARADC_4_ECDR149     SARADC_4.ECDR[21].R           /* External Channel Data Register */
#define SARADC_4_ECDR150     SARADC_4.ECDR[22].R           /* External Channel Data Register */
#define SARADC_4_ECDR151     SARADC_4.ECDR[23].R           /* External Channel Data Register */
#define SARADC_4_ECDR152     SARADC_4.ECDR[24].R           /* External Channel Data Register */
#define SARADC_4_ECDR153     SARADC_4.ECDR[25].R           /* External Channel Data Register */
#define SARADC_4_ECDR154     SARADC_4.ECDR[26].R           /* External Channel Data Register */
#define SARADC_4_ECDR155     SARADC_4.ECDR[27].R           /* External Channel Data Register */
#define SARADC_4_ECDR156     SARADC_4.ECDR[28].R           /* External Channel Data Register */
#define SARADC_4_ECDR157     SARADC_4.ECDR[29].R           /* External Channel Data Register */
#define SARADC_4_ECDR158     SARADC_4.ECDR[30].R           /* External Channel Data Register */
#define SARADC_4_ECDR159     SARADC_4.ECDR[31].R           /* External Channel Data Register */
#define SARADC_4_ECDR160     SARADC_4.ECDR[32].R           /* External Channel Data Register */
#define SARADC_4_ECDR161     SARADC_4.ECDR[33].R           /* External Channel Data Register */
#define SARADC_4_ECDR162     SARADC_4.ECDR[34].R           /* External Channel Data Register */
#define SARADC_4_ECDR163     SARADC_4.ECDR[35].R           /* External Channel Data Register */
#define SARADC_4_ECDR164     SARADC_4.ECDR[36].R           /* External Channel Data Register */
#define SARADC_4_ECDR165     SARADC_4.ECDR[37].R           /* External Channel Data Register */
#define SARADC_4_ECDR166     SARADC_4.ECDR[38].R           /* External Channel Data Register */
#define SARADC_4_ECDR167     SARADC_4.ECDR[39].R           /* External Channel Data Register */
#define SARADC_4_ECDR168     SARADC_4.ECDR[40].R           /* External Channel Data Register */
#define SARADC_4_ECDR169     SARADC_4.ECDR[41].R           /* External Channel Data Register */
#define SARADC_4_ECDR170     SARADC_4.ECDR[42].R           /* External Channel Data Register */
#define SARADC_4_ECDR171     SARADC_4.ECDR[43].R           /* External Channel Data Register */
#define SARADC_4_ECDR172     SARADC_4.ECDR[44].R           /* External Channel Data Register */
#define SARADC_4_ECDR173     SARADC_4.ECDR[45].R           /* External Channel Data Register */
#define SARADC_4_ECDR174     SARADC_4.ECDR[46].R           /* External Channel Data Register */
#define SARADC_4_ECDR175     SARADC_4.ECDR[47].R           /* External Channel Data Register */
#define SARADC_4_ECDR176     SARADC_4.ECDR[48].R           /* External Channel Data Register */
#define SARADC_4_ECDR177     SARADC_4.ECDR[49].R           /* External Channel Data Register */
#define SARADC_4_ECDR178     SARADC_4.ECDR[50].R           /* External Channel Data Register */
#define SARADC_4_ECDR179     SARADC_4.ECDR[51].R           /* External Channel Data Register */
#define SARADC_4_ECDR180     SARADC_4.ECDR[52].R           /* External Channel Data Register */
#define SARADC_4_ECDR181     SARADC_4.ECDR[53].R           /* External Channel Data Register */
#define SARADC_4_ECDR182     SARADC_4.ECDR[54].R           /* External Channel Data Register */
#define SARADC_4_ECDR183     SARADC_4.ECDR[55].R           /* External Channel Data Register */
#define SARADC_4_ECDR184     SARADC_4.ECDR[56].R           /* External Channel Data Register */
#define SARADC_4_ECDR185     SARADC_4.ECDR[57].R           /* External Channel Data Register */
#define SARADC_4_ECDR186     SARADC_4.ECDR[58].R           /* External Channel Data Register */
#define SARADC_4_ECDR187     SARADC_4.ECDR[59].R           /* External Channel Data Register */
#define SARADC_4_ECDR188     SARADC_4.ECDR[60].R           /* External Channel Data Register */
#define SARADC_4_ECDR189     SARADC_4.ECDR[61].R           /* External Channel Data Register */
#define SARADC_4_ECDR190     SARADC_4.ECDR[62].R           /* External Channel Data Register */
#define SARADC_4_ECDR191     SARADC_4.ECDR[63].R           /* External Channel Data Register */
#define SARADC_4_ECDR192     SARADC_4.ECDR[64].R           /* External Channel Data Register */
#define SARADC_4_ECDR193     SARADC_4.ECDR[65].R           /* External Channel Data Register */
#define SARADC_4_ECDR194     SARADC_4.ECDR[66].R           /* External Channel Data Register */
#define SARADC_4_ECDR195     SARADC_4.ECDR[67].R           /* External Channel Data Register */
#define SARADC_4_ECDR196     SARADC_4.ECDR[68].R           /* External Channel Data Register */
#define SARADC_4_ECDR197     SARADC_4.ECDR[69].R           /* External Channel Data Register */
#define SARADC_4_ECDR198     SARADC_4.ECDR[70].R           /* External Channel Data Register */
#define SARADC_4_ECDR199     SARADC_4.ECDR[71].R           /* External Channel Data Register */
#define SARADC_4_ECDR200     SARADC_4.ECDR[72].R           /* External Channel Data Register */
#define SARADC_4_ECDR201     SARADC_4.ECDR[73].R           /* External Channel Data Register */
#define SARADC_4_ECDR202     SARADC_4.ECDR[74].R           /* External Channel Data Register */
#define SARADC_4_ECDR203     SARADC_4.ECDR[75].R           /* External Channel Data Register */
#define SARADC_4_ECDR204     SARADC_4.ECDR[76].R           /* External Channel Data Register */
#define SARADC_4_ECDR205     SARADC_4.ECDR[77].R           /* External Channel Data Register */
#define SARADC_4_ECDR206     SARADC_4.ECDR[78].R           /* External Channel Data Register */
#define SARADC_4_ECDR207     SARADC_4.ECDR[79].R           /* External Channel Data Register */
#define SARADC_4_ECDR208     SARADC_4.ECDR[80].R           /* External Channel Data Register */
#define SARADC_4_ECDR209     SARADC_4.ECDR[81].R           /* External Channel Data Register */
#define SARADC_4_ECDR210     SARADC_4.ECDR[82].R           /* External Channel Data Register */
#define SARADC_4_ECDR211     SARADC_4.ECDR[83].R           /* External Channel Data Register */
#define SARADC_4_ECDR212     SARADC_4.ECDR[84].R           /* External Channel Data Register */
#define SARADC_4_ECDR213     SARADC_4.ECDR[85].R           /* External Channel Data Register */
#define SARADC_4_ECDR214     SARADC_4.ECDR[86].R           /* External Channel Data Register */
#define SARADC_4_ECDR215     SARADC_4.ECDR[87].R           /* External Channel Data Register */
#define SARADC_4_ECDR216     SARADC_4.ECDR[88].R           /* External Channel Data Register */
#define SARADC_4_ECDR217     SARADC_4.ECDR[89].R           /* External Channel Data Register */
#define SARADC_4_ECDR218     SARADC_4.ECDR[90].R           /* External Channel Data Register */
#define SARADC_4_ECDR219     SARADC_4.ECDR[91].R           /* External Channel Data Register */
#define SARADC_4_ECDR220     SARADC_4.ECDR[92].R           /* External Channel Data Register */
#define SARADC_4_ECDR221     SARADC_4.ECDR[93].R           /* External Channel Data Register */
#define SARADC_4_ECDR222     SARADC_4.ECDR[94].R           /* External Channel Data Register */
#define SARADC_4_ECDR223     SARADC_4.ECDR[95].R           /* External Channel Data Register */
#define SARADC_4_ECDR224     SARADC_4.ECDR[96].R           /* External Channel Data Register */
#define SARADC_4_ECDR225     SARADC_4.ECDR[97].R           /* External Channel Data Register */
#define SARADC_4_ECDR226     SARADC_4.ECDR[98].R           /* External Channel Data Register */
#define SARADC_4_ECDR227     SARADC_4.ECDR[99].R           /* External Channel Data Register */
#define SARADC_4_ECDR228     SARADC_4.ECDR[100].R          /* External Channel Data Register */
#define SARADC_4_ECDR229     SARADC_4.ECDR[101].R          /* External Channel Data Register */
#define SARADC_4_ECDR230     SARADC_4.ECDR[102].R          /* External Channel Data Register */
#define SARADC_4_ECDR231     SARADC_4.ECDR[103].R          /* External Channel Data Register */
#define SARADC_4_ECDR232     SARADC_4.ECDR[104].R          /* External Channel Data Register */
#define SARADC_4_ECDR233     SARADC_4.ECDR[105].R          /* External Channel Data Register */
#define SARADC_4_ECDR234     SARADC_4.ECDR[106].R          /* External Channel Data Register */
#define SARADC_4_ECDR235     SARADC_4.ECDR[107].R          /* External Channel Data Register */
#define SARADC_4_ECDR236     SARADC_4.ECDR[108].R          /* External Channel Data Register */
#define SARADC_4_ECDR237     SARADC_4.ECDR[109].R          /* External Channel Data Register */
#define SARADC_4_ECDR238     SARADC_4.ECDR[110].R          /* External Channel Data Register */
#define SARADC_4_ECDR239     SARADC_4.ECDR[111].R          /* External Channel Data Register */
#define SARADC_4_ECDR240     SARADC_4.ECDR[112].R          /* External Channel Data Register */
#define SARADC_4_ECDR241     SARADC_4.ECDR[113].R          /* External Channel Data Register */
#define SARADC_4_ECDR242     SARADC_4.ECDR[114].R          /* External Channel Data Register */
#define SARADC_4_ECDR243     SARADC_4.ECDR[115].R          /* External Channel Data Register */
#define SARADC_4_ECDR244     SARADC_4.ECDR[116].R          /* External Channel Data Register */
#define SARADC_4_ECDR245     SARADC_4.ECDR[117].R          /* External Channel Data Register */
#define SARADC_4_ECDR246     SARADC_4.ECDR[118].R          /* External Channel Data Register */
#define SARADC_4_ECDR247     SARADC_4.ECDR[119].R          /* External Channel Data Register */
#define SARADC_4_ECDR248     SARADC_4.ECDR[120].R          /* External Channel Data Register */
#define SARADC_4_ECDR249     SARADC_4.ECDR[121].R          /* External Channel Data Register */
#define SARADC_4_ECDR250     SARADC_4.ECDR[122].R          /* External Channel Data Register */
#define SARADC_4_ECDR251     SARADC_4.ECDR[123].R          /* External Channel Data Register */
#define SARADC_4_ECDR252     SARADC_4.ECDR[124].R          /* External Channel Data Register */
#define SARADC_4_ECDR253     SARADC_4.ECDR[125].R          /* External Channel Data Register */
#define SARADC_4_ECDR254     SARADC_4.ECDR[126].R          /* External Channel Data Register */
#define SARADC_4_ECDR255     SARADC_4.ECDR[127].R          /* External Channel Data Register */

/* SARADC */
#define SARADC_5_MCR         SARADC_5.MCR.R                /* Main Configuration Register */
#define SARADC_5_MSR         SARADC_5.MSR.R                /* Main Status Register */
#define SARADC_5_ISR         SARADC_5.ISR.R                /* Interrupt Status Register */
#define SARADC_5_ICIPR0      SARADC_5.ICIPR[0].R           /* Internal channel Interrupt Pending Register */
#define SARADC_5_ICIPR1      SARADC_5.ICIPR[1].R           /* Internal channel Interrupt Pending Register */
#define SARADC_5_ICIPR2      SARADC_5.ICIPR[2].R           /* Internal channel Interrupt Pending Register */
#define SARADC_5_IMR         SARADC_5.IMR.R                /* Interrupt Mask Register */
#define SARADC_5_ICIMR0      SARADC_5.ICIMR[0].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_5_ICIMR1      SARADC_5.ICIMR[1].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_5_ICIMR2      SARADC_5.ICIMR[2].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_5_WTISR       SARADC_5.WTISR.R              /* Watchdog Threshold Interrupt Status Register */
#define SARADC_5_WTIMR       SARADC_5.WTIMR.R              /* Watchdog Threshold Interrupt Mask Register */
#define SARADC_5_DMAE        SARADC_5.DMAE.R               /* DMA Enable Register */
#define SARADC_5_ICDSR0      SARADC_5.ICDSR[0].R           /* Internal Channel DMA Select Register */
#define SARADC_5_ICDSR1      SARADC_5.ICDSR[1].R           /* Internal Channel DMA Select Register */
#define SARADC_5_ICDSR2      SARADC_5.ICDSR[2].R           /* Internal Channel DMA Select Register */
#define SARADC_5_WTHRHLR0    SARADC_5.WTHRHLR[0].R         /* Watchdog Threshold Register */
#define SARADC_5_WTHRHLR1    SARADC_5.WTHRHLR[1].R         /* Watchdog Threshold Register */
#define SARADC_5_WTHRHLR2    SARADC_5.WTHRHLR[2].R         /* Watchdog Threshold Register */
#define SARADC_5_WTHRHLR3    SARADC_5.WTHRHLR[3].R         /* Watchdog Threshold Register */
#define SARADC_5_CTR0        SARADC_5.CTR[0].R             /* Conversion Timing Register */
#define SARADC_5_CTR1        SARADC_5.CTR[1].R             /* Conversion Timing Register */
#define SARADC_5_CTR2        SARADC_5.CTR[2].R             /* Conversion Timing Register */
#define SARADC_5_CTR3        SARADC_5.CTR[3].R             /* Conversion Timing Register */
#define SARADC_5_ICNCMR0     SARADC_5.ICNCMR[0].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_5_ICNCMR1     SARADC_5.ICNCMR[1].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_5_ICNCMR2     SARADC_5.ICNCMR[2].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_5_ICJCMR0     SARADC_5.ICJCMR[0].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_5_ICJCMR1     SARADC_5.ICJCMR[1].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_5_ICJCMR2     SARADC_5.ICJCMR[2].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_5_PDEDR       SARADC_5.PDEDR.R              /* Power Down Exit Delay Register */
#define SARADC_5_ICDR0       SARADC_5.ICDR[0].R            /* Internal Channel Data Register */
#define SARADC_5_ICDR1       SARADC_5.ICDR[1].R            /* Internal Channel Data Register */
#define SARADC_5_ICDR2       SARADC_5.ICDR[2].R            /* Internal Channel Data Register */
#define SARADC_5_ICDR3       SARADC_5.ICDR[3].R            /* Internal Channel Data Register */
#define SARADC_5_ICDR4       SARADC_5.ICDR[4].R            /* Internal Channel Data Register */
#define SARADC_5_ICDR5       SARADC_5.ICDR[5].R            /* Internal Channel Data Register */
#define SARADC_5_ICDR6       SARADC_5.ICDR[6].R            /* Internal Channel Data Register */
#define SARADC_5_ICDR7       SARADC_5.ICDR[7].R            /* Internal Channel Data Register */
#define SARADC_5_ICDR8       SARADC_5.ICDR[8].R            /* Internal Channel Data Register */
#define SARADC_5_ICDR9       SARADC_5.ICDR[9].R            /* Internal Channel Data Register */
#define SARADC_5_ICDR10      SARADC_5.ICDR[10].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR11      SARADC_5.ICDR[11].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR12      SARADC_5.ICDR[12].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR13      SARADC_5.ICDR[13].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR14      SARADC_5.ICDR[14].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR15      SARADC_5.ICDR[15].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR16      SARADC_5.ICDR[16].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR17      SARADC_5.ICDR[17].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR18      SARADC_5.ICDR[18].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR19      SARADC_5.ICDR[19].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR20      SARADC_5.ICDR[20].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR21      SARADC_5.ICDR[21].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR22      SARADC_5.ICDR[22].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR23      SARADC_5.ICDR[23].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR24      SARADC_5.ICDR[24].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR25      SARADC_5.ICDR[25].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR26      SARADC_5.ICDR[26].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR27      SARADC_5.ICDR[27].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR28      SARADC_5.ICDR[28].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR29      SARADC_5.ICDR[29].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR30      SARADC_5.ICDR[30].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR31      SARADC_5.ICDR[31].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR32      SARADC_5.ICDR[32].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR33      SARADC_5.ICDR[33].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR34      SARADC_5.ICDR[34].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR35      SARADC_5.ICDR[35].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR36      SARADC_5.ICDR[36].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR37      SARADC_5.ICDR[37].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR38      SARADC_5.ICDR[38].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR39      SARADC_5.ICDR[39].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR40      SARADC_5.ICDR[40].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR41      SARADC_5.ICDR[41].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR42      SARADC_5.ICDR[42].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR43      SARADC_5.ICDR[43].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR44      SARADC_5.ICDR[44].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR45      SARADC_5.ICDR[45].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR46      SARADC_5.ICDR[46].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR47      SARADC_5.ICDR[47].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR48      SARADC_5.ICDR[48].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR49      SARADC_5.ICDR[49].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR50      SARADC_5.ICDR[50].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR51      SARADC_5.ICDR[51].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR52      SARADC_5.ICDR[52].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR53      SARADC_5.ICDR[53].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR54      SARADC_5.ICDR[54].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR55      SARADC_5.ICDR[55].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR56      SARADC_5.ICDR[56].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR57      SARADC_5.ICDR[57].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR58      SARADC_5.ICDR[58].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR59      SARADC_5.ICDR[59].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR60      SARADC_5.ICDR[60].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR61      SARADC_5.ICDR[61].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR62      SARADC_5.ICDR[62].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR63      SARADC_5.ICDR[63].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR64      SARADC_5.ICDR[64].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR65      SARADC_5.ICDR[65].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR66      SARADC_5.ICDR[66].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR67      SARADC_5.ICDR[67].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR68      SARADC_5.ICDR[68].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR69      SARADC_5.ICDR[69].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR70      SARADC_5.ICDR[70].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR71      SARADC_5.ICDR[71].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR72      SARADC_5.ICDR[72].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR73      SARADC_5.ICDR[73].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR74      SARADC_5.ICDR[74].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR75      SARADC_5.ICDR[75].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR76      SARADC_5.ICDR[76].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR77      SARADC_5.ICDR[77].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR78      SARADC_5.ICDR[78].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR79      SARADC_5.ICDR[79].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR80      SARADC_5.ICDR[80].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR81      SARADC_5.ICDR[81].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR82      SARADC_5.ICDR[82].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR83      SARADC_5.ICDR[83].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR84      SARADC_5.ICDR[84].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR85      SARADC_5.ICDR[85].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR86      SARADC_5.ICDR[86].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR87      SARADC_5.ICDR[87].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR88      SARADC_5.ICDR[88].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR89      SARADC_5.ICDR[89].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR90      SARADC_5.ICDR[90].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR91      SARADC_5.ICDR[91].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR92      SARADC_5.ICDR[92].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR93      SARADC_5.ICDR[93].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR94      SARADC_5.ICDR[94].R           /* Internal Channel Data Register */
#define SARADC_5_ICDR95      SARADC_5.ICDR[95].R           /* Internal Channel Data Register */
#define SARADC_5_ICWSELR0    SARADC_5.ICWSELR[0].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_5_ICWSELR1    SARADC_5.ICWSELR[1].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_5_ICWSELR2    SARADC_5.ICWSELR[2].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_5_ICWSELR3    SARADC_5.ICWSELR[3].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_5_ICWSELR4    SARADC_5.ICWSELR[4].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_5_ICWSELR5    SARADC_5.ICWSELR[5].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_5_ICWSELR6    SARADC_5.ICWSELR[6].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_5_ICWSELR7    SARADC_5.ICWSELR[7].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_5_ICWSELR8    SARADC_5.ICWSELR[8].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_5_ICWSELR9    SARADC_5.ICWSELR[9].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_5_ICWSELR10   SARADC_5.ICWSELR[10].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_5_ICWSELR11   SARADC_5.ICWSELR[11].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_5_ICWENR0     SARADC_5.ICWENR[0].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_5_ICWENR1     SARADC_5.ICWENR[1].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_5_ICWENR2     SARADC_5.ICWENR[2].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_5_ICAWORR0    SARADC_5.ICAWORR[0].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_5_ICAWORR1    SARADC_5.ICAWORR[1].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_5_ICAWORR2    SARADC_5.ICAWORR[2].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_5_TCIPR       SARADC_5.TCIPR.R              /* Test Channel Interrupt Pending Register */
#define SARADC_5_TCIMR       SARADC_5.TCIMR.R              /* Test Channel Interrupt Mask Register */
#define SARADC_5_TCDSR       SARADC_5.TCDSR.R              /* Test Channel DMA Select Register */
#define SARADC_5_TCNCMR      SARADC_5.TCNCMR.R             /* Test Channel Normal Conversion Mask Register */
#define SARADC_5_TCJCMR      SARADC_5.TCJCMR.R             /* Test Channel Injected Conversion Mask Register */
#define SARADC_5_TCWSELR0    SARADC_5.TCWSELR[0].R         /* Test Channel Watchdog Selection Register */
#define SARADC_5_TCWSELR1    SARADC_5.TCWSELR[1].R         /* Test Channel Watchdog Selection Register */
#define SARADC_5_TCWSELR2    SARADC_5.TCWSELR[2].R         /* Test Channel Watchdog Selection Register */
#define SARADC_5_TCWSELR3    SARADC_5.TCWSELR[3].R         /* Test Channel Watchdog Selection Register */
#define SARADC_5_TCWENR      SARADC_5.TCWENR.R             /* Test Channel Watchdog Enable Register */
#define SARADC_5_TCAWORR     SARADC_5.TCAWORR.R            /* Test Channel Analog Watchdog Out of Range Register */
#define SARADC_5_TCCAPR0     SARADC_5.TCCAPR[0].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_5_TCCAPR1     SARADC_5.TCCAPR[1].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_5_TCCAPR2     SARADC_5.TCCAPR[2].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_5_TCCAPR3     SARADC_5.TCCAPR[3].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_5_TCCAPR4     SARADC_5.TCCAPR[4].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_5_TCCAPR5     SARADC_5.TCCAPR[5].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_5_TCCAPR6     SARADC_5.TCCAPR[6].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_5_TCCAPR7     SARADC_5.TCCAPR[7].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_5_TCDR96      SARADC_5.TCDR[0].R            /* Test Channel Data Register */
#define SARADC_5_TCDR97      SARADC_5.TCDR[1].R            /* Test Channel Data Register */
#define SARADC_5_TCDR98      SARADC_5.TCDR[2].R            /* Test Channel Data Register */
#define SARADC_5_TCDR99      SARADC_5.TCDR[3].R            /* Test Channel Data Register */
#define SARADC_5_TCDR100     SARADC_5.TCDR[4].R            /* Test Channel Data Register */
#define SARADC_5_TCDR101     SARADC_5.TCDR[5].R            /* Test Channel Data Register */
#define SARADC_5_TCDR102     SARADC_5.TCDR[6].R            /* Test Channel Data Register */
#define SARADC_5_TCDR103     SARADC_5.TCDR[7].R            /* Test Channel Data Register */
#define SARADC_5_TCDR104     SARADC_5.TCDR[8].R            /* Test Channel Data Register */
#define SARADC_5_TCDR105     SARADC_5.TCDR[9].R            /* Test Channel Data Register */
#define SARADC_5_TCDR106     SARADC_5.TCDR[10].R           /* Test Channel Data Register */
#define SARADC_5_TCDR107     SARADC_5.TCDR[11].R           /* Test Channel Data Register */
#define SARADC_5_TCDR108     SARADC_5.TCDR[12].R           /* Test Channel Data Register */
#define SARADC_5_TCDR109     SARADC_5.TCDR[13].R           /* Test Channel Data Register */
#define SARADC_5_TCDR110     SARADC_5.TCDR[14].R           /* Test Channel Data Register */
#define SARADC_5_TCDR111     SARADC_5.TCDR[15].R           /* Test Channel Data Register */
#define SARADC_5_TCDR112     SARADC_5.TCDR[16].R           /* Test Channel Data Register */
#define SARADC_5_TCDR113     SARADC_5.TCDR[17].R           /* Test Channel Data Register */
#define SARADC_5_TCDR114     SARADC_5.TCDR[18].R           /* Test Channel Data Register */
#define SARADC_5_TCDR115     SARADC_5.TCDR[19].R           /* Test Channel Data Register */
#define SARADC_5_TCDR116     SARADC_5.TCDR[20].R           /* Test Channel Data Register */
#define SARADC_5_TCDR117     SARADC_5.TCDR[21].R           /* Test Channel Data Register */
#define SARADC_5_TCDR118     SARADC_5.TCDR[22].R           /* Test Channel Data Register */
#define SARADC_5_TCDR119     SARADC_5.TCDR[23].R           /* Test Channel Data Register */
#define SARADC_5_TCDR120     SARADC_5.TCDR[24].R           /* Test Channel Data Register */
#define SARADC_5_TCDR121     SARADC_5.TCDR[25].R           /* Test Channel Data Register */
#define SARADC_5_TCDR122     SARADC_5.TCDR[26].R           /* Test Channel Data Register */
#define SARADC_5_TCDR123     SARADC_5.TCDR[27].R           /* Test Channel Data Register */
#define SARADC_5_TCDR124     SARADC_5.TCDR[28].R           /* Test Channel Data Register */
#define SARADC_5_TCDR125     SARADC_5.TCDR[29].R           /* Test Channel Data Register */
#define SARADC_5_TCDR126     SARADC_5.TCDR[30].R           /* Test Channel Data Register */
#define SARADC_5_TCDR127     SARADC_5.TCDR[31].R           /* Test Channel Data Register */
#define SARADC_5_ECDSDR      SARADC_5.ECDSDR.R             /* External Channel Decode Signals Delay Register */
#define SARADC_5_ECIPR0      SARADC_5.ECIPR[0].R           /* External Channel Interrupt Pending Register */
#define SARADC_5_ECIPR1      SARADC_5.ECIPR[1].R           /* External Channel Interrupt Pending Register */
#define SARADC_5_ECIPR2      SARADC_5.ECIPR[2].R           /* External Channel Interrupt Pending Register */
#define SARADC_5_ECIPR3      SARADC_5.ECIPR[3].R           /* External Channel Interrupt Pending Register */
#define SARADC_5_ECIMR0      SARADC_5.ECIMR[0].R           /* External Channel Interrupt Mask Register */
#define SARADC_5_ECIMR1      SARADC_5.ECIMR[1].R           /* External Channel Interrupt Mask Register */
#define SARADC_5_ECIMR2      SARADC_5.ECIMR[2].R           /* External Channel Interrupt Mask Register */
#define SARADC_5_ECIMR3      SARADC_5.ECIMR[3].R           /* External Channel Interrupt Mask Register */
#define SARADC_5_ECDSR0      SARADC_5.ECDSR[0].R           /* External Channel DMA Select Register */
#define SARADC_5_ECDSR1      SARADC_5.ECDSR[1].R           /* External Channel DMA Select Register */
#define SARADC_5_ECDSR2      SARADC_5.ECDSR[2].R           /* External Channel DMA Select Register */
#define SARADC_5_ECDSR3      SARADC_5.ECDSR[3].R           /* External Channel DMA Select Register */
#define SARADC_5_ECNCMR0     SARADC_5.ECNCMR[0].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_5_ECNCMR1     SARADC_5.ECNCMR[1].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_5_ECNCMR2     SARADC_5.ECNCMR[2].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_5_ECNCMR3     SARADC_5.ECNCMR[3].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_5_ECJCMR0     SARADC_5.ECJCMR[0].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_5_ECJCMR1     SARADC_5.ECJCMR[1].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_5_ECJCMR2     SARADC_5.ECJCMR[2].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_5_ECJCMR3     SARADC_5.ECJCMR[3].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_5_ECWSELR0    SARADC_5.ECWSELR[0].R         /* External Channel Watchdog Selection Register */
#define SARADC_5_ECWSELR1    SARADC_5.ECWSELR[1].R         /* External Channel Watchdog Selection Register */
#define SARADC_5_ECWSELR2    SARADC_5.ECWSELR[2].R         /* External Channel Watchdog Selection Register */
#define SARADC_5_ECWSELR3    SARADC_5.ECWSELR[3].R         /* External Channel Watchdog Selection Register */
#define SARADC_5_ECWSELR4    SARADC_5.ECWSELR[4].R         /* External Channel Watchdog Selection Register */
#define SARADC_5_ECWSELR5    SARADC_5.ECWSELR[5].R         /* External Channel Watchdog Selection Register */
#define SARADC_5_ECWSELR6    SARADC_5.ECWSELR[6].R         /* External Channel Watchdog Selection Register */
#define SARADC_5_ECWSELR7    SARADC_5.ECWSELR[7].R         /* External Channel Watchdog Selection Register */
#define SARADC_5_ECWSELR8    SARADC_5.ECWSELR[8].R         /* External Channel Watchdog Selection Register */
#define SARADC_5_ECWSELR9    SARADC_5.ECWSELR[9].R         /* External Channel Watchdog Selection Register */
#define SARADC_5_ECWSELR10   SARADC_5.ECWSELR[10].R        /* External Channel Watchdog Selection Register */
#define SARADC_5_ECWSELR11   SARADC_5.ECWSELR[11].R        /* External Channel Watchdog Selection Register */
#define SARADC_5_ECWSELR12   SARADC_5.ECWSELR[12].R        /* External Channel Watchdog Selection Register */
#define SARADC_5_ECWSELR13   SARADC_5.ECWSELR[13].R        /* External Channel Watchdog Selection Register */
#define SARADC_5_ECWSELR14   SARADC_5.ECWSELR[14].R        /* External Channel Watchdog Selection Register */
#define SARADC_5_ECWSELR15   SARADC_5.ECWSELR[15].R        /* External Channel Watchdog Selection Register */
#define SARADC_5_ECWENR0     SARADC_5.ECWENR[0].R          /* External Channel Watchdog Enable Register */
#define SARADC_5_ECWENR1     SARADC_5.ECWENR[1].R          /* External Channel Watchdog Enable Register */
#define SARADC_5_ECWENR2     SARADC_5.ECWENR[2].R          /* External Channel Watchdog Enable Register */
#define SARADC_5_ECWENR3     SARADC_5.ECWENR[3].R          /* External Channel Watchdog Enable Register */
#define SARADC_5_ECAWORR0    SARADC_5.ECAWORR[0].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_5_ECAWORR1    SARADC_5.ECAWORR[1].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_5_ECAWORR2    SARADC_5.ECAWORR[2].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_5_ECAWORR3    SARADC_5.ECAWORR[3].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_5_ECMICR0     SARADC_5.ECMICR[0].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_5_ECMICR1     SARADC_5.ECMICR[1].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_5_ECMICR2     SARADC_5.ECMICR[2].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_5_ECMICR3     SARADC_5.ECMICR[3].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_5_ECDR128     SARADC_5.ECDR[0].R            /* External Channel Data Register */
#define SARADC_5_ECDR129     SARADC_5.ECDR[1].R            /* External Channel Data Register */
#define SARADC_5_ECDR130     SARADC_5.ECDR[2].R            /* External Channel Data Register */
#define SARADC_5_ECDR131     SARADC_5.ECDR[3].R            /* External Channel Data Register */
#define SARADC_5_ECDR132     SARADC_5.ECDR[4].R            /* External Channel Data Register */
#define SARADC_5_ECDR133     SARADC_5.ECDR[5].R            /* External Channel Data Register */
#define SARADC_5_ECDR134     SARADC_5.ECDR[6].R            /* External Channel Data Register */
#define SARADC_5_ECDR135     SARADC_5.ECDR[7].R            /* External Channel Data Register */
#define SARADC_5_ECDR136     SARADC_5.ECDR[8].R            /* External Channel Data Register */
#define SARADC_5_ECDR137     SARADC_5.ECDR[9].R            /* External Channel Data Register */
#define SARADC_5_ECDR138     SARADC_5.ECDR[10].R           /* External Channel Data Register */
#define SARADC_5_ECDR139     SARADC_5.ECDR[11].R           /* External Channel Data Register */
#define SARADC_5_ECDR140     SARADC_5.ECDR[12].R           /* External Channel Data Register */
#define SARADC_5_ECDR141     SARADC_5.ECDR[13].R           /* External Channel Data Register */
#define SARADC_5_ECDR142     SARADC_5.ECDR[14].R           /* External Channel Data Register */
#define SARADC_5_ECDR143     SARADC_5.ECDR[15].R           /* External Channel Data Register */
#define SARADC_5_ECDR144     SARADC_5.ECDR[16].R           /* External Channel Data Register */
#define SARADC_5_ECDR145     SARADC_5.ECDR[17].R           /* External Channel Data Register */
#define SARADC_5_ECDR146     SARADC_5.ECDR[18].R           /* External Channel Data Register */
#define SARADC_5_ECDR147     SARADC_5.ECDR[19].R           /* External Channel Data Register */
#define SARADC_5_ECDR148     SARADC_5.ECDR[20].R           /* External Channel Data Register */
#define SARADC_5_ECDR149     SARADC_5.ECDR[21].R           /* External Channel Data Register */
#define SARADC_5_ECDR150     SARADC_5.ECDR[22].R           /* External Channel Data Register */
#define SARADC_5_ECDR151     SARADC_5.ECDR[23].R           /* External Channel Data Register */
#define SARADC_5_ECDR152     SARADC_5.ECDR[24].R           /* External Channel Data Register */
#define SARADC_5_ECDR153     SARADC_5.ECDR[25].R           /* External Channel Data Register */
#define SARADC_5_ECDR154     SARADC_5.ECDR[26].R           /* External Channel Data Register */
#define SARADC_5_ECDR155     SARADC_5.ECDR[27].R           /* External Channel Data Register */
#define SARADC_5_ECDR156     SARADC_5.ECDR[28].R           /* External Channel Data Register */
#define SARADC_5_ECDR157     SARADC_5.ECDR[29].R           /* External Channel Data Register */
#define SARADC_5_ECDR158     SARADC_5.ECDR[30].R           /* External Channel Data Register */
#define SARADC_5_ECDR159     SARADC_5.ECDR[31].R           /* External Channel Data Register */
#define SARADC_5_ECDR160     SARADC_5.ECDR[32].R           /* External Channel Data Register */
#define SARADC_5_ECDR161     SARADC_5.ECDR[33].R           /* External Channel Data Register */
#define SARADC_5_ECDR162     SARADC_5.ECDR[34].R           /* External Channel Data Register */
#define SARADC_5_ECDR163     SARADC_5.ECDR[35].R           /* External Channel Data Register */
#define SARADC_5_ECDR164     SARADC_5.ECDR[36].R           /* External Channel Data Register */
#define SARADC_5_ECDR165     SARADC_5.ECDR[37].R           /* External Channel Data Register */
#define SARADC_5_ECDR166     SARADC_5.ECDR[38].R           /* External Channel Data Register */
#define SARADC_5_ECDR167     SARADC_5.ECDR[39].R           /* External Channel Data Register */
#define SARADC_5_ECDR168     SARADC_5.ECDR[40].R           /* External Channel Data Register */
#define SARADC_5_ECDR169     SARADC_5.ECDR[41].R           /* External Channel Data Register */
#define SARADC_5_ECDR170     SARADC_5.ECDR[42].R           /* External Channel Data Register */
#define SARADC_5_ECDR171     SARADC_5.ECDR[43].R           /* External Channel Data Register */
#define SARADC_5_ECDR172     SARADC_5.ECDR[44].R           /* External Channel Data Register */
#define SARADC_5_ECDR173     SARADC_5.ECDR[45].R           /* External Channel Data Register */
#define SARADC_5_ECDR174     SARADC_5.ECDR[46].R           /* External Channel Data Register */
#define SARADC_5_ECDR175     SARADC_5.ECDR[47].R           /* External Channel Data Register */
#define SARADC_5_ECDR176     SARADC_5.ECDR[48].R           /* External Channel Data Register */
#define SARADC_5_ECDR177     SARADC_5.ECDR[49].R           /* External Channel Data Register */
#define SARADC_5_ECDR178     SARADC_5.ECDR[50].R           /* External Channel Data Register */
#define SARADC_5_ECDR179     SARADC_5.ECDR[51].R           /* External Channel Data Register */
#define SARADC_5_ECDR180     SARADC_5.ECDR[52].R           /* External Channel Data Register */
#define SARADC_5_ECDR181     SARADC_5.ECDR[53].R           /* External Channel Data Register */
#define SARADC_5_ECDR182     SARADC_5.ECDR[54].R           /* External Channel Data Register */
#define SARADC_5_ECDR183     SARADC_5.ECDR[55].R           /* External Channel Data Register */
#define SARADC_5_ECDR184     SARADC_5.ECDR[56].R           /* External Channel Data Register */
#define SARADC_5_ECDR185     SARADC_5.ECDR[57].R           /* External Channel Data Register */
#define SARADC_5_ECDR186     SARADC_5.ECDR[58].R           /* External Channel Data Register */
#define SARADC_5_ECDR187     SARADC_5.ECDR[59].R           /* External Channel Data Register */
#define SARADC_5_ECDR188     SARADC_5.ECDR[60].R           /* External Channel Data Register */
#define SARADC_5_ECDR189     SARADC_5.ECDR[61].R           /* External Channel Data Register */
#define SARADC_5_ECDR190     SARADC_5.ECDR[62].R           /* External Channel Data Register */
#define SARADC_5_ECDR191     SARADC_5.ECDR[63].R           /* External Channel Data Register */
#define SARADC_5_ECDR192     SARADC_5.ECDR[64].R           /* External Channel Data Register */
#define SARADC_5_ECDR193     SARADC_5.ECDR[65].R           /* External Channel Data Register */
#define SARADC_5_ECDR194     SARADC_5.ECDR[66].R           /* External Channel Data Register */
#define SARADC_5_ECDR195     SARADC_5.ECDR[67].R           /* External Channel Data Register */
#define SARADC_5_ECDR196     SARADC_5.ECDR[68].R           /* External Channel Data Register */
#define SARADC_5_ECDR197     SARADC_5.ECDR[69].R           /* External Channel Data Register */
#define SARADC_5_ECDR198     SARADC_5.ECDR[70].R           /* External Channel Data Register */
#define SARADC_5_ECDR199     SARADC_5.ECDR[71].R           /* External Channel Data Register */
#define SARADC_5_ECDR200     SARADC_5.ECDR[72].R           /* External Channel Data Register */
#define SARADC_5_ECDR201     SARADC_5.ECDR[73].R           /* External Channel Data Register */
#define SARADC_5_ECDR202     SARADC_5.ECDR[74].R           /* External Channel Data Register */
#define SARADC_5_ECDR203     SARADC_5.ECDR[75].R           /* External Channel Data Register */
#define SARADC_5_ECDR204     SARADC_5.ECDR[76].R           /* External Channel Data Register */
#define SARADC_5_ECDR205     SARADC_5.ECDR[77].R           /* External Channel Data Register */
#define SARADC_5_ECDR206     SARADC_5.ECDR[78].R           /* External Channel Data Register */
#define SARADC_5_ECDR207     SARADC_5.ECDR[79].R           /* External Channel Data Register */
#define SARADC_5_ECDR208     SARADC_5.ECDR[80].R           /* External Channel Data Register */
#define SARADC_5_ECDR209     SARADC_5.ECDR[81].R           /* External Channel Data Register */
#define SARADC_5_ECDR210     SARADC_5.ECDR[82].R           /* External Channel Data Register */
#define SARADC_5_ECDR211     SARADC_5.ECDR[83].R           /* External Channel Data Register */
#define SARADC_5_ECDR212     SARADC_5.ECDR[84].R           /* External Channel Data Register */
#define SARADC_5_ECDR213     SARADC_5.ECDR[85].R           /* External Channel Data Register */
#define SARADC_5_ECDR214     SARADC_5.ECDR[86].R           /* External Channel Data Register */
#define SARADC_5_ECDR215     SARADC_5.ECDR[87].R           /* External Channel Data Register */
#define SARADC_5_ECDR216     SARADC_5.ECDR[88].R           /* External Channel Data Register */
#define SARADC_5_ECDR217     SARADC_5.ECDR[89].R           /* External Channel Data Register */
#define SARADC_5_ECDR218     SARADC_5.ECDR[90].R           /* External Channel Data Register */
#define SARADC_5_ECDR219     SARADC_5.ECDR[91].R           /* External Channel Data Register */
#define SARADC_5_ECDR220     SARADC_5.ECDR[92].R           /* External Channel Data Register */
#define SARADC_5_ECDR221     SARADC_5.ECDR[93].R           /* External Channel Data Register */
#define SARADC_5_ECDR222     SARADC_5.ECDR[94].R           /* External Channel Data Register */
#define SARADC_5_ECDR223     SARADC_5.ECDR[95].R           /* External Channel Data Register */
#define SARADC_5_ECDR224     SARADC_5.ECDR[96].R           /* External Channel Data Register */
#define SARADC_5_ECDR225     SARADC_5.ECDR[97].R           /* External Channel Data Register */
#define SARADC_5_ECDR226     SARADC_5.ECDR[98].R           /* External Channel Data Register */
#define SARADC_5_ECDR227     SARADC_5.ECDR[99].R           /* External Channel Data Register */
#define SARADC_5_ECDR228     SARADC_5.ECDR[100].R          /* External Channel Data Register */
#define SARADC_5_ECDR229     SARADC_5.ECDR[101].R          /* External Channel Data Register */
#define SARADC_5_ECDR230     SARADC_5.ECDR[102].R          /* External Channel Data Register */
#define SARADC_5_ECDR231     SARADC_5.ECDR[103].R          /* External Channel Data Register */
#define SARADC_5_ECDR232     SARADC_5.ECDR[104].R          /* External Channel Data Register */
#define SARADC_5_ECDR233     SARADC_5.ECDR[105].R          /* External Channel Data Register */
#define SARADC_5_ECDR234     SARADC_5.ECDR[106].R          /* External Channel Data Register */
#define SARADC_5_ECDR235     SARADC_5.ECDR[107].R          /* External Channel Data Register */
#define SARADC_5_ECDR236     SARADC_5.ECDR[108].R          /* External Channel Data Register */
#define SARADC_5_ECDR237     SARADC_5.ECDR[109].R          /* External Channel Data Register */
#define SARADC_5_ECDR238     SARADC_5.ECDR[110].R          /* External Channel Data Register */
#define SARADC_5_ECDR239     SARADC_5.ECDR[111].R          /* External Channel Data Register */
#define SARADC_5_ECDR240     SARADC_5.ECDR[112].R          /* External Channel Data Register */
#define SARADC_5_ECDR241     SARADC_5.ECDR[113].R          /* External Channel Data Register */
#define SARADC_5_ECDR242     SARADC_5.ECDR[114].R          /* External Channel Data Register */
#define SARADC_5_ECDR243     SARADC_5.ECDR[115].R          /* External Channel Data Register */
#define SARADC_5_ECDR244     SARADC_5.ECDR[116].R          /* External Channel Data Register */
#define SARADC_5_ECDR245     SARADC_5.ECDR[117].R          /* External Channel Data Register */
#define SARADC_5_ECDR246     SARADC_5.ECDR[118].R          /* External Channel Data Register */
#define SARADC_5_ECDR247     SARADC_5.ECDR[119].R          /* External Channel Data Register */
#define SARADC_5_ECDR248     SARADC_5.ECDR[120].R          /* External Channel Data Register */
#define SARADC_5_ECDR249     SARADC_5.ECDR[121].R          /* External Channel Data Register */
#define SARADC_5_ECDR250     SARADC_5.ECDR[122].R          /* External Channel Data Register */
#define SARADC_5_ECDR251     SARADC_5.ECDR[123].R          /* External Channel Data Register */
#define SARADC_5_ECDR252     SARADC_5.ECDR[124].R          /* External Channel Data Register */
#define SARADC_5_ECDR253     SARADC_5.ECDR[125].R          /* External Channel Data Register */
#define SARADC_5_ECDR254     SARADC_5.ECDR[126].R          /* External Channel Data Register */
#define SARADC_5_ECDR255     SARADC_5.ECDR[127].R          /* External Channel Data Register */

/* SARADC */
#define SARADC_6_MCR         SARADC_6.MCR.R                /* Main Configuration Register */
#define SARADC_6_MSR         SARADC_6.MSR.R                /* Main Status Register */
#define SARADC_6_ISR         SARADC_6.ISR.R                /* Interrupt Status Register */
#define SARADC_6_ICIPR0      SARADC_6.ICIPR[0].R           /* Internal channel Interrupt Pending Register */
#define SARADC_6_ICIPR1      SARADC_6.ICIPR[1].R           /* Internal channel Interrupt Pending Register */
#define SARADC_6_ICIPR2      SARADC_6.ICIPR[2].R           /* Internal channel Interrupt Pending Register */
#define SARADC_6_IMR         SARADC_6.IMR.R                /* Interrupt Mask Register */
#define SARADC_6_ICIMR0      SARADC_6.ICIMR[0].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_6_ICIMR1      SARADC_6.ICIMR[1].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_6_ICIMR2      SARADC_6.ICIMR[2].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_6_WTISR       SARADC_6.WTISR.R              /* Watchdog Threshold Interrupt Status Register */
#define SARADC_6_WTIMR       SARADC_6.WTIMR.R              /* Watchdog Threshold Interrupt Mask Register */
#define SARADC_6_DMAE        SARADC_6.DMAE.R               /* DMA Enable Register */
#define SARADC_6_ICDSR0      SARADC_6.ICDSR[0].R           /* Internal Channel DMA Select Register */
#define SARADC_6_ICDSR1      SARADC_6.ICDSR[1].R           /* Internal Channel DMA Select Register */
#define SARADC_6_ICDSR2      SARADC_6.ICDSR[2].R           /* Internal Channel DMA Select Register */
#define SARADC_6_WTHRHLR0    SARADC_6.WTHRHLR[0].R         /* Watchdog Threshold Register */
#define SARADC_6_WTHRHLR1    SARADC_6.WTHRHLR[1].R         /* Watchdog Threshold Register */
#define SARADC_6_WTHRHLR2    SARADC_6.WTHRHLR[2].R         /* Watchdog Threshold Register */
#define SARADC_6_WTHRHLR3    SARADC_6.WTHRHLR[3].R         /* Watchdog Threshold Register */
#define SARADC_6_CTR0        SARADC_6.CTR[0].R             /* Conversion Timing Register */
#define SARADC_6_CTR1        SARADC_6.CTR[1].R             /* Conversion Timing Register */
#define SARADC_6_CTR2        SARADC_6.CTR[2].R             /* Conversion Timing Register */
#define SARADC_6_CTR3        SARADC_6.CTR[3].R             /* Conversion Timing Register */
#define SARADC_6_ICNCMR0     SARADC_6.ICNCMR[0].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_6_ICNCMR1     SARADC_6.ICNCMR[1].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_6_ICNCMR2     SARADC_6.ICNCMR[2].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_6_ICJCMR0     SARADC_6.ICJCMR[0].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_6_ICJCMR1     SARADC_6.ICJCMR[1].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_6_ICJCMR2     SARADC_6.ICJCMR[2].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_6_PDEDR       SARADC_6.PDEDR.R              /* Power Down Exit Delay Register */
#define SARADC_6_ICDR0       SARADC_6.ICDR[0].R            /* Internal Channel Data Register */
#define SARADC_6_ICDR1       SARADC_6.ICDR[1].R            /* Internal Channel Data Register */
#define SARADC_6_ICDR2       SARADC_6.ICDR[2].R            /* Internal Channel Data Register */
#define SARADC_6_ICDR3       SARADC_6.ICDR[3].R            /* Internal Channel Data Register */
#define SARADC_6_ICDR4       SARADC_6.ICDR[4].R            /* Internal Channel Data Register */
#define SARADC_6_ICDR5       SARADC_6.ICDR[5].R            /* Internal Channel Data Register */
#define SARADC_6_ICDR6       SARADC_6.ICDR[6].R            /* Internal Channel Data Register */
#define SARADC_6_ICDR7       SARADC_6.ICDR[7].R            /* Internal Channel Data Register */
#define SARADC_6_ICDR8       SARADC_6.ICDR[8].R            /* Internal Channel Data Register */
#define SARADC_6_ICDR9       SARADC_6.ICDR[9].R            /* Internal Channel Data Register */
#define SARADC_6_ICDR10      SARADC_6.ICDR[10].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR11      SARADC_6.ICDR[11].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR12      SARADC_6.ICDR[12].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR13      SARADC_6.ICDR[13].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR14      SARADC_6.ICDR[14].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR15      SARADC_6.ICDR[15].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR16      SARADC_6.ICDR[16].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR17      SARADC_6.ICDR[17].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR18      SARADC_6.ICDR[18].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR19      SARADC_6.ICDR[19].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR20      SARADC_6.ICDR[20].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR21      SARADC_6.ICDR[21].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR22      SARADC_6.ICDR[22].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR23      SARADC_6.ICDR[23].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR24      SARADC_6.ICDR[24].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR25      SARADC_6.ICDR[25].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR26      SARADC_6.ICDR[26].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR27      SARADC_6.ICDR[27].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR28      SARADC_6.ICDR[28].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR29      SARADC_6.ICDR[29].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR30      SARADC_6.ICDR[30].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR31      SARADC_6.ICDR[31].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR32      SARADC_6.ICDR[32].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR33      SARADC_6.ICDR[33].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR34      SARADC_6.ICDR[34].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR35      SARADC_6.ICDR[35].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR36      SARADC_6.ICDR[36].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR37      SARADC_6.ICDR[37].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR38      SARADC_6.ICDR[38].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR39      SARADC_6.ICDR[39].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR40      SARADC_6.ICDR[40].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR41      SARADC_6.ICDR[41].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR42      SARADC_6.ICDR[42].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR43      SARADC_6.ICDR[43].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR44      SARADC_6.ICDR[44].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR45      SARADC_6.ICDR[45].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR46      SARADC_6.ICDR[46].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR47      SARADC_6.ICDR[47].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR48      SARADC_6.ICDR[48].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR49      SARADC_6.ICDR[49].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR50      SARADC_6.ICDR[50].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR51      SARADC_6.ICDR[51].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR52      SARADC_6.ICDR[52].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR53      SARADC_6.ICDR[53].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR54      SARADC_6.ICDR[54].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR55      SARADC_6.ICDR[55].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR56      SARADC_6.ICDR[56].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR57      SARADC_6.ICDR[57].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR58      SARADC_6.ICDR[58].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR59      SARADC_6.ICDR[59].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR60      SARADC_6.ICDR[60].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR61      SARADC_6.ICDR[61].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR62      SARADC_6.ICDR[62].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR63      SARADC_6.ICDR[63].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR64      SARADC_6.ICDR[64].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR65      SARADC_6.ICDR[65].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR66      SARADC_6.ICDR[66].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR67      SARADC_6.ICDR[67].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR68      SARADC_6.ICDR[68].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR69      SARADC_6.ICDR[69].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR70      SARADC_6.ICDR[70].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR71      SARADC_6.ICDR[71].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR72      SARADC_6.ICDR[72].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR73      SARADC_6.ICDR[73].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR74      SARADC_6.ICDR[74].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR75      SARADC_6.ICDR[75].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR76      SARADC_6.ICDR[76].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR77      SARADC_6.ICDR[77].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR78      SARADC_6.ICDR[78].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR79      SARADC_6.ICDR[79].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR80      SARADC_6.ICDR[80].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR81      SARADC_6.ICDR[81].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR82      SARADC_6.ICDR[82].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR83      SARADC_6.ICDR[83].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR84      SARADC_6.ICDR[84].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR85      SARADC_6.ICDR[85].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR86      SARADC_6.ICDR[86].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR87      SARADC_6.ICDR[87].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR88      SARADC_6.ICDR[88].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR89      SARADC_6.ICDR[89].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR90      SARADC_6.ICDR[90].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR91      SARADC_6.ICDR[91].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR92      SARADC_6.ICDR[92].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR93      SARADC_6.ICDR[93].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR94      SARADC_6.ICDR[94].R           /* Internal Channel Data Register */
#define SARADC_6_ICDR95      SARADC_6.ICDR[95].R           /* Internal Channel Data Register */
#define SARADC_6_ICWSELR0    SARADC_6.ICWSELR[0].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_6_ICWSELR1    SARADC_6.ICWSELR[1].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_6_ICWSELR2    SARADC_6.ICWSELR[2].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_6_ICWSELR3    SARADC_6.ICWSELR[3].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_6_ICWSELR4    SARADC_6.ICWSELR[4].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_6_ICWSELR5    SARADC_6.ICWSELR[5].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_6_ICWSELR6    SARADC_6.ICWSELR[6].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_6_ICWSELR7    SARADC_6.ICWSELR[7].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_6_ICWSELR8    SARADC_6.ICWSELR[8].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_6_ICWSELR9    SARADC_6.ICWSELR[9].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_6_ICWSELR10   SARADC_6.ICWSELR[10].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_6_ICWSELR11   SARADC_6.ICWSELR[11].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_6_ICWENR0     SARADC_6.ICWENR[0].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_6_ICWENR1     SARADC_6.ICWENR[1].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_6_ICWENR2     SARADC_6.ICWENR[2].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_6_ICAWORR0    SARADC_6.ICAWORR[0].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_6_ICAWORR1    SARADC_6.ICAWORR[1].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_6_ICAWORR2    SARADC_6.ICAWORR[2].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_6_TCIPR       SARADC_6.TCIPR.R              /* Test Channel Interrupt Pending Register */
#define SARADC_6_TCIMR       SARADC_6.TCIMR.R              /* Test Channel Interrupt Mask Register */
#define SARADC_6_TCDSR       SARADC_6.TCDSR.R              /* Test Channel DMA Select Register */
#define SARADC_6_TCNCMR      SARADC_6.TCNCMR.R             /* Test Channel Normal Conversion Mask Register */
#define SARADC_6_TCJCMR      SARADC_6.TCJCMR.R             /* Test Channel Injected Conversion Mask Register */
#define SARADC_6_TCWSELR0    SARADC_6.TCWSELR[0].R         /* Test Channel Watchdog Selection Register */
#define SARADC_6_TCWSELR1    SARADC_6.TCWSELR[1].R         /* Test Channel Watchdog Selection Register */
#define SARADC_6_TCWSELR2    SARADC_6.TCWSELR[2].R         /* Test Channel Watchdog Selection Register */
#define SARADC_6_TCWSELR3    SARADC_6.TCWSELR[3].R         /* Test Channel Watchdog Selection Register */
#define SARADC_6_TCWENR      SARADC_6.TCWENR.R             /* Test Channel Watchdog Enable Register */
#define SARADC_6_TCAWORR     SARADC_6.TCAWORR.R            /* Test Channel Analog Watchdog Out of Range Register */
#define SARADC_6_TCCAPR0     SARADC_6.TCCAPR[0].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_6_TCCAPR1     SARADC_6.TCCAPR[1].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_6_TCCAPR2     SARADC_6.TCCAPR[2].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_6_TCCAPR3     SARADC_6.TCCAPR[3].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_6_TCCAPR4     SARADC_6.TCCAPR[4].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_6_TCCAPR5     SARADC_6.TCCAPR[5].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_6_TCCAPR6     SARADC_6.TCCAPR[6].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_6_TCCAPR7     SARADC_6.TCCAPR[7].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_6_TCDR96      SARADC_6.TCDR[0].R            /* Test Channel Data Register */
#define SARADC_6_TCDR97      SARADC_6.TCDR[1].R            /* Test Channel Data Register */
#define SARADC_6_TCDR98      SARADC_6.TCDR[2].R            /* Test Channel Data Register */
#define SARADC_6_TCDR99      SARADC_6.TCDR[3].R            /* Test Channel Data Register */
#define SARADC_6_TCDR100     SARADC_6.TCDR[4].R            /* Test Channel Data Register */
#define SARADC_6_TCDR101     SARADC_6.TCDR[5].R            /* Test Channel Data Register */
#define SARADC_6_TCDR102     SARADC_6.TCDR[6].R            /* Test Channel Data Register */
#define SARADC_6_TCDR103     SARADC_6.TCDR[7].R            /* Test Channel Data Register */
#define SARADC_6_TCDR104     SARADC_6.TCDR[8].R            /* Test Channel Data Register */
#define SARADC_6_TCDR105     SARADC_6.TCDR[9].R            /* Test Channel Data Register */
#define SARADC_6_TCDR106     SARADC_6.TCDR[10].R           /* Test Channel Data Register */
#define SARADC_6_TCDR107     SARADC_6.TCDR[11].R           /* Test Channel Data Register */
#define SARADC_6_TCDR108     SARADC_6.TCDR[12].R           /* Test Channel Data Register */
#define SARADC_6_TCDR109     SARADC_6.TCDR[13].R           /* Test Channel Data Register */
#define SARADC_6_TCDR110     SARADC_6.TCDR[14].R           /* Test Channel Data Register */
#define SARADC_6_TCDR111     SARADC_6.TCDR[15].R           /* Test Channel Data Register */
#define SARADC_6_TCDR112     SARADC_6.TCDR[16].R           /* Test Channel Data Register */
#define SARADC_6_TCDR113     SARADC_6.TCDR[17].R           /* Test Channel Data Register */
#define SARADC_6_TCDR114     SARADC_6.TCDR[18].R           /* Test Channel Data Register */
#define SARADC_6_TCDR115     SARADC_6.TCDR[19].R           /* Test Channel Data Register */
#define SARADC_6_TCDR116     SARADC_6.TCDR[20].R           /* Test Channel Data Register */
#define SARADC_6_TCDR117     SARADC_6.TCDR[21].R           /* Test Channel Data Register */
#define SARADC_6_TCDR118     SARADC_6.TCDR[22].R           /* Test Channel Data Register */
#define SARADC_6_TCDR119     SARADC_6.TCDR[23].R           /* Test Channel Data Register */
#define SARADC_6_TCDR120     SARADC_6.TCDR[24].R           /* Test Channel Data Register */
#define SARADC_6_TCDR121     SARADC_6.TCDR[25].R           /* Test Channel Data Register */
#define SARADC_6_TCDR122     SARADC_6.TCDR[26].R           /* Test Channel Data Register */
#define SARADC_6_TCDR123     SARADC_6.TCDR[27].R           /* Test Channel Data Register */
#define SARADC_6_TCDR124     SARADC_6.TCDR[28].R           /* Test Channel Data Register */
#define SARADC_6_TCDR125     SARADC_6.TCDR[29].R           /* Test Channel Data Register */
#define SARADC_6_TCDR126     SARADC_6.TCDR[30].R           /* Test Channel Data Register */
#define SARADC_6_TCDR127     SARADC_6.TCDR[31].R           /* Test Channel Data Register */
#define SARADC_6_ECDSDR      SARADC_6.ECDSDR.R             /* External Channel Decode Signals Delay Register */
#define SARADC_6_ECIPR0      SARADC_6.ECIPR[0].R           /* External Channel Interrupt Pending Register */
#define SARADC_6_ECIPR1      SARADC_6.ECIPR[1].R           /* External Channel Interrupt Pending Register */
#define SARADC_6_ECIPR2      SARADC_6.ECIPR[2].R           /* External Channel Interrupt Pending Register */
#define SARADC_6_ECIPR3      SARADC_6.ECIPR[3].R           /* External Channel Interrupt Pending Register */
#define SARADC_6_ECIMR0      SARADC_6.ECIMR[0].R           /* External Channel Interrupt Mask Register */
#define SARADC_6_ECIMR1      SARADC_6.ECIMR[1].R           /* External Channel Interrupt Mask Register */
#define SARADC_6_ECIMR2      SARADC_6.ECIMR[2].R           /* External Channel Interrupt Mask Register */
#define SARADC_6_ECIMR3      SARADC_6.ECIMR[3].R           /* External Channel Interrupt Mask Register */
#define SARADC_6_ECDSR0      SARADC_6.ECDSR[0].R           /* External Channel DMA Select Register */
#define SARADC_6_ECDSR1      SARADC_6.ECDSR[1].R           /* External Channel DMA Select Register */
#define SARADC_6_ECDSR2      SARADC_6.ECDSR[2].R           /* External Channel DMA Select Register */
#define SARADC_6_ECDSR3      SARADC_6.ECDSR[3].R           /* External Channel DMA Select Register */
#define SARADC_6_ECNCMR0     SARADC_6.ECNCMR[0].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_6_ECNCMR1     SARADC_6.ECNCMR[1].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_6_ECNCMR2     SARADC_6.ECNCMR[2].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_6_ECNCMR3     SARADC_6.ECNCMR[3].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_6_ECJCMR0     SARADC_6.ECJCMR[0].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_6_ECJCMR1     SARADC_6.ECJCMR[1].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_6_ECJCMR2     SARADC_6.ECJCMR[2].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_6_ECJCMR3     SARADC_6.ECJCMR[3].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_6_ECWSELR0    SARADC_6.ECWSELR[0].R         /* External Channel Watchdog Selection Register */
#define SARADC_6_ECWSELR1    SARADC_6.ECWSELR[1].R         /* External Channel Watchdog Selection Register */
#define SARADC_6_ECWSELR2    SARADC_6.ECWSELR[2].R         /* External Channel Watchdog Selection Register */
#define SARADC_6_ECWSELR3    SARADC_6.ECWSELR[3].R         /* External Channel Watchdog Selection Register */
#define SARADC_6_ECWSELR4    SARADC_6.ECWSELR[4].R         /* External Channel Watchdog Selection Register */
#define SARADC_6_ECWSELR5    SARADC_6.ECWSELR[5].R         /* External Channel Watchdog Selection Register */
#define SARADC_6_ECWSELR6    SARADC_6.ECWSELR[6].R         /* External Channel Watchdog Selection Register */
#define SARADC_6_ECWSELR7    SARADC_6.ECWSELR[7].R         /* External Channel Watchdog Selection Register */
#define SARADC_6_ECWSELR8    SARADC_6.ECWSELR[8].R         /* External Channel Watchdog Selection Register */
#define SARADC_6_ECWSELR9    SARADC_6.ECWSELR[9].R         /* External Channel Watchdog Selection Register */
#define SARADC_6_ECWSELR10   SARADC_6.ECWSELR[10].R        /* External Channel Watchdog Selection Register */
#define SARADC_6_ECWSELR11   SARADC_6.ECWSELR[11].R        /* External Channel Watchdog Selection Register */
#define SARADC_6_ECWSELR12   SARADC_6.ECWSELR[12].R        /* External Channel Watchdog Selection Register */
#define SARADC_6_ECWSELR13   SARADC_6.ECWSELR[13].R        /* External Channel Watchdog Selection Register */
#define SARADC_6_ECWSELR14   SARADC_6.ECWSELR[14].R        /* External Channel Watchdog Selection Register */
#define SARADC_6_ECWSELR15   SARADC_6.ECWSELR[15].R        /* External Channel Watchdog Selection Register */
#define SARADC_6_ECWENR0     SARADC_6.ECWENR[0].R          /* External Channel Watchdog Enable Register */
#define SARADC_6_ECWENR1     SARADC_6.ECWENR[1].R          /* External Channel Watchdog Enable Register */
#define SARADC_6_ECWENR2     SARADC_6.ECWENR[2].R          /* External Channel Watchdog Enable Register */
#define SARADC_6_ECWENR3     SARADC_6.ECWENR[3].R          /* External Channel Watchdog Enable Register */
#define SARADC_6_ECAWORR0    SARADC_6.ECAWORR[0].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_6_ECAWORR1    SARADC_6.ECAWORR[1].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_6_ECAWORR2    SARADC_6.ECAWORR[2].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_6_ECAWORR3    SARADC_6.ECAWORR[3].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_6_ECMICR0     SARADC_6.ECMICR[0].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_6_ECMICR1     SARADC_6.ECMICR[1].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_6_ECMICR2     SARADC_6.ECMICR[2].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_6_ECMICR3     SARADC_6.ECMICR[3].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_6_ECDR128     SARADC_6.ECDR[0].R            /* External Channel Data Register */
#define SARADC_6_ECDR129     SARADC_6.ECDR[1].R            /* External Channel Data Register */
#define SARADC_6_ECDR130     SARADC_6.ECDR[2].R            /* External Channel Data Register */
#define SARADC_6_ECDR131     SARADC_6.ECDR[3].R            /* External Channel Data Register */
#define SARADC_6_ECDR132     SARADC_6.ECDR[4].R            /* External Channel Data Register */
#define SARADC_6_ECDR133     SARADC_6.ECDR[5].R            /* External Channel Data Register */
#define SARADC_6_ECDR134     SARADC_6.ECDR[6].R            /* External Channel Data Register */
#define SARADC_6_ECDR135     SARADC_6.ECDR[7].R            /* External Channel Data Register */
#define SARADC_6_ECDR136     SARADC_6.ECDR[8].R            /* External Channel Data Register */
#define SARADC_6_ECDR137     SARADC_6.ECDR[9].R            /* External Channel Data Register */
#define SARADC_6_ECDR138     SARADC_6.ECDR[10].R           /* External Channel Data Register */
#define SARADC_6_ECDR139     SARADC_6.ECDR[11].R           /* External Channel Data Register */
#define SARADC_6_ECDR140     SARADC_6.ECDR[12].R           /* External Channel Data Register */
#define SARADC_6_ECDR141     SARADC_6.ECDR[13].R           /* External Channel Data Register */
#define SARADC_6_ECDR142     SARADC_6.ECDR[14].R           /* External Channel Data Register */
#define SARADC_6_ECDR143     SARADC_6.ECDR[15].R           /* External Channel Data Register */
#define SARADC_6_ECDR144     SARADC_6.ECDR[16].R           /* External Channel Data Register */
#define SARADC_6_ECDR145     SARADC_6.ECDR[17].R           /* External Channel Data Register */
#define SARADC_6_ECDR146     SARADC_6.ECDR[18].R           /* External Channel Data Register */
#define SARADC_6_ECDR147     SARADC_6.ECDR[19].R           /* External Channel Data Register */
#define SARADC_6_ECDR148     SARADC_6.ECDR[20].R           /* External Channel Data Register */
#define SARADC_6_ECDR149     SARADC_6.ECDR[21].R           /* External Channel Data Register */
#define SARADC_6_ECDR150     SARADC_6.ECDR[22].R           /* External Channel Data Register */
#define SARADC_6_ECDR151     SARADC_6.ECDR[23].R           /* External Channel Data Register */
#define SARADC_6_ECDR152     SARADC_6.ECDR[24].R           /* External Channel Data Register */
#define SARADC_6_ECDR153     SARADC_6.ECDR[25].R           /* External Channel Data Register */
#define SARADC_6_ECDR154     SARADC_6.ECDR[26].R           /* External Channel Data Register */
#define SARADC_6_ECDR155     SARADC_6.ECDR[27].R           /* External Channel Data Register */
#define SARADC_6_ECDR156     SARADC_6.ECDR[28].R           /* External Channel Data Register */
#define SARADC_6_ECDR157     SARADC_6.ECDR[29].R           /* External Channel Data Register */
#define SARADC_6_ECDR158     SARADC_6.ECDR[30].R           /* External Channel Data Register */
#define SARADC_6_ECDR159     SARADC_6.ECDR[31].R           /* External Channel Data Register */
#define SARADC_6_ECDR160     SARADC_6.ECDR[32].R           /* External Channel Data Register */
#define SARADC_6_ECDR161     SARADC_6.ECDR[33].R           /* External Channel Data Register */
#define SARADC_6_ECDR162     SARADC_6.ECDR[34].R           /* External Channel Data Register */
#define SARADC_6_ECDR163     SARADC_6.ECDR[35].R           /* External Channel Data Register */
#define SARADC_6_ECDR164     SARADC_6.ECDR[36].R           /* External Channel Data Register */
#define SARADC_6_ECDR165     SARADC_6.ECDR[37].R           /* External Channel Data Register */
#define SARADC_6_ECDR166     SARADC_6.ECDR[38].R           /* External Channel Data Register */
#define SARADC_6_ECDR167     SARADC_6.ECDR[39].R           /* External Channel Data Register */
#define SARADC_6_ECDR168     SARADC_6.ECDR[40].R           /* External Channel Data Register */
#define SARADC_6_ECDR169     SARADC_6.ECDR[41].R           /* External Channel Data Register */
#define SARADC_6_ECDR170     SARADC_6.ECDR[42].R           /* External Channel Data Register */
#define SARADC_6_ECDR171     SARADC_6.ECDR[43].R           /* External Channel Data Register */
#define SARADC_6_ECDR172     SARADC_6.ECDR[44].R           /* External Channel Data Register */
#define SARADC_6_ECDR173     SARADC_6.ECDR[45].R           /* External Channel Data Register */
#define SARADC_6_ECDR174     SARADC_6.ECDR[46].R           /* External Channel Data Register */
#define SARADC_6_ECDR175     SARADC_6.ECDR[47].R           /* External Channel Data Register */
#define SARADC_6_ECDR176     SARADC_6.ECDR[48].R           /* External Channel Data Register */
#define SARADC_6_ECDR177     SARADC_6.ECDR[49].R           /* External Channel Data Register */
#define SARADC_6_ECDR178     SARADC_6.ECDR[50].R           /* External Channel Data Register */
#define SARADC_6_ECDR179     SARADC_6.ECDR[51].R           /* External Channel Data Register */
#define SARADC_6_ECDR180     SARADC_6.ECDR[52].R           /* External Channel Data Register */
#define SARADC_6_ECDR181     SARADC_6.ECDR[53].R           /* External Channel Data Register */
#define SARADC_6_ECDR182     SARADC_6.ECDR[54].R           /* External Channel Data Register */
#define SARADC_6_ECDR183     SARADC_6.ECDR[55].R           /* External Channel Data Register */
#define SARADC_6_ECDR184     SARADC_6.ECDR[56].R           /* External Channel Data Register */
#define SARADC_6_ECDR185     SARADC_6.ECDR[57].R           /* External Channel Data Register */
#define SARADC_6_ECDR186     SARADC_6.ECDR[58].R           /* External Channel Data Register */
#define SARADC_6_ECDR187     SARADC_6.ECDR[59].R           /* External Channel Data Register */
#define SARADC_6_ECDR188     SARADC_6.ECDR[60].R           /* External Channel Data Register */
#define SARADC_6_ECDR189     SARADC_6.ECDR[61].R           /* External Channel Data Register */
#define SARADC_6_ECDR190     SARADC_6.ECDR[62].R           /* External Channel Data Register */
#define SARADC_6_ECDR191     SARADC_6.ECDR[63].R           /* External Channel Data Register */
#define SARADC_6_ECDR192     SARADC_6.ECDR[64].R           /* External Channel Data Register */
#define SARADC_6_ECDR193     SARADC_6.ECDR[65].R           /* External Channel Data Register */
#define SARADC_6_ECDR194     SARADC_6.ECDR[66].R           /* External Channel Data Register */
#define SARADC_6_ECDR195     SARADC_6.ECDR[67].R           /* External Channel Data Register */
#define SARADC_6_ECDR196     SARADC_6.ECDR[68].R           /* External Channel Data Register */
#define SARADC_6_ECDR197     SARADC_6.ECDR[69].R           /* External Channel Data Register */
#define SARADC_6_ECDR198     SARADC_6.ECDR[70].R           /* External Channel Data Register */
#define SARADC_6_ECDR199     SARADC_6.ECDR[71].R           /* External Channel Data Register */
#define SARADC_6_ECDR200     SARADC_6.ECDR[72].R           /* External Channel Data Register */
#define SARADC_6_ECDR201     SARADC_6.ECDR[73].R           /* External Channel Data Register */
#define SARADC_6_ECDR202     SARADC_6.ECDR[74].R           /* External Channel Data Register */
#define SARADC_6_ECDR203     SARADC_6.ECDR[75].R           /* External Channel Data Register */
#define SARADC_6_ECDR204     SARADC_6.ECDR[76].R           /* External Channel Data Register */
#define SARADC_6_ECDR205     SARADC_6.ECDR[77].R           /* External Channel Data Register */
#define SARADC_6_ECDR206     SARADC_6.ECDR[78].R           /* External Channel Data Register */
#define SARADC_6_ECDR207     SARADC_6.ECDR[79].R           /* External Channel Data Register */
#define SARADC_6_ECDR208     SARADC_6.ECDR[80].R           /* External Channel Data Register */
#define SARADC_6_ECDR209     SARADC_6.ECDR[81].R           /* External Channel Data Register */
#define SARADC_6_ECDR210     SARADC_6.ECDR[82].R           /* External Channel Data Register */
#define SARADC_6_ECDR211     SARADC_6.ECDR[83].R           /* External Channel Data Register */
#define SARADC_6_ECDR212     SARADC_6.ECDR[84].R           /* External Channel Data Register */
#define SARADC_6_ECDR213     SARADC_6.ECDR[85].R           /* External Channel Data Register */
#define SARADC_6_ECDR214     SARADC_6.ECDR[86].R           /* External Channel Data Register */
#define SARADC_6_ECDR215     SARADC_6.ECDR[87].R           /* External Channel Data Register */
#define SARADC_6_ECDR216     SARADC_6.ECDR[88].R           /* External Channel Data Register */
#define SARADC_6_ECDR217     SARADC_6.ECDR[89].R           /* External Channel Data Register */
#define SARADC_6_ECDR218     SARADC_6.ECDR[90].R           /* External Channel Data Register */
#define SARADC_6_ECDR219     SARADC_6.ECDR[91].R           /* External Channel Data Register */
#define SARADC_6_ECDR220     SARADC_6.ECDR[92].R           /* External Channel Data Register */
#define SARADC_6_ECDR221     SARADC_6.ECDR[93].R           /* External Channel Data Register */
#define SARADC_6_ECDR222     SARADC_6.ECDR[94].R           /* External Channel Data Register */
#define SARADC_6_ECDR223     SARADC_6.ECDR[95].R           /* External Channel Data Register */
#define SARADC_6_ECDR224     SARADC_6.ECDR[96].R           /* External Channel Data Register */
#define SARADC_6_ECDR225     SARADC_6.ECDR[97].R           /* External Channel Data Register */
#define SARADC_6_ECDR226     SARADC_6.ECDR[98].R           /* External Channel Data Register */
#define SARADC_6_ECDR227     SARADC_6.ECDR[99].R           /* External Channel Data Register */
#define SARADC_6_ECDR228     SARADC_6.ECDR[100].R          /* External Channel Data Register */
#define SARADC_6_ECDR229     SARADC_6.ECDR[101].R          /* External Channel Data Register */
#define SARADC_6_ECDR230     SARADC_6.ECDR[102].R          /* External Channel Data Register */
#define SARADC_6_ECDR231     SARADC_6.ECDR[103].R          /* External Channel Data Register */
#define SARADC_6_ECDR232     SARADC_6.ECDR[104].R          /* External Channel Data Register */
#define SARADC_6_ECDR233     SARADC_6.ECDR[105].R          /* External Channel Data Register */
#define SARADC_6_ECDR234     SARADC_6.ECDR[106].R          /* External Channel Data Register */
#define SARADC_6_ECDR235     SARADC_6.ECDR[107].R          /* External Channel Data Register */
#define SARADC_6_ECDR236     SARADC_6.ECDR[108].R          /* External Channel Data Register */
#define SARADC_6_ECDR237     SARADC_6.ECDR[109].R          /* External Channel Data Register */
#define SARADC_6_ECDR238     SARADC_6.ECDR[110].R          /* External Channel Data Register */
#define SARADC_6_ECDR239     SARADC_6.ECDR[111].R          /* External Channel Data Register */
#define SARADC_6_ECDR240     SARADC_6.ECDR[112].R          /* External Channel Data Register */
#define SARADC_6_ECDR241     SARADC_6.ECDR[113].R          /* External Channel Data Register */
#define SARADC_6_ECDR242     SARADC_6.ECDR[114].R          /* External Channel Data Register */
#define SARADC_6_ECDR243     SARADC_6.ECDR[115].R          /* External Channel Data Register */
#define SARADC_6_ECDR244     SARADC_6.ECDR[116].R          /* External Channel Data Register */
#define SARADC_6_ECDR245     SARADC_6.ECDR[117].R          /* External Channel Data Register */
#define SARADC_6_ECDR246     SARADC_6.ECDR[118].R          /* External Channel Data Register */
#define SARADC_6_ECDR247     SARADC_6.ECDR[119].R          /* External Channel Data Register */
#define SARADC_6_ECDR248     SARADC_6.ECDR[120].R          /* External Channel Data Register */
#define SARADC_6_ECDR249     SARADC_6.ECDR[121].R          /* External Channel Data Register */
#define SARADC_6_ECDR250     SARADC_6.ECDR[122].R          /* External Channel Data Register */
#define SARADC_6_ECDR251     SARADC_6.ECDR[123].R          /* External Channel Data Register */
#define SARADC_6_ECDR252     SARADC_6.ECDR[124].R          /* External Channel Data Register */
#define SARADC_6_ECDR253     SARADC_6.ECDR[125].R          /* External Channel Data Register */
#define SARADC_6_ECDR254     SARADC_6.ECDR[126].R          /* External Channel Data Register */
#define SARADC_6_ECDR255     SARADC_6.ECDR[127].R          /* External Channel Data Register */

/* SARADC */
#define SARADC_7_MCR         SARADC_7.MCR.R                /* Main Configuration Register */
#define SARADC_7_MSR         SARADC_7.MSR.R                /* Main Status Register */
#define SARADC_7_ISR         SARADC_7.ISR.R                /* Interrupt Status Register */
#define SARADC_7_ICIPR0      SARADC_7.ICIPR[0].R           /* Internal channel Interrupt Pending Register */
#define SARADC_7_ICIPR1      SARADC_7.ICIPR[1].R           /* Internal channel Interrupt Pending Register */
#define SARADC_7_ICIPR2      SARADC_7.ICIPR[2].R           /* Internal channel Interrupt Pending Register */
#define SARADC_7_IMR         SARADC_7.IMR.R                /* Interrupt Mask Register */
#define SARADC_7_ICIMR0      SARADC_7.ICIMR[0].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_7_ICIMR1      SARADC_7.ICIMR[1].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_7_ICIMR2      SARADC_7.ICIMR[2].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_7_WTISR       SARADC_7.WTISR.R              /* Watchdog Threshold Interrupt Status Register */
#define SARADC_7_WTIMR       SARADC_7.WTIMR.R              /* Watchdog Threshold Interrupt Mask Register */
#define SARADC_7_DMAE        SARADC_7.DMAE.R               /* DMA Enable Register */
#define SARADC_7_ICDSR0      SARADC_7.ICDSR[0].R           /* Internal Channel DMA Select Register */
#define SARADC_7_ICDSR1      SARADC_7.ICDSR[1].R           /* Internal Channel DMA Select Register */
#define SARADC_7_ICDSR2      SARADC_7.ICDSR[2].R           /* Internal Channel DMA Select Register */
#define SARADC_7_WTHRHLR0    SARADC_7.WTHRHLR[0].R         /* Watchdog Threshold Register */
#define SARADC_7_WTHRHLR1    SARADC_7.WTHRHLR[1].R         /* Watchdog Threshold Register */
#define SARADC_7_WTHRHLR2    SARADC_7.WTHRHLR[2].R         /* Watchdog Threshold Register */
#define SARADC_7_WTHRHLR3    SARADC_7.WTHRHLR[3].R         /* Watchdog Threshold Register */
#define SARADC_7_CTR0        SARADC_7.CTR[0].R             /* Conversion Timing Register */
#define SARADC_7_CTR1        SARADC_7.CTR[1].R             /* Conversion Timing Register */
#define SARADC_7_CTR2        SARADC_7.CTR[2].R             /* Conversion Timing Register */
#define SARADC_7_CTR3        SARADC_7.CTR[3].R             /* Conversion Timing Register */
#define SARADC_7_ICNCMR0     SARADC_7.ICNCMR[0].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_7_ICNCMR1     SARADC_7.ICNCMR[1].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_7_ICNCMR2     SARADC_7.ICNCMR[2].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_7_ICJCMR0     SARADC_7.ICJCMR[0].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_7_ICJCMR1     SARADC_7.ICJCMR[1].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_7_ICJCMR2     SARADC_7.ICJCMR[2].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_7_PDEDR       SARADC_7.PDEDR.R              /* Power Down Exit Delay Register */
#define SARADC_7_ICDR0       SARADC_7.ICDR[0].R            /* Internal Channel Data Register */
#define SARADC_7_ICDR1       SARADC_7.ICDR[1].R            /* Internal Channel Data Register */
#define SARADC_7_ICDR2       SARADC_7.ICDR[2].R            /* Internal Channel Data Register */
#define SARADC_7_ICDR3       SARADC_7.ICDR[3].R            /* Internal Channel Data Register */
#define SARADC_7_ICDR4       SARADC_7.ICDR[4].R            /* Internal Channel Data Register */
#define SARADC_7_ICDR5       SARADC_7.ICDR[5].R            /* Internal Channel Data Register */
#define SARADC_7_ICDR6       SARADC_7.ICDR[6].R            /* Internal Channel Data Register */
#define SARADC_7_ICDR7       SARADC_7.ICDR[7].R            /* Internal Channel Data Register */
#define SARADC_7_ICDR8       SARADC_7.ICDR[8].R            /* Internal Channel Data Register */
#define SARADC_7_ICDR9       SARADC_7.ICDR[9].R            /* Internal Channel Data Register */
#define SARADC_7_ICDR10      SARADC_7.ICDR[10].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR11      SARADC_7.ICDR[11].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR12      SARADC_7.ICDR[12].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR13      SARADC_7.ICDR[13].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR14      SARADC_7.ICDR[14].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR15      SARADC_7.ICDR[15].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR16      SARADC_7.ICDR[16].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR17      SARADC_7.ICDR[17].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR18      SARADC_7.ICDR[18].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR19      SARADC_7.ICDR[19].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR20      SARADC_7.ICDR[20].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR21      SARADC_7.ICDR[21].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR22      SARADC_7.ICDR[22].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR23      SARADC_7.ICDR[23].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR24      SARADC_7.ICDR[24].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR25      SARADC_7.ICDR[25].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR26      SARADC_7.ICDR[26].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR27      SARADC_7.ICDR[27].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR28      SARADC_7.ICDR[28].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR29      SARADC_7.ICDR[29].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR30      SARADC_7.ICDR[30].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR31      SARADC_7.ICDR[31].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR32      SARADC_7.ICDR[32].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR33      SARADC_7.ICDR[33].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR34      SARADC_7.ICDR[34].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR35      SARADC_7.ICDR[35].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR36      SARADC_7.ICDR[36].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR37      SARADC_7.ICDR[37].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR38      SARADC_7.ICDR[38].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR39      SARADC_7.ICDR[39].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR40      SARADC_7.ICDR[40].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR41      SARADC_7.ICDR[41].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR42      SARADC_7.ICDR[42].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR43      SARADC_7.ICDR[43].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR44      SARADC_7.ICDR[44].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR45      SARADC_7.ICDR[45].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR46      SARADC_7.ICDR[46].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR47      SARADC_7.ICDR[47].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR48      SARADC_7.ICDR[48].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR49      SARADC_7.ICDR[49].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR50      SARADC_7.ICDR[50].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR51      SARADC_7.ICDR[51].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR52      SARADC_7.ICDR[52].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR53      SARADC_7.ICDR[53].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR54      SARADC_7.ICDR[54].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR55      SARADC_7.ICDR[55].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR56      SARADC_7.ICDR[56].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR57      SARADC_7.ICDR[57].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR58      SARADC_7.ICDR[58].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR59      SARADC_7.ICDR[59].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR60      SARADC_7.ICDR[60].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR61      SARADC_7.ICDR[61].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR62      SARADC_7.ICDR[62].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR63      SARADC_7.ICDR[63].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR64      SARADC_7.ICDR[64].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR65      SARADC_7.ICDR[65].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR66      SARADC_7.ICDR[66].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR67      SARADC_7.ICDR[67].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR68      SARADC_7.ICDR[68].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR69      SARADC_7.ICDR[69].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR70      SARADC_7.ICDR[70].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR71      SARADC_7.ICDR[71].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR72      SARADC_7.ICDR[72].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR73      SARADC_7.ICDR[73].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR74      SARADC_7.ICDR[74].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR75      SARADC_7.ICDR[75].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR76      SARADC_7.ICDR[76].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR77      SARADC_7.ICDR[77].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR78      SARADC_7.ICDR[78].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR79      SARADC_7.ICDR[79].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR80      SARADC_7.ICDR[80].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR81      SARADC_7.ICDR[81].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR82      SARADC_7.ICDR[82].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR83      SARADC_7.ICDR[83].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR84      SARADC_7.ICDR[84].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR85      SARADC_7.ICDR[85].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR86      SARADC_7.ICDR[86].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR87      SARADC_7.ICDR[87].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR88      SARADC_7.ICDR[88].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR89      SARADC_7.ICDR[89].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR90      SARADC_7.ICDR[90].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR91      SARADC_7.ICDR[91].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR92      SARADC_7.ICDR[92].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR93      SARADC_7.ICDR[93].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR94      SARADC_7.ICDR[94].R           /* Internal Channel Data Register */
#define SARADC_7_ICDR95      SARADC_7.ICDR[95].R           /* Internal Channel Data Register */
#define SARADC_7_ICWSELR0    SARADC_7.ICWSELR[0].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_7_ICWSELR1    SARADC_7.ICWSELR[1].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_7_ICWSELR2    SARADC_7.ICWSELR[2].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_7_ICWSELR3    SARADC_7.ICWSELR[3].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_7_ICWSELR4    SARADC_7.ICWSELR[4].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_7_ICWSELR5    SARADC_7.ICWSELR[5].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_7_ICWSELR6    SARADC_7.ICWSELR[6].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_7_ICWSELR7    SARADC_7.ICWSELR[7].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_7_ICWSELR8    SARADC_7.ICWSELR[8].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_7_ICWSELR9    SARADC_7.ICWSELR[9].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_7_ICWSELR10   SARADC_7.ICWSELR[10].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_7_ICWSELR11   SARADC_7.ICWSELR[11].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_7_ICWENR0     SARADC_7.ICWENR[0].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_7_ICWENR1     SARADC_7.ICWENR[1].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_7_ICWENR2     SARADC_7.ICWENR[2].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_7_ICAWORR0    SARADC_7.ICAWORR[0].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_7_ICAWORR1    SARADC_7.ICAWORR[1].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_7_ICAWORR2    SARADC_7.ICAWORR[2].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_7_TCIPR       SARADC_7.TCIPR.R              /* Test Channel Interrupt Pending Register */
#define SARADC_7_TCIMR       SARADC_7.TCIMR.R              /* Test Channel Interrupt Mask Register */
#define SARADC_7_TCDSR       SARADC_7.TCDSR.R              /* Test Channel DMA Select Register */
#define SARADC_7_TCNCMR      SARADC_7.TCNCMR.R             /* Test Channel Normal Conversion Mask Register */
#define SARADC_7_TCJCMR      SARADC_7.TCJCMR.R             /* Test Channel Injected Conversion Mask Register */
#define SARADC_7_TCWSELR0    SARADC_7.TCWSELR[0].R         /* Test Channel Watchdog Selection Register */
#define SARADC_7_TCWSELR1    SARADC_7.TCWSELR[1].R         /* Test Channel Watchdog Selection Register */
#define SARADC_7_TCWSELR2    SARADC_7.TCWSELR[2].R         /* Test Channel Watchdog Selection Register */
#define SARADC_7_TCWSELR3    SARADC_7.TCWSELR[3].R         /* Test Channel Watchdog Selection Register */
#define SARADC_7_TCWENR      SARADC_7.TCWENR.R             /* Test Channel Watchdog Enable Register */
#define SARADC_7_TCAWORR     SARADC_7.TCAWORR.R            /* Test Channel Analog Watchdog Out of Range Register */
#define SARADC_7_TCCAPR0     SARADC_7.TCCAPR[0].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_7_TCCAPR1     SARADC_7.TCCAPR[1].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_7_TCCAPR2     SARADC_7.TCCAPR[2].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_7_TCCAPR3     SARADC_7.TCCAPR[3].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_7_TCCAPR4     SARADC_7.TCCAPR[4].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_7_TCCAPR5     SARADC_7.TCCAPR[5].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_7_TCCAPR6     SARADC_7.TCCAPR[6].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_7_TCCAPR7     SARADC_7.TCCAPR[7].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_7_TCDR96      SARADC_7.TCDR[0].R            /* Test Channel Data Register */
#define SARADC_7_TCDR97      SARADC_7.TCDR[1].R            /* Test Channel Data Register */
#define SARADC_7_TCDR98      SARADC_7.TCDR[2].R            /* Test Channel Data Register */
#define SARADC_7_TCDR99      SARADC_7.TCDR[3].R            /* Test Channel Data Register */
#define SARADC_7_TCDR100     SARADC_7.TCDR[4].R            /* Test Channel Data Register */
#define SARADC_7_TCDR101     SARADC_7.TCDR[5].R            /* Test Channel Data Register */
#define SARADC_7_TCDR102     SARADC_7.TCDR[6].R            /* Test Channel Data Register */
#define SARADC_7_TCDR103     SARADC_7.TCDR[7].R            /* Test Channel Data Register */
#define SARADC_7_TCDR104     SARADC_7.TCDR[8].R            /* Test Channel Data Register */
#define SARADC_7_TCDR105     SARADC_7.TCDR[9].R            /* Test Channel Data Register */
#define SARADC_7_TCDR106     SARADC_7.TCDR[10].R           /* Test Channel Data Register */
#define SARADC_7_TCDR107     SARADC_7.TCDR[11].R           /* Test Channel Data Register */
#define SARADC_7_TCDR108     SARADC_7.TCDR[12].R           /* Test Channel Data Register */
#define SARADC_7_TCDR109     SARADC_7.TCDR[13].R           /* Test Channel Data Register */
#define SARADC_7_TCDR110     SARADC_7.TCDR[14].R           /* Test Channel Data Register */
#define SARADC_7_TCDR111     SARADC_7.TCDR[15].R           /* Test Channel Data Register */
#define SARADC_7_TCDR112     SARADC_7.TCDR[16].R           /* Test Channel Data Register */
#define SARADC_7_TCDR113     SARADC_7.TCDR[17].R           /* Test Channel Data Register */
#define SARADC_7_TCDR114     SARADC_7.TCDR[18].R           /* Test Channel Data Register */
#define SARADC_7_TCDR115     SARADC_7.TCDR[19].R           /* Test Channel Data Register */
#define SARADC_7_TCDR116     SARADC_7.TCDR[20].R           /* Test Channel Data Register */
#define SARADC_7_TCDR117     SARADC_7.TCDR[21].R           /* Test Channel Data Register */
#define SARADC_7_TCDR118     SARADC_7.TCDR[22].R           /* Test Channel Data Register */
#define SARADC_7_TCDR119     SARADC_7.TCDR[23].R           /* Test Channel Data Register */
#define SARADC_7_TCDR120     SARADC_7.TCDR[24].R           /* Test Channel Data Register */
#define SARADC_7_TCDR121     SARADC_7.TCDR[25].R           /* Test Channel Data Register */
#define SARADC_7_TCDR122     SARADC_7.TCDR[26].R           /* Test Channel Data Register */
#define SARADC_7_TCDR123     SARADC_7.TCDR[27].R           /* Test Channel Data Register */
#define SARADC_7_TCDR124     SARADC_7.TCDR[28].R           /* Test Channel Data Register */
#define SARADC_7_TCDR125     SARADC_7.TCDR[29].R           /* Test Channel Data Register */
#define SARADC_7_TCDR126     SARADC_7.TCDR[30].R           /* Test Channel Data Register */
#define SARADC_7_TCDR127     SARADC_7.TCDR[31].R           /* Test Channel Data Register */
#define SARADC_7_ECDSDR      SARADC_7.ECDSDR.R             /* External Channel Decode Signals Delay Register */
#define SARADC_7_ECIPR0      SARADC_7.ECIPR[0].R           /* External Channel Interrupt Pending Register */
#define SARADC_7_ECIPR1      SARADC_7.ECIPR[1].R           /* External Channel Interrupt Pending Register */
#define SARADC_7_ECIPR2      SARADC_7.ECIPR[2].R           /* External Channel Interrupt Pending Register */
#define SARADC_7_ECIPR3      SARADC_7.ECIPR[3].R           /* External Channel Interrupt Pending Register */
#define SARADC_7_ECIMR0      SARADC_7.ECIMR[0].R           /* External Channel Interrupt Mask Register */
#define SARADC_7_ECIMR1      SARADC_7.ECIMR[1].R           /* External Channel Interrupt Mask Register */
#define SARADC_7_ECIMR2      SARADC_7.ECIMR[2].R           /* External Channel Interrupt Mask Register */
#define SARADC_7_ECIMR3      SARADC_7.ECIMR[3].R           /* External Channel Interrupt Mask Register */
#define SARADC_7_ECDSR0      SARADC_7.ECDSR[0].R           /* External Channel DMA Select Register */
#define SARADC_7_ECDSR1      SARADC_7.ECDSR[1].R           /* External Channel DMA Select Register */
#define SARADC_7_ECDSR2      SARADC_7.ECDSR[2].R           /* External Channel DMA Select Register */
#define SARADC_7_ECDSR3      SARADC_7.ECDSR[3].R           /* External Channel DMA Select Register */
#define SARADC_7_ECNCMR0     SARADC_7.ECNCMR[0].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_7_ECNCMR1     SARADC_7.ECNCMR[1].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_7_ECNCMR2     SARADC_7.ECNCMR[2].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_7_ECNCMR3     SARADC_7.ECNCMR[3].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_7_ECJCMR0     SARADC_7.ECJCMR[0].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_7_ECJCMR1     SARADC_7.ECJCMR[1].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_7_ECJCMR2     SARADC_7.ECJCMR[2].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_7_ECJCMR3     SARADC_7.ECJCMR[3].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_7_ECWSELR0    SARADC_7.ECWSELR[0].R         /* External Channel Watchdog Selection Register */
#define SARADC_7_ECWSELR1    SARADC_7.ECWSELR[1].R         /* External Channel Watchdog Selection Register */
#define SARADC_7_ECWSELR2    SARADC_7.ECWSELR[2].R         /* External Channel Watchdog Selection Register */
#define SARADC_7_ECWSELR3    SARADC_7.ECWSELR[3].R         /* External Channel Watchdog Selection Register */
#define SARADC_7_ECWSELR4    SARADC_7.ECWSELR[4].R         /* External Channel Watchdog Selection Register */
#define SARADC_7_ECWSELR5    SARADC_7.ECWSELR[5].R         /* External Channel Watchdog Selection Register */
#define SARADC_7_ECWSELR6    SARADC_7.ECWSELR[6].R         /* External Channel Watchdog Selection Register */
#define SARADC_7_ECWSELR7    SARADC_7.ECWSELR[7].R         /* External Channel Watchdog Selection Register */
#define SARADC_7_ECWSELR8    SARADC_7.ECWSELR[8].R         /* External Channel Watchdog Selection Register */
#define SARADC_7_ECWSELR9    SARADC_7.ECWSELR[9].R         /* External Channel Watchdog Selection Register */
#define SARADC_7_ECWSELR10   SARADC_7.ECWSELR[10].R        /* External Channel Watchdog Selection Register */
#define SARADC_7_ECWSELR11   SARADC_7.ECWSELR[11].R        /* External Channel Watchdog Selection Register */
#define SARADC_7_ECWSELR12   SARADC_7.ECWSELR[12].R        /* External Channel Watchdog Selection Register */
#define SARADC_7_ECWSELR13   SARADC_7.ECWSELR[13].R        /* External Channel Watchdog Selection Register */
#define SARADC_7_ECWSELR14   SARADC_7.ECWSELR[14].R        /* External Channel Watchdog Selection Register */
#define SARADC_7_ECWSELR15   SARADC_7.ECWSELR[15].R        /* External Channel Watchdog Selection Register */
#define SARADC_7_ECWENR0     SARADC_7.ECWENR[0].R          /* External Channel Watchdog Enable Register */
#define SARADC_7_ECWENR1     SARADC_7.ECWENR[1].R          /* External Channel Watchdog Enable Register */
#define SARADC_7_ECWENR2     SARADC_7.ECWENR[2].R          /* External Channel Watchdog Enable Register */
#define SARADC_7_ECWENR3     SARADC_7.ECWENR[3].R          /* External Channel Watchdog Enable Register */
#define SARADC_7_ECAWORR0    SARADC_7.ECAWORR[0].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_7_ECAWORR1    SARADC_7.ECAWORR[1].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_7_ECAWORR2    SARADC_7.ECAWORR[2].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_7_ECAWORR3    SARADC_7.ECAWORR[3].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_7_ECMICR0     SARADC_7.ECMICR[0].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_7_ECMICR1     SARADC_7.ECMICR[1].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_7_ECMICR2     SARADC_7.ECMICR[2].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_7_ECMICR3     SARADC_7.ECMICR[3].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_7_ECDR128     SARADC_7.ECDR[0].R            /* External Channel Data Register */
#define SARADC_7_ECDR129     SARADC_7.ECDR[1].R            /* External Channel Data Register */
#define SARADC_7_ECDR130     SARADC_7.ECDR[2].R            /* External Channel Data Register */
#define SARADC_7_ECDR131     SARADC_7.ECDR[3].R            /* External Channel Data Register */
#define SARADC_7_ECDR132     SARADC_7.ECDR[4].R            /* External Channel Data Register */
#define SARADC_7_ECDR133     SARADC_7.ECDR[5].R            /* External Channel Data Register */
#define SARADC_7_ECDR134     SARADC_7.ECDR[6].R            /* External Channel Data Register */
#define SARADC_7_ECDR135     SARADC_7.ECDR[7].R            /* External Channel Data Register */
#define SARADC_7_ECDR136     SARADC_7.ECDR[8].R            /* External Channel Data Register */
#define SARADC_7_ECDR137     SARADC_7.ECDR[9].R            /* External Channel Data Register */
#define SARADC_7_ECDR138     SARADC_7.ECDR[10].R           /* External Channel Data Register */
#define SARADC_7_ECDR139     SARADC_7.ECDR[11].R           /* External Channel Data Register */
#define SARADC_7_ECDR140     SARADC_7.ECDR[12].R           /* External Channel Data Register */
#define SARADC_7_ECDR141     SARADC_7.ECDR[13].R           /* External Channel Data Register */
#define SARADC_7_ECDR142     SARADC_7.ECDR[14].R           /* External Channel Data Register */
#define SARADC_7_ECDR143     SARADC_7.ECDR[15].R           /* External Channel Data Register */
#define SARADC_7_ECDR144     SARADC_7.ECDR[16].R           /* External Channel Data Register */
#define SARADC_7_ECDR145     SARADC_7.ECDR[17].R           /* External Channel Data Register */
#define SARADC_7_ECDR146     SARADC_7.ECDR[18].R           /* External Channel Data Register */
#define SARADC_7_ECDR147     SARADC_7.ECDR[19].R           /* External Channel Data Register */
#define SARADC_7_ECDR148     SARADC_7.ECDR[20].R           /* External Channel Data Register */
#define SARADC_7_ECDR149     SARADC_7.ECDR[21].R           /* External Channel Data Register */
#define SARADC_7_ECDR150     SARADC_7.ECDR[22].R           /* External Channel Data Register */
#define SARADC_7_ECDR151     SARADC_7.ECDR[23].R           /* External Channel Data Register */
#define SARADC_7_ECDR152     SARADC_7.ECDR[24].R           /* External Channel Data Register */
#define SARADC_7_ECDR153     SARADC_7.ECDR[25].R           /* External Channel Data Register */
#define SARADC_7_ECDR154     SARADC_7.ECDR[26].R           /* External Channel Data Register */
#define SARADC_7_ECDR155     SARADC_7.ECDR[27].R           /* External Channel Data Register */
#define SARADC_7_ECDR156     SARADC_7.ECDR[28].R           /* External Channel Data Register */
#define SARADC_7_ECDR157     SARADC_7.ECDR[29].R           /* External Channel Data Register */
#define SARADC_7_ECDR158     SARADC_7.ECDR[30].R           /* External Channel Data Register */
#define SARADC_7_ECDR159     SARADC_7.ECDR[31].R           /* External Channel Data Register */
#define SARADC_7_ECDR160     SARADC_7.ECDR[32].R           /* External Channel Data Register */
#define SARADC_7_ECDR161     SARADC_7.ECDR[33].R           /* External Channel Data Register */
#define SARADC_7_ECDR162     SARADC_7.ECDR[34].R           /* External Channel Data Register */
#define SARADC_7_ECDR163     SARADC_7.ECDR[35].R           /* External Channel Data Register */
#define SARADC_7_ECDR164     SARADC_7.ECDR[36].R           /* External Channel Data Register */
#define SARADC_7_ECDR165     SARADC_7.ECDR[37].R           /* External Channel Data Register */
#define SARADC_7_ECDR166     SARADC_7.ECDR[38].R           /* External Channel Data Register */
#define SARADC_7_ECDR167     SARADC_7.ECDR[39].R           /* External Channel Data Register */
#define SARADC_7_ECDR168     SARADC_7.ECDR[40].R           /* External Channel Data Register */
#define SARADC_7_ECDR169     SARADC_7.ECDR[41].R           /* External Channel Data Register */
#define SARADC_7_ECDR170     SARADC_7.ECDR[42].R           /* External Channel Data Register */
#define SARADC_7_ECDR171     SARADC_7.ECDR[43].R           /* External Channel Data Register */
#define SARADC_7_ECDR172     SARADC_7.ECDR[44].R           /* External Channel Data Register */
#define SARADC_7_ECDR173     SARADC_7.ECDR[45].R           /* External Channel Data Register */
#define SARADC_7_ECDR174     SARADC_7.ECDR[46].R           /* External Channel Data Register */
#define SARADC_7_ECDR175     SARADC_7.ECDR[47].R           /* External Channel Data Register */
#define SARADC_7_ECDR176     SARADC_7.ECDR[48].R           /* External Channel Data Register */
#define SARADC_7_ECDR177     SARADC_7.ECDR[49].R           /* External Channel Data Register */
#define SARADC_7_ECDR178     SARADC_7.ECDR[50].R           /* External Channel Data Register */
#define SARADC_7_ECDR179     SARADC_7.ECDR[51].R           /* External Channel Data Register */
#define SARADC_7_ECDR180     SARADC_7.ECDR[52].R           /* External Channel Data Register */
#define SARADC_7_ECDR181     SARADC_7.ECDR[53].R           /* External Channel Data Register */
#define SARADC_7_ECDR182     SARADC_7.ECDR[54].R           /* External Channel Data Register */
#define SARADC_7_ECDR183     SARADC_7.ECDR[55].R           /* External Channel Data Register */
#define SARADC_7_ECDR184     SARADC_7.ECDR[56].R           /* External Channel Data Register */
#define SARADC_7_ECDR185     SARADC_7.ECDR[57].R           /* External Channel Data Register */
#define SARADC_7_ECDR186     SARADC_7.ECDR[58].R           /* External Channel Data Register */
#define SARADC_7_ECDR187     SARADC_7.ECDR[59].R           /* External Channel Data Register */
#define SARADC_7_ECDR188     SARADC_7.ECDR[60].R           /* External Channel Data Register */
#define SARADC_7_ECDR189     SARADC_7.ECDR[61].R           /* External Channel Data Register */
#define SARADC_7_ECDR190     SARADC_7.ECDR[62].R           /* External Channel Data Register */
#define SARADC_7_ECDR191     SARADC_7.ECDR[63].R           /* External Channel Data Register */
#define SARADC_7_ECDR192     SARADC_7.ECDR[64].R           /* External Channel Data Register */
#define SARADC_7_ECDR193     SARADC_7.ECDR[65].R           /* External Channel Data Register */
#define SARADC_7_ECDR194     SARADC_7.ECDR[66].R           /* External Channel Data Register */
#define SARADC_7_ECDR195     SARADC_7.ECDR[67].R           /* External Channel Data Register */
#define SARADC_7_ECDR196     SARADC_7.ECDR[68].R           /* External Channel Data Register */
#define SARADC_7_ECDR197     SARADC_7.ECDR[69].R           /* External Channel Data Register */
#define SARADC_7_ECDR198     SARADC_7.ECDR[70].R           /* External Channel Data Register */
#define SARADC_7_ECDR199     SARADC_7.ECDR[71].R           /* External Channel Data Register */
#define SARADC_7_ECDR200     SARADC_7.ECDR[72].R           /* External Channel Data Register */
#define SARADC_7_ECDR201     SARADC_7.ECDR[73].R           /* External Channel Data Register */
#define SARADC_7_ECDR202     SARADC_7.ECDR[74].R           /* External Channel Data Register */
#define SARADC_7_ECDR203     SARADC_7.ECDR[75].R           /* External Channel Data Register */
#define SARADC_7_ECDR204     SARADC_7.ECDR[76].R           /* External Channel Data Register */
#define SARADC_7_ECDR205     SARADC_7.ECDR[77].R           /* External Channel Data Register */
#define SARADC_7_ECDR206     SARADC_7.ECDR[78].R           /* External Channel Data Register */
#define SARADC_7_ECDR207     SARADC_7.ECDR[79].R           /* External Channel Data Register */
#define SARADC_7_ECDR208     SARADC_7.ECDR[80].R           /* External Channel Data Register */
#define SARADC_7_ECDR209     SARADC_7.ECDR[81].R           /* External Channel Data Register */
#define SARADC_7_ECDR210     SARADC_7.ECDR[82].R           /* External Channel Data Register */
#define SARADC_7_ECDR211     SARADC_7.ECDR[83].R           /* External Channel Data Register */
#define SARADC_7_ECDR212     SARADC_7.ECDR[84].R           /* External Channel Data Register */
#define SARADC_7_ECDR213     SARADC_7.ECDR[85].R           /* External Channel Data Register */
#define SARADC_7_ECDR214     SARADC_7.ECDR[86].R           /* External Channel Data Register */
#define SARADC_7_ECDR215     SARADC_7.ECDR[87].R           /* External Channel Data Register */
#define SARADC_7_ECDR216     SARADC_7.ECDR[88].R           /* External Channel Data Register */
#define SARADC_7_ECDR217     SARADC_7.ECDR[89].R           /* External Channel Data Register */
#define SARADC_7_ECDR218     SARADC_7.ECDR[90].R           /* External Channel Data Register */
#define SARADC_7_ECDR219     SARADC_7.ECDR[91].R           /* External Channel Data Register */
#define SARADC_7_ECDR220     SARADC_7.ECDR[92].R           /* External Channel Data Register */
#define SARADC_7_ECDR221     SARADC_7.ECDR[93].R           /* External Channel Data Register */
#define SARADC_7_ECDR222     SARADC_7.ECDR[94].R           /* External Channel Data Register */
#define SARADC_7_ECDR223     SARADC_7.ECDR[95].R           /* External Channel Data Register */
#define SARADC_7_ECDR224     SARADC_7.ECDR[96].R           /* External Channel Data Register */
#define SARADC_7_ECDR225     SARADC_7.ECDR[97].R           /* External Channel Data Register */
#define SARADC_7_ECDR226     SARADC_7.ECDR[98].R           /* External Channel Data Register */
#define SARADC_7_ECDR227     SARADC_7.ECDR[99].R           /* External Channel Data Register */
#define SARADC_7_ECDR228     SARADC_7.ECDR[100].R          /* External Channel Data Register */
#define SARADC_7_ECDR229     SARADC_7.ECDR[101].R          /* External Channel Data Register */
#define SARADC_7_ECDR230     SARADC_7.ECDR[102].R          /* External Channel Data Register */
#define SARADC_7_ECDR231     SARADC_7.ECDR[103].R          /* External Channel Data Register */
#define SARADC_7_ECDR232     SARADC_7.ECDR[104].R          /* External Channel Data Register */
#define SARADC_7_ECDR233     SARADC_7.ECDR[105].R          /* External Channel Data Register */
#define SARADC_7_ECDR234     SARADC_7.ECDR[106].R          /* External Channel Data Register */
#define SARADC_7_ECDR235     SARADC_7.ECDR[107].R          /* External Channel Data Register */
#define SARADC_7_ECDR236     SARADC_7.ECDR[108].R          /* External Channel Data Register */
#define SARADC_7_ECDR237     SARADC_7.ECDR[109].R          /* External Channel Data Register */
#define SARADC_7_ECDR238     SARADC_7.ECDR[110].R          /* External Channel Data Register */
#define SARADC_7_ECDR239     SARADC_7.ECDR[111].R          /* External Channel Data Register */
#define SARADC_7_ECDR240     SARADC_7.ECDR[112].R          /* External Channel Data Register */
#define SARADC_7_ECDR241     SARADC_7.ECDR[113].R          /* External Channel Data Register */
#define SARADC_7_ECDR242     SARADC_7.ECDR[114].R          /* External Channel Data Register */
#define SARADC_7_ECDR243     SARADC_7.ECDR[115].R          /* External Channel Data Register */
#define SARADC_7_ECDR244     SARADC_7.ECDR[116].R          /* External Channel Data Register */
#define SARADC_7_ECDR245     SARADC_7.ECDR[117].R          /* External Channel Data Register */
#define SARADC_7_ECDR246     SARADC_7.ECDR[118].R          /* External Channel Data Register */
#define SARADC_7_ECDR247     SARADC_7.ECDR[119].R          /* External Channel Data Register */
#define SARADC_7_ECDR248     SARADC_7.ECDR[120].R          /* External Channel Data Register */
#define SARADC_7_ECDR249     SARADC_7.ECDR[121].R          /* External Channel Data Register */
#define SARADC_7_ECDR250     SARADC_7.ECDR[122].R          /* External Channel Data Register */
#define SARADC_7_ECDR251     SARADC_7.ECDR[123].R          /* External Channel Data Register */
#define SARADC_7_ECDR252     SARADC_7.ECDR[124].R          /* External Channel Data Register */
#define SARADC_7_ECDR253     SARADC_7.ECDR[125].R          /* External Channel Data Register */
#define SARADC_7_ECDR254     SARADC_7.ECDR[126].R          /* External Channel Data Register */
#define SARADC_7_ECDR255     SARADC_7.ECDR[127].R          /* External Channel Data Register */

/* SARADC */
#define SARADC_8_MCR         SARADC_8.MCR.R                /* Main Configuration Register */
#define SARADC_8_MSR         SARADC_8.MSR.R                /* Main Status Register */
#define SARADC_8_ISR         SARADC_8.ISR.R                /* Interrupt Status Register */
#define SARADC_8_ICIPR0      SARADC_8.ICIPR[0].R           /* Internal channel Interrupt Pending Register */
#define SARADC_8_ICIPR1      SARADC_8.ICIPR[1].R           /* Internal channel Interrupt Pending Register */
#define SARADC_8_ICIPR2      SARADC_8.ICIPR[2].R           /* Internal channel Interrupt Pending Register */
#define SARADC_8_IMR         SARADC_8.IMR.R                /* Interrupt Mask Register */
#define SARADC_8_ICIMR0      SARADC_8.ICIMR[0].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_8_ICIMR1      SARADC_8.ICIMR[1].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_8_ICIMR2      SARADC_8.ICIMR[2].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_8_WTISR       SARADC_8.WTISR.R              /* Watchdog Threshold Interrupt Status Register */
#define SARADC_8_WTIMR       SARADC_8.WTIMR.R              /* Watchdog Threshold Interrupt Mask Register */
#define SARADC_8_DMAE        SARADC_8.DMAE.R               /* DMA Enable Register */
#define SARADC_8_ICDSR0      SARADC_8.ICDSR[0].R           /* Internal Channel DMA Select Register */
#define SARADC_8_ICDSR1      SARADC_8.ICDSR[1].R           /* Internal Channel DMA Select Register */
#define SARADC_8_ICDSR2      SARADC_8.ICDSR[2].R           /* Internal Channel DMA Select Register */
#define SARADC_8_WTHRHLR0    SARADC_8.WTHRHLR[0].R         /* Watchdog Threshold Register */
#define SARADC_8_WTHRHLR1    SARADC_8.WTHRHLR[1].R         /* Watchdog Threshold Register */
#define SARADC_8_WTHRHLR2    SARADC_8.WTHRHLR[2].R         /* Watchdog Threshold Register */
#define SARADC_8_WTHRHLR3    SARADC_8.WTHRHLR[3].R         /* Watchdog Threshold Register */
#define SARADC_8_CTR0        SARADC_8.CTR[0].R             /* Conversion Timing Register */
#define SARADC_8_CTR1        SARADC_8.CTR[1].R             /* Conversion Timing Register */
#define SARADC_8_CTR2        SARADC_8.CTR[2].R             /* Conversion Timing Register */
#define SARADC_8_CTR3        SARADC_8.CTR[3].R             /* Conversion Timing Register */
#define SARADC_8_ICNCMR0     SARADC_8.ICNCMR[0].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_8_ICNCMR1     SARADC_8.ICNCMR[1].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_8_ICNCMR2     SARADC_8.ICNCMR[2].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_8_ICJCMR0     SARADC_8.ICJCMR[0].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_8_ICJCMR1     SARADC_8.ICJCMR[1].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_8_ICJCMR2     SARADC_8.ICJCMR[2].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_8_PDEDR       SARADC_8.PDEDR.R              /* Power Down Exit Delay Register */
#define SARADC_8_ICDR0       SARADC_8.ICDR[0].R            /* Internal Channel Data Register */
#define SARADC_8_ICDR1       SARADC_8.ICDR[1].R            /* Internal Channel Data Register */
#define SARADC_8_ICDR2       SARADC_8.ICDR[2].R            /* Internal Channel Data Register */
#define SARADC_8_ICDR3       SARADC_8.ICDR[3].R            /* Internal Channel Data Register */
#define SARADC_8_ICDR4       SARADC_8.ICDR[4].R            /* Internal Channel Data Register */
#define SARADC_8_ICDR5       SARADC_8.ICDR[5].R            /* Internal Channel Data Register */
#define SARADC_8_ICDR6       SARADC_8.ICDR[6].R            /* Internal Channel Data Register */
#define SARADC_8_ICDR7       SARADC_8.ICDR[7].R            /* Internal Channel Data Register */
#define SARADC_8_ICDR8       SARADC_8.ICDR[8].R            /* Internal Channel Data Register */
#define SARADC_8_ICDR9       SARADC_8.ICDR[9].R            /* Internal Channel Data Register */
#define SARADC_8_ICDR10      SARADC_8.ICDR[10].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR11      SARADC_8.ICDR[11].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR12      SARADC_8.ICDR[12].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR13      SARADC_8.ICDR[13].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR14      SARADC_8.ICDR[14].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR15      SARADC_8.ICDR[15].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR16      SARADC_8.ICDR[16].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR17      SARADC_8.ICDR[17].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR18      SARADC_8.ICDR[18].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR19      SARADC_8.ICDR[19].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR20      SARADC_8.ICDR[20].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR21      SARADC_8.ICDR[21].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR22      SARADC_8.ICDR[22].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR23      SARADC_8.ICDR[23].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR24      SARADC_8.ICDR[24].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR25      SARADC_8.ICDR[25].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR26      SARADC_8.ICDR[26].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR27      SARADC_8.ICDR[27].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR28      SARADC_8.ICDR[28].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR29      SARADC_8.ICDR[29].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR30      SARADC_8.ICDR[30].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR31      SARADC_8.ICDR[31].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR32      SARADC_8.ICDR[32].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR33      SARADC_8.ICDR[33].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR34      SARADC_8.ICDR[34].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR35      SARADC_8.ICDR[35].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR36      SARADC_8.ICDR[36].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR37      SARADC_8.ICDR[37].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR38      SARADC_8.ICDR[38].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR39      SARADC_8.ICDR[39].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR40      SARADC_8.ICDR[40].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR41      SARADC_8.ICDR[41].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR42      SARADC_8.ICDR[42].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR43      SARADC_8.ICDR[43].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR44      SARADC_8.ICDR[44].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR45      SARADC_8.ICDR[45].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR46      SARADC_8.ICDR[46].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR47      SARADC_8.ICDR[47].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR48      SARADC_8.ICDR[48].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR49      SARADC_8.ICDR[49].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR50      SARADC_8.ICDR[50].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR51      SARADC_8.ICDR[51].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR52      SARADC_8.ICDR[52].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR53      SARADC_8.ICDR[53].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR54      SARADC_8.ICDR[54].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR55      SARADC_8.ICDR[55].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR56      SARADC_8.ICDR[56].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR57      SARADC_8.ICDR[57].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR58      SARADC_8.ICDR[58].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR59      SARADC_8.ICDR[59].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR60      SARADC_8.ICDR[60].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR61      SARADC_8.ICDR[61].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR62      SARADC_8.ICDR[62].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR63      SARADC_8.ICDR[63].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR64      SARADC_8.ICDR[64].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR65      SARADC_8.ICDR[65].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR66      SARADC_8.ICDR[66].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR67      SARADC_8.ICDR[67].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR68      SARADC_8.ICDR[68].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR69      SARADC_8.ICDR[69].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR70      SARADC_8.ICDR[70].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR71      SARADC_8.ICDR[71].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR72      SARADC_8.ICDR[72].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR73      SARADC_8.ICDR[73].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR74      SARADC_8.ICDR[74].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR75      SARADC_8.ICDR[75].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR76      SARADC_8.ICDR[76].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR77      SARADC_8.ICDR[77].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR78      SARADC_8.ICDR[78].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR79      SARADC_8.ICDR[79].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR80      SARADC_8.ICDR[80].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR81      SARADC_8.ICDR[81].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR82      SARADC_8.ICDR[82].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR83      SARADC_8.ICDR[83].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR84      SARADC_8.ICDR[84].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR85      SARADC_8.ICDR[85].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR86      SARADC_8.ICDR[86].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR87      SARADC_8.ICDR[87].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR88      SARADC_8.ICDR[88].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR89      SARADC_8.ICDR[89].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR90      SARADC_8.ICDR[90].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR91      SARADC_8.ICDR[91].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR92      SARADC_8.ICDR[92].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR93      SARADC_8.ICDR[93].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR94      SARADC_8.ICDR[94].R           /* Internal Channel Data Register */
#define SARADC_8_ICDR95      SARADC_8.ICDR[95].R           /* Internal Channel Data Register */
#define SARADC_8_ICWSELR0    SARADC_8.ICWSELR[0].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_8_ICWSELR1    SARADC_8.ICWSELR[1].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_8_ICWSELR2    SARADC_8.ICWSELR[2].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_8_ICWSELR3    SARADC_8.ICWSELR[3].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_8_ICWSELR4    SARADC_8.ICWSELR[4].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_8_ICWSELR5    SARADC_8.ICWSELR[5].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_8_ICWSELR6    SARADC_8.ICWSELR[6].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_8_ICWSELR7    SARADC_8.ICWSELR[7].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_8_ICWSELR8    SARADC_8.ICWSELR[8].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_8_ICWSELR9    SARADC_8.ICWSELR[9].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_8_ICWSELR10   SARADC_8.ICWSELR[10].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_8_ICWSELR11   SARADC_8.ICWSELR[11].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_8_ICWENR0     SARADC_8.ICWENR[0].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_8_ICWENR1     SARADC_8.ICWENR[1].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_8_ICWENR2     SARADC_8.ICWENR[2].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_8_ICAWORR0    SARADC_8.ICAWORR[0].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_8_ICAWORR1    SARADC_8.ICAWORR[1].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_8_ICAWORR2    SARADC_8.ICAWORR[2].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_8_TCIPR       SARADC_8.TCIPR.R              /* Test Channel Interrupt Pending Register */
#define SARADC_8_TCIMR       SARADC_8.TCIMR.R              /* Test Channel Interrupt Mask Register */
#define SARADC_8_TCDSR       SARADC_8.TCDSR.R              /* Test Channel DMA Select Register */
#define SARADC_8_TCNCMR      SARADC_8.TCNCMR.R             /* Test Channel Normal Conversion Mask Register */
#define SARADC_8_TCJCMR      SARADC_8.TCJCMR.R             /* Test Channel Injected Conversion Mask Register */
#define SARADC_8_TCWSELR0    SARADC_8.TCWSELR[0].R         /* Test Channel Watchdog Selection Register */
#define SARADC_8_TCWSELR1    SARADC_8.TCWSELR[1].R         /* Test Channel Watchdog Selection Register */
#define SARADC_8_TCWSELR2    SARADC_8.TCWSELR[2].R         /* Test Channel Watchdog Selection Register */
#define SARADC_8_TCWSELR3    SARADC_8.TCWSELR[3].R         /* Test Channel Watchdog Selection Register */
#define SARADC_8_TCWENR      SARADC_8.TCWENR.R             /* Test Channel Watchdog Enable Register */
#define SARADC_8_TCAWORR     SARADC_8.TCAWORR.R            /* Test Channel Analog Watchdog Out of Range Register */
#define SARADC_8_TCCAPR0     SARADC_8.TCCAPR[0].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_8_TCCAPR1     SARADC_8.TCCAPR[1].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_8_TCCAPR2     SARADC_8.TCCAPR[2].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_8_TCCAPR3     SARADC_8.TCCAPR[3].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_8_TCCAPR4     SARADC_8.TCCAPR[4].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_8_TCCAPR5     SARADC_8.TCCAPR[5].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_8_TCCAPR6     SARADC_8.TCCAPR[6].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_8_TCCAPR7     SARADC_8.TCCAPR[7].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_8_TCDR96      SARADC_8.TCDR[0].R            /* Test Channel Data Register */
#define SARADC_8_TCDR97      SARADC_8.TCDR[1].R            /* Test Channel Data Register */
#define SARADC_8_TCDR98      SARADC_8.TCDR[2].R            /* Test Channel Data Register */
#define SARADC_8_TCDR99      SARADC_8.TCDR[3].R            /* Test Channel Data Register */
#define SARADC_8_TCDR100     SARADC_8.TCDR[4].R            /* Test Channel Data Register */
#define SARADC_8_TCDR101     SARADC_8.TCDR[5].R            /* Test Channel Data Register */
#define SARADC_8_TCDR102     SARADC_8.TCDR[6].R            /* Test Channel Data Register */
#define SARADC_8_TCDR103     SARADC_8.TCDR[7].R            /* Test Channel Data Register */
#define SARADC_8_TCDR104     SARADC_8.TCDR[8].R            /* Test Channel Data Register */
#define SARADC_8_TCDR105     SARADC_8.TCDR[9].R            /* Test Channel Data Register */
#define SARADC_8_TCDR106     SARADC_8.TCDR[10].R           /* Test Channel Data Register */
#define SARADC_8_TCDR107     SARADC_8.TCDR[11].R           /* Test Channel Data Register */
#define SARADC_8_TCDR108     SARADC_8.TCDR[12].R           /* Test Channel Data Register */
#define SARADC_8_TCDR109     SARADC_8.TCDR[13].R           /* Test Channel Data Register */
#define SARADC_8_TCDR110     SARADC_8.TCDR[14].R           /* Test Channel Data Register */
#define SARADC_8_TCDR111     SARADC_8.TCDR[15].R           /* Test Channel Data Register */
#define SARADC_8_TCDR112     SARADC_8.TCDR[16].R           /* Test Channel Data Register */
#define SARADC_8_TCDR113     SARADC_8.TCDR[17].R           /* Test Channel Data Register */
#define SARADC_8_TCDR114     SARADC_8.TCDR[18].R           /* Test Channel Data Register */
#define SARADC_8_TCDR115     SARADC_8.TCDR[19].R           /* Test Channel Data Register */
#define SARADC_8_TCDR116     SARADC_8.TCDR[20].R           /* Test Channel Data Register */
#define SARADC_8_TCDR117     SARADC_8.TCDR[21].R           /* Test Channel Data Register */
#define SARADC_8_TCDR118     SARADC_8.TCDR[22].R           /* Test Channel Data Register */
#define SARADC_8_TCDR119     SARADC_8.TCDR[23].R           /* Test Channel Data Register */
#define SARADC_8_TCDR120     SARADC_8.TCDR[24].R           /* Test Channel Data Register */
#define SARADC_8_TCDR121     SARADC_8.TCDR[25].R           /* Test Channel Data Register */
#define SARADC_8_TCDR122     SARADC_8.TCDR[26].R           /* Test Channel Data Register */
#define SARADC_8_TCDR123     SARADC_8.TCDR[27].R           /* Test Channel Data Register */
#define SARADC_8_TCDR124     SARADC_8.TCDR[28].R           /* Test Channel Data Register */
#define SARADC_8_TCDR125     SARADC_8.TCDR[29].R           /* Test Channel Data Register */
#define SARADC_8_TCDR126     SARADC_8.TCDR[30].R           /* Test Channel Data Register */
#define SARADC_8_TCDR127     SARADC_8.TCDR[31].R           /* Test Channel Data Register */
#define SARADC_8_ECDSDR      SARADC_8.ECDSDR.R             /* External Channel Decode Signals Delay Register */
#define SARADC_8_ECIPR0      SARADC_8.ECIPR[0].R           /* External Channel Interrupt Pending Register */
#define SARADC_8_ECIPR1      SARADC_8.ECIPR[1].R           /* External Channel Interrupt Pending Register */
#define SARADC_8_ECIPR2      SARADC_8.ECIPR[2].R           /* External Channel Interrupt Pending Register */
#define SARADC_8_ECIPR3      SARADC_8.ECIPR[3].R           /* External Channel Interrupt Pending Register */
#define SARADC_8_ECIMR0      SARADC_8.ECIMR[0].R           /* External Channel Interrupt Mask Register */
#define SARADC_8_ECIMR1      SARADC_8.ECIMR[1].R           /* External Channel Interrupt Mask Register */
#define SARADC_8_ECIMR2      SARADC_8.ECIMR[2].R           /* External Channel Interrupt Mask Register */
#define SARADC_8_ECIMR3      SARADC_8.ECIMR[3].R           /* External Channel Interrupt Mask Register */
#define SARADC_8_ECDSR0      SARADC_8.ECDSR[0].R           /* External Channel DMA Select Register */
#define SARADC_8_ECDSR1      SARADC_8.ECDSR[1].R           /* External Channel DMA Select Register */
#define SARADC_8_ECDSR2      SARADC_8.ECDSR[2].R           /* External Channel DMA Select Register */
#define SARADC_8_ECDSR3      SARADC_8.ECDSR[3].R           /* External Channel DMA Select Register */
#define SARADC_8_ECNCMR0     SARADC_8.ECNCMR[0].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_8_ECNCMR1     SARADC_8.ECNCMR[1].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_8_ECNCMR2     SARADC_8.ECNCMR[2].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_8_ECNCMR3     SARADC_8.ECNCMR[3].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_8_ECJCMR0     SARADC_8.ECJCMR[0].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_8_ECJCMR1     SARADC_8.ECJCMR[1].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_8_ECJCMR2     SARADC_8.ECJCMR[2].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_8_ECJCMR3     SARADC_8.ECJCMR[3].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_8_ECWSELR0    SARADC_8.ECWSELR[0].R         /* External Channel Watchdog Selection Register */
#define SARADC_8_ECWSELR1    SARADC_8.ECWSELR[1].R         /* External Channel Watchdog Selection Register */
#define SARADC_8_ECWSELR2    SARADC_8.ECWSELR[2].R         /* External Channel Watchdog Selection Register */
#define SARADC_8_ECWSELR3    SARADC_8.ECWSELR[3].R         /* External Channel Watchdog Selection Register */
#define SARADC_8_ECWSELR4    SARADC_8.ECWSELR[4].R         /* External Channel Watchdog Selection Register */
#define SARADC_8_ECWSELR5    SARADC_8.ECWSELR[5].R         /* External Channel Watchdog Selection Register */
#define SARADC_8_ECWSELR6    SARADC_8.ECWSELR[6].R         /* External Channel Watchdog Selection Register */
#define SARADC_8_ECWSELR7    SARADC_8.ECWSELR[7].R         /* External Channel Watchdog Selection Register */
#define SARADC_8_ECWSELR8    SARADC_8.ECWSELR[8].R         /* External Channel Watchdog Selection Register */
#define SARADC_8_ECWSELR9    SARADC_8.ECWSELR[9].R         /* External Channel Watchdog Selection Register */
#define SARADC_8_ECWSELR10   SARADC_8.ECWSELR[10].R        /* External Channel Watchdog Selection Register */
#define SARADC_8_ECWSELR11   SARADC_8.ECWSELR[11].R        /* External Channel Watchdog Selection Register */
#define SARADC_8_ECWSELR12   SARADC_8.ECWSELR[12].R        /* External Channel Watchdog Selection Register */
#define SARADC_8_ECWSELR13   SARADC_8.ECWSELR[13].R        /* External Channel Watchdog Selection Register */
#define SARADC_8_ECWSELR14   SARADC_8.ECWSELR[14].R        /* External Channel Watchdog Selection Register */
#define SARADC_8_ECWSELR15   SARADC_8.ECWSELR[15].R        /* External Channel Watchdog Selection Register */
#define SARADC_8_ECWENR0     SARADC_8.ECWENR[0].R          /* External Channel Watchdog Enable Register */
#define SARADC_8_ECWENR1     SARADC_8.ECWENR[1].R          /* External Channel Watchdog Enable Register */
#define SARADC_8_ECWENR2     SARADC_8.ECWENR[2].R          /* External Channel Watchdog Enable Register */
#define SARADC_8_ECWENR3     SARADC_8.ECWENR[3].R          /* External Channel Watchdog Enable Register */
#define SARADC_8_ECAWORR0    SARADC_8.ECAWORR[0].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_8_ECAWORR1    SARADC_8.ECAWORR[1].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_8_ECAWORR2    SARADC_8.ECAWORR[2].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_8_ECAWORR3    SARADC_8.ECAWORR[3].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_8_ECMICR0     SARADC_8.ECMICR[0].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_8_ECMICR1     SARADC_8.ECMICR[1].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_8_ECMICR2     SARADC_8.ECMICR[2].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_8_ECMICR3     SARADC_8.ECMICR[3].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_8_ECDR128     SARADC_8.ECDR[0].R            /* External Channel Data Register */
#define SARADC_8_ECDR129     SARADC_8.ECDR[1].R            /* External Channel Data Register */
#define SARADC_8_ECDR130     SARADC_8.ECDR[2].R            /* External Channel Data Register */
#define SARADC_8_ECDR131     SARADC_8.ECDR[3].R            /* External Channel Data Register */
#define SARADC_8_ECDR132     SARADC_8.ECDR[4].R            /* External Channel Data Register */
#define SARADC_8_ECDR133     SARADC_8.ECDR[5].R            /* External Channel Data Register */
#define SARADC_8_ECDR134     SARADC_8.ECDR[6].R            /* External Channel Data Register */
#define SARADC_8_ECDR135     SARADC_8.ECDR[7].R            /* External Channel Data Register */
#define SARADC_8_ECDR136     SARADC_8.ECDR[8].R            /* External Channel Data Register */
#define SARADC_8_ECDR137     SARADC_8.ECDR[9].R            /* External Channel Data Register */
#define SARADC_8_ECDR138     SARADC_8.ECDR[10].R           /* External Channel Data Register */
#define SARADC_8_ECDR139     SARADC_8.ECDR[11].R           /* External Channel Data Register */
#define SARADC_8_ECDR140     SARADC_8.ECDR[12].R           /* External Channel Data Register */
#define SARADC_8_ECDR141     SARADC_8.ECDR[13].R           /* External Channel Data Register */
#define SARADC_8_ECDR142     SARADC_8.ECDR[14].R           /* External Channel Data Register */
#define SARADC_8_ECDR143     SARADC_8.ECDR[15].R           /* External Channel Data Register */
#define SARADC_8_ECDR144     SARADC_8.ECDR[16].R           /* External Channel Data Register */
#define SARADC_8_ECDR145     SARADC_8.ECDR[17].R           /* External Channel Data Register */
#define SARADC_8_ECDR146     SARADC_8.ECDR[18].R           /* External Channel Data Register */
#define SARADC_8_ECDR147     SARADC_8.ECDR[19].R           /* External Channel Data Register */
#define SARADC_8_ECDR148     SARADC_8.ECDR[20].R           /* External Channel Data Register */
#define SARADC_8_ECDR149     SARADC_8.ECDR[21].R           /* External Channel Data Register */
#define SARADC_8_ECDR150     SARADC_8.ECDR[22].R           /* External Channel Data Register */
#define SARADC_8_ECDR151     SARADC_8.ECDR[23].R           /* External Channel Data Register */
#define SARADC_8_ECDR152     SARADC_8.ECDR[24].R           /* External Channel Data Register */
#define SARADC_8_ECDR153     SARADC_8.ECDR[25].R           /* External Channel Data Register */
#define SARADC_8_ECDR154     SARADC_8.ECDR[26].R           /* External Channel Data Register */
#define SARADC_8_ECDR155     SARADC_8.ECDR[27].R           /* External Channel Data Register */
#define SARADC_8_ECDR156     SARADC_8.ECDR[28].R           /* External Channel Data Register */
#define SARADC_8_ECDR157     SARADC_8.ECDR[29].R           /* External Channel Data Register */
#define SARADC_8_ECDR158     SARADC_8.ECDR[30].R           /* External Channel Data Register */
#define SARADC_8_ECDR159     SARADC_8.ECDR[31].R           /* External Channel Data Register */
#define SARADC_8_ECDR160     SARADC_8.ECDR[32].R           /* External Channel Data Register */
#define SARADC_8_ECDR161     SARADC_8.ECDR[33].R           /* External Channel Data Register */
#define SARADC_8_ECDR162     SARADC_8.ECDR[34].R           /* External Channel Data Register */
#define SARADC_8_ECDR163     SARADC_8.ECDR[35].R           /* External Channel Data Register */
#define SARADC_8_ECDR164     SARADC_8.ECDR[36].R           /* External Channel Data Register */
#define SARADC_8_ECDR165     SARADC_8.ECDR[37].R           /* External Channel Data Register */
#define SARADC_8_ECDR166     SARADC_8.ECDR[38].R           /* External Channel Data Register */
#define SARADC_8_ECDR167     SARADC_8.ECDR[39].R           /* External Channel Data Register */
#define SARADC_8_ECDR168     SARADC_8.ECDR[40].R           /* External Channel Data Register */
#define SARADC_8_ECDR169     SARADC_8.ECDR[41].R           /* External Channel Data Register */
#define SARADC_8_ECDR170     SARADC_8.ECDR[42].R           /* External Channel Data Register */
#define SARADC_8_ECDR171     SARADC_8.ECDR[43].R           /* External Channel Data Register */
#define SARADC_8_ECDR172     SARADC_8.ECDR[44].R           /* External Channel Data Register */
#define SARADC_8_ECDR173     SARADC_8.ECDR[45].R           /* External Channel Data Register */
#define SARADC_8_ECDR174     SARADC_8.ECDR[46].R           /* External Channel Data Register */
#define SARADC_8_ECDR175     SARADC_8.ECDR[47].R           /* External Channel Data Register */
#define SARADC_8_ECDR176     SARADC_8.ECDR[48].R           /* External Channel Data Register */
#define SARADC_8_ECDR177     SARADC_8.ECDR[49].R           /* External Channel Data Register */
#define SARADC_8_ECDR178     SARADC_8.ECDR[50].R           /* External Channel Data Register */
#define SARADC_8_ECDR179     SARADC_8.ECDR[51].R           /* External Channel Data Register */
#define SARADC_8_ECDR180     SARADC_8.ECDR[52].R           /* External Channel Data Register */
#define SARADC_8_ECDR181     SARADC_8.ECDR[53].R           /* External Channel Data Register */
#define SARADC_8_ECDR182     SARADC_8.ECDR[54].R           /* External Channel Data Register */
#define SARADC_8_ECDR183     SARADC_8.ECDR[55].R           /* External Channel Data Register */
#define SARADC_8_ECDR184     SARADC_8.ECDR[56].R           /* External Channel Data Register */
#define SARADC_8_ECDR185     SARADC_8.ECDR[57].R           /* External Channel Data Register */
#define SARADC_8_ECDR186     SARADC_8.ECDR[58].R           /* External Channel Data Register */
#define SARADC_8_ECDR187     SARADC_8.ECDR[59].R           /* External Channel Data Register */
#define SARADC_8_ECDR188     SARADC_8.ECDR[60].R           /* External Channel Data Register */
#define SARADC_8_ECDR189     SARADC_8.ECDR[61].R           /* External Channel Data Register */
#define SARADC_8_ECDR190     SARADC_8.ECDR[62].R           /* External Channel Data Register */
#define SARADC_8_ECDR191     SARADC_8.ECDR[63].R           /* External Channel Data Register */
#define SARADC_8_ECDR192     SARADC_8.ECDR[64].R           /* External Channel Data Register */
#define SARADC_8_ECDR193     SARADC_8.ECDR[65].R           /* External Channel Data Register */
#define SARADC_8_ECDR194     SARADC_8.ECDR[66].R           /* External Channel Data Register */
#define SARADC_8_ECDR195     SARADC_8.ECDR[67].R           /* External Channel Data Register */
#define SARADC_8_ECDR196     SARADC_8.ECDR[68].R           /* External Channel Data Register */
#define SARADC_8_ECDR197     SARADC_8.ECDR[69].R           /* External Channel Data Register */
#define SARADC_8_ECDR198     SARADC_8.ECDR[70].R           /* External Channel Data Register */
#define SARADC_8_ECDR199     SARADC_8.ECDR[71].R           /* External Channel Data Register */
#define SARADC_8_ECDR200     SARADC_8.ECDR[72].R           /* External Channel Data Register */
#define SARADC_8_ECDR201     SARADC_8.ECDR[73].R           /* External Channel Data Register */
#define SARADC_8_ECDR202     SARADC_8.ECDR[74].R           /* External Channel Data Register */
#define SARADC_8_ECDR203     SARADC_8.ECDR[75].R           /* External Channel Data Register */
#define SARADC_8_ECDR204     SARADC_8.ECDR[76].R           /* External Channel Data Register */
#define SARADC_8_ECDR205     SARADC_8.ECDR[77].R           /* External Channel Data Register */
#define SARADC_8_ECDR206     SARADC_8.ECDR[78].R           /* External Channel Data Register */
#define SARADC_8_ECDR207     SARADC_8.ECDR[79].R           /* External Channel Data Register */
#define SARADC_8_ECDR208     SARADC_8.ECDR[80].R           /* External Channel Data Register */
#define SARADC_8_ECDR209     SARADC_8.ECDR[81].R           /* External Channel Data Register */
#define SARADC_8_ECDR210     SARADC_8.ECDR[82].R           /* External Channel Data Register */
#define SARADC_8_ECDR211     SARADC_8.ECDR[83].R           /* External Channel Data Register */
#define SARADC_8_ECDR212     SARADC_8.ECDR[84].R           /* External Channel Data Register */
#define SARADC_8_ECDR213     SARADC_8.ECDR[85].R           /* External Channel Data Register */
#define SARADC_8_ECDR214     SARADC_8.ECDR[86].R           /* External Channel Data Register */
#define SARADC_8_ECDR215     SARADC_8.ECDR[87].R           /* External Channel Data Register */
#define SARADC_8_ECDR216     SARADC_8.ECDR[88].R           /* External Channel Data Register */
#define SARADC_8_ECDR217     SARADC_8.ECDR[89].R           /* External Channel Data Register */
#define SARADC_8_ECDR218     SARADC_8.ECDR[90].R           /* External Channel Data Register */
#define SARADC_8_ECDR219     SARADC_8.ECDR[91].R           /* External Channel Data Register */
#define SARADC_8_ECDR220     SARADC_8.ECDR[92].R           /* External Channel Data Register */
#define SARADC_8_ECDR221     SARADC_8.ECDR[93].R           /* External Channel Data Register */
#define SARADC_8_ECDR222     SARADC_8.ECDR[94].R           /* External Channel Data Register */
#define SARADC_8_ECDR223     SARADC_8.ECDR[95].R           /* External Channel Data Register */
#define SARADC_8_ECDR224     SARADC_8.ECDR[96].R           /* External Channel Data Register */
#define SARADC_8_ECDR225     SARADC_8.ECDR[97].R           /* External Channel Data Register */
#define SARADC_8_ECDR226     SARADC_8.ECDR[98].R           /* External Channel Data Register */
#define SARADC_8_ECDR227     SARADC_8.ECDR[99].R           /* External Channel Data Register */
#define SARADC_8_ECDR228     SARADC_8.ECDR[100].R          /* External Channel Data Register */
#define SARADC_8_ECDR229     SARADC_8.ECDR[101].R          /* External Channel Data Register */
#define SARADC_8_ECDR230     SARADC_8.ECDR[102].R          /* External Channel Data Register */
#define SARADC_8_ECDR231     SARADC_8.ECDR[103].R          /* External Channel Data Register */
#define SARADC_8_ECDR232     SARADC_8.ECDR[104].R          /* External Channel Data Register */
#define SARADC_8_ECDR233     SARADC_8.ECDR[105].R          /* External Channel Data Register */
#define SARADC_8_ECDR234     SARADC_8.ECDR[106].R          /* External Channel Data Register */
#define SARADC_8_ECDR235     SARADC_8.ECDR[107].R          /* External Channel Data Register */
#define SARADC_8_ECDR236     SARADC_8.ECDR[108].R          /* External Channel Data Register */
#define SARADC_8_ECDR237     SARADC_8.ECDR[109].R          /* External Channel Data Register */
#define SARADC_8_ECDR238     SARADC_8.ECDR[110].R          /* External Channel Data Register */
#define SARADC_8_ECDR239     SARADC_8.ECDR[111].R          /* External Channel Data Register */
#define SARADC_8_ECDR240     SARADC_8.ECDR[112].R          /* External Channel Data Register */
#define SARADC_8_ECDR241     SARADC_8.ECDR[113].R          /* External Channel Data Register */
#define SARADC_8_ECDR242     SARADC_8.ECDR[114].R          /* External Channel Data Register */
#define SARADC_8_ECDR243     SARADC_8.ECDR[115].R          /* External Channel Data Register */
#define SARADC_8_ECDR244     SARADC_8.ECDR[116].R          /* External Channel Data Register */
#define SARADC_8_ECDR245     SARADC_8.ECDR[117].R          /* External Channel Data Register */
#define SARADC_8_ECDR246     SARADC_8.ECDR[118].R          /* External Channel Data Register */
#define SARADC_8_ECDR247     SARADC_8.ECDR[119].R          /* External Channel Data Register */
#define SARADC_8_ECDR248     SARADC_8.ECDR[120].R          /* External Channel Data Register */
#define SARADC_8_ECDR249     SARADC_8.ECDR[121].R          /* External Channel Data Register */
#define SARADC_8_ECDR250     SARADC_8.ECDR[122].R          /* External Channel Data Register */
#define SARADC_8_ECDR251     SARADC_8.ECDR[123].R          /* External Channel Data Register */
#define SARADC_8_ECDR252     SARADC_8.ECDR[124].R          /* External Channel Data Register */
#define SARADC_8_ECDR253     SARADC_8.ECDR[125].R          /* External Channel Data Register */
#define SARADC_8_ECDR254     SARADC_8.ECDR[126].R          /* External Channel Data Register */
#define SARADC_8_ECDR255     SARADC_8.ECDR[127].R          /* External Channel Data Register */

/* SARADC */
#define SARADC_9_MCR         SARADC_9.MCR.R                /* Main Configuration Register */
#define SARADC_9_MSR         SARADC_9.MSR.R                /* Main Status Register */
#define SARADC_9_ISR         SARADC_9.ISR.R                /* Interrupt Status Register */
#define SARADC_9_ICIPR0      SARADC_9.ICIPR[0].R           /* Internal channel Interrupt Pending Register */
#define SARADC_9_ICIPR1      SARADC_9.ICIPR[1].R           /* Internal channel Interrupt Pending Register */
#define SARADC_9_ICIPR2      SARADC_9.ICIPR[2].R           /* Internal channel Interrupt Pending Register */
#define SARADC_9_IMR         SARADC_9.IMR.R                /* Interrupt Mask Register */
#define SARADC_9_ICIMR0      SARADC_9.ICIMR[0].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_9_ICIMR1      SARADC_9.ICIMR[1].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_9_ICIMR2      SARADC_9.ICIMR[2].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_9_WTISR       SARADC_9.WTISR.R              /* Watchdog Threshold Interrupt Status Register */
#define SARADC_9_WTIMR       SARADC_9.WTIMR.R              /* Watchdog Threshold Interrupt Mask Register */
#define SARADC_9_DMAE        SARADC_9.DMAE.R               /* DMA Enable Register */
#define SARADC_9_ICDSR0      SARADC_9.ICDSR[0].R           /* Internal Channel DMA Select Register */
#define SARADC_9_ICDSR1      SARADC_9.ICDSR[1].R           /* Internal Channel DMA Select Register */
#define SARADC_9_ICDSR2      SARADC_9.ICDSR[2].R           /* Internal Channel DMA Select Register */
#define SARADC_9_WTHRHLR0    SARADC_9.WTHRHLR[0].R         /* Watchdog Threshold Register */
#define SARADC_9_WTHRHLR1    SARADC_9.WTHRHLR[1].R         /* Watchdog Threshold Register */
#define SARADC_9_WTHRHLR2    SARADC_9.WTHRHLR[2].R         /* Watchdog Threshold Register */
#define SARADC_9_WTHRHLR3    SARADC_9.WTHRHLR[3].R         /* Watchdog Threshold Register */
#define SARADC_9_CTR0        SARADC_9.CTR[0].R             /* Conversion Timing Register */
#define SARADC_9_CTR1        SARADC_9.CTR[1].R             /* Conversion Timing Register */
#define SARADC_9_CTR2        SARADC_9.CTR[2].R             /* Conversion Timing Register */
#define SARADC_9_CTR3        SARADC_9.CTR[3].R             /* Conversion Timing Register */
#define SARADC_9_ICNCMR0     SARADC_9.ICNCMR[0].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_9_ICNCMR1     SARADC_9.ICNCMR[1].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_9_ICNCMR2     SARADC_9.ICNCMR[2].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_9_ICJCMR0     SARADC_9.ICJCMR[0].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_9_ICJCMR1     SARADC_9.ICJCMR[1].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_9_ICJCMR2     SARADC_9.ICJCMR[2].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_9_PDEDR       SARADC_9.PDEDR.R              /* Power Down Exit Delay Register */
#define SARADC_9_ICDR0       SARADC_9.ICDR[0].R            /* Internal Channel Data Register */
#define SARADC_9_ICDR1       SARADC_9.ICDR[1].R            /* Internal Channel Data Register */
#define SARADC_9_ICDR2       SARADC_9.ICDR[2].R            /* Internal Channel Data Register */
#define SARADC_9_ICDR3       SARADC_9.ICDR[3].R            /* Internal Channel Data Register */
#define SARADC_9_ICDR4       SARADC_9.ICDR[4].R            /* Internal Channel Data Register */
#define SARADC_9_ICDR5       SARADC_9.ICDR[5].R            /* Internal Channel Data Register */
#define SARADC_9_ICDR6       SARADC_9.ICDR[6].R            /* Internal Channel Data Register */
#define SARADC_9_ICDR7       SARADC_9.ICDR[7].R            /* Internal Channel Data Register */
#define SARADC_9_ICDR8       SARADC_9.ICDR[8].R            /* Internal Channel Data Register */
#define SARADC_9_ICDR9       SARADC_9.ICDR[9].R            /* Internal Channel Data Register */
#define SARADC_9_ICDR10      SARADC_9.ICDR[10].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR11      SARADC_9.ICDR[11].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR12      SARADC_9.ICDR[12].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR13      SARADC_9.ICDR[13].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR14      SARADC_9.ICDR[14].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR15      SARADC_9.ICDR[15].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR16      SARADC_9.ICDR[16].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR17      SARADC_9.ICDR[17].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR18      SARADC_9.ICDR[18].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR19      SARADC_9.ICDR[19].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR20      SARADC_9.ICDR[20].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR21      SARADC_9.ICDR[21].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR22      SARADC_9.ICDR[22].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR23      SARADC_9.ICDR[23].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR24      SARADC_9.ICDR[24].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR25      SARADC_9.ICDR[25].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR26      SARADC_9.ICDR[26].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR27      SARADC_9.ICDR[27].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR28      SARADC_9.ICDR[28].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR29      SARADC_9.ICDR[29].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR30      SARADC_9.ICDR[30].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR31      SARADC_9.ICDR[31].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR32      SARADC_9.ICDR[32].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR33      SARADC_9.ICDR[33].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR34      SARADC_9.ICDR[34].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR35      SARADC_9.ICDR[35].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR36      SARADC_9.ICDR[36].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR37      SARADC_9.ICDR[37].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR38      SARADC_9.ICDR[38].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR39      SARADC_9.ICDR[39].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR40      SARADC_9.ICDR[40].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR41      SARADC_9.ICDR[41].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR42      SARADC_9.ICDR[42].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR43      SARADC_9.ICDR[43].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR44      SARADC_9.ICDR[44].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR45      SARADC_9.ICDR[45].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR46      SARADC_9.ICDR[46].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR47      SARADC_9.ICDR[47].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR48      SARADC_9.ICDR[48].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR49      SARADC_9.ICDR[49].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR50      SARADC_9.ICDR[50].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR51      SARADC_9.ICDR[51].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR52      SARADC_9.ICDR[52].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR53      SARADC_9.ICDR[53].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR54      SARADC_9.ICDR[54].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR55      SARADC_9.ICDR[55].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR56      SARADC_9.ICDR[56].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR57      SARADC_9.ICDR[57].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR58      SARADC_9.ICDR[58].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR59      SARADC_9.ICDR[59].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR60      SARADC_9.ICDR[60].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR61      SARADC_9.ICDR[61].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR62      SARADC_9.ICDR[62].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR63      SARADC_9.ICDR[63].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR64      SARADC_9.ICDR[64].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR65      SARADC_9.ICDR[65].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR66      SARADC_9.ICDR[66].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR67      SARADC_9.ICDR[67].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR68      SARADC_9.ICDR[68].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR69      SARADC_9.ICDR[69].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR70      SARADC_9.ICDR[70].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR71      SARADC_9.ICDR[71].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR72      SARADC_9.ICDR[72].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR73      SARADC_9.ICDR[73].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR74      SARADC_9.ICDR[74].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR75      SARADC_9.ICDR[75].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR76      SARADC_9.ICDR[76].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR77      SARADC_9.ICDR[77].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR78      SARADC_9.ICDR[78].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR79      SARADC_9.ICDR[79].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR80      SARADC_9.ICDR[80].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR81      SARADC_9.ICDR[81].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR82      SARADC_9.ICDR[82].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR83      SARADC_9.ICDR[83].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR84      SARADC_9.ICDR[84].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR85      SARADC_9.ICDR[85].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR86      SARADC_9.ICDR[86].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR87      SARADC_9.ICDR[87].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR88      SARADC_9.ICDR[88].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR89      SARADC_9.ICDR[89].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR90      SARADC_9.ICDR[90].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR91      SARADC_9.ICDR[91].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR92      SARADC_9.ICDR[92].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR93      SARADC_9.ICDR[93].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR94      SARADC_9.ICDR[94].R           /* Internal Channel Data Register */
#define SARADC_9_ICDR95      SARADC_9.ICDR[95].R           /* Internal Channel Data Register */
#define SARADC_9_ICWSELR0    SARADC_9.ICWSELR[0].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_9_ICWSELR1    SARADC_9.ICWSELR[1].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_9_ICWSELR2    SARADC_9.ICWSELR[2].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_9_ICWSELR3    SARADC_9.ICWSELR[3].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_9_ICWSELR4    SARADC_9.ICWSELR[4].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_9_ICWSELR5    SARADC_9.ICWSELR[5].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_9_ICWSELR6    SARADC_9.ICWSELR[6].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_9_ICWSELR7    SARADC_9.ICWSELR[7].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_9_ICWSELR8    SARADC_9.ICWSELR[8].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_9_ICWSELR9    SARADC_9.ICWSELR[9].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_9_ICWSELR10   SARADC_9.ICWSELR[10].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_9_ICWSELR11   SARADC_9.ICWSELR[11].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_9_ICWENR0     SARADC_9.ICWENR[0].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_9_ICWENR1     SARADC_9.ICWENR[1].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_9_ICWENR2     SARADC_9.ICWENR[2].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_9_ICAWORR0    SARADC_9.ICAWORR[0].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_9_ICAWORR1    SARADC_9.ICAWORR[1].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_9_ICAWORR2    SARADC_9.ICAWORR[2].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_9_TCIPR       SARADC_9.TCIPR.R              /* Test Channel Interrupt Pending Register */
#define SARADC_9_TCIMR       SARADC_9.TCIMR.R              /* Test Channel Interrupt Mask Register */
#define SARADC_9_TCDSR       SARADC_9.TCDSR.R              /* Test Channel DMA Select Register */
#define SARADC_9_TCNCMR      SARADC_9.TCNCMR.R             /* Test Channel Normal Conversion Mask Register */
#define SARADC_9_TCJCMR      SARADC_9.TCJCMR.R             /* Test Channel Injected Conversion Mask Register */
#define SARADC_9_TCWSELR0    SARADC_9.TCWSELR[0].R         /* Test Channel Watchdog Selection Register */
#define SARADC_9_TCWSELR1    SARADC_9.TCWSELR[1].R         /* Test Channel Watchdog Selection Register */
#define SARADC_9_TCWSELR2    SARADC_9.TCWSELR[2].R         /* Test Channel Watchdog Selection Register */
#define SARADC_9_TCWSELR3    SARADC_9.TCWSELR[3].R         /* Test Channel Watchdog Selection Register */
#define SARADC_9_TCWENR      SARADC_9.TCWENR.R             /* Test Channel Watchdog Enable Register */
#define SARADC_9_TCAWORR     SARADC_9.TCAWORR.R            /* Test Channel Analog Watchdog Out of Range Register */
#define SARADC_9_TCCAPR0     SARADC_9.TCCAPR[0].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_9_TCCAPR1     SARADC_9.TCCAPR[1].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_9_TCCAPR2     SARADC_9.TCCAPR[2].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_9_TCCAPR3     SARADC_9.TCCAPR[3].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_9_TCCAPR4     SARADC_9.TCCAPR[4].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_9_TCCAPR5     SARADC_9.TCCAPR[5].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_9_TCCAPR6     SARADC_9.TCCAPR[6].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_9_TCCAPR7     SARADC_9.TCCAPR[7].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_9_TCDR96      SARADC_9.TCDR[0].R            /* Test Channel Data Register */
#define SARADC_9_TCDR97      SARADC_9.TCDR[1].R            /* Test Channel Data Register */
#define SARADC_9_TCDR98      SARADC_9.TCDR[2].R            /* Test Channel Data Register */
#define SARADC_9_TCDR99      SARADC_9.TCDR[3].R            /* Test Channel Data Register */
#define SARADC_9_TCDR100     SARADC_9.TCDR[4].R            /* Test Channel Data Register */
#define SARADC_9_TCDR101     SARADC_9.TCDR[5].R            /* Test Channel Data Register */
#define SARADC_9_TCDR102     SARADC_9.TCDR[6].R            /* Test Channel Data Register */
#define SARADC_9_TCDR103     SARADC_9.TCDR[7].R            /* Test Channel Data Register */
#define SARADC_9_TCDR104     SARADC_9.TCDR[8].R            /* Test Channel Data Register */
#define SARADC_9_TCDR105     SARADC_9.TCDR[9].R            /* Test Channel Data Register */
#define SARADC_9_TCDR106     SARADC_9.TCDR[10].R           /* Test Channel Data Register */
#define SARADC_9_TCDR107     SARADC_9.TCDR[11].R           /* Test Channel Data Register */
#define SARADC_9_TCDR108     SARADC_9.TCDR[12].R           /* Test Channel Data Register */
#define SARADC_9_TCDR109     SARADC_9.TCDR[13].R           /* Test Channel Data Register */
#define SARADC_9_TCDR110     SARADC_9.TCDR[14].R           /* Test Channel Data Register */
#define SARADC_9_TCDR111     SARADC_9.TCDR[15].R           /* Test Channel Data Register */
#define SARADC_9_TCDR112     SARADC_9.TCDR[16].R           /* Test Channel Data Register */
#define SARADC_9_TCDR113     SARADC_9.TCDR[17].R           /* Test Channel Data Register */
#define SARADC_9_TCDR114     SARADC_9.TCDR[18].R           /* Test Channel Data Register */
#define SARADC_9_TCDR115     SARADC_9.TCDR[19].R           /* Test Channel Data Register */
#define SARADC_9_TCDR116     SARADC_9.TCDR[20].R           /* Test Channel Data Register */
#define SARADC_9_TCDR117     SARADC_9.TCDR[21].R           /* Test Channel Data Register */
#define SARADC_9_TCDR118     SARADC_9.TCDR[22].R           /* Test Channel Data Register */
#define SARADC_9_TCDR119     SARADC_9.TCDR[23].R           /* Test Channel Data Register */
#define SARADC_9_TCDR120     SARADC_9.TCDR[24].R           /* Test Channel Data Register */
#define SARADC_9_TCDR121     SARADC_9.TCDR[25].R           /* Test Channel Data Register */
#define SARADC_9_TCDR122     SARADC_9.TCDR[26].R           /* Test Channel Data Register */
#define SARADC_9_TCDR123     SARADC_9.TCDR[27].R           /* Test Channel Data Register */
#define SARADC_9_TCDR124     SARADC_9.TCDR[28].R           /* Test Channel Data Register */
#define SARADC_9_TCDR125     SARADC_9.TCDR[29].R           /* Test Channel Data Register */
#define SARADC_9_TCDR126     SARADC_9.TCDR[30].R           /* Test Channel Data Register */
#define SARADC_9_TCDR127     SARADC_9.TCDR[31].R           /* Test Channel Data Register */
#define SARADC_9_ECDSDR      SARADC_9.ECDSDR.R             /* External Channel Decode Signals Delay Register */
#define SARADC_9_ECIPR0      SARADC_9.ECIPR[0].R           /* External Channel Interrupt Pending Register */
#define SARADC_9_ECIPR1      SARADC_9.ECIPR[1].R           /* External Channel Interrupt Pending Register */
#define SARADC_9_ECIPR2      SARADC_9.ECIPR[2].R           /* External Channel Interrupt Pending Register */
#define SARADC_9_ECIPR3      SARADC_9.ECIPR[3].R           /* External Channel Interrupt Pending Register */
#define SARADC_9_ECIMR0      SARADC_9.ECIMR[0].R           /* External Channel Interrupt Mask Register */
#define SARADC_9_ECIMR1      SARADC_9.ECIMR[1].R           /* External Channel Interrupt Mask Register */
#define SARADC_9_ECIMR2      SARADC_9.ECIMR[2].R           /* External Channel Interrupt Mask Register */
#define SARADC_9_ECIMR3      SARADC_9.ECIMR[3].R           /* External Channel Interrupt Mask Register */
#define SARADC_9_ECDSR0      SARADC_9.ECDSR[0].R           /* External Channel DMA Select Register */
#define SARADC_9_ECDSR1      SARADC_9.ECDSR[1].R           /* External Channel DMA Select Register */
#define SARADC_9_ECDSR2      SARADC_9.ECDSR[2].R           /* External Channel DMA Select Register */
#define SARADC_9_ECDSR3      SARADC_9.ECDSR[3].R           /* External Channel DMA Select Register */
#define SARADC_9_ECNCMR0     SARADC_9.ECNCMR[0].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_9_ECNCMR1     SARADC_9.ECNCMR[1].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_9_ECNCMR2     SARADC_9.ECNCMR[2].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_9_ECNCMR3     SARADC_9.ECNCMR[3].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_9_ECJCMR0     SARADC_9.ECJCMR[0].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_9_ECJCMR1     SARADC_9.ECJCMR[1].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_9_ECJCMR2     SARADC_9.ECJCMR[2].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_9_ECJCMR3     SARADC_9.ECJCMR[3].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_9_ECWSELR0    SARADC_9.ECWSELR[0].R         /* External Channel Watchdog Selection Register */
#define SARADC_9_ECWSELR1    SARADC_9.ECWSELR[1].R         /* External Channel Watchdog Selection Register */
#define SARADC_9_ECWSELR2    SARADC_9.ECWSELR[2].R         /* External Channel Watchdog Selection Register */
#define SARADC_9_ECWSELR3    SARADC_9.ECWSELR[3].R         /* External Channel Watchdog Selection Register */
#define SARADC_9_ECWSELR4    SARADC_9.ECWSELR[4].R         /* External Channel Watchdog Selection Register */
#define SARADC_9_ECWSELR5    SARADC_9.ECWSELR[5].R         /* External Channel Watchdog Selection Register */
#define SARADC_9_ECWSELR6    SARADC_9.ECWSELR[6].R         /* External Channel Watchdog Selection Register */
#define SARADC_9_ECWSELR7    SARADC_9.ECWSELR[7].R         /* External Channel Watchdog Selection Register */
#define SARADC_9_ECWSELR8    SARADC_9.ECWSELR[8].R         /* External Channel Watchdog Selection Register */
#define SARADC_9_ECWSELR9    SARADC_9.ECWSELR[9].R         /* External Channel Watchdog Selection Register */
#define SARADC_9_ECWSELR10   SARADC_9.ECWSELR[10].R        /* External Channel Watchdog Selection Register */
#define SARADC_9_ECWSELR11   SARADC_9.ECWSELR[11].R        /* External Channel Watchdog Selection Register */
#define SARADC_9_ECWSELR12   SARADC_9.ECWSELR[12].R        /* External Channel Watchdog Selection Register */
#define SARADC_9_ECWSELR13   SARADC_9.ECWSELR[13].R        /* External Channel Watchdog Selection Register */
#define SARADC_9_ECWSELR14   SARADC_9.ECWSELR[14].R        /* External Channel Watchdog Selection Register */
#define SARADC_9_ECWSELR15   SARADC_9.ECWSELR[15].R        /* External Channel Watchdog Selection Register */
#define SARADC_9_ECWENR0     SARADC_9.ECWENR[0].R          /* External Channel Watchdog Enable Register */
#define SARADC_9_ECWENR1     SARADC_9.ECWENR[1].R          /* External Channel Watchdog Enable Register */
#define SARADC_9_ECWENR2     SARADC_9.ECWENR[2].R          /* External Channel Watchdog Enable Register */
#define SARADC_9_ECWENR3     SARADC_9.ECWENR[3].R          /* External Channel Watchdog Enable Register */
#define SARADC_9_ECAWORR0    SARADC_9.ECAWORR[0].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_9_ECAWORR1    SARADC_9.ECAWORR[1].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_9_ECAWORR2    SARADC_9.ECAWORR[2].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_9_ECAWORR3    SARADC_9.ECAWORR[3].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_9_ECMICR0     SARADC_9.ECMICR[0].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_9_ECMICR1     SARADC_9.ECMICR[1].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_9_ECMICR2     SARADC_9.ECMICR[2].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_9_ECMICR3     SARADC_9.ECMICR[3].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_9_ECDR128     SARADC_9.ECDR[0].R            /* External Channel Data Register */
#define SARADC_9_ECDR129     SARADC_9.ECDR[1].R            /* External Channel Data Register */
#define SARADC_9_ECDR130     SARADC_9.ECDR[2].R            /* External Channel Data Register */
#define SARADC_9_ECDR131     SARADC_9.ECDR[3].R            /* External Channel Data Register */
#define SARADC_9_ECDR132     SARADC_9.ECDR[4].R            /* External Channel Data Register */
#define SARADC_9_ECDR133     SARADC_9.ECDR[5].R            /* External Channel Data Register */
#define SARADC_9_ECDR134     SARADC_9.ECDR[6].R            /* External Channel Data Register */
#define SARADC_9_ECDR135     SARADC_9.ECDR[7].R            /* External Channel Data Register */
#define SARADC_9_ECDR136     SARADC_9.ECDR[8].R            /* External Channel Data Register */
#define SARADC_9_ECDR137     SARADC_9.ECDR[9].R            /* External Channel Data Register */
#define SARADC_9_ECDR138     SARADC_9.ECDR[10].R           /* External Channel Data Register */
#define SARADC_9_ECDR139     SARADC_9.ECDR[11].R           /* External Channel Data Register */
#define SARADC_9_ECDR140     SARADC_9.ECDR[12].R           /* External Channel Data Register */
#define SARADC_9_ECDR141     SARADC_9.ECDR[13].R           /* External Channel Data Register */
#define SARADC_9_ECDR142     SARADC_9.ECDR[14].R           /* External Channel Data Register */
#define SARADC_9_ECDR143     SARADC_9.ECDR[15].R           /* External Channel Data Register */
#define SARADC_9_ECDR144     SARADC_9.ECDR[16].R           /* External Channel Data Register */
#define SARADC_9_ECDR145     SARADC_9.ECDR[17].R           /* External Channel Data Register */
#define SARADC_9_ECDR146     SARADC_9.ECDR[18].R           /* External Channel Data Register */
#define SARADC_9_ECDR147     SARADC_9.ECDR[19].R           /* External Channel Data Register */
#define SARADC_9_ECDR148     SARADC_9.ECDR[20].R           /* External Channel Data Register */
#define SARADC_9_ECDR149     SARADC_9.ECDR[21].R           /* External Channel Data Register */
#define SARADC_9_ECDR150     SARADC_9.ECDR[22].R           /* External Channel Data Register */
#define SARADC_9_ECDR151     SARADC_9.ECDR[23].R           /* External Channel Data Register */
#define SARADC_9_ECDR152     SARADC_9.ECDR[24].R           /* External Channel Data Register */
#define SARADC_9_ECDR153     SARADC_9.ECDR[25].R           /* External Channel Data Register */
#define SARADC_9_ECDR154     SARADC_9.ECDR[26].R           /* External Channel Data Register */
#define SARADC_9_ECDR155     SARADC_9.ECDR[27].R           /* External Channel Data Register */
#define SARADC_9_ECDR156     SARADC_9.ECDR[28].R           /* External Channel Data Register */
#define SARADC_9_ECDR157     SARADC_9.ECDR[29].R           /* External Channel Data Register */
#define SARADC_9_ECDR158     SARADC_9.ECDR[30].R           /* External Channel Data Register */
#define SARADC_9_ECDR159     SARADC_9.ECDR[31].R           /* External Channel Data Register */
#define SARADC_9_ECDR160     SARADC_9.ECDR[32].R           /* External Channel Data Register */
#define SARADC_9_ECDR161     SARADC_9.ECDR[33].R           /* External Channel Data Register */
#define SARADC_9_ECDR162     SARADC_9.ECDR[34].R           /* External Channel Data Register */
#define SARADC_9_ECDR163     SARADC_9.ECDR[35].R           /* External Channel Data Register */
#define SARADC_9_ECDR164     SARADC_9.ECDR[36].R           /* External Channel Data Register */
#define SARADC_9_ECDR165     SARADC_9.ECDR[37].R           /* External Channel Data Register */
#define SARADC_9_ECDR166     SARADC_9.ECDR[38].R           /* External Channel Data Register */
#define SARADC_9_ECDR167     SARADC_9.ECDR[39].R           /* External Channel Data Register */
#define SARADC_9_ECDR168     SARADC_9.ECDR[40].R           /* External Channel Data Register */
#define SARADC_9_ECDR169     SARADC_9.ECDR[41].R           /* External Channel Data Register */
#define SARADC_9_ECDR170     SARADC_9.ECDR[42].R           /* External Channel Data Register */
#define SARADC_9_ECDR171     SARADC_9.ECDR[43].R           /* External Channel Data Register */
#define SARADC_9_ECDR172     SARADC_9.ECDR[44].R           /* External Channel Data Register */
#define SARADC_9_ECDR173     SARADC_9.ECDR[45].R           /* External Channel Data Register */
#define SARADC_9_ECDR174     SARADC_9.ECDR[46].R           /* External Channel Data Register */
#define SARADC_9_ECDR175     SARADC_9.ECDR[47].R           /* External Channel Data Register */
#define SARADC_9_ECDR176     SARADC_9.ECDR[48].R           /* External Channel Data Register */
#define SARADC_9_ECDR177     SARADC_9.ECDR[49].R           /* External Channel Data Register */
#define SARADC_9_ECDR178     SARADC_9.ECDR[50].R           /* External Channel Data Register */
#define SARADC_9_ECDR179     SARADC_9.ECDR[51].R           /* External Channel Data Register */
#define SARADC_9_ECDR180     SARADC_9.ECDR[52].R           /* External Channel Data Register */
#define SARADC_9_ECDR181     SARADC_9.ECDR[53].R           /* External Channel Data Register */
#define SARADC_9_ECDR182     SARADC_9.ECDR[54].R           /* External Channel Data Register */
#define SARADC_9_ECDR183     SARADC_9.ECDR[55].R           /* External Channel Data Register */
#define SARADC_9_ECDR184     SARADC_9.ECDR[56].R           /* External Channel Data Register */
#define SARADC_9_ECDR185     SARADC_9.ECDR[57].R           /* External Channel Data Register */
#define SARADC_9_ECDR186     SARADC_9.ECDR[58].R           /* External Channel Data Register */
#define SARADC_9_ECDR187     SARADC_9.ECDR[59].R           /* External Channel Data Register */
#define SARADC_9_ECDR188     SARADC_9.ECDR[60].R           /* External Channel Data Register */
#define SARADC_9_ECDR189     SARADC_9.ECDR[61].R           /* External Channel Data Register */
#define SARADC_9_ECDR190     SARADC_9.ECDR[62].R           /* External Channel Data Register */
#define SARADC_9_ECDR191     SARADC_9.ECDR[63].R           /* External Channel Data Register */
#define SARADC_9_ECDR192     SARADC_9.ECDR[64].R           /* External Channel Data Register */
#define SARADC_9_ECDR193     SARADC_9.ECDR[65].R           /* External Channel Data Register */
#define SARADC_9_ECDR194     SARADC_9.ECDR[66].R           /* External Channel Data Register */
#define SARADC_9_ECDR195     SARADC_9.ECDR[67].R           /* External Channel Data Register */
#define SARADC_9_ECDR196     SARADC_9.ECDR[68].R           /* External Channel Data Register */
#define SARADC_9_ECDR197     SARADC_9.ECDR[69].R           /* External Channel Data Register */
#define SARADC_9_ECDR198     SARADC_9.ECDR[70].R           /* External Channel Data Register */
#define SARADC_9_ECDR199     SARADC_9.ECDR[71].R           /* External Channel Data Register */
#define SARADC_9_ECDR200     SARADC_9.ECDR[72].R           /* External Channel Data Register */
#define SARADC_9_ECDR201     SARADC_9.ECDR[73].R           /* External Channel Data Register */
#define SARADC_9_ECDR202     SARADC_9.ECDR[74].R           /* External Channel Data Register */
#define SARADC_9_ECDR203     SARADC_9.ECDR[75].R           /* External Channel Data Register */
#define SARADC_9_ECDR204     SARADC_9.ECDR[76].R           /* External Channel Data Register */
#define SARADC_9_ECDR205     SARADC_9.ECDR[77].R           /* External Channel Data Register */
#define SARADC_9_ECDR206     SARADC_9.ECDR[78].R           /* External Channel Data Register */
#define SARADC_9_ECDR207     SARADC_9.ECDR[79].R           /* External Channel Data Register */
#define SARADC_9_ECDR208     SARADC_9.ECDR[80].R           /* External Channel Data Register */
#define SARADC_9_ECDR209     SARADC_9.ECDR[81].R           /* External Channel Data Register */
#define SARADC_9_ECDR210     SARADC_9.ECDR[82].R           /* External Channel Data Register */
#define SARADC_9_ECDR211     SARADC_9.ECDR[83].R           /* External Channel Data Register */
#define SARADC_9_ECDR212     SARADC_9.ECDR[84].R           /* External Channel Data Register */
#define SARADC_9_ECDR213     SARADC_9.ECDR[85].R           /* External Channel Data Register */
#define SARADC_9_ECDR214     SARADC_9.ECDR[86].R           /* External Channel Data Register */
#define SARADC_9_ECDR215     SARADC_9.ECDR[87].R           /* External Channel Data Register */
#define SARADC_9_ECDR216     SARADC_9.ECDR[88].R           /* External Channel Data Register */
#define SARADC_9_ECDR217     SARADC_9.ECDR[89].R           /* External Channel Data Register */
#define SARADC_9_ECDR218     SARADC_9.ECDR[90].R           /* External Channel Data Register */
#define SARADC_9_ECDR219     SARADC_9.ECDR[91].R           /* External Channel Data Register */
#define SARADC_9_ECDR220     SARADC_9.ECDR[92].R           /* External Channel Data Register */
#define SARADC_9_ECDR221     SARADC_9.ECDR[93].R           /* External Channel Data Register */
#define SARADC_9_ECDR222     SARADC_9.ECDR[94].R           /* External Channel Data Register */
#define SARADC_9_ECDR223     SARADC_9.ECDR[95].R           /* External Channel Data Register */
#define SARADC_9_ECDR224     SARADC_9.ECDR[96].R           /* External Channel Data Register */
#define SARADC_9_ECDR225     SARADC_9.ECDR[97].R           /* External Channel Data Register */
#define SARADC_9_ECDR226     SARADC_9.ECDR[98].R           /* External Channel Data Register */
#define SARADC_9_ECDR227     SARADC_9.ECDR[99].R           /* External Channel Data Register */
#define SARADC_9_ECDR228     SARADC_9.ECDR[100].R          /* External Channel Data Register */
#define SARADC_9_ECDR229     SARADC_9.ECDR[101].R          /* External Channel Data Register */
#define SARADC_9_ECDR230     SARADC_9.ECDR[102].R          /* External Channel Data Register */
#define SARADC_9_ECDR231     SARADC_9.ECDR[103].R          /* External Channel Data Register */
#define SARADC_9_ECDR232     SARADC_9.ECDR[104].R          /* External Channel Data Register */
#define SARADC_9_ECDR233     SARADC_9.ECDR[105].R          /* External Channel Data Register */
#define SARADC_9_ECDR234     SARADC_9.ECDR[106].R          /* External Channel Data Register */
#define SARADC_9_ECDR235     SARADC_9.ECDR[107].R          /* External Channel Data Register */
#define SARADC_9_ECDR236     SARADC_9.ECDR[108].R          /* External Channel Data Register */
#define SARADC_9_ECDR237     SARADC_9.ECDR[109].R          /* External Channel Data Register */
#define SARADC_9_ECDR238     SARADC_9.ECDR[110].R          /* External Channel Data Register */
#define SARADC_9_ECDR239     SARADC_9.ECDR[111].R          /* External Channel Data Register */
#define SARADC_9_ECDR240     SARADC_9.ECDR[112].R          /* External Channel Data Register */
#define SARADC_9_ECDR241     SARADC_9.ECDR[113].R          /* External Channel Data Register */
#define SARADC_9_ECDR242     SARADC_9.ECDR[114].R          /* External Channel Data Register */
#define SARADC_9_ECDR243     SARADC_9.ECDR[115].R          /* External Channel Data Register */
#define SARADC_9_ECDR244     SARADC_9.ECDR[116].R          /* External Channel Data Register */
#define SARADC_9_ECDR245     SARADC_9.ECDR[117].R          /* External Channel Data Register */
#define SARADC_9_ECDR246     SARADC_9.ECDR[118].R          /* External Channel Data Register */
#define SARADC_9_ECDR247     SARADC_9.ECDR[119].R          /* External Channel Data Register */
#define SARADC_9_ECDR248     SARADC_9.ECDR[120].R          /* External Channel Data Register */
#define SARADC_9_ECDR249     SARADC_9.ECDR[121].R          /* External Channel Data Register */
#define SARADC_9_ECDR250     SARADC_9.ECDR[122].R          /* External Channel Data Register */
#define SARADC_9_ECDR251     SARADC_9.ECDR[123].R          /* External Channel Data Register */
#define SARADC_9_ECDR252     SARADC_9.ECDR[124].R          /* External Channel Data Register */
#define SARADC_9_ECDR253     SARADC_9.ECDR[125].R          /* External Channel Data Register */
#define SARADC_9_ECDR254     SARADC_9.ECDR[126].R          /* External Channel Data Register */
#define SARADC_9_ECDR255     SARADC_9.ECDR[127].R          /* External Channel Data Register */

/* SARADC */
#define SARADC_B_MCR         SARADC_B.MCR.R                /* Main Configuration Register */
#define SARADC_B_MSR         SARADC_B.MSR.R                /* Main Status Register */
#define SARADC_B_ISR         SARADC_B.ISR.R                /* Interrupt Status Register */
#define SARADC_B_ICIPR0      SARADC_B.ICIPR[0].R           /* Internal channel Interrupt Pending Register */
#define SARADC_B_ICIPR1      SARADC_B.ICIPR[1].R           /* Internal channel Interrupt Pending Register */
#define SARADC_B_ICIPR2      SARADC_B.ICIPR[2].R           /* Internal channel Interrupt Pending Register */
#define SARADC_B_IMR         SARADC_B.IMR.R                /* Interrupt Mask Register */
#define SARADC_B_ICIMR0      SARADC_B.ICIMR[0].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_B_ICIMR1      SARADC_B.ICIMR[1].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_B_ICIMR2      SARADC_B.ICIMR[2].R           /* Internal Channel Interrupt Mask Register */
#define SARADC_B_WTISR       SARADC_B.WTISR.R              /* Watchdog Threshold Interrupt Status Register */
#define SARADC_B_WTIMR       SARADC_B.WTIMR.R              /* Watchdog Threshold Interrupt Mask Register */
#define SARADC_B_DMAE        SARADC_B.DMAE.R               /* DMA Enable Register */
#define SARADC_B_ICDSR0      SARADC_B.ICDSR[0].R           /* Internal Channel DMA Select Register */
#define SARADC_B_ICDSR1      SARADC_B.ICDSR[1].R           /* Internal Channel DMA Select Register */
#define SARADC_B_ICDSR2      SARADC_B.ICDSR[2].R           /* Internal Channel DMA Select Register */
#define SARADC_B_WTHRHLR0    SARADC_B.WTHRHLR[0].R         /* Watchdog Threshold Register */
#define SARADC_B_WTHRHLR1    SARADC_B.WTHRHLR[1].R         /* Watchdog Threshold Register */
#define SARADC_B_WTHRHLR2    SARADC_B.WTHRHLR[2].R         /* Watchdog Threshold Register */
#define SARADC_B_WTHRHLR3    SARADC_B.WTHRHLR[3].R         /* Watchdog Threshold Register */
#define SARADC_B_CTR0        SARADC_B.CTR[0].R             /* Conversion Timing Register */
#define SARADC_B_CTR1        SARADC_B.CTR[1].R             /* Conversion Timing Register */
#define SARADC_B_CTR2        SARADC_B.CTR[2].R             /* Conversion Timing Register */
#define SARADC_B_CTR3        SARADC_B.CTR[3].R             /* Conversion Timing Register */
#define SARADC_B_ICNCMR0     SARADC_B.ICNCMR[0].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_B_ICNCMR1     SARADC_B.ICNCMR[1].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_B_ICNCMR2     SARADC_B.ICNCMR[2].R          /* Internal Channel Normal Conversion Mask Register */
#define SARADC_B_ICJCMR0     SARADC_B.ICJCMR[0].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_B_ICJCMR1     SARADC_B.ICJCMR[1].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_B_ICJCMR2     SARADC_B.ICJCMR[2].R          /* Internal Channel Injected Conversion Mask Register */
#define SARADC_B_PDEDR       SARADC_B.PDEDR.R              /* Power Down Exit Delay Register */
#define SARADC_B_ICDR0       SARADC_B.ICDR[0].R            /* Internal Channel Data Register */
#define SARADC_B_ICDR1       SARADC_B.ICDR[1].R            /* Internal Channel Data Register */
#define SARADC_B_ICDR2       SARADC_B.ICDR[2].R            /* Internal Channel Data Register */
#define SARADC_B_ICDR3       SARADC_B.ICDR[3].R            /* Internal Channel Data Register */
#define SARADC_B_ICDR4       SARADC_B.ICDR[4].R            /* Internal Channel Data Register */
#define SARADC_B_ICDR5       SARADC_B.ICDR[5].R            /* Internal Channel Data Register */
#define SARADC_B_ICDR6       SARADC_B.ICDR[6].R            /* Internal Channel Data Register */
#define SARADC_B_ICDR7       SARADC_B.ICDR[7].R            /* Internal Channel Data Register */
#define SARADC_B_ICDR8       SARADC_B.ICDR[8].R            /* Internal Channel Data Register */
#define SARADC_B_ICDR9       SARADC_B.ICDR[9].R            /* Internal Channel Data Register */
#define SARADC_B_ICDR10      SARADC_B.ICDR[10].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR11      SARADC_B.ICDR[11].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR12      SARADC_B.ICDR[12].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR13      SARADC_B.ICDR[13].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR14      SARADC_B.ICDR[14].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR15      SARADC_B.ICDR[15].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR16      SARADC_B.ICDR[16].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR17      SARADC_B.ICDR[17].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR18      SARADC_B.ICDR[18].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR19      SARADC_B.ICDR[19].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR20      SARADC_B.ICDR[20].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR21      SARADC_B.ICDR[21].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR22      SARADC_B.ICDR[22].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR23      SARADC_B.ICDR[23].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR24      SARADC_B.ICDR[24].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR25      SARADC_B.ICDR[25].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR26      SARADC_B.ICDR[26].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR27      SARADC_B.ICDR[27].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR28      SARADC_B.ICDR[28].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR29      SARADC_B.ICDR[29].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR30      SARADC_B.ICDR[30].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR31      SARADC_B.ICDR[31].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR32      SARADC_B.ICDR[32].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR33      SARADC_B.ICDR[33].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR34      SARADC_B.ICDR[34].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR35      SARADC_B.ICDR[35].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR36      SARADC_B.ICDR[36].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR37      SARADC_B.ICDR[37].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR38      SARADC_B.ICDR[38].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR39      SARADC_B.ICDR[39].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR40      SARADC_B.ICDR[40].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR41      SARADC_B.ICDR[41].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR42      SARADC_B.ICDR[42].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR43      SARADC_B.ICDR[43].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR44      SARADC_B.ICDR[44].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR45      SARADC_B.ICDR[45].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR46      SARADC_B.ICDR[46].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR47      SARADC_B.ICDR[47].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR48      SARADC_B.ICDR[48].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR49      SARADC_B.ICDR[49].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR50      SARADC_B.ICDR[50].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR51      SARADC_B.ICDR[51].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR52      SARADC_B.ICDR[52].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR53      SARADC_B.ICDR[53].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR54      SARADC_B.ICDR[54].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR55      SARADC_B.ICDR[55].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR56      SARADC_B.ICDR[56].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR57      SARADC_B.ICDR[57].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR58      SARADC_B.ICDR[58].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR59      SARADC_B.ICDR[59].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR60      SARADC_B.ICDR[60].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR61      SARADC_B.ICDR[61].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR62      SARADC_B.ICDR[62].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR63      SARADC_B.ICDR[63].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR64      SARADC_B.ICDR[64].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR65      SARADC_B.ICDR[65].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR66      SARADC_B.ICDR[66].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR67      SARADC_B.ICDR[67].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR68      SARADC_B.ICDR[68].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR69      SARADC_B.ICDR[69].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR70      SARADC_B.ICDR[70].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR71      SARADC_B.ICDR[71].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR72      SARADC_B.ICDR[72].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR73      SARADC_B.ICDR[73].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR74      SARADC_B.ICDR[74].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR75      SARADC_B.ICDR[75].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR76      SARADC_B.ICDR[76].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR77      SARADC_B.ICDR[77].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR78      SARADC_B.ICDR[78].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR79      SARADC_B.ICDR[79].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR80      SARADC_B.ICDR[80].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR81      SARADC_B.ICDR[81].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR82      SARADC_B.ICDR[82].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR83      SARADC_B.ICDR[83].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR84      SARADC_B.ICDR[84].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR85      SARADC_B.ICDR[85].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR86      SARADC_B.ICDR[86].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR87      SARADC_B.ICDR[87].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR88      SARADC_B.ICDR[88].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR89      SARADC_B.ICDR[89].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR90      SARADC_B.ICDR[90].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR91      SARADC_B.ICDR[91].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR92      SARADC_B.ICDR[92].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR93      SARADC_B.ICDR[93].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR94      SARADC_B.ICDR[94].R           /* Internal Channel Data Register */
#define SARADC_B_ICDR95      SARADC_B.ICDR[95].R           /* Internal Channel Data Register */
#define SARADC_B_ICWSELR0    SARADC_B.ICWSELR[0].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_B_ICWSELR1    SARADC_B.ICWSELR[1].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_B_ICWSELR2    SARADC_B.ICWSELR[2].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_B_ICWSELR3    SARADC_B.ICWSELR[3].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_B_ICWSELR4    SARADC_B.ICWSELR[4].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_B_ICWSELR5    SARADC_B.ICWSELR[5].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_B_ICWSELR6    SARADC_B.ICWSELR[6].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_B_ICWSELR7    SARADC_B.ICWSELR[7].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_B_ICWSELR8    SARADC_B.ICWSELR[8].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_B_ICWSELR9    SARADC_B.ICWSELR[9].R         /* Internal Channel Watchdog Selection Register */
#define SARADC_B_ICWSELR10   SARADC_B.ICWSELR[10].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_B_ICWSELR11   SARADC_B.ICWSELR[11].R        /* Internal Channel Watchdog Selection Register */
#define SARADC_B_ICWENR0     SARADC_B.ICWENR[0].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_B_ICWENR1     SARADC_B.ICWENR[1].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_B_ICWENR2     SARADC_B.ICWENR[2].R          /* Internal Channel Watchdog Enable Register */
#define SARADC_B_ICAWORR0    SARADC_B.ICAWORR[0].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_B_ICAWORR1    SARADC_B.ICAWORR[1].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_B_ICAWORR2    SARADC_B.ICAWORR[2].R         /* Internal Channel Analog Watchdog Out of Range register */
#define SARADC_B_TCIPR       SARADC_B.TCIPR.R              /* Test Channel Interrupt Pending Register */
#define SARADC_B_TCIMR       SARADC_B.TCIMR.R              /* Test Channel Interrupt Mask Register */
#define SARADC_B_TCDSR       SARADC_B.TCDSR.R              /* Test Channel DMA Select Register */
#define SARADC_B_TCNCMR      SARADC_B.TCNCMR.R             /* Test Channel Normal Conversion Mask Register */
#define SARADC_B_TCJCMR      SARADC_B.TCJCMR.R             /* Test Channel Injected Conversion Mask Register */
#define SARADC_B_TCWSELR0    SARADC_B.TCWSELR[0].R         /* Test Channel Watchdog Selection Register */
#define SARADC_B_TCWSELR1    SARADC_B.TCWSELR[1].R         /* Test Channel Watchdog Selection Register */
#define SARADC_B_TCWSELR2    SARADC_B.TCWSELR[2].R         /* Test Channel Watchdog Selection Register */
#define SARADC_B_TCWSELR3    SARADC_B.TCWSELR[3].R         /* Test Channel Watchdog Selection Register */
#define SARADC_B_TCWENR      SARADC_B.TCWENR.R             /* Test Channel Watchdog Enable Register */
#define SARADC_B_TCAWORR     SARADC_B.TCAWORR.R            /* Test Channel Analog Watchdog Out of Range Register */
#define SARADC_B_TCCAPR0     SARADC_B.TCCAPR[0].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_B_TCCAPR1     SARADC_B.TCCAPR[1].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_B_TCCAPR2     SARADC_B.TCCAPR[2].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_B_TCCAPR3     SARADC_B.TCCAPR[3].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_B_TCCAPR4     SARADC_B.TCCAPR[4].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_B_TCCAPR5     SARADC_B.TCCAPR[5].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_B_TCCAPR6     SARADC_B.TCCAPR[6].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_B_TCCAPR7     SARADC_B.TCCAPR[7].R          /* Test Channel Connection with Analog Pin Register */
#define SARADC_B_TCDR96      SARADC_B.TCDR[0].R            /* Test Channel Data Register */
#define SARADC_B_TCDR97      SARADC_B.TCDR[1].R            /* Test Channel Data Register */
#define SARADC_B_TCDR98      SARADC_B.TCDR[2].R            /* Test Channel Data Register */
#define SARADC_B_TCDR99      SARADC_B.TCDR[3].R            /* Test Channel Data Register */
#define SARADC_B_TCDR100     SARADC_B.TCDR[4].R            /* Test Channel Data Register */
#define SARADC_B_TCDR101     SARADC_B.TCDR[5].R            /* Test Channel Data Register */
#define SARADC_B_TCDR102     SARADC_B.TCDR[6].R            /* Test Channel Data Register */
#define SARADC_B_TCDR103     SARADC_B.TCDR[7].R            /* Test Channel Data Register */
#define SARADC_B_TCDR104     SARADC_B.TCDR[8].R            /* Test Channel Data Register */
#define SARADC_B_TCDR105     SARADC_B.TCDR[9].R            /* Test Channel Data Register */
#define SARADC_B_TCDR106     SARADC_B.TCDR[10].R           /* Test Channel Data Register */
#define SARADC_B_TCDR107     SARADC_B.TCDR[11].R           /* Test Channel Data Register */
#define SARADC_B_TCDR108     SARADC_B.TCDR[12].R           /* Test Channel Data Register */
#define SARADC_B_TCDR109     SARADC_B.TCDR[13].R           /* Test Channel Data Register */
#define SARADC_B_TCDR110     SARADC_B.TCDR[14].R           /* Test Channel Data Register */
#define SARADC_B_TCDR111     SARADC_B.TCDR[15].R           /* Test Channel Data Register */
#define SARADC_B_TCDR112     SARADC_B.TCDR[16].R           /* Test Channel Data Register */
#define SARADC_B_TCDR113     SARADC_B.TCDR[17].R           /* Test Channel Data Register */
#define SARADC_B_TCDR114     SARADC_B.TCDR[18].R           /* Test Channel Data Register */
#define SARADC_B_TCDR115     SARADC_B.TCDR[19].R           /* Test Channel Data Register */
#define SARADC_B_TCDR116     SARADC_B.TCDR[20].R           /* Test Channel Data Register */
#define SARADC_B_TCDR117     SARADC_B.TCDR[21].R           /* Test Channel Data Register */
#define SARADC_B_TCDR118     SARADC_B.TCDR[22].R           /* Test Channel Data Register */
#define SARADC_B_TCDR119     SARADC_B.TCDR[23].R           /* Test Channel Data Register */
#define SARADC_B_TCDR120     SARADC_B.TCDR[24].R           /* Test Channel Data Register */
#define SARADC_B_TCDR121     SARADC_B.TCDR[25].R           /* Test Channel Data Register */
#define SARADC_B_TCDR122     SARADC_B.TCDR[26].R           /* Test Channel Data Register */
#define SARADC_B_TCDR123     SARADC_B.TCDR[27].R           /* Test Channel Data Register */
#define SARADC_B_TCDR124     SARADC_B.TCDR[28].R           /* Test Channel Data Register */
#define SARADC_B_TCDR125     SARADC_B.TCDR[29].R           /* Test Channel Data Register */
#define SARADC_B_TCDR126     SARADC_B.TCDR[30].R           /* Test Channel Data Register */
#define SARADC_B_TCDR127     SARADC_B.TCDR[31].R           /* Test Channel Data Register */
#define SARADC_B_ECDSDR      SARADC_B.ECDSDR.R             /* External Channel Decode Signals Delay Register */
#define SARADC_B_ECIPR0      SARADC_B.ECIPR[0].R           /* External Channel Interrupt Pending Register */
#define SARADC_B_ECIPR1      SARADC_B.ECIPR[1].R           /* External Channel Interrupt Pending Register */
#define SARADC_B_ECIPR2      SARADC_B.ECIPR[2].R           /* External Channel Interrupt Pending Register */
#define SARADC_B_ECIPR3      SARADC_B.ECIPR[3].R           /* External Channel Interrupt Pending Register */
#define SARADC_B_ECIMR0      SARADC_B.ECIMR[0].R           /* External Channel Interrupt Mask Register */
#define SARADC_B_ECIMR1      SARADC_B.ECIMR[1].R           /* External Channel Interrupt Mask Register */
#define SARADC_B_ECIMR2      SARADC_B.ECIMR[2].R           /* External Channel Interrupt Mask Register */
#define SARADC_B_ECIMR3      SARADC_B.ECIMR[3].R           /* External Channel Interrupt Mask Register */
#define SARADC_B_ECDSR0      SARADC_B.ECDSR[0].R           /* External Channel DMA Select Register */
#define SARADC_B_ECDSR1      SARADC_B.ECDSR[1].R           /* External Channel DMA Select Register */
#define SARADC_B_ECDSR2      SARADC_B.ECDSR[2].R           /* External Channel DMA Select Register */
#define SARADC_B_ECDSR3      SARADC_B.ECDSR[3].R           /* External Channel DMA Select Register */
#define SARADC_B_ECNCMR0     SARADC_B.ECNCMR[0].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_B_ECNCMR1     SARADC_B.ECNCMR[1].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_B_ECNCMR2     SARADC_B.ECNCMR[2].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_B_ECNCMR3     SARADC_B.ECNCMR[3].R          /* External Channel Normal Conversion Mask Register */
#define SARADC_B_ECJCMR0     SARADC_B.ECJCMR[0].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_B_ECJCMR1     SARADC_B.ECJCMR[1].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_B_ECJCMR2     SARADC_B.ECJCMR[2].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_B_ECJCMR3     SARADC_B.ECJCMR[3].R          /* External Channel Injected Conversion Mask Register */
#define SARADC_B_ECWSELR0    SARADC_B.ECWSELR[0].R         /* External Channel Watchdog Selection Register */
#define SARADC_B_ECWSELR1    SARADC_B.ECWSELR[1].R         /* External Channel Watchdog Selection Register */
#define SARADC_B_ECWSELR2    SARADC_B.ECWSELR[2].R         /* External Channel Watchdog Selection Register */
#define SARADC_B_ECWSELR3    SARADC_B.ECWSELR[3].R         /* External Channel Watchdog Selection Register */
#define SARADC_B_ECWSELR4    SARADC_B.ECWSELR[4].R         /* External Channel Watchdog Selection Register */
#define SARADC_B_ECWSELR5    SARADC_B.ECWSELR[5].R         /* External Channel Watchdog Selection Register */
#define SARADC_B_ECWSELR6    SARADC_B.ECWSELR[6].R         /* External Channel Watchdog Selection Register */
#define SARADC_B_ECWSELR7    SARADC_B.ECWSELR[7].R         /* External Channel Watchdog Selection Register */
#define SARADC_B_ECWSELR8    SARADC_B.ECWSELR[8].R         /* External Channel Watchdog Selection Register */
#define SARADC_B_ECWSELR9    SARADC_B.ECWSELR[9].R         /* External Channel Watchdog Selection Register */
#define SARADC_B_ECWSELR10   SARADC_B.ECWSELR[10].R        /* External Channel Watchdog Selection Register */
#define SARADC_B_ECWSELR11   SARADC_B.ECWSELR[11].R        /* External Channel Watchdog Selection Register */
#define SARADC_B_ECWSELR12   SARADC_B.ECWSELR[12].R        /* External Channel Watchdog Selection Register */
#define SARADC_B_ECWSELR13   SARADC_B.ECWSELR[13].R        /* External Channel Watchdog Selection Register */
#define SARADC_B_ECWSELR14   SARADC_B.ECWSELR[14].R        /* External Channel Watchdog Selection Register */
#define SARADC_B_ECWSELR15   SARADC_B.ECWSELR[15].R        /* External Channel Watchdog Selection Register */
#define SARADC_B_ECWENR0     SARADC_B.ECWENR[0].R          /* External Channel Watchdog Enable Register */
#define SARADC_B_ECWENR1     SARADC_B.ECWENR[1].R          /* External Channel Watchdog Enable Register */
#define SARADC_B_ECWENR2     SARADC_B.ECWENR[2].R          /* External Channel Watchdog Enable Register */
#define SARADC_B_ECWENR3     SARADC_B.ECWENR[3].R          /* External Channel Watchdog Enable Register */
#define SARADC_B_ECAWORR0    SARADC_B.ECAWORR[0].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_B_ECAWORR1    SARADC_B.ECAWORR[1].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_B_ECAWORR2    SARADC_B.ECAWORR[2].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_B_ECAWORR3    SARADC_B.ECAWORR[3].R         /* External Channel Analog Watchdog Out of Range register */
#define SARADC_B_ECMICR0     SARADC_B.ECMICR[0].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_B_ECMICR1     SARADC_B.ECMICR[1].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_B_ECMICR2     SARADC_B.ECMICR[2].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_B_ECMICR3     SARADC_B.ECMICR[3].R          /* External Channel Mapping to Internal Channel Register */
#define SARADC_B_ECDR128     SARADC_B.ECDR[0].R            /* External Channel Data Register */
#define SARADC_B_ECDR129     SARADC_B.ECDR[1].R            /* External Channel Data Register */
#define SARADC_B_ECDR130     SARADC_B.ECDR[2].R            /* External Channel Data Register */
#define SARADC_B_ECDR131     SARADC_B.ECDR[3].R            /* External Channel Data Register */
#define SARADC_B_ECDR132     SARADC_B.ECDR[4].R            /* External Channel Data Register */
#define SARADC_B_ECDR133     SARADC_B.ECDR[5].R            /* External Channel Data Register */
#define SARADC_B_ECDR134     SARADC_B.ECDR[6].R            /* External Channel Data Register */
#define SARADC_B_ECDR135     SARADC_B.ECDR[7].R            /* External Channel Data Register */
#define SARADC_B_ECDR136     SARADC_B.ECDR[8].R            /* External Channel Data Register */
#define SARADC_B_ECDR137     SARADC_B.ECDR[9].R            /* External Channel Data Register */
#define SARADC_B_ECDR138     SARADC_B.ECDR[10].R           /* External Channel Data Register */
#define SARADC_B_ECDR139     SARADC_B.ECDR[11].R           /* External Channel Data Register */
#define SARADC_B_ECDR140     SARADC_B.ECDR[12].R           /* External Channel Data Register */
#define SARADC_B_ECDR141     SARADC_B.ECDR[13].R           /* External Channel Data Register */
#define SARADC_B_ECDR142     SARADC_B.ECDR[14].R           /* External Channel Data Register */
#define SARADC_B_ECDR143     SARADC_B.ECDR[15].R           /* External Channel Data Register */
#define SARADC_B_ECDR144     SARADC_B.ECDR[16].R           /* External Channel Data Register */
#define SARADC_B_ECDR145     SARADC_B.ECDR[17].R           /* External Channel Data Register */
#define SARADC_B_ECDR146     SARADC_B.ECDR[18].R           /* External Channel Data Register */
#define SARADC_B_ECDR147     SARADC_B.ECDR[19].R           /* External Channel Data Register */
#define SARADC_B_ECDR148     SARADC_B.ECDR[20].R           /* External Channel Data Register */
#define SARADC_B_ECDR149     SARADC_B.ECDR[21].R           /* External Channel Data Register */
#define SARADC_B_ECDR150     SARADC_B.ECDR[22].R           /* External Channel Data Register */
#define SARADC_B_ECDR151     SARADC_B.ECDR[23].R           /* External Channel Data Register */
#define SARADC_B_ECDR152     SARADC_B.ECDR[24].R           /* External Channel Data Register */
#define SARADC_B_ECDR153     SARADC_B.ECDR[25].R           /* External Channel Data Register */
#define SARADC_B_ECDR154     SARADC_B.ECDR[26].R           /* External Channel Data Register */
#define SARADC_B_ECDR155     SARADC_B.ECDR[27].R           /* External Channel Data Register */
#define SARADC_B_ECDR156     SARADC_B.ECDR[28].R           /* External Channel Data Register */
#define SARADC_B_ECDR157     SARADC_B.ECDR[29].R           /* External Channel Data Register */
#define SARADC_B_ECDR158     SARADC_B.ECDR[30].R           /* External Channel Data Register */
#define SARADC_B_ECDR159     SARADC_B.ECDR[31].R           /* External Channel Data Register */
#define SARADC_B_ECDR160     SARADC_B.ECDR[32].R           /* External Channel Data Register */
#define SARADC_B_ECDR161     SARADC_B.ECDR[33].R           /* External Channel Data Register */
#define SARADC_B_ECDR162     SARADC_B.ECDR[34].R           /* External Channel Data Register */
#define SARADC_B_ECDR163     SARADC_B.ECDR[35].R           /* External Channel Data Register */
#define SARADC_B_ECDR164     SARADC_B.ECDR[36].R           /* External Channel Data Register */
#define SARADC_B_ECDR165     SARADC_B.ECDR[37].R           /* External Channel Data Register */
#define SARADC_B_ECDR166     SARADC_B.ECDR[38].R           /* External Channel Data Register */
#define SARADC_B_ECDR167     SARADC_B.ECDR[39].R           /* External Channel Data Register */
#define SARADC_B_ECDR168     SARADC_B.ECDR[40].R           /* External Channel Data Register */
#define SARADC_B_ECDR169     SARADC_B.ECDR[41].R           /* External Channel Data Register */
#define SARADC_B_ECDR170     SARADC_B.ECDR[42].R           /* External Channel Data Register */
#define SARADC_B_ECDR171     SARADC_B.ECDR[43].R           /* External Channel Data Register */
#define SARADC_B_ECDR172     SARADC_B.ECDR[44].R           /* External Channel Data Register */
#define SARADC_B_ECDR173     SARADC_B.ECDR[45].R           /* External Channel Data Register */
#define SARADC_B_ECDR174     SARADC_B.ECDR[46].R           /* External Channel Data Register */
#define SARADC_B_ECDR175     SARADC_B.ECDR[47].R           /* External Channel Data Register */
#define SARADC_B_ECDR176     SARADC_B.ECDR[48].R           /* External Channel Data Register */
#define SARADC_B_ECDR177     SARADC_B.ECDR[49].R           /* External Channel Data Register */
#define SARADC_B_ECDR178     SARADC_B.ECDR[50].R           /* External Channel Data Register */
#define SARADC_B_ECDR179     SARADC_B.ECDR[51].R           /* External Channel Data Register */
#define SARADC_B_ECDR180     SARADC_B.ECDR[52].R           /* External Channel Data Register */
#define SARADC_B_ECDR181     SARADC_B.ECDR[53].R           /* External Channel Data Register */
#define SARADC_B_ECDR182     SARADC_B.ECDR[54].R           /* External Channel Data Register */
#define SARADC_B_ECDR183     SARADC_B.ECDR[55].R           /* External Channel Data Register */
#define SARADC_B_ECDR184     SARADC_B.ECDR[56].R           /* External Channel Data Register */
#define SARADC_B_ECDR185     SARADC_B.ECDR[57].R           /* External Channel Data Register */
#define SARADC_B_ECDR186     SARADC_B.ECDR[58].R           /* External Channel Data Register */
#define SARADC_B_ECDR187     SARADC_B.ECDR[59].R           /* External Channel Data Register */
#define SARADC_B_ECDR188     SARADC_B.ECDR[60].R           /* External Channel Data Register */
#define SARADC_B_ECDR189     SARADC_B.ECDR[61].R           /* External Channel Data Register */
#define SARADC_B_ECDR190     SARADC_B.ECDR[62].R           /* External Channel Data Register */
#define SARADC_B_ECDR191     SARADC_B.ECDR[63].R           /* External Channel Data Register */
#define SARADC_B_ECDR192     SARADC_B.ECDR[64].R           /* External Channel Data Register */
#define SARADC_B_ECDR193     SARADC_B.ECDR[65].R           /* External Channel Data Register */
#define SARADC_B_ECDR194     SARADC_B.ECDR[66].R           /* External Channel Data Register */
#define SARADC_B_ECDR195     SARADC_B.ECDR[67].R           /* External Channel Data Register */
#define SARADC_B_ECDR196     SARADC_B.ECDR[68].R           /* External Channel Data Register */
#define SARADC_B_ECDR197     SARADC_B.ECDR[69].R           /* External Channel Data Register */
#define SARADC_B_ECDR198     SARADC_B.ECDR[70].R           /* External Channel Data Register */
#define SARADC_B_ECDR199     SARADC_B.ECDR[71].R           /* External Channel Data Register */
#define SARADC_B_ECDR200     SARADC_B.ECDR[72].R           /* External Channel Data Register */
#define SARADC_B_ECDR201     SARADC_B.ECDR[73].R           /* External Channel Data Register */
#define SARADC_B_ECDR202     SARADC_B.ECDR[74].R           /* External Channel Data Register */
#define SARADC_B_ECDR203     SARADC_B.ECDR[75].R           /* External Channel Data Register */
#define SARADC_B_ECDR204     SARADC_B.ECDR[76].R           /* External Channel Data Register */
#define SARADC_B_ECDR205     SARADC_B.ECDR[77].R           /* External Channel Data Register */
#define SARADC_B_ECDR206     SARADC_B.ECDR[78].R           /* External Channel Data Register */
#define SARADC_B_ECDR207     SARADC_B.ECDR[79].R           /* External Channel Data Register */
#define SARADC_B_ECDR208     SARADC_B.ECDR[80].R           /* External Channel Data Register */
#define SARADC_B_ECDR209     SARADC_B.ECDR[81].R           /* External Channel Data Register */
#define SARADC_B_ECDR210     SARADC_B.ECDR[82].R           /* External Channel Data Register */
#define SARADC_B_ECDR211     SARADC_B.ECDR[83].R           /* External Channel Data Register */
#define SARADC_B_ECDR212     SARADC_B.ECDR[84].R           /* External Channel Data Register */
#define SARADC_B_ECDR213     SARADC_B.ECDR[85].R           /* External Channel Data Register */
#define SARADC_B_ECDR214     SARADC_B.ECDR[86].R           /* External Channel Data Register */
#define SARADC_B_ECDR215     SARADC_B.ECDR[87].R           /* External Channel Data Register */
#define SARADC_B_ECDR216     SARADC_B.ECDR[88].R           /* External Channel Data Register */
#define SARADC_B_ECDR217     SARADC_B.ECDR[89].R           /* External Channel Data Register */
#define SARADC_B_ECDR218     SARADC_B.ECDR[90].R           /* External Channel Data Register */
#define SARADC_B_ECDR219     SARADC_B.ECDR[91].R           /* External Channel Data Register */
#define SARADC_B_ECDR220     SARADC_B.ECDR[92].R           /* External Channel Data Register */
#define SARADC_B_ECDR221     SARADC_B.ECDR[93].R           /* External Channel Data Register */
#define SARADC_B_ECDR222     SARADC_B.ECDR[94].R           /* External Channel Data Register */
#define SARADC_B_ECDR223     SARADC_B.ECDR[95].R           /* External Channel Data Register */
#define SARADC_B_ECDR224     SARADC_B.ECDR[96].R           /* External Channel Data Register */
#define SARADC_B_ECDR225     SARADC_B.ECDR[97].R           /* External Channel Data Register */
#define SARADC_B_ECDR226     SARADC_B.ECDR[98].R           /* External Channel Data Register */
#define SARADC_B_ECDR227     SARADC_B.ECDR[99].R           /* External Channel Data Register */
#define SARADC_B_ECDR228     SARADC_B.ECDR[100].R          /* External Channel Data Register */
#define SARADC_B_ECDR229     SARADC_B.ECDR[101].R          /* External Channel Data Register */
#define SARADC_B_ECDR230     SARADC_B.ECDR[102].R          /* External Channel Data Register */
#define SARADC_B_ECDR231     SARADC_B.ECDR[103].R          /* External Channel Data Register */
#define SARADC_B_ECDR232     SARADC_B.ECDR[104].R          /* External Channel Data Register */
#define SARADC_B_ECDR233     SARADC_B.ECDR[105].R          /* External Channel Data Register */
#define SARADC_B_ECDR234     SARADC_B.ECDR[106].R          /* External Channel Data Register */
#define SARADC_B_ECDR235     SARADC_B.ECDR[107].R          /* External Channel Data Register */
#define SARADC_B_ECDR236     SARADC_B.ECDR[108].R          /* External Channel Data Register */
#define SARADC_B_ECDR237     SARADC_B.ECDR[109].R          /* External Channel Data Register */
#define SARADC_B_ECDR238     SARADC_B.ECDR[110].R          /* External Channel Data Register */
#define SARADC_B_ECDR239     SARADC_B.ECDR[111].R          /* External Channel Data Register */
#define SARADC_B_ECDR240     SARADC_B.ECDR[112].R          /* External Channel Data Register */
#define SARADC_B_ECDR241     SARADC_B.ECDR[113].R          /* External Channel Data Register */
#define SARADC_B_ECDR242     SARADC_B.ECDR[114].R          /* External Channel Data Register */
#define SARADC_B_ECDR243     SARADC_B.ECDR[115].R          /* External Channel Data Register */
#define SARADC_B_ECDR244     SARADC_B.ECDR[116].R          /* External Channel Data Register */
#define SARADC_B_ECDR245     SARADC_B.ECDR[117].R          /* External Channel Data Register */
#define SARADC_B_ECDR246     SARADC_B.ECDR[118].R          /* External Channel Data Register */
#define SARADC_B_ECDR247     SARADC_B.ECDR[119].R          /* External Channel Data Register */
#define SARADC_B_ECDR248     SARADC_B.ECDR[120].R          /* External Channel Data Register */
#define SARADC_B_ECDR249     SARADC_B.ECDR[121].R          /* External Channel Data Register */
#define SARADC_B_ECDR250     SARADC_B.ECDR[122].R          /* External Channel Data Register */
#define SARADC_B_ECDR251     SARADC_B.ECDR[123].R          /* External Channel Data Register */
#define SARADC_B_ECDR252     SARADC_B.ECDR[124].R          /* External Channel Data Register */
#define SARADC_B_ECDR253     SARADC_B.ECDR[125].R          /* External Channel Data Register */
#define SARADC_B_ECDR254     SARADC_B.ECDR[126].R          /* External Channel Data Register */
#define SARADC_B_ECDR255     SARADC_B.ECDR[127].R          /* External Channel Data Register */

/* SDADC */
#define SDADC_0_MCR          SDADC_0.MCR.R                 /* Module Configuration Register */
#define SDADC_0_CSR          SDADC_0.CSR.R                 /* Channel Selection Register */
#define SDADC_0_RKR          SDADC_0.RKR.R                 /* Reset Key Register */
#define SDADC_0_SFR          SDADC_0.SFR.R                 /* Status Flag Register */
#define SDADC_0_RSER         SDADC_0.RSER.R                /* Request Select and Enable Register */
#define SDADC_0_OSDR         SDADC_0.OSDR.R                /* Output Settling Delay Register */
#define SDADC_0_FCR          SDADC_0.FCR.R                 /* FIFO Control Register */
#define SDADC_0_STKR         SDADC_0.STKR.R                /* Software Trigger Key Register */
#define SDADC_0_CDR          SDADC_0.CDR.R                 /* Converted Data Register */
#define SDADC_0_WTHHLR       SDADC_0.WTHHLR.R              /* WDG Threshold Register */

/* SDADC */
#define SDADC_1_MCR          SDADC_1.MCR.R                 /* Module Configuration Register */
#define SDADC_1_CSR          SDADC_1.CSR.R                 /* Channel Selection Register */
#define SDADC_1_RKR          SDADC_1.RKR.R                 /* Reset Key Register */
#define SDADC_1_SFR          SDADC_1.SFR.R                 /* Status Flag Register */
#define SDADC_1_RSER         SDADC_1.RSER.R                /* Request Select and Enable Register */
#define SDADC_1_OSDR         SDADC_1.OSDR.R                /* Output Settling Delay Register */
#define SDADC_1_FCR          SDADC_1.FCR.R                 /* FIFO Control Register */
#define SDADC_1_STKR         SDADC_1.STKR.R                /* Software Trigger Key Register */
#define SDADC_1_CDR          SDADC_1.CDR.R                 /* Converted Data Register */
#define SDADC_1_WTHHLR       SDADC_1.WTHHLR.R              /* WDG Threshold Register */

/* SDADC */
#define SDADC_2_MCR          SDADC_2.MCR.R                 /* Module Configuration Register */
#define SDADC_2_CSR          SDADC_2.CSR.R                 /* Channel Selection Register */
#define SDADC_2_RKR          SDADC_2.RKR.R                 /* Reset Key Register */
#define SDADC_2_SFR          SDADC_2.SFR.R                 /* Status Flag Register */
#define SDADC_2_RSER         SDADC_2.RSER.R                /* Request Select and Enable Register */
#define SDADC_2_OSDR         SDADC_2.OSDR.R                /* Output Settling Delay Register */
#define SDADC_2_FCR          SDADC_2.FCR.R                 /* FIFO Control Register */
#define SDADC_2_STKR         SDADC_2.STKR.R                /* Software Trigger Key Register */
#define SDADC_2_CDR          SDADC_2.CDR.R                 /* Converted Data Register */
#define SDADC_2_WTHHLR       SDADC_2.WTHHLR.R              /* WDG Threshold Register */

/* SDADC */
#define SDADC_3_MCR          SDADC_3.MCR.R                 /* Module Configuration Register */
#define SDADC_3_CSR          SDADC_3.CSR.R                 /* Channel Selection Register */
#define SDADC_3_RKR          SDADC_3.RKR.R                 /* Reset Key Register */
#define SDADC_3_SFR          SDADC_3.SFR.R                 /* Status Flag Register */
#define SDADC_3_RSER         SDADC_3.RSER.R                /* Request Select and Enable Register */
#define SDADC_3_OSDR         SDADC_3.OSDR.R                /* Output Settling Delay Register */
#define SDADC_3_FCR          SDADC_3.FCR.R                 /* FIFO Control Register */
#define SDADC_3_STKR         SDADC_3.STKR.R                /* Software Trigger Key Register */
#define SDADC_3_CDR          SDADC_3.CDR.R                 /* Converted Data Register */
#define SDADC_3_WTHHLR       SDADC_3.WTHHLR.R              /* WDG Threshold Register */

/* SDADC */
#define SDADC_4_MCR          SDADC_4.MCR.R                 /* Module Configuration Register */
#define SDADC_4_CSR          SDADC_4.CSR.R                 /* Channel Selection Register */
#define SDADC_4_RKR          SDADC_4.RKR.R                 /* Reset Key Register */
#define SDADC_4_SFR          SDADC_4.SFR.R                 /* Status Flag Register */
#define SDADC_4_RSER         SDADC_4.RSER.R                /* Request Select and Enable Register */
#define SDADC_4_OSDR         SDADC_4.OSDR.R                /* Output Settling Delay Register */
#define SDADC_4_FCR          SDADC_4.FCR.R                 /* FIFO Control Register */
#define SDADC_4_STKR         SDADC_4.STKR.R                /* Software Trigger Key Register */
#define SDADC_4_CDR          SDADC_4.CDR.R                 /* Converted Data Register */
#define SDADC_4_WTHHLR       SDADC_4.WTHHLR.R              /* WDG Threshold Register */

/* SDADC */
#define SDADC_5_MCR          SDADC_5.MCR.R                 /* Module Configuration Register */
#define SDADC_5_CSR          SDADC_5.CSR.R                 /* Channel Selection Register */
#define SDADC_5_RKR          SDADC_5.RKR.R                 /* Reset Key Register */
#define SDADC_5_SFR          SDADC_5.SFR.R                 /* Status Flag Register */
#define SDADC_5_RSER         SDADC_5.RSER.R                /* Request Select and Enable Register */
#define SDADC_5_OSDR         SDADC_5.OSDR.R                /* Output Settling Delay Register */
#define SDADC_5_FCR          SDADC_5.FCR.R                 /* FIFO Control Register */
#define SDADC_5_STKR         SDADC_5.STKR.R                /* Software Trigger Key Register */
#define SDADC_5_CDR          SDADC_5.CDR.R                 /* Converted Data Register */
#define SDADC_5_WTHHLR       SDADC_5.WTHHLR.R              /* WDG Threshold Register */

/* SDADC */
#define SDADC_6_MCR          SDADC_6.MCR.R                 /* Module Configuration Register */
#define SDADC_6_CSR          SDADC_6.CSR.R                 /* Channel Selection Register */
#define SDADC_6_RKR          SDADC_6.RKR.R                 /* Reset Key Register */
#define SDADC_6_SFR          SDADC_6.SFR.R                 /* Status Flag Register */
#define SDADC_6_RSER         SDADC_6.RSER.R                /* Request Select and Enable Register */
#define SDADC_6_OSDR         SDADC_6.OSDR.R                /* Output Settling Delay Register */
#define SDADC_6_FCR          SDADC_6.FCR.R                 /* FIFO Control Register */
#define SDADC_6_STKR         SDADC_6.STKR.R                /* Software Trigger Key Register */
#define SDADC_6_CDR          SDADC_6.CDR.R                 /* Converted Data Register */
#define SDADC_6_WTHHLR       SDADC_6.WTHHLR.R              /* WDG Threshold Register */

/* SDADC */
#define SDADC_7_MCR          SDADC_7.MCR.R                 /* Module Configuration Register */
#define SDADC_7_CSR          SDADC_7.CSR.R                 /* Channel Selection Register */
#define SDADC_7_RKR          SDADC_7.RKR.R                 /* Reset Key Register */
#define SDADC_7_SFR          SDADC_7.SFR.R                 /* Status Flag Register */
#define SDADC_7_RSER         SDADC_7.RSER.R                /* Request Select and Enable Register */
#define SDADC_7_OSDR         SDADC_7.OSDR.R                /* Output Settling Delay Register */
#define SDADC_7_FCR          SDADC_7.FCR.R                 /* FIFO Control Register */
#define SDADC_7_STKR         SDADC_7.STKR.R                /* Software Trigger Key Register */
#define SDADC_7_CDR          SDADC_7.CDR.R                 /* Converted Data Register */
#define SDADC_7_WTHHLR       SDADC_7.WTHHLR.R              /* WDG Threshold Register */

/* SDADC */
#define SDADC_8_MCR          SDADC_8.MCR.R                 /* Module Configuration Register */
#define SDADC_8_CSR          SDADC_8.CSR.R                 /* Channel Selection Register */
#define SDADC_8_RKR          SDADC_8.RKR.R                 /* Reset Key Register */
#define SDADC_8_SFR          SDADC_8.SFR.R                 /* Status Flag Register */
#define SDADC_8_RSER         SDADC_8.RSER.R                /* Request Select and Enable Register */
#define SDADC_8_OSDR         SDADC_8.OSDR.R                /* Output Settling Delay Register */
#define SDADC_8_FCR          SDADC_8.FCR.R                 /* FIFO Control Register */
#define SDADC_8_STKR         SDADC_8.STKR.R                /* Software Trigger Key Register */
#define SDADC_8_CDR          SDADC_8.CDR.R                 /* Converted Data Register */
#define SDADC_8_WTHHLR       SDADC_8.WTHHLR.R              /* WDG Threshold Register */

/* SDADC */
#define SDADC_9_MCR          SDADC_9.MCR.R                 /* Module Configuration Register */
#define SDADC_9_CSR          SDADC_9.CSR.R                 /* Channel Selection Register */
#define SDADC_9_RKR          SDADC_9.RKR.R                 /* Reset Key Register */
#define SDADC_9_SFR          SDADC_9.SFR.R                 /* Status Flag Register */
#define SDADC_9_RSER         SDADC_9.RSER.R                /* Request Select and Enable Register */
#define SDADC_9_OSDR         SDADC_9.OSDR.R                /* Output Settling Delay Register */
#define SDADC_9_FCR          SDADC_9.FCR.R                 /* FIFO Control Register */
#define SDADC_9_STKR         SDADC_9.STKR.R                /* Software Trigger Key Register */
#define SDADC_9_CDR          SDADC_9.CDR.R                 /* Converted Data Register */
#define SDADC_9_WTHHLR       SDADC_9.WTHHLR.R              /* WDG Threshold Register */

/* SEMA42 */
#define SEMA42_GATE0         SEMA42.GATE[0].R              /* Gate Register */
#define SEMA42_GATE1         SEMA42.GATE[1].R              /* Gate Register */
#define SEMA42_GATE2         SEMA42.GATE[2].R              /* Gate Register */
#define SEMA42_GATE3         SEMA42.GATE[3].R              /* Gate Register */
#define SEMA42_GATE4         SEMA42.GATE[4].R              /* Gate Register */
#define SEMA42_GATE5         SEMA42.GATE[5].R              /* Gate Register */
#define SEMA42_GATE6         SEMA42.GATE[6].R              /* Gate Register */
#define SEMA42_GATE7         SEMA42.GATE[7].R              /* Gate Register */
#define SEMA42_GATE8         SEMA42.GATE[8].R              /* Gate Register */
#define SEMA42_GATE9         SEMA42.GATE[9].R              /* Gate Register */
#define SEMA42_GATE10        SEMA42.GATE[10].R             /* Gate Register */
#define SEMA42_GATE11        SEMA42.GATE[11].R             /* Gate Register */
#define SEMA42_GATE12        SEMA42.GATE[12].R             /* Gate Register */
#define SEMA42_GATE13        SEMA42.GATE[13].R             /* Gate Register */
#define SEMA42_GATE14        SEMA42.GATE[14].R             /* Gate Register */
#define SEMA42_GATE15        SEMA42.GATE[15].R             /* Gate Register */
#define SEMA42_RSTGT_R       SEMA42.RSTGT.R.R              /* Reset Gate Read */
#define SEMA42_RSTGT_W       SEMA42.RSTGT.W.R              /* Reset Gate Write */

/* SIPI */
#define SIPI_0_CCR0          SIPI_0.CCR0.R                 /* SIPI Channel Control Register 0 */
#define SIPI_0_CSR0          SIPI_0.CSR0.R                 /* SIPI Channel Status Register 0 */
#define SIPI_0_CIR0          SIPI_0.CIR0.R                 /* SIPI Channel Interrupt Register 0 */
#define SIPI_0_CTOR0         SIPI_0.CTOR0.R                /* SIPI Channel Timeout Register 0 */
#define SIPI_0_CCRC0         SIPI_0.CCRC0.R                /* SIPI Channel CRC Register 0 */
#define SIPI_0_CAR0          SIPI_0.CAR0.R                 /* SIPI Channel Address Register 0 */
#define SIPI_0_CDR0          SIPI_0.CDR0.R                 /* SIPI Channel Data Register 0 */
#define SIPI_0_CCR1          SIPI_0.CCR1.R                 /* SIPI Channel Control Register 1 */
#define SIPI_0_CSR1          SIPI_0.CSR1.R                 /* SIPI Channel Status Register 1 */
#define SIPI_0_CIR1          SIPI_0.CIR1.R                 /* SIPI Channel Interrupt Register 1 */
#define SIPI_0_CTOR1         SIPI_0.CTOR1.R                /* SIPI Channel Timeout Register 1 */
#define SIPI_0_CCRC1         SIPI_0.CCRC1.R                /* SIPI Channel CRC Register 1 */
#define SIPI_0_CAR1          SIPI_0.CAR1.R                 /* SIPI Channel Address Register 1 */
#define SIPI_0_CDR1          SIPI_0.CDR1.R                 /* SIPI Channel Data Register 1 */
#define SIPI_0_CCR2          SIPI_0.CCR2.R                 /* SIPI Channel Control Register 2 */
#define SIPI_0_CSR2          SIPI_0.CSR2.R                 /* SIPI Channel Status Register 2 */
#define SIPI_0_CIR2          SIPI_0.CIR2.R                 /* SIPI Channel Interrupt Register 2 */
#define SIPI_0_CTOR2         SIPI_0.CTOR2.R                /* SIPI Channel Timeout Register 2 */
#define SIPI_0_CCRC2         SIPI_0.CCRC2.R                /* SIPI Channel CRC Register 2 */
#define SIPI_0_CAR2          SIPI_0.CAR2.R                 /* SIPI Channel Address Register 2 */
#define SIPI_0_CDR2_0        SIPI_0.CDR2[0].R              /* SIPI Channel Data Register 2 */
#define SIPI_0_CDR2_1        SIPI_0.CDR2[1].R              /* SIPI Channel Data Register 2 */
#define SIPI_0_CDR2_2        SIPI_0.CDR2[2].R              /* SIPI Channel Data Register 2 */
#define SIPI_0_CDR2_3        SIPI_0.CDR2[3].R              /* SIPI Channel Data Register 2 */
#define SIPI_0_CDR2_4        SIPI_0.CDR2[4].R              /* SIPI Channel Data Register 2 */
#define SIPI_0_CDR2_5        SIPI_0.CDR2[5].R              /* SIPI Channel Data Register 2 */
#define SIPI_0_CDR2_6        SIPI_0.CDR2[6].R              /* SIPI Channel Data Register 2 */
#define SIPI_0_CDR2_7        SIPI_0.CDR2[7].R              /* SIPI Channel Data Register 2 */
#define SIPI_0_CCR3          SIPI_0.CCR3.R                 /* SIPI Channel Control Register 3 */
#define SIPI_0_CSR3          SIPI_0.CSR3.R                 /* SIPI Channel Status Register 3 */
#define SIPI_0_CIR3          SIPI_0.CIR3.R                 /* SIPI Channel Interrupt Register 3 */
#define SIPI_0_CTOR3         SIPI_0.CTOR3.R                /* SIPI Channel Timeout Register 3 */
#define SIPI_0_CCRC3         SIPI_0.CCRC3.R                /* SIPI Channel CRC Register 3 */
#define SIPI_0_CAR3          SIPI_0.CAR3.R                 /* SIPI Channel Address Register 3 */
#define SIPI_0_CDR3          SIPI_0.CDR3.R                 /* SIPI Channel Data Register 3 */
#define SIPI_0_MCR           SIPI_0.MCR.R                  /* SIPI Module Configuration Register */
#define SIPI_0_SR            SIPI_0.SR.R                   /* SIPI Status Register */
#define SIPI_0_MAXCR         SIPI_0.MAXCR.R                /* SIPI Max Count Register */
#define SIPI_0_ARR           SIPI_0.ARR.R                  /* SIPI Address Reload Register */
#define SIPI_0_ACR           SIPI_0.ACR.R                  /* SIPI Address Count Register */
#define SIPI_0_ERR           SIPI_0.ERR.R                  /* SIPI Error Register */

/* SIPI */
#define SIPI_1_MCR           SIPI_1.MCR.R                  /* SIPI Module Configuration Register */
#define SIPI_1_SR            SIPI_1.SR.R                   /* SIPI Status Register */

/* SIUL2 */
#define SIUL2_MIDR1          SIUL2.MIDR1.R                 /* MCU ID Register #1 */
#define SIUL2_MIDR2          SIUL2.MIDR2.R                 /* MCU ID Register #2 */
#define SIUL2_DISR0          SIUL2.DISR0.R                 /* DMA/Interrupt Status Flag Register0 */
#define SIUL2_DIRER0         SIUL2.DIRER0.R                /* DMA/Interrupt Request Enable Register0 */
#define SIUL2_DIRSR0         SIUL2.DIRSR0.R                /* DMA/Interrupt Request Select Register0 */
#define SIUL2_IREER0         SIUL2.IREER0.R                /* Interrupt Rising-Edge Event Enable Register0 */
#define SIUL2_IFEER0         SIUL2.IFEER0.R                /* Interrupt Falling-Edge Event Enable Register0 */
#define SIUL2_IFER0          SIUL2.IFER0.R                 /* Interrupt Filter Enable Register0 */
#define SIUL2_IFMCR0         SIUL2.IFMCR[0].R              /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR1         SIUL2.IFMCR[1].R              /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR2         SIUL2.IFMCR[2].R              /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR3         SIUL2.IFMCR[3].R              /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR4         SIUL2.IFMCR[4].R              /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR5         SIUL2.IFMCR[5].R              /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR6         SIUL2.IFMCR[6].R              /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR7         SIUL2.IFMCR[7].R              /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR8         SIUL2.IFMCR[8].R              /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR9         SIUL2.IFMCR[9].R              /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR10        SIUL2.IFMCR[10].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR11        SIUL2.IFMCR[11].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR12        SIUL2.IFMCR[12].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR13        SIUL2.IFMCR[13].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR14        SIUL2.IFMCR[14].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR15        SIUL2.IFMCR[15].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR16        SIUL2.IFMCR[16].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR17        SIUL2.IFMCR[17].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR18        SIUL2.IFMCR[18].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR19        SIUL2.IFMCR[19].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR20        SIUL2.IFMCR[20].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR21        SIUL2.IFMCR[21].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR22        SIUL2.IFMCR[22].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR23        SIUL2.IFMCR[23].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR24        SIUL2.IFMCR[24].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR25        SIUL2.IFMCR[25].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR26        SIUL2.IFMCR[26].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR27        SIUL2.IFMCR[27].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR28        SIUL2.IFMCR[28].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR29        SIUL2.IFMCR[29].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR30        SIUL2.IFMCR[30].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFMCR31        SIUL2.IFMCR[31].R             /* Interrupt Filter Maximum Counter Register */
#define SIUL2_IFCPR          SIUL2.IFCPR.R                 /* Interrupt Filter Clock Prescaler */
#define SIUL2_SCR0           SIUL2.SCR0.R                  /* SoC Configuration Register0 */
#define SIUL2_MSCR_IO_0      SIUL2.MSCR_IO[0].R            /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_1      SIUL2.MSCR_IO[1].R            /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_2      SIUL2.MSCR_IO[2].R            /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_3      SIUL2.MSCR_IO[3].R            /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_4      SIUL2.MSCR_IO[4].R            /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_5      SIUL2.MSCR_IO[5].R            /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_6      SIUL2.MSCR_IO[6].R            /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_7      SIUL2.MSCR_IO[7].R            /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_8      SIUL2.MSCR_IO[8].R            /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_9      SIUL2.MSCR_IO[9].R            /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_10     SIUL2.MSCR_IO[10].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_11     SIUL2.MSCR_IO[11].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_12     SIUL2.MSCR_IO[12].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_13     SIUL2.MSCR_IO[13].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_14     SIUL2.MSCR_IO[14].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_15     SIUL2.MSCR_IO[15].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_16     SIUL2.MSCR_IO[16].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_17     SIUL2.MSCR_IO[17].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_18     SIUL2.MSCR_IO[18].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_19     SIUL2.MSCR_IO[19].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_20     SIUL2.MSCR_IO[20].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_21     SIUL2.MSCR_IO[21].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_22     SIUL2.MSCR_IO[22].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_23     SIUL2.MSCR_IO[23].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_24     SIUL2.MSCR_IO[24].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_25     SIUL2.MSCR_IO[25].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_26     SIUL2.MSCR_IO[26].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_27     SIUL2.MSCR_IO[27].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_28     SIUL2.MSCR_IO[28].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_29     SIUL2.MSCR_IO[29].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_30     SIUL2.MSCR_IO[30].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_31     SIUL2.MSCR_IO[31].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_32     SIUL2.MSCR_IO[32].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_33     SIUL2.MSCR_IO[33].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_34     SIUL2.MSCR_IO[34].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_35     SIUL2.MSCR_IO[35].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_36     SIUL2.MSCR_IO[36].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_37     SIUL2.MSCR_IO[37].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_38     SIUL2.MSCR_IO[38].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_39     SIUL2.MSCR_IO[39].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_40     SIUL2.MSCR_IO[40].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_41     SIUL2.MSCR_IO[41].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_42     SIUL2.MSCR_IO[42].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_43     SIUL2.MSCR_IO[43].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_44     SIUL2.MSCR_IO[44].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_45     SIUL2.MSCR_IO[45].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_46     SIUL2.MSCR_IO[46].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_47     SIUL2.MSCR_IO[47].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_48     SIUL2.MSCR_IO[48].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_49     SIUL2.MSCR_IO[49].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_50     SIUL2.MSCR_IO[50].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_51     SIUL2.MSCR_IO[51].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_52     SIUL2.MSCR_IO[52].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_53     SIUL2.MSCR_IO[53].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_54     SIUL2.MSCR_IO[54].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_55     SIUL2.MSCR_IO[55].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_56     SIUL2.MSCR_IO[56].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_57     SIUL2.MSCR_IO[57].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_58     SIUL2.MSCR_IO[58].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_59     SIUL2.MSCR_IO[59].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_60     SIUL2.MSCR_IO[60].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_61     SIUL2.MSCR_IO[61].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_62     SIUL2.MSCR_IO[62].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_63     SIUL2.MSCR_IO[63].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_64     SIUL2.MSCR_IO[64].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_65     SIUL2.MSCR_IO[65].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_66     SIUL2.MSCR_IO[66].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_67     SIUL2.MSCR_IO[67].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_68     SIUL2.MSCR_IO[68].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_69     SIUL2.MSCR_IO[69].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_70     SIUL2.MSCR_IO[70].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_71     SIUL2.MSCR_IO[71].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_72     SIUL2.MSCR_IO[72].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_73     SIUL2.MSCR_IO[73].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_74     SIUL2.MSCR_IO[74].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_75     SIUL2.MSCR_IO[75].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_76     SIUL2.MSCR_IO[76].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_77     SIUL2.MSCR_IO[77].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_78     SIUL2.MSCR_IO[78].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_79     SIUL2.MSCR_IO[79].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_80     SIUL2.MSCR_IO[80].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_81     SIUL2.MSCR_IO[81].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_82     SIUL2.MSCR_IO[82].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_83     SIUL2.MSCR_IO[83].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_84     SIUL2.MSCR_IO[84].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_85     SIUL2.MSCR_IO[85].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_86     SIUL2.MSCR_IO[86].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_87     SIUL2.MSCR_IO[87].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_88     SIUL2.MSCR_IO[88].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_89     SIUL2.MSCR_IO[89].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_90     SIUL2.MSCR_IO[90].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_91     SIUL2.MSCR_IO[91].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_92     SIUL2.MSCR_IO[92].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_93     SIUL2.MSCR_IO[93].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_94     SIUL2.MSCR_IO[94].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_95     SIUL2.MSCR_IO[95].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_96     SIUL2.MSCR_IO[96].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_97     SIUL2.MSCR_IO[97].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_98     SIUL2.MSCR_IO[98].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_99     SIUL2.MSCR_IO[99].R           /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_100    SIUL2.MSCR_IO[100].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_101    SIUL2.MSCR_IO[101].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_102    SIUL2.MSCR_IO[102].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_103    SIUL2.MSCR_IO[103].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_104    SIUL2.MSCR_IO[104].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_105    SIUL2.MSCR_IO[105].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_106    SIUL2.MSCR_IO[106].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_107    SIUL2.MSCR_IO[107].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_108    SIUL2.MSCR_IO[108].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_109    SIUL2.MSCR_IO[109].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_110    SIUL2.MSCR_IO[110].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_111    SIUL2.MSCR_IO[111].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_112    SIUL2.MSCR_IO[112].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_113    SIUL2.MSCR_IO[113].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_114    SIUL2.MSCR_IO[114].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_115    SIUL2.MSCR_IO[115].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_116    SIUL2.MSCR_IO[116].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_117    SIUL2.MSCR_IO[117].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_118    SIUL2.MSCR_IO[118].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_119    SIUL2.MSCR_IO[119].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_120    SIUL2.MSCR_IO[120].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_121    SIUL2.MSCR_IO[121].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_122    SIUL2.MSCR_IO[122].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_123    SIUL2.MSCR_IO[123].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_124    SIUL2.MSCR_IO[124].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_125    SIUL2.MSCR_IO[125].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_126    SIUL2.MSCR_IO[126].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_127    SIUL2.MSCR_IO[127].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_128    SIUL2.MSCR_IO[128].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_129    SIUL2.MSCR_IO[129].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_130    SIUL2.MSCR_IO[130].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_131    SIUL2.MSCR_IO[131].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_132    SIUL2.MSCR_IO[132].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_133    SIUL2.MSCR_IO[133].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_134    SIUL2.MSCR_IO[134].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_135    SIUL2.MSCR_IO[135].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_136    SIUL2.MSCR_IO[136].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_137    SIUL2.MSCR_IO[137].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_138    SIUL2.MSCR_IO[138].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_139    SIUL2.MSCR_IO[139].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_140    SIUL2.MSCR_IO[140].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_141    SIUL2.MSCR_IO[141].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_142    SIUL2.MSCR_IO[142].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_143    SIUL2.MSCR_IO[143].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_144    SIUL2.MSCR_IO[144].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_145    SIUL2.MSCR_IO[145].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_146    SIUL2.MSCR_IO[146].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_147    SIUL2.MSCR_IO[147].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_148    SIUL2.MSCR_IO[148].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_149    SIUL2.MSCR_IO[149].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_150    SIUL2.MSCR_IO[150].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_151    SIUL2.MSCR_IO[151].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_152    SIUL2.MSCR_IO[152].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_153    SIUL2.MSCR_IO[153].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_154    SIUL2.MSCR_IO[154].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_155    SIUL2.MSCR_IO[155].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_156    SIUL2.MSCR_IO[156].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_157    SIUL2.MSCR_IO[157].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_158    SIUL2.MSCR_IO[158].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_159    SIUL2.MSCR_IO[159].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_160    SIUL2.MSCR_IO[160].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_161    SIUL2.MSCR_IO[161].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_162    SIUL2.MSCR_IO[162].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_163    SIUL2.MSCR_IO[163].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_164    SIUL2.MSCR_IO[164].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_165    SIUL2.MSCR_IO[165].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_166    SIUL2.MSCR_IO[166].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_167    SIUL2.MSCR_IO[167].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_168    SIUL2.MSCR_IO[168].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_169    SIUL2.MSCR_IO[169].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_170    SIUL2.MSCR_IO[170].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_171    SIUL2.MSCR_IO[171].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_172    SIUL2.MSCR_IO[172].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_173    SIUL2.MSCR_IO[173].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_174    SIUL2.MSCR_IO[174].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_175    SIUL2.MSCR_IO[175].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_176    SIUL2.MSCR_IO[176].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_177    SIUL2.MSCR_IO[177].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_178    SIUL2.MSCR_IO[178].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_179    SIUL2.MSCR_IO[179].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_180    SIUL2.MSCR_IO[180].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_181    SIUL2.MSCR_IO[181].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_182    SIUL2.MSCR_IO[182].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_183    SIUL2.MSCR_IO[183].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_184    SIUL2.MSCR_IO[184].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_185    SIUL2.MSCR_IO[185].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_186    SIUL2.MSCR_IO[186].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_187    SIUL2.MSCR_IO[187].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_188    SIUL2.MSCR_IO[188].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_189    SIUL2.MSCR_IO[189].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_190    SIUL2.MSCR_IO[190].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_191    SIUL2.MSCR_IO[191].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_192    SIUL2.MSCR_IO[192].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_193    SIUL2.MSCR_IO[193].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_194    SIUL2.MSCR_IO[194].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_195    SIUL2.MSCR_IO[195].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_196    SIUL2.MSCR_IO[196].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_197    SIUL2.MSCR_IO[197].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_198    SIUL2.MSCR_IO[198].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_199    SIUL2.MSCR_IO[199].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_200    SIUL2.MSCR_IO[200].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_201    SIUL2.MSCR_IO[201].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_202    SIUL2.MSCR_IO[202].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_203    SIUL2.MSCR_IO[203].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_204    SIUL2.MSCR_IO[204].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_205    SIUL2.MSCR_IO[205].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_206    SIUL2.MSCR_IO[206].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_207    SIUL2.MSCR_IO[207].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_208    SIUL2.MSCR_IO[208].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_209    SIUL2.MSCR_IO[209].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_210    SIUL2.MSCR_IO[210].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_211    SIUL2.MSCR_IO[211].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_212    SIUL2.MSCR_IO[212].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_213    SIUL2.MSCR_IO[213].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_214    SIUL2.MSCR_IO[214].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_215    SIUL2.MSCR_IO[215].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_216    SIUL2.MSCR_IO[216].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_217    SIUL2.MSCR_IO[217].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_218    SIUL2.MSCR_IO[218].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_219    SIUL2.MSCR_IO[219].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_220    SIUL2.MSCR_IO[220].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_221    SIUL2.MSCR_IO[221].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_222    SIUL2.MSCR_IO[222].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_223    SIUL2.MSCR_IO[223].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_224    SIUL2.MSCR_IO[224].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_225    SIUL2.MSCR_IO[225].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_226    SIUL2.MSCR_IO[226].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_227    SIUL2.MSCR_IO[227].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_228    SIUL2.MSCR_IO[228].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_229    SIUL2.MSCR_IO[229].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_230    SIUL2.MSCR_IO[230].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_231    SIUL2.MSCR_IO[231].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_232    SIUL2.MSCR_IO[232].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_233    SIUL2.MSCR_IO[233].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_234    SIUL2.MSCR_IO[234].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_235    SIUL2.MSCR_IO[235].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_236    SIUL2.MSCR_IO[236].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_237    SIUL2.MSCR_IO[237].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_238    SIUL2.MSCR_IO[238].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_239    SIUL2.MSCR_IO[239].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_240    SIUL2.MSCR_IO[240].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_241    SIUL2.MSCR_IO[241].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_242    SIUL2.MSCR_IO[242].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_243    SIUL2.MSCR_IO[243].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_244    SIUL2.MSCR_IO[244].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_245    SIUL2.MSCR_IO[245].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_246    SIUL2.MSCR_IO[246].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_247    SIUL2.MSCR_IO[247].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_248    SIUL2.MSCR_IO[248].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_249    SIUL2.MSCR_IO[249].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_250    SIUL2.MSCR_IO[250].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_251    SIUL2.MSCR_IO[251].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_252    SIUL2.MSCR_IO[252].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_253    SIUL2.MSCR_IO[253].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_254    SIUL2.MSCR_IO[254].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_255    SIUL2.MSCR_IO[255].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_256    SIUL2.MSCR_IO[256].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_257    SIUL2.MSCR_IO[257].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_258    SIUL2.MSCR_IO[258].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_259    SIUL2.MSCR_IO[259].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_260    SIUL2.MSCR_IO[260].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_261    SIUL2.MSCR_IO[261].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_262    SIUL2.MSCR_IO[262].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_263    SIUL2.MSCR_IO[263].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_264    SIUL2.MSCR_IO[264].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_265    SIUL2.MSCR_IO[265].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_266    SIUL2.MSCR_IO[266].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_267    SIUL2.MSCR_IO[267].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_268    SIUL2.MSCR_IO[268].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_269    SIUL2.MSCR_IO[269].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_270    SIUL2.MSCR_IO[270].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_271    SIUL2.MSCR_IO[271].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_272    SIUL2.MSCR_IO[272].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_273    SIUL2.MSCR_IO[273].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_274    SIUL2.MSCR_IO[274].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_275    SIUL2.MSCR_IO[275].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_276    SIUL2.MSCR_IO[276].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_277    SIUL2.MSCR_IO[277].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_278    SIUL2.MSCR_IO[278].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_279    SIUL2.MSCR_IO[279].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_280    SIUL2.MSCR_IO[280].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_281    SIUL2.MSCR_IO[281].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_282    SIUL2.MSCR_IO[282].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_283    SIUL2.MSCR_IO[283].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_284    SIUL2.MSCR_IO[284].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_285    SIUL2.MSCR_IO[285].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_286    SIUL2.MSCR_IO[286].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_287    SIUL2.MSCR_IO[287].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_288    SIUL2.MSCR_IO[288].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_289    SIUL2.MSCR_IO[289].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_290    SIUL2.MSCR_IO[290].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_291    SIUL2.MSCR_IO[291].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_292    SIUL2.MSCR_IO[292].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_293    SIUL2.MSCR_IO[293].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_294    SIUL2.MSCR_IO[294].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_295    SIUL2.MSCR_IO[295].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_296    SIUL2.MSCR_IO[296].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_297    SIUL2.MSCR_IO[297].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_298    SIUL2.MSCR_IO[298].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_299    SIUL2.MSCR_IO[299].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_300    SIUL2.MSCR_IO[300].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_301    SIUL2.MSCR_IO[301].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_302    SIUL2.MSCR_IO[302].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_303    SIUL2.MSCR_IO[303].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_304    SIUL2.MSCR_IO[304].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_305    SIUL2.MSCR_IO[305].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_306    SIUL2.MSCR_IO[306].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_307    SIUL2.MSCR_IO[307].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_308    SIUL2.MSCR_IO[308].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_309    SIUL2.MSCR_IO[309].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_310    SIUL2.MSCR_IO[310].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_311    SIUL2.MSCR_IO[311].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_312    SIUL2.MSCR_IO[312].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_313    SIUL2.MSCR_IO[313].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_314    SIUL2.MSCR_IO[314].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_315    SIUL2.MSCR_IO[315].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_316    SIUL2.MSCR_IO[316].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_317    SIUL2.MSCR_IO[317].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_318    SIUL2.MSCR_IO[318].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_319    SIUL2.MSCR_IO[319].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_320    SIUL2.MSCR_IO[320].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_321    SIUL2.MSCR_IO[321].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_322    SIUL2.MSCR_IO[322].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_323    SIUL2.MSCR_IO[323].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_324    SIUL2.MSCR_IO[324].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_325    SIUL2.MSCR_IO[325].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_326    SIUL2.MSCR_IO[326].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_327    SIUL2.MSCR_IO[327].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_328    SIUL2.MSCR_IO[328].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_329    SIUL2.MSCR_IO[329].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_330    SIUL2.MSCR_IO[330].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_331    SIUL2.MSCR_IO[331].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_332    SIUL2.MSCR_IO[332].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_333    SIUL2.MSCR_IO[333].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_334    SIUL2.MSCR_IO[334].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_335    SIUL2.MSCR_IO[335].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_336    SIUL2.MSCR_IO[336].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_337    SIUL2.MSCR_IO[337].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_338    SIUL2.MSCR_IO[338].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_339    SIUL2.MSCR_IO[339].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_340    SIUL2.MSCR_IO[340].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_341    SIUL2.MSCR_IO[341].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_342    SIUL2.MSCR_IO[342].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_343    SIUL2.MSCR_IO[343].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_344    SIUL2.MSCR_IO[344].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_345    SIUL2.MSCR_IO[345].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_346    SIUL2.MSCR_IO[346].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_347    SIUL2.MSCR_IO[347].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_348    SIUL2.MSCR_IO[348].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_349    SIUL2.MSCR_IO[349].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_350    SIUL2.MSCR_IO[350].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_351    SIUL2.MSCR_IO[351].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_352    SIUL2.MSCR_IO[352].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_353    SIUL2.MSCR_IO[353].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_354    SIUL2.MSCR_IO[354].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_355    SIUL2.MSCR_IO[355].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_356    SIUL2.MSCR_IO[356].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_357    SIUL2.MSCR_IO[357].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_358    SIUL2.MSCR_IO[358].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_359    SIUL2.MSCR_IO[359].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_360    SIUL2.MSCR_IO[360].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_361    SIUL2.MSCR_IO[361].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_362    SIUL2.MSCR_IO[362].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_363    SIUL2.MSCR_IO[363].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_364    SIUL2.MSCR_IO[364].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_365    SIUL2.MSCR_IO[365].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_366    SIUL2.MSCR_IO[366].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_367    SIUL2.MSCR_IO[367].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_368    SIUL2.MSCR_IO[368].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_369    SIUL2.MSCR_IO[369].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_370    SIUL2.MSCR_IO[370].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_371    SIUL2.MSCR_IO[371].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_372    SIUL2.MSCR_IO[372].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_373    SIUL2.MSCR_IO[373].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_374    SIUL2.MSCR_IO[374].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_375    SIUL2.MSCR_IO[375].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_376    SIUL2.MSCR_IO[376].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_377    SIUL2.MSCR_IO[377].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_378    SIUL2.MSCR_IO[378].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_379    SIUL2.MSCR_IO[379].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_380    SIUL2.MSCR_IO[380].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_381    SIUL2.MSCR_IO[381].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_382    SIUL2.MSCR_IO[382].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_383    SIUL2.MSCR_IO[383].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_384    SIUL2.MSCR_IO[384].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_385    SIUL2.MSCR_IO[385].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_386    SIUL2.MSCR_IO[386].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_387    SIUL2.MSCR_IO[387].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_388    SIUL2.MSCR_IO[388].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_389    SIUL2.MSCR_IO[389].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_390    SIUL2.MSCR_IO[390].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_391    SIUL2.MSCR_IO[391].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_392    SIUL2.MSCR_IO[392].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_393    SIUL2.MSCR_IO[393].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_394    SIUL2.MSCR_IO[394].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_395    SIUL2.MSCR_IO[395].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_396    SIUL2.MSCR_IO[396].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_397    SIUL2.MSCR_IO[397].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_398    SIUL2.MSCR_IO[398].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_399    SIUL2.MSCR_IO[399].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_400    SIUL2.MSCR_IO[400].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_401    SIUL2.MSCR_IO[401].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_402    SIUL2.MSCR_IO[402].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_403    SIUL2.MSCR_IO[403].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_404    SIUL2.MSCR_IO[404].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_405    SIUL2.MSCR_IO[405].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_406    SIUL2.MSCR_IO[406].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_407    SIUL2.MSCR_IO[407].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_408    SIUL2.MSCR_IO[408].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_409    SIUL2.MSCR_IO[409].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_410    SIUL2.MSCR_IO[410].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_411    SIUL2.MSCR_IO[411].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_412    SIUL2.MSCR_IO[412].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_413    SIUL2.MSCR_IO[413].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_414    SIUL2.MSCR_IO[414].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_415    SIUL2.MSCR_IO[415].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_416    SIUL2.MSCR_IO[416].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_417    SIUL2.MSCR_IO[417].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_418    SIUL2.MSCR_IO[418].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_419    SIUL2.MSCR_IO[419].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_420    SIUL2.MSCR_IO[420].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_421    SIUL2.MSCR_IO[421].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_422    SIUL2.MSCR_IO[422].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_423    SIUL2.MSCR_IO[423].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_424    SIUL2.MSCR_IO[424].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_425    SIUL2.MSCR_IO[425].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_426    SIUL2.MSCR_IO[426].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_427    SIUL2.MSCR_IO[427].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_428    SIUL2.MSCR_IO[428].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_429    SIUL2.MSCR_IO[429].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_430    SIUL2.MSCR_IO[430].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_431    SIUL2.MSCR_IO[431].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_432    SIUL2.MSCR_IO[432].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_433    SIUL2.MSCR_IO[433].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_434    SIUL2.MSCR_IO[434].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_435    SIUL2.MSCR_IO[435].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_436    SIUL2.MSCR_IO[436].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_437    SIUL2.MSCR_IO[437].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_438    SIUL2.MSCR_IO[438].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_439    SIUL2.MSCR_IO[439].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_440    SIUL2.MSCR_IO[440].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_441    SIUL2.MSCR_IO[441].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_442    SIUL2.MSCR_IO[442].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_443    SIUL2.MSCR_IO[443].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_444    SIUL2.MSCR_IO[444].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_445    SIUL2.MSCR_IO[445].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_446    SIUL2.MSCR_IO[446].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_447    SIUL2.MSCR_IO[447].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_448    SIUL2.MSCR_IO[448].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_449    SIUL2.MSCR_IO[449].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_450    SIUL2.MSCR_IO[450].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_451    SIUL2.MSCR_IO[451].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_452    SIUL2.MSCR_IO[452].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_453    SIUL2.MSCR_IO[453].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_454    SIUL2.MSCR_IO[454].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_455    SIUL2.MSCR_IO[455].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_456    SIUL2.MSCR_IO[456].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_457    SIUL2.MSCR_IO[457].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_458    SIUL2.MSCR_IO[458].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_459    SIUL2.MSCR_IO[459].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_460    SIUL2.MSCR_IO[460].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_461    SIUL2.MSCR_IO[461].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_462    SIUL2.MSCR_IO[462].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_463    SIUL2.MSCR_IO[463].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_464    SIUL2.MSCR_IO[464].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_465    SIUL2.MSCR_IO[465].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_466    SIUL2.MSCR_IO[466].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_467    SIUL2.MSCR_IO[467].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_468    SIUL2.MSCR_IO[468].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_469    SIUL2.MSCR_IO[469].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_470    SIUL2.MSCR_IO[470].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_471    SIUL2.MSCR_IO[471].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_472    SIUL2.MSCR_IO[472].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_473    SIUL2.MSCR_IO[473].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_474    SIUL2.MSCR_IO[474].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_475    SIUL2.MSCR_IO[475].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_476    SIUL2.MSCR_IO[476].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_477    SIUL2.MSCR_IO[477].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_478    SIUL2.MSCR_IO[478].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_479    SIUL2.MSCR_IO[479].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_480    SIUL2.MSCR_IO[480].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_481    SIUL2.MSCR_IO[481].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_482    SIUL2.MSCR_IO[482].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_483    SIUL2.MSCR_IO[483].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_484    SIUL2.MSCR_IO[484].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_485    SIUL2.MSCR_IO[485].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_486    SIUL2.MSCR_IO[486].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_487    SIUL2.MSCR_IO[487].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_488    SIUL2.MSCR_IO[488].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_489    SIUL2.MSCR_IO[489].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_490    SIUL2.MSCR_IO[490].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_491    SIUL2.MSCR_IO[491].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_492    SIUL2.MSCR_IO[492].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_493    SIUL2.MSCR_IO[493].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_494    SIUL2.MSCR_IO[494].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_495    SIUL2.MSCR_IO[495].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_496    SIUL2.MSCR_IO[496].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_497    SIUL2.MSCR_IO[497].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_498    SIUL2.MSCR_IO[498].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_499    SIUL2.MSCR_IO[499].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_500    SIUL2.MSCR_IO[500].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_501    SIUL2.MSCR_IO[501].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_502    SIUL2.MSCR_IO[502].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_503    SIUL2.MSCR_IO[503].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_504    SIUL2.MSCR_IO[504].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_505    SIUL2.MSCR_IO[505].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_506    SIUL2.MSCR_IO[506].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_507    SIUL2.MSCR_IO[507].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_508    SIUL2.MSCR_IO[508].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_509    SIUL2.MSCR_IO[509].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_510    SIUL2.MSCR_IO[510].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_IO_511    SIUL2.MSCR_IO[511].R          /* I/O Pin Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_MUX_512   SIUL2.MSCR_MUX[0].R           /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_513   SIUL2.MSCR_MUX[1].R           /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_514   SIUL2.MSCR_MUX[2].R           /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_515   SIUL2.MSCR_MUX[3].R           /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_516   SIUL2.MSCR_MUX[4].R           /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_517   SIUL2.MSCR_MUX[5].R           /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_518   SIUL2.MSCR_MUX[6].R           /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_519   SIUL2.MSCR_MUX[7].R           /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_520   SIUL2.MSCR_MUX[8].R           /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_521   SIUL2.MSCR_MUX[9].R           /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_522   SIUL2.MSCR_MUX[10].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_523   SIUL2.MSCR_MUX[11].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_524   SIUL2.MSCR_MUX[12].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_525   SIUL2.MSCR_MUX[13].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_526   SIUL2.MSCR_MUX[14].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_527   SIUL2.MSCR_MUX[15].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_528   SIUL2.MSCR_MUX[16].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_529   SIUL2.MSCR_MUX[17].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_530   SIUL2.MSCR_MUX[18].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_531   SIUL2.MSCR_MUX[19].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_532   SIUL2.MSCR_MUX[20].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_533   SIUL2.MSCR_MUX[21].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_534   SIUL2.MSCR_MUX[22].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_535   SIUL2.MSCR_MUX[23].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_536   SIUL2.MSCR_MUX[24].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_537   SIUL2.MSCR_MUX[25].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_538   SIUL2.MSCR_MUX[26].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_539   SIUL2.MSCR_MUX[27].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_540   SIUL2.MSCR_MUX[28].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_541   SIUL2.MSCR_MUX[29].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_542   SIUL2.MSCR_MUX[30].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_543   SIUL2.MSCR_MUX[31].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_544   SIUL2.MSCR_MUX[32].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_545   SIUL2.MSCR_MUX[33].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_546   SIUL2.MSCR_MUX[34].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_547   SIUL2.MSCR_MUX[35].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_548   SIUL2.MSCR_MUX[36].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_549   SIUL2.MSCR_MUX[37].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_550   SIUL2.MSCR_MUX[38].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_551   SIUL2.MSCR_MUX[39].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_552   SIUL2.MSCR_MUX[40].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_553   SIUL2.MSCR_MUX[41].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_554   SIUL2.MSCR_MUX[42].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_555   SIUL2.MSCR_MUX[43].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_556   SIUL2.MSCR_MUX[44].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_557   SIUL2.MSCR_MUX[45].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_558   SIUL2.MSCR_MUX[46].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_559   SIUL2.MSCR_MUX[47].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_560   SIUL2.MSCR_MUX[48].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_561   SIUL2.MSCR_MUX[49].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_562   SIUL2.MSCR_MUX[50].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_563   SIUL2.MSCR_MUX[51].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_564   SIUL2.MSCR_MUX[52].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_565   SIUL2.MSCR_MUX[53].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_566   SIUL2.MSCR_MUX[54].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_567   SIUL2.MSCR_MUX[55].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_568   SIUL2.MSCR_MUX[56].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_569   SIUL2.MSCR_MUX[57].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_570   SIUL2.MSCR_MUX[58].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_571   SIUL2.MSCR_MUX[59].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_572   SIUL2.MSCR_MUX[60].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_573   SIUL2.MSCR_MUX[61].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_574   SIUL2.MSCR_MUX[62].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_575   SIUL2.MSCR_MUX[63].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_576   SIUL2.MSCR_MUX[64].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_577   SIUL2.MSCR_MUX[65].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_578   SIUL2.MSCR_MUX[66].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_579   SIUL2.MSCR_MUX[67].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_580   SIUL2.MSCR_MUX[68].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_581   SIUL2.MSCR_MUX[69].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_582   SIUL2.MSCR_MUX[70].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_583   SIUL2.MSCR_MUX[71].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_584   SIUL2.MSCR_MUX[72].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_585   SIUL2.MSCR_MUX[73].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_586   SIUL2.MSCR_MUX[74].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_587   SIUL2.MSCR_MUX[75].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_588   SIUL2.MSCR_MUX[76].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_589   SIUL2.MSCR_MUX[77].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_590   SIUL2.MSCR_MUX[78].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_591   SIUL2.MSCR_MUX[79].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_592   SIUL2.MSCR_MUX[80].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_593   SIUL2.MSCR_MUX[81].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_594   SIUL2.MSCR_MUX[82].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_595   SIUL2.MSCR_MUX[83].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_596   SIUL2.MSCR_MUX[84].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_597   SIUL2.MSCR_MUX[85].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_598   SIUL2.MSCR_MUX[86].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_599   SIUL2.MSCR_MUX[87].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_600   SIUL2.MSCR_MUX[88].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_601   SIUL2.MSCR_MUX[89].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_602   SIUL2.MSCR_MUX[90].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_603   SIUL2.MSCR_MUX[91].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_604   SIUL2.MSCR_MUX[92].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_605   SIUL2.MSCR_MUX[93].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_606   SIUL2.MSCR_MUX[94].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_607   SIUL2.MSCR_MUX[95].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_608   SIUL2.MSCR_MUX[96].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_609   SIUL2.MSCR_MUX[97].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_610   SIUL2.MSCR_MUX[98].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_611   SIUL2.MSCR_MUX[99].R          /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_612   SIUL2.MSCR_MUX[100].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_613   SIUL2.MSCR_MUX[101].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_614   SIUL2.MSCR_MUX[102].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_615   SIUL2.MSCR_MUX[103].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_616   SIUL2.MSCR_MUX[104].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_617   SIUL2.MSCR_MUX[105].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_618   SIUL2.MSCR_MUX[106].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_619   SIUL2.MSCR_MUX[107].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_620   SIUL2.MSCR_MUX[108].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_621   SIUL2.MSCR_MUX[109].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_622   SIUL2.MSCR_MUX[110].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_623   SIUL2.MSCR_MUX[111].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_624   SIUL2.MSCR_MUX[112].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_625   SIUL2.MSCR_MUX[113].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_626   SIUL2.MSCR_MUX[114].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_627   SIUL2.MSCR_MUX[115].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_628   SIUL2.MSCR_MUX[116].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_629   SIUL2.MSCR_MUX[117].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_630   SIUL2.MSCR_MUX[118].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_631   SIUL2.MSCR_MUX[119].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_632   SIUL2.MSCR_MUX[120].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_633   SIUL2.MSCR_MUX[121].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_634   SIUL2.MSCR_MUX[122].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_635   SIUL2.MSCR_MUX[123].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_636   SIUL2.MSCR_MUX[124].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_637   SIUL2.MSCR_MUX[125].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_638   SIUL2.MSCR_MUX[126].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_639   SIUL2.MSCR_MUX[127].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_640   SIUL2.MSCR_MUX[128].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_641   SIUL2.MSCR_MUX[129].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_642   SIUL2.MSCR_MUX[130].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_643   SIUL2.MSCR_MUX[131].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_644   SIUL2.MSCR_MUX[132].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_645   SIUL2.MSCR_MUX[133].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_646   SIUL2.MSCR_MUX[134].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_647   SIUL2.MSCR_MUX[135].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_648   SIUL2.MSCR_MUX[136].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_649   SIUL2.MSCR_MUX[137].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_650   SIUL2.MSCR_MUX[138].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_651   SIUL2.MSCR_MUX[139].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_652   SIUL2.MSCR_MUX[140].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_653   SIUL2.MSCR_MUX[141].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_654   SIUL2.MSCR_MUX[142].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_655   SIUL2.MSCR_MUX[143].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_656   SIUL2.MSCR_MUX[144].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_657   SIUL2.MSCR_MUX[145].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_658   SIUL2.MSCR_MUX[146].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_659   SIUL2.MSCR_MUX[147].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_660   SIUL2.MSCR_MUX[148].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_661   SIUL2.MSCR_MUX[149].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_662   SIUL2.MSCR_MUX[150].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_663   SIUL2.MSCR_MUX[151].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_664   SIUL2.MSCR_MUX[152].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_665   SIUL2.MSCR_MUX[153].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_666   SIUL2.MSCR_MUX[154].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_667   SIUL2.MSCR_MUX[155].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_668   SIUL2.MSCR_MUX[156].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_669   SIUL2.MSCR_MUX[157].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_670   SIUL2.MSCR_MUX[158].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_671   SIUL2.MSCR_MUX[159].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_672   SIUL2.MSCR_MUX[160].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_673   SIUL2.MSCR_MUX[161].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_674   SIUL2.MSCR_MUX[162].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_675   SIUL2.MSCR_MUX[163].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_676   SIUL2.MSCR_MUX[164].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_677   SIUL2.MSCR_MUX[165].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_678   SIUL2.MSCR_MUX[166].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_679   SIUL2.MSCR_MUX[167].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_680   SIUL2.MSCR_MUX[168].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_681   SIUL2.MSCR_MUX[169].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_682   SIUL2.MSCR_MUX[170].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_683   SIUL2.MSCR_MUX[171].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_684   SIUL2.MSCR_MUX[172].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_685   SIUL2.MSCR_MUX[173].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_686   SIUL2.MSCR_MUX[174].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_687   SIUL2.MSCR_MUX[175].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_688   SIUL2.MSCR_MUX[176].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_689   SIUL2.MSCR_MUX[177].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_690   SIUL2.MSCR_MUX[178].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_691   SIUL2.MSCR_MUX[179].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_692   SIUL2.MSCR_MUX[180].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_693   SIUL2.MSCR_MUX[181].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_694   SIUL2.MSCR_MUX[182].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_695   SIUL2.MSCR_MUX[183].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_696   SIUL2.MSCR_MUX[184].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_697   SIUL2.MSCR_MUX[185].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_698   SIUL2.MSCR_MUX[186].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_699   SIUL2.MSCR_MUX[187].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_700   SIUL2.MSCR_MUX[188].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_701   SIUL2.MSCR_MUX[189].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_702   SIUL2.MSCR_MUX[190].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_703   SIUL2.MSCR_MUX[191].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_704   SIUL2.MSCR_MUX[192].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_705   SIUL2.MSCR_MUX[193].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_706   SIUL2.MSCR_MUX[194].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_707   SIUL2.MSCR_MUX[195].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_708   SIUL2.MSCR_MUX[196].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_709   SIUL2.MSCR_MUX[197].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_710   SIUL2.MSCR_MUX[198].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_711   SIUL2.MSCR_MUX[199].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_712   SIUL2.MSCR_MUX[200].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_713   SIUL2.MSCR_MUX[201].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_714   SIUL2.MSCR_MUX[202].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_715   SIUL2.MSCR_MUX[203].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_716   SIUL2.MSCR_MUX[204].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_717   SIUL2.MSCR_MUX[205].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_718   SIUL2.MSCR_MUX[206].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_719   SIUL2.MSCR_MUX[207].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_720   SIUL2.MSCR_MUX[208].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_721   SIUL2.MSCR_MUX[209].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_722   SIUL2.MSCR_MUX[210].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_723   SIUL2.MSCR_MUX[211].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_724   SIUL2.MSCR_MUX[212].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_725   SIUL2.MSCR_MUX[213].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_726   SIUL2.MSCR_MUX[214].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_727   SIUL2.MSCR_MUX[215].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_728   SIUL2.MSCR_MUX[216].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_729   SIUL2.MSCR_MUX[217].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_730   SIUL2.MSCR_MUX[218].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_731   SIUL2.MSCR_MUX[219].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_732   SIUL2.MSCR_MUX[220].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_733   SIUL2.MSCR_MUX[221].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_734   SIUL2.MSCR_MUX[222].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_735   SIUL2.MSCR_MUX[223].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_736   SIUL2.MSCR_MUX[224].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_737   SIUL2.MSCR_MUX[225].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_738   SIUL2.MSCR_MUX[226].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_739   SIUL2.MSCR_MUX[227].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_740   SIUL2.MSCR_MUX[228].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_741   SIUL2.MSCR_MUX[229].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_742   SIUL2.MSCR_MUX[230].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_743   SIUL2.MSCR_MUX[231].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_744   SIUL2.MSCR_MUX[232].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_745   SIUL2.MSCR_MUX[233].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_746   SIUL2.MSCR_MUX[234].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_747   SIUL2.MSCR_MUX[235].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_748   SIUL2.MSCR_MUX[236].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_749   SIUL2.MSCR_MUX[237].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_750   SIUL2.MSCR_MUX[238].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_751   SIUL2.MSCR_MUX[239].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_752   SIUL2.MSCR_MUX[240].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_753   SIUL2.MSCR_MUX[241].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_754   SIUL2.MSCR_MUX[242].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_755   SIUL2.MSCR_MUX[243].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_756   SIUL2.MSCR_MUX[244].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_757   SIUL2.MSCR_MUX[245].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_758   SIUL2.MSCR_MUX[246].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_759   SIUL2.MSCR_MUX[247].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_760   SIUL2.MSCR_MUX[248].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_761   SIUL2.MSCR_MUX[249].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_762   SIUL2.MSCR_MUX[250].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_763   SIUL2.MSCR_MUX[251].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_764   SIUL2.MSCR_MUX[252].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_765   SIUL2.MSCR_MUX[253].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_766   SIUL2.MSCR_MUX[254].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_767   SIUL2.MSCR_MUX[255].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_768   SIUL2.MSCR_MUX[256].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_769   SIUL2.MSCR_MUX[257].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_770   SIUL2.MSCR_MUX[258].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_771   SIUL2.MSCR_MUX[259].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_772   SIUL2.MSCR_MUX[260].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_773   SIUL2.MSCR_MUX[261].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_774   SIUL2.MSCR_MUX[262].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_775   SIUL2.MSCR_MUX[263].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_776   SIUL2.MSCR_MUX[264].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_777   SIUL2.MSCR_MUX[265].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_778   SIUL2.MSCR_MUX[266].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_779   SIUL2.MSCR_MUX[267].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_780   SIUL2.MSCR_MUX[268].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_781   SIUL2.MSCR_MUX[269].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_782   SIUL2.MSCR_MUX[270].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_783   SIUL2.MSCR_MUX[271].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_784   SIUL2.MSCR_MUX[272].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_785   SIUL2.MSCR_MUX[273].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_786   SIUL2.MSCR_MUX[274].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_787   SIUL2.MSCR_MUX[275].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_788   SIUL2.MSCR_MUX[276].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_789   SIUL2.MSCR_MUX[277].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_790   SIUL2.MSCR_MUX[278].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_791   SIUL2.MSCR_MUX[279].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_792   SIUL2.MSCR_MUX[280].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_793   SIUL2.MSCR_MUX[281].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_794   SIUL2.MSCR_MUX[282].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_795   SIUL2.MSCR_MUX[283].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_796   SIUL2.MSCR_MUX[284].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_797   SIUL2.MSCR_MUX[285].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_798   SIUL2.MSCR_MUX[286].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_799   SIUL2.MSCR_MUX[287].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_800   SIUL2.MSCR_MUX[288].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_801   SIUL2.MSCR_MUX[289].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_802   SIUL2.MSCR_MUX[290].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_803   SIUL2.MSCR_MUX[291].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_804   SIUL2.MSCR_MUX[292].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_805   SIUL2.MSCR_MUX[293].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_806   SIUL2.MSCR_MUX[294].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_807   SIUL2.MSCR_MUX[295].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_808   SIUL2.MSCR_MUX[296].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_809   SIUL2.MSCR_MUX[297].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_810   SIUL2.MSCR_MUX[298].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_811   SIUL2.MSCR_MUX[299].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_812   SIUL2.MSCR_MUX[300].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_813   SIUL2.MSCR_MUX[301].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_814   SIUL2.MSCR_MUX[302].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_815   SIUL2.MSCR_MUX[303].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_816   SIUL2.MSCR_MUX[304].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_817   SIUL2.MSCR_MUX[305].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_818   SIUL2.MSCR_MUX[306].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_819   SIUL2.MSCR_MUX[307].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_820   SIUL2.MSCR_MUX[308].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_821   SIUL2.MSCR_MUX[309].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_822   SIUL2.MSCR_MUX[310].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_823   SIUL2.MSCR_MUX[311].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_824   SIUL2.MSCR_MUX[312].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_825   SIUL2.MSCR_MUX[313].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_826   SIUL2.MSCR_MUX[314].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_827   SIUL2.MSCR_MUX[315].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_828   SIUL2.MSCR_MUX[316].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_829   SIUL2.MSCR_MUX[317].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_830   SIUL2.MSCR_MUX[318].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_831   SIUL2.MSCR_MUX[319].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_832   SIUL2.MSCR_MUX[320].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_833   SIUL2.MSCR_MUX[321].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_834   SIUL2.MSCR_MUX[322].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_835   SIUL2.MSCR_MUX[323].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_836   SIUL2.MSCR_MUX[324].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_837   SIUL2.MSCR_MUX[325].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_838   SIUL2.MSCR_MUX[326].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_839   SIUL2.MSCR_MUX[327].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_840   SIUL2.MSCR_MUX[328].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_841   SIUL2.MSCR_MUX[329].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_842   SIUL2.MSCR_MUX[330].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_843   SIUL2.MSCR_MUX[331].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_844   SIUL2.MSCR_MUX[332].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_845   SIUL2.MSCR_MUX[333].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_846   SIUL2.MSCR_MUX[334].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_847   SIUL2.MSCR_MUX[335].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_848   SIUL2.MSCR_MUX[336].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_849   SIUL2.MSCR_MUX[337].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_850   SIUL2.MSCR_MUX[338].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_851   SIUL2.MSCR_MUX[339].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_852   SIUL2.MSCR_MUX[340].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_853   SIUL2.MSCR_MUX[341].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_854   SIUL2.MSCR_MUX[342].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_855   SIUL2.MSCR_MUX[343].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_856   SIUL2.MSCR_MUX[344].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_857   SIUL2.MSCR_MUX[345].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_858   SIUL2.MSCR_MUX[346].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_859   SIUL2.MSCR_MUX[347].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_860   SIUL2.MSCR_MUX[348].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_861   SIUL2.MSCR_MUX[349].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_862   SIUL2.MSCR_MUX[350].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_863   SIUL2.MSCR_MUX[351].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_864   SIUL2.MSCR_MUX[352].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_865   SIUL2.MSCR_MUX[353].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_866   SIUL2.MSCR_MUX[354].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_867   SIUL2.MSCR_MUX[355].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_868   SIUL2.MSCR_MUX[356].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_869   SIUL2.MSCR_MUX[357].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_870   SIUL2.MSCR_MUX[358].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_871   SIUL2.MSCR_MUX[359].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_872   SIUL2.MSCR_MUX[360].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_873   SIUL2.MSCR_MUX[361].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_874   SIUL2.MSCR_MUX[362].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_875   SIUL2.MSCR_MUX[363].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_876   SIUL2.MSCR_MUX[364].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_877   SIUL2.MSCR_MUX[365].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_878   SIUL2.MSCR_MUX[366].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_879   SIUL2.MSCR_MUX[367].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_880   SIUL2.MSCR_MUX[368].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_881   SIUL2.MSCR_MUX[369].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_882   SIUL2.MSCR_MUX[370].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_883   SIUL2.MSCR_MUX[371].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_884   SIUL2.MSCR_MUX[372].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_885   SIUL2.MSCR_MUX[373].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_886   SIUL2.MSCR_MUX[374].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_887   SIUL2.MSCR_MUX[375].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_888   SIUL2.MSCR_MUX[376].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_889   SIUL2.MSCR_MUX[377].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_890   SIUL2.MSCR_MUX[378].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_891   SIUL2.MSCR_MUX[379].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_892   SIUL2.MSCR_MUX[380].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_893   SIUL2.MSCR_MUX[381].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_894   SIUL2.MSCR_MUX[382].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_895   SIUL2.MSCR_MUX[383].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_896   SIUL2.MSCR_MUX[384].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_897   SIUL2.MSCR_MUX[385].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_898   SIUL2.MSCR_MUX[386].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_899   SIUL2.MSCR_MUX[387].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_900   SIUL2.MSCR_MUX[388].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_901   SIUL2.MSCR_MUX[389].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_902   SIUL2.MSCR_MUX[390].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_903   SIUL2.MSCR_MUX[391].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_904   SIUL2.MSCR_MUX[392].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_905   SIUL2.MSCR_MUX[393].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_906   SIUL2.MSCR_MUX[394].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_907   SIUL2.MSCR_MUX[395].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_908   SIUL2.MSCR_MUX[396].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_909   SIUL2.MSCR_MUX[397].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_910   SIUL2.MSCR_MUX[398].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_911   SIUL2.MSCR_MUX[399].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_912   SIUL2.MSCR_MUX[400].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_913   SIUL2.MSCR_MUX[401].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_914   SIUL2.MSCR_MUX[402].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_915   SIUL2.MSCR_MUX[403].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_916   SIUL2.MSCR_MUX[404].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_917   SIUL2.MSCR_MUX[405].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_918   SIUL2.MSCR_MUX[406].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_919   SIUL2.MSCR_MUX[407].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_920   SIUL2.MSCR_MUX[408].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_921   SIUL2.MSCR_MUX[409].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_922   SIUL2.MSCR_MUX[410].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_923   SIUL2.MSCR_MUX[411].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_924   SIUL2.MSCR_MUX[412].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_925   SIUL2.MSCR_MUX[413].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_926   SIUL2.MSCR_MUX[414].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_927   SIUL2.MSCR_MUX[415].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_928   SIUL2.MSCR_MUX[416].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_929   SIUL2.MSCR_MUX[417].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_930   SIUL2.MSCR_MUX[418].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_931   SIUL2.MSCR_MUX[419].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_932   SIUL2.MSCR_MUX[420].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_933   SIUL2.MSCR_MUX[421].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_934   SIUL2.MSCR_MUX[422].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_935   SIUL2.MSCR_MUX[423].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_936   SIUL2.MSCR_MUX[424].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_937   SIUL2.MSCR_MUX[425].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_938   SIUL2.MSCR_MUX[426].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_939   SIUL2.MSCR_MUX[427].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_940   SIUL2.MSCR_MUX[428].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_941   SIUL2.MSCR_MUX[429].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_942   SIUL2.MSCR_MUX[430].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_943   SIUL2.MSCR_MUX[431].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_944   SIUL2.MSCR_MUX[432].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_945   SIUL2.MSCR_MUX[433].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_946   SIUL2.MSCR_MUX[434].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_947   SIUL2.MSCR_MUX[435].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_948   SIUL2.MSCR_MUX[436].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_949   SIUL2.MSCR_MUX[437].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_950   SIUL2.MSCR_MUX[438].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_951   SIUL2.MSCR_MUX[439].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_952   SIUL2.MSCR_MUX[440].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_953   SIUL2.MSCR_MUX[441].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_954   SIUL2.MSCR_MUX[442].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_955   SIUL2.MSCR_MUX[443].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_956   SIUL2.MSCR_MUX[444].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_957   SIUL2.MSCR_MUX[445].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_958   SIUL2.MSCR_MUX[446].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_959   SIUL2.MSCR_MUX[447].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_960   SIUL2.MSCR_MUX[448].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_961   SIUL2.MSCR_MUX[449].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_962   SIUL2.MSCR_MUX[450].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_963   SIUL2.MSCR_MUX[451].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_964   SIUL2.MSCR_MUX[452].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_965   SIUL2.MSCR_MUX[453].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_966   SIUL2.MSCR_MUX[454].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_967   SIUL2.MSCR_MUX[455].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_968   SIUL2.MSCR_MUX[456].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_969   SIUL2.MSCR_MUX[457].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_970   SIUL2.MSCR_MUX[458].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_971   SIUL2.MSCR_MUX[459].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_972   SIUL2.MSCR_MUX[460].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_973   SIUL2.MSCR_MUX[461].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_974   SIUL2.MSCR_MUX[462].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_975   SIUL2.MSCR_MUX[463].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_976   SIUL2.MSCR_MUX[464].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_977   SIUL2.MSCR_MUX[465].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_978   SIUL2.MSCR_MUX[466].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_979   SIUL2.MSCR_MUX[467].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_980   SIUL2.MSCR_MUX[468].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_981   SIUL2.MSCR_MUX[469].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_982   SIUL2.MSCR_MUX[470].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_983   SIUL2.MSCR_MUX[471].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_984   SIUL2.MSCR_MUX[472].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_985   SIUL2.MSCR_MUX[473].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_986   SIUL2.MSCR_MUX[474].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_987   SIUL2.MSCR_MUX[475].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_988   SIUL2.MSCR_MUX[476].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_989   SIUL2.MSCR_MUX[477].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_990   SIUL2.MSCR_MUX[478].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_991   SIUL2.MSCR_MUX[479].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_992   SIUL2.MSCR_MUX[480].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_993   SIUL2.MSCR_MUX[481].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_994   SIUL2.MSCR_MUX[482].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_995   SIUL2.MSCR_MUX[483].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_996   SIUL2.MSCR_MUX[484].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_997   SIUL2.MSCR_MUX[485].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_998   SIUL2.MSCR_MUX[486].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_999   SIUL2.MSCR_MUX[487].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1000  SIUL2.MSCR_MUX[488].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1001  SIUL2.MSCR_MUX[489].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1002  SIUL2.MSCR_MUX[490].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1003  SIUL2.MSCR_MUX[491].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1004  SIUL2.MSCR_MUX[492].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1005  SIUL2.MSCR_MUX[493].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1006  SIUL2.MSCR_MUX[494].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1007  SIUL2.MSCR_MUX[495].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1008  SIUL2.MSCR_MUX[496].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1009  SIUL2.MSCR_MUX[497].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1010  SIUL2.MSCR_MUX[498].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1011  SIUL2.MSCR_MUX[499].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1012  SIUL2.MSCR_MUX[500].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1013  SIUL2.MSCR_MUX[501].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1014  SIUL2.MSCR_MUX[502].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1015  SIUL2.MSCR_MUX[503].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1016  SIUL2.MSCR_MUX[504].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1017  SIUL2.MSCR_MUX[505].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1018  SIUL2.MSCR_MUX[506].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1019  SIUL2.MSCR_MUX[507].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1020  SIUL2.MSCR_MUX[508].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1021  SIUL2.MSCR_MUX[509].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1022  SIUL2.MSCR_MUX[510].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_MSCR_MUX_1023  SIUL2.MSCR_MUX[511].R         /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
#define SIUL2_GPDO0          SIUL2.GPDO[0].R               /* GPIO Pad Data Out Register */
#define SIUL2_GPDO1          SIUL2.GPDO[1].R               /* GPIO Pad Data Out Register */
#define SIUL2_GPDO2          SIUL2.GPDO[2].R               /* GPIO Pad Data Out Register */
#define SIUL2_GPDO3          SIUL2.GPDO[3].R               /* GPIO Pad Data Out Register */
#define SIUL2_GPDO4          SIUL2.GPDO[4].R               /* GPIO Pad Data Out Register */
#define SIUL2_GPDO5          SIUL2.GPDO[5].R               /* GPIO Pad Data Out Register */
#define SIUL2_GPDO6          SIUL2.GPDO[6].R               /* GPIO Pad Data Out Register */
#define SIUL2_GPDO7          SIUL2.GPDO[7].R               /* GPIO Pad Data Out Register */
#define SIUL2_GPDO8          SIUL2.GPDO[8].R               /* GPIO Pad Data Out Register */
#define SIUL2_GPDO9          SIUL2.GPDO[9].R               /* GPIO Pad Data Out Register */
#define SIUL2_GPDO10         SIUL2.GPDO[10].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO11         SIUL2.GPDO[11].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO12         SIUL2.GPDO[12].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO13         SIUL2.GPDO[13].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO14         SIUL2.GPDO[14].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO15         SIUL2.GPDO[15].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO16         SIUL2.GPDO[16].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO17         SIUL2.GPDO[17].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO18         SIUL2.GPDO[18].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO19         SIUL2.GPDO[19].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO20         SIUL2.GPDO[20].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO21         SIUL2.GPDO[21].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO22         SIUL2.GPDO[22].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO23         SIUL2.GPDO[23].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO24         SIUL2.GPDO[24].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO25         SIUL2.GPDO[25].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO26         SIUL2.GPDO[26].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO27         SIUL2.GPDO[27].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO28         SIUL2.GPDO[28].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO29         SIUL2.GPDO[29].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO30         SIUL2.GPDO[30].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO31         SIUL2.GPDO[31].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO32         SIUL2.GPDO[32].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO33         SIUL2.GPDO[33].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO34         SIUL2.GPDO[34].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO35         SIUL2.GPDO[35].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO36         SIUL2.GPDO[36].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO37         SIUL2.GPDO[37].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO38         SIUL2.GPDO[38].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO39         SIUL2.GPDO[39].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO40         SIUL2.GPDO[40].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO41         SIUL2.GPDO[41].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO42         SIUL2.GPDO[42].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO43         SIUL2.GPDO[43].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO44         SIUL2.GPDO[44].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO45         SIUL2.GPDO[45].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO46         SIUL2.GPDO[46].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO47         SIUL2.GPDO[47].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO48         SIUL2.GPDO[48].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO49         SIUL2.GPDO[49].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO50         SIUL2.GPDO[50].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO51         SIUL2.GPDO[51].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO52         SIUL2.GPDO[52].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO53         SIUL2.GPDO[53].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO54         SIUL2.GPDO[54].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO55         SIUL2.GPDO[55].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO56         SIUL2.GPDO[56].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO57         SIUL2.GPDO[57].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO58         SIUL2.GPDO[58].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO59         SIUL2.GPDO[59].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO60         SIUL2.GPDO[60].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO61         SIUL2.GPDO[61].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO62         SIUL2.GPDO[62].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO63         SIUL2.GPDO[63].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO64         SIUL2.GPDO[64].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO65         SIUL2.GPDO[65].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO66         SIUL2.GPDO[66].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO67         SIUL2.GPDO[67].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO68         SIUL2.GPDO[68].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO69         SIUL2.GPDO[69].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO70         SIUL2.GPDO[70].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO71         SIUL2.GPDO[71].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO72         SIUL2.GPDO[72].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO73         SIUL2.GPDO[73].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO74         SIUL2.GPDO[74].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO75         SIUL2.GPDO[75].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO76         SIUL2.GPDO[76].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO77         SIUL2.GPDO[77].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO78         SIUL2.GPDO[78].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO79         SIUL2.GPDO[79].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO80         SIUL2.GPDO[80].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO81         SIUL2.GPDO[81].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO82         SIUL2.GPDO[82].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO83         SIUL2.GPDO[83].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO84         SIUL2.GPDO[84].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO85         SIUL2.GPDO[85].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO86         SIUL2.GPDO[86].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO87         SIUL2.GPDO[87].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO88         SIUL2.GPDO[88].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO89         SIUL2.GPDO[89].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO90         SIUL2.GPDO[90].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO91         SIUL2.GPDO[91].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO92         SIUL2.GPDO[92].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO93         SIUL2.GPDO[93].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO94         SIUL2.GPDO[94].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO95         SIUL2.GPDO[95].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO96         SIUL2.GPDO[96].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO97         SIUL2.GPDO[97].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO98         SIUL2.GPDO[98].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO99         SIUL2.GPDO[99].R              /* GPIO Pad Data Out Register */
#define SIUL2_GPDO100        SIUL2.GPDO[100].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO101        SIUL2.GPDO[101].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO102        SIUL2.GPDO[102].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO103        SIUL2.GPDO[103].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO104        SIUL2.GPDO[104].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO105        SIUL2.GPDO[105].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO106        SIUL2.GPDO[106].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO107        SIUL2.GPDO[107].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO108        SIUL2.GPDO[108].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO109        SIUL2.GPDO[109].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO110        SIUL2.GPDO[110].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO111        SIUL2.GPDO[111].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO112        SIUL2.GPDO[112].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO113        SIUL2.GPDO[113].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO114        SIUL2.GPDO[114].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO115        SIUL2.GPDO[115].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO116        SIUL2.GPDO[116].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO117        SIUL2.GPDO[117].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO118        SIUL2.GPDO[118].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO119        SIUL2.GPDO[119].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO120        SIUL2.GPDO[120].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO121        SIUL2.GPDO[121].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO122        SIUL2.GPDO[122].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO123        SIUL2.GPDO[123].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO124        SIUL2.GPDO[124].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO125        SIUL2.GPDO[125].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO126        SIUL2.GPDO[126].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO127        SIUL2.GPDO[127].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO128        SIUL2.GPDO[128].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO129        SIUL2.GPDO[129].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO130        SIUL2.GPDO[130].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO131        SIUL2.GPDO[131].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO132        SIUL2.GPDO[132].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO133        SIUL2.GPDO[133].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO134        SIUL2.GPDO[134].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO135        SIUL2.GPDO[135].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO136        SIUL2.GPDO[136].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO137        SIUL2.GPDO[137].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO138        SIUL2.GPDO[138].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO139        SIUL2.GPDO[139].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO140        SIUL2.GPDO[140].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO141        SIUL2.GPDO[141].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO142        SIUL2.GPDO[142].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO143        SIUL2.GPDO[143].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO144        SIUL2.GPDO[144].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO145        SIUL2.GPDO[145].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO146        SIUL2.GPDO[146].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO147        SIUL2.GPDO[147].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO148        SIUL2.GPDO[148].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO149        SIUL2.GPDO[149].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO150        SIUL2.GPDO[150].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO151        SIUL2.GPDO[151].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO152        SIUL2.GPDO[152].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO153        SIUL2.GPDO[153].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO154        SIUL2.GPDO[154].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO155        SIUL2.GPDO[155].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO156        SIUL2.GPDO[156].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO157        SIUL2.GPDO[157].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO158        SIUL2.GPDO[158].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO159        SIUL2.GPDO[159].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO160        SIUL2.GPDO[160].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO161        SIUL2.GPDO[161].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO162        SIUL2.GPDO[162].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO163        SIUL2.GPDO[163].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO164        SIUL2.GPDO[164].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO165        SIUL2.GPDO[165].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO166        SIUL2.GPDO[166].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO167        SIUL2.GPDO[167].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO168        SIUL2.GPDO[168].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO169        SIUL2.GPDO[169].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO170        SIUL2.GPDO[170].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO171        SIUL2.GPDO[171].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO172        SIUL2.GPDO[172].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO173        SIUL2.GPDO[173].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO174        SIUL2.GPDO[174].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO175        SIUL2.GPDO[175].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO176        SIUL2.GPDO[176].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO177        SIUL2.GPDO[177].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO178        SIUL2.GPDO[178].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO179        SIUL2.GPDO[179].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO180        SIUL2.GPDO[180].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO181        SIUL2.GPDO[181].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO182        SIUL2.GPDO[182].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO183        SIUL2.GPDO[183].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO184        SIUL2.GPDO[184].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO185        SIUL2.GPDO[185].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO186        SIUL2.GPDO[186].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO187        SIUL2.GPDO[187].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO188        SIUL2.GPDO[188].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO189        SIUL2.GPDO[189].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO190        SIUL2.GPDO[190].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO191        SIUL2.GPDO[191].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO192        SIUL2.GPDO[192].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO193        SIUL2.GPDO[193].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO194        SIUL2.GPDO[194].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO195        SIUL2.GPDO[195].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO196        SIUL2.GPDO[196].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO197        SIUL2.GPDO[197].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO198        SIUL2.GPDO[198].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO199        SIUL2.GPDO[199].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO200        SIUL2.GPDO[200].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO201        SIUL2.GPDO[201].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO202        SIUL2.GPDO[202].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO203        SIUL2.GPDO[203].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO204        SIUL2.GPDO[204].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO205        SIUL2.GPDO[205].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO206        SIUL2.GPDO[206].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO207        SIUL2.GPDO[207].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO208        SIUL2.GPDO[208].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO209        SIUL2.GPDO[209].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO210        SIUL2.GPDO[210].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO211        SIUL2.GPDO[211].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO212        SIUL2.GPDO[212].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO213        SIUL2.GPDO[213].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO214        SIUL2.GPDO[214].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO215        SIUL2.GPDO[215].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO216        SIUL2.GPDO[216].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO217        SIUL2.GPDO[217].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO218        SIUL2.GPDO[218].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO219        SIUL2.GPDO[219].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO220        SIUL2.GPDO[220].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO221        SIUL2.GPDO[221].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO222        SIUL2.GPDO[222].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO223        SIUL2.GPDO[223].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO224        SIUL2.GPDO[224].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO225        SIUL2.GPDO[225].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO226        SIUL2.GPDO[226].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO227        SIUL2.GPDO[227].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO228        SIUL2.GPDO[228].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO229        SIUL2.GPDO[229].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO230        SIUL2.GPDO[230].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO231        SIUL2.GPDO[231].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO232        SIUL2.GPDO[232].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO233        SIUL2.GPDO[233].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO234        SIUL2.GPDO[234].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO235        SIUL2.GPDO[235].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO236        SIUL2.GPDO[236].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO237        SIUL2.GPDO[237].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO238        SIUL2.GPDO[238].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO239        SIUL2.GPDO[239].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO240        SIUL2.GPDO[240].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO241        SIUL2.GPDO[241].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO242        SIUL2.GPDO[242].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO243        SIUL2.GPDO[243].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO244        SIUL2.GPDO[244].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO245        SIUL2.GPDO[245].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO246        SIUL2.GPDO[246].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO247        SIUL2.GPDO[247].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO248        SIUL2.GPDO[248].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO249        SIUL2.GPDO[249].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO250        SIUL2.GPDO[250].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO251        SIUL2.GPDO[251].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO252        SIUL2.GPDO[252].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO253        SIUL2.GPDO[253].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO254        SIUL2.GPDO[254].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO255        SIUL2.GPDO[255].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO256        SIUL2.GPDO[256].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO257        SIUL2.GPDO[257].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO258        SIUL2.GPDO[258].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO259        SIUL2.GPDO[259].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO260        SIUL2.GPDO[260].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO261        SIUL2.GPDO[261].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO262        SIUL2.GPDO[262].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO263        SIUL2.GPDO[263].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO264        SIUL2.GPDO[264].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO265        SIUL2.GPDO[265].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO266        SIUL2.GPDO[266].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO267        SIUL2.GPDO[267].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO268        SIUL2.GPDO[268].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO269        SIUL2.GPDO[269].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO270        SIUL2.GPDO[270].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO271        SIUL2.GPDO[271].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO272        SIUL2.GPDO[272].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO273        SIUL2.GPDO[273].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO274        SIUL2.GPDO[274].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO275        SIUL2.GPDO[275].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO276        SIUL2.GPDO[276].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO277        SIUL2.GPDO[277].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO278        SIUL2.GPDO[278].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO279        SIUL2.GPDO[279].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO280        SIUL2.GPDO[280].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO281        SIUL2.GPDO[281].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO282        SIUL2.GPDO[282].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO283        SIUL2.GPDO[283].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO284        SIUL2.GPDO[284].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO285        SIUL2.GPDO[285].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO286        SIUL2.GPDO[286].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO287        SIUL2.GPDO[287].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO288        SIUL2.GPDO[288].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO289        SIUL2.GPDO[289].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO290        SIUL2.GPDO[290].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO291        SIUL2.GPDO[291].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO292        SIUL2.GPDO[292].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO293        SIUL2.GPDO[293].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO294        SIUL2.GPDO[294].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO295        SIUL2.GPDO[295].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO296        SIUL2.GPDO[296].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO297        SIUL2.GPDO[297].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO298        SIUL2.GPDO[298].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO299        SIUL2.GPDO[299].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO300        SIUL2.GPDO[300].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO301        SIUL2.GPDO[301].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO302        SIUL2.GPDO[302].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO303        SIUL2.GPDO[303].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO304        SIUL2.GPDO[304].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO305        SIUL2.GPDO[305].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO306        SIUL2.GPDO[306].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO307        SIUL2.GPDO[307].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO308        SIUL2.GPDO[308].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO309        SIUL2.GPDO[309].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO310        SIUL2.GPDO[310].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO311        SIUL2.GPDO[311].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO312        SIUL2.GPDO[312].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO313        SIUL2.GPDO[313].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO314        SIUL2.GPDO[314].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO315        SIUL2.GPDO[315].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO316        SIUL2.GPDO[316].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO317        SIUL2.GPDO[317].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO318        SIUL2.GPDO[318].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO319        SIUL2.GPDO[319].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO320        SIUL2.GPDO[320].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO321        SIUL2.GPDO[321].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO322        SIUL2.GPDO[322].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO323        SIUL2.GPDO[323].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO324        SIUL2.GPDO[324].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO325        SIUL2.GPDO[325].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO326        SIUL2.GPDO[326].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO327        SIUL2.GPDO[327].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO328        SIUL2.GPDO[328].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO329        SIUL2.GPDO[329].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO330        SIUL2.GPDO[330].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO331        SIUL2.GPDO[331].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO332        SIUL2.GPDO[332].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO333        SIUL2.GPDO[333].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO334        SIUL2.GPDO[334].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO335        SIUL2.GPDO[335].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO336        SIUL2.GPDO[336].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO337        SIUL2.GPDO[337].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO338        SIUL2.GPDO[338].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO339        SIUL2.GPDO[339].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO340        SIUL2.GPDO[340].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO341        SIUL2.GPDO[341].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO342        SIUL2.GPDO[342].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO343        SIUL2.GPDO[343].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO344        SIUL2.GPDO[344].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO345        SIUL2.GPDO[345].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO346        SIUL2.GPDO[346].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO347        SIUL2.GPDO[347].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO348        SIUL2.GPDO[348].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO349        SIUL2.GPDO[349].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO350        SIUL2.GPDO[350].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO351        SIUL2.GPDO[351].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO352        SIUL2.GPDO[352].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO353        SIUL2.GPDO[353].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO354        SIUL2.GPDO[354].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO355        SIUL2.GPDO[355].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO356        SIUL2.GPDO[356].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO357        SIUL2.GPDO[357].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO358        SIUL2.GPDO[358].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO359        SIUL2.GPDO[359].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO360        SIUL2.GPDO[360].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO361        SIUL2.GPDO[361].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO362        SIUL2.GPDO[362].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO363        SIUL2.GPDO[363].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO364        SIUL2.GPDO[364].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO365        SIUL2.GPDO[365].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO366        SIUL2.GPDO[366].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO367        SIUL2.GPDO[367].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO368        SIUL2.GPDO[368].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO369        SIUL2.GPDO[369].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO370        SIUL2.GPDO[370].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO371        SIUL2.GPDO[371].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO372        SIUL2.GPDO[372].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO373        SIUL2.GPDO[373].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO374        SIUL2.GPDO[374].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO375        SIUL2.GPDO[375].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO376        SIUL2.GPDO[376].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO377        SIUL2.GPDO[377].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO378        SIUL2.GPDO[378].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO379        SIUL2.GPDO[379].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO380        SIUL2.GPDO[380].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO381        SIUL2.GPDO[381].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO382        SIUL2.GPDO[382].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO383        SIUL2.GPDO[383].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO384        SIUL2.GPDO[384].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO385        SIUL2.GPDO[385].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO386        SIUL2.GPDO[386].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO387        SIUL2.GPDO[387].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO388        SIUL2.GPDO[388].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO389        SIUL2.GPDO[389].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO390        SIUL2.GPDO[390].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO391        SIUL2.GPDO[391].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO392        SIUL2.GPDO[392].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO393        SIUL2.GPDO[393].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO394        SIUL2.GPDO[394].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO395        SIUL2.GPDO[395].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO396        SIUL2.GPDO[396].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO397        SIUL2.GPDO[397].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO398        SIUL2.GPDO[398].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO399        SIUL2.GPDO[399].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO400        SIUL2.GPDO[400].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO401        SIUL2.GPDO[401].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO402        SIUL2.GPDO[402].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO403        SIUL2.GPDO[403].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO404        SIUL2.GPDO[404].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO405        SIUL2.GPDO[405].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO406        SIUL2.GPDO[406].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO407        SIUL2.GPDO[407].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO408        SIUL2.GPDO[408].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO409        SIUL2.GPDO[409].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO410        SIUL2.GPDO[410].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO411        SIUL2.GPDO[411].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO412        SIUL2.GPDO[412].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO413        SIUL2.GPDO[413].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO414        SIUL2.GPDO[414].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO415        SIUL2.GPDO[415].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO416        SIUL2.GPDO[416].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO417        SIUL2.GPDO[417].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO418        SIUL2.GPDO[418].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO419        SIUL2.GPDO[419].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO420        SIUL2.GPDO[420].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO421        SIUL2.GPDO[421].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO422        SIUL2.GPDO[422].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO423        SIUL2.GPDO[423].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO424        SIUL2.GPDO[424].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO425        SIUL2.GPDO[425].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO426        SIUL2.GPDO[426].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO427        SIUL2.GPDO[427].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO428        SIUL2.GPDO[428].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO429        SIUL2.GPDO[429].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO430        SIUL2.GPDO[430].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO431        SIUL2.GPDO[431].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO432        SIUL2.GPDO[432].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO433        SIUL2.GPDO[433].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO434        SIUL2.GPDO[434].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO435        SIUL2.GPDO[435].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO436        SIUL2.GPDO[436].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO437        SIUL2.GPDO[437].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO438        SIUL2.GPDO[438].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO439        SIUL2.GPDO[439].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO440        SIUL2.GPDO[440].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO441        SIUL2.GPDO[441].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO442        SIUL2.GPDO[442].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO443        SIUL2.GPDO[443].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO444        SIUL2.GPDO[444].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO445        SIUL2.GPDO[445].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO446        SIUL2.GPDO[446].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO447        SIUL2.GPDO[447].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO448        SIUL2.GPDO[448].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO449        SIUL2.GPDO[449].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO450        SIUL2.GPDO[450].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO451        SIUL2.GPDO[451].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO452        SIUL2.GPDO[452].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO453        SIUL2.GPDO[453].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO454        SIUL2.GPDO[454].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO455        SIUL2.GPDO[455].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO456        SIUL2.GPDO[456].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO457        SIUL2.GPDO[457].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO458        SIUL2.GPDO[458].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO459        SIUL2.GPDO[459].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO460        SIUL2.GPDO[460].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO461        SIUL2.GPDO[461].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO462        SIUL2.GPDO[462].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO463        SIUL2.GPDO[463].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO464        SIUL2.GPDO[464].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO465        SIUL2.GPDO[465].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO466        SIUL2.GPDO[466].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO467        SIUL2.GPDO[467].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO468        SIUL2.GPDO[468].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO469        SIUL2.GPDO[469].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO470        SIUL2.GPDO[470].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO471        SIUL2.GPDO[471].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO472        SIUL2.GPDO[472].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO473        SIUL2.GPDO[473].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO474        SIUL2.GPDO[474].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO475        SIUL2.GPDO[475].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO476        SIUL2.GPDO[476].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO477        SIUL2.GPDO[477].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO478        SIUL2.GPDO[478].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO479        SIUL2.GPDO[479].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO480        SIUL2.GPDO[480].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO481        SIUL2.GPDO[481].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO482        SIUL2.GPDO[482].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO483        SIUL2.GPDO[483].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO484        SIUL2.GPDO[484].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO485        SIUL2.GPDO[485].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO486        SIUL2.GPDO[486].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO487        SIUL2.GPDO[487].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO488        SIUL2.GPDO[488].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO489        SIUL2.GPDO[489].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO490        SIUL2.GPDO[490].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO491        SIUL2.GPDO[491].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO492        SIUL2.GPDO[492].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO493        SIUL2.GPDO[493].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO494        SIUL2.GPDO[494].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO495        SIUL2.GPDO[495].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO496        SIUL2.GPDO[496].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO497        SIUL2.GPDO[497].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO498        SIUL2.GPDO[498].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO499        SIUL2.GPDO[499].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO500        SIUL2.GPDO[500].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO501        SIUL2.GPDO[501].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO502        SIUL2.GPDO[502].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO503        SIUL2.GPDO[503].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO504        SIUL2.GPDO[504].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO505        SIUL2.GPDO[505].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO506        SIUL2.GPDO[506].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO507        SIUL2.GPDO[507].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO508        SIUL2.GPDO[508].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO509        SIUL2.GPDO[509].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO510        SIUL2.GPDO[510].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDO511        SIUL2.GPDO[511].R             /* GPIO Pad Data Out Register */
#define SIUL2_GPDI0          SIUL2.GPDI[0].R               /* GPIO Pad Data In Register */
#define SIUL2_GPDI1          SIUL2.GPDI[1].R               /* GPIO Pad Data In Register */
#define SIUL2_GPDI2          SIUL2.GPDI[2].R               /* GPIO Pad Data In Register */
#define SIUL2_GPDI3          SIUL2.GPDI[3].R               /* GPIO Pad Data In Register */
#define SIUL2_GPDI4          SIUL2.GPDI[4].R               /* GPIO Pad Data In Register */
#define SIUL2_GPDI5          SIUL2.GPDI[5].R               /* GPIO Pad Data In Register */
#define SIUL2_GPDI6          SIUL2.GPDI[6].R               /* GPIO Pad Data In Register */
#define SIUL2_GPDI7          SIUL2.GPDI[7].R               /* GPIO Pad Data In Register */
#define SIUL2_GPDI8          SIUL2.GPDI[8].R               /* GPIO Pad Data In Register */
#define SIUL2_GPDI9          SIUL2.GPDI[9].R               /* GPIO Pad Data In Register */
#define SIUL2_GPDI10         SIUL2.GPDI[10].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI11         SIUL2.GPDI[11].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI12         SIUL2.GPDI[12].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI13         SIUL2.GPDI[13].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI14         SIUL2.GPDI[14].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI15         SIUL2.GPDI[15].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI16         SIUL2.GPDI[16].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI17         SIUL2.GPDI[17].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI18         SIUL2.GPDI[18].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI19         SIUL2.GPDI[19].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI20         SIUL2.GPDI[20].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI21         SIUL2.GPDI[21].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI22         SIUL2.GPDI[22].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI23         SIUL2.GPDI[23].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI24         SIUL2.GPDI[24].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI25         SIUL2.GPDI[25].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI26         SIUL2.GPDI[26].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI27         SIUL2.GPDI[27].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI28         SIUL2.GPDI[28].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI29         SIUL2.GPDI[29].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI30         SIUL2.GPDI[30].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI31         SIUL2.GPDI[31].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI32         SIUL2.GPDI[32].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI33         SIUL2.GPDI[33].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI34         SIUL2.GPDI[34].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI35         SIUL2.GPDI[35].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI36         SIUL2.GPDI[36].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI37         SIUL2.GPDI[37].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI38         SIUL2.GPDI[38].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI39         SIUL2.GPDI[39].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI40         SIUL2.GPDI[40].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI41         SIUL2.GPDI[41].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI42         SIUL2.GPDI[42].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI43         SIUL2.GPDI[43].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI44         SIUL2.GPDI[44].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI45         SIUL2.GPDI[45].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI46         SIUL2.GPDI[46].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI47         SIUL2.GPDI[47].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI48         SIUL2.GPDI[48].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI49         SIUL2.GPDI[49].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI50         SIUL2.GPDI[50].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI51         SIUL2.GPDI[51].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI52         SIUL2.GPDI[52].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI53         SIUL2.GPDI[53].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI54         SIUL2.GPDI[54].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI55         SIUL2.GPDI[55].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI56         SIUL2.GPDI[56].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI57         SIUL2.GPDI[57].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI58         SIUL2.GPDI[58].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI59         SIUL2.GPDI[59].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI60         SIUL2.GPDI[60].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI61         SIUL2.GPDI[61].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI62         SIUL2.GPDI[62].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI63         SIUL2.GPDI[63].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI64         SIUL2.GPDI[64].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI65         SIUL2.GPDI[65].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI66         SIUL2.GPDI[66].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI67         SIUL2.GPDI[67].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI68         SIUL2.GPDI[68].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI69         SIUL2.GPDI[69].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI70         SIUL2.GPDI[70].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI71         SIUL2.GPDI[71].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI72         SIUL2.GPDI[72].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI73         SIUL2.GPDI[73].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI74         SIUL2.GPDI[74].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI75         SIUL2.GPDI[75].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI76         SIUL2.GPDI[76].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI77         SIUL2.GPDI[77].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI78         SIUL2.GPDI[78].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI79         SIUL2.GPDI[79].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI80         SIUL2.GPDI[80].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI81         SIUL2.GPDI[81].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI82         SIUL2.GPDI[82].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI83         SIUL2.GPDI[83].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI84         SIUL2.GPDI[84].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI85         SIUL2.GPDI[85].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI86         SIUL2.GPDI[86].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI87         SIUL2.GPDI[87].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI88         SIUL2.GPDI[88].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI89         SIUL2.GPDI[89].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI90         SIUL2.GPDI[90].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI91         SIUL2.GPDI[91].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI92         SIUL2.GPDI[92].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI93         SIUL2.GPDI[93].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI94         SIUL2.GPDI[94].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI95         SIUL2.GPDI[95].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI96         SIUL2.GPDI[96].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI97         SIUL2.GPDI[97].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI98         SIUL2.GPDI[98].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI99         SIUL2.GPDI[99].R              /* GPIO Pad Data In Register */
#define SIUL2_GPDI100        SIUL2.GPDI[100].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI101        SIUL2.GPDI[101].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI102        SIUL2.GPDI[102].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI103        SIUL2.GPDI[103].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI104        SIUL2.GPDI[104].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI105        SIUL2.GPDI[105].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI106        SIUL2.GPDI[106].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI107        SIUL2.GPDI[107].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI108        SIUL2.GPDI[108].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI109        SIUL2.GPDI[109].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI110        SIUL2.GPDI[110].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI111        SIUL2.GPDI[111].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI112        SIUL2.GPDI[112].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI113        SIUL2.GPDI[113].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI114        SIUL2.GPDI[114].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI115        SIUL2.GPDI[115].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI116        SIUL2.GPDI[116].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI117        SIUL2.GPDI[117].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI118        SIUL2.GPDI[118].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI119        SIUL2.GPDI[119].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI120        SIUL2.GPDI[120].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI121        SIUL2.GPDI[121].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI122        SIUL2.GPDI[122].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI123        SIUL2.GPDI[123].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI124        SIUL2.GPDI[124].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI125        SIUL2.GPDI[125].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI126        SIUL2.GPDI[126].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI127        SIUL2.GPDI[127].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI128        SIUL2.GPDI[128].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI129        SIUL2.GPDI[129].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI130        SIUL2.GPDI[130].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI131        SIUL2.GPDI[131].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI132        SIUL2.GPDI[132].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI133        SIUL2.GPDI[133].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI134        SIUL2.GPDI[134].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI135        SIUL2.GPDI[135].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI136        SIUL2.GPDI[136].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI137        SIUL2.GPDI[137].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI138        SIUL2.GPDI[138].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI139        SIUL2.GPDI[139].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI140        SIUL2.GPDI[140].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI141        SIUL2.GPDI[141].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI142        SIUL2.GPDI[142].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI143        SIUL2.GPDI[143].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI144        SIUL2.GPDI[144].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI145        SIUL2.GPDI[145].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI146        SIUL2.GPDI[146].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI147        SIUL2.GPDI[147].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI148        SIUL2.GPDI[148].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI149        SIUL2.GPDI[149].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI150        SIUL2.GPDI[150].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI151        SIUL2.GPDI[151].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI152        SIUL2.GPDI[152].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI153        SIUL2.GPDI[153].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI154        SIUL2.GPDI[154].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI155        SIUL2.GPDI[155].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI156        SIUL2.GPDI[156].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI157        SIUL2.GPDI[157].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI158        SIUL2.GPDI[158].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI159        SIUL2.GPDI[159].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI160        SIUL2.GPDI[160].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI161        SIUL2.GPDI[161].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI162        SIUL2.GPDI[162].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI163        SIUL2.GPDI[163].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI164        SIUL2.GPDI[164].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI165        SIUL2.GPDI[165].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI166        SIUL2.GPDI[166].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI167        SIUL2.GPDI[167].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI168        SIUL2.GPDI[168].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI169        SIUL2.GPDI[169].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI170        SIUL2.GPDI[170].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI171        SIUL2.GPDI[171].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI172        SIUL2.GPDI[172].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI173        SIUL2.GPDI[173].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI174        SIUL2.GPDI[174].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI175        SIUL2.GPDI[175].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI176        SIUL2.GPDI[176].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI177        SIUL2.GPDI[177].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI178        SIUL2.GPDI[178].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI179        SIUL2.GPDI[179].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI180        SIUL2.GPDI[180].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI181        SIUL2.GPDI[181].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI182        SIUL2.GPDI[182].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI183        SIUL2.GPDI[183].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI184        SIUL2.GPDI[184].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI185        SIUL2.GPDI[185].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI186        SIUL2.GPDI[186].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI187        SIUL2.GPDI[187].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI188        SIUL2.GPDI[188].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI189        SIUL2.GPDI[189].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI190        SIUL2.GPDI[190].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI191        SIUL2.GPDI[191].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI192        SIUL2.GPDI[192].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI193        SIUL2.GPDI[193].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI194        SIUL2.GPDI[194].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI195        SIUL2.GPDI[195].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI196        SIUL2.GPDI[196].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI197        SIUL2.GPDI[197].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI198        SIUL2.GPDI[198].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI199        SIUL2.GPDI[199].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI200        SIUL2.GPDI[200].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI201        SIUL2.GPDI[201].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI202        SIUL2.GPDI[202].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI203        SIUL2.GPDI[203].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI204        SIUL2.GPDI[204].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI205        SIUL2.GPDI[205].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI206        SIUL2.GPDI[206].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI207        SIUL2.GPDI[207].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI208        SIUL2.GPDI[208].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI209        SIUL2.GPDI[209].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI210        SIUL2.GPDI[210].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI211        SIUL2.GPDI[211].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI212        SIUL2.GPDI[212].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI213        SIUL2.GPDI[213].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI214        SIUL2.GPDI[214].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI215        SIUL2.GPDI[215].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI216        SIUL2.GPDI[216].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI217        SIUL2.GPDI[217].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI218        SIUL2.GPDI[218].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI219        SIUL2.GPDI[219].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI220        SIUL2.GPDI[220].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI221        SIUL2.GPDI[221].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI222        SIUL2.GPDI[222].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI223        SIUL2.GPDI[223].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI224        SIUL2.GPDI[224].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI225        SIUL2.GPDI[225].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI226        SIUL2.GPDI[226].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI227        SIUL2.GPDI[227].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI228        SIUL2.GPDI[228].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI229        SIUL2.GPDI[229].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI230        SIUL2.GPDI[230].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI231        SIUL2.GPDI[231].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI232        SIUL2.GPDI[232].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI233        SIUL2.GPDI[233].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI234        SIUL2.GPDI[234].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI235        SIUL2.GPDI[235].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI236        SIUL2.GPDI[236].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI237        SIUL2.GPDI[237].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI238        SIUL2.GPDI[238].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI239        SIUL2.GPDI[239].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI240        SIUL2.GPDI[240].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI241        SIUL2.GPDI[241].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI242        SIUL2.GPDI[242].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI243        SIUL2.GPDI[243].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI244        SIUL2.GPDI[244].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI245        SIUL2.GPDI[245].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI246        SIUL2.GPDI[246].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI247        SIUL2.GPDI[247].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI248        SIUL2.GPDI[248].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI249        SIUL2.GPDI[249].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI250        SIUL2.GPDI[250].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI251        SIUL2.GPDI[251].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI252        SIUL2.GPDI[252].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI253        SIUL2.GPDI[253].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI254        SIUL2.GPDI[254].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI255        SIUL2.GPDI[255].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI256        SIUL2.GPDI[256].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI257        SIUL2.GPDI[257].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI258        SIUL2.GPDI[258].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI259        SIUL2.GPDI[259].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI260        SIUL2.GPDI[260].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI261        SIUL2.GPDI[261].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI262        SIUL2.GPDI[262].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI263        SIUL2.GPDI[263].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI264        SIUL2.GPDI[264].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI265        SIUL2.GPDI[265].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI266        SIUL2.GPDI[266].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI267        SIUL2.GPDI[267].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI268        SIUL2.GPDI[268].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI269        SIUL2.GPDI[269].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI270        SIUL2.GPDI[270].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI271        SIUL2.GPDI[271].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI272        SIUL2.GPDI[272].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI273        SIUL2.GPDI[273].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI274        SIUL2.GPDI[274].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI275        SIUL2.GPDI[275].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI276        SIUL2.GPDI[276].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI277        SIUL2.GPDI[277].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI278        SIUL2.GPDI[278].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI279        SIUL2.GPDI[279].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI280        SIUL2.GPDI[280].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI281        SIUL2.GPDI[281].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI282        SIUL2.GPDI[282].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI283        SIUL2.GPDI[283].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI284        SIUL2.GPDI[284].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI285        SIUL2.GPDI[285].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI286        SIUL2.GPDI[286].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI287        SIUL2.GPDI[287].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI288        SIUL2.GPDI[288].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI289        SIUL2.GPDI[289].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI290        SIUL2.GPDI[290].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI291        SIUL2.GPDI[291].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI292        SIUL2.GPDI[292].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI293        SIUL2.GPDI[293].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI294        SIUL2.GPDI[294].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI295        SIUL2.GPDI[295].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI296        SIUL2.GPDI[296].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI297        SIUL2.GPDI[297].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI298        SIUL2.GPDI[298].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI299        SIUL2.GPDI[299].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI300        SIUL2.GPDI[300].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI301        SIUL2.GPDI[301].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI302        SIUL2.GPDI[302].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI303        SIUL2.GPDI[303].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI304        SIUL2.GPDI[304].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI305        SIUL2.GPDI[305].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI306        SIUL2.GPDI[306].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI307        SIUL2.GPDI[307].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI308        SIUL2.GPDI[308].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI309        SIUL2.GPDI[309].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI310        SIUL2.GPDI[310].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI311        SIUL2.GPDI[311].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI312        SIUL2.GPDI[312].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI313        SIUL2.GPDI[313].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI314        SIUL2.GPDI[314].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI315        SIUL2.GPDI[315].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI316        SIUL2.GPDI[316].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI317        SIUL2.GPDI[317].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI318        SIUL2.GPDI[318].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI319        SIUL2.GPDI[319].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI320        SIUL2.GPDI[320].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI321        SIUL2.GPDI[321].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI322        SIUL2.GPDI[322].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI323        SIUL2.GPDI[323].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI324        SIUL2.GPDI[324].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI325        SIUL2.GPDI[325].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI326        SIUL2.GPDI[326].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI327        SIUL2.GPDI[327].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI328        SIUL2.GPDI[328].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI329        SIUL2.GPDI[329].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI330        SIUL2.GPDI[330].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI331        SIUL2.GPDI[331].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI332        SIUL2.GPDI[332].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI333        SIUL2.GPDI[333].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI334        SIUL2.GPDI[334].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI335        SIUL2.GPDI[335].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI336        SIUL2.GPDI[336].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI337        SIUL2.GPDI[337].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI338        SIUL2.GPDI[338].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI339        SIUL2.GPDI[339].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI340        SIUL2.GPDI[340].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI341        SIUL2.GPDI[341].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI342        SIUL2.GPDI[342].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI343        SIUL2.GPDI[343].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI344        SIUL2.GPDI[344].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI345        SIUL2.GPDI[345].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI346        SIUL2.GPDI[346].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI347        SIUL2.GPDI[347].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI348        SIUL2.GPDI[348].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI349        SIUL2.GPDI[349].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI350        SIUL2.GPDI[350].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI351        SIUL2.GPDI[351].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI352        SIUL2.GPDI[352].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI353        SIUL2.GPDI[353].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI354        SIUL2.GPDI[354].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI355        SIUL2.GPDI[355].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI356        SIUL2.GPDI[356].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI357        SIUL2.GPDI[357].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI358        SIUL2.GPDI[358].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI359        SIUL2.GPDI[359].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI360        SIUL2.GPDI[360].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI361        SIUL2.GPDI[361].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI362        SIUL2.GPDI[362].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI363        SIUL2.GPDI[363].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI364        SIUL2.GPDI[364].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI365        SIUL2.GPDI[365].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI366        SIUL2.GPDI[366].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI367        SIUL2.GPDI[367].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI368        SIUL2.GPDI[368].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI369        SIUL2.GPDI[369].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI370        SIUL2.GPDI[370].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI371        SIUL2.GPDI[371].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI372        SIUL2.GPDI[372].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI373        SIUL2.GPDI[373].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI374        SIUL2.GPDI[374].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI375        SIUL2.GPDI[375].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI376        SIUL2.GPDI[376].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI377        SIUL2.GPDI[377].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI378        SIUL2.GPDI[378].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI379        SIUL2.GPDI[379].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI380        SIUL2.GPDI[380].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI381        SIUL2.GPDI[381].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI382        SIUL2.GPDI[382].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI383        SIUL2.GPDI[383].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI384        SIUL2.GPDI[384].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI385        SIUL2.GPDI[385].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI386        SIUL2.GPDI[386].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI387        SIUL2.GPDI[387].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI388        SIUL2.GPDI[388].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI389        SIUL2.GPDI[389].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI390        SIUL2.GPDI[390].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI391        SIUL2.GPDI[391].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI392        SIUL2.GPDI[392].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI393        SIUL2.GPDI[393].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI394        SIUL2.GPDI[394].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI395        SIUL2.GPDI[395].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI396        SIUL2.GPDI[396].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI397        SIUL2.GPDI[397].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI398        SIUL2.GPDI[398].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI399        SIUL2.GPDI[399].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI400        SIUL2.GPDI[400].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI401        SIUL2.GPDI[401].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI402        SIUL2.GPDI[402].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI403        SIUL2.GPDI[403].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI404        SIUL2.GPDI[404].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI405        SIUL2.GPDI[405].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI406        SIUL2.GPDI[406].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI407        SIUL2.GPDI[407].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI408        SIUL2.GPDI[408].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI409        SIUL2.GPDI[409].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI410        SIUL2.GPDI[410].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI411        SIUL2.GPDI[411].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI412        SIUL2.GPDI[412].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI413        SIUL2.GPDI[413].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI414        SIUL2.GPDI[414].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI415        SIUL2.GPDI[415].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI416        SIUL2.GPDI[416].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI417        SIUL2.GPDI[417].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI418        SIUL2.GPDI[418].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI419        SIUL2.GPDI[419].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI420        SIUL2.GPDI[420].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI421        SIUL2.GPDI[421].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI422        SIUL2.GPDI[422].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI423        SIUL2.GPDI[423].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI424        SIUL2.GPDI[424].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI425        SIUL2.GPDI[425].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI426        SIUL2.GPDI[426].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI427        SIUL2.GPDI[427].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI428        SIUL2.GPDI[428].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI429        SIUL2.GPDI[429].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI430        SIUL2.GPDI[430].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI431        SIUL2.GPDI[431].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI432        SIUL2.GPDI[432].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI433        SIUL2.GPDI[433].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI434        SIUL2.GPDI[434].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI435        SIUL2.GPDI[435].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI436        SIUL2.GPDI[436].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI437        SIUL2.GPDI[437].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI438        SIUL2.GPDI[438].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI439        SIUL2.GPDI[439].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI440        SIUL2.GPDI[440].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI441        SIUL2.GPDI[441].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI442        SIUL2.GPDI[442].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI443        SIUL2.GPDI[443].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI444        SIUL2.GPDI[444].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI445        SIUL2.GPDI[445].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI446        SIUL2.GPDI[446].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI447        SIUL2.GPDI[447].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI448        SIUL2.GPDI[448].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI449        SIUL2.GPDI[449].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI450        SIUL2.GPDI[450].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI451        SIUL2.GPDI[451].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI452        SIUL2.GPDI[452].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI453        SIUL2.GPDI[453].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI454        SIUL2.GPDI[454].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI455        SIUL2.GPDI[455].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI456        SIUL2.GPDI[456].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI457        SIUL2.GPDI[457].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI458        SIUL2.GPDI[458].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI459        SIUL2.GPDI[459].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI460        SIUL2.GPDI[460].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI461        SIUL2.GPDI[461].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI462        SIUL2.GPDI[462].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI463        SIUL2.GPDI[463].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI464        SIUL2.GPDI[464].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI465        SIUL2.GPDI[465].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI466        SIUL2.GPDI[466].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI467        SIUL2.GPDI[467].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI468        SIUL2.GPDI[468].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI469        SIUL2.GPDI[469].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI470        SIUL2.GPDI[470].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI471        SIUL2.GPDI[471].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI472        SIUL2.GPDI[472].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI473        SIUL2.GPDI[473].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI474        SIUL2.GPDI[474].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI475        SIUL2.GPDI[475].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI476        SIUL2.GPDI[476].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI477        SIUL2.GPDI[477].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI478        SIUL2.GPDI[478].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI479        SIUL2.GPDI[479].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI480        SIUL2.GPDI[480].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI481        SIUL2.GPDI[481].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI482        SIUL2.GPDI[482].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI483        SIUL2.GPDI[483].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI484        SIUL2.GPDI[484].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI485        SIUL2.GPDI[485].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI486        SIUL2.GPDI[486].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI487        SIUL2.GPDI[487].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI488        SIUL2.GPDI[488].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI489        SIUL2.GPDI[489].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI490        SIUL2.GPDI[490].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI491        SIUL2.GPDI[491].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI492        SIUL2.GPDI[492].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI493        SIUL2.GPDI[493].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI494        SIUL2.GPDI[494].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI495        SIUL2.GPDI[495].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI496        SIUL2.GPDI[496].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI497        SIUL2.GPDI[497].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI498        SIUL2.GPDI[498].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI499        SIUL2.GPDI[499].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI500        SIUL2.GPDI[500].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI501        SIUL2.GPDI[501].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI502        SIUL2.GPDI[502].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI503        SIUL2.GPDI[503].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI504        SIUL2.GPDI[504].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI505        SIUL2.GPDI[505].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI506        SIUL2.GPDI[506].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI507        SIUL2.GPDI[507].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI508        SIUL2.GPDI[508].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI509        SIUL2.GPDI[509].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI510        SIUL2.GPDI[510].R             /* GPIO Pad Data In Register */
#define SIUL2_GPDI511        SIUL2.GPDI[511].R             /* GPIO Pad Data In Register */
#define SIUL2_PGPDO0         SIUL2.PGPDO[0].R              /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO1         SIUL2.PGPDO[1].R              /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO2         SIUL2.PGPDO[2].R              /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO3         SIUL2.PGPDO[3].R              /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO4         SIUL2.PGPDO[4].R              /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO5         SIUL2.PGPDO[5].R              /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO6         SIUL2.PGPDO[6].R              /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO7         SIUL2.PGPDO[7].R              /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO8         SIUL2.PGPDO[8].R              /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO9         SIUL2.PGPDO[9].R              /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO10        SIUL2.PGPDO[10].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO11        SIUL2.PGPDO[11].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO12        SIUL2.PGPDO[12].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO13        SIUL2.PGPDO[13].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO14        SIUL2.PGPDO[14].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO15        SIUL2.PGPDO[15].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO16        SIUL2.PGPDO[16].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO17        SIUL2.PGPDO[17].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO18        SIUL2.PGPDO[18].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO19        SIUL2.PGPDO[19].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO20        SIUL2.PGPDO[20].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO21        SIUL2.PGPDO[21].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO22        SIUL2.PGPDO[22].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO23        SIUL2.PGPDO[23].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO24        SIUL2.PGPDO[24].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO25        SIUL2.PGPDO[25].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO26        SIUL2.PGPDO[26].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO27        SIUL2.PGPDO[27].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO28        SIUL2.PGPDO[28].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO29        SIUL2.PGPDO[29].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO30        SIUL2.PGPDO[30].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDO31        SIUL2.PGPDO[31].R             /* Parallel GPIO Pad Data Out Register */
#define SIUL2_PGPDI0         SIUL2.PGPDI[0].R              /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI1         SIUL2.PGPDI[1].R              /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI2         SIUL2.PGPDI[2].R              /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI3         SIUL2.PGPDI[3].R              /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI4         SIUL2.PGPDI[4].R              /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI5         SIUL2.PGPDI[5].R              /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI6         SIUL2.PGPDI[6].R              /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI7         SIUL2.PGPDI[7].R              /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI8         SIUL2.PGPDI[8].R              /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI9         SIUL2.PGPDI[9].R              /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI10        SIUL2.PGPDI[10].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI11        SIUL2.PGPDI[11].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI12        SIUL2.PGPDI[12].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI13        SIUL2.PGPDI[13].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI14        SIUL2.PGPDI[14].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI15        SIUL2.PGPDI[15].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI16        SIUL2.PGPDI[16].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI17        SIUL2.PGPDI[17].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI18        SIUL2.PGPDI[18].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI19        SIUL2.PGPDI[19].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI20        SIUL2.PGPDI[20].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI21        SIUL2.PGPDI[21].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI22        SIUL2.PGPDI[22].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI23        SIUL2.PGPDI[23].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI24        SIUL2.PGPDI[24].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI25        SIUL2.PGPDI[25].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI26        SIUL2.PGPDI[26].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI27        SIUL2.PGPDI[27].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI28        SIUL2.PGPDI[28].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI29        SIUL2.PGPDI[29].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI30        SIUL2.PGPDI[30].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_PGPDI31        SIUL2.PGPDI[31].R             /* Parallel GPIO Pad Data In Register */
#define SIUL2_MPGPDO0        SIUL2.MPGPDO[0].R             /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO1        SIUL2.MPGPDO[1].R             /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO2        SIUL2.MPGPDO[2].R             /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO3        SIUL2.MPGPDO[3].R             /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO4        SIUL2.MPGPDO[4].R             /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO5        SIUL2.MPGPDO[5].R             /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO6        SIUL2.MPGPDO[6].R             /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO7        SIUL2.MPGPDO[7].R             /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO8        SIUL2.MPGPDO[8].R             /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO9        SIUL2.MPGPDO[9].R             /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO10       SIUL2.MPGPDO[10].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO11       SIUL2.MPGPDO[11].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO12       SIUL2.MPGPDO[12].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO13       SIUL2.MPGPDO[13].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO14       SIUL2.MPGPDO[14].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO15       SIUL2.MPGPDO[15].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO16       SIUL2.MPGPDO[16].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO17       SIUL2.MPGPDO[17].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO18       SIUL2.MPGPDO[18].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO19       SIUL2.MPGPDO[19].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO20       SIUL2.MPGPDO[20].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO21       SIUL2.MPGPDO[21].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO22       SIUL2.MPGPDO[22].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO23       SIUL2.MPGPDO[23].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO24       SIUL2.MPGPDO[24].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO25       SIUL2.MPGPDO[25].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO26       SIUL2.MPGPDO[26].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO27       SIUL2.MPGPDO[27].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO28       SIUL2.MPGPDO[28].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO29       SIUL2.MPGPDO[29].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO30       SIUL2.MPGPDO[30].R            /* Masked Parallel GPIO Pad Data Out Register */
#define SIUL2_MPGPDO31       SIUL2.MPGPDO[31].R            /* Masked Parallel GPIO Pad Data Out Register */

/* SMPU */
#define SMPU_0_CESR0         SMPU_0.CESR0.R                /* Control/Error Status Register 0 */
#define SMPU_0_CESR1         SMPU_0.CESR1.R                /* Control/Error Status Register 1 */
#define SMPU_0_EAR0          SMPU_0.ERROR[0].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_0_EDR0          SMPU_0.ERROR[0].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_0_EAR1          SMPU_0.ERROR[1].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_0_EDR1          SMPU_0.ERROR[1].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_0_EAR2          SMPU_0.ERROR[2].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_0_EDR2          SMPU_0.ERROR[2].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_0_EAR3          SMPU_0.ERROR[3].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_0_EDR3          SMPU_0.ERROR[3].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_0_EAR4          SMPU_0.ERROR[4].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_0_EDR4          SMPU_0.ERROR[4].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_0_EAR5          SMPU_0.ERROR[5].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_0_EDR5          SMPU_0.ERROR[5].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_0_EAR6          SMPU_0.ERROR[6].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_0_EDR6          SMPU_0.ERROR[6].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_0_EAR7          SMPU_0.ERROR[7].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_0_EDR7          SMPU_0.ERROR[7].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_0_EAR8          SMPU_0.ERROR[8].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_0_EDR8          SMPU_0.ERROR[8].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_0_EAR9          SMPU_0.ERROR[9].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_0_EDR9          SMPU_0.ERROR[9].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_0_EAR10         SMPU_0.ERROR[10].EAR.R        /* Error Address Register, Bus Master n */
#define SMPU_0_EDR10         SMPU_0.ERROR[10].EDR.R        /* Error Detail Register, Bus Master n */
#define SMPU_0_EAR11         SMPU_0.ERROR[11].EAR.R        /* Error Address Register, Bus Master n */
#define SMPU_0_EDR11         SMPU_0.ERROR[11].EDR.R        /* Error Detail Register, Bus Master n */
#define SMPU_0_EAR12         SMPU_0.ERROR[12].EAR.R        /* Error Address Register, Bus Master n */
#define SMPU_0_EDR12         SMPU_0.ERROR[12].EDR.R        /* Error Detail Register, Bus Master n */
#define SMPU_0_EAR13         SMPU_0.ERROR[13].EAR.R        /* Error Address Register, Bus Master n */
#define SMPU_0_EDR13         SMPU_0.ERROR[13].EDR.R        /* Error Detail Register, Bus Master n */
#define SMPU_0_EAR14         SMPU_0.ERROR[14].EAR.R        /* Error Address Register, Bus Master n */
#define SMPU_0_EDR14         SMPU_0.ERROR[14].EDR.R        /* Error Detail Register, Bus Master n */
#define SMPU_0_EAR15         SMPU_0.ERROR[15].EAR.R        /* Error Address Register, Bus Master n */
#define SMPU_0_EDR15         SMPU_0.ERROR[15].EDR.R        /* Error Detail Register, Bus Master n */
#define SMPU_0_RGD0_WORD0    SMPU_0.RGD[0].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_0_RGD0_WORD1    SMPU_0.RGD[0].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_0_RGD0_WORD2_FMT0 SMPU_0.RGD[0].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_0_RGD0_WORD3    SMPU_0.RGD[0].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_0_RGD1_WORD0    SMPU_0.RGD[1].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_0_RGD1_WORD1    SMPU_0.RGD[1].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_0_RGD1_WORD2_FMT0 SMPU_0.RGD[1].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_0_RGD1_WORD3    SMPU_0.RGD[1].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_0_RGD2_WORD0    SMPU_0.RGD[2].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_0_RGD2_WORD1    SMPU_0.RGD[2].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_0_RGD2_WORD2_FMT0 SMPU_0.RGD[2].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_0_RGD2_WORD3    SMPU_0.RGD[2].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_0_RGD3_WORD0    SMPU_0.RGD[3].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_0_RGD3_WORD1    SMPU_0.RGD[3].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_0_RGD3_WORD2_FMT0 SMPU_0.RGD[3].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_0_RGD3_WORD3    SMPU_0.RGD[3].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_0_RGD4_WORD0    SMPU_0.RGD[4].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_0_RGD4_WORD1    SMPU_0.RGD[4].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_0_RGD4_WORD2_FMT0 SMPU_0.RGD[4].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_0_RGD4_WORD3    SMPU_0.RGD[4].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_0_RGD5_WORD0    SMPU_0.RGD[5].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_0_RGD5_WORD1    SMPU_0.RGD[5].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_0_RGD5_WORD2_FMT0 SMPU_0.RGD[5].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_0_RGD5_WORD3    SMPU_0.RGD[5].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_0_RGD6_WORD0    SMPU_0.RGD[6].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_0_RGD6_WORD1    SMPU_0.RGD[6].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_0_RGD6_WORD2_FMT0 SMPU_0.RGD[6].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_0_RGD6_WORD3    SMPU_0.RGD[6].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_0_RGD7_WORD0    SMPU_0.RGD[7].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_0_RGD7_WORD1    SMPU_0.RGD[7].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_0_RGD7_WORD2_FMT0 SMPU_0.RGD[7].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_0_RGD7_WORD3    SMPU_0.RGD[7].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_0_RGD8_WORD0    SMPU_0.RGD[8].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_0_RGD8_WORD1    SMPU_0.RGD[8].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_0_RGD8_WORD2_FMT0 SMPU_0.RGD[8].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_0_RGD8_WORD3    SMPU_0.RGD[8].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_0_RGD9_WORD0    SMPU_0.RGD[9].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_0_RGD9_WORD1    SMPU_0.RGD[9].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_0_RGD9_WORD2_FMT0 SMPU_0.RGD[9].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_0_RGD9_WORD3    SMPU_0.RGD[9].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_0_RGD10_WORD0   SMPU_0.RGD[10].WORD0.R        /* Region Descriptor n, Word 0 */
#define SMPU_0_RGD10_WORD1   SMPU_0.RGD[10].WORD1.R        /* Region Descriptor n, Word 1 */
#define SMPU_0_RGD10_WORD2_FMT0 SMPU_0.RGD[10].WORD2.R     /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_0_RGD10_WORD3   SMPU_0.RGD[10].WORD3.R        /* Region Descriptor n, Word 3 */
#define SMPU_0_RGD11_WORD0   SMPU_0.RGD[11].WORD0.R        /* Region Descriptor n, Word 0 */
#define SMPU_0_RGD11_WORD1   SMPU_0.RGD[11].WORD1.R        /* Region Descriptor n, Word 1 */
#define SMPU_0_RGD11_WORD2_FMT0 SMPU_0.RGD[11].WORD2.R     /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_0_RGD11_WORD3   SMPU_0.RGD[11].WORD3.R        /* Region Descriptor n, Word 3 */

/* SMPU */
#define SMPU_1_CESR0         SMPU_1.CESR0.R                /* Control/Error Status Register 0 */
#define SMPU_1_CESR1         SMPU_1.CESR1.R                /* Control/Error Status Register 1 */
#define SMPU_1_EAR0          SMPU_1.ERROR[0].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_1_EDR0          SMPU_1.ERROR[0].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_1_EAR1          SMPU_1.ERROR[1].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_1_EDR1          SMPU_1.ERROR[1].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_1_EAR2          SMPU_1.ERROR[2].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_1_EDR2          SMPU_1.ERROR[2].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_1_EAR3          SMPU_1.ERROR[3].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_1_EDR3          SMPU_1.ERROR[3].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_1_EAR4          SMPU_1.ERROR[4].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_1_EDR4          SMPU_1.ERROR[4].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_1_EAR5          SMPU_1.ERROR[5].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_1_EDR5          SMPU_1.ERROR[5].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_1_EAR6          SMPU_1.ERROR[6].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_1_EDR6          SMPU_1.ERROR[6].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_1_EAR7          SMPU_1.ERROR[7].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_1_EDR7          SMPU_1.ERROR[7].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_1_EAR8          SMPU_1.ERROR[8].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_1_EDR8          SMPU_1.ERROR[8].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_1_EAR9          SMPU_1.ERROR[9].EAR.R         /* Error Address Register, Bus Master n */
#define SMPU_1_EDR9          SMPU_1.ERROR[9].EDR.R         /* Error Detail Register, Bus Master n */
#define SMPU_1_EAR10         SMPU_1.ERROR[10].EAR.R        /* Error Address Register, Bus Master n */
#define SMPU_1_EDR10         SMPU_1.ERROR[10].EDR.R        /* Error Detail Register, Bus Master n */
#define SMPU_1_EAR11         SMPU_1.ERROR[11].EAR.R        /* Error Address Register, Bus Master n */
#define SMPU_1_EDR11         SMPU_1.ERROR[11].EDR.R        /* Error Detail Register, Bus Master n */
#define SMPU_1_EAR12         SMPU_1.ERROR[12].EAR.R        /* Error Address Register, Bus Master n */
#define SMPU_1_EDR12         SMPU_1.ERROR[12].EDR.R        /* Error Detail Register, Bus Master n */
#define SMPU_1_EAR13         SMPU_1.ERROR[13].EAR.R        /* Error Address Register, Bus Master n */
#define SMPU_1_EDR13         SMPU_1.ERROR[13].EDR.R        /* Error Detail Register, Bus Master n */
#define SMPU_1_EAR14         SMPU_1.ERROR[14].EAR.R        /* Error Address Register, Bus Master n */
#define SMPU_1_EDR14         SMPU_1.ERROR[14].EDR.R        /* Error Detail Register, Bus Master n */
#define SMPU_1_EAR15         SMPU_1.ERROR[15].EAR.R        /* Error Address Register, Bus Master n */
#define SMPU_1_EDR15         SMPU_1.ERROR[15].EDR.R        /* Error Detail Register, Bus Master n */
#define SMPU_1_RGD0_WORD0    SMPU_1.RGD[0].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_1_RGD0_WORD1    SMPU_1.RGD[0].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_1_RGD0_WORD2_FMT0 SMPU_1.RGD[0].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_1_RGD0_WORD3    SMPU_1.RGD[0].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_1_RGD1_WORD0    SMPU_1.RGD[1].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_1_RGD1_WORD1    SMPU_1.RGD[1].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_1_RGD1_WORD2_FMT0 SMPU_1.RGD[1].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_1_RGD1_WORD3    SMPU_1.RGD[1].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_1_RGD2_WORD0    SMPU_1.RGD[2].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_1_RGD2_WORD1    SMPU_1.RGD[2].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_1_RGD2_WORD2_FMT0 SMPU_1.RGD[2].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_1_RGD2_WORD3    SMPU_1.RGD[2].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_1_RGD3_WORD0    SMPU_1.RGD[3].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_1_RGD3_WORD1    SMPU_1.RGD[3].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_1_RGD3_WORD2_FMT0 SMPU_1.RGD[3].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_1_RGD3_WORD3    SMPU_1.RGD[3].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_1_RGD4_WORD0    SMPU_1.RGD[4].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_1_RGD4_WORD1    SMPU_1.RGD[4].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_1_RGD4_WORD2_FMT0 SMPU_1.RGD[4].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_1_RGD4_WORD3    SMPU_1.RGD[4].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_1_RGD5_WORD0    SMPU_1.RGD[5].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_1_RGD5_WORD1    SMPU_1.RGD[5].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_1_RGD5_WORD2_FMT0 SMPU_1.RGD[5].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_1_RGD5_WORD3    SMPU_1.RGD[5].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_1_RGD6_WORD0    SMPU_1.RGD[6].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_1_RGD6_WORD1    SMPU_1.RGD[6].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_1_RGD6_WORD2_FMT0 SMPU_1.RGD[6].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_1_RGD6_WORD3    SMPU_1.RGD[6].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_1_RGD7_WORD0    SMPU_1.RGD[7].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_1_RGD7_WORD1    SMPU_1.RGD[7].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_1_RGD7_WORD2_FMT0 SMPU_1.RGD[7].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_1_RGD7_WORD3    SMPU_1.RGD[7].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_1_RGD8_WORD0    SMPU_1.RGD[8].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_1_RGD8_WORD1    SMPU_1.RGD[8].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_1_RGD8_WORD2_FMT0 SMPU_1.RGD[8].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_1_RGD8_WORD3    SMPU_1.RGD[8].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_1_RGD9_WORD0    SMPU_1.RGD[9].WORD0.R         /* Region Descriptor n, Word 0 */
#define SMPU_1_RGD9_WORD1    SMPU_1.RGD[9].WORD1.R         /* Region Descriptor n, Word 1 */
#define SMPU_1_RGD9_WORD2_FMT0 SMPU_1.RGD[9].WORD2.R       /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_1_RGD9_WORD3    SMPU_1.RGD[9].WORD3.R         /* Region Descriptor n, Word 3 */
#define SMPU_1_RGD10_WORD0   SMPU_1.RGD[10].WORD0.R        /* Region Descriptor n, Word 0 */
#define SMPU_1_RGD10_WORD1   SMPU_1.RGD[10].WORD1.R        /* Region Descriptor n, Word 1 */
#define SMPU_1_RGD10_WORD2_FMT0 SMPU_1.RGD[10].WORD2.R     /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_1_RGD10_WORD3   SMPU_1.RGD[10].WORD3.R        /* Region Descriptor n, Word 3 */
#define SMPU_1_RGD11_WORD0   SMPU_1.RGD[11].WORD0.R        /* Region Descriptor n, Word 0 */
#define SMPU_1_RGD11_WORD1   SMPU_1.RGD[11].WORD1.R        /* Region Descriptor n, Word 1 */
#define SMPU_1_RGD11_WORD2_FMT0 SMPU_1.RGD[11].WORD2.R     /* Region Descriptor n, Word 2 Format 0 */
#define SMPU_1_RGD11_WORD3   SMPU_1.RGD[11].WORD3.R        /* Region Descriptor n, Word 3 */

/* SRX */
#define SRX_0_GBL_CTRL       SRX_0.GBL_CTRL.R              /* Global Control Register */
#define SRX_0_CHNL_EN        SRX_0.CHNL_EN.R               /* Channel Enable Register */
#define SRX_0_GBL_STATUS     SRX_0.GBL_STATUS.R            /* Global Status Register */
#define SRX_0_FMSG_RDY       SRX_0.FMSG_RDY.R              /* Fast Message Ready Status Register */
#define SRX_0_SMSG_RDY       SRX_0.SMSG_RDY.R              /* Slow Serial Message Ready Status Register */
#define SRX_0_DATA_CTRL1     SRX_0.DATA_CTRL1.R            /* Data Control Register 1 */
#define SRX_0_FDMA_CTRL      SRX_0.FDMA_CTRL.R             /* Fast Message DMA Control Register */
#define SRX_0_SDMA_CTRL      SRX_0.SDMA_CTRL.R             /* Slow Serial Message DMA Control Register */
#define SRX_0_FRDY_IE        SRX_0.FRDY_IE.R               /* Fast Message Ready Interrupt Control Register */
#define SRX_0_SRDY_IE        SRX_0.SRDY_IE.R               /* Slow Serial Message Ready Interrupt Enable Register */
#define SRX_0_DMA_FMSG_DATA  SRX_0.DMA_FMSG_DATA.R         /* DMA Fast Message Data Read Register */
#define SRX_0_DMA_FMSG_CRC   SRX_0.DMA_FMSG_CRC.R          /* DMA Fast Message CRC Read Register */
#define SRX_0_DMA_FMSG_TS    SRX_0.DMA_FMSG_TS.R           /* DMA Fast Message Time Stamp Read Register */
#define SRX_0_DMA_SMSG_BIT3  SRX_0.DMA_SMSG_BIT3.R         /* DMA Slow Serial Message Bit3 Read Register */
#define SRX_0_DMA_SMSG_BIT2  SRX_0.DMA_SMSG_BIT2.R         /* DMA Slow Serial Message Bit2 Read Register */
#define SRX_0_DMA_SMSG_TS    SRX_0.DMA_SMSG_TS.R           /* DMA Slow Serial Message Time Stamp Read Register */
#define SRX_0_CH0_CLK_CTRL   SRX_0.CH[0].CLK_CTRL.R        /* Channel 'n' Clock Control Register (n = 0 to (CH-1)) */
#define SRX_0_CH0_STATUS     SRX_0.CH[0].STATUS.R          /* Channel 'n' Status Register (n=0 to (CH-1)) */
#define SRX_0_CH0_CONFIG     SRX_0.CH[0].CONFIG.R          /* Channel 'n' Configuration Register (n=0 to (CH-1)) */
#define SRX_0_CH1_CLK_CTRL   SRX_0.CH[1].CLK_CTRL.R        /* Channel 'n' Clock Control Register (n = 0 to (CH-1)) */
#define SRX_0_CH1_STATUS     SRX_0.CH[1].STATUS.R          /* Channel 'n' Status Register (n=0 to (CH-1)) */
#define SRX_0_CH1_CONFIG     SRX_0.CH[1].CONFIG.R          /* Channel 'n' Configuration Register (n=0 to (CH-1)) */
#define SRX_0_CH2_CLK_CTRL   SRX_0.CH[2].CLK_CTRL.R        /* Channel 'n' Clock Control Register (n = 0 to (CH-1)) */
#define SRX_0_CH2_STATUS     SRX_0.CH[2].STATUS.R          /* Channel 'n' Status Register (n=0 to (CH-1)) */
#define SRX_0_CH2_CONFIG     SRX_0.CH[2].CONFIG.R          /* Channel 'n' Configuration Register (n=0 to (CH-1)) */
#define SRX_0_CH3_CLK_CTRL   SRX_0.CH[3].CLK_CTRL.R        /* Channel 'n' Clock Control Register (n = 0 to (CH-1)) */
#define SRX_0_CH3_STATUS     SRX_0.CH[3].STATUS.R          /* Channel 'n' Status Register (n=0 to (CH-1)) */
#define SRX_0_CH3_CONFIG     SRX_0.CH[3].CONFIG.R          /* Channel 'n' Configuration Register (n=0 to (CH-1)) */
#define SRX_0_CH4_CLK_CTRL   SRX_0.CH[4].CLK_CTRL.R        /* Channel 'n' Clock Control Register (n = 0 to (CH-1)) */
#define SRX_0_CH4_STATUS     SRX_0.CH[4].STATUS.R          /* Channel 'n' Status Register (n=0 to (CH-1)) */
#define SRX_0_CH4_CONFIG     SRX_0.CH[4].CONFIG.R          /* Channel 'n' Configuration Register (n=0 to (CH-1)) */
#define SRX_0_CH5_CLK_CTRL   SRX_0.CH[5].CLK_CTRL.R        /* Channel 'n' Clock Control Register (n = 0 to (CH-1)) */
#define SRX_0_CH5_STATUS     SRX_0.CH[5].STATUS.R          /* Channel 'n' Status Register (n=0 to (CH-1)) */
#define SRX_0_CH5_CONFIG     SRX_0.CH[5].CONFIG.R          /* Channel 'n' Configuration Register (n=0 to (CH-1)) */
#define SRX_0_CH6_CLK_CTRL   SRX_0.CH[6].CLK_CTRL.R        /* Channel 'n' Clock Control Register (n = 0 to (CH-1)) */
#define SRX_0_CH6_STATUS     SRX_0.CH[6].STATUS.R          /* Channel 'n' Status Register (n=0 to (CH-1)) */
#define SRX_0_CH6_CONFIG     SRX_0.CH[6].CONFIG.R          /* Channel 'n' Configuration Register (n=0 to (CH-1)) */
#define SRX_0_CH7_CLK_CTRL   SRX_0.CH[7].CLK_CTRL.R        /* Channel 'n' Clock Control Register (n = 0 to (CH-1)) */
#define SRX_0_CH7_STATUS     SRX_0.CH[7].STATUS.R          /* Channel 'n' Status Register (n=0 to (CH-1)) */
#define SRX_0_CH7_CONFIG     SRX_0.CH[7].CONFIG.R          /* Channel 'n' Configuration Register (n=0 to (CH-1)) */
#define SRX_0_CH0_FMSG_DATA  SRX_0.CHANNEL[0].FMSG_DATA.R  /* Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)) */
#define SRX_0_CH0_FMSG_CRC   SRX_0.CHANNEL[0].FMSG_CRC.R   /* Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)) */
#define SRX_0_CH0_FMSG_TS    SRX_0.CHANNEL[0].FMSG_TS.R    /* Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_0_CH0_SMSG_BIT3  SRX_0.CHANNEL[0].SMSG_BIT3.R  /* Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)) */
#define SRX_0_CH0_SMSG_BIT2  SRX_0.CHANNEL[0].SMSG_BIT2.R  /* Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)) */
#define SRX_0_CH0_SMSG_TS    SRX_0.CHANNEL[0].SMSG_TS.R    /* Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_0_CH1_FMSG_DATA  SRX_0.CHANNEL[1].FMSG_DATA.R  /* Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)) */
#define SRX_0_CH1_FMSG_CRC   SRX_0.CHANNEL[1].FMSG_CRC.R   /* Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)) */
#define SRX_0_CH1_FMSG_TS    SRX_0.CHANNEL[1].FMSG_TS.R    /* Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_0_CH1_SMSG_BIT3  SRX_0.CHANNEL[1].SMSG_BIT3.R  /* Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)) */
#define SRX_0_CH1_SMSG_BIT2  SRX_0.CHANNEL[1].SMSG_BIT2.R  /* Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)) */
#define SRX_0_CH1_SMSG_TS    SRX_0.CHANNEL[1].SMSG_TS.R    /* Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_0_CH2_FMSG_DATA  SRX_0.CHANNEL[2].FMSG_DATA.R  /* Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)) */
#define SRX_0_CH2_FMSG_CRC   SRX_0.CHANNEL[2].FMSG_CRC.R   /* Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)) */
#define SRX_0_CH2_FMSG_TS    SRX_0.CHANNEL[2].FMSG_TS.R    /* Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_0_CH2_SMSG_BIT3  SRX_0.CHANNEL[2].SMSG_BIT3.R  /* Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)) */
#define SRX_0_CH2_SMSG_BIT2  SRX_0.CHANNEL[2].SMSG_BIT2.R  /* Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)) */
#define SRX_0_CH2_SMSG_TS    SRX_0.CHANNEL[2].SMSG_TS.R    /* Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_0_CH3_FMSG_DATA  SRX_0.CHANNEL[3].FMSG_DATA.R  /* Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)) */
#define SRX_0_CH3_FMSG_CRC   SRX_0.CHANNEL[3].FMSG_CRC.R   /* Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)) */
#define SRX_0_CH3_FMSG_TS    SRX_0.CHANNEL[3].FMSG_TS.R    /* Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_0_CH3_SMSG_BIT3  SRX_0.CHANNEL[3].SMSG_BIT3.R  /* Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)) */
#define SRX_0_CH3_SMSG_BIT2  SRX_0.CHANNEL[3].SMSG_BIT2.R  /* Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)) */
#define SRX_0_CH3_SMSG_TS    SRX_0.CHANNEL[3].SMSG_TS.R    /* Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_0_CH4_FMSG_DATA  SRX_0.CHANNEL[4].FMSG_DATA.R  /* Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)) */
#define SRX_0_CH4_FMSG_CRC   SRX_0.CHANNEL[4].FMSG_CRC.R   /* Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)) */
#define SRX_0_CH4_FMSG_TS    SRX_0.CHANNEL[4].FMSG_TS.R    /* Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_0_CH4_SMSG_BIT3  SRX_0.CHANNEL[4].SMSG_BIT3.R  /* Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)) */
#define SRX_0_CH4_SMSG_BIT2  SRX_0.CHANNEL[4].SMSG_BIT2.R  /* Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)) */
#define SRX_0_CH4_SMSG_TS    SRX_0.CHANNEL[4].SMSG_TS.R    /* Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_0_CH5_FMSG_DATA  SRX_0.CHANNEL[5].FMSG_DATA.R  /* Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)) */
#define SRX_0_CH5_FMSG_CRC   SRX_0.CHANNEL[5].FMSG_CRC.R   /* Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)) */
#define SRX_0_CH5_FMSG_TS    SRX_0.CHANNEL[5].FMSG_TS.R    /* Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_0_CH5_SMSG_BIT3  SRX_0.CHANNEL[5].SMSG_BIT3.R  /* Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)) */
#define SRX_0_CH5_SMSG_BIT2  SRX_0.CHANNEL[5].SMSG_BIT2.R  /* Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)) */
#define SRX_0_CH5_SMSG_TS    SRX_0.CHANNEL[5].SMSG_TS.R    /* Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_0_CH6_FMSG_DATA  SRX_0.CHANNEL[6].FMSG_DATA.R  /* Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)) */
#define SRX_0_CH6_FMSG_CRC   SRX_0.CHANNEL[6].FMSG_CRC.R   /* Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)) */
#define SRX_0_CH6_FMSG_TS    SRX_0.CHANNEL[6].FMSG_TS.R    /* Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_0_CH6_SMSG_BIT3  SRX_0.CHANNEL[6].SMSG_BIT3.R  /* Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)) */
#define SRX_0_CH6_SMSG_BIT2  SRX_0.CHANNEL[6].SMSG_BIT2.R  /* Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)) */
#define SRX_0_CH6_SMSG_TS    SRX_0.CHANNEL[6].SMSG_TS.R    /* Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_0_CH7_FMSG_DATA  SRX_0.CHANNEL[7].FMSG_DATA.R  /* Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)) */
#define SRX_0_CH7_FMSG_CRC   SRX_0.CHANNEL[7].FMSG_CRC.R   /* Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)) */
#define SRX_0_CH7_FMSG_TS    SRX_0.CHANNEL[7].FMSG_TS.R    /* Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_0_CH7_SMSG_BIT3  SRX_0.CHANNEL[7].SMSG_BIT3.R  /* Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)) */
#define SRX_0_CH7_SMSG_BIT2  SRX_0.CHANNEL[7].SMSG_BIT2.R  /* Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)) */
#define SRX_0_CH7_SMSG_TS    SRX_0.CHANNEL[7].SMSG_TS.R    /* Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)) */

/* SRX */
#define SRX_1_GBL_CTRL       SRX_1.GBL_CTRL.R              /* Global Control Register */
#define SRX_1_CHNL_EN        SRX_1.CHNL_EN.R               /* Channel Enable Register */
#define SRX_1_GBL_STATUS     SRX_1.GBL_STATUS.R            /* Global Status Register */
#define SRX_1_FMSG_RDY       SRX_1.FMSG_RDY.R              /* Fast Message Ready Status Register */
#define SRX_1_SMSG_RDY       SRX_1.SMSG_RDY.R              /* Slow Serial Message Ready Status Register */
#define SRX_1_DATA_CTRL1     SRX_1.DATA_CTRL1.R            /* Data Control Register 1 */
#define SRX_1_FDMA_CTRL      SRX_1.FDMA_CTRL.R             /* Fast Message DMA Control Register */
#define SRX_1_SDMA_CTRL      SRX_1.SDMA_CTRL.R             /* Slow Serial Message DMA Control Register */
#define SRX_1_FRDY_IE        SRX_1.FRDY_IE.R               /* Fast Message Ready Interrupt Control Register */
#define SRX_1_SRDY_IE        SRX_1.SRDY_IE.R               /* Slow Serial Message Ready Interrupt Enable Register */
#define SRX_1_DMA_FMSG_DATA  SRX_1.DMA_FMSG_DATA.R         /* DMA Fast Message Data Read Register */
#define SRX_1_DMA_FMSG_CRC   SRX_1.DMA_FMSG_CRC.R          /* DMA Fast Message CRC Read Register */
#define SRX_1_DMA_FMSG_TS    SRX_1.DMA_FMSG_TS.R           /* DMA Fast Message Time Stamp Read Register */
#define SRX_1_DMA_SMSG_BIT3  SRX_1.DMA_SMSG_BIT3.R         /* DMA Slow Serial Message Bit3 Read Register */
#define SRX_1_DMA_SMSG_BIT2  SRX_1.DMA_SMSG_BIT2.R         /* DMA Slow Serial Message Bit2 Read Register */
#define SRX_1_DMA_SMSG_TS    SRX_1.DMA_SMSG_TS.R           /* DMA Slow Serial Message Time Stamp Read Register */
#define SRX_1_CH0_CLK_CTRL   SRX_1.CH[0].CLK_CTRL.R        /* Channel 'n' Clock Control Register (n = 0 to (CH-1)) */
#define SRX_1_CH0_STATUS     SRX_1.CH[0].STATUS.R          /* Channel 'n' Status Register (n=0 to (CH-1)) */
#define SRX_1_CH0_CONFIG     SRX_1.CH[0].CONFIG.R          /* Channel 'n' Configuration Register (n=0 to (CH-1)) */
#define SRX_1_CH1_CLK_CTRL   SRX_1.CH[1].CLK_CTRL.R        /* Channel 'n' Clock Control Register (n = 0 to (CH-1)) */
#define SRX_1_CH1_STATUS     SRX_1.CH[1].STATUS.R          /* Channel 'n' Status Register (n=0 to (CH-1)) */
#define SRX_1_CH1_CONFIG     SRX_1.CH[1].CONFIG.R          /* Channel 'n' Configuration Register (n=0 to (CH-1)) */
#define SRX_1_CH2_CLK_CTRL   SRX_1.CH[2].CLK_CTRL.R        /* Channel 'n' Clock Control Register (n = 0 to (CH-1)) */
#define SRX_1_CH2_STATUS     SRX_1.CH[2].STATUS.R          /* Channel 'n' Status Register (n=0 to (CH-1)) */
#define SRX_1_CH2_CONFIG     SRX_1.CH[2].CONFIG.R          /* Channel 'n' Configuration Register (n=0 to (CH-1)) */
#define SRX_1_CH3_CLK_CTRL   SRX_1.CH[3].CLK_CTRL.R        /* Channel 'n' Clock Control Register (n = 0 to (CH-1)) */
#define SRX_1_CH3_STATUS     SRX_1.CH[3].STATUS.R          /* Channel 'n' Status Register (n=0 to (CH-1)) */
#define SRX_1_CH3_CONFIG     SRX_1.CH[3].CONFIG.R          /* Channel 'n' Configuration Register (n=0 to (CH-1)) */
#define SRX_1_CH4_CLK_CTRL   SRX_1.CH[4].CLK_CTRL.R        /* Channel 'n' Clock Control Register (n = 0 to (CH-1)) */
#define SRX_1_CH4_STATUS     SRX_1.CH[4].STATUS.R          /* Channel 'n' Status Register (n=0 to (CH-1)) */
#define SRX_1_CH4_CONFIG     SRX_1.CH[4].CONFIG.R          /* Channel 'n' Configuration Register (n=0 to (CH-1)) */
#define SRX_1_CH5_CLK_CTRL   SRX_1.CH[5].CLK_CTRL.R        /* Channel 'n' Clock Control Register (n = 0 to (CH-1)) */
#define SRX_1_CH5_STATUS     SRX_1.CH[5].STATUS.R          /* Channel 'n' Status Register (n=0 to (CH-1)) */
#define SRX_1_CH5_CONFIG     SRX_1.CH[5].CONFIG.R          /* Channel 'n' Configuration Register (n=0 to (CH-1)) */
#define SRX_1_CH6_CLK_CTRL   SRX_1.CH[6].CLK_CTRL.R        /* Channel 'n' Clock Control Register (n = 0 to (CH-1)) */
#define SRX_1_CH6_STATUS     SRX_1.CH[6].STATUS.R          /* Channel 'n' Status Register (n=0 to (CH-1)) */
#define SRX_1_CH6_CONFIG     SRX_1.CH[6].CONFIG.R          /* Channel 'n' Configuration Register (n=0 to (CH-1)) */
#define SRX_1_CH7_CLK_CTRL   SRX_1.CH[7].CLK_CTRL.R        /* Channel 'n' Clock Control Register (n = 0 to (CH-1)) */
#define SRX_1_CH7_STATUS     SRX_1.CH[7].STATUS.R          /* Channel 'n' Status Register (n=0 to (CH-1)) */
#define SRX_1_CH7_CONFIG     SRX_1.CH[7].CONFIG.R          /* Channel 'n' Configuration Register (n=0 to (CH-1)) */
#define SRX_1_CH0_FMSG_DATA  SRX_1.CHANNEL[0].FMSG_DATA.R  /* Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)) */
#define SRX_1_CH0_FMSG_CRC   SRX_1.CHANNEL[0].FMSG_CRC.R   /* Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)) */
#define SRX_1_CH0_FMSG_TS    SRX_1.CHANNEL[0].FMSG_TS.R    /* Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_1_CH0_SMSG_BIT3  SRX_1.CHANNEL[0].SMSG_BIT3.R  /* Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)) */
#define SRX_1_CH0_SMSG_BIT2  SRX_1.CHANNEL[0].SMSG_BIT2.R  /* Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)) */
#define SRX_1_CH0_SMSG_TS    SRX_1.CHANNEL[0].SMSG_TS.R    /* Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_1_CH1_FMSG_DATA  SRX_1.CHANNEL[1].FMSG_DATA.R  /* Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)) */
#define SRX_1_CH1_FMSG_CRC   SRX_1.CHANNEL[1].FMSG_CRC.R   /* Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)) */
#define SRX_1_CH1_FMSG_TS    SRX_1.CHANNEL[1].FMSG_TS.R    /* Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_1_CH1_SMSG_BIT3  SRX_1.CHANNEL[1].SMSG_BIT3.R  /* Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)) */
#define SRX_1_CH1_SMSG_BIT2  SRX_1.CHANNEL[1].SMSG_BIT2.R  /* Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)) */
#define SRX_1_CH1_SMSG_TS    SRX_1.CHANNEL[1].SMSG_TS.R    /* Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_1_CH2_FMSG_DATA  SRX_1.CHANNEL[2].FMSG_DATA.R  /* Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)) */
#define SRX_1_CH2_FMSG_CRC   SRX_1.CHANNEL[2].FMSG_CRC.R   /* Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)) */
#define SRX_1_CH2_FMSG_TS    SRX_1.CHANNEL[2].FMSG_TS.R    /* Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_1_CH2_SMSG_BIT3  SRX_1.CHANNEL[2].SMSG_BIT3.R  /* Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)) */
#define SRX_1_CH2_SMSG_BIT2  SRX_1.CHANNEL[2].SMSG_BIT2.R  /* Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)) */
#define SRX_1_CH2_SMSG_TS    SRX_1.CHANNEL[2].SMSG_TS.R    /* Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_1_CH3_FMSG_DATA  SRX_1.CHANNEL[3].FMSG_DATA.R  /* Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)) */
#define SRX_1_CH3_FMSG_CRC   SRX_1.CHANNEL[3].FMSG_CRC.R   /* Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)) */
#define SRX_1_CH3_FMSG_TS    SRX_1.CHANNEL[3].FMSG_TS.R    /* Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_1_CH3_SMSG_BIT3  SRX_1.CHANNEL[3].SMSG_BIT3.R  /* Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)) */
#define SRX_1_CH3_SMSG_BIT2  SRX_1.CHANNEL[3].SMSG_BIT2.R  /* Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)) */
#define SRX_1_CH3_SMSG_TS    SRX_1.CHANNEL[3].SMSG_TS.R    /* Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_1_CH4_FMSG_DATA  SRX_1.CHANNEL[4].FMSG_DATA.R  /* Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)) */
#define SRX_1_CH4_FMSG_CRC   SRX_1.CHANNEL[4].FMSG_CRC.R   /* Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)) */
#define SRX_1_CH4_FMSG_TS    SRX_1.CHANNEL[4].FMSG_TS.R    /* Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_1_CH4_SMSG_BIT3  SRX_1.CHANNEL[4].SMSG_BIT3.R  /* Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)) */
#define SRX_1_CH4_SMSG_BIT2  SRX_1.CHANNEL[4].SMSG_BIT2.R  /* Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)) */
#define SRX_1_CH4_SMSG_TS    SRX_1.CHANNEL[4].SMSG_TS.R    /* Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_1_CH5_FMSG_DATA  SRX_1.CHANNEL[5].FMSG_DATA.R  /* Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)) */
#define SRX_1_CH5_FMSG_CRC   SRX_1.CHANNEL[5].FMSG_CRC.R   /* Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)) */
#define SRX_1_CH5_FMSG_TS    SRX_1.CHANNEL[5].FMSG_TS.R    /* Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_1_CH5_SMSG_BIT3  SRX_1.CHANNEL[5].SMSG_BIT3.R  /* Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)) */
#define SRX_1_CH5_SMSG_BIT2  SRX_1.CHANNEL[5].SMSG_BIT2.R  /* Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)) */
#define SRX_1_CH5_SMSG_TS    SRX_1.CHANNEL[5].SMSG_TS.R    /* Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_1_CH6_FMSG_DATA  SRX_1.CHANNEL[6].FMSG_DATA.R  /* Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)) */
#define SRX_1_CH6_FMSG_CRC   SRX_1.CHANNEL[6].FMSG_CRC.R   /* Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)) */
#define SRX_1_CH6_FMSG_TS    SRX_1.CHANNEL[6].FMSG_TS.R    /* Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_1_CH6_SMSG_BIT3  SRX_1.CHANNEL[6].SMSG_BIT3.R  /* Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)) */
#define SRX_1_CH6_SMSG_BIT2  SRX_1.CHANNEL[6].SMSG_BIT2.R  /* Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)) */
#define SRX_1_CH6_SMSG_TS    SRX_1.CHANNEL[6].SMSG_TS.R    /* Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_1_CH7_FMSG_DATA  SRX_1.CHANNEL[7].FMSG_DATA.R  /* Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)) */
#define SRX_1_CH7_FMSG_CRC   SRX_1.CHANNEL[7].FMSG_CRC.R   /* Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)) */
#define SRX_1_CH7_FMSG_TS    SRX_1.CHANNEL[7].FMSG_TS.R    /* Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)) */
#define SRX_1_CH7_SMSG_BIT3  SRX_1.CHANNEL[7].SMSG_BIT3.R  /* Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)) */
#define SRX_1_CH7_SMSG_BIT2  SRX_1.CHANNEL[7].SMSG_BIT2.R  /* Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)) */
#define SRX_1_CH7_SMSG_TS    SRX_1.CHANNEL[7].SMSG_TS.R    /* Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)) */

/* SSCM */
#define SSCM_STATUS          SSCM.STATUS.R                 /* SSCM System Status */
#define SSCM_MEMCONFIG       SSCM.MEMCONFIG.R              /* SSCM System Memory and ID Register */
#define SSCM_ERROR           SSCM.ERROR.R                  /* SSCM Error Configuration Register */
#define SSCM_UOPS            SSCM.UOPS.R                   /* SSCM HSM and User Option Status Register */
#define SSCM_PSA             SSCM.PSA.R                    /* Processor Start Address Register */
#define SSCM_HSA             SSCM.HSA.R                    /* SSCM HSM Start Address Register */
#define SSCM_LCSTAT          SSCM.LCSTAT.R                 /* Life Cycle Status Register */

/* STCU2 */
#define STCU2_RUN            STCU2.RUN.R                   /* STCU2 Run Register */
#define STCU2_RUNSW          STCU2.RUNSW.R                 /* STCU2 Run Software Register */
#define STCU2_SKC            STCU2.SKC.R                   /* STCU2 SK Code Register */
#define STCU2_CFG            STCU2.CFG.R                   /* STCU2 Configuration Register */
#define STCU2_PLL_CFG        STCU2.PLL_CFG.R               /* STCU2 PLL Configuration Register */
#define STCU2_WDG            STCU2.WDG.R                   /* STCU2 Watchdog Register Granularity */
#define STCU2_INT_FLG        STCU2.INT_FLG.R               /* STCU2 Interrupt Flag Register */
#define STCU2_CRCE           STCU2.CRCE.R                  /* STCU2 CRC Expected Status Register */
#define STCU2_CRCR           STCU2.CRCR.R                  /* STCU2 CRC Read Status Register */
#define STCU2_ERR_STAT       STCU2.ERR_STAT.R              /* STCU2 Error Register */
#define STCU2_ERR_FM         STCU2.ERR_FM.R                /* STCU2 Error FM Register */
#define STCU2_LBS            STCU2.LBS.R                   /* STCU2 Off-Line LBIST Status Register */
#define STCU2_LBE            STCU2.LBE.R                   /* STCU2 Off-Line LBIST End Flag Register */
#define STCU2_LBSSW          STCU2.LBSSW.R                 /* STCU2 On-Line LBIST Status Register */
#define STCU2_LBESW          STCU2.LBESW.R                 /* STCU2 On-Line LBIST End Flag Register */
#define STCU2_LBRMSW         STCU2.LBRMSW.R                /* STCU2 On-Line LBIST Reset Management */
#define STCU2_LBUFM          STCU2.LBUFM.R                 /* STCU2 LBIST Unrecoverable FM Register */
#define STCU2_MBSL           STCU2.MBSL.R                  /* STCU2 Off-Line MBIST Status Low Register */
#define STCU2_MBSM           STCU2.MBSM.R                  /* STCU2 Off-Line MBIST Status Medium Register */
#define STCU2_MBSH           STCU2.MBSH.R                  /* STCU2 Off-Line MBIST Status High Register */
#define STCU2_MBEL           STCU2.MBEL.R                  /* STCU2 Off-Line MBIST End Flag Low Register */
#define STCU2_MBEM           STCU2.MBEM.R                  /* STCU2 Off-Line MBIST End Flag Medium Register */
#define STCU2_MBEH           STCU2.MBEH.R                  /* STCU2 Off-Line MBIST End Flag High Register */
#define STCU2_MBSLSW         STCU2.MBSLSW.R                /* STCU2 On-Line MBIST Status Low Register */
#define STCU2_MBSMSW         STCU2.MBSMSW.R                /* STCU2 On-Line MBIST Status Medium Register */
#define STCU2_MBSHSW         STCU2.MBSHSW.R                /* STCU2 On-Line MBIST Status High Register */
#define STCU2_MBELSW         STCU2.MBELSW.R                /* STCU2 On-Line MBIST End Flag Low Register */
#define STCU2_MBEMSW         STCU2.MBEMSW.R                /* STCU2 On-Line MBIST End Flag Medium Register */
#define STCU2_MBEHSW         STCU2.MBEHSW.R                /* STCU2 On-Line MBIST End Flag High Register */
#define STCU2_MBUFML         STCU2.MBUFML.R                /* STCU2 MBIST Unrecoverable FM Low Register */
#define STCU2_MBUFMM         STCU2.MBUFMM.R                /* STCU2 MBIST Unrecoverable FM Medium Register */
#define STCU2_MBUFMH         STCU2.MBUFMH.R                /* STCU2 MBIST Unrecoverable FM High Register */
#define STCU2_LB_CTRL0       STCU2.LB[0].LB_CTRL.R         /* STCU2 LBIST Control Register */
#define STCU2_LB_PCS0        STCU2.LB[0].LB_PCS.R          /* STCU2 LBIST PC Stop Register */
#define STCU2_LB_PRPGL0      STCU2.LB[0].LB_PRPGL.R        /* STCU2 LBIST PRPG Low Register */
#define STCU2_LB_PRPGH0      STCU2.LB[0].LB_PRPGH.R        /* STCU2 LBIST PRPG High Register */
#define STCU2_LB_MISREL0     STCU2.LB[0].LB_MISREL.R       /* STCU2 Off-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREH0     STCU2.LB[0].LB_MISREH.R       /* STCU2 Off-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRL0     STCU2.LB[0].LB_MISRRL.R       /* STCU2 Off-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRH0     STCU2.LB[0].LB_MISRRH.R       /* STCU2 Off-Line LBIST MISR Read High Register */
#define STCU2_LB_MISRELSW0   STCU2.LB[0].LB_MISRELSW.R     /* STCU2 On-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREHSW0   STCU2.LB[0].LB_MISREHSW.R     /* STCU2 On-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRLSW0   STCU2.LB[0].LB_MISRRLSW.R     /* STCU2 On-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRHSW0   STCU2.LB[0].LB_MISRRHSW.R     /* STCU2 On-Line LBIST MISR Read High Register */
#define STCU2_LB_CTRL1       STCU2.LB[1].LB_CTRL.R         /* STCU2 LBIST Control Register */
#define STCU2_LB_PCS1        STCU2.LB[1].LB_PCS.R          /* STCU2 LBIST PC Stop Register */
#define STCU2_LB_PRPGL1      STCU2.LB[1].LB_PRPGL.R        /* STCU2 LBIST PRPG Low Register */
#define STCU2_LB_PRPGH1      STCU2.LB[1].LB_PRPGH.R        /* STCU2 LBIST PRPG High Register */
#define STCU2_LB_MISREL1     STCU2.LB[1].LB_MISREL.R       /* STCU2 Off-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREH1     STCU2.LB[1].LB_MISREH.R       /* STCU2 Off-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRL1     STCU2.LB[1].LB_MISRRL.R       /* STCU2 Off-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRH1     STCU2.LB[1].LB_MISRRH.R       /* STCU2 Off-Line LBIST MISR Read High Register */
#define STCU2_LB_MISRELSW1   STCU2.LB[1].LB_MISRELSW.R     /* STCU2 On-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREHSW1   STCU2.LB[1].LB_MISREHSW.R     /* STCU2 On-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRLSW1   STCU2.LB[1].LB_MISRRLSW.R     /* STCU2 On-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRHSW1   STCU2.LB[1].LB_MISRRHSW.R     /* STCU2 On-Line LBIST MISR Read High Register */
#define STCU2_LB_CTRL2       STCU2.LB[2].LB_CTRL.R         /* STCU2 LBIST Control Register */
#define STCU2_LB_PCS2        STCU2.LB[2].LB_PCS.R          /* STCU2 LBIST PC Stop Register */
#define STCU2_LB_PRPGL2      STCU2.LB[2].LB_PRPGL.R        /* STCU2 LBIST PRPG Low Register */
#define STCU2_LB_PRPGH2      STCU2.LB[2].LB_PRPGH.R        /* STCU2 LBIST PRPG High Register */
#define STCU2_LB_MISREL2     STCU2.LB[2].LB_MISREL.R       /* STCU2 Off-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREH2     STCU2.LB[2].LB_MISREH.R       /* STCU2 Off-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRL2     STCU2.LB[2].LB_MISRRL.R       /* STCU2 Off-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRH2     STCU2.LB[2].LB_MISRRH.R       /* STCU2 Off-Line LBIST MISR Read High Register */
#define STCU2_LB_MISRELSW2   STCU2.LB[2].LB_MISRELSW.R     /* STCU2 On-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREHSW2   STCU2.LB[2].LB_MISREHSW.R     /* STCU2 On-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRLSW2   STCU2.LB[2].LB_MISRRLSW.R     /* STCU2 On-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRHSW2   STCU2.LB[2].LB_MISRRHSW.R     /* STCU2 On-Line LBIST MISR Read High Register */
#define STCU2_LB_CTRL3       STCU2.LB[3].LB_CTRL.R         /* STCU2 LBIST Control Register */
#define STCU2_LB_PCS3        STCU2.LB[3].LB_PCS.R          /* STCU2 LBIST PC Stop Register */
#define STCU2_LB_PRPGL3      STCU2.LB[3].LB_PRPGL.R        /* STCU2 LBIST PRPG Low Register */
#define STCU2_LB_PRPGH3      STCU2.LB[3].LB_PRPGH.R        /* STCU2 LBIST PRPG High Register */
#define STCU2_LB_MISREL3     STCU2.LB[3].LB_MISREL.R       /* STCU2 Off-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREH3     STCU2.LB[3].LB_MISREH.R       /* STCU2 Off-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRL3     STCU2.LB[3].LB_MISRRL.R       /* STCU2 Off-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRH3     STCU2.LB[3].LB_MISRRH.R       /* STCU2 Off-Line LBIST MISR Read High Register */
#define STCU2_LB_MISRELSW3   STCU2.LB[3].LB_MISRELSW.R     /* STCU2 On-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREHSW3   STCU2.LB[3].LB_MISREHSW.R     /* STCU2 On-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRLSW3   STCU2.LB[3].LB_MISRRLSW.R     /* STCU2 On-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRHSW3   STCU2.LB[3].LB_MISRRHSW.R     /* STCU2 On-Line LBIST MISR Read High Register */
#define STCU2_LB_CTRL4       STCU2.LB[4].LB_CTRL.R         /* STCU2 LBIST Control Register */
#define STCU2_LB_PCS4        STCU2.LB[4].LB_PCS.R          /* STCU2 LBIST PC Stop Register */
#define STCU2_LB_PRPGL4      STCU2.LB[4].LB_PRPGL.R        /* STCU2 LBIST PRPG Low Register */
#define STCU2_LB_PRPGH4      STCU2.LB[4].LB_PRPGH.R        /* STCU2 LBIST PRPG High Register */
#define STCU2_LB_MISREL4     STCU2.LB[4].LB_MISREL.R       /* STCU2 Off-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREH4     STCU2.LB[4].LB_MISREH.R       /* STCU2 Off-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRL4     STCU2.LB[4].LB_MISRRL.R       /* STCU2 Off-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRH4     STCU2.LB[4].LB_MISRRH.R       /* STCU2 Off-Line LBIST MISR Read High Register */
#define STCU2_LB_MISRELSW4   STCU2.LB[4].LB_MISRELSW.R     /* STCU2 On-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREHSW4   STCU2.LB[4].LB_MISREHSW.R     /* STCU2 On-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRLSW4   STCU2.LB[4].LB_MISRRLSW.R     /* STCU2 On-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRHSW4   STCU2.LB[4].LB_MISRRHSW.R     /* STCU2 On-Line LBIST MISR Read High Register */
#define STCU2_LB_CTRL5       STCU2.LB[5].LB_CTRL.R         /* STCU2 LBIST Control Register */
#define STCU2_LB_PCS5        STCU2.LB[5].LB_PCS.R          /* STCU2 LBIST PC Stop Register */
#define STCU2_LB_PRPGL5      STCU2.LB[5].LB_PRPGL.R        /* STCU2 LBIST PRPG Low Register */
#define STCU2_LB_PRPGH5      STCU2.LB[5].LB_PRPGH.R        /* STCU2 LBIST PRPG High Register */
#define STCU2_LB_MISREL5     STCU2.LB[5].LB_MISREL.R       /* STCU2 Off-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREH5     STCU2.LB[5].LB_MISREH.R       /* STCU2 Off-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRL5     STCU2.LB[5].LB_MISRRL.R       /* STCU2 Off-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRH5     STCU2.LB[5].LB_MISRRH.R       /* STCU2 Off-Line LBIST MISR Read High Register */
#define STCU2_LB_MISRELSW5   STCU2.LB[5].LB_MISRELSW.R     /* STCU2 On-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREHSW5   STCU2.LB[5].LB_MISREHSW.R     /* STCU2 On-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRLSW5   STCU2.LB[5].LB_MISRRLSW.R     /* STCU2 On-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRHSW5   STCU2.LB[5].LB_MISRRHSW.R     /* STCU2 On-Line LBIST MISR Read High Register */
#define STCU2_LB_CTRL6       STCU2.LB[6].LB_CTRL.R         /* STCU2 LBIST Control Register */
#define STCU2_LB_PCS6        STCU2.LB[6].LB_PCS.R          /* STCU2 LBIST PC Stop Register */
#define STCU2_LB_PRPGL6      STCU2.LB[6].LB_PRPGL.R        /* STCU2 LBIST PRPG Low Register */
#define STCU2_LB_PRPGH6      STCU2.LB[6].LB_PRPGH.R        /* STCU2 LBIST PRPG High Register */
#define STCU2_LB_MISREL6     STCU2.LB[6].LB_MISREL.R       /* STCU2 Off-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREH6     STCU2.LB[6].LB_MISREH.R       /* STCU2 Off-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRL6     STCU2.LB[6].LB_MISRRL.R       /* STCU2 Off-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRH6     STCU2.LB[6].LB_MISRRH.R       /* STCU2 Off-Line LBIST MISR Read High Register */
#define STCU2_LB_MISRELSW6   STCU2.LB[6].LB_MISRELSW.R     /* STCU2 On-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREHSW6   STCU2.LB[6].LB_MISREHSW.R     /* STCU2 On-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRLSW6   STCU2.LB[6].LB_MISRRLSW.R     /* STCU2 On-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRHSW6   STCU2.LB[6].LB_MISRRHSW.R     /* STCU2 On-Line LBIST MISR Read High Register */
#define STCU2_LB_CTRL7       STCU2.LB[7].LB_CTRL.R         /* STCU2 LBIST Control Register */
#define STCU2_LB_PCS7        STCU2.LB[7].LB_PCS.R          /* STCU2 LBIST PC Stop Register */
#define STCU2_LB_PRPGL7      STCU2.LB[7].LB_PRPGL.R        /* STCU2 LBIST PRPG Low Register */
#define STCU2_LB_PRPGH7      STCU2.LB[7].LB_PRPGH.R        /* STCU2 LBIST PRPG High Register */
#define STCU2_LB_MISREL7     STCU2.LB[7].LB_MISREL.R       /* STCU2 Off-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREH7     STCU2.LB[7].LB_MISREH.R       /* STCU2 Off-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRL7     STCU2.LB[7].LB_MISRRL.R       /* STCU2 Off-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRH7     STCU2.LB[7].LB_MISRRH.R       /* STCU2 Off-Line LBIST MISR Read High Register */
#define STCU2_LB_MISRELSW7   STCU2.LB[7].LB_MISRELSW.R     /* STCU2 On-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREHSW7   STCU2.LB[7].LB_MISREHSW.R     /* STCU2 On-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRLSW7   STCU2.LB[7].LB_MISRRLSW.R     /* STCU2 On-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRHSW7   STCU2.LB[7].LB_MISRRHSW.R     /* STCU2 On-Line LBIST MISR Read High Register */
#define STCU2_LB_CTRL8       STCU2.LB[8].LB_CTRL.R         /* STCU2 LBIST Control Register */
#define STCU2_LB_PCS8        STCU2.LB[8].LB_PCS.R          /* STCU2 LBIST PC Stop Register */
#define STCU2_LB_PRPGL8      STCU2.LB[8].LB_PRPGL.R        /* STCU2 LBIST PRPG Low Register */
#define STCU2_LB_PRPGH8      STCU2.LB[8].LB_PRPGH.R        /* STCU2 LBIST PRPG High Register */
#define STCU2_LB_MISREL8     STCU2.LB[8].LB_MISREL.R       /* STCU2 Off-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREH8     STCU2.LB[8].LB_MISREH.R       /* STCU2 Off-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRL8     STCU2.LB[8].LB_MISRRL.R       /* STCU2 Off-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRH8     STCU2.LB[8].LB_MISRRH.R       /* STCU2 Off-Line LBIST MISR Read High Register */
#define STCU2_LB_MISRELSW8   STCU2.LB[8].LB_MISRELSW.R     /* STCU2 On-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREHSW8   STCU2.LB[8].LB_MISREHSW.R     /* STCU2 On-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRLSW8   STCU2.LB[8].LB_MISRRLSW.R     /* STCU2 On-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRHSW8   STCU2.LB[8].LB_MISRRHSW.R     /* STCU2 On-Line LBIST MISR Read High Register */
#define STCU2_LB_CTRL9       STCU2.LB[9].LB_CTRL.R         /* STCU2 LBIST Control Register */
#define STCU2_LB_PCS9        STCU2.LB[9].LB_PCS.R          /* STCU2 LBIST PC Stop Register */
#define STCU2_LB_PRPGL9      STCU2.LB[9].LB_PRPGL.R        /* STCU2 LBIST PRPG Low Register */
#define STCU2_LB_PRPGH9      STCU2.LB[9].LB_PRPGH.R        /* STCU2 LBIST PRPG High Register */
#define STCU2_LB_MISREL9     STCU2.LB[9].LB_MISREL.R       /* STCU2 Off-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREH9     STCU2.LB[9].LB_MISREH.R       /* STCU2 Off-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRL9     STCU2.LB[9].LB_MISRRL.R       /* STCU2 Off-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRH9     STCU2.LB[9].LB_MISRRH.R       /* STCU2 Off-Line LBIST MISR Read High Register */
#define STCU2_LB_MISRELSW9   STCU2.LB[9].LB_MISRELSW.R     /* STCU2 On-Line LBIST MISR Expected Low Register */
#define STCU2_LB_MISREHSW9   STCU2.LB[9].LB_MISREHSW.R     /* STCU2 On-Line LBIST MISR Expected High Register */
#define STCU2_LB_MISRRLSW9   STCU2.LB[9].LB_MISRRLSW.R     /* STCU2 On-Line LBIST MISR Read Low Register */
#define STCU2_LB_MISRRHSW9   STCU2.LB[9].LB_MISRRHSW.R     /* STCU2 On-Line LBIST MISR Read High Register */
#define STCU2_MB_CTRL0       STCU2.MB_CTRL[0].R            /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL1       STCU2.MB_CTRL[1].R            /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL2       STCU2.MB_CTRL[2].R            /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL3       STCU2.MB_CTRL[3].R            /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL4       STCU2.MB_CTRL[4].R            /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL5       STCU2.MB_CTRL[5].R            /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL6       STCU2.MB_CTRL[6].R            /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL7       STCU2.MB_CTRL[7].R            /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL8       STCU2.MB_CTRL[8].R            /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL9       STCU2.MB_CTRL[9].R            /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL10      STCU2.MB_CTRL[10].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL11      STCU2.MB_CTRL[11].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL12      STCU2.MB_CTRL[12].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL13      STCU2.MB_CTRL[13].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL14      STCU2.MB_CTRL[14].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL15      STCU2.MB_CTRL[15].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL16      STCU2.MB_CTRL[16].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL17      STCU2.MB_CTRL[17].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL18      STCU2.MB_CTRL[18].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL19      STCU2.MB_CTRL[19].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL20      STCU2.MB_CTRL[20].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL21      STCU2.MB_CTRL[21].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL22      STCU2.MB_CTRL[22].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL23      STCU2.MB_CTRL[23].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL24      STCU2.MB_CTRL[24].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL25      STCU2.MB_CTRL[25].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL26      STCU2.MB_CTRL[26].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL27      STCU2.MB_CTRL[27].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL28      STCU2.MB_CTRL[28].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL29      STCU2.MB_CTRL[29].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL30      STCU2.MB_CTRL[30].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL31      STCU2.MB_CTRL[31].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL32      STCU2.MB_CTRL[32].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL33      STCU2.MB_CTRL[33].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL34      STCU2.MB_CTRL[34].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL35      STCU2.MB_CTRL[35].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL36      STCU2.MB_CTRL[36].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL37      STCU2.MB_CTRL[37].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL38      STCU2.MB_CTRL[38].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL39      STCU2.MB_CTRL[39].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL40      STCU2.MB_CTRL[40].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL41      STCU2.MB_CTRL[41].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL42      STCU2.MB_CTRL[42].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL43      STCU2.MB_CTRL[43].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL44      STCU2.MB_CTRL[44].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL45      STCU2.MB_CTRL[45].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL46      STCU2.MB_CTRL[46].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL47      STCU2.MB_CTRL[47].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL48      STCU2.MB_CTRL[48].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL49      STCU2.MB_CTRL[49].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL50      STCU2.MB_CTRL[50].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL51      STCU2.MB_CTRL[51].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL52      STCU2.MB_CTRL[52].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL53      STCU2.MB_CTRL[53].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL54      STCU2.MB_CTRL[54].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL55      STCU2.MB_CTRL[55].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL56      STCU2.MB_CTRL[56].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL57      STCU2.MB_CTRL[57].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL58      STCU2.MB_CTRL[58].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL59      STCU2.MB_CTRL[59].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL60      STCU2.MB_CTRL[60].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL61      STCU2.MB_CTRL[61].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL62      STCU2.MB_CTRL[62].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL63      STCU2.MB_CTRL[63].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL64      STCU2.MB_CTRL[64].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL65      STCU2.MB_CTRL[65].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL66      STCU2.MB_CTRL[66].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL67      STCU2.MB_CTRL[67].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL68      STCU2.MB_CTRL[68].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL69      STCU2.MB_CTRL[69].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL70      STCU2.MB_CTRL[70].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL71      STCU2.MB_CTRL[71].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL72      STCU2.MB_CTRL[72].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL73      STCU2.MB_CTRL[73].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL74      STCU2.MB_CTRL[74].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL75      STCU2.MB_CTRL[75].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL76      STCU2.MB_CTRL[76].R           /* STCU2 MBIST Control Register */
#define STCU2_MB_CTRL77      STCU2.MB_CTRL[77].R           /* STCU2 MBIST Control Register */

/* STM */
#define STM_0_CR             STM_0.CR.R                    /* STM Control Register */
#define STM_0_CNT            STM_0.CNT.R                   /* STM Count Register */
#define STM_0_CCR0           STM_0.CHANNEL[0].CCR.R        /* STM Channel Control Register */
#define STM_0_CIR0           STM_0.CHANNEL[0].CIR.R        /* STM Channel Interrupt Register */
#define STM_0_CMP0           STM_0.CHANNEL[0].CMP.R        /* STM Channel Compare Register */
#define STM_0_CCR1           STM_0.CHANNEL[1].CCR.R        /* STM Channel Control Register */
#define STM_0_CIR1           STM_0.CHANNEL[1].CIR.R        /* STM Channel Interrupt Register */
#define STM_0_CMP1           STM_0.CHANNEL[1].CMP.R        /* STM Channel Compare Register */
#define STM_0_CCR2           STM_0.CHANNEL[2].CCR.R        /* STM Channel Control Register */
#define STM_0_CIR2           STM_0.CHANNEL[2].CIR.R        /* STM Channel Interrupt Register */
#define STM_0_CMP2           STM_0.CHANNEL[2].CMP.R        /* STM Channel Compare Register */
#define STM_0_CCR3           STM_0.CHANNEL[3].CCR.R        /* STM Channel Control Register */
#define STM_0_CIR3           STM_0.CHANNEL[3].CIR.R        /* STM Channel Interrupt Register */
#define STM_0_CMP3           STM_0.CHANNEL[3].CMP.R        /* STM Channel Compare Register */

/* STM */
#define STM_1_CR             STM_1.CR.R                    /* STM Control Register */
#define STM_1_CNT            STM_1.CNT.R                   /* STM Count Register */
#define STM_1_CCR0           STM_1.CHANNEL[0].CCR.R        /* STM Channel Control Register */
#define STM_1_CIR0           STM_1.CHANNEL[0].CIR.R        /* STM Channel Interrupt Register */
#define STM_1_CMP0           STM_1.CHANNEL[0].CMP.R        /* STM Channel Compare Register */
#define STM_1_CCR1           STM_1.CHANNEL[1].CCR.R        /* STM Channel Control Register */
#define STM_1_CIR1           STM_1.CHANNEL[1].CIR.R        /* STM Channel Interrupt Register */
#define STM_1_CMP1           STM_1.CHANNEL[1].CMP.R        /* STM Channel Compare Register */
#define STM_1_CCR2           STM_1.CHANNEL[2].CCR.R        /* STM Channel Control Register */
#define STM_1_CIR2           STM_1.CHANNEL[2].CIR.R        /* STM Channel Interrupt Register */
#define STM_1_CMP2           STM_1.CHANNEL[2].CMP.R        /* STM Channel Compare Register */
#define STM_1_CCR3           STM_1.CHANNEL[3].CCR.R        /* STM Channel Control Register */
#define STM_1_CIR3           STM_1.CHANNEL[3].CIR.R        /* STM Channel Interrupt Register */
#define STM_1_CMP3           STM_1.CHANNEL[3].CMP.R        /* STM Channel Compare Register */

/* STM */
#define STM_2_CR             STM_2.CR.R                    /* STM Control Register */
#define STM_2_CNT            STM_2.CNT.R                   /* STM Count Register */
#define STM_2_CCR0           STM_2.CHANNEL[0].CCR.R        /* STM Channel Control Register */
#define STM_2_CIR0           STM_2.CHANNEL[0].CIR.R        /* STM Channel Interrupt Register */
#define STM_2_CMP0           STM_2.CHANNEL[0].CMP.R        /* STM Channel Compare Register */
#define STM_2_CCR1           STM_2.CHANNEL[1].CCR.R        /* STM Channel Control Register */
#define STM_2_CIR1           STM_2.CHANNEL[1].CIR.R        /* STM Channel Interrupt Register */
#define STM_2_CMP1           STM_2.CHANNEL[1].CMP.R        /* STM Channel Compare Register */
#define STM_2_CCR2           STM_2.CHANNEL[2].CCR.R        /* STM Channel Control Register */
#define STM_2_CIR2           STM_2.CHANNEL[2].CIR.R        /* STM Channel Interrupt Register */
#define STM_2_CMP2           STM_2.CHANNEL[2].CMP.R        /* STM Channel Compare Register */
#define STM_2_CCR3           STM_2.CHANNEL[3].CCR.R        /* STM Channel Control Register */
#define STM_2_CIR3           STM_2.CHANNEL[3].CIR.R        /* STM Channel Interrupt Register */
#define STM_2_CMP3           STM_2.CHANNEL[3].CMP.R        /* STM Channel Compare Register */

/* SWT */
#define SWT_0_CR             SWT_0.CR.R                    /* SWT Control Register */
#define SWT_0_IR             SWT_0.IR.R                    /* SWT Interrupt Register */
#define SWT_0_TO             SWT_0.TO.R                    /* SWT Time-out Register */
#define SWT_0_WN             SWT_0.WN.R                    /* SWT Window Register */
#define SWT_0_SR             SWT_0.SR.R                    /* SWT Service Register */
#define SWT_0_CO             SWT_0.CO.R                    /* SWT Counter Output Register */
#define SWT_0_SK             SWT_0.SK.R                    /* SWT Service Key Register */

/* SWT */
#define SWT_1_CR             SWT_1.CR.R                    /* SWT Control Register */
#define SWT_1_IR             SWT_1.IR.R                    /* SWT Interrupt Register */
#define SWT_1_TO             SWT_1.TO.R                    /* SWT Time-out Register */
#define SWT_1_WN             SWT_1.WN.R                    /* SWT Window Register */
#define SWT_1_SR             SWT_1.SR.R                    /* SWT Service Register */
#define SWT_1_CO             SWT_1.CO.R                    /* SWT Counter Output Register */
#define SWT_1_SK             SWT_1.SK.R                    /* SWT Service Key Register */

/* SWT */
#define SWT_2_CR             SWT_2.CR.R                    /* SWT Control Register */
#define SWT_2_IR             SWT_2.IR.R                    /* SWT Interrupt Register */
#define SWT_2_TO             SWT_2.TO.R                    /* SWT Time-out Register */
#define SWT_2_WN             SWT_2.WN.R                    /* SWT Window Register */
#define SWT_2_SR             SWT_2.SR.R                    /* SWT Service Register */
#define SWT_2_CO             SWT_2.CO.R                    /* SWT Counter Output Register */
#define SWT_2_SK             SWT_2.SK.R                    /* SWT Service Key Register */

/* SWT */
#define SWT_3_CR             SWT_3.CR.R                    /* SWT Control Register */
#define SWT_3_IR             SWT_3.IR.R                    /* SWT Interrupt Register */
#define SWT_3_TO             SWT_3.TO.R                    /* SWT Time-out Register */
#define SWT_3_WN             SWT_3.WN.R                    /* SWT Window Register */
#define SWT_3_SR             SWT_3.SR.R                    /* SWT Service Register */
#define SWT_3_CO             SWT_3.CO.R                    /* SWT Counter Output Register */
#define SWT_3_SK             SWT_3.SK.R                    /* SWT Service Key Register */

/* TDM */
#define TDM_TDRSR            TDM.TDRSR.R                   /* TDR Status Register */
#define TDM_LFPAR            TDM.LFPAR.R                   /* Last Flash Programmed Address Register */
#define TDM_DBA              TDM.DBA.R                     /* Diary Base Address */
#define TDM_STO_KEY0         TDM.STO_KEY[0].R              /* Software Tamper Override Key Region */
#define TDM_STO_KEY1         TDM.STO_KEY[1].R              /* Software Tamper Override Key Region */
#define TDM_STO_KEY2         TDM.STO_KEY[2].R              /* Software Tamper Override Key Region */
#define TDM_STO_KEY3         TDM.STO_KEY[3].R              /* Software Tamper Override Key Region */
#define TDM_STO_KEY4         TDM.STO_KEY[4].R              /* Software Tamper Override Key Region */
#define TDM_STO_KEY5         TDM.STO_KEY[5].R              /* Software Tamper Override Key Region */

/* WKPU */
#define WKPU_NSR             WKPU.NSR.R                    /* NMI Status Flag Register */
#define WKPU_NCR             WKPU.NCR.R                    /* NMI Configuration Register */

/* XBAR */
#define XBAR_0_PRS0          XBAR_0.PORT[0].PRS.R          /* XBAR Priority Registers Slave */
#define XBAR_0_CRS0          XBAR_0.PORT[0].CRS.R          /* XBAR Control Register */
#define XBAR_0_PRS1          XBAR_0.PORT[1].PRS.R          /* XBAR Priority Registers Slave */
#define XBAR_0_CRS1          XBAR_0.PORT[1].CRS.R          /* XBAR Control Register */
#define XBAR_0_PRS2          XBAR_0.PORT[2].PRS.R          /* XBAR Priority Registers Slave */
#define XBAR_0_CRS2          XBAR_0.PORT[2].CRS.R          /* XBAR Control Register */
#define XBAR_0_PRS3          XBAR_0.PORT[3].PRS.R          /* XBAR Priority Registers Slave */
#define XBAR_0_CRS3          XBAR_0.PORT[3].CRS.R          /* XBAR Control Register */
#define XBAR_0_PRS4          XBAR_0.PORT[4].PRS.R          /* XBAR Priority Registers Slave */
#define XBAR_0_CRS4          XBAR_0.PORT[4].CRS.R          /* XBAR Control Register */
#define XBAR_0_PRS5          XBAR_0.PORT[5].PRS.R          /* XBAR Priority Registers Slave */
#define XBAR_0_CRS5          XBAR_0.PORT[5].CRS.R          /* XBAR Control Register */
#define XBAR_0_PRS6          XBAR_0.PORT[6].PRS.R          /* XBAR Priority Registers Slave */
#define XBAR_0_CRS6          XBAR_0.PORT[6].CRS.R          /* XBAR Control Register */
#define XBAR_0_PRS7          XBAR_0.PORT[7].PRS.R          /* XBAR Priority Registers Slave */
#define XBAR_0_CRS7          XBAR_0.PORT[7].CRS.R          /* XBAR Control Register */

/* XBAR */
#define XBAR_1_PRS0          XBAR_1.PORT[0].PRS.R          /* XBAR Priority Registers Slave */
#define XBAR_1_CRS0          XBAR_1.PORT[0].CRS.R          /* XBAR Control Register */
#define XBAR_1_PRS1          XBAR_1.PORT[1].PRS.R          /* XBAR Priority Registers Slave */
#define XBAR_1_CRS1          XBAR_1.PORT[1].CRS.R          /* XBAR Control Register */
#define XBAR_1_PRS2          XBAR_1.PORT[2].PRS.R          /* XBAR Priority Registers Slave */
#define XBAR_1_CRS2          XBAR_1.PORT[2].CRS.R          /* XBAR Control Register */
#define XBAR_1_PRS3          XBAR_1.PORT[3].PRS.R          /* XBAR Priority Registers Slave */
#define XBAR_1_CRS3          XBAR_1.PORT[3].CRS.R          /* XBAR Control Register */
#define XBAR_1_PRS4          XBAR_1.PORT[4].PRS.R          /* XBAR Priority Registers Slave */
#define XBAR_1_CRS4          XBAR_1.PORT[4].CRS.R          /* XBAR Control Register */
#define XBAR_1_PRS5          XBAR_1.PORT[5].PRS.R          /* XBAR Priority Registers Slave */
#define XBAR_1_CRS5          XBAR_1.PORT[5].CRS.R          /* XBAR Control Register */
#define XBAR_1_PRS6          XBAR_1.PORT[6].PRS.R          /* XBAR Priority Registers Slave */
#define XBAR_1_CRS6          XBAR_1.PORT[6].CRS.R          /* XBAR Control Register */
#define XBAR_1_PRS7          XBAR_1.PORT[7].PRS.R          /* XBAR Priority Registers Slave */
#define XBAR_1_CRS7          XBAR_1.PORT[7].CRS.R          /* XBAR Control Register */

/* XBIC */
#define XBIC_0_MCR           XBIC_0.MCR.R                  /* XBIC Module Control Register */
#define XBIC_0_EIR           XBIC_0.EIR.R                  /* XBIC Error Injection Register */
#define XBIC_0_ESR           XBIC_0.ESR.R                  /* XBIC Error Status Register */
#define XBIC_0_EAR           XBIC_0.EAR.R                  /* XBIC Error Address Register */

/* XBIC */
#define XBIC_1_MCR           XBIC_1.MCR.R                  /* XBIC Module Control Register */
#define XBIC_1_EIR           XBIC_1.EIR.R                  /* XBIC Error Injection Register */
#define XBIC_1_ESR           XBIC_1.ESR.R                  /* XBIC Error Status Register */
#define XBIC_1_EAR           XBIC_1.EAR.R                  /* XBIC Error Address Register */

/* XOSC */
#define XOSC_CTL             XOSC.CTL.R                    /* XOSC Control Register */

/* eDMA */
#define eDMA_0_CR            eDMA_0.CR.R                   /* Control Register */
#define eDMA_0_ES            eDMA_0.ES.R                   /* Error Status */
#define eDMA_0_ERQH          eDMA_0.ERQH.R                 /* Enable Request Register High */
#define eDMA_0_ERQL          eDMA_0.ERQL.R                 /* Enable Request Register Low */
#define eDMA_0_EEIH          eDMA_0.EEIH.R                 /* Enable Error Interrupt Register High */
#define eDMA_0_EEIL          eDMA_0.EEIL.R                 /* Enable Error Interrupt Register Low */
#define eDMA_0_SERQ          eDMA_0.SERQ.R                 /* Set Enable Request Register */
#define eDMA_0_CERQ          eDMA_0.CERQ.R                 /* Clear Enable Request Register */
#define eDMA_0_SEEI          eDMA_0.SEEI.R                 /* Set Enable Error Interrupt Register */
#define eDMA_0_CEEI          eDMA_0.CEEI.R                 /* Clear Enable Error Interrupt Register */
#define eDMA_0_CINT          eDMA_0.CINT.R                 /* Clear Interrupt Request Register */
#define eDMA_0_CERR          eDMA_0.CERR.R                 /* Clear Error Register */
#define eDMA_0_SSRT          eDMA_0.SSRT.R                 /* Set START Bit Register */
#define eDMA_0_CDNE          eDMA_0.CDNE.R                 /* Clear DONE Status Bit Register */
#define eDMA_0_INTH          eDMA_0.INTH.R                 /* Interrupt Request Register High */
#define eDMA_0_INTL          eDMA_0.INTL.R                 /* Interrupt Request Register Low */
#define eDMA_0_ERRH          eDMA_0.ERRH.R                 /* Error Register High */
#define eDMA_0_ERRL          eDMA_0.ERRL.R                 /* Error Register Low */
#define eDMA_0_HRSH          eDMA_0.HRSH.R                 /* Hardware Request Status Register High */
#define eDMA_0_HRSL          eDMA_0.HRSL.R                 /* Hardware Request Status Register Low */
#define eDMA_0_DCHPRI0       eDMA_0.DCHPRI[0].R            /* Channel Priority Register */
#define eDMA_0_DCHPRI1       eDMA_0.DCHPRI[1].R            /* Channel Priority Register */
#define eDMA_0_DCHPRI2       eDMA_0.DCHPRI[2].R            /* Channel Priority Register */
#define eDMA_0_DCHPRI3       eDMA_0.DCHPRI[3].R            /* Channel Priority Register */
#define eDMA_0_DCHPRI4       eDMA_0.DCHPRI[4].R            /* Channel Priority Register */
#define eDMA_0_DCHPRI5       eDMA_0.DCHPRI[5].R            /* Channel Priority Register */
#define eDMA_0_DCHPRI6       eDMA_0.DCHPRI[6].R            /* Channel Priority Register */
#define eDMA_0_DCHPRI7       eDMA_0.DCHPRI[7].R            /* Channel Priority Register */
#define eDMA_0_DCHPRI8       eDMA_0.DCHPRI[8].R            /* Channel Priority Register */
#define eDMA_0_DCHPRI9       eDMA_0.DCHPRI[9].R            /* Channel Priority Register */
#define eDMA_0_DCHPRI10      eDMA_0.DCHPRI[10].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI11      eDMA_0.DCHPRI[11].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI12      eDMA_0.DCHPRI[12].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI13      eDMA_0.DCHPRI[13].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI14      eDMA_0.DCHPRI[14].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI15      eDMA_0.DCHPRI[15].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI16      eDMA_0.DCHPRI[16].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI17      eDMA_0.DCHPRI[17].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI18      eDMA_0.DCHPRI[18].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI19      eDMA_0.DCHPRI[19].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI20      eDMA_0.DCHPRI[20].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI21      eDMA_0.DCHPRI[21].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI22      eDMA_0.DCHPRI[22].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI23      eDMA_0.DCHPRI[23].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI24      eDMA_0.DCHPRI[24].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI25      eDMA_0.DCHPRI[25].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI26      eDMA_0.DCHPRI[26].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI27      eDMA_0.DCHPRI[27].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI28      eDMA_0.DCHPRI[28].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI29      eDMA_0.DCHPRI[29].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI30      eDMA_0.DCHPRI[30].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI31      eDMA_0.DCHPRI[31].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI32      eDMA_0.DCHPRI[32].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI33      eDMA_0.DCHPRI[33].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI34      eDMA_0.DCHPRI[34].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI35      eDMA_0.DCHPRI[35].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI36      eDMA_0.DCHPRI[36].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI37      eDMA_0.DCHPRI[37].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI38      eDMA_0.DCHPRI[38].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI39      eDMA_0.DCHPRI[39].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI40      eDMA_0.DCHPRI[40].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI41      eDMA_0.DCHPRI[41].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI42      eDMA_0.DCHPRI[42].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI43      eDMA_0.DCHPRI[43].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI44      eDMA_0.DCHPRI[44].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI45      eDMA_0.DCHPRI[45].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI46      eDMA_0.DCHPRI[46].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI47      eDMA_0.DCHPRI[47].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI48      eDMA_0.DCHPRI[48].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI49      eDMA_0.DCHPRI[49].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI50      eDMA_0.DCHPRI[50].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI51      eDMA_0.DCHPRI[51].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI52      eDMA_0.DCHPRI[52].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI53      eDMA_0.DCHPRI[53].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI54      eDMA_0.DCHPRI[54].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI55      eDMA_0.DCHPRI[55].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI56      eDMA_0.DCHPRI[56].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI57      eDMA_0.DCHPRI[57].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI58      eDMA_0.DCHPRI[58].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI59      eDMA_0.DCHPRI[59].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI60      eDMA_0.DCHPRI[60].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI61      eDMA_0.DCHPRI[61].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI62      eDMA_0.DCHPRI[62].R           /* Channel Priority Register */
#define eDMA_0_DCHPRI63      eDMA_0.DCHPRI[63].R           /* Channel Priority Register */
#define eDMA_0_DCHMID0       eDMA_0.DCHMID[0].R            /* Channel Master ID Register */
#define eDMA_0_DCHMID1       eDMA_0.DCHMID[1].R            /* Channel Master ID Register */
#define eDMA_0_DCHMID2       eDMA_0.DCHMID[2].R            /* Channel Master ID Register */
#define eDMA_0_DCHMID3       eDMA_0.DCHMID[3].R            /* Channel Master ID Register */
#define eDMA_0_DCHMID4       eDMA_0.DCHMID[4].R            /* Channel Master ID Register */
#define eDMA_0_DCHMID5       eDMA_0.DCHMID[5].R            /* Channel Master ID Register */
#define eDMA_0_DCHMID6       eDMA_0.DCHMID[6].R            /* Channel Master ID Register */
#define eDMA_0_DCHMID7       eDMA_0.DCHMID[7].R            /* Channel Master ID Register */
#define eDMA_0_DCHMID8       eDMA_0.DCHMID[8].R            /* Channel Master ID Register */
#define eDMA_0_DCHMID9       eDMA_0.DCHMID[9].R            /* Channel Master ID Register */
#define eDMA_0_DCHMID10      eDMA_0.DCHMID[10].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID11      eDMA_0.DCHMID[11].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID12      eDMA_0.DCHMID[12].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID13      eDMA_0.DCHMID[13].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID14      eDMA_0.DCHMID[14].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID15      eDMA_0.DCHMID[15].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID16      eDMA_0.DCHMID[16].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID17      eDMA_0.DCHMID[17].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID18      eDMA_0.DCHMID[18].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID19      eDMA_0.DCHMID[19].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID20      eDMA_0.DCHMID[20].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID21      eDMA_0.DCHMID[21].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID22      eDMA_0.DCHMID[22].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID23      eDMA_0.DCHMID[23].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID24      eDMA_0.DCHMID[24].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID25      eDMA_0.DCHMID[25].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID26      eDMA_0.DCHMID[26].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID27      eDMA_0.DCHMID[27].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID28      eDMA_0.DCHMID[28].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID29      eDMA_0.DCHMID[29].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID30      eDMA_0.DCHMID[30].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID31      eDMA_0.DCHMID[31].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID32      eDMA_0.DCHMID[32].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID33      eDMA_0.DCHMID[33].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID34      eDMA_0.DCHMID[34].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID35      eDMA_0.DCHMID[35].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID36      eDMA_0.DCHMID[36].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID37      eDMA_0.DCHMID[37].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID38      eDMA_0.DCHMID[38].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID39      eDMA_0.DCHMID[39].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID40      eDMA_0.DCHMID[40].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID41      eDMA_0.DCHMID[41].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID42      eDMA_0.DCHMID[42].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID43      eDMA_0.DCHMID[43].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID44      eDMA_0.DCHMID[44].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID45      eDMA_0.DCHMID[45].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID46      eDMA_0.DCHMID[46].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID47      eDMA_0.DCHMID[47].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID48      eDMA_0.DCHMID[48].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID49      eDMA_0.DCHMID[49].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID50      eDMA_0.DCHMID[50].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID51      eDMA_0.DCHMID[51].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID52      eDMA_0.DCHMID[52].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID53      eDMA_0.DCHMID[53].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID54      eDMA_0.DCHMID[54].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID55      eDMA_0.DCHMID[55].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID56      eDMA_0.DCHMID[56].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID57      eDMA_0.DCHMID[57].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID58      eDMA_0.DCHMID[58].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID59      eDMA_0.DCHMID[59].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID60      eDMA_0.DCHMID[60].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID61      eDMA_0.DCHMID[61].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID62      eDMA_0.DCHMID[62].R           /* Channel Master ID Register */
#define eDMA_0_DCHMID63      eDMA_0.DCHMID[63].R           /* Channel Master ID Register */
#define eDMA_0_TCD0_SADDR    eDMA_0.TCD[0].SADDR.R         /* TCD Source Address */
#define eDMA_0_TCD0_ATTR     eDMA_0.TCD[0].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_0_TCD0_SOFF     eDMA_0.TCD[0].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_0_TCD0_NBYTES_MLNO eDMA_0.TCD[0].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD0_NBYTES_MLOFFNO eDMA_0.TCD[0].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD0_NBYTES_MLOFFYES eDMA_0.TCD[0].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD0_SLAST    eDMA_0.TCD[0].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD0_DADDR    eDMA_0.TCD[0].DADDR.R         /* TCD Destination Address */
#define eDMA_0_TCD0_CITER_ELINKNO eDMA_0.TCD[0].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD0_CITER_ELINKYES eDMA_0.TCD[0].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD0_DOFF     eDMA_0.TCD[0].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD0_DLASTSGA eDMA_0.TCD[0].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD0_BITER_ELINKNO eDMA_0.TCD[0].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD0_BITER_ELINKYES eDMA_0.TCD[0].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD0_CSR      eDMA_0.TCD[0].CSR.R           /* TCD Control and Status */
#define eDMA_0_TCD1_SADDR    eDMA_0.TCD[1].SADDR.R         /* TCD Source Address */
#define eDMA_0_TCD1_ATTR     eDMA_0.TCD[1].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_0_TCD1_SOFF     eDMA_0.TCD[1].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_0_TCD1_NBYTES_MLNO eDMA_0.TCD[1].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD1_NBYTES_MLOFFNO eDMA_0.TCD[1].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD1_NBYTES_MLOFFYES eDMA_0.TCD[1].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD1_SLAST    eDMA_0.TCD[1].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD1_DADDR    eDMA_0.TCD[1].DADDR.R         /* TCD Destination Address */
#define eDMA_0_TCD1_CITER_ELINKNO eDMA_0.TCD[1].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD1_CITER_ELINKYES eDMA_0.TCD[1].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD1_DOFF     eDMA_0.TCD[1].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD1_DLASTSGA eDMA_0.TCD[1].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD1_BITER_ELINKNO eDMA_0.TCD[1].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD1_BITER_ELINKYES eDMA_0.TCD[1].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD1_CSR      eDMA_0.TCD[1].CSR.R           /* TCD Control and Status */
#define eDMA_0_TCD2_SADDR    eDMA_0.TCD[2].SADDR.R         /* TCD Source Address */
#define eDMA_0_TCD2_ATTR     eDMA_0.TCD[2].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_0_TCD2_SOFF     eDMA_0.TCD[2].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_0_TCD2_NBYTES_MLNO eDMA_0.TCD[2].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD2_NBYTES_MLOFFNO eDMA_0.TCD[2].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD2_NBYTES_MLOFFYES eDMA_0.TCD[2].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD2_SLAST    eDMA_0.TCD[2].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD2_DADDR    eDMA_0.TCD[2].DADDR.R         /* TCD Destination Address */
#define eDMA_0_TCD2_CITER_ELINKNO eDMA_0.TCD[2].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD2_CITER_ELINKYES eDMA_0.TCD[2].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD2_DOFF     eDMA_0.TCD[2].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD2_DLASTSGA eDMA_0.TCD[2].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD2_BITER_ELINKNO eDMA_0.TCD[2].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD2_BITER_ELINKYES eDMA_0.TCD[2].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD2_CSR      eDMA_0.TCD[2].CSR.R           /* TCD Control and Status */
#define eDMA_0_TCD3_SADDR    eDMA_0.TCD[3].SADDR.R         /* TCD Source Address */
#define eDMA_0_TCD3_ATTR     eDMA_0.TCD[3].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_0_TCD3_SOFF     eDMA_0.TCD[3].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_0_TCD3_NBYTES_MLNO eDMA_0.TCD[3].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD3_NBYTES_MLOFFNO eDMA_0.TCD[3].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD3_NBYTES_MLOFFYES eDMA_0.TCD[3].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD3_SLAST    eDMA_0.TCD[3].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD3_DADDR    eDMA_0.TCD[3].DADDR.R         /* TCD Destination Address */
#define eDMA_0_TCD3_CITER_ELINKNO eDMA_0.TCD[3].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD3_CITER_ELINKYES eDMA_0.TCD[3].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD3_DOFF     eDMA_0.TCD[3].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD3_DLASTSGA eDMA_0.TCD[3].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD3_BITER_ELINKNO eDMA_0.TCD[3].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD3_BITER_ELINKYES eDMA_0.TCD[3].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD3_CSR      eDMA_0.TCD[3].CSR.R           /* TCD Control and Status */
#define eDMA_0_TCD4_SADDR    eDMA_0.TCD[4].SADDR.R         /* TCD Source Address */
#define eDMA_0_TCD4_ATTR     eDMA_0.TCD[4].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_0_TCD4_SOFF     eDMA_0.TCD[4].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_0_TCD4_NBYTES_MLNO eDMA_0.TCD[4].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD4_NBYTES_MLOFFNO eDMA_0.TCD[4].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD4_NBYTES_MLOFFYES eDMA_0.TCD[4].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD4_SLAST    eDMA_0.TCD[4].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD4_DADDR    eDMA_0.TCD[4].DADDR.R         /* TCD Destination Address */
#define eDMA_0_TCD4_CITER_ELINKNO eDMA_0.TCD[4].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD4_CITER_ELINKYES eDMA_0.TCD[4].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD4_DOFF     eDMA_0.TCD[4].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD4_DLASTSGA eDMA_0.TCD[4].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD4_BITER_ELINKNO eDMA_0.TCD[4].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD4_BITER_ELINKYES eDMA_0.TCD[4].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD4_CSR      eDMA_0.TCD[4].CSR.R           /* TCD Control and Status */
#define eDMA_0_TCD5_SADDR    eDMA_0.TCD[5].SADDR.R         /* TCD Source Address */
#define eDMA_0_TCD5_ATTR     eDMA_0.TCD[5].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_0_TCD5_SOFF     eDMA_0.TCD[5].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_0_TCD5_NBYTES_MLNO eDMA_0.TCD[5].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD5_NBYTES_MLOFFNO eDMA_0.TCD[5].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD5_NBYTES_MLOFFYES eDMA_0.TCD[5].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD5_SLAST    eDMA_0.TCD[5].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD5_DADDR    eDMA_0.TCD[5].DADDR.R         /* TCD Destination Address */
#define eDMA_0_TCD5_CITER_ELINKNO eDMA_0.TCD[5].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD5_CITER_ELINKYES eDMA_0.TCD[5].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD5_DOFF     eDMA_0.TCD[5].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD5_DLASTSGA eDMA_0.TCD[5].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD5_BITER_ELINKNO eDMA_0.TCD[5].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD5_BITER_ELINKYES eDMA_0.TCD[5].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD5_CSR      eDMA_0.TCD[5].CSR.R           /* TCD Control and Status */
#define eDMA_0_TCD6_SADDR    eDMA_0.TCD[6].SADDR.R         /* TCD Source Address */
#define eDMA_0_TCD6_ATTR     eDMA_0.TCD[6].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_0_TCD6_SOFF     eDMA_0.TCD[6].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_0_TCD6_NBYTES_MLNO eDMA_0.TCD[6].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD6_NBYTES_MLOFFNO eDMA_0.TCD[6].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD6_NBYTES_MLOFFYES eDMA_0.TCD[6].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD6_SLAST    eDMA_0.TCD[6].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD6_DADDR    eDMA_0.TCD[6].DADDR.R         /* TCD Destination Address */
#define eDMA_0_TCD6_CITER_ELINKNO eDMA_0.TCD[6].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD6_CITER_ELINKYES eDMA_0.TCD[6].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD6_DOFF     eDMA_0.TCD[6].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD6_DLASTSGA eDMA_0.TCD[6].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD6_BITER_ELINKNO eDMA_0.TCD[6].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD6_BITER_ELINKYES eDMA_0.TCD[6].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD6_CSR      eDMA_0.TCD[6].CSR.R           /* TCD Control and Status */
#define eDMA_0_TCD7_SADDR    eDMA_0.TCD[7].SADDR.R         /* TCD Source Address */
#define eDMA_0_TCD7_ATTR     eDMA_0.TCD[7].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_0_TCD7_SOFF     eDMA_0.TCD[7].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_0_TCD7_NBYTES_MLNO eDMA_0.TCD[7].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD7_NBYTES_MLOFFNO eDMA_0.TCD[7].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD7_NBYTES_MLOFFYES eDMA_0.TCD[7].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD7_SLAST    eDMA_0.TCD[7].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD7_DADDR    eDMA_0.TCD[7].DADDR.R         /* TCD Destination Address */
#define eDMA_0_TCD7_CITER_ELINKNO eDMA_0.TCD[7].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD7_CITER_ELINKYES eDMA_0.TCD[7].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD7_DOFF     eDMA_0.TCD[7].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD7_DLASTSGA eDMA_0.TCD[7].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD7_BITER_ELINKNO eDMA_0.TCD[7].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD7_BITER_ELINKYES eDMA_0.TCD[7].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD7_CSR      eDMA_0.TCD[7].CSR.R           /* TCD Control and Status */
#define eDMA_0_TCD8_SADDR    eDMA_0.TCD[8].SADDR.R         /* TCD Source Address */
#define eDMA_0_TCD8_ATTR     eDMA_0.TCD[8].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_0_TCD8_SOFF     eDMA_0.TCD[8].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_0_TCD8_NBYTES_MLNO eDMA_0.TCD[8].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD8_NBYTES_MLOFFNO eDMA_0.TCD[8].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD8_NBYTES_MLOFFYES eDMA_0.TCD[8].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD8_SLAST    eDMA_0.TCD[8].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD8_DADDR    eDMA_0.TCD[8].DADDR.R         /* TCD Destination Address */
#define eDMA_0_TCD8_CITER_ELINKNO eDMA_0.TCD[8].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD8_CITER_ELINKYES eDMA_0.TCD[8].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD8_DOFF     eDMA_0.TCD[8].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD8_DLASTSGA eDMA_0.TCD[8].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD8_BITER_ELINKNO eDMA_0.TCD[8].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD8_BITER_ELINKYES eDMA_0.TCD[8].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD8_CSR      eDMA_0.TCD[8].CSR.R           /* TCD Control and Status */
#define eDMA_0_TCD9_SADDR    eDMA_0.TCD[9].SADDR.R         /* TCD Source Address */
#define eDMA_0_TCD9_ATTR     eDMA_0.TCD[9].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_0_TCD9_SOFF     eDMA_0.TCD[9].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_0_TCD9_NBYTES_MLNO eDMA_0.TCD[9].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD9_NBYTES_MLOFFNO eDMA_0.TCD[9].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD9_NBYTES_MLOFFYES eDMA_0.TCD[9].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD9_SLAST    eDMA_0.TCD[9].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD9_DADDR    eDMA_0.TCD[9].DADDR.R         /* TCD Destination Address */
#define eDMA_0_TCD9_CITER_ELINKNO eDMA_0.TCD[9].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD9_CITER_ELINKYES eDMA_0.TCD[9].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD9_DOFF     eDMA_0.TCD[9].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD9_DLASTSGA eDMA_0.TCD[9].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD9_BITER_ELINKNO eDMA_0.TCD[9].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD9_BITER_ELINKYES eDMA_0.TCD[9].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD9_CSR      eDMA_0.TCD[9].CSR.R           /* TCD Control and Status */
#define eDMA_0_TCD10_SADDR   eDMA_0.TCD[10].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD10_ATTR    eDMA_0.TCD[10].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD10_SOFF    eDMA_0.TCD[10].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD10_NBYTES_MLNO eDMA_0.TCD[10].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD10_NBYTES_MLOFFNO eDMA_0.TCD[10].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD10_NBYTES_MLOFFYES eDMA_0.TCD[10].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD10_SLAST   eDMA_0.TCD[10].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD10_DADDR   eDMA_0.TCD[10].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD10_CITER_ELINKNO eDMA_0.TCD[10].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD10_CITER_ELINKYES eDMA_0.TCD[10].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD10_DOFF    eDMA_0.TCD[10].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD10_DLASTSGA eDMA_0.TCD[10].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD10_BITER_ELINKNO eDMA_0.TCD[10].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD10_BITER_ELINKYES eDMA_0.TCD[10].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD10_CSR     eDMA_0.TCD[10].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD11_SADDR   eDMA_0.TCD[11].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD11_ATTR    eDMA_0.TCD[11].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD11_SOFF    eDMA_0.TCD[11].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD11_NBYTES_MLNO eDMA_0.TCD[11].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD11_NBYTES_MLOFFNO eDMA_0.TCD[11].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD11_NBYTES_MLOFFYES eDMA_0.TCD[11].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD11_SLAST   eDMA_0.TCD[11].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD11_DADDR   eDMA_0.TCD[11].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD11_CITER_ELINKNO eDMA_0.TCD[11].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD11_CITER_ELINKYES eDMA_0.TCD[11].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD11_DOFF    eDMA_0.TCD[11].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD11_DLASTSGA eDMA_0.TCD[11].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD11_BITER_ELINKNO eDMA_0.TCD[11].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD11_BITER_ELINKYES eDMA_0.TCD[11].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD11_CSR     eDMA_0.TCD[11].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD12_SADDR   eDMA_0.TCD[12].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD12_ATTR    eDMA_0.TCD[12].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD12_SOFF    eDMA_0.TCD[12].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD12_NBYTES_MLNO eDMA_0.TCD[12].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD12_NBYTES_MLOFFNO eDMA_0.TCD[12].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD12_NBYTES_MLOFFYES eDMA_0.TCD[12].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD12_SLAST   eDMA_0.TCD[12].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD12_DADDR   eDMA_0.TCD[12].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD12_CITER_ELINKNO eDMA_0.TCD[12].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD12_CITER_ELINKYES eDMA_0.TCD[12].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD12_DOFF    eDMA_0.TCD[12].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD12_DLASTSGA eDMA_0.TCD[12].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD12_BITER_ELINKNO eDMA_0.TCD[12].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD12_BITER_ELINKYES eDMA_0.TCD[12].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD12_CSR     eDMA_0.TCD[12].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD13_SADDR   eDMA_0.TCD[13].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD13_ATTR    eDMA_0.TCD[13].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD13_SOFF    eDMA_0.TCD[13].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD13_NBYTES_MLNO eDMA_0.TCD[13].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD13_NBYTES_MLOFFNO eDMA_0.TCD[13].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD13_NBYTES_MLOFFYES eDMA_0.TCD[13].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD13_SLAST   eDMA_0.TCD[13].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD13_DADDR   eDMA_0.TCD[13].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD13_CITER_ELINKNO eDMA_0.TCD[13].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD13_CITER_ELINKYES eDMA_0.TCD[13].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD13_DOFF    eDMA_0.TCD[13].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD13_DLASTSGA eDMA_0.TCD[13].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD13_BITER_ELINKNO eDMA_0.TCD[13].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD13_BITER_ELINKYES eDMA_0.TCD[13].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD13_CSR     eDMA_0.TCD[13].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD14_SADDR   eDMA_0.TCD[14].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD14_ATTR    eDMA_0.TCD[14].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD14_SOFF    eDMA_0.TCD[14].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD14_NBYTES_MLNO eDMA_0.TCD[14].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD14_NBYTES_MLOFFNO eDMA_0.TCD[14].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD14_NBYTES_MLOFFYES eDMA_0.TCD[14].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD14_SLAST   eDMA_0.TCD[14].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD14_DADDR   eDMA_0.TCD[14].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD14_CITER_ELINKNO eDMA_0.TCD[14].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD14_CITER_ELINKYES eDMA_0.TCD[14].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD14_DOFF    eDMA_0.TCD[14].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD14_DLASTSGA eDMA_0.TCD[14].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD14_BITER_ELINKNO eDMA_0.TCD[14].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD14_BITER_ELINKYES eDMA_0.TCD[14].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD14_CSR     eDMA_0.TCD[14].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD15_SADDR   eDMA_0.TCD[15].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD15_ATTR    eDMA_0.TCD[15].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD15_SOFF    eDMA_0.TCD[15].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD15_NBYTES_MLNO eDMA_0.TCD[15].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD15_NBYTES_MLOFFNO eDMA_0.TCD[15].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD15_NBYTES_MLOFFYES eDMA_0.TCD[15].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD15_SLAST   eDMA_0.TCD[15].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD15_DADDR   eDMA_0.TCD[15].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD15_CITER_ELINKNO eDMA_0.TCD[15].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD15_CITER_ELINKYES eDMA_0.TCD[15].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD15_DOFF    eDMA_0.TCD[15].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD15_DLASTSGA eDMA_0.TCD[15].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD15_BITER_ELINKNO eDMA_0.TCD[15].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD15_BITER_ELINKYES eDMA_0.TCD[15].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD15_CSR     eDMA_0.TCD[15].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD16_SADDR   eDMA_0.TCD[16].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD16_ATTR    eDMA_0.TCD[16].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD16_SOFF    eDMA_0.TCD[16].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD16_NBYTES_MLNO eDMA_0.TCD[16].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD16_NBYTES_MLOFFNO eDMA_0.TCD[16].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD16_NBYTES_MLOFFYES eDMA_0.TCD[16].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD16_SLAST   eDMA_0.TCD[16].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD16_DADDR   eDMA_0.TCD[16].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD16_CITER_ELINKNO eDMA_0.TCD[16].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD16_CITER_ELINKYES eDMA_0.TCD[16].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD16_DOFF    eDMA_0.TCD[16].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD16_DLASTSGA eDMA_0.TCD[16].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD16_BITER_ELINKNO eDMA_0.TCD[16].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD16_BITER_ELINKYES eDMA_0.TCD[16].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD16_CSR     eDMA_0.TCD[16].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD17_SADDR   eDMA_0.TCD[17].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD17_ATTR    eDMA_0.TCD[17].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD17_SOFF    eDMA_0.TCD[17].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD17_NBYTES_MLNO eDMA_0.TCD[17].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD17_NBYTES_MLOFFNO eDMA_0.TCD[17].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD17_NBYTES_MLOFFYES eDMA_0.TCD[17].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD17_SLAST   eDMA_0.TCD[17].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD17_DADDR   eDMA_0.TCD[17].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD17_CITER_ELINKNO eDMA_0.TCD[17].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD17_CITER_ELINKYES eDMA_0.TCD[17].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD17_DOFF    eDMA_0.TCD[17].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD17_DLASTSGA eDMA_0.TCD[17].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD17_BITER_ELINKNO eDMA_0.TCD[17].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD17_BITER_ELINKYES eDMA_0.TCD[17].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD17_CSR     eDMA_0.TCD[17].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD18_SADDR   eDMA_0.TCD[18].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD18_ATTR    eDMA_0.TCD[18].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD18_SOFF    eDMA_0.TCD[18].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD18_NBYTES_MLNO eDMA_0.TCD[18].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD18_NBYTES_MLOFFNO eDMA_0.TCD[18].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD18_NBYTES_MLOFFYES eDMA_0.TCD[18].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD18_SLAST   eDMA_0.TCD[18].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD18_DADDR   eDMA_0.TCD[18].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD18_CITER_ELINKNO eDMA_0.TCD[18].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD18_CITER_ELINKYES eDMA_0.TCD[18].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD18_DOFF    eDMA_0.TCD[18].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD18_DLASTSGA eDMA_0.TCD[18].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD18_BITER_ELINKNO eDMA_0.TCD[18].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD18_BITER_ELINKYES eDMA_0.TCD[18].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD18_CSR     eDMA_0.TCD[18].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD19_SADDR   eDMA_0.TCD[19].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD19_ATTR    eDMA_0.TCD[19].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD19_SOFF    eDMA_0.TCD[19].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD19_NBYTES_MLNO eDMA_0.TCD[19].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD19_NBYTES_MLOFFNO eDMA_0.TCD[19].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD19_NBYTES_MLOFFYES eDMA_0.TCD[19].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD19_SLAST   eDMA_0.TCD[19].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD19_DADDR   eDMA_0.TCD[19].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD19_CITER_ELINKNO eDMA_0.TCD[19].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD19_CITER_ELINKYES eDMA_0.TCD[19].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD19_DOFF    eDMA_0.TCD[19].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD19_DLASTSGA eDMA_0.TCD[19].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD19_BITER_ELINKNO eDMA_0.TCD[19].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD19_BITER_ELINKYES eDMA_0.TCD[19].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD19_CSR     eDMA_0.TCD[19].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD20_SADDR   eDMA_0.TCD[20].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD20_ATTR    eDMA_0.TCD[20].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD20_SOFF    eDMA_0.TCD[20].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD20_NBYTES_MLNO eDMA_0.TCD[20].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD20_NBYTES_MLOFFNO eDMA_0.TCD[20].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD20_NBYTES_MLOFFYES eDMA_0.TCD[20].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD20_SLAST   eDMA_0.TCD[20].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD20_DADDR   eDMA_0.TCD[20].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD20_CITER_ELINKNO eDMA_0.TCD[20].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD20_CITER_ELINKYES eDMA_0.TCD[20].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD20_DOFF    eDMA_0.TCD[20].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD20_DLASTSGA eDMA_0.TCD[20].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD20_BITER_ELINKNO eDMA_0.TCD[20].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD20_BITER_ELINKYES eDMA_0.TCD[20].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD20_CSR     eDMA_0.TCD[20].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD21_SADDR   eDMA_0.TCD[21].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD21_ATTR    eDMA_0.TCD[21].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD21_SOFF    eDMA_0.TCD[21].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD21_NBYTES_MLNO eDMA_0.TCD[21].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD21_NBYTES_MLOFFNO eDMA_0.TCD[21].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD21_NBYTES_MLOFFYES eDMA_0.TCD[21].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD21_SLAST   eDMA_0.TCD[21].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD21_DADDR   eDMA_0.TCD[21].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD21_CITER_ELINKNO eDMA_0.TCD[21].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD21_CITER_ELINKYES eDMA_0.TCD[21].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD21_DOFF    eDMA_0.TCD[21].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD21_DLASTSGA eDMA_0.TCD[21].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD21_BITER_ELINKNO eDMA_0.TCD[21].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD21_BITER_ELINKYES eDMA_0.TCD[21].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD21_CSR     eDMA_0.TCD[21].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD22_SADDR   eDMA_0.TCD[22].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD22_ATTR    eDMA_0.TCD[22].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD22_SOFF    eDMA_0.TCD[22].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD22_NBYTES_MLNO eDMA_0.TCD[22].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD22_NBYTES_MLOFFNO eDMA_0.TCD[22].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD22_NBYTES_MLOFFYES eDMA_0.TCD[22].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD22_SLAST   eDMA_0.TCD[22].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD22_DADDR   eDMA_0.TCD[22].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD22_CITER_ELINKNO eDMA_0.TCD[22].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD22_CITER_ELINKYES eDMA_0.TCD[22].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD22_DOFF    eDMA_0.TCD[22].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD22_DLASTSGA eDMA_0.TCD[22].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD22_BITER_ELINKNO eDMA_0.TCD[22].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD22_BITER_ELINKYES eDMA_0.TCD[22].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD22_CSR     eDMA_0.TCD[22].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD23_SADDR   eDMA_0.TCD[23].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD23_ATTR    eDMA_0.TCD[23].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD23_SOFF    eDMA_0.TCD[23].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD23_NBYTES_MLNO eDMA_0.TCD[23].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD23_NBYTES_MLOFFNO eDMA_0.TCD[23].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD23_NBYTES_MLOFFYES eDMA_0.TCD[23].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD23_SLAST   eDMA_0.TCD[23].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD23_DADDR   eDMA_0.TCD[23].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD23_CITER_ELINKNO eDMA_0.TCD[23].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD23_CITER_ELINKYES eDMA_0.TCD[23].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD23_DOFF    eDMA_0.TCD[23].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD23_DLASTSGA eDMA_0.TCD[23].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD23_BITER_ELINKNO eDMA_0.TCD[23].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD23_BITER_ELINKYES eDMA_0.TCD[23].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD23_CSR     eDMA_0.TCD[23].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD24_SADDR   eDMA_0.TCD[24].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD24_ATTR    eDMA_0.TCD[24].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD24_SOFF    eDMA_0.TCD[24].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD24_NBYTES_MLNO eDMA_0.TCD[24].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD24_NBYTES_MLOFFNO eDMA_0.TCD[24].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD24_NBYTES_MLOFFYES eDMA_0.TCD[24].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD24_SLAST   eDMA_0.TCD[24].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD24_DADDR   eDMA_0.TCD[24].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD24_CITER_ELINKNO eDMA_0.TCD[24].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD24_CITER_ELINKYES eDMA_0.TCD[24].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD24_DOFF    eDMA_0.TCD[24].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD24_DLASTSGA eDMA_0.TCD[24].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD24_BITER_ELINKNO eDMA_0.TCD[24].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD24_BITER_ELINKYES eDMA_0.TCD[24].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD24_CSR     eDMA_0.TCD[24].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD25_SADDR   eDMA_0.TCD[25].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD25_ATTR    eDMA_0.TCD[25].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD25_SOFF    eDMA_0.TCD[25].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD25_NBYTES_MLNO eDMA_0.TCD[25].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD25_NBYTES_MLOFFNO eDMA_0.TCD[25].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD25_NBYTES_MLOFFYES eDMA_0.TCD[25].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD25_SLAST   eDMA_0.TCD[25].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD25_DADDR   eDMA_0.TCD[25].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD25_CITER_ELINKNO eDMA_0.TCD[25].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD25_CITER_ELINKYES eDMA_0.TCD[25].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD25_DOFF    eDMA_0.TCD[25].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD25_DLASTSGA eDMA_0.TCD[25].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD25_BITER_ELINKNO eDMA_0.TCD[25].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD25_BITER_ELINKYES eDMA_0.TCD[25].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD25_CSR     eDMA_0.TCD[25].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD26_SADDR   eDMA_0.TCD[26].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD26_ATTR    eDMA_0.TCD[26].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD26_SOFF    eDMA_0.TCD[26].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD26_NBYTES_MLNO eDMA_0.TCD[26].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD26_NBYTES_MLOFFNO eDMA_0.TCD[26].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD26_NBYTES_MLOFFYES eDMA_0.TCD[26].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD26_SLAST   eDMA_0.TCD[26].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD26_DADDR   eDMA_0.TCD[26].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD26_CITER_ELINKNO eDMA_0.TCD[26].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD26_CITER_ELINKYES eDMA_0.TCD[26].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD26_DOFF    eDMA_0.TCD[26].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD26_DLASTSGA eDMA_0.TCD[26].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD26_BITER_ELINKNO eDMA_0.TCD[26].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD26_BITER_ELINKYES eDMA_0.TCD[26].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD26_CSR     eDMA_0.TCD[26].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD27_SADDR   eDMA_0.TCD[27].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD27_ATTR    eDMA_0.TCD[27].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD27_SOFF    eDMA_0.TCD[27].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD27_NBYTES_MLNO eDMA_0.TCD[27].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD27_NBYTES_MLOFFNO eDMA_0.TCD[27].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD27_NBYTES_MLOFFYES eDMA_0.TCD[27].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD27_SLAST   eDMA_0.TCD[27].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD27_DADDR   eDMA_0.TCD[27].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD27_CITER_ELINKNO eDMA_0.TCD[27].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD27_CITER_ELINKYES eDMA_0.TCD[27].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD27_DOFF    eDMA_0.TCD[27].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD27_DLASTSGA eDMA_0.TCD[27].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD27_BITER_ELINKNO eDMA_0.TCD[27].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD27_BITER_ELINKYES eDMA_0.TCD[27].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD27_CSR     eDMA_0.TCD[27].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD28_SADDR   eDMA_0.TCD[28].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD28_ATTR    eDMA_0.TCD[28].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD28_SOFF    eDMA_0.TCD[28].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD28_NBYTES_MLNO eDMA_0.TCD[28].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD28_NBYTES_MLOFFNO eDMA_0.TCD[28].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD28_NBYTES_MLOFFYES eDMA_0.TCD[28].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD28_SLAST   eDMA_0.TCD[28].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD28_DADDR   eDMA_0.TCD[28].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD28_CITER_ELINKNO eDMA_0.TCD[28].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD28_CITER_ELINKYES eDMA_0.TCD[28].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD28_DOFF    eDMA_0.TCD[28].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD28_DLASTSGA eDMA_0.TCD[28].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD28_BITER_ELINKNO eDMA_0.TCD[28].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD28_BITER_ELINKYES eDMA_0.TCD[28].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD28_CSR     eDMA_0.TCD[28].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD29_SADDR   eDMA_0.TCD[29].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD29_ATTR    eDMA_0.TCD[29].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD29_SOFF    eDMA_0.TCD[29].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD29_NBYTES_MLNO eDMA_0.TCD[29].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD29_NBYTES_MLOFFNO eDMA_0.TCD[29].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD29_NBYTES_MLOFFYES eDMA_0.TCD[29].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD29_SLAST   eDMA_0.TCD[29].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD29_DADDR   eDMA_0.TCD[29].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD29_CITER_ELINKNO eDMA_0.TCD[29].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD29_CITER_ELINKYES eDMA_0.TCD[29].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD29_DOFF    eDMA_0.TCD[29].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD29_DLASTSGA eDMA_0.TCD[29].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD29_BITER_ELINKNO eDMA_0.TCD[29].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD29_BITER_ELINKYES eDMA_0.TCD[29].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD29_CSR     eDMA_0.TCD[29].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD30_SADDR   eDMA_0.TCD[30].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD30_ATTR    eDMA_0.TCD[30].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD30_SOFF    eDMA_0.TCD[30].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD30_NBYTES_MLNO eDMA_0.TCD[30].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD30_NBYTES_MLOFFNO eDMA_0.TCD[30].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD30_NBYTES_MLOFFYES eDMA_0.TCD[30].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD30_SLAST   eDMA_0.TCD[30].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD30_DADDR   eDMA_0.TCD[30].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD30_CITER_ELINKNO eDMA_0.TCD[30].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD30_CITER_ELINKYES eDMA_0.TCD[30].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD30_DOFF    eDMA_0.TCD[30].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD30_DLASTSGA eDMA_0.TCD[30].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD30_BITER_ELINKNO eDMA_0.TCD[30].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD30_BITER_ELINKYES eDMA_0.TCD[30].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD30_CSR     eDMA_0.TCD[30].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD31_SADDR   eDMA_0.TCD[31].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD31_ATTR    eDMA_0.TCD[31].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD31_SOFF    eDMA_0.TCD[31].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD31_NBYTES_MLNO eDMA_0.TCD[31].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD31_NBYTES_MLOFFNO eDMA_0.TCD[31].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD31_NBYTES_MLOFFYES eDMA_0.TCD[31].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD31_SLAST   eDMA_0.TCD[31].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD31_DADDR   eDMA_0.TCD[31].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD31_CITER_ELINKNO eDMA_0.TCD[31].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD31_CITER_ELINKYES eDMA_0.TCD[31].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD31_DOFF    eDMA_0.TCD[31].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD31_DLASTSGA eDMA_0.TCD[31].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD31_BITER_ELINKNO eDMA_0.TCD[31].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD31_BITER_ELINKYES eDMA_0.TCD[31].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD31_CSR     eDMA_0.TCD[31].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD32_SADDR   eDMA_0.TCD[32].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD32_ATTR    eDMA_0.TCD[32].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD32_SOFF    eDMA_0.TCD[32].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD32_NBYTES_MLNO eDMA_0.TCD[32].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD32_NBYTES_MLOFFNO eDMA_0.TCD[32].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD32_NBYTES_MLOFFYES eDMA_0.TCD[32].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD32_SLAST   eDMA_0.TCD[32].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD32_DADDR   eDMA_0.TCD[32].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD32_CITER_ELINKNO eDMA_0.TCD[32].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD32_CITER_ELINKYES eDMA_0.TCD[32].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD32_DOFF    eDMA_0.TCD[32].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD32_DLASTSGA eDMA_0.TCD[32].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD32_BITER_ELINKNO eDMA_0.TCD[32].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD32_BITER_ELINKYES eDMA_0.TCD[32].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD32_CSR     eDMA_0.TCD[32].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD33_SADDR   eDMA_0.TCD[33].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD33_ATTR    eDMA_0.TCD[33].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD33_SOFF    eDMA_0.TCD[33].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD33_NBYTES_MLNO eDMA_0.TCD[33].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD33_NBYTES_MLOFFNO eDMA_0.TCD[33].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD33_NBYTES_MLOFFYES eDMA_0.TCD[33].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD33_SLAST   eDMA_0.TCD[33].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD33_DADDR   eDMA_0.TCD[33].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD33_CITER_ELINKNO eDMA_0.TCD[33].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD33_CITER_ELINKYES eDMA_0.TCD[33].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD33_DOFF    eDMA_0.TCD[33].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD33_DLASTSGA eDMA_0.TCD[33].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD33_BITER_ELINKNO eDMA_0.TCD[33].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD33_BITER_ELINKYES eDMA_0.TCD[33].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD33_CSR     eDMA_0.TCD[33].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD34_SADDR   eDMA_0.TCD[34].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD34_ATTR    eDMA_0.TCD[34].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD34_SOFF    eDMA_0.TCD[34].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD34_NBYTES_MLNO eDMA_0.TCD[34].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD34_NBYTES_MLOFFNO eDMA_0.TCD[34].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD34_NBYTES_MLOFFYES eDMA_0.TCD[34].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD34_SLAST   eDMA_0.TCD[34].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD34_DADDR   eDMA_0.TCD[34].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD34_CITER_ELINKNO eDMA_0.TCD[34].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD34_CITER_ELINKYES eDMA_0.TCD[34].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD34_DOFF    eDMA_0.TCD[34].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD34_DLASTSGA eDMA_0.TCD[34].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD34_BITER_ELINKNO eDMA_0.TCD[34].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD34_BITER_ELINKYES eDMA_0.TCD[34].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD34_CSR     eDMA_0.TCD[34].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD35_SADDR   eDMA_0.TCD[35].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD35_ATTR    eDMA_0.TCD[35].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD35_SOFF    eDMA_0.TCD[35].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD35_NBYTES_MLNO eDMA_0.TCD[35].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD35_NBYTES_MLOFFNO eDMA_0.TCD[35].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD35_NBYTES_MLOFFYES eDMA_0.TCD[35].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD35_SLAST   eDMA_0.TCD[35].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD35_DADDR   eDMA_0.TCD[35].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD35_CITER_ELINKNO eDMA_0.TCD[35].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD35_CITER_ELINKYES eDMA_0.TCD[35].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD35_DOFF    eDMA_0.TCD[35].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD35_DLASTSGA eDMA_0.TCD[35].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD35_BITER_ELINKNO eDMA_0.TCD[35].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD35_BITER_ELINKYES eDMA_0.TCD[35].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD35_CSR     eDMA_0.TCD[35].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD36_SADDR   eDMA_0.TCD[36].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD36_ATTR    eDMA_0.TCD[36].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD36_SOFF    eDMA_0.TCD[36].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD36_NBYTES_MLNO eDMA_0.TCD[36].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD36_NBYTES_MLOFFNO eDMA_0.TCD[36].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD36_NBYTES_MLOFFYES eDMA_0.TCD[36].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD36_SLAST   eDMA_0.TCD[36].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD36_DADDR   eDMA_0.TCD[36].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD36_CITER_ELINKNO eDMA_0.TCD[36].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD36_CITER_ELINKYES eDMA_0.TCD[36].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD36_DOFF    eDMA_0.TCD[36].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD36_DLASTSGA eDMA_0.TCD[36].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD36_BITER_ELINKNO eDMA_0.TCD[36].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD36_BITER_ELINKYES eDMA_0.TCD[36].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD36_CSR     eDMA_0.TCD[36].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD37_SADDR   eDMA_0.TCD[37].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD37_ATTR    eDMA_0.TCD[37].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD37_SOFF    eDMA_0.TCD[37].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD37_NBYTES_MLNO eDMA_0.TCD[37].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD37_NBYTES_MLOFFNO eDMA_0.TCD[37].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD37_NBYTES_MLOFFYES eDMA_0.TCD[37].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD37_SLAST   eDMA_0.TCD[37].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD37_DADDR   eDMA_0.TCD[37].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD37_CITER_ELINKNO eDMA_0.TCD[37].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD37_CITER_ELINKYES eDMA_0.TCD[37].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD37_DOFF    eDMA_0.TCD[37].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD37_DLASTSGA eDMA_0.TCD[37].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD37_BITER_ELINKNO eDMA_0.TCD[37].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD37_BITER_ELINKYES eDMA_0.TCD[37].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD37_CSR     eDMA_0.TCD[37].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD38_SADDR   eDMA_0.TCD[38].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD38_ATTR    eDMA_0.TCD[38].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD38_SOFF    eDMA_0.TCD[38].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD38_NBYTES_MLNO eDMA_0.TCD[38].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD38_NBYTES_MLOFFNO eDMA_0.TCD[38].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD38_NBYTES_MLOFFYES eDMA_0.TCD[38].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD38_SLAST   eDMA_0.TCD[38].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD38_DADDR   eDMA_0.TCD[38].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD38_CITER_ELINKNO eDMA_0.TCD[38].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD38_CITER_ELINKYES eDMA_0.TCD[38].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD38_DOFF    eDMA_0.TCD[38].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD38_DLASTSGA eDMA_0.TCD[38].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD38_BITER_ELINKNO eDMA_0.TCD[38].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD38_BITER_ELINKYES eDMA_0.TCD[38].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD38_CSR     eDMA_0.TCD[38].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD39_SADDR   eDMA_0.TCD[39].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD39_ATTR    eDMA_0.TCD[39].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD39_SOFF    eDMA_0.TCD[39].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD39_NBYTES_MLNO eDMA_0.TCD[39].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD39_NBYTES_MLOFFNO eDMA_0.TCD[39].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD39_NBYTES_MLOFFYES eDMA_0.TCD[39].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD39_SLAST   eDMA_0.TCD[39].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD39_DADDR   eDMA_0.TCD[39].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD39_CITER_ELINKNO eDMA_0.TCD[39].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD39_CITER_ELINKYES eDMA_0.TCD[39].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD39_DOFF    eDMA_0.TCD[39].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD39_DLASTSGA eDMA_0.TCD[39].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD39_BITER_ELINKNO eDMA_0.TCD[39].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD39_BITER_ELINKYES eDMA_0.TCD[39].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD39_CSR     eDMA_0.TCD[39].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD40_SADDR   eDMA_0.TCD[40].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD40_ATTR    eDMA_0.TCD[40].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD40_SOFF    eDMA_0.TCD[40].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD40_NBYTES_MLNO eDMA_0.TCD[40].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD40_NBYTES_MLOFFNO eDMA_0.TCD[40].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD40_NBYTES_MLOFFYES eDMA_0.TCD[40].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD40_SLAST   eDMA_0.TCD[40].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD40_DADDR   eDMA_0.TCD[40].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD40_CITER_ELINKNO eDMA_0.TCD[40].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD40_CITER_ELINKYES eDMA_0.TCD[40].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD40_DOFF    eDMA_0.TCD[40].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD40_DLASTSGA eDMA_0.TCD[40].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD40_BITER_ELINKNO eDMA_0.TCD[40].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD40_BITER_ELINKYES eDMA_0.TCD[40].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD40_CSR     eDMA_0.TCD[40].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD41_SADDR   eDMA_0.TCD[41].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD41_ATTR    eDMA_0.TCD[41].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD41_SOFF    eDMA_0.TCD[41].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD41_NBYTES_MLNO eDMA_0.TCD[41].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD41_NBYTES_MLOFFNO eDMA_0.TCD[41].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD41_NBYTES_MLOFFYES eDMA_0.TCD[41].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD41_SLAST   eDMA_0.TCD[41].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD41_DADDR   eDMA_0.TCD[41].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD41_CITER_ELINKNO eDMA_0.TCD[41].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD41_CITER_ELINKYES eDMA_0.TCD[41].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD41_DOFF    eDMA_0.TCD[41].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD41_DLASTSGA eDMA_0.TCD[41].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD41_BITER_ELINKNO eDMA_0.TCD[41].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD41_BITER_ELINKYES eDMA_0.TCD[41].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD41_CSR     eDMA_0.TCD[41].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD42_SADDR   eDMA_0.TCD[42].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD42_ATTR    eDMA_0.TCD[42].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD42_SOFF    eDMA_0.TCD[42].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD42_NBYTES_MLNO eDMA_0.TCD[42].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD42_NBYTES_MLOFFNO eDMA_0.TCD[42].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD42_NBYTES_MLOFFYES eDMA_0.TCD[42].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD42_SLAST   eDMA_0.TCD[42].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD42_DADDR   eDMA_0.TCD[42].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD42_CITER_ELINKNO eDMA_0.TCD[42].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD42_CITER_ELINKYES eDMA_0.TCD[42].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD42_DOFF    eDMA_0.TCD[42].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD42_DLASTSGA eDMA_0.TCD[42].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD42_BITER_ELINKNO eDMA_0.TCD[42].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD42_BITER_ELINKYES eDMA_0.TCD[42].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD42_CSR     eDMA_0.TCD[42].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD43_SADDR   eDMA_0.TCD[43].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD43_ATTR    eDMA_0.TCD[43].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD43_SOFF    eDMA_0.TCD[43].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD43_NBYTES_MLNO eDMA_0.TCD[43].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD43_NBYTES_MLOFFNO eDMA_0.TCD[43].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD43_NBYTES_MLOFFYES eDMA_0.TCD[43].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD43_SLAST   eDMA_0.TCD[43].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD43_DADDR   eDMA_0.TCD[43].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD43_CITER_ELINKNO eDMA_0.TCD[43].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD43_CITER_ELINKYES eDMA_0.TCD[43].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD43_DOFF    eDMA_0.TCD[43].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD43_DLASTSGA eDMA_0.TCD[43].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD43_BITER_ELINKNO eDMA_0.TCD[43].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD43_BITER_ELINKYES eDMA_0.TCD[43].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD43_CSR     eDMA_0.TCD[43].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD44_SADDR   eDMA_0.TCD[44].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD44_ATTR    eDMA_0.TCD[44].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD44_SOFF    eDMA_0.TCD[44].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD44_NBYTES_MLNO eDMA_0.TCD[44].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD44_NBYTES_MLOFFNO eDMA_0.TCD[44].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD44_NBYTES_MLOFFYES eDMA_0.TCD[44].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD44_SLAST   eDMA_0.TCD[44].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD44_DADDR   eDMA_0.TCD[44].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD44_CITER_ELINKNO eDMA_0.TCD[44].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD44_CITER_ELINKYES eDMA_0.TCD[44].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD44_DOFF    eDMA_0.TCD[44].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD44_DLASTSGA eDMA_0.TCD[44].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD44_BITER_ELINKNO eDMA_0.TCD[44].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD44_BITER_ELINKYES eDMA_0.TCD[44].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD44_CSR     eDMA_0.TCD[44].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD45_SADDR   eDMA_0.TCD[45].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD45_ATTR    eDMA_0.TCD[45].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD45_SOFF    eDMA_0.TCD[45].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD45_NBYTES_MLNO eDMA_0.TCD[45].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD45_NBYTES_MLOFFNO eDMA_0.TCD[45].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD45_NBYTES_MLOFFYES eDMA_0.TCD[45].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD45_SLAST   eDMA_0.TCD[45].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD45_DADDR   eDMA_0.TCD[45].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD45_CITER_ELINKNO eDMA_0.TCD[45].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD45_CITER_ELINKYES eDMA_0.TCD[45].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD45_DOFF    eDMA_0.TCD[45].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD45_DLASTSGA eDMA_0.TCD[45].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD45_BITER_ELINKNO eDMA_0.TCD[45].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD45_BITER_ELINKYES eDMA_0.TCD[45].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD45_CSR     eDMA_0.TCD[45].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD46_SADDR   eDMA_0.TCD[46].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD46_ATTR    eDMA_0.TCD[46].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD46_SOFF    eDMA_0.TCD[46].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD46_NBYTES_MLNO eDMA_0.TCD[46].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD46_NBYTES_MLOFFNO eDMA_0.TCD[46].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD46_NBYTES_MLOFFYES eDMA_0.TCD[46].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD46_SLAST   eDMA_0.TCD[46].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD46_DADDR   eDMA_0.TCD[46].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD46_CITER_ELINKNO eDMA_0.TCD[46].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD46_CITER_ELINKYES eDMA_0.TCD[46].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD46_DOFF    eDMA_0.TCD[46].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD46_DLASTSGA eDMA_0.TCD[46].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD46_BITER_ELINKNO eDMA_0.TCD[46].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD46_BITER_ELINKYES eDMA_0.TCD[46].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD46_CSR     eDMA_0.TCD[46].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD47_SADDR   eDMA_0.TCD[47].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD47_ATTR    eDMA_0.TCD[47].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD47_SOFF    eDMA_0.TCD[47].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD47_NBYTES_MLNO eDMA_0.TCD[47].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD47_NBYTES_MLOFFNO eDMA_0.TCD[47].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD47_NBYTES_MLOFFYES eDMA_0.TCD[47].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD47_SLAST   eDMA_0.TCD[47].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD47_DADDR   eDMA_0.TCD[47].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD47_CITER_ELINKNO eDMA_0.TCD[47].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD47_CITER_ELINKYES eDMA_0.TCD[47].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD47_DOFF    eDMA_0.TCD[47].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD47_DLASTSGA eDMA_0.TCD[47].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD47_BITER_ELINKNO eDMA_0.TCD[47].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD47_BITER_ELINKYES eDMA_0.TCD[47].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD47_CSR     eDMA_0.TCD[47].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD48_SADDR   eDMA_0.TCD[48].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD48_ATTR    eDMA_0.TCD[48].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD48_SOFF    eDMA_0.TCD[48].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD48_NBYTES_MLNO eDMA_0.TCD[48].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD48_NBYTES_MLOFFNO eDMA_0.TCD[48].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD48_NBYTES_MLOFFYES eDMA_0.TCD[48].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD48_SLAST   eDMA_0.TCD[48].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD48_DADDR   eDMA_0.TCD[48].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD48_CITER_ELINKNO eDMA_0.TCD[48].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD48_CITER_ELINKYES eDMA_0.TCD[48].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD48_DOFF    eDMA_0.TCD[48].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD48_DLASTSGA eDMA_0.TCD[48].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD48_BITER_ELINKNO eDMA_0.TCD[48].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD48_BITER_ELINKYES eDMA_0.TCD[48].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD48_CSR     eDMA_0.TCD[48].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD49_SADDR   eDMA_0.TCD[49].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD49_ATTR    eDMA_0.TCD[49].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD49_SOFF    eDMA_0.TCD[49].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD49_NBYTES_MLNO eDMA_0.TCD[49].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD49_NBYTES_MLOFFNO eDMA_0.TCD[49].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD49_NBYTES_MLOFFYES eDMA_0.TCD[49].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD49_SLAST   eDMA_0.TCD[49].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD49_DADDR   eDMA_0.TCD[49].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD49_CITER_ELINKNO eDMA_0.TCD[49].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD49_CITER_ELINKYES eDMA_0.TCD[49].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD49_DOFF    eDMA_0.TCD[49].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD49_DLASTSGA eDMA_0.TCD[49].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD49_BITER_ELINKNO eDMA_0.TCD[49].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD49_BITER_ELINKYES eDMA_0.TCD[49].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD49_CSR     eDMA_0.TCD[49].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD50_SADDR   eDMA_0.TCD[50].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD50_ATTR    eDMA_0.TCD[50].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD50_SOFF    eDMA_0.TCD[50].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD50_NBYTES_MLNO eDMA_0.TCD[50].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD50_NBYTES_MLOFFNO eDMA_0.TCD[50].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD50_NBYTES_MLOFFYES eDMA_0.TCD[50].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD50_SLAST   eDMA_0.TCD[50].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD50_DADDR   eDMA_0.TCD[50].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD50_CITER_ELINKNO eDMA_0.TCD[50].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD50_CITER_ELINKYES eDMA_0.TCD[50].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD50_DOFF    eDMA_0.TCD[50].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD50_DLASTSGA eDMA_0.TCD[50].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD50_BITER_ELINKNO eDMA_0.TCD[50].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD50_BITER_ELINKYES eDMA_0.TCD[50].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD50_CSR     eDMA_0.TCD[50].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD51_SADDR   eDMA_0.TCD[51].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD51_ATTR    eDMA_0.TCD[51].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD51_SOFF    eDMA_0.TCD[51].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD51_NBYTES_MLNO eDMA_0.TCD[51].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD51_NBYTES_MLOFFNO eDMA_0.TCD[51].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD51_NBYTES_MLOFFYES eDMA_0.TCD[51].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD51_SLAST   eDMA_0.TCD[51].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD51_DADDR   eDMA_0.TCD[51].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD51_CITER_ELINKNO eDMA_0.TCD[51].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD51_CITER_ELINKYES eDMA_0.TCD[51].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD51_DOFF    eDMA_0.TCD[51].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD51_DLASTSGA eDMA_0.TCD[51].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD51_BITER_ELINKNO eDMA_0.TCD[51].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD51_BITER_ELINKYES eDMA_0.TCD[51].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD51_CSR     eDMA_0.TCD[51].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD52_SADDR   eDMA_0.TCD[52].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD52_ATTR    eDMA_0.TCD[52].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD52_SOFF    eDMA_0.TCD[52].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD52_NBYTES_MLNO eDMA_0.TCD[52].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD52_NBYTES_MLOFFNO eDMA_0.TCD[52].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD52_NBYTES_MLOFFYES eDMA_0.TCD[52].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD52_SLAST   eDMA_0.TCD[52].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD52_DADDR   eDMA_0.TCD[52].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD52_CITER_ELINKNO eDMA_0.TCD[52].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD52_CITER_ELINKYES eDMA_0.TCD[52].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD52_DOFF    eDMA_0.TCD[52].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD52_DLASTSGA eDMA_0.TCD[52].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD52_BITER_ELINKNO eDMA_0.TCD[52].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD52_BITER_ELINKYES eDMA_0.TCD[52].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD52_CSR     eDMA_0.TCD[52].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD53_SADDR   eDMA_0.TCD[53].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD53_ATTR    eDMA_0.TCD[53].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD53_SOFF    eDMA_0.TCD[53].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD53_NBYTES_MLNO eDMA_0.TCD[53].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD53_NBYTES_MLOFFNO eDMA_0.TCD[53].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD53_NBYTES_MLOFFYES eDMA_0.TCD[53].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD53_SLAST   eDMA_0.TCD[53].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD53_DADDR   eDMA_0.TCD[53].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD53_CITER_ELINKNO eDMA_0.TCD[53].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD53_CITER_ELINKYES eDMA_0.TCD[53].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD53_DOFF    eDMA_0.TCD[53].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD53_DLASTSGA eDMA_0.TCD[53].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD53_BITER_ELINKNO eDMA_0.TCD[53].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD53_BITER_ELINKYES eDMA_0.TCD[53].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD53_CSR     eDMA_0.TCD[53].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD54_SADDR   eDMA_0.TCD[54].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD54_ATTR    eDMA_0.TCD[54].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD54_SOFF    eDMA_0.TCD[54].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD54_NBYTES_MLNO eDMA_0.TCD[54].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD54_NBYTES_MLOFFNO eDMA_0.TCD[54].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD54_NBYTES_MLOFFYES eDMA_0.TCD[54].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD54_SLAST   eDMA_0.TCD[54].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD54_DADDR   eDMA_0.TCD[54].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD54_CITER_ELINKNO eDMA_0.TCD[54].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD54_CITER_ELINKYES eDMA_0.TCD[54].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD54_DOFF    eDMA_0.TCD[54].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD54_DLASTSGA eDMA_0.TCD[54].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD54_BITER_ELINKNO eDMA_0.TCD[54].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD54_BITER_ELINKYES eDMA_0.TCD[54].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD54_CSR     eDMA_0.TCD[54].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD55_SADDR   eDMA_0.TCD[55].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD55_ATTR    eDMA_0.TCD[55].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD55_SOFF    eDMA_0.TCD[55].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD55_NBYTES_MLNO eDMA_0.TCD[55].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD55_NBYTES_MLOFFNO eDMA_0.TCD[55].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD55_NBYTES_MLOFFYES eDMA_0.TCD[55].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD55_SLAST   eDMA_0.TCD[55].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD55_DADDR   eDMA_0.TCD[55].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD55_CITER_ELINKNO eDMA_0.TCD[55].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD55_CITER_ELINKYES eDMA_0.TCD[55].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD55_DOFF    eDMA_0.TCD[55].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD55_DLASTSGA eDMA_0.TCD[55].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD55_BITER_ELINKNO eDMA_0.TCD[55].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD55_BITER_ELINKYES eDMA_0.TCD[55].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD55_CSR     eDMA_0.TCD[55].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD56_SADDR   eDMA_0.TCD[56].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD56_ATTR    eDMA_0.TCD[56].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD56_SOFF    eDMA_0.TCD[56].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD56_NBYTES_MLNO eDMA_0.TCD[56].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD56_NBYTES_MLOFFNO eDMA_0.TCD[56].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD56_NBYTES_MLOFFYES eDMA_0.TCD[56].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD56_SLAST   eDMA_0.TCD[56].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD56_DADDR   eDMA_0.TCD[56].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD56_CITER_ELINKNO eDMA_0.TCD[56].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD56_CITER_ELINKYES eDMA_0.TCD[56].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD56_DOFF    eDMA_0.TCD[56].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD56_DLASTSGA eDMA_0.TCD[56].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD56_BITER_ELINKNO eDMA_0.TCD[56].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD56_BITER_ELINKYES eDMA_0.TCD[56].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD56_CSR     eDMA_0.TCD[56].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD57_SADDR   eDMA_0.TCD[57].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD57_ATTR    eDMA_0.TCD[57].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD57_SOFF    eDMA_0.TCD[57].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD57_NBYTES_MLNO eDMA_0.TCD[57].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD57_NBYTES_MLOFFNO eDMA_0.TCD[57].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD57_NBYTES_MLOFFYES eDMA_0.TCD[57].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD57_SLAST   eDMA_0.TCD[57].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD57_DADDR   eDMA_0.TCD[57].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD57_CITER_ELINKNO eDMA_0.TCD[57].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD57_CITER_ELINKYES eDMA_0.TCD[57].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD57_DOFF    eDMA_0.TCD[57].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD57_DLASTSGA eDMA_0.TCD[57].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD57_BITER_ELINKNO eDMA_0.TCD[57].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD57_BITER_ELINKYES eDMA_0.TCD[57].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD57_CSR     eDMA_0.TCD[57].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD58_SADDR   eDMA_0.TCD[58].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD58_ATTR    eDMA_0.TCD[58].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD58_SOFF    eDMA_0.TCD[58].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD58_NBYTES_MLNO eDMA_0.TCD[58].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD58_NBYTES_MLOFFNO eDMA_0.TCD[58].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD58_NBYTES_MLOFFYES eDMA_0.TCD[58].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD58_SLAST   eDMA_0.TCD[58].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD58_DADDR   eDMA_0.TCD[58].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD58_CITER_ELINKNO eDMA_0.TCD[58].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD58_CITER_ELINKYES eDMA_0.TCD[58].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD58_DOFF    eDMA_0.TCD[58].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD58_DLASTSGA eDMA_0.TCD[58].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD58_BITER_ELINKNO eDMA_0.TCD[58].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD58_BITER_ELINKYES eDMA_0.TCD[58].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD58_CSR     eDMA_0.TCD[58].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD59_SADDR   eDMA_0.TCD[59].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD59_ATTR    eDMA_0.TCD[59].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD59_SOFF    eDMA_0.TCD[59].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD59_NBYTES_MLNO eDMA_0.TCD[59].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD59_NBYTES_MLOFFNO eDMA_0.TCD[59].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD59_NBYTES_MLOFFYES eDMA_0.TCD[59].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD59_SLAST   eDMA_0.TCD[59].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD59_DADDR   eDMA_0.TCD[59].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD59_CITER_ELINKNO eDMA_0.TCD[59].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD59_CITER_ELINKYES eDMA_0.TCD[59].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD59_DOFF    eDMA_0.TCD[59].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD59_DLASTSGA eDMA_0.TCD[59].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD59_BITER_ELINKNO eDMA_0.TCD[59].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD59_BITER_ELINKYES eDMA_0.TCD[59].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD59_CSR     eDMA_0.TCD[59].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD60_SADDR   eDMA_0.TCD[60].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD60_ATTR    eDMA_0.TCD[60].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD60_SOFF    eDMA_0.TCD[60].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD60_NBYTES_MLNO eDMA_0.TCD[60].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD60_NBYTES_MLOFFNO eDMA_0.TCD[60].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD60_NBYTES_MLOFFYES eDMA_0.TCD[60].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD60_SLAST   eDMA_0.TCD[60].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD60_DADDR   eDMA_0.TCD[60].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD60_CITER_ELINKNO eDMA_0.TCD[60].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD60_CITER_ELINKYES eDMA_0.TCD[60].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD60_DOFF    eDMA_0.TCD[60].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD60_DLASTSGA eDMA_0.TCD[60].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD60_BITER_ELINKNO eDMA_0.TCD[60].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD60_BITER_ELINKYES eDMA_0.TCD[60].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD60_CSR     eDMA_0.TCD[60].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD61_SADDR   eDMA_0.TCD[61].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD61_ATTR    eDMA_0.TCD[61].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD61_SOFF    eDMA_0.TCD[61].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD61_NBYTES_MLNO eDMA_0.TCD[61].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD61_NBYTES_MLOFFNO eDMA_0.TCD[61].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD61_NBYTES_MLOFFYES eDMA_0.TCD[61].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD61_SLAST   eDMA_0.TCD[61].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD61_DADDR   eDMA_0.TCD[61].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD61_CITER_ELINKNO eDMA_0.TCD[61].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD61_CITER_ELINKYES eDMA_0.TCD[61].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD61_DOFF    eDMA_0.TCD[61].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD61_DLASTSGA eDMA_0.TCD[61].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD61_BITER_ELINKNO eDMA_0.TCD[61].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD61_BITER_ELINKYES eDMA_0.TCD[61].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD61_CSR     eDMA_0.TCD[61].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD62_SADDR   eDMA_0.TCD[62].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD62_ATTR    eDMA_0.TCD[62].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD62_SOFF    eDMA_0.TCD[62].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD62_NBYTES_MLNO eDMA_0.TCD[62].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD62_NBYTES_MLOFFNO eDMA_0.TCD[62].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD62_NBYTES_MLOFFYES eDMA_0.TCD[62].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD62_SLAST   eDMA_0.TCD[62].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD62_DADDR   eDMA_0.TCD[62].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD62_CITER_ELINKNO eDMA_0.TCD[62].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD62_CITER_ELINKYES eDMA_0.TCD[62].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD62_DOFF    eDMA_0.TCD[62].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD62_DLASTSGA eDMA_0.TCD[62].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD62_BITER_ELINKNO eDMA_0.TCD[62].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD62_BITER_ELINKYES eDMA_0.TCD[62].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD62_CSR     eDMA_0.TCD[62].CSR.R          /* TCD Control and Status */
#define eDMA_0_TCD63_SADDR   eDMA_0.TCD[63].SADDR.R        /* TCD Source Address */
#define eDMA_0_TCD63_ATTR    eDMA_0.TCD[63].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_0_TCD63_SOFF    eDMA_0.TCD[63].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_0_TCD63_NBYTES_MLNO eDMA_0.TCD[63].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_0_TCD63_NBYTES_MLOFFNO eDMA_0.TCD[63].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_0_TCD63_NBYTES_MLOFFYES eDMA_0.TCD[63].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_0_TCD63_SLAST   eDMA_0.TCD[63].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_0_TCD63_DADDR   eDMA_0.TCD[63].DADDR.R        /* TCD Destination Address */
#define eDMA_0_TCD63_CITER_ELINKNO eDMA_0.TCD[63].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD63_CITER_ELINKYES eDMA_0.TCD[63].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD63_DOFF    eDMA_0.TCD[63].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_0_TCD63_DLASTSGA eDMA_0.TCD[63].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_0_TCD63_BITER_ELINKNO eDMA_0.TCD[63].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_0_TCD63_BITER_ELINKYES eDMA_0.TCD[63].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_0_TCD63_CSR     eDMA_0.TCD[63].CSR.R          /* TCD Control and Status */

/* eDMA */
#define eDMA_1_CR            eDMA_1.CR.R                   /* Control Register */
#define eDMA_1_ES            eDMA_1.ES.R                   /* Error Status */
#define eDMA_1_ERQH          eDMA_1.ERQH.R                 /* Enable Request Register High */
#define eDMA_1_ERQL          eDMA_1.ERQL.R                 /* Enable Request Register Low */
#define eDMA_1_EEIH          eDMA_1.EEIH.R                 /* Enable Error Interrupt Register High */
#define eDMA_1_EEIL          eDMA_1.EEIL.R                 /* Enable Error Interrupt Register Low */
#define eDMA_1_SERQ          eDMA_1.SERQ.R                 /* Set Enable Request Register */
#define eDMA_1_CERQ          eDMA_1.CERQ.R                 /* Clear Enable Request Register */
#define eDMA_1_SEEI          eDMA_1.SEEI.R                 /* Set Enable Error Interrupt Register */
#define eDMA_1_CEEI          eDMA_1.CEEI.R                 /* Clear Enable Error Interrupt Register */
#define eDMA_1_CINT          eDMA_1.CINT.R                 /* Clear Interrupt Request Register */
#define eDMA_1_CERR          eDMA_1.CERR.R                 /* Clear Error Register */
#define eDMA_1_SSRT          eDMA_1.SSRT.R                 /* Set START Bit Register */
#define eDMA_1_CDNE          eDMA_1.CDNE.R                 /* Clear DONE Status Bit Register */
#define eDMA_1_INTH          eDMA_1.INTH.R                 /* Interrupt Request Register High */
#define eDMA_1_INTL          eDMA_1.INTL.R                 /* Interrupt Request Register Low */
#define eDMA_1_ERRH          eDMA_1.ERRH.R                 /* Error Register High */
#define eDMA_1_ERRL          eDMA_1.ERRL.R                 /* Error Register Low */
#define eDMA_1_HRSH          eDMA_1.HRSH.R                 /* Hardware Request Status Register High */
#define eDMA_1_HRSL          eDMA_1.HRSL.R                 /* Hardware Request Status Register Low */
#define eDMA_1_DCHPRI0       eDMA_1.DCHPRI[0].R            /* Channel Priority Register */
#define eDMA_1_DCHPRI1       eDMA_1.DCHPRI[1].R            /* Channel Priority Register */
#define eDMA_1_DCHPRI2       eDMA_1.DCHPRI[2].R            /* Channel Priority Register */
#define eDMA_1_DCHPRI3       eDMA_1.DCHPRI[3].R            /* Channel Priority Register */
#define eDMA_1_DCHPRI4       eDMA_1.DCHPRI[4].R            /* Channel Priority Register */
#define eDMA_1_DCHPRI5       eDMA_1.DCHPRI[5].R            /* Channel Priority Register */
#define eDMA_1_DCHPRI6       eDMA_1.DCHPRI[6].R            /* Channel Priority Register */
#define eDMA_1_DCHPRI7       eDMA_1.DCHPRI[7].R            /* Channel Priority Register */
#define eDMA_1_DCHPRI8       eDMA_1.DCHPRI[8].R            /* Channel Priority Register */
#define eDMA_1_DCHPRI9       eDMA_1.DCHPRI[9].R            /* Channel Priority Register */
#define eDMA_1_DCHPRI10      eDMA_1.DCHPRI[10].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI11      eDMA_1.DCHPRI[11].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI12      eDMA_1.DCHPRI[12].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI13      eDMA_1.DCHPRI[13].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI14      eDMA_1.DCHPRI[14].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI15      eDMA_1.DCHPRI[15].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI16      eDMA_1.DCHPRI[16].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI17      eDMA_1.DCHPRI[17].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI18      eDMA_1.DCHPRI[18].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI19      eDMA_1.DCHPRI[19].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI20      eDMA_1.DCHPRI[20].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI21      eDMA_1.DCHPRI[21].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI22      eDMA_1.DCHPRI[22].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI23      eDMA_1.DCHPRI[23].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI24      eDMA_1.DCHPRI[24].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI25      eDMA_1.DCHPRI[25].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI26      eDMA_1.DCHPRI[26].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI27      eDMA_1.DCHPRI[27].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI28      eDMA_1.DCHPRI[28].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI29      eDMA_1.DCHPRI[29].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI30      eDMA_1.DCHPRI[30].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI31      eDMA_1.DCHPRI[31].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI32      eDMA_1.DCHPRI[32].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI33      eDMA_1.DCHPRI[33].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI34      eDMA_1.DCHPRI[34].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI35      eDMA_1.DCHPRI[35].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI36      eDMA_1.DCHPRI[36].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI37      eDMA_1.DCHPRI[37].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI38      eDMA_1.DCHPRI[38].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI39      eDMA_1.DCHPRI[39].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI40      eDMA_1.DCHPRI[40].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI41      eDMA_1.DCHPRI[41].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI42      eDMA_1.DCHPRI[42].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI43      eDMA_1.DCHPRI[43].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI44      eDMA_1.DCHPRI[44].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI45      eDMA_1.DCHPRI[45].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI46      eDMA_1.DCHPRI[46].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI47      eDMA_1.DCHPRI[47].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI48      eDMA_1.DCHPRI[48].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI49      eDMA_1.DCHPRI[49].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI50      eDMA_1.DCHPRI[50].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI51      eDMA_1.DCHPRI[51].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI52      eDMA_1.DCHPRI[52].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI53      eDMA_1.DCHPRI[53].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI54      eDMA_1.DCHPRI[54].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI55      eDMA_1.DCHPRI[55].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI56      eDMA_1.DCHPRI[56].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI57      eDMA_1.DCHPRI[57].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI58      eDMA_1.DCHPRI[58].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI59      eDMA_1.DCHPRI[59].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI60      eDMA_1.DCHPRI[60].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI61      eDMA_1.DCHPRI[61].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI62      eDMA_1.DCHPRI[62].R           /* Channel Priority Register */
#define eDMA_1_DCHPRI63      eDMA_1.DCHPRI[63].R           /* Channel Priority Register */
#define eDMA_1_DCHMID0       eDMA_1.DCHMID[0].R            /* Channel Master ID Register */
#define eDMA_1_DCHMID1       eDMA_1.DCHMID[1].R            /* Channel Master ID Register */
#define eDMA_1_DCHMID2       eDMA_1.DCHMID[2].R            /* Channel Master ID Register */
#define eDMA_1_DCHMID3       eDMA_1.DCHMID[3].R            /* Channel Master ID Register */
#define eDMA_1_DCHMID4       eDMA_1.DCHMID[4].R            /* Channel Master ID Register */
#define eDMA_1_DCHMID5       eDMA_1.DCHMID[5].R            /* Channel Master ID Register */
#define eDMA_1_DCHMID6       eDMA_1.DCHMID[6].R            /* Channel Master ID Register */
#define eDMA_1_DCHMID7       eDMA_1.DCHMID[7].R            /* Channel Master ID Register */
#define eDMA_1_DCHMID8       eDMA_1.DCHMID[8].R            /* Channel Master ID Register */
#define eDMA_1_DCHMID9       eDMA_1.DCHMID[9].R            /* Channel Master ID Register */
#define eDMA_1_DCHMID10      eDMA_1.DCHMID[10].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID11      eDMA_1.DCHMID[11].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID12      eDMA_1.DCHMID[12].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID13      eDMA_1.DCHMID[13].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID14      eDMA_1.DCHMID[14].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID15      eDMA_1.DCHMID[15].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID16      eDMA_1.DCHMID[16].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID17      eDMA_1.DCHMID[17].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID18      eDMA_1.DCHMID[18].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID19      eDMA_1.DCHMID[19].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID20      eDMA_1.DCHMID[20].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID21      eDMA_1.DCHMID[21].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID22      eDMA_1.DCHMID[22].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID23      eDMA_1.DCHMID[23].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID24      eDMA_1.DCHMID[24].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID25      eDMA_1.DCHMID[25].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID26      eDMA_1.DCHMID[26].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID27      eDMA_1.DCHMID[27].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID28      eDMA_1.DCHMID[28].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID29      eDMA_1.DCHMID[29].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID30      eDMA_1.DCHMID[30].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID31      eDMA_1.DCHMID[31].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID32      eDMA_1.DCHMID[32].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID33      eDMA_1.DCHMID[33].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID34      eDMA_1.DCHMID[34].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID35      eDMA_1.DCHMID[35].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID36      eDMA_1.DCHMID[36].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID37      eDMA_1.DCHMID[37].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID38      eDMA_1.DCHMID[38].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID39      eDMA_1.DCHMID[39].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID40      eDMA_1.DCHMID[40].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID41      eDMA_1.DCHMID[41].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID42      eDMA_1.DCHMID[42].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID43      eDMA_1.DCHMID[43].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID44      eDMA_1.DCHMID[44].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID45      eDMA_1.DCHMID[45].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID46      eDMA_1.DCHMID[46].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID47      eDMA_1.DCHMID[47].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID48      eDMA_1.DCHMID[48].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID49      eDMA_1.DCHMID[49].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID50      eDMA_1.DCHMID[50].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID51      eDMA_1.DCHMID[51].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID52      eDMA_1.DCHMID[52].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID53      eDMA_1.DCHMID[53].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID54      eDMA_1.DCHMID[54].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID55      eDMA_1.DCHMID[55].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID56      eDMA_1.DCHMID[56].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID57      eDMA_1.DCHMID[57].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID58      eDMA_1.DCHMID[58].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID59      eDMA_1.DCHMID[59].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID60      eDMA_1.DCHMID[60].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID61      eDMA_1.DCHMID[61].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID62      eDMA_1.DCHMID[62].R           /* Channel Master ID Register */
#define eDMA_1_DCHMID63      eDMA_1.DCHMID[63].R           /* Channel Master ID Register */
#define eDMA_1_TCD0_SADDR    eDMA_1.TCD[0].SADDR.R         /* TCD Source Address */
#define eDMA_1_TCD0_ATTR     eDMA_1.TCD[0].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_1_TCD0_SOFF     eDMA_1.TCD[0].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_1_TCD0_NBYTES_MLNO eDMA_1.TCD[0].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD0_NBYTES_MLOFFNO eDMA_1.TCD[0].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD0_NBYTES_MLOFFYES eDMA_1.TCD[0].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD0_SLAST    eDMA_1.TCD[0].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD0_DADDR    eDMA_1.TCD[0].DADDR.R         /* TCD Destination Address */
#define eDMA_1_TCD0_CITER_ELINKNO eDMA_1.TCD[0].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD0_CITER_ELINKYES eDMA_1.TCD[0].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD0_DOFF     eDMA_1.TCD[0].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD0_DLASTSGA eDMA_1.TCD[0].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD0_BITER_ELINKNO eDMA_1.TCD[0].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD0_BITER_ELINKYES eDMA_1.TCD[0].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD0_CSR      eDMA_1.TCD[0].CSR.R           /* TCD Control and Status */
#define eDMA_1_TCD1_SADDR    eDMA_1.TCD[1].SADDR.R         /* TCD Source Address */
#define eDMA_1_TCD1_ATTR     eDMA_1.TCD[1].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_1_TCD1_SOFF     eDMA_1.TCD[1].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_1_TCD1_NBYTES_MLNO eDMA_1.TCD[1].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD1_NBYTES_MLOFFNO eDMA_1.TCD[1].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD1_NBYTES_MLOFFYES eDMA_1.TCD[1].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD1_SLAST    eDMA_1.TCD[1].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD1_DADDR    eDMA_1.TCD[1].DADDR.R         /* TCD Destination Address */
#define eDMA_1_TCD1_CITER_ELINKNO eDMA_1.TCD[1].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD1_CITER_ELINKYES eDMA_1.TCD[1].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD1_DOFF     eDMA_1.TCD[1].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD1_DLASTSGA eDMA_1.TCD[1].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD1_BITER_ELINKNO eDMA_1.TCD[1].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD1_BITER_ELINKYES eDMA_1.TCD[1].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD1_CSR      eDMA_1.TCD[1].CSR.R           /* TCD Control and Status */
#define eDMA_1_TCD2_SADDR    eDMA_1.TCD[2].SADDR.R         /* TCD Source Address */
#define eDMA_1_TCD2_ATTR     eDMA_1.TCD[2].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_1_TCD2_SOFF     eDMA_1.TCD[2].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_1_TCD2_NBYTES_MLNO eDMA_1.TCD[2].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD2_NBYTES_MLOFFNO eDMA_1.TCD[2].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD2_NBYTES_MLOFFYES eDMA_1.TCD[2].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD2_SLAST    eDMA_1.TCD[2].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD2_DADDR    eDMA_1.TCD[2].DADDR.R         /* TCD Destination Address */
#define eDMA_1_TCD2_CITER_ELINKNO eDMA_1.TCD[2].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD2_CITER_ELINKYES eDMA_1.TCD[2].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD2_DOFF     eDMA_1.TCD[2].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD2_DLASTSGA eDMA_1.TCD[2].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD2_BITER_ELINKNO eDMA_1.TCD[2].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD2_BITER_ELINKYES eDMA_1.TCD[2].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD2_CSR      eDMA_1.TCD[2].CSR.R           /* TCD Control and Status */
#define eDMA_1_TCD3_SADDR    eDMA_1.TCD[3].SADDR.R         /* TCD Source Address */
#define eDMA_1_TCD3_ATTR     eDMA_1.TCD[3].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_1_TCD3_SOFF     eDMA_1.TCD[3].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_1_TCD3_NBYTES_MLNO eDMA_1.TCD[3].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD3_NBYTES_MLOFFNO eDMA_1.TCD[3].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD3_NBYTES_MLOFFYES eDMA_1.TCD[3].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD3_SLAST    eDMA_1.TCD[3].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD3_DADDR    eDMA_1.TCD[3].DADDR.R         /* TCD Destination Address */
#define eDMA_1_TCD3_CITER_ELINKNO eDMA_1.TCD[3].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD3_CITER_ELINKYES eDMA_1.TCD[3].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD3_DOFF     eDMA_1.TCD[3].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD3_DLASTSGA eDMA_1.TCD[3].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD3_BITER_ELINKNO eDMA_1.TCD[3].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD3_BITER_ELINKYES eDMA_1.TCD[3].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD3_CSR      eDMA_1.TCD[3].CSR.R           /* TCD Control and Status */
#define eDMA_1_TCD4_SADDR    eDMA_1.TCD[4].SADDR.R         /* TCD Source Address */
#define eDMA_1_TCD4_ATTR     eDMA_1.TCD[4].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_1_TCD4_SOFF     eDMA_1.TCD[4].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_1_TCD4_NBYTES_MLNO eDMA_1.TCD[4].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD4_NBYTES_MLOFFNO eDMA_1.TCD[4].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD4_NBYTES_MLOFFYES eDMA_1.TCD[4].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD4_SLAST    eDMA_1.TCD[4].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD4_DADDR    eDMA_1.TCD[4].DADDR.R         /* TCD Destination Address */
#define eDMA_1_TCD4_CITER_ELINKNO eDMA_1.TCD[4].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD4_CITER_ELINKYES eDMA_1.TCD[4].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD4_DOFF     eDMA_1.TCD[4].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD4_DLASTSGA eDMA_1.TCD[4].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD4_BITER_ELINKNO eDMA_1.TCD[4].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD4_BITER_ELINKYES eDMA_1.TCD[4].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD4_CSR      eDMA_1.TCD[4].CSR.R           /* TCD Control and Status */
#define eDMA_1_TCD5_SADDR    eDMA_1.TCD[5].SADDR.R         /* TCD Source Address */
#define eDMA_1_TCD5_ATTR     eDMA_1.TCD[5].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_1_TCD5_SOFF     eDMA_1.TCD[5].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_1_TCD5_NBYTES_MLNO eDMA_1.TCD[5].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD5_NBYTES_MLOFFNO eDMA_1.TCD[5].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD5_NBYTES_MLOFFYES eDMA_1.TCD[5].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD5_SLAST    eDMA_1.TCD[5].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD5_DADDR    eDMA_1.TCD[5].DADDR.R         /* TCD Destination Address */
#define eDMA_1_TCD5_CITER_ELINKNO eDMA_1.TCD[5].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD5_CITER_ELINKYES eDMA_1.TCD[5].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD5_DOFF     eDMA_1.TCD[5].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD5_DLASTSGA eDMA_1.TCD[5].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD5_BITER_ELINKNO eDMA_1.TCD[5].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD5_BITER_ELINKYES eDMA_1.TCD[5].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD5_CSR      eDMA_1.TCD[5].CSR.R           /* TCD Control and Status */
#define eDMA_1_TCD6_SADDR    eDMA_1.TCD[6].SADDR.R         /* TCD Source Address */
#define eDMA_1_TCD6_ATTR     eDMA_1.TCD[6].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_1_TCD6_SOFF     eDMA_1.TCD[6].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_1_TCD6_NBYTES_MLNO eDMA_1.TCD[6].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD6_NBYTES_MLOFFNO eDMA_1.TCD[6].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD6_NBYTES_MLOFFYES eDMA_1.TCD[6].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD6_SLAST    eDMA_1.TCD[6].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD6_DADDR    eDMA_1.TCD[6].DADDR.R         /* TCD Destination Address */
#define eDMA_1_TCD6_CITER_ELINKNO eDMA_1.TCD[6].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD6_CITER_ELINKYES eDMA_1.TCD[6].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD6_DOFF     eDMA_1.TCD[6].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD6_DLASTSGA eDMA_1.TCD[6].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD6_BITER_ELINKNO eDMA_1.TCD[6].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD6_BITER_ELINKYES eDMA_1.TCD[6].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD6_CSR      eDMA_1.TCD[6].CSR.R           /* TCD Control and Status */
#define eDMA_1_TCD7_SADDR    eDMA_1.TCD[7].SADDR.R         /* TCD Source Address */
#define eDMA_1_TCD7_ATTR     eDMA_1.TCD[7].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_1_TCD7_SOFF     eDMA_1.TCD[7].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_1_TCD7_NBYTES_MLNO eDMA_1.TCD[7].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD7_NBYTES_MLOFFNO eDMA_1.TCD[7].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD7_NBYTES_MLOFFYES eDMA_1.TCD[7].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD7_SLAST    eDMA_1.TCD[7].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD7_DADDR    eDMA_1.TCD[7].DADDR.R         /* TCD Destination Address */
#define eDMA_1_TCD7_CITER_ELINKNO eDMA_1.TCD[7].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD7_CITER_ELINKYES eDMA_1.TCD[7].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD7_DOFF     eDMA_1.TCD[7].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD7_DLASTSGA eDMA_1.TCD[7].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD7_BITER_ELINKNO eDMA_1.TCD[7].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD7_BITER_ELINKYES eDMA_1.TCD[7].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD7_CSR      eDMA_1.TCD[7].CSR.R           /* TCD Control and Status */
#define eDMA_1_TCD8_SADDR    eDMA_1.TCD[8].SADDR.R         /* TCD Source Address */
#define eDMA_1_TCD8_ATTR     eDMA_1.TCD[8].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_1_TCD8_SOFF     eDMA_1.TCD[8].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_1_TCD8_NBYTES_MLNO eDMA_1.TCD[8].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD8_NBYTES_MLOFFNO eDMA_1.TCD[8].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD8_NBYTES_MLOFFYES eDMA_1.TCD[8].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD8_SLAST    eDMA_1.TCD[8].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD8_DADDR    eDMA_1.TCD[8].DADDR.R         /* TCD Destination Address */
#define eDMA_1_TCD8_CITER_ELINKNO eDMA_1.TCD[8].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD8_CITER_ELINKYES eDMA_1.TCD[8].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD8_DOFF     eDMA_1.TCD[8].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD8_DLASTSGA eDMA_1.TCD[8].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD8_BITER_ELINKNO eDMA_1.TCD[8].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD8_BITER_ELINKYES eDMA_1.TCD[8].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD8_CSR      eDMA_1.TCD[8].CSR.R           /* TCD Control and Status */
#define eDMA_1_TCD9_SADDR    eDMA_1.TCD[9].SADDR.R         /* TCD Source Address */
#define eDMA_1_TCD9_ATTR     eDMA_1.TCD[9].ATTR.R          /* TCD Transfer Attributes */
#define eDMA_1_TCD9_SOFF     eDMA_1.TCD[9].SOFF.R          /* TCD Signed Source Address Offset */
#define eDMA_1_TCD9_NBYTES_MLNO eDMA_1.TCD[9].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD9_NBYTES_MLOFFNO eDMA_1.TCD[9].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD9_NBYTES_MLOFFYES eDMA_1.TCD[9].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD9_SLAST    eDMA_1.TCD[9].SLAST.R         /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD9_DADDR    eDMA_1.TCD[9].DADDR.R         /* TCD Destination Address */
#define eDMA_1_TCD9_CITER_ELINKNO eDMA_1.TCD[9].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD9_CITER_ELINKYES eDMA_1.TCD[9].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD9_DOFF     eDMA_1.TCD[9].DOFF.R          /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD9_DLASTSGA eDMA_1.TCD[9].DLASTSGA.R      /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD9_BITER_ELINKNO eDMA_1.TCD[9].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD9_BITER_ELINKYES eDMA_1.TCD[9].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD9_CSR      eDMA_1.TCD[9].CSR.R           /* TCD Control and Status */
#define eDMA_1_TCD10_SADDR   eDMA_1.TCD[10].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD10_ATTR    eDMA_1.TCD[10].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD10_SOFF    eDMA_1.TCD[10].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD10_NBYTES_MLNO eDMA_1.TCD[10].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD10_NBYTES_MLOFFNO eDMA_1.TCD[10].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD10_NBYTES_MLOFFYES eDMA_1.TCD[10].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD10_SLAST   eDMA_1.TCD[10].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD10_DADDR   eDMA_1.TCD[10].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD10_CITER_ELINKNO eDMA_1.TCD[10].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD10_CITER_ELINKYES eDMA_1.TCD[10].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD10_DOFF    eDMA_1.TCD[10].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD10_DLASTSGA eDMA_1.TCD[10].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD10_BITER_ELINKNO eDMA_1.TCD[10].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD10_BITER_ELINKYES eDMA_1.TCD[10].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD10_CSR     eDMA_1.TCD[10].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD11_SADDR   eDMA_1.TCD[11].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD11_ATTR    eDMA_1.TCD[11].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD11_SOFF    eDMA_1.TCD[11].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD11_NBYTES_MLNO eDMA_1.TCD[11].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD11_NBYTES_MLOFFNO eDMA_1.TCD[11].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD11_NBYTES_MLOFFYES eDMA_1.TCD[11].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD11_SLAST   eDMA_1.TCD[11].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD11_DADDR   eDMA_1.TCD[11].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD11_CITER_ELINKNO eDMA_1.TCD[11].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD11_CITER_ELINKYES eDMA_1.TCD[11].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD11_DOFF    eDMA_1.TCD[11].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD11_DLASTSGA eDMA_1.TCD[11].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD11_BITER_ELINKNO eDMA_1.TCD[11].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD11_BITER_ELINKYES eDMA_1.TCD[11].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD11_CSR     eDMA_1.TCD[11].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD12_SADDR   eDMA_1.TCD[12].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD12_ATTR    eDMA_1.TCD[12].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD12_SOFF    eDMA_1.TCD[12].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD12_NBYTES_MLNO eDMA_1.TCD[12].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD12_NBYTES_MLOFFNO eDMA_1.TCD[12].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD12_NBYTES_MLOFFYES eDMA_1.TCD[12].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD12_SLAST   eDMA_1.TCD[12].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD12_DADDR   eDMA_1.TCD[12].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD12_CITER_ELINKNO eDMA_1.TCD[12].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD12_CITER_ELINKYES eDMA_1.TCD[12].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD12_DOFF    eDMA_1.TCD[12].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD12_DLASTSGA eDMA_1.TCD[12].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD12_BITER_ELINKNO eDMA_1.TCD[12].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD12_BITER_ELINKYES eDMA_1.TCD[12].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD12_CSR     eDMA_1.TCD[12].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD13_SADDR   eDMA_1.TCD[13].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD13_ATTR    eDMA_1.TCD[13].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD13_SOFF    eDMA_1.TCD[13].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD13_NBYTES_MLNO eDMA_1.TCD[13].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD13_NBYTES_MLOFFNO eDMA_1.TCD[13].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD13_NBYTES_MLOFFYES eDMA_1.TCD[13].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD13_SLAST   eDMA_1.TCD[13].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD13_DADDR   eDMA_1.TCD[13].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD13_CITER_ELINKNO eDMA_1.TCD[13].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD13_CITER_ELINKYES eDMA_1.TCD[13].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD13_DOFF    eDMA_1.TCD[13].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD13_DLASTSGA eDMA_1.TCD[13].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD13_BITER_ELINKNO eDMA_1.TCD[13].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD13_BITER_ELINKYES eDMA_1.TCD[13].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD13_CSR     eDMA_1.TCD[13].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD14_SADDR   eDMA_1.TCD[14].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD14_ATTR    eDMA_1.TCD[14].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD14_SOFF    eDMA_1.TCD[14].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD14_NBYTES_MLNO eDMA_1.TCD[14].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD14_NBYTES_MLOFFNO eDMA_1.TCD[14].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD14_NBYTES_MLOFFYES eDMA_1.TCD[14].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD14_SLAST   eDMA_1.TCD[14].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD14_DADDR   eDMA_1.TCD[14].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD14_CITER_ELINKNO eDMA_1.TCD[14].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD14_CITER_ELINKYES eDMA_1.TCD[14].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD14_DOFF    eDMA_1.TCD[14].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD14_DLASTSGA eDMA_1.TCD[14].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD14_BITER_ELINKNO eDMA_1.TCD[14].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD14_BITER_ELINKYES eDMA_1.TCD[14].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD14_CSR     eDMA_1.TCD[14].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD15_SADDR   eDMA_1.TCD[15].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD15_ATTR    eDMA_1.TCD[15].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD15_SOFF    eDMA_1.TCD[15].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD15_NBYTES_MLNO eDMA_1.TCD[15].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD15_NBYTES_MLOFFNO eDMA_1.TCD[15].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD15_NBYTES_MLOFFYES eDMA_1.TCD[15].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD15_SLAST   eDMA_1.TCD[15].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD15_DADDR   eDMA_1.TCD[15].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD15_CITER_ELINKNO eDMA_1.TCD[15].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD15_CITER_ELINKYES eDMA_1.TCD[15].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD15_DOFF    eDMA_1.TCD[15].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD15_DLASTSGA eDMA_1.TCD[15].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD15_BITER_ELINKNO eDMA_1.TCD[15].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD15_BITER_ELINKYES eDMA_1.TCD[15].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD15_CSR     eDMA_1.TCD[15].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD16_SADDR   eDMA_1.TCD[16].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD16_ATTR    eDMA_1.TCD[16].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD16_SOFF    eDMA_1.TCD[16].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD16_NBYTES_MLNO eDMA_1.TCD[16].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD16_NBYTES_MLOFFNO eDMA_1.TCD[16].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD16_NBYTES_MLOFFYES eDMA_1.TCD[16].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD16_SLAST   eDMA_1.TCD[16].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD16_DADDR   eDMA_1.TCD[16].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD16_CITER_ELINKNO eDMA_1.TCD[16].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD16_CITER_ELINKYES eDMA_1.TCD[16].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD16_DOFF    eDMA_1.TCD[16].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD16_DLASTSGA eDMA_1.TCD[16].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD16_BITER_ELINKNO eDMA_1.TCD[16].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD16_BITER_ELINKYES eDMA_1.TCD[16].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD16_CSR     eDMA_1.TCD[16].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD17_SADDR   eDMA_1.TCD[17].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD17_ATTR    eDMA_1.TCD[17].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD17_SOFF    eDMA_1.TCD[17].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD17_NBYTES_MLNO eDMA_1.TCD[17].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD17_NBYTES_MLOFFNO eDMA_1.TCD[17].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD17_NBYTES_MLOFFYES eDMA_1.TCD[17].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD17_SLAST   eDMA_1.TCD[17].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD17_DADDR   eDMA_1.TCD[17].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD17_CITER_ELINKNO eDMA_1.TCD[17].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD17_CITER_ELINKYES eDMA_1.TCD[17].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD17_DOFF    eDMA_1.TCD[17].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD17_DLASTSGA eDMA_1.TCD[17].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD17_BITER_ELINKNO eDMA_1.TCD[17].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD17_BITER_ELINKYES eDMA_1.TCD[17].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD17_CSR     eDMA_1.TCD[17].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD18_SADDR   eDMA_1.TCD[18].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD18_ATTR    eDMA_1.TCD[18].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD18_SOFF    eDMA_1.TCD[18].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD18_NBYTES_MLNO eDMA_1.TCD[18].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD18_NBYTES_MLOFFNO eDMA_1.TCD[18].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD18_NBYTES_MLOFFYES eDMA_1.TCD[18].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD18_SLAST   eDMA_1.TCD[18].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD18_DADDR   eDMA_1.TCD[18].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD18_CITER_ELINKNO eDMA_1.TCD[18].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD18_CITER_ELINKYES eDMA_1.TCD[18].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD18_DOFF    eDMA_1.TCD[18].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD18_DLASTSGA eDMA_1.TCD[18].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD18_BITER_ELINKNO eDMA_1.TCD[18].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD18_BITER_ELINKYES eDMA_1.TCD[18].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD18_CSR     eDMA_1.TCD[18].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD19_SADDR   eDMA_1.TCD[19].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD19_ATTR    eDMA_1.TCD[19].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD19_SOFF    eDMA_1.TCD[19].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD19_NBYTES_MLNO eDMA_1.TCD[19].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD19_NBYTES_MLOFFNO eDMA_1.TCD[19].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD19_NBYTES_MLOFFYES eDMA_1.TCD[19].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD19_SLAST   eDMA_1.TCD[19].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD19_DADDR   eDMA_1.TCD[19].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD19_CITER_ELINKNO eDMA_1.TCD[19].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD19_CITER_ELINKYES eDMA_1.TCD[19].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD19_DOFF    eDMA_1.TCD[19].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD19_DLASTSGA eDMA_1.TCD[19].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD19_BITER_ELINKNO eDMA_1.TCD[19].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD19_BITER_ELINKYES eDMA_1.TCD[19].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD19_CSR     eDMA_1.TCD[19].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD20_SADDR   eDMA_1.TCD[20].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD20_ATTR    eDMA_1.TCD[20].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD20_SOFF    eDMA_1.TCD[20].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD20_NBYTES_MLNO eDMA_1.TCD[20].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD20_NBYTES_MLOFFNO eDMA_1.TCD[20].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD20_NBYTES_MLOFFYES eDMA_1.TCD[20].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD20_SLAST   eDMA_1.TCD[20].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD20_DADDR   eDMA_1.TCD[20].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD20_CITER_ELINKNO eDMA_1.TCD[20].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD20_CITER_ELINKYES eDMA_1.TCD[20].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD20_DOFF    eDMA_1.TCD[20].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD20_DLASTSGA eDMA_1.TCD[20].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD20_BITER_ELINKNO eDMA_1.TCD[20].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD20_BITER_ELINKYES eDMA_1.TCD[20].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD20_CSR     eDMA_1.TCD[20].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD21_SADDR   eDMA_1.TCD[21].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD21_ATTR    eDMA_1.TCD[21].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD21_SOFF    eDMA_1.TCD[21].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD21_NBYTES_MLNO eDMA_1.TCD[21].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD21_NBYTES_MLOFFNO eDMA_1.TCD[21].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD21_NBYTES_MLOFFYES eDMA_1.TCD[21].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD21_SLAST   eDMA_1.TCD[21].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD21_DADDR   eDMA_1.TCD[21].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD21_CITER_ELINKNO eDMA_1.TCD[21].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD21_CITER_ELINKYES eDMA_1.TCD[21].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD21_DOFF    eDMA_1.TCD[21].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD21_DLASTSGA eDMA_1.TCD[21].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD21_BITER_ELINKNO eDMA_1.TCD[21].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD21_BITER_ELINKYES eDMA_1.TCD[21].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD21_CSR     eDMA_1.TCD[21].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD22_SADDR   eDMA_1.TCD[22].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD22_ATTR    eDMA_1.TCD[22].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD22_SOFF    eDMA_1.TCD[22].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD22_NBYTES_MLNO eDMA_1.TCD[22].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD22_NBYTES_MLOFFNO eDMA_1.TCD[22].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD22_NBYTES_MLOFFYES eDMA_1.TCD[22].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD22_SLAST   eDMA_1.TCD[22].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD22_DADDR   eDMA_1.TCD[22].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD22_CITER_ELINKNO eDMA_1.TCD[22].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD22_CITER_ELINKYES eDMA_1.TCD[22].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD22_DOFF    eDMA_1.TCD[22].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD22_DLASTSGA eDMA_1.TCD[22].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD22_BITER_ELINKNO eDMA_1.TCD[22].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD22_BITER_ELINKYES eDMA_1.TCD[22].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD22_CSR     eDMA_1.TCD[22].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD23_SADDR   eDMA_1.TCD[23].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD23_ATTR    eDMA_1.TCD[23].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD23_SOFF    eDMA_1.TCD[23].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD23_NBYTES_MLNO eDMA_1.TCD[23].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD23_NBYTES_MLOFFNO eDMA_1.TCD[23].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD23_NBYTES_MLOFFYES eDMA_1.TCD[23].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD23_SLAST   eDMA_1.TCD[23].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD23_DADDR   eDMA_1.TCD[23].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD23_CITER_ELINKNO eDMA_1.TCD[23].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD23_CITER_ELINKYES eDMA_1.TCD[23].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD23_DOFF    eDMA_1.TCD[23].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD23_DLASTSGA eDMA_1.TCD[23].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD23_BITER_ELINKNO eDMA_1.TCD[23].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD23_BITER_ELINKYES eDMA_1.TCD[23].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD23_CSR     eDMA_1.TCD[23].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD24_SADDR   eDMA_1.TCD[24].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD24_ATTR    eDMA_1.TCD[24].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD24_SOFF    eDMA_1.TCD[24].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD24_NBYTES_MLNO eDMA_1.TCD[24].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD24_NBYTES_MLOFFNO eDMA_1.TCD[24].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD24_NBYTES_MLOFFYES eDMA_1.TCD[24].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD24_SLAST   eDMA_1.TCD[24].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD24_DADDR   eDMA_1.TCD[24].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD24_CITER_ELINKNO eDMA_1.TCD[24].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD24_CITER_ELINKYES eDMA_1.TCD[24].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD24_DOFF    eDMA_1.TCD[24].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD24_DLASTSGA eDMA_1.TCD[24].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD24_BITER_ELINKNO eDMA_1.TCD[24].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD24_BITER_ELINKYES eDMA_1.TCD[24].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD24_CSR     eDMA_1.TCD[24].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD25_SADDR   eDMA_1.TCD[25].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD25_ATTR    eDMA_1.TCD[25].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD25_SOFF    eDMA_1.TCD[25].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD25_NBYTES_MLNO eDMA_1.TCD[25].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD25_NBYTES_MLOFFNO eDMA_1.TCD[25].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD25_NBYTES_MLOFFYES eDMA_1.TCD[25].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD25_SLAST   eDMA_1.TCD[25].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD25_DADDR   eDMA_1.TCD[25].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD25_CITER_ELINKNO eDMA_1.TCD[25].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD25_CITER_ELINKYES eDMA_1.TCD[25].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD25_DOFF    eDMA_1.TCD[25].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD25_DLASTSGA eDMA_1.TCD[25].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD25_BITER_ELINKNO eDMA_1.TCD[25].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD25_BITER_ELINKYES eDMA_1.TCD[25].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD25_CSR     eDMA_1.TCD[25].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD26_SADDR   eDMA_1.TCD[26].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD26_ATTR    eDMA_1.TCD[26].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD26_SOFF    eDMA_1.TCD[26].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD26_NBYTES_MLNO eDMA_1.TCD[26].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD26_NBYTES_MLOFFNO eDMA_1.TCD[26].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD26_NBYTES_MLOFFYES eDMA_1.TCD[26].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD26_SLAST   eDMA_1.TCD[26].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD26_DADDR   eDMA_1.TCD[26].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD26_CITER_ELINKNO eDMA_1.TCD[26].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD26_CITER_ELINKYES eDMA_1.TCD[26].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD26_DOFF    eDMA_1.TCD[26].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD26_DLASTSGA eDMA_1.TCD[26].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD26_BITER_ELINKNO eDMA_1.TCD[26].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD26_BITER_ELINKYES eDMA_1.TCD[26].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD26_CSR     eDMA_1.TCD[26].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD27_SADDR   eDMA_1.TCD[27].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD27_ATTR    eDMA_1.TCD[27].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD27_SOFF    eDMA_1.TCD[27].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD27_NBYTES_MLNO eDMA_1.TCD[27].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD27_NBYTES_MLOFFNO eDMA_1.TCD[27].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD27_NBYTES_MLOFFYES eDMA_1.TCD[27].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD27_SLAST   eDMA_1.TCD[27].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD27_DADDR   eDMA_1.TCD[27].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD27_CITER_ELINKNO eDMA_1.TCD[27].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD27_CITER_ELINKYES eDMA_1.TCD[27].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD27_DOFF    eDMA_1.TCD[27].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD27_DLASTSGA eDMA_1.TCD[27].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD27_BITER_ELINKNO eDMA_1.TCD[27].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD27_BITER_ELINKYES eDMA_1.TCD[27].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD27_CSR     eDMA_1.TCD[27].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD28_SADDR   eDMA_1.TCD[28].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD28_ATTR    eDMA_1.TCD[28].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD28_SOFF    eDMA_1.TCD[28].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD28_NBYTES_MLNO eDMA_1.TCD[28].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD28_NBYTES_MLOFFNO eDMA_1.TCD[28].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD28_NBYTES_MLOFFYES eDMA_1.TCD[28].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD28_SLAST   eDMA_1.TCD[28].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD28_DADDR   eDMA_1.TCD[28].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD28_CITER_ELINKNO eDMA_1.TCD[28].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD28_CITER_ELINKYES eDMA_1.TCD[28].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD28_DOFF    eDMA_1.TCD[28].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD28_DLASTSGA eDMA_1.TCD[28].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD28_BITER_ELINKNO eDMA_1.TCD[28].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD28_BITER_ELINKYES eDMA_1.TCD[28].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD28_CSR     eDMA_1.TCD[28].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD29_SADDR   eDMA_1.TCD[29].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD29_ATTR    eDMA_1.TCD[29].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD29_SOFF    eDMA_1.TCD[29].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD29_NBYTES_MLNO eDMA_1.TCD[29].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD29_NBYTES_MLOFFNO eDMA_1.TCD[29].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD29_NBYTES_MLOFFYES eDMA_1.TCD[29].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD29_SLAST   eDMA_1.TCD[29].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD29_DADDR   eDMA_1.TCD[29].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD29_CITER_ELINKNO eDMA_1.TCD[29].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD29_CITER_ELINKYES eDMA_1.TCD[29].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD29_DOFF    eDMA_1.TCD[29].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD29_DLASTSGA eDMA_1.TCD[29].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD29_BITER_ELINKNO eDMA_1.TCD[29].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD29_BITER_ELINKYES eDMA_1.TCD[29].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD29_CSR     eDMA_1.TCD[29].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD30_SADDR   eDMA_1.TCD[30].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD30_ATTR    eDMA_1.TCD[30].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD30_SOFF    eDMA_1.TCD[30].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD30_NBYTES_MLNO eDMA_1.TCD[30].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD30_NBYTES_MLOFFNO eDMA_1.TCD[30].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD30_NBYTES_MLOFFYES eDMA_1.TCD[30].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD30_SLAST   eDMA_1.TCD[30].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD30_DADDR   eDMA_1.TCD[30].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD30_CITER_ELINKNO eDMA_1.TCD[30].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD30_CITER_ELINKYES eDMA_1.TCD[30].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD30_DOFF    eDMA_1.TCD[30].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD30_DLASTSGA eDMA_1.TCD[30].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD30_BITER_ELINKNO eDMA_1.TCD[30].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD30_BITER_ELINKYES eDMA_1.TCD[30].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD30_CSR     eDMA_1.TCD[30].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD31_SADDR   eDMA_1.TCD[31].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD31_ATTR    eDMA_1.TCD[31].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD31_SOFF    eDMA_1.TCD[31].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD31_NBYTES_MLNO eDMA_1.TCD[31].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD31_NBYTES_MLOFFNO eDMA_1.TCD[31].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD31_NBYTES_MLOFFYES eDMA_1.TCD[31].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD31_SLAST   eDMA_1.TCD[31].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD31_DADDR   eDMA_1.TCD[31].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD31_CITER_ELINKNO eDMA_1.TCD[31].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD31_CITER_ELINKYES eDMA_1.TCD[31].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD31_DOFF    eDMA_1.TCD[31].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD31_DLASTSGA eDMA_1.TCD[31].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD31_BITER_ELINKNO eDMA_1.TCD[31].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD31_BITER_ELINKYES eDMA_1.TCD[31].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD31_CSR     eDMA_1.TCD[31].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD32_SADDR   eDMA_1.TCD[32].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD32_ATTR    eDMA_1.TCD[32].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD32_SOFF    eDMA_1.TCD[32].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD32_NBYTES_MLNO eDMA_1.TCD[32].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD32_NBYTES_MLOFFNO eDMA_1.TCD[32].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD32_NBYTES_MLOFFYES eDMA_1.TCD[32].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD32_SLAST   eDMA_1.TCD[32].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD32_DADDR   eDMA_1.TCD[32].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD32_CITER_ELINKNO eDMA_1.TCD[32].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD32_CITER_ELINKYES eDMA_1.TCD[32].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD32_DOFF    eDMA_1.TCD[32].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD32_DLASTSGA eDMA_1.TCD[32].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD32_BITER_ELINKNO eDMA_1.TCD[32].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD32_BITER_ELINKYES eDMA_1.TCD[32].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD32_CSR     eDMA_1.TCD[32].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD33_SADDR   eDMA_1.TCD[33].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD33_ATTR    eDMA_1.TCD[33].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD33_SOFF    eDMA_1.TCD[33].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD33_NBYTES_MLNO eDMA_1.TCD[33].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD33_NBYTES_MLOFFNO eDMA_1.TCD[33].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD33_NBYTES_MLOFFYES eDMA_1.TCD[33].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD33_SLAST   eDMA_1.TCD[33].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD33_DADDR   eDMA_1.TCD[33].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD33_CITER_ELINKNO eDMA_1.TCD[33].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD33_CITER_ELINKYES eDMA_1.TCD[33].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD33_DOFF    eDMA_1.TCD[33].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD33_DLASTSGA eDMA_1.TCD[33].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD33_BITER_ELINKNO eDMA_1.TCD[33].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD33_BITER_ELINKYES eDMA_1.TCD[33].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD33_CSR     eDMA_1.TCD[33].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD34_SADDR   eDMA_1.TCD[34].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD34_ATTR    eDMA_1.TCD[34].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD34_SOFF    eDMA_1.TCD[34].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD34_NBYTES_MLNO eDMA_1.TCD[34].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD34_NBYTES_MLOFFNO eDMA_1.TCD[34].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD34_NBYTES_MLOFFYES eDMA_1.TCD[34].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD34_SLAST   eDMA_1.TCD[34].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD34_DADDR   eDMA_1.TCD[34].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD34_CITER_ELINKNO eDMA_1.TCD[34].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD34_CITER_ELINKYES eDMA_1.TCD[34].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD34_DOFF    eDMA_1.TCD[34].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD34_DLASTSGA eDMA_1.TCD[34].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD34_BITER_ELINKNO eDMA_1.TCD[34].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD34_BITER_ELINKYES eDMA_1.TCD[34].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD34_CSR     eDMA_1.TCD[34].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD35_SADDR   eDMA_1.TCD[35].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD35_ATTR    eDMA_1.TCD[35].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD35_SOFF    eDMA_1.TCD[35].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD35_NBYTES_MLNO eDMA_1.TCD[35].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD35_NBYTES_MLOFFNO eDMA_1.TCD[35].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD35_NBYTES_MLOFFYES eDMA_1.TCD[35].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD35_SLAST   eDMA_1.TCD[35].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD35_DADDR   eDMA_1.TCD[35].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD35_CITER_ELINKNO eDMA_1.TCD[35].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD35_CITER_ELINKYES eDMA_1.TCD[35].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD35_DOFF    eDMA_1.TCD[35].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD35_DLASTSGA eDMA_1.TCD[35].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD35_BITER_ELINKNO eDMA_1.TCD[35].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD35_BITER_ELINKYES eDMA_1.TCD[35].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD35_CSR     eDMA_1.TCD[35].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD36_SADDR   eDMA_1.TCD[36].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD36_ATTR    eDMA_1.TCD[36].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD36_SOFF    eDMA_1.TCD[36].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD36_NBYTES_MLNO eDMA_1.TCD[36].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD36_NBYTES_MLOFFNO eDMA_1.TCD[36].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD36_NBYTES_MLOFFYES eDMA_1.TCD[36].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD36_SLAST   eDMA_1.TCD[36].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD36_DADDR   eDMA_1.TCD[36].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD36_CITER_ELINKNO eDMA_1.TCD[36].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD36_CITER_ELINKYES eDMA_1.TCD[36].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD36_DOFF    eDMA_1.TCD[36].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD36_DLASTSGA eDMA_1.TCD[36].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD36_BITER_ELINKNO eDMA_1.TCD[36].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD36_BITER_ELINKYES eDMA_1.TCD[36].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD36_CSR     eDMA_1.TCD[36].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD37_SADDR   eDMA_1.TCD[37].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD37_ATTR    eDMA_1.TCD[37].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD37_SOFF    eDMA_1.TCD[37].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD37_NBYTES_MLNO eDMA_1.TCD[37].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD37_NBYTES_MLOFFNO eDMA_1.TCD[37].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD37_NBYTES_MLOFFYES eDMA_1.TCD[37].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD37_SLAST   eDMA_1.TCD[37].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD37_DADDR   eDMA_1.TCD[37].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD37_CITER_ELINKNO eDMA_1.TCD[37].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD37_CITER_ELINKYES eDMA_1.TCD[37].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD37_DOFF    eDMA_1.TCD[37].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD37_DLASTSGA eDMA_1.TCD[37].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD37_BITER_ELINKNO eDMA_1.TCD[37].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD37_BITER_ELINKYES eDMA_1.TCD[37].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD37_CSR     eDMA_1.TCD[37].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD38_SADDR   eDMA_1.TCD[38].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD38_ATTR    eDMA_1.TCD[38].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD38_SOFF    eDMA_1.TCD[38].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD38_NBYTES_MLNO eDMA_1.TCD[38].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD38_NBYTES_MLOFFNO eDMA_1.TCD[38].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD38_NBYTES_MLOFFYES eDMA_1.TCD[38].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD38_SLAST   eDMA_1.TCD[38].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD38_DADDR   eDMA_1.TCD[38].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD38_CITER_ELINKNO eDMA_1.TCD[38].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD38_CITER_ELINKYES eDMA_1.TCD[38].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD38_DOFF    eDMA_1.TCD[38].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD38_DLASTSGA eDMA_1.TCD[38].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD38_BITER_ELINKNO eDMA_1.TCD[38].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD38_BITER_ELINKYES eDMA_1.TCD[38].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD38_CSR     eDMA_1.TCD[38].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD39_SADDR   eDMA_1.TCD[39].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD39_ATTR    eDMA_1.TCD[39].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD39_SOFF    eDMA_1.TCD[39].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD39_NBYTES_MLNO eDMA_1.TCD[39].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD39_NBYTES_MLOFFNO eDMA_1.TCD[39].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD39_NBYTES_MLOFFYES eDMA_1.TCD[39].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD39_SLAST   eDMA_1.TCD[39].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD39_DADDR   eDMA_1.TCD[39].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD39_CITER_ELINKNO eDMA_1.TCD[39].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD39_CITER_ELINKYES eDMA_1.TCD[39].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD39_DOFF    eDMA_1.TCD[39].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD39_DLASTSGA eDMA_1.TCD[39].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD39_BITER_ELINKNO eDMA_1.TCD[39].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD39_BITER_ELINKYES eDMA_1.TCD[39].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD39_CSR     eDMA_1.TCD[39].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD40_SADDR   eDMA_1.TCD[40].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD40_ATTR    eDMA_1.TCD[40].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD40_SOFF    eDMA_1.TCD[40].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD40_NBYTES_MLNO eDMA_1.TCD[40].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD40_NBYTES_MLOFFNO eDMA_1.TCD[40].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD40_NBYTES_MLOFFYES eDMA_1.TCD[40].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD40_SLAST   eDMA_1.TCD[40].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD40_DADDR   eDMA_1.TCD[40].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD40_CITER_ELINKNO eDMA_1.TCD[40].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD40_CITER_ELINKYES eDMA_1.TCD[40].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD40_DOFF    eDMA_1.TCD[40].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD40_DLASTSGA eDMA_1.TCD[40].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD40_BITER_ELINKNO eDMA_1.TCD[40].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD40_BITER_ELINKYES eDMA_1.TCD[40].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD40_CSR     eDMA_1.TCD[40].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD41_SADDR   eDMA_1.TCD[41].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD41_ATTR    eDMA_1.TCD[41].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD41_SOFF    eDMA_1.TCD[41].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD41_NBYTES_MLNO eDMA_1.TCD[41].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD41_NBYTES_MLOFFNO eDMA_1.TCD[41].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD41_NBYTES_MLOFFYES eDMA_1.TCD[41].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD41_SLAST   eDMA_1.TCD[41].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD41_DADDR   eDMA_1.TCD[41].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD41_CITER_ELINKNO eDMA_1.TCD[41].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD41_CITER_ELINKYES eDMA_1.TCD[41].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD41_DOFF    eDMA_1.TCD[41].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD41_DLASTSGA eDMA_1.TCD[41].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD41_BITER_ELINKNO eDMA_1.TCD[41].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD41_BITER_ELINKYES eDMA_1.TCD[41].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD41_CSR     eDMA_1.TCD[41].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD42_SADDR   eDMA_1.TCD[42].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD42_ATTR    eDMA_1.TCD[42].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD42_SOFF    eDMA_1.TCD[42].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD42_NBYTES_MLNO eDMA_1.TCD[42].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD42_NBYTES_MLOFFNO eDMA_1.TCD[42].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD42_NBYTES_MLOFFYES eDMA_1.TCD[42].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD42_SLAST   eDMA_1.TCD[42].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD42_DADDR   eDMA_1.TCD[42].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD42_CITER_ELINKNO eDMA_1.TCD[42].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD42_CITER_ELINKYES eDMA_1.TCD[42].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD42_DOFF    eDMA_1.TCD[42].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD42_DLASTSGA eDMA_1.TCD[42].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD42_BITER_ELINKNO eDMA_1.TCD[42].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD42_BITER_ELINKYES eDMA_1.TCD[42].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD42_CSR     eDMA_1.TCD[42].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD43_SADDR   eDMA_1.TCD[43].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD43_ATTR    eDMA_1.TCD[43].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD43_SOFF    eDMA_1.TCD[43].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD43_NBYTES_MLNO eDMA_1.TCD[43].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD43_NBYTES_MLOFFNO eDMA_1.TCD[43].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD43_NBYTES_MLOFFYES eDMA_1.TCD[43].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD43_SLAST   eDMA_1.TCD[43].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD43_DADDR   eDMA_1.TCD[43].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD43_CITER_ELINKNO eDMA_1.TCD[43].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD43_CITER_ELINKYES eDMA_1.TCD[43].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD43_DOFF    eDMA_1.TCD[43].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD43_DLASTSGA eDMA_1.TCD[43].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD43_BITER_ELINKNO eDMA_1.TCD[43].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD43_BITER_ELINKYES eDMA_1.TCD[43].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD43_CSR     eDMA_1.TCD[43].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD44_SADDR   eDMA_1.TCD[44].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD44_ATTR    eDMA_1.TCD[44].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD44_SOFF    eDMA_1.TCD[44].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD44_NBYTES_MLNO eDMA_1.TCD[44].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD44_NBYTES_MLOFFNO eDMA_1.TCD[44].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD44_NBYTES_MLOFFYES eDMA_1.TCD[44].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD44_SLAST   eDMA_1.TCD[44].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD44_DADDR   eDMA_1.TCD[44].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD44_CITER_ELINKNO eDMA_1.TCD[44].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD44_CITER_ELINKYES eDMA_1.TCD[44].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD44_DOFF    eDMA_1.TCD[44].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD44_DLASTSGA eDMA_1.TCD[44].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD44_BITER_ELINKNO eDMA_1.TCD[44].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD44_BITER_ELINKYES eDMA_1.TCD[44].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD44_CSR     eDMA_1.TCD[44].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD45_SADDR   eDMA_1.TCD[45].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD45_ATTR    eDMA_1.TCD[45].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD45_SOFF    eDMA_1.TCD[45].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD45_NBYTES_MLNO eDMA_1.TCD[45].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD45_NBYTES_MLOFFNO eDMA_1.TCD[45].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD45_NBYTES_MLOFFYES eDMA_1.TCD[45].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD45_SLAST   eDMA_1.TCD[45].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD45_DADDR   eDMA_1.TCD[45].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD45_CITER_ELINKNO eDMA_1.TCD[45].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD45_CITER_ELINKYES eDMA_1.TCD[45].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD45_DOFF    eDMA_1.TCD[45].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD45_DLASTSGA eDMA_1.TCD[45].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD45_BITER_ELINKNO eDMA_1.TCD[45].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD45_BITER_ELINKYES eDMA_1.TCD[45].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD45_CSR     eDMA_1.TCD[45].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD46_SADDR   eDMA_1.TCD[46].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD46_ATTR    eDMA_1.TCD[46].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD46_SOFF    eDMA_1.TCD[46].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD46_NBYTES_MLNO eDMA_1.TCD[46].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD46_NBYTES_MLOFFNO eDMA_1.TCD[46].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD46_NBYTES_MLOFFYES eDMA_1.TCD[46].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD46_SLAST   eDMA_1.TCD[46].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD46_DADDR   eDMA_1.TCD[46].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD46_CITER_ELINKNO eDMA_1.TCD[46].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD46_CITER_ELINKYES eDMA_1.TCD[46].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD46_DOFF    eDMA_1.TCD[46].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD46_DLASTSGA eDMA_1.TCD[46].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD46_BITER_ELINKNO eDMA_1.TCD[46].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD46_BITER_ELINKYES eDMA_1.TCD[46].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD46_CSR     eDMA_1.TCD[46].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD47_SADDR   eDMA_1.TCD[47].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD47_ATTR    eDMA_1.TCD[47].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD47_SOFF    eDMA_1.TCD[47].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD47_NBYTES_MLNO eDMA_1.TCD[47].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD47_NBYTES_MLOFFNO eDMA_1.TCD[47].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD47_NBYTES_MLOFFYES eDMA_1.TCD[47].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD47_SLAST   eDMA_1.TCD[47].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD47_DADDR   eDMA_1.TCD[47].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD47_CITER_ELINKNO eDMA_1.TCD[47].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD47_CITER_ELINKYES eDMA_1.TCD[47].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD47_DOFF    eDMA_1.TCD[47].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD47_DLASTSGA eDMA_1.TCD[47].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD47_BITER_ELINKNO eDMA_1.TCD[47].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD47_BITER_ELINKYES eDMA_1.TCD[47].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD47_CSR     eDMA_1.TCD[47].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD48_SADDR   eDMA_1.TCD[48].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD48_ATTR    eDMA_1.TCD[48].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD48_SOFF    eDMA_1.TCD[48].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD48_NBYTES_MLNO eDMA_1.TCD[48].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD48_NBYTES_MLOFFNO eDMA_1.TCD[48].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD48_NBYTES_MLOFFYES eDMA_1.TCD[48].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD48_SLAST   eDMA_1.TCD[48].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD48_DADDR   eDMA_1.TCD[48].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD48_CITER_ELINKNO eDMA_1.TCD[48].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD48_CITER_ELINKYES eDMA_1.TCD[48].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD48_DOFF    eDMA_1.TCD[48].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD48_DLASTSGA eDMA_1.TCD[48].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD48_BITER_ELINKNO eDMA_1.TCD[48].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD48_BITER_ELINKYES eDMA_1.TCD[48].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD48_CSR     eDMA_1.TCD[48].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD49_SADDR   eDMA_1.TCD[49].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD49_ATTR    eDMA_1.TCD[49].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD49_SOFF    eDMA_1.TCD[49].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD49_NBYTES_MLNO eDMA_1.TCD[49].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD49_NBYTES_MLOFFNO eDMA_1.TCD[49].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD49_NBYTES_MLOFFYES eDMA_1.TCD[49].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD49_SLAST   eDMA_1.TCD[49].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD49_DADDR   eDMA_1.TCD[49].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD49_CITER_ELINKNO eDMA_1.TCD[49].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD49_CITER_ELINKYES eDMA_1.TCD[49].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD49_DOFF    eDMA_1.TCD[49].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD49_DLASTSGA eDMA_1.TCD[49].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD49_BITER_ELINKNO eDMA_1.TCD[49].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD49_BITER_ELINKYES eDMA_1.TCD[49].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD49_CSR     eDMA_1.TCD[49].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD50_SADDR   eDMA_1.TCD[50].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD50_ATTR    eDMA_1.TCD[50].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD50_SOFF    eDMA_1.TCD[50].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD50_NBYTES_MLNO eDMA_1.TCD[50].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD50_NBYTES_MLOFFNO eDMA_1.TCD[50].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD50_NBYTES_MLOFFYES eDMA_1.TCD[50].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD50_SLAST   eDMA_1.TCD[50].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD50_DADDR   eDMA_1.TCD[50].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD50_CITER_ELINKNO eDMA_1.TCD[50].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD50_CITER_ELINKYES eDMA_1.TCD[50].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD50_DOFF    eDMA_1.TCD[50].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD50_DLASTSGA eDMA_1.TCD[50].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD50_BITER_ELINKNO eDMA_1.TCD[50].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD50_BITER_ELINKYES eDMA_1.TCD[50].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD50_CSR     eDMA_1.TCD[50].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD51_SADDR   eDMA_1.TCD[51].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD51_ATTR    eDMA_1.TCD[51].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD51_SOFF    eDMA_1.TCD[51].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD51_NBYTES_MLNO eDMA_1.TCD[51].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD51_NBYTES_MLOFFNO eDMA_1.TCD[51].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD51_NBYTES_MLOFFYES eDMA_1.TCD[51].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD51_SLAST   eDMA_1.TCD[51].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD51_DADDR   eDMA_1.TCD[51].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD51_CITER_ELINKNO eDMA_1.TCD[51].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD51_CITER_ELINKYES eDMA_1.TCD[51].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD51_DOFF    eDMA_1.TCD[51].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD51_DLASTSGA eDMA_1.TCD[51].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD51_BITER_ELINKNO eDMA_1.TCD[51].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD51_BITER_ELINKYES eDMA_1.TCD[51].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD51_CSR     eDMA_1.TCD[51].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD52_SADDR   eDMA_1.TCD[52].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD52_ATTR    eDMA_1.TCD[52].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD52_SOFF    eDMA_1.TCD[52].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD52_NBYTES_MLNO eDMA_1.TCD[52].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD52_NBYTES_MLOFFNO eDMA_1.TCD[52].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD52_NBYTES_MLOFFYES eDMA_1.TCD[52].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD52_SLAST   eDMA_1.TCD[52].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD52_DADDR   eDMA_1.TCD[52].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD52_CITER_ELINKNO eDMA_1.TCD[52].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD52_CITER_ELINKYES eDMA_1.TCD[52].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD52_DOFF    eDMA_1.TCD[52].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD52_DLASTSGA eDMA_1.TCD[52].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD52_BITER_ELINKNO eDMA_1.TCD[52].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD52_BITER_ELINKYES eDMA_1.TCD[52].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD52_CSR     eDMA_1.TCD[52].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD53_SADDR   eDMA_1.TCD[53].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD53_ATTR    eDMA_1.TCD[53].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD53_SOFF    eDMA_1.TCD[53].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD53_NBYTES_MLNO eDMA_1.TCD[53].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD53_NBYTES_MLOFFNO eDMA_1.TCD[53].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD53_NBYTES_MLOFFYES eDMA_1.TCD[53].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD53_SLAST   eDMA_1.TCD[53].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD53_DADDR   eDMA_1.TCD[53].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD53_CITER_ELINKNO eDMA_1.TCD[53].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD53_CITER_ELINKYES eDMA_1.TCD[53].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD53_DOFF    eDMA_1.TCD[53].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD53_DLASTSGA eDMA_1.TCD[53].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD53_BITER_ELINKNO eDMA_1.TCD[53].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD53_BITER_ELINKYES eDMA_1.TCD[53].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD53_CSR     eDMA_1.TCD[53].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD54_SADDR   eDMA_1.TCD[54].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD54_ATTR    eDMA_1.TCD[54].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD54_SOFF    eDMA_1.TCD[54].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD54_NBYTES_MLNO eDMA_1.TCD[54].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD54_NBYTES_MLOFFNO eDMA_1.TCD[54].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD54_NBYTES_MLOFFYES eDMA_1.TCD[54].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD54_SLAST   eDMA_1.TCD[54].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD54_DADDR   eDMA_1.TCD[54].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD54_CITER_ELINKNO eDMA_1.TCD[54].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD54_CITER_ELINKYES eDMA_1.TCD[54].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD54_DOFF    eDMA_1.TCD[54].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD54_DLASTSGA eDMA_1.TCD[54].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD54_BITER_ELINKNO eDMA_1.TCD[54].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD54_BITER_ELINKYES eDMA_1.TCD[54].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD54_CSR     eDMA_1.TCD[54].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD55_SADDR   eDMA_1.TCD[55].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD55_ATTR    eDMA_1.TCD[55].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD55_SOFF    eDMA_1.TCD[55].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD55_NBYTES_MLNO eDMA_1.TCD[55].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD55_NBYTES_MLOFFNO eDMA_1.TCD[55].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD55_NBYTES_MLOFFYES eDMA_1.TCD[55].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD55_SLAST   eDMA_1.TCD[55].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD55_DADDR   eDMA_1.TCD[55].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD55_CITER_ELINKNO eDMA_1.TCD[55].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD55_CITER_ELINKYES eDMA_1.TCD[55].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD55_DOFF    eDMA_1.TCD[55].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD55_DLASTSGA eDMA_1.TCD[55].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD55_BITER_ELINKNO eDMA_1.TCD[55].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD55_BITER_ELINKYES eDMA_1.TCD[55].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD55_CSR     eDMA_1.TCD[55].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD56_SADDR   eDMA_1.TCD[56].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD56_ATTR    eDMA_1.TCD[56].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD56_SOFF    eDMA_1.TCD[56].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD56_NBYTES_MLNO eDMA_1.TCD[56].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD56_NBYTES_MLOFFNO eDMA_1.TCD[56].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD56_NBYTES_MLOFFYES eDMA_1.TCD[56].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD56_SLAST   eDMA_1.TCD[56].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD56_DADDR   eDMA_1.TCD[56].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD56_CITER_ELINKNO eDMA_1.TCD[56].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD56_CITER_ELINKYES eDMA_1.TCD[56].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD56_DOFF    eDMA_1.TCD[56].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD56_DLASTSGA eDMA_1.TCD[56].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD56_BITER_ELINKNO eDMA_1.TCD[56].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD56_BITER_ELINKYES eDMA_1.TCD[56].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD56_CSR     eDMA_1.TCD[56].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD57_SADDR   eDMA_1.TCD[57].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD57_ATTR    eDMA_1.TCD[57].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD57_SOFF    eDMA_1.TCD[57].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD57_NBYTES_MLNO eDMA_1.TCD[57].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD57_NBYTES_MLOFFNO eDMA_1.TCD[57].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD57_NBYTES_MLOFFYES eDMA_1.TCD[57].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD57_SLAST   eDMA_1.TCD[57].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD57_DADDR   eDMA_1.TCD[57].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD57_CITER_ELINKNO eDMA_1.TCD[57].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD57_CITER_ELINKYES eDMA_1.TCD[57].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD57_DOFF    eDMA_1.TCD[57].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD57_DLASTSGA eDMA_1.TCD[57].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD57_BITER_ELINKNO eDMA_1.TCD[57].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD57_BITER_ELINKYES eDMA_1.TCD[57].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD57_CSR     eDMA_1.TCD[57].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD58_SADDR   eDMA_1.TCD[58].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD58_ATTR    eDMA_1.TCD[58].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD58_SOFF    eDMA_1.TCD[58].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD58_NBYTES_MLNO eDMA_1.TCD[58].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD58_NBYTES_MLOFFNO eDMA_1.TCD[58].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD58_NBYTES_MLOFFYES eDMA_1.TCD[58].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD58_SLAST   eDMA_1.TCD[58].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD58_DADDR   eDMA_1.TCD[58].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD58_CITER_ELINKNO eDMA_1.TCD[58].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD58_CITER_ELINKYES eDMA_1.TCD[58].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD58_DOFF    eDMA_1.TCD[58].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD58_DLASTSGA eDMA_1.TCD[58].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD58_BITER_ELINKNO eDMA_1.TCD[58].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD58_BITER_ELINKYES eDMA_1.TCD[58].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD58_CSR     eDMA_1.TCD[58].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD59_SADDR   eDMA_1.TCD[59].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD59_ATTR    eDMA_1.TCD[59].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD59_SOFF    eDMA_1.TCD[59].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD59_NBYTES_MLNO eDMA_1.TCD[59].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD59_NBYTES_MLOFFNO eDMA_1.TCD[59].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD59_NBYTES_MLOFFYES eDMA_1.TCD[59].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD59_SLAST   eDMA_1.TCD[59].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD59_DADDR   eDMA_1.TCD[59].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD59_CITER_ELINKNO eDMA_1.TCD[59].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD59_CITER_ELINKYES eDMA_1.TCD[59].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD59_DOFF    eDMA_1.TCD[59].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD59_DLASTSGA eDMA_1.TCD[59].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD59_BITER_ELINKNO eDMA_1.TCD[59].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD59_BITER_ELINKYES eDMA_1.TCD[59].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD59_CSR     eDMA_1.TCD[59].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD60_SADDR   eDMA_1.TCD[60].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD60_ATTR    eDMA_1.TCD[60].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD60_SOFF    eDMA_1.TCD[60].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD60_NBYTES_MLNO eDMA_1.TCD[60].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD60_NBYTES_MLOFFNO eDMA_1.TCD[60].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD60_NBYTES_MLOFFYES eDMA_1.TCD[60].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD60_SLAST   eDMA_1.TCD[60].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD60_DADDR   eDMA_1.TCD[60].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD60_CITER_ELINKNO eDMA_1.TCD[60].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD60_CITER_ELINKYES eDMA_1.TCD[60].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD60_DOFF    eDMA_1.TCD[60].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD60_DLASTSGA eDMA_1.TCD[60].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD60_BITER_ELINKNO eDMA_1.TCD[60].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD60_BITER_ELINKYES eDMA_1.TCD[60].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD60_CSR     eDMA_1.TCD[60].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD61_SADDR   eDMA_1.TCD[61].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD61_ATTR    eDMA_1.TCD[61].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD61_SOFF    eDMA_1.TCD[61].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD61_NBYTES_MLNO eDMA_1.TCD[61].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD61_NBYTES_MLOFFNO eDMA_1.TCD[61].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD61_NBYTES_MLOFFYES eDMA_1.TCD[61].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD61_SLAST   eDMA_1.TCD[61].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD61_DADDR   eDMA_1.TCD[61].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD61_CITER_ELINKNO eDMA_1.TCD[61].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD61_CITER_ELINKYES eDMA_1.TCD[61].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD61_DOFF    eDMA_1.TCD[61].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD61_DLASTSGA eDMA_1.TCD[61].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD61_BITER_ELINKNO eDMA_1.TCD[61].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD61_BITER_ELINKYES eDMA_1.TCD[61].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD61_CSR     eDMA_1.TCD[61].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD62_SADDR   eDMA_1.TCD[62].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD62_ATTR    eDMA_1.TCD[62].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD62_SOFF    eDMA_1.TCD[62].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD62_NBYTES_MLNO eDMA_1.TCD[62].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD62_NBYTES_MLOFFNO eDMA_1.TCD[62].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD62_NBYTES_MLOFFYES eDMA_1.TCD[62].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD62_SLAST   eDMA_1.TCD[62].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD62_DADDR   eDMA_1.TCD[62].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD62_CITER_ELINKNO eDMA_1.TCD[62].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD62_CITER_ELINKYES eDMA_1.TCD[62].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD62_DOFF    eDMA_1.TCD[62].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD62_DLASTSGA eDMA_1.TCD[62].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD62_BITER_ELINKNO eDMA_1.TCD[62].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD62_BITER_ELINKYES eDMA_1.TCD[62].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD62_CSR     eDMA_1.TCD[62].CSR.R          /* TCD Control and Status */
#define eDMA_1_TCD63_SADDR   eDMA_1.TCD[63].SADDR.R        /* TCD Source Address */
#define eDMA_1_TCD63_ATTR    eDMA_1.TCD[63].ATTR.R         /* TCD Transfer Attributes */
#define eDMA_1_TCD63_SOFF    eDMA_1.TCD[63].SOFF.R         /* TCD Signed Source Address Offset */
#define eDMA_1_TCD63_NBYTES_MLNO eDMA_1.TCD[63].NBYTES.MLNO.R /* TCD Minor Byte Count Minor Loop Disabled */
#define eDMA_1_TCD63_NBYTES_MLOFFNO eDMA_1.TCD[63].NBYTES.MLOFFNO.R /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
#define eDMA_1_TCD63_NBYTES_MLOFFYES eDMA_1.TCD[63].NBYTES.MLOFFYES.R /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
#define eDMA_1_TCD63_SLAST   eDMA_1.TCD[63].SLAST.R        /* TCD Last Source Address Adjustment */
#define eDMA_1_TCD63_DADDR   eDMA_1.TCD[63].DADDR.R        /* TCD Destination Address */
#define eDMA_1_TCD63_CITER_ELINKNO eDMA_1.TCD[63].CITER.ELINKNO.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD63_CITER_ELINKYES eDMA_1.TCD[63].CITER.ELINKYES.R /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD63_DOFF    eDMA_1.TCD[63].DOFF.R         /* TCD Signed Destination Address Offset */
#define eDMA_1_TCD63_DLASTSGA eDMA_1.TCD[63].DLASTSGA.R    /* TCD Last Destination Address Adjustment/Scatter Gather Address */
#define eDMA_1_TCD63_BITER_ELINKNO eDMA_1.TCD[63].BITER.ELINKNO.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
#define eDMA_1_TCD63_BITER_ELINKYES eDMA_1.TCD[63].BITER.ELINKYES.R /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
#define eDMA_1_TCD63_CSR     eDMA_1.TCD[63].CSR.R          /* TCD Control and Status */

#ifdef __MWERKS__
#pragma pop
#endif
#ifdef __ghs__
#pragma ghs endnowarning
#endif
#ifdef  __cplusplus
}
#endif
#endif /* ifdef _MPC5777M_H */
