/*!
\page TU1 TU1 (TimerUnit_LDD)
**          This TimerUnit component provides a low level API for unified hardware access across
**          various timer devices using the Prescaler-Counter-Compare-Capture timer structure.

- \subpage TU1_settings
- \subpage TU1_regs_overview  
- \subpage TU1_regs_details
- \ref TU1_module "Component documentation" 

\page TU1_regs_overview Registers Initialization Overview
This page initialization values for the registers of the peripheral(s) configured
by the component. 
<table>
<tr><td colspan="4" class="ttitle1">TU1 Initialization</td></tr>
<tr><td class="ttitle2">Address</td><td class="ttitle2">Register</td><td class="ttitle2">Register Value</td><td class="ttitle2">Register Description</td></tr>
<tr><td>0x0000E40E</td><td>SIM_PCE2</td><td>
    0x00000008
 </td><td>SIM_PCE2 register, peripheral TU1.</td></tr>
<tr><td>0x0000E100</td><td>PIT0_CTRL</td><td>
    0x00000001
 </td><td>PIT0_CTRL register, peripheral TU1.</td></tr>
<tr><td>0x0000E101</td><td>PIT0_MOD</td><td>
    0x000003E8
 </td><td>PIT0_MOD register, peripheral TU1.</td></tr>
</table>
<br/>
\page TU1_regs_details Register Initialization Details
This page contains detailed description of initialization values for the 
registers of the peripheral(s) configured by the component. 

<div class="reghdr1">SIM_PCE2</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">CMPA</td><td colspan="1" rowspan="2">CMPB</td><td colspan="1" rowspan="2">CMPC</td>
<td colspan="1" rowspan="2">CMPD</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">CYCADC</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">CRC</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">PIT0</td><td colspan="1" rowspan="2">PIT1</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x0000E40E</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x00000008</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00000000</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>12</td><td>CMPA</td><td>0x00</td><td>CMPA IPBus Clock Enable (enables both CMP and 6-bit reference DAC)</td>
<tr><td>11</td><td>CMPB</td><td>0x00</td><td>CMPB IPBus Clock Enable (enables both CMP and 6-bit reference DAC)</td>
<tr><td>10</td><td>CMPC</td><td>0x00</td><td>CMPC IPBus Clock Enable (enables both CMP and 6-bit reference DAC)</td>
<tr><td>9</td><td>CMPD</td><td>0x00</td><td>CMPD IPBus Clock Enable (enables both CMP and 6-bit reference DAC)</td>
<tr><td>7</td><td>CYCADC</td><td>0x00</td><td>Cyclic ADC IPBus Clock Enable</td>
<tr><td>5</td><td>CRC</td><td>0x00</td><td>CRC IPBus Clock Enable</td>
<tr><td>3</td><td>PIT0</td><td>0x01</td><td>Programmable Interval Timer IPBus Clock Enable</td>
<tr><td>2</td><td>PIT1</td><td>0x00</td><td>Programmable Interval Timer IPBus Clock Enable</td>
</tr></table>
<div class="reghdr1">PIT0_CTRL</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">SLAVE</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="2" rowspan="2">CLKSEL</td><td colspan="1" rowspan="2">-</td>
<td colspan="4" rowspan="2">PRESCALER</td><td colspan="1" rowspan="2">PRF</td><td colspan="1" rowspan="2">PRIE</td>
<td colspan="1" rowspan="2">CNT_EN</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x0000E100</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x00000001</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00000000</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>15</td><td>SLAVE</td><td>0x00</td><td>This field is used to place this PIT module in slave mode. This means that the CNT_EN field is ignored and instead this PIT uses the master count enable signal broadcast from the PIT0 module. This bit allows synchronization of the counts across multiple PIT modules. This bit is only useful in designs with multiple PIT modules. Setting this bit in the (master) PIT0 module has no effect as its own CNT_EN field is also the master count enable</td>
<tr><td>8 - 9</td><td>CLKSEL</td><td>0x00</td><td>This field is used to select the source of the clocking for the counter. This field should not be changed when CNT_EN is set. The default selection is the IPBus clock</td>
<tr><td>3 - 6</td><td>PRESCALER</td><td>0x00</td><td>This field is used to select the prescaling of the selected clock to determine the counting rate of the PIT</td>
<tr><td>2</td><td>PRF</td><td>0x00</td><td>PIT Roll-Over Flag</td>
<tr><td>1</td><td>PRIE</td><td>0x00</td><td>PIT Roll-Over Interrupt Enable</td>
<tr><td>0</td><td>CNT_EN</td><td>0x01</td><td>Count Enable</td>
</tr></table>
<div class="reghdr1">PIT0_MOD</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="16" rowspan="2">MODULO_VALUE</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x0000E101</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x000003E8</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00000000</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>0 - 15</td><td>MODULO_VALUE</td><td>0x00</td><td>This read/write register stores the modulo value for the PIT counter. When the PIT counter rolls over to 0x0000 from this value, the PRF bit becomes set and the PIT counter resumes counting from 0x0000</td>
</tr></table>
*/
/*!
\page TU1_settings Component Settings
\code
**          Component name                                 : TU1
**          Module name                                    : PIT0
**          Counter                                        : PIT0_CNTR
**          Counter direction                              : Up
**          Counter width                                  : 16 bits
**          Value type                                     : Optimal
**          Input clock source                             : Internal
**            Counter frequency                            : Auto select
**          Counter restart                                : On-match
**            Period device                                : PIT0_MOD
**            Period                                       : 100 kHz
**            Interrupt                                    : Disabled
**          Channel list                                   : 0
**          Initialization                                 : 
**            Enabled in init. code                        : yes
**            Auto initialization                          : no
**            Event mask                                   : 
**              OnCounterRestart                           : Disabled
**              OnChannel0                                 : Disabled
**              OnChannel1                                 : Disabled
**              OnChannel2                                 : Disabled
**              OnChannel3                                 : Disabled
**              OnChannel4                                 : Disabled
**              OnChannel5                                 : Disabled
**              OnChannel6                                 : Disabled
**              OnChannel7                                 : Disabled
**          CPU clock/configuration selection              : 
**            Clock configuration 0                        : This component enabled
**            Clock configuration 1                        : This component disabled
**            Clock configuration 2                        : This component disabled
**            Clock configuration 3                        : This component disabled
**            Clock configuration 4                        : This component disabled
**            Clock configuration 5                        : This component disabled
**            Clock configuration 6                        : This component disabled
**            Clock configuration 7                        : This component disabled
\endcode
*/
