/** ###################################################################
**     THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename    : Cpu.c
**     Project     : ramISR
**     Processor   : MC56F82748VLH
**     Component   : MC56F82748VLH
**     Version     : Component 01.055, Driver 01.00, CPU db: 3.50.001
**     Datasheet   : MC56F827XXRM Rev.1 Draft A 02/2012
**     Compiler    : CodeWarrior DSP C Compiler
**     Date/Time   : 2015-03-20, 21:55, # CodeGen: 115
**     Abstract    :
**
**     Settings    :
**
**     Contents    :
**         EnableInt   - void Cpu_EnableInt(void);
**         DisableInt  - void Cpu_DisableInt(void);
**         SetWaitMode - void Cpu_SetWaitMode(void);
**         SetStopMode - void Cpu_SetStopMode(void);
**
**     (c) Freescale Semiconductor, Inc.
**     2004 All Rights Reserved
**
**     Copyright : 1997 - 2014 Freescale Semiconductor, Inc. 
**     All Rights Reserved.
**     
**     Redistribution and use in source and binary forms, with or without modification,
**     are permitted provided that the following conditions are met:
**     
**     o Redistributions of source code must retain the above copyright notice, this list
**       of conditions and the following disclaimer.
**     
**     o Redistributions in binary form must reproduce the above copyright notice, this
**       list of conditions and the following disclaimer in the documentation and/or
**       other materials provided with the distribution.
**     
**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
**       contributors may be used to endorse or promote products derived from this
**       software without specific prior written permission.
**     
**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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** ###################################################################*/
/*!
** @file Cpu.c
** @version 01.00
** @brief
**
*/         
/*!
**  @addtogroup Cpu_module Cpu module documentation
**  @{
*/         

/* MODULE Cpu. */

/* {Default RTOS Adapter} No RTOS includes */
#include "Cpu.h"
#include "Events.h"
#include "Init_Config.h"

#ifdef __cplusplus
extern "C" {
#endif



/*
** ===================================================================
**     Method      :  Common_Init (component MC56F82748VLH)
**     Description :
**         Initialization of registers for that there is no 
**         initialization component.
**     Parameters  : None
**     Returns     : Nothing
** ===================================================================
*/
#if CPU_COMMON_INIT
void Common_Init(void)
{
  /* Common initialization of registers which initialization is required 
     for proper functionality of components in the project but initialization
     component which would be configuring these registers is missing 
     in the project. 
     Add associated initialization component to the project to avoid 
     initialization of registers in the Common_Init().
     Also, after reset value optimization property affects initialization of 
     registers in this method (see active generator configuration 
     Optimizations\Utilize after reset values property or enabled processor 
     component Common settings\Utilize after reset values property) */
  /* Enable clock gate of peripherals initialized in Common_Init() */
  /* SIM_PCE0: GPIOE=1 */
  PeriphSetBitMask16(SIM_PCE0, SIM_PCE0_GPIOE_MASK);

  /* GPIOE_PER: PE&=~1,PE|=2 */
  PeriphSetBits16(GPIOE_PER, GPIO_PER_PE(0x01), GPIO_PER_PE(0x02));
  /* GPIOE_SRE: SRE&=~1 */
  PeriphClearBitMask16(GPIOE_SRE, GPIO_SRE_SRE(0x01));
  /* INTC_IPR8: PWMA_CAP=0,PWMA_RERR=0,PWMA_FAULT=0 */
  PeriphClearBitMask16(INTC_IPR8, \
    INTC_IPR8_PWMA_CAP(0x03) | \
    INTC_IPR8_PWMA_RERR(0x03) | \
    INTC_IPR8_PWMA_FAULT(0x03) \
  );
  /* INTC_IPR9: PWMA_CMP0=0,PWMA_RELOAD0=2 */
  PeriphSetBits16(INTC_IPR9, \
    INTC_IPR9_PWMA_CMP0(0x03) | \
    INTC_IPR9_PWMA_RELOAD0(0x01),  \
    INTC_IPR9_PWMA_RELOAD0(0x02) \
  );
  /* SIM_PCE3: PWMACH0=1,PWMACH1=0,PWMACH2=0,PWMACH3=0 */
  PeriphSetBits16(SIM_PCE3, \
    SIM_PCE3_PWMACH1_MASK | \
    SIM_PCE3_PWMACH2_MASK | \
    SIM_PCE3_PWMACH3_MASK,  \
    SIM_PCE3_PWMACH0_MASK \
  );

  /* Disable clock gate of peripherals initialized in Common_Init() */
  /* SIM_PCE0: GPIOE=0 */
  PeriphClearBitMask16(SIM_PCE0, SIM_PCE0_GPIOE_MASK);
}

#endif /* CPU_COMMON_INIT */

/*
** ===================================================================
**     Method      :  Components_Init (component MC56F82748VLH)
**     Description :
**         Initialization of components (with exception for Peripheral
**         Initialization Components which are initialized in 
**         Peripherals_Init() method).
**         For example, if automatic initialization feature 
**         is enabled in LDD component then its Init method call 
**         is executed in Components_Init() method.
**     Parameters  : None
**     Returns     : Nothing
** ===================================================================
*/
#if CPU_COMPONENTS_INIT
void Components_Init(void)
{
  /* ### BitIO_LDD "BitIoLdd1" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  (void)BitIoLdd1_Init(NULL);
}
#endif /* CPU_COMPONENTS_INIT */


#ifdef __cplusplus
}
#endif

/* END Cpu. */

