/* ###################################################################
**     THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename    : PWMA_Config.h
**     Project     : ramISR
**     Processor   : MC56F82748VLH
**     Component   : Init_eFlexPWM
**     Version     : Component 01.000, Driver 01.00, CPU db: 3.50.001
**     Compiler    : CodeWarrior DSP C Compiler
**     Date/Time   : 2015-05-14, 14:03, # CodeGen: 62
**     Abstract    :
**          This file implements the eFlexPWM (PWMA) module initialization
**          according to the Peripheral Initialization settings, and
**          defines interrupt service routines prototypes.
**     Settings    :
**          Component name                                 : PWMA
**          Device                                         : PWMA
**          Settings                                       : 
**            Submodule 0                                  : Enabled
**              Clock setting                              : 
**                PWM clock source                         : IP Bus clock
**                PWM generator clock                      : Enabled
**                PWM prescaler                            : 1
**                Module clock                             : 100 MHz
**                Init counter value                       : 1
**                PWM value 0 - half cycle point           : 0
**                PWM value 1 - counter modulo             : 1000
**                Fractional circuit power up              : Disabled
**                Fractional value 1 circuit               : Disabled
**                Fractional value 1                       : 0
**                Dead time value 0                        : 0
**                Dead time value 1                        : 0
**                PWM frequency                            : 100.0000 kHz
**                PWM period                               : 10.0000 us
**                PWM dead time 0                          : 0
**                PWM dead time 1                          : 0
**              Enabled in Wait mode                       : no
**              Enabled in Debug mode                      : no
**              Channel settings                           : 
**                Mode of PWM ch A and B                   : Complementary
**                Complementary PWM source                 : PWM23
**                Double switching                         : Disabled
**                Split DBLPWM to channel A and B          : Disabled
**                Channel A (PWM23)                        : 
**                  PWM function                           : 
**                    PWM value 2                          : 500
**                    Fractional value 2 and 3 circuit     : Disabled
**                    Fractional value 2                   : 0
**                    PWM value 3                          : 1000
**                    Fractional value 3                   : 0
**                    SW output                            : Logic 0
**                    Deadtime source                      : Generated PWM
**                    Output fault state                   : Forced to 0 prior to output polarity
**                    Output polarity                      : Not inverted
**                    Channel masked                       : no
**                    Channel output                       : Enabled
**                    Fault channel 0                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : no
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                    Fault channel 1                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : no
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                  E-capture function                     : 
**                    FIFOs water mark level               : 0
**                    Edge counter                         : Disabled
**                    Edge compare                         : 0
**                    Input select A                       : Raw PWMA input signal
**                    Capture 0 circuitry                  : Disabled
**                    Capture 1 circuitry                  : Disabled
**                    Capture circuitry mode               : Free running
**                    Input capture process                : Disabled
**                Channel B (PWM45)                        : 
**                  PWM function                           : 
**                    PWM value 4                          : 0
**                    Fractional value 4 and 5 circuit     : Disabled
**                    Fractional value 4                   : 0
**                    PWM value 5                          : 0
**                    Fractional value 5                   : 0
**                    SW output                            : Logic 0
**                    Deadtime source                      : Generated PWM
**                    Output fault state                   : Forced to 0 prior to output polarity
**                    Output polarity                      : Not inverted
**                    Channel masked                       : no
**                    Channel output                       : Disabled
**                    Fault channel 0                      : 
**                      Disable by fault 0                 : yes
**                      Disable by fault 1                 : yes
**                      Disable by fault 2                 : yes
**                      Disable by fault 3                 : yes
**                    Fault channel 1                      : 
**                      Disable by fault 0                 : yes
**                      Disable by fault 1                 : yes
**                      Disable by fault 2                 : yes
**                      Disable by fault 3                 : yes
**                  E-capture function                     : 
**                    FIFOs water mark level               : 0
**                    Edge counter                         : Disabled
**                    Edge compare                         : 0
**                    Input select B                       : Raw PWMB input signal
**                    Capture 0 circuitry                  : Disabled
**                    Capture 1 circuitry                  : Disabled
**                    Capture circuitry mode               : Free running
**                    Input capture process                : Disabled
**                Channel X (PWM01)                        : 
**                  PWM function                           : 
**                    Output fault state                   : Forced to 0 prior to output polarity
**                    Output polarity                      : Not inverted
**                    Channel masked                       : no
**                    X Double switching                   : Disabled
**                    Channel output                       : Disabled
**                    Fault channel 0                      : 
**                      Disable by fault 0                 : yes
**                      Disable by fault 1                 : yes
**                      Disable by fault 2                 : yes
**                      Disable by fault 3                 : yes
**                    Fault channel 1                      : 
**                      Disable by fault 0                 : yes
**                      Disable by fault 1                 : yes
**                      Disable by fault 2                 : yes
**                      Disable by fault 3                 : yes
**                  E-capture function                     : 
**                    FIFOs water mark level               : 0
**                    Edge counter                         : Disabled
**                    Edge compare                         : 0
**                    Input select X                       : Raw PWMX input signal
**                    Capture 0 circuitry                  : Disabled
**                    Capture 1 circuitry                  : Disabled
**                    Capture circuitry mode               : Free running
**                    Input capture process                : Disabled
**              Output trigger settings                    : 
**                Output trigger 0 source select           : OUT_TRIG0 signal
**                Output trigger 1 source select           : OUT_TRIG1 signal
**                OUT_TRIG0 signal settings                : 
**                  Output trigger for Val 0               : Disabled
**                  Output trigger for Val 2               : Disabled
**                  Output trigger for Val 4               : Disabled
**                OUT_TRIG1 signal settings                : 
**                  Output trigger for Val 1               : Disabled
**                  Output trigger for Val 3               : Disabled
**                  Output trigger for Val 5               : Disabled
**              Reload settings                            : 
**                Reload source                            : Local reload signal
**                Reload frequency                         : 1
**                Half cycle reload                        : Disabled
**                Full cycle reload                        : Enabled
**                Load mode                                : Load at next PWM reload if LDOK is set
**              Force and initialization settings          : 
**                Initialization source                    : Local sync signal
**                Force initialization                     : Disabled
**                Force source                             : Local force signal
**                Init value ch A                          : Low
**                Init value ch B                          : Low
**                Init value ch X                          : Low
**            Submodule 1                                  : Disabled
**            Submodule 2                                  : Disabled
**            Submodule 3                                  : Disabled
**            Fault channel 0 protection settings          : 
**              Common fault settings                      : 
**                Input filter                             : Disabled
**                Fault Glitch Stretch                     : Disabled
**              Fault 0                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**              Fault 1                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**              Fault 2                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**              Fault 3                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**            Fault channel 1 protection settings          : 
**              Common fault settings                      : 
**                Input filter                             : Disabled
**                Fault Glitch Stretch                     : Disabled
**              Fault 0                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**              Fault 1                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**              Fault 2                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**              Fault 3                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**          Pins                                           : 
**            SM0 pins                                     : Disabled
**            SM1 pins                                     : Disabled
**            SM2 pins                                     : Disabled
**            SM3 pins                                     : Disabled
**            PWM Faults                                   : 
**              Fault channel 0                            : 
**                Fault 0                                  : Disabled
**                Fault 1                                  : Disabled
**                Fault 2                                  : Disabled
**                Fault 3                                  : Disabled
**              Fault channel 1                            : 
**                Fault 4                                  : Disabled
**                Fault 5                                  : Disabled
**                Fault 6                                  : Disabled
**                Fault 7                                  : Disabled
**            External clock                               : 
**              External clock                             : Disabled
**              External clock frequency                   : 1
**            External force                               : Disabled
**          Interrupts/DMA                                 : 
**            SM0 Interrupts/DMA                           : Enabled
**              Compare interrupt                          : 
**                Interrupt                                : INT_eFlexPWMA_CMP0
**                Interrupt priority                       : disabled
**                ISR Name                                 : 
**                Compare interrupt 0                      : Disabled
**                Compare interrupt 1                      : Disabled
**                Compare interrupt 2                      : Disabled
**                Compare interrupt 3                      : Disabled
**                Compare interrupt 4                      : Disabled
**                Compare interrupt 5                      : Disabled
**              Capture interrupt                          : 
**                Interrupt                                : INT_eFlexPWMA_CAP
**                Interrupt priority                       : disabled
**                ISR Name                                 : 
**                Capture A 0 interrupt                    : Disabled
**                Capture A 1 interrupt                    : Disabled
**                Capture B 0 interrupt                    : Disabled
**                Capture B 1 interrupt                    : Disabled
**                Capture X 0 interrupt                    : Disabled
**                Capture X 1 interrupt                    : Disabled
**              Reload interrupt                           : 
**                Interrupt                                : INT_eFlexPWMA_RELOAD0
**                Interrupt priority                       : 1
**                ISR Name                                 : PIT_100k_OnInterrupt
**                Reload interrupt                         : Enabled
**              Reload error interrupt                     : 
**                Interrupt                                : INT_eFlexPWMA_RERR
**                Interrupt priority                       : disabled
**                ISR Name                                 : 
**                SM0 reload error interrupt               : Disabled
**              DMA settings                               : 
**                DMA for value registers                  : Disabled
**                Selected capture FIFO watermarks         : OR'ed together
**                Capture FIFO read DMA request            : Disabled
**                Capture A 0 FIFO DMA                     : Disabled
**                Capture A 1 FIFO DMA                     : Disabled
**                Capture B 0 FIFO DMA                     : Disabled
**                Capture B 1 FIFO DMA                     : Disabled
**                Capture X 0 FIFO DMA                     : Disabled
**                Capture X 1 FIFO DMA                     : Disabled
**            SM1 Interrupts/DMA                           : Disabled
**            SM2 Interrupts/DMA                           : Disabled
**            SM3 Interrupts/DMA                           : Disabled
**            Fault interrupt                              : 
**              Interrupt                                  : INT_eFlexPWMA_FAULT
**              Interrupt priority                         : disabled
**              ISR Name                                   : 
**              Channel 0 fault 0 interrupt                : Disabled
**              Channel 0 fault 1 interrupt                : Disabled
**              Channel 0 fault 2 interrupt                : Disabled
**              Channel 0 fault 3 interrupt                : Disabled
**              Channel 1 Fault 0 interrupt                : Disabled
**              Channel 1 Fault 1 interrupt                : Disabled
**              Channel 1 Fault 2 interrupt                : Disabled
**              Channel 1 Fault 3 interrupt                : Disabled
**          Initialization                                 : 
**            Load values after init into SM0              : yes
**            Load values after init into SM1              : no
**            Load values after init into SM2              : no
**            Load values after init into SM3              : no
**            Update mask SM0 immediately                  : no
**            Update mask SM1 immediately                  : no
**            Update mask SM2 immediately                  : no
**            Update mask SM3 immediately                  : no
**            PWM clock rate                               : PWM_2x_Bus_clock
**            PLL output divided                           : By1
**            Enable peripheral clock for SM0              : yes
**            Enable peripheral clock for SM1              : disabled
**            Enable peripheral clock for SM2              : disabled
**            Enable peripheral clock for SM3              : disabled
**            Fault channel 0 test                         : No simulated fault
**            Fault channel 1 test                         : No simulated fault
**            Fault flag clearing                          : 
**              Fault channel 0 flag 0                     : Clear
**              Fault channel 0 flag 1                     : Clear
**              Fault channel 0 flag 2                     : Clear
**              Fault channel 0 flag 3                     : Clear
**              Fault channel 1 flag 0                     : Clear
**              Fault channel 1 flag 1                     : Clear
**              Fault channel 1 flag 2                     : Clear
**              Fault channel 1 flag 3                     : Clear
**            Monitor PLL mode                             : Do not monitor PLL
**            Call Init method                             : yes
**            Utilize after reset values                   : default
**     Contents    :
**         Init - void PWMA_Init(void);
**
**     Copyright : 1997 - 2014 Freescale Semiconductor, Inc. 
**     All Rights Reserved.
**     
**     Redistribution and use in source and binary forms, with or without modification,
**     are permitted provided that the following conditions are met:
**     
**     o Redistributions of source code must retain the above copyright notice, this list
**       of conditions and the following disclaimer.
**     
**     o Redistributions in binary form must reproduce the above copyright notice, this
**       list of conditions and the following disclaimer in the documentation and/or
**       other materials provided with the distribution.
**     
**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
**       contributors may be used to endorse or promote products derived from this
**       software without specific prior written permission.
**     
**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**     
**     http: www.freescale.com
**     mail: support@freescale.com
** ###################################################################*/
/*!
** @file PWMA_Config.h                                                  
** @version 01.00
** @brief
**          This file implements the eFlexPWM (PWMA) module initialization
**          according to the Peripheral Initialization settings, and
**          defines interrupt service routines prototypes.
*/         
/*!
**  @addtogroup PWMA_Config_module PWMA_Config module documentation
**  @{
*/         

#ifndef PWMA_Config_H_
#define PWMA_Config_H_

/* MODULE PWMA. */

/* PWMA_MCTRL: IPOL&=~1,RUN&=~1,CLDOK|=1,LDOK&=~1 */
#define PWMA_MCTRL_VALUE_1   0x10
#define PWMA_MCTRL_MASK_1    0x1111
/* PWMA_SM0INTEN: ??=0,??=0,REIE=0,RIE=0,CA1IE=0,CA0IE=0,CB1IE=0,CB0IE=0,CX1IE=0,CX0IE=0,CMPIE=0 */
#define PWMA_SM0INTEN_VALUE_1 0x00
/* PWMA_FCTRL0: FLVL=0,FAUTO=0,FSAFE=0,FIE=0 */
#define PWMA_FCTRL0_VALUE_1  0x00
/* PWMA_FCTRL1: FLVL=0,FAUTO=0,FSAFE=0,FIE=0 */
#define PWMA_FCTRL1_VALUE_1  0x00
/* PWMA_SM0OCTRL: PWMA_IN=0,PWMB_IN=0,PWMX_IN=0,??=0,??=0,POLA=0,POLB=0,POLX=0,??=0,??=0,PWMAFS=0,PWMBFS=0,PWMXFS=0 */
#define PWMA_SM0OCTRL_VALUE  0x00
/* PWMA_SM0INIT: INIT=1 */
#define PWMA_SM0INIT_VALUE   0x01
/* PWMA_SM0CTRL2: DBGEN=0,WAITEN=0,INDEP=0,PWM23_INIT=0,PWM45_INIT=0,PWMX_INIT=0,INIT_SEL=0,FRCEN=0,FORCE=0,FORCE_SEL=0,RELOAD_SEL=0,CLK_SEL=0 */
#define PWMA_SM0CTRL2_VALUE  0x00
/* PWMA_SM0CTRL: LDFQ=0,HALF=0,FULL=1,DT=0,??=0,PRSC=0,SPLIT=0,LDMOD=0,DBLX=0,DBLEN=0 */
#define PWMA_SM0CTRL_VALUE   0x0400
/* PWMA_SM0TCTRL: PWAOT0=0,PWBOT1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUT_TRIG_EN=0 */
#define PWMA_SM0TCTRL_VALUE  0x00
/* PWMA_SM0VAL0: VAL0=0 */
#define PWMA_SM0VAL0_VALUE   0x00
/* PWMA_SM0VAL1: VAL1=0x03E8 */
#define PWMA_SM0VAL1_VALUE   0x03E8
/* PWMA_SM0VAL2: VAL2=0x01F4 */
#define PWMA_SM0VAL2_VALUE   0x01F4
/* PWMA_SM0VAL3: VAL3=0x03E8 */
#define PWMA_SM0VAL3_VALUE   0x03E8
/* PWMA_SM0VAL4: VAL4=0 */
#define PWMA_SM0VAL4_VALUE   0x00
/* PWMA_SM0VAL5: VAL5=0 */
#define PWMA_SM0VAL5_VALUE   0x00
/* PWMA_SM0FRACVAL1: FRACVAL1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
#define PWMA_SM0FRACVAL1_VALUE 0x00
/* PWMA_SM0FRACVAL2: FRACVAL2=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
#define PWMA_SM0FRACVAL2_VALUE 0x00
/* PWMA_SM0FRACVAL3: FRACVAL3=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
#define PWMA_SM0FRACVAL3_VALUE 0x00
/* PWMA_SM0FRACVAL4: FRACVAL4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
#define PWMA_SM0FRACVAL4_VALUE 0x00
/* PWMA_SM0FRACVAL5: FRACVAL5=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
#define PWMA_SM0FRACVAL5_VALUE 0x00
/* PWMA_SM0FRCTRL: TEST=0,??=0,??=0,??=0,??=0,??=0,??=0,FRAC_PU=0,??=0,??=0,??=0,FRAC45_EN=0,??=0,FRAC23_EN=0,FRAC1_EN=0,??=0 */
#define PWMA_SM0FRCTRL_VALUE 0x00
/* PWMA_SM0DISMAP0: ??=1,??=1,??=1,??=1,DIS0X=0x0F,DIS0B=0x0F,DIS0A=0 */
#define PWMA_SM0DISMAP0_VALUE 0xFFF0
/* PWMA_SM0DISMAP1: ??=1,??=1,??=1,??=1,DIS1X=0x0F,DIS1B=0x0F,DIS1A=0 */
#define PWMA_SM0DISMAP1_VALUE 0xFFF0
/* PWMA_SM0DTCNT0: ??=0,??=0,??=0,??=0,??=0,DTCNT0=0 */
#define PWMA_SM0DTCNT0_VALUE 0x00
/* PWMA_SM0DTCNT1: ??=0,??=0,??=0,??=0,??=0,DTCNT1=0 */
#define PWMA_SM0DTCNT1_VALUE 0x00
/* PWMA_SM0CAPTCOMPA: EDGCNTA=0,EDGCMPA=0 */
#define PWMA_SM0CAPTCOMPA_VALUE 0x00
/* PWMA_SM0CAPTCOMPB: EDGCNTB=0,EDGCMPB=0 */
#define PWMA_SM0CAPTCOMPB_VALUE 0x00
/* PWMA_SM0CAPTCOMPX: EDGCNTX=0,EDGCMPX=0 */
#define PWMA_SM0CAPTCOMPX_VALUE 0x00
/* PWMA_FFILT0: GSTR=0,??=0,??=0,??=0,??=0,FILT_CNT=0,FILT_PER=0 */
#define PWMA_FFILT0_VALUE    0x00
#define PWMA_FFILT0_MASK     0xFFFF
/* PWMA_FFILT1: GSTR=0,??=0,??=0,??=0,??=0,FILT_CNT=0,FILT_PER=0 */
#define PWMA_FFILT1_VALUE    0x00
#define PWMA_FFILT1_MASK     0xFFFF
/* PWMA_MASK: UPDATE_MASK=0,MASKA&=~1,MASKB&=~1,MASKX&=~1 */
#define PWMA_MASK_VALUE      0x00
#define PWMA_MASK_MASK       0xF111
/* PWMA_SWCOUT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,SM0OUT23=0,SM0OUT45=0 */
#define PWMA_SWCOUT_VALUE    0x00
#define PWMA_SWCOUT_MASK     0xFF03
/* PWMA_DTSRCSEL: SM0SEL23=0,SM0SEL45=0 */
#define PWMA_DTSRCSEL_VALUE  0x00
#define PWMA_DTSRCSEL_MASK   0x0F
/* PWMA_MCTRL2: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MONPLL=0 */
#define PWMA_MCTRL2_VALUE    0x00
/* PWMA_OUTEN: ??=0,??=0,??=0,??=0,PWMA_EN|=1,PWMB_EN&=~1,PWMX_EN&=~1 */
#define PWMA_OUTEN_VALUE     0x0100
#define PWMA_OUTEN_MASK      0xF111
/* PWMA_SM0CAPTCTRLA: CA1CNT=0,CA0CNT=0,CFAWM=0,EDGCNTA_EN=0,INP_SELA=0,EDGA1=0,EDGA0=0,ONESHOTA=0,ARMA=0 */
#define PWMA_SM0CAPTCTRLA_VALUE 0x00
/* PWMA_SM0CAPTCTRLB: CB1CNT=0,CB0CNT=0,CFBWM=0,EDGCNTB_EN=0,INP_SELB=0,EDGB1=0,EDGB0=0,ONESHOTB=0,ARMB=0 */
#define PWMA_SM0CAPTCTRLB_VALUE 0x00
/* PWMA_SM0CAPTCTRLX: CX1CNT=0,CX0CNT=0,CFXWM=0,EDGCNTX_EN=0,INP_SELX=0,EDGX1=0,EDGX0=0,ONESHOTX=0,ARMX=0 */
#define PWMA_SM0CAPTCTRLX_VALUE 0x00
/* PWMA_MCTRL: IPOL&=~1,RUN=0,LDOK=1 */
#define PWMA_MCTRL_VALUE_2   0x01
#define PWMA_MCTRL_MASK_2    0x1F0F
/* PWMA_FSTS1: FHALF=0,FFPIN=0x0F,FFULL=0,FFLAG=0x0F */
#define PWMA_FSTS1_VALUE     0x0F0F
/* PWMA_FSTS0: FHALF=0,FFPIN=0x0F,FFULL=0,FFLAG=0x0F */
#define PWMA_FSTS0_VALUE     0x0F0F
/* PWMA_FCTRL0: FLVL=0,FAUTO=0,FSAFE=0,FIE=0 */
#define PWMA_FCTRL0_VALUE_2  0x00
/* PWMA_FCTRL1: FLVL=0,FAUTO=0,FSAFE=0,FIE=0 */
#define PWMA_FCTRL1_VALUE_2  0x00
/* PWMA_MCTRL: RUN|=1 */
#define PWMA_MCTRL_VALUE_3   0x0100
#define PWMA_MCTRL_MASK_3    0x0100
/* PWMA_SM0STS: ??=0,RUF=0,REF=1,RF=1,CFA1=1,CFA0=1,CFB1=1,CFB0=1,CFX1=1,CFX0=1,CMPF=0x3F */
#define PWMA_SM0STS_VALUE    0x3FFF
/* PWMA_SM0INTEN: ??=0,??=0,REIE=0,RIE=1,CA1IE=0,CA0IE=0,CB1IE=0,CB0IE=0,CX1IE=0,CX0IE=0,CMPIE=0 */
#define PWMA_SM0INTEN_VALUE_2 0x1000
/* PWMA_SM0DMAEN: ??=0,??=0,??=0,??=0,??=0,??=0,VALDE=0,FAND=0,CAPTDE=0,CA1DE=0,CA0DE=0,CB1DE=0,CB0DE=0,CX1DE=0,CX0DE=0 */
#define PWMA_SM0DMAEN_VALUE  0x00
/* PWMA_FTST0: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FTEST=0 */
#define PWMA_FTST0_VALUE     0x00
/* PWMA_FTST1: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FTEST=0 */
#define PWMA_FTST1_VALUE     0x00

#define PWMA_AUTOINIT

#define INT_eFlexPWMA_RELOAD0_ISR PIT_100k_OnInterrupt

/* END PWMA. */
#endif /* #ifndef __PWMA_Config_H_ */
/*!
** @}
*/
/*
** ###################################################################
**
**     This file was created by Processor Expert 10.3 [05.09]
**     for the Freescale 56800 series of microcontrollers.
**
** ###################################################################
*/
