NXP® SemiconductorsMSE9S12B128_0L80R
Mask Set ErrataRev. February 11, 2011



MC9S12B128, Mask 0L80R


Introduction
This errata sheet applies to the following devices:

MC9S12B128, MC9S12B64



MCU Device Mask Set Identification

The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1K79X. All standard devices are marked with a mask set number and a date code.



MCU Device Date Codes

Device markings indicate the week of manufacture and the mask set used. The date is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the work week. For instance, the date code "0201" indicates the first week of the year 2002.



MCU Device Part Number Prefixes

Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix.



Errata System Tracking Numbers

MUCtsXXXXX is the tracking number for device errata. It can be used with the mask set and date code to identify a specific erratum.



Errata Summary


Errata NumberModule affectedBrief DescriptionWork-
around
MUCts01096 mscan MSCAN: Data byte corrupted in receive buffer YES
MUCts01106 mscan MSCAN: Time stamp corrupted in receive buffer YES
MUCts01371 mscan MSCAN: Message erroneously accepted if bus error in bit 6 of EOF YES
MUCts01485 mcu_9b128 Reduced flash program temperature range and increased programming time YES
MUCts01861 S12_bdm Possible manipulation of return address when exiting BDM active mode YES
MUCts02384 eets1k EEPROM Program Failure during Sector-Modify YES
MUCts02415 S12_mebi MEBI: Missing ECLK edge on first external access after mode switching YES
MUCts03031 tim_16b8c TIM:Normal Output Compare event happens on setting OC7M bit if OM/OL=0 YES
MUCts03403 spi SPI: Disabling slave SPI together with clearing CPHA while SS low locks transmit shift register for the next transmission YES
MUCts03472 atd_10b16c ATD: Abort of an A/D conversion sequence with write to ATDxCTL0/1/2/3 may not work YES
MUCts03570 mscan MSCAN: Corrupt ID may be sent in early-SOF condition YES
MUCts03660 vreg_3v3 vreg_3v3.02.05: Possible incorrect operation if device is wakened from stop mode within 4.7µs of stop mode entry NO
MUCts03687 atd_10b16c ADC: conversion does not start with 2 consecutive writes to ATDCTL5 YES
MUCts04078 pwm_8b8c PWM: Emergency shutdown input can be overruled YES
MUCts04160 tim_16b8c TIM_16B8C: Output compare pulse is inaccurate YES
MUCts04214 pwm_8b8c PWM: Wrong output level after shutdown restart in 16bit concatenated channel mode NO
MUCts04221 pwm_8b8c PWM: Wrong output value after restart from stop or wait mode NO



MSCAN: Data byte corrupted in receive bufferMUCts01096

Description

When the foreground receive buffer (RxFG) is read with the Receiver Full

Flag (RXF) set, the value of one or more data bytes may be incorrect due
to corruption after the message reception. The corruption can occur at
the end of a message transmission from any of the three transmit message
buffers of the same msCAN module. The affected data byte is overwritten
by a byte of the corrupting transmit buffer's Time Stamp Register, TSRH
for even, TSRL for odd addresses affected, respectively. The value
written is zero ($00) if the internal timer has not been enabled (TIME=0
in CANCTL0).

The corruption can only occur if all of the following three conditions
are met:

1. Rx and Tx message length relationship
If the number of data bytes transmitted, n, is five or less, Data
Segment Register (n+2) in RxFG is corrupted, i.e. DSR2 if n=0, .., DSR7
if n=5.
No corruption occurs for n > 5. Also, DSR0 and DSR1 are never affected.

2. Timing
A received message may contain corrupted data if RxFG is read after the
end of a message transmission from the same msCAN module.
No corruption is seen if all received messages are read within the time
window beginning when RXF is set and ending with the completion of
transmission of a subsequent message by the same msCAN module (the
'green window'). The width of the green window depends on many factors:
application software (Tx message scheduling, Rx/Tx interrupt priorities,
etc.), bus load, baud rate, and transmit message length. The minimum
(guaranteed) green window width is 376us for 125kbps, for example. This
minimum value occurs only in case of a transmit message following
back-to-back to the receive message, and for zero data bytes and zero
stuff bits. The green window width inversely scales with the baud rate.

3. Receive FIFO Buffer #
Only receive buffer 0 (Rx0) of the 5-stage FIFO can be affected.
At least four out of every five messages received are not affected.

Workaround


In affected systems where the lengths of messages can be adjusted, using

six or more bytes for transmission eliminates the issue completely.
Systems using an MCU with unused msCAN modules should use one to
transmit only and one to receive only, to completely avoid the issue.
For other systems the likelihood of problem occurrence can be further
reduced by maximizing the receive interrupt priority, i.e. use CAN0 for
the most critical bus in a multi-bus application, and/or promoting the
msCAN receive interrupt to highest priority using the HPRIO register.
In (control) systems where the signal representation can be adjusted,
and the time stamp is not used (TIME=0), mapping $00 to an 'illegal'
signal would allow problem detection and appropriate software means of
reaction.
In systems where all byte values are legal (e.g. data download),
checksums and/or parities can be used to signal problem occurrence and
allow for proper handling (e.g. request for retransmission).
Alternatively, the use of data filter algorithms may suppress or at
least reduce the effect of the problem.



MSCAN: Time stamp corrupted in receive bufferMUCts01106

Description

When the foreground receive buffer (RxFG) is read, with the Receiver

Full Flag (RXF) set, the value of the Time Stamp Register may be
incorrect due to corruption. The Time Stamp Register is written
correctly when the message is received, but may be overwritten by the
timer value at the end of a subsequent reception. The corruption can
only occur close to a data overrun, when the receive buffer FIFO is
full.

The problem occurs whenever the following two conditions are met:

1. Receive buffer system is full
All five receive buffers contain valid messages waiting to be read by
the application.

2. Another valid message is seen on the bus. This message must be sent
from another node, i.e. it must not be transmitted from the respective
msCAN module itself.

At the end of the message in 2. the Time Stamp Register of the oldest
message in the receive FIFO is overwritten.

Note: if the message in 2. passes the message filter system the Overrun
Interrupt Flag (OVRIF) is also set.

Workaround


The application software has to ensure to read the receive messages in

due time to avoid data overrun in any case. This will automatically
minimize the risk of a Time Stamp Register overwrite event.



MSCAN: Message erroneously accepted if bus error in bit 6 of EOFMUCts01371

Description

If a particular error condition occurs within the end of frame segment

(EOF) of a CAN message, the msCAN module recognises and accepts a
non-valid message as being valid, contrary to the CAN specification. The
msCAN module incorrectly validates messages after five recessive bits of
the end of frame instead of after six bits. If a bus error occurs during
the sixth bit of end of frame, the msCAN module will already have
accepted the message as valid, even although an error frame is
transmitted and the receive error counter is incremented.

The CAN protocol states that message validation differs between bus
transmitter and receiver devices (refer to part B, section 5 of CAN
protocol for details). In the case where the 7th bit of the EOF segment
is dominant, the message is valid for the receiver but not for the
transmitter. This erratum extends this case to the 6th bit of the EOF
segment.

Workaround


This erratum will not be an issue if the application software is

protected against the known double receive problem of the CAN protocol.
This problem occurs when a message is not recognised as valid by the
transmitter, but is recognised as valid by a receiver, as described
above. When this happens, the message is re-transmitted and hence the
receiver will receive the same message twice.




Reduced flash program temperature range and increased programming timeMUCts01485

Description

The flash program temperature range specification has been reduced. The

specification now stipulates that flash program operations must take
place between temperatures of 0C and 125C ambient.

In addition, the flash program times have been increased as follows:

Programming Time
Min. Max.
Single Word Program (Tswpgm) 66.0us 99.2us
Flash Row Program - Consecutive Word (Tbwpgm) 40.4us 57.8us
Flash Row Program - 64 words (Tbrpgm) 2608.7us 3742.7us

Actual programming time will vary between the above bounds depending on
flash clock and bus clock frequencies.

Important Notes:
1) Program time is internally controlled by the flash state machine.
No action needs to be taken by users in connection with this erratum.
2) Both flash erase and flash read temperature specifications and
operation times are unaffected by this erratum.
3) EEPROM is unaffected by this erratum.

Workaround


None.



Possible manipulation of return address when exiting BDM active modeMUCts01861

Description

Upon leaving BDM active mode, the CPU return address is stored

temporarily for a few cycles in the BDM shift register. If a BDM command
transmission is detected during this time, the return address will be
manipulated in the BDM shift register. This situation is likely to occur
when a CPU BGND instruction is executed in user code during debugging
under the following conditions:

(i) The BDM module is not enabled AND
(ii) BDM commands are sent from the host

If this situation occurs, the CPU will execute BDM firmware and will
check the status of the ENBDM bit in the BDMSTS register. If the BDM is
disabled, the ENBDM bit will be clear, and hence the BDM firmware will
be exited and the shift register manipulation described above will occur.

Workaround


Avoid using the BGND instruction when the ENBDM bit in the BDMSTS

register is cleared.



EEPROM Program Failure during Sector-ModifyMUCts02384

Description

At oscillator frequencies above 4MHz the Program step of the EEPROM

Sector-Modify command can fail depending on the bus frequency. As a
result, no programming of the EEPROM occurs. There is no impact to the
Erase step of the Sector-Modify command. Since a partial programming of
the word cannot occur, there is not a reliability issue caused by the
Sector-Modify command if the programmed word is verified.

Oscillator Bus
Frequency Frequency
---------- ----------------------
4MHz No Issue
8MHz Fbus <20MHz : No issue
16MHz Fbus <16MHz : No issue




Workaround


Use seperate Erase and Program commands in place of the Sector-Modify

command. If the Sector-Modify command is used and fails the program step
as confirmed by a user verification step, a Program command alone can be
used to effectively complete the operation since the erase step does
successfully erase the sector.



MEBI: Missing ECLK edge on first external access after mode switchingMUCts02415

Description

If the ECLK is used as an external bus control signal (ESTR=1) the first

external access is lost after switching from a single chip mode with
enabled ECLK output to an expanded mode. The ECLK is erroneously held in
the high phase thus the first external bus access does not generate a
rising ECLK edge for the external logic to latch the address. The ECLK
stretches low after the lost access resulting in all following external
accesses to be valid.

Workaround


Enter expanded mode with ECLK output disabled (NECLK=1). Enable the ECLK

after switching the mode before executing the first external access.



TIM:Normal Output Compare event happens on setting OC7M bit if OM/OL=0 MUCts03031

Description

When an OC7M bit is set, an erroneous normal output compare event can 

happen on a timer port if the compare action is selected as "Timer
disconnected from output pin logic ".

Corresponding configuration:
* TIOSx = 1 --> Output compare mode
* OMx = OLx = 0 --> Output compare logic disconnected from the pin
* OC7Mx = 1 --> Mask bit set for OC7 event







Workaround


Set OC7Mx = 1 only for channels where the output compare action should 

drive the pin, and OC7Mx = 0 for all other channels where the pin is
required to be disconnected from the output compare logic.



SPI: Disabling slave SPI together with clearing CPHA while SS low locks transmit shift register for the next transmissionMUCts03403

Description

With the SPI configured as a slave, clearing the SPE bit (to disable 

the SPI) together with clearing the CPHA bit while the SS pin is low
causes the transmit shift register to be locked for the next
transmission following the SPI being re-enabled as a slave with SS
still being low.

This means new transmit data is not accepted for the first
transmission after re-enabling the SPI (indicated by SPTEF staying low
after storing transmit data into SPIDR), but for the next following
transmission.



Workaround


When disabling the slave SPI, CPHA should not be cleared at the same time. 




ATD: Abort of an A/D conversion sequence with write to ATDxCTL0/1/2/3 may not workMUCts03472

Description

Starting a conversion with a write to ATDxCTL5 or on an external trigger

event, and aborting immediately afterwards with a write to ATDxCTL0,
ATDCTL1, ATDxCTL2 or ATDxCTL3 can fail to stop the conversion process.

Workaround


Only write to ATDxCTL4 to abort an ongoing conversion sequence.


Use the recommended start and abort procedures from the Block Guide.
Section : Initialization/Application Information
Subsection: Setting up and starting an A/D conversion
Subsection: Aborting an A/D conversion



MSCAN: Corrupt ID may be sent in early-SOF conditionMUCts03570

Description

The initial eight ID bits will be corrupted if a message is set up for

transmission during the third bit of INTERMISSION and a dominant bit is
sampled leading to an early-SOF*.

The CRC is calculated from the resulting bit stream so that the
receiving nodes will still validate the message.

An early-SOF condition may only occur if the oscillators in the network
operate at a tolerance range which could lead to a cumulated phase error
after 11 bit times larger than phase segment 2.

In case arbitration is lost during transmission of the corrupt
identifier, a non-corrupted ID will be sent with the next attempt if the
transmit request remains active.

*The CAN protocol condition referred to as 'early-SOF' in this erratum
is detailed in "Bosch CAN Specification Version 2.0" Part A, section 9,
and a Note to section 3.2.5 INTERFRAME SPACING – INTERMISSION in Part B.

Workaround


Due to increased oscillator tolerance a transmission start in the third

bit of intermission is possible and allowed. The errata can be avoided
when calculating the maximum oscillator tolerance of the overall CAN
system. The phase error after 11 bit times due to the oscillator
tolerance should be smaller than phase segment 2.

If an early-SOF cannot be avoided the following methods will provide
prevention:

- Assigning the same value to all upper eight ID bits in the network
- Allocating dedicated data length codes (DLC) to every identifier used
in the network and checking for correspondence after reception
- Assigning only IDs (x) which do not consist of a combination of other
assigned IDs (y,z) and using the acceptance filters to reject
erroneous messages, i.e.
- for standard frames: IDx[11:0] != {IDy[11:3], IDz[2:0]}
- for extended frames: IDx[28:21] != {IDy[28:21],IDz[20:0]}



vreg_3v3.02.05: Possible incorrect operation if device is wakened from stop mode within 4.7µs of stop mode entryMUCts03660

Description

It is possible that after the device enters Stop or Pseudo-Stop mode it

may reset rather than wake up normally upon reception of the wake-up
signal.

CONDITIONS: This event will only happen provided ALL of the following
conditions are met:
1) Device is powered by the on-chip voltage regulator.
2) Device enters stop or pseudo-stop mode by execution of STOP
instruction by the CPU (provided the S-bit in CCR is cleared)
NOTE: The part enters stop mode either after 12 oscillator clock cycles
with the PLL disengaged or 3 PLL clock cycles and 8 oscillator clock
cycles with the PLL engaged after the STOP command is executed.
3) The wake-up signal is activated within a specific very short
window (typically 11ns long, not longer than 20ns). The position of the
window varies between different devices, however it never starts sooner
than 1.6µs and never ends later than 4.7µs after the stop mode entry.

This really narrow width of the susceptible window (20ns maximum) makes
the erratum unlikely to ever show in the applications life.

The incorrect behavior will never occur if ANY of the wake-up conditions
are met at the time when the stop mode entry is attempted (an enabled
interrupt is pending).

EFFECT:
If this incorrect behavior occurs, the device will Reset and indicate a
Low Voltage Reset (LVR) as the reset source.
The device will operate normally after the reset.

Workaround


None. 


--

Asynchronous Low Voltage Resets are possible in any microcontroller
application (due to power supply drops) and the integrated LVR and LVI
features and dedicated LVR reset vector are provided to manage this fact
cleanly. For best practice, the application's software should be written
to recover from a Low Voltage Reset in a controlled manner. An
application software written to deal with valid Low Voltage Resets
should correctly manage erroneous LVR events.

It can also be possible to avoid erroneous Low Voltage Resets from
synchronous wake-up events by configuring the application software to
ensure that the entry into stop occurs at such a time, in relation to
the wake-up event timer, that a wake-up event does not occur within
1.6µs to 4.7µs after Stop/Pseudo-Stop entry.



ADC: conversion does not start with 2 consecutive writes to ATDCTL5MUCts03687

Description

When the ATD is started with write to ATDCTL5

and, which is very unusual and not necessary,
within a certain period again started with write
to ATDCTL5. The conversion will not start at all.
This does only happen if the two consecutive writes to ATDCTL5 occur
within one "ATD clock period". An ATD clock period is defined by a full
rollover of the ATD clock prescaler. That is for example PRS[4:0] = 2 -
> (2+1)*2 = within 6 bus cycles.


Workaround


Only write once to ATDCTL5 when starting a conversion.


Use the recommended start and abort procedures from the Block Guide.
Section : Initialization/Application Information Subsection: Setting up
and starting an A/D conversion Subsection: Aborting an A/D conversion



PWM: Emergency shutdown input can be overruledMUCts04078

Description

If the PWM emergency shutdown feature is enabled (PWM7ENA=1) and PWM

channel 7 is disabled (PWME7=0) another lower priority function
available on the related pin can take control over the data direction.
This does not lead to a problem if input mode is maintained. If the
alternative function switches to output mode the shutdown function may
unintentionally be triggered by the output data.


Workaround


When using the PWM emergency shutdown feature the GPIO function on the

pin associated with PWM channel 7 should be selected as an input.

In the case that this pin is selected as an output or where an
alternative function is enabled which could drive it as an output,
enable PWM channel 7 by setting the PWME7 bit. This prevents an
active shutdown level driven on the (output) pin from resulting in an
emergency shutdown of the enabled PWM channels.




TIM_16B8C: Output compare pulse is inaccurateMUCts04160

Description

The pulse width of an output compare (which resets the free running

counter when TCRE = 1) will measure one more bus clock cycle than
expected.



Workaround


The specification has been updated. Please refer to revision 01.05 (05 

May 2010) or later.

In description of bitfield TCRE in register TSCR2,a note has been added:
TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler
counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to
0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it
will last only one bus cycle then reset to 0.








PWM: Wrong output level after shutdown restart in 16bit concatenated channel modeMUCts04214

Description

When the PWM is used in 16-bit (concatenation) channel and the emergency

shutdown feature is being used, after de-asserting PWM channel 7
(note:PWMRSTRT should be set) the PWM channels (PP0-PP6) do not show the
state which is set by PWMLVL bit when the 16-bit counter is non-zero.


Workaround


None. 




PWM: Wrong output value after restart from stop or wait modeMUCts04221

Description

In low power modes (stop/p-stop/wait – PSWAI=1) and during PWM PP7

de-assert and when PWM counter reaching 0, the PWM channel outputs
(PP0-PP6) cannot keep the state which is set by PWMLVL bit.



Workaround


None. 



© NXP Semiconductors, Inc., 2011. All rights reserved.