NXP® SemiconductorsMSE9S12C32_0M34C
Mask Set ErrataRev. February 13, 2011

MC9S12C32, Mask 0M34C

This errata sheet applies to the following devices:

MC9S12C32, MC9S12GC32, MC9S12GC16, MC9S12Q32, MC3S12Q32

MCU Device Mask Set Identification

The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1K79X. All standard devices are marked with a mask set number and a date code.

MCU Device Date Codes

Device markings indicate the week of manufacture and the mask set used. The date is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the work week. For instance, the date code "0201" indicates the first week of the year 2002.

MCU Device Part Number Prefixes

Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix.

Errata System Tracking Numbers

MUCtsXXXXX is the tracking number for device errata. It can be used with the mask set and date code to identify a specific erratum.

Errata Summary

Errata NumberModule affectedBrief DescriptionWork-
MUCts02415 S12_mebi MEBI: Missing ECLK edge on first external access after mode switching YES
MUCts02958 mscan msCAN: Potential byte corruption when FIFO full YES
MUCts03031 tim_16b8c TIM:Normal Output Compare event happens on setting OC7M bit if OM/OL=0 YES
MUCts03403 spi SPI: Disabling slave SPI together with clearing CPHA while SS low locks transmit shift register for the next transmission YES
MUCts03568 mscan MSCAN: Corrupt ID may be sent in early-SOF condition YES
MUCts03662 vreg_3v3 vreg_3v3.02.08: Possible incorrect operation if device is wakened from stop mode within 4.7µs of stop mode entry NO
MUCts03683 atd_10b8c ADC: conversion does not start with 2 consecutive writes to ATDCTL5 YES
MUCts04076 pwm_8b6c PWM: Emergency shutdown input can be overruled YES
MUCts04160 tim_16b8c TIM_16B8C: Output compare pulse is inaccurate YES
MUCts04223 pwm_8b6c PWM: Wrong output level after shutdown restart in 16bit concatenated channel mode NO
MUCts04225 pwm_8b6c PWM: Wrong output value after restart from stop or wait mode NO

MEBI: Missing ECLK edge on first external access after mode switchingMUCts02415


If the ECLK is used as an external bus control signal (ESTR=1) the first

external access is lost after switching from a single chip mode with
enabled ECLK output to an expanded mode. The ECLK is erroneously held in
the high phase thus the first external bus access does not generate a
rising ECLK edge for the external logic to latch the address. The ECLK
stretches low after the lost access resulting in all following external
accesses to be valid.


Enter expanded mode with ECLK output disabled (NECLK=1). Enable the ECLK

after switching the mode before executing the first external access.

msCAN: Potential byte corruption when FIFO fullMUCts02958


When messages received by the msCAN controller are not serviced in 

time, such that the five-stage FIFO becomes full, one data byte of
the oldest message in the receive buffer FIFO may contain invalid data
with the value 0x7F.

The data lengths of the oldest and the newest message in the FIFO
determine if this occurs, and if so, the position of the affected Data
Segment Register (DSR) byte:

DSR(n+2) is affected in oldest message if newest message has data
length n.


This issue occurs only when the message buffer FIFO runs full:
The FIFO has been filled with four messages 'a' (oldest), 'b', 'c',
and 'd', when a new message 'e' is received that is protocol
compliant (no errors) and that passes the acceptance filter.

and the oldest and newest message lengths meet the following critera:
The data length codes, La and Le, of messages 'a' and 'e' are such
3 <= La <= 8, and
0 <= Le <= 5, and
Le <= La - 3.


Consider the case where La = 8, and Le = 4.
Here n = Le = 4, therefore byte DSR(n+2) = DSR6 (i.e. the seventh data
byte of message 'a') gets written to 0x7F.


A. The FIFO runs full without service (near-overrun situation) - Pa:
Application software will typically avoid this possible overrun
situation, minimizing the probability of this condition occurring -
hence this is typically a very low probability (that is dependent on
the application implementation).

B. Message length dependency - Pb:
If all Rx messages have the same length, or are 6, 7, or 8 bytes
long, there is no possibility of the error occurring, and Pb = 0.

For random non-0 data lengths, Pb = 0.25 (approximately).

Overall, the probability of the error occurring is P = Pa x Pb.


The following precautions can be taken to avoid the problem:

- Do not allow the receive FIFO buffer to become full.
> If necessary, raise the Rx interrupt priority so that condition
A is avoided.
- Use constant data lengths (any value) for the Rx messages
> E.g. use eight bytes only, and pad shorter messages with dummy
- Use (mixed) data lengths in the range 6 to 8.
- Use (mixed) data lengths in the range 1 to 3.
- Use a parity or checksum scheme to detect a corrupted byte.
- Check for the 'critical' value 0x7F in bytes 3 to 8.

TIM:Normal Output Compare event happens on setting OC7M bit if OM/OL=0 MUCts03031


When an OC7M bit is set, an erroneous normal output compare event can 

happen on a timer port if the compare action is selected as "Timer
disconnected from output pin logic ".

Corresponding configuration:
* TIOSx = 1 --> Output compare mode
* OMx = OLx = 0 --> Output compare logic disconnected from the pin
* OC7Mx = 1 --> Mask bit set for OC7 event


Set OC7Mx = 1 only for channels where the output compare action should 

drive the pin, and OC7Mx = 0 for all other channels where the pin is
required to be disconnected from the output compare logic.

SPI: Disabling slave SPI together with clearing CPHA while SS low locks transmit shift register for the next transmissionMUCts03403


With the SPI configured as a slave, clearing the SPE bit (to disable 

the SPI) together with clearing the CPHA bit while the SS pin is low
causes the transmit shift register to be locked for the next
transmission following the SPI being re-enabled as a slave with SS
still being low.

This means new transmit data is not accepted for the first
transmission after re-enabling the SPI (indicated by SPTEF staying low
after storing transmit data into SPIDR), but for the next following


When disabling the slave SPI, CPHA should not be cleared at the same time. 

MSCAN: Corrupt ID may be sent in early-SOF conditionMUCts03568


The initial eight ID bits will be corrupted if a message is set up for

transmission during the third bit of INTERMISSION and a dominant bit is
sampled leading to an early-SOF*.

The CRC is calculated from the resulting bit stream so that the
receiving nodes will still validate the message.

An early-SOF condition may only occur if the oscillators in the network
operate at a tolerance range which could lead to a cumulated phase error
after 11 bit times larger than phase segment 2.

In case arbitration is lost during transmission of the corrupt
identifier, a non-corrupted ID will be sent with the next attempt if the
transmit request remains active.

*The CAN protocol condition referred to as 'early-SOF' in this erratum
is detailed in "Bosch CAN Specification Version 2.0" Part A, section 9,
and a Note to section 3.2.5 INTERFRAME SPACING – INTERMISSION in Part B.


Due to increased oscillator tolerance a transmission start in the third

bit of intermission is possible and allowed. The errata can be avoided
when calculating the maximum oscillator tolerance of the overall CAN
system. The phase error after 11 bit times due to the oscillator
tolerance should be smaller than phase segment 2.

If an early-SOF cannot be avoided the following methods will provide

- Assigning the same value to all upper eight ID bits in the network
- Allocating dedicated data length codes (DLC) to every identifier used
in the network and checking for correspondence after reception
- Assigning only IDs (x) which do not consist of a combination of other
assigned IDs (y,z) and using the acceptance filters to reject
erroneous messages, i.e.
- for standard frames: IDx[11:0] != {IDy[11:3], IDz[2:0]}
- for extended frames: IDx[28:21] != {IDy[28:21],IDz[20:0]}

vreg_3v3.02.08: Possible incorrect operation if device is wakened from stop mode within 4.7µs of stop mode entryMUCts03662


It is possible that after the device enters Stop or Pseudo-Stop mode it

may reset rather than wake up normally upon reception of the wake-up

This will only happen provided ALL of the following conditions are met:
1) Device is powered by the on-chip voltage regulator.
2) Device enters stop or pseudo-stop mode by execution of STOP
instruction by the CPU (providing the S-bit in CCR is cleared)
NOTE: The part enters stop mode either after 12 oscillator clock cycles
with the PLL disengaged or 3 PLL clock cycles and 8 oscillator clock
cycles with the PLL engaged after the STOP command is executed.
3) The wake-up signal is activated within a specific very short
window (typically 11ns long, not longer than 20ns). The position of the
window varies between different devices, however it never starts sooner
than 1.6µs and never ends later than 4.7µs after the stop mode entry.
This really narrow width of the susceptible window (20ns maximum) makes
the erratum unlikely to ever show in the applications life.

The incorrect behavior will never occur if ANY of the wake-up conditions
are met at the time when the stop mode entry is attempted (an enabled
interrupt is pending).

If this incorrect behavior occurs, the device will Reset and indicate a
Low Voltage Reset (LVR) as the reset source.
The device will operate normally after the reset.




Asynchronous Low Voltage Resets are possible in any microcontroller
application (due to power supply drops) and the integrated LVR and LVI
features and dedicated LVR reset vector are provided to manage this fact
cleanly. For best practice, the application's software should be written
to recover from a Low Voltage Reset in a controlled manner.
An application software written to deal with valid Low Voltage Resets
should correctly manage erroneous LVR events.

It can also be possible to avoid erroneous Low Voltage Resets from
synchronous wake-up events by configuring the application software to
ensure that the entry into stop occurs at such a time, in relation to
the wake-up event timer, that a wake-up event does not occur within
1.6µs to 4.7µs after Stop/Pseudo-Stop entry.

ADC: conversion does not start with 2 consecutive writes to ATDCTL5MUCts03683


When the ATD is started with write to ATDCTL5

and, which is very unusual and not necessary,
within a certain period again started with write
to ATDCTL5. The conversion will not start at all.
This does only happen if the two consecutive writes to ATDCTL5 occur
within one "ATD clock period". An ATD clock period is defined by a full
rollover of the ATD clock prescaler. That is for example PRS[4:0] = 2 -
> (2+1)*2 = within 6 bus cycles.


Only write once to ATDCTL5 when starting a conversion.

Use the recommended start and abort procedures from the Block Guide.
Section : Initialization/Application Information Subsection: Setting up
and starting an A/D conversion Subsection: Aborting an A/D conversion

PWM: Emergency shutdown input can be overruledMUCts04076


If the PWM emergency shutdown feature is enabled (PWM5ENA=1) and PWM

channel 5 is disabled (PWME5=0) another lower priority function
available on the related pin can take control over the data direction.
This does not lead to a problem if input mode is maintained. If the
alternative function switches to output mode the shutdown function may
unintentionally be triggered by the output data.


When using the PWM emergency shutdown feature the GPIO function on the

pin associated with PWM channel 5 should be selected as an input.

In the case that this pin is selected as an output or where an
alternative function is enabled which could drive it as an output,
enable PWM channel 5 by setting the PWME5 bit. This prevents an
active shutdown level driven on the (output) pin from resulting in an
emergency shutdown of the enabled PWM channels.

TIM_16B8C: Output compare pulse is inaccurateMUCts04160


The pulse width of an output compare (which resets the free running

counter when TCRE = 1) will measure one more bus clock cycle than


The specification has been updated. Please refer to revision 01.05 (05 

May 2010) or later.

In description of bitfield TCRE in register TSCR2,a note has been added:
TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler
counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to
0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it
will last only one bus cycle then reset to 0.

PWM: Wrong output level after shutdown restart in 16bit concatenated channel modeMUCts04223


When the PWM is used in 16-bit (concatenation) channel and the 

shutdown feature is being used, after de-asserting PWM channel 5
(note:PWMRSTRT should be set) the PWM channels (PP0-PP4) do not show
state which is set by PWMLVL bit when the 16-bit counter is non-zero.



PWM: Wrong output value after restart from stop or wait modeMUCts04225


In low power modes (stop/p-stop/wait ?PSWAI=1) and during PWM PP5

de-assert and when PWM counter reaching 0, the PWM channel outputs
(PP0-PP4) cannot keep the state which is set by PWMLVL bit.



© NXP Semiconductors, Inc., 2011. All rights reserved.