NXP® SemiconductorsMSE9S12D256B_0K79X
Mask Set ErrataRev. February 13, 2011



MC9S12DP256B, Mask 0K79X


Introduction
This errata sheet applies to the following devices:

MC9S12DP256B, MC9S12DT256C, MC9S12DJ256C, MC9S12DG256C, MC9S12DT256B, MC9S12DJ256B, MC9S12DG256B, MC9S12A256B



MCU Device Mask Set Identification

The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1K79X. All standard devices are marked with a mask set number and a date code.



MCU Device Date Codes

Device markings indicate the week of manufacture and the mask set used. The date is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the work week. For instance, the date code "0201" indicates the first week of the year 2002.



MCU Device Part Number Prefixes

Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix.



Errata System Tracking Numbers

MUCtsXXXXX is the tracking number for device errata. It can be used with the mask set and date code to identify a specific erratum.



Errata Summary


Errata NumberModule affectedBrief DescriptionWork-
around
MUCts00358 fts256k FTS256K: Incorrect fetch of buffered data and addresses NO
MUCts00398 crg CRG: RTI flag clearing delay when running on PLL clock YES
MUCts00407 atd_10b8c ATD: Switching from scan to single mode corrupts data registers YES
MUCts00424 atd_10b8c ATD current consumption in low power modes YES
MUCts00426 crg CRG: RTI clocks remain active if RTIF is set YES
MUCts00429 spi SPI locks if disabled during message transmission YES
MUCts00434 crg CRG: Self Clock Frequency too high YES
MUCts00436 S12_bdm BDM loses sync when using PLL at high frequencies YES
MUCts00459 osc OSC: Clock Monitor Frequency lower than specified NO
MUCts00463 pwm_8b8c PWM channel early start after leaving emergency shutdown mode NO
MUCts00468 S12_bkp Breakpoint Module: potential extraneous data match NO
MUCts00470 spi SPI can receive incorrect data in slave mode YES
MUCts00478 spi SPIF-flag is set wrongly in slave mode after SPI re-enabling YES
MUCts00479 spi SPI locks if re-enabled as master YES
MUCts00482 atd_10b8c ATD: Incorrect offset of transfer curve for 8-bit resolution NO
MUCts00502 S12_mebi MEBI: Non-multiplexed addresses on PK change before end of cycle YES
MUCts00510 sci SCI interrupt asserts only if an odd number of interrupts active YES
MUCts00511 SFC0032_16B9 NVM Reliability Errata NO
MUCts00512 SFC0002_16A4 EEPROM Reliability Errata NO
MUCts00522 mscan MSCAN extended ID rejected if stuff bit between ID16 and ID15 YES
MUCts00531 spi SPIF flag is set wrongly in slave mode YES
MUCts00548 spi SPIF flag is set wrongly -> SPI locks in master mode YES
MUCts00565 S12_mebi Missing external ECLK during reset vector fetch NO
MUCts00570 spi SPIDR is writeable though the SPTEF flag is cleared. YES
MUCts00575 fts256k FTS256K: Erase Verify impact on subsequent Erase operations YES
MUCts00589 ect_16b8c ECT: can't use channel 0-3 for OC if queuing is enabled YES
MUCts00590 util MSCAN: Glitch filter exceeds spec limits NO
MUCts00603 fts256k Program & Erase of flash blocked in Normal Single Chip Mode when secure YES
MUCts00604 eets4k Program & Erase of EEPROM blocked in Normal Single Chip Mode when secure YES
MUCts00616 pim_9dp256 PE7 (XCLKS) is not pulled up internally when reset in emulation mode YES
MUCts00618 util Key wake-up: Glitch filter exceeds upper 10us limit YES
MUCts00648 sram12k Reduced operating voltage range for 25MHz NO
MUCts00655 pim_9dp256 SPI2: SS2 and SCK2 inputs swapped if routed on Port H YES
MUCts00702 spi SPTEF flag set erroneously YES
MUCts00741 atd_10b8c ATD: Flags in ATDSTAT0 do not clear by writing '1', ETORF erroneously set YES
MUCts00747 spi SPI in Mode Fault state, but MISO output buffer not disabled. NO
MUCts00792 atd_10b8c ATD: Write to ATDCTL5 may not clear SCF, CCF and ASCIF flags YES
MUCts00794 spi MISO not kept after sixteenth SCK edge. YES
MUCts00811 ect_16b8c ECT: Input pulse shorter than delay counter period recognised as a valid YES
MUCts00814 crg PLL: If osc_clock is 2 to 3 times pll_clock, STOP can cause SCM or reset YES
MUCts00844 fts256k Flash: ACCERR is not set for a Byte Access YES
MUCts00868 eets4k EE: ACCERR is not generated for a Byte Access YES
MUCts00973 fts256k CCIF command complete flag may be erroneously set. YES
MUCts00974 eets4k CCIF command complete flag may be erroneously set. YES
MUCts00978 fts256k STOP instruction may set flash ACCERR flag. YES
MUCts00985 eets4k STOP instruction may set EEPROM ACCERR flag. YES
MUCts01032 atd_10b8c CCF flags in ATDSTAT1 register might fail to set NO
MUCts01043 atd_10b8c ATD: Clearing of CCF flags in ATDSTAT1 by write of ATDCTL5 might not work YES
MUCts01086 mscan MSCAN: Data byte corrupted in receive buffer YES
MUCts01090 mscan MSCAN: Time stamp corrupted in receive buffer YES
MUCts01367 mscan MSCAN: Message erroneously accepted if bus error in bit 6 of EOF YES
MUCts01532 ect_16b8c ECT_16B8C: Output compare pulse is inaccurate YES
MUCts01968 S12_bdm Possible manipulation of return address when exiting BDM active mode YES
MUCts02345 S12_mebi MEBI: Missing ECLK edge on first external access after mode switching YES
MUCts02718 atd_10b8c ATD: In FIFO mode, write to ATDCTL5 does not clear CC2-0 YES
MUCts03194 eets4k EEPROM Program Failure during Sector-Modify YES
MUCts03345 eets4k EETS4K: Erase Verify impact on subsequent Erase operations YES
MUCts03575 mscan MSCAN: Corrupt ID may be sent in early-SOF condition YES
MUCts04075 pwm_8b8c PWM: Emergency shutdown input can be overruled YES
MUCts04109 ect_16b8c ECT: Channel 0 - 3 Input Capture interrupts inhibited when BUFEN=1, LATQ=0 and NOVWx=1 YES
MUCts04215 pwm_8b8c PWM: Wrong output level after shutdown restart in 16bit concatenated channel mode NO
MUCts04219 pwm_8b8c PWM: Wrong output value after restart from stop or wait mode NO



FTS256K: Incorrect fetch of buffered data and addressesMUCts00358

Description

During pipelined programming the data and addresses fetched from the

FDATA and FADDR buffers will be incorrect if the BKSEL bits in the FCNFG
register do not point to the appropriate back of registers.

Workaround


None.



CRG: RTI flag clearing delay when running on PLL clockMUCts00398

Description

If the system is running on the PLL Clock at frequencies greater than

10X the incoming oscillator clock, a RTI flag clearing sequence
initiated immediately prior to executing the WAIT instruction, with the
SYSWAI=1 and the PLLWAI=0, may not completely clear the RTI interrupt
flag circuitry. This will result in a premature RTI flag and interrupt,
if enabled.

Workaround


After clearing the RTI flag add a 3 OSC clock cycle delay prior to

entering WAIT mode.



ATD: Switching from scan to single mode corrupts data registersMUCts00407

Description

Switching from a SCAN mode conversion sequence to a SINGLE mode

conversion sequence can corrupt the data registers, shifting their
values forward by a word.

Workaround


To switch from a SCAN mode conversion sequence to a SINGLE mode

conversion sequence:
1. Disable the ATD by clearing the ADPU bit in the ATDCTL2 register
2. Clear the SCAN bit in ATDCTL5 to switch to single conversion mode
3. Set the ADPU bit in the ATDCTL2 register to re-enable the ATD.
4. Allow 20us for the ATD to initialize before writing again to ATDCTL5
to start the single conversion sequence.



ATD current consumption in low power modesMUCts00424

Description

If any ATD module is enabled when the CPU encouters stop instruction or

cpu encounters wait instruction with atd stop in wait bit set,
atd current consumption may be out of specification.


Workaround


The ATD modules should be disabled prior to entering stopmode. 




CRG: RTI clocks remain active if RTIF is setMUCts00426

Description

The RTI clock continues to run if the RTIF(RTI interrupt flag) is set,

regardless of the RTICTL register setting or RTIWAI bit setting. This
can lead to faulty operation in the following scenarios.

1. If WAIT mode is entered with the RTIWAI bit set, RTIE bit cleared,
and the RTIF set, the RTI clock, and RTI counters will continue to
operate in WAIT mode and consume current.

2. If The RTICTL register is cleared(RTICTL=$00) while the RTIF is set,
the RTI clocks will continue to run until the RTIF is cleared.

3. If a new non zero value is written to the RTICTL register when the
RTIF is set, the first RTI time-out period following the write may not
be the correct duration.

Workaround


Clear the RTICTL register and then RTIF prior to entering WAIT mode or

before writing a new non zero value to the RTICTL register.



SPI locks if disabled during message transmissionMUCts00429

Description

In master mode during a transmission SPI locks if SPE bit is cleared.

After re-enabling, writing to SPIDR does not result in message
transmission.

Workaround


Disable the SPI module only if transmission queue is empty (SPTEF=1) and

transfer is complete (SPIF=1). Add a delay of one SCK period after the
SPI interrupt flag is set (SPIF=1) before disabling the SPI.







CRG: Self Clock Frequency too highMUCts00434

Description

The self clock mode frequency,fSCM, can exceed the maximum specified

value. In this case the clock quality check will always fail for EXTAL
frequencies below 800kHz. This affects three additional spec values.

1. The clock quality check may fail for EXTAL frequencies below 800kHz.
Therefore the crystal oscillator frequency range, fOSC, minimum value is
1.0MHz.

2. The PLL may not lock to the minimum specific PLL frequency of
8.0MHz. Therefore the VCO locking range, fVCO, minimum value is 12.0MHz.
This corresponds to a minimum 6.0MHz bus frequency (when using the PLL
as the source for the bus clock, PLLSEL = 1).

3. The clock quality check timeout minimum value is 0.25 seconds, not
0.45 seconds as previously stated in the documentation. The maximum
value is unaffected.




Workaround


1. Only use quartz crystals, resonators or oscillators >= 1MHz. 

2. Only synthesize PLL frequencies (PLLCLK) from 12MHz to the maximum
specified value (i.e. only synthesize bus frequencies >= 6MHz).





BDM loses sync when using PLL at high frequenciesMUCts00436

Description

When using the BDM constant clock source, i.e. CLKSW=0, with the PLL

engaged (PLLSEL=1) and a PLL frequency multiplication factor greater
than or equal to 2, the BDM can lose communication with the host system.

Workaround


Do not use the BDM constant clock source with the PLL engaged and a

frequency multiplication factor greater than or equal to 2. Set CLKSW=1
before engaging the PLL.




OSC: Clock Monitor Frequency lower than specifiedMUCts00459

Description

The clock monitor failure assert frequency is f_CMFA=(max:100khz,

typ:50kHz, min:25kHz) and not as the specifed f_CMFA=(max:200khz,
typ:100kHz, min:50kHz).

Workaround


None.



PWM channel early start after leaving emergency shutdown modeMUCts00463

Description

When recovering from the emergency shutdown mode by disasserting the

active level on the PWM emergency shutdown input pin and subsequently
asserting the PWMRSTRT bit, the enabled PWM channels do not hold the
shutdown output level (PWMLVL) until the corresponding counter passes
zero. This may result in a pulse of undefined length on enabled PWM
channels.

Workaround


None.



Breakpoint Module: potential extraneous data matchMUCts00468

Description

When using the breakpoint in full mode, there is a chance of a false

match. Internally there
is a separate read data bus and write data bus. When in full mode
with the read/write match function is disabled, both buses are always
compared to the contents of data match register. The circuit should only
match the active bus on any particular bus cycle. The false match can
occur if the address matches on a read cycle and matching data is on the
write data bus or the address matches on a write cycle and the matching
data is on the read data bus.




SPI can receive incorrect data in slave modeMUCts00470

Description

An SPI configured for slave mode operation can receive incorrect data.

If there are clock edges on SCK while SPE=0, and then SPE is set to one,
the received data will be incorrect. In CPHA=1 mode the SPI will
continue to receive incorrect data as long as SPE=1.

Workaround


Depending on the current SPI mode, the following bits must be configured

while disabling the SPI:

- Set CPHA=1 and ensure that the CPOL-bit is clear every time the SPI is
disabled from slave mode.
- Clear CPHA and ensure that CPOL is clear every time the SPI is
disabled
from master mode.






SPIF-flag is set wrongly in slave mode after SPI re-enablingMUCts00478

Description

The SPIF interrupt flag is erroneously set (and the SPI interrupt vector

is called if the SPIE interrupt enable bit is set) by the following
sequence of events:

1. Receive a byte of data with the SPI interface configured in slave
mode specifically with the CPHA and the CPOL bits set to 1.
2. Clear the SPIF interrupt flag bit in the SPISR status register by
reading the SPISR status register followed by a read of SPIDR data
register.
3. Disable the SPI module by clearing all bits in the SPICR1 control
register.
4. Re-enable the SPI module with the CPHA and the CPOL bits set to 1.





Workaround


   1. Avoid configuring the SPI module with both the CPHA and CPOL bits

set to 1.
OR
2. To clear the erroneous SPIF interrupt flag, the following sequence
must be followed:

If no other interrupts are configured:

Wait for a minimum of three bus cycles after re-enabling the SPI
module, then clear the SPIF interrupt flag by dummy reading the SPISR
status register followed by the SPIDR data register.

If other interrupts are configured and enabled:

1. Disable all interrupts by setting the interrupt mask bit of the
condition code register (CCR). This can be accomplished by
executing an SEI instruction.
2. Re-enable the SPI module by setting the SPE, CPHA and CPOL bits in
the SPICR1 control register. Wait for a minimum of three bus
cycles after re-enabling the SPI module, then clear the SPIF
interrupt flag by dummy reading the SPISR status register followed
by the SPIDR data register.
3. Re-enable all interrupts by clearing the interrupt mask bit of the
CCR. This can be accomplished by executing a CLI instruction.

Notes on using workarounds:

It is possible that a valid SPI interrupt condition may be masked and
cleared during the erroneous setting and resetting of the SPIF
interrupt flag if:

1. The interrupt service routine of an XIRQ interrupt takes more time
to execute than the time required to receive a byte of SPI data.
OR
2. A valid byte of SPI data is received as the SPIF interrupt flag is
being reset.



SPI locks if re-enabled as masterMUCts00479

Description

The SPI locks if it is disabled in master mode with CPHA=1 in SPICR1 and

re-enabled in master mode with CPHA=1.







Workaround


Make sure that CHPA is not set when SPI is disabled after a

transmission in master mode.





ATD: Incorrect offset of transfer curve for 8-bit resolutionMUCts00482

Description

8-bit mode transfer characteristic shows incorrect result of 17.5mV for

first transition. This is because independently of 8- or 10-bit
resolution an offset of 2.5mV is used which is only correct for 10-bit
resolution.



Workaround


None.



MEBI: Non-multiplexed addresses on PK change before end of cycleMUCts00502

Description

In expanded modes with the EMK emulate port k bit set and the EXSTR[1:0]

external access stretch bits 1 & 0 set to 01, 10 or 11 the
non-multiplexed addresses on PK[5:0] change during E clock high phase.



Workaround


If the external access is stretched (EXSTR[1:0] set to 01, 10 or 11) off

chip address latches should be used to register the non-multiplexed
addresses on PK[5:0].



SCI interrupt asserts only if an odd number of interrupts activeMUCts00510

Description

The SCI interrupt is only asserted if an odd number of interrupts

are enabled and set.

For example, if a transmit data register empty and a receive ready
interrupt are active at the same time, the CPU interrupt request
is not asserted. This can lead to missing interrupts or spurious
interrupts where the request gets deasserted before the CPU fetches the
interrupt vector. These spurious interrupts will be handled by
direction via the SWI interrupt vector.



Workaround


The problem is minimized by fast interrupt response times and slow

baud rates. Details of a workaround that greatly reduces the possibility
of this erratum occurring during the normal transmission and reception
of SCI data can be found in Engineering Bulletin EB614 "SCI Interrupt
Errata Workaround for HCS12 Family Devices" at www.nxp.com.

1) Single wire operation - use a mixture of interrupt and polling

Use only the receive interrupt and move the first bytes of a message
into the transmit queue using transmit data register empty flag
polling. When a new byte is received and the receive interrupt is
asserted, the transmit data buffer will be empty and a new byte can be
written for transmission.

2) Full duplex operation - use third interrupt method.

If the SCI interrupt is not asserted while a transmit or receive
interrupt is pending (because an even number of interrupts are pending),
the newly received byte will cause an overflow error and generate a
third interrupt. This will assert the CPU interrupt line as an odd
number of interrupts are now active. User software must detect the
overrun error and request a re-transmission of the last message frame.
Use care with this solution as one frame of data is lost and must be
recovered by user software. Flag bits should be polled at a frequency
directly proportional to the baud rate.




NVM Reliability ErrataMUCts00511

Description

Flash cycling performance is 10 cycles at -40 to + 125C.

Data Retention is specified for 15 years.

Note that data retention lifetime is specified for an average
temperature use profile.

Workaround


no 




EEPROM Reliability ErrataMUCts00512

Description

EEPROM cycling performance is 10K cycles at -40 to +125C.

Data retention is specified for 5 years on words after executing 10K
cycles. However, if only 10 cycles are executed on a word, then data
retention is specified for 15 years.

Note that data retention lifetime is specified for an average
temperature use profile.




Workaround


None.



MSCAN extended ID rejected if stuff bit between ID16 and ID15MUCts00522

Description

For 32-bit and 16-bit identifier acceptance modes, an extended ID CAN

frame with a stuff bit between ID16 and ID15 can be erroneously
rejected, depending on IDAR0, IDAR1, and IDMR1.

Extended IDs (ID28-ID0) which generate a stuff bit between ID16 and
ID15:

IDAR0 IDAR1 IDAR2 IDAR3
******** ***1111x xxxxxxxx xxxxxxxx

where x = 0 or 1 (don't care)
* = pattern for ID28 to ID18 (see following)

Affected extended IDs (ID28 - ID18) patterns:

a) xxxxxxxxx01 exceptions: 01111100001
xxxx1000001 except 11111000001

b) xxxxx100000 exception: 01111100000

c) xxxx0111111

d) x0111110000

e) 10000000000

f) 11111111111

g) 10000011111

When an affected ID is received, an incorrect value is compared to the
2nd byte of the filter (IDAR1 and IDAR5, plus IDAR3 and IDAR7 in 16-bit
mode). This incorrect value is the shift register contents before ID15
is shifted in (i.e. right shifted by 1).


Workaround


If the problematic IDs cannot be avoided, the workaround is to mask

certain bits with IDMR1 (and IDMR5, plus IDMR3 and IDMR7 in 16-bit
mode).

Example 1: to receive the message IDs
xxxx xxxx x011 111x xxxx xxxx xxxx xxxx
IDMR1 etc. must be 111x xxx1, i.e. ID20,19,18,15 must be masked.

Example 2: to receive the message IDs
xxxx 0111 1111 111x xxxx xxxx xxxx xxxx
IDMR1 etc. must be 1xxx xxx1, i.e. ID20 and ID15 must be masked.

In general, using IDMR1 etc. 1111 xxx1, i.e. masking ID20,19,18,SRR,15,
hides the problem.



SPIF flag is set wrongly in slave modeMUCts00531

Description

If an SPI is enabled in slave mode with the CPHA bit set, all other bits

in their reset state, and SS/SCK pins driven low then clearing the CPHA
bit will cause the SPIF bit to be set three Bus Clock cycles after the
CPHA bit is cleared.

Workaround


Change of CPHA bit should only occur while SPI is disabled

(SPE bit cleared).



SPIF flag is set wrongly -> SPI locks in master modeMUCts00548

Description

The SPIF interrupt flag is erroneously set and the SPI module locks-up

if the following sequence of events occur:

1. Receive a byte of data with the SPI interface configured in slave
mode.
2. Clear the SPIF interrupt flag bit in the SPISR status register by
reading the SPISR status register followed by a read of SPIDR data
register.
3. Disable the SPI module by clearing all bits in the SPICR1 control
register except the CPHA (clock phase) bit (set SPICR1 to $04).
4. Start the SPI master mode enable sequence by first writing the SPICR1
control register to $08 (clearing the CPHA (clock phase) bit and
setting the CPOL (clock polarity) bit). At this point the SPIF
interrupt flag is erroneously set and the SPI module locks-up.

Workaround


Write the SPICR1 control register to $0C (CPHA (clock phase) and CPOL

(clock polarity) bits set) before writing the register to $08 during the
re-enable sequence.



Missing external ECLK during reset vector fetchMUCts00565

Description

The reset conditions of the ECLK control logic in the MEBI 

inhibit the generation of 1 ECLK pulse during the reset
vector fetch. This can prevent the external logic from
latching the reset vector address.

Workaround


None.



SPIDR is writeable though the SPTEF flag is cleared.MUCts00570

Description

Data can be placed into the SPI Data Register (SPIDR) even though the

SPTEF flag is cleared. The SPTEF flag indicates whether the transmit
buffer is empty (SPTEF=1) or full (SPTEF=0). Data can be placed into the
SPI Data Register by reading SPISR with SPTEF=1 followed by a write to
the SPI Data Register. If SPTEF=0, a write to the SPI Data Register
should be ignored, according to the SPI specification. This is not true
for the current implementation, where data can be placed into the SPI
Data Register though SPTEF=0.




Workaround


Do not write to the SPI Data Register until you have

read SPISR with SPTEF=1.



FTS256K: Erase Verify impact on subsequent Erase operationsMUCts00575

Description

If the Erase Verify ($05) command is issued on an array that is not

erased as indicated by the FSTAT/ESTAT BLANK bit not being set upon
command completion, the execution of the Sector Erase ($40) or Mass
Erase ($41) command will not properly erase the intended region. The
Program ($20) command will execute properly.

Workaround


If the Erase Verify ($05) command is issued on an array that is not

erased, subsequent Sector Erase ($40) or Mass Erase ($41) commands must
be issued twice before the intended region is properly erased.



ECT: can't use channel 0-3 for OC if queuing is enabledMUCts00589

Description

When using one or more of channels 0-3 as output compare, while using

the remaining channels 0-3 in the enhanced input capture mode
(TFMOD=1,BUFEN = 1, LATQ = 0 in ICSYS register), the output compare(s)
will take place, but the output compare flag(s) will not be set.



Workaround


If a customer wants to use less than the maximum of 4 Input capture

channels in this mode the other channels left in 0-3 can not be
used as output compares since the OCIF flag never gets set.






MSCAN: Glitch filter exceeds spec limitsMUCts00590

Description

The specified MSCAN wake-up glitch filter pulse limits can be exceeded.

At low temp/high VDD the module may wake up from sleep mode on glitches
<2us while for pulses >5us it may not wake up from sleep mode at high
temp/low VDD.

The device operates at relaxed limits:

MSCAN Wake-up dominant pulse filtered: max. 1us
MSCAN Wake-up dominant pulse pass: min. 7us


Workaround


None.



Program & Erase of flash blocked in Normal Single Chip Mode when secureMUCts00603

Description

In normal single chip mode, when security is enabled, it is not 

possible to launch the Program ($20), Sector-Erase ($40) and Erase-
Verify ($05) commands in the flash. The Mass-Erase
($41) command can be launched.


Workaround


To enable the Program ($20), Sector-Erase ($40) 

and Erase-Verify ($05) commands in the flash, security must be
disabled via the backdoor key sequence. See Flash User Guide for
details of the backdoor key operation.




Program & Erase of EEPROM blocked in Normal Single Chip Mode when secureMUCts00604

Description

In normal single chip mode, when security is enabled, it is not 

possible to launch the Program ($20), Sector-Erase ($40), Sector-Modify
($60) and Erase-Verify ($05) commands in the EEPROM. The Mass-Erase
($41) command can be launched.

Workaround


To enable the Program ($20), Sector-Erase ($40), Sector-Modify ($60) 

and Erase-Verify ($05) commands in the EEPROM, security must be
disabled via the backdoor key sequence. See Flash User Guide for
details of the backdoor key operation.



PE7 (XCLKS) is not pulled up internally when reset in emulation modeMUCts00616

Description

When the MCU is reset in emulation expanded wide or narrow mode, PE7

(XCLKS) is not pulled up internally.



Workaround


When using the MCU in expanded emulation wide / narrow mode, ensure that

PE7 (XCLKS) is driven by an external device during RESET low.



Key wake-up: Glitch filter exceeds upper 10us limitMUCts00618

Description

The specified maximum pulse width limit of the key wake-up glitch filter

may be exceeded during high temperature and low supply voltage
conditions. The MCU may not wake from STOP mode on pulses slightly
greater than or equal to 10us.





Workaround


The glitch filter now operates at a maximum pulse width limit of 14us.

Ensure that valid MCU wake pulses have a duration of at least 14us.



Reduced operating voltage range for 25MHzMUCts00648

Description

1. Operating (bus) frequencies <= 20MHz


- No change in operating spec i.e. 4.5V - 5.25V for 'C', "V" and "M"
parts

2. Operating (bus) frequencies > 20MHz but <= 25MHz

- 'C' part, no change in operating spec i.e. 4.5V - 5.25V

- 'V' & 'M' parts, change of operating spec to 4.75V - 5.25V

Workaround


None.



SPI2: SS2 and SCK2 inputs swapped if routed on Port HMUCts00655

Description

The input connections from PH7(SS2) and PH6(SCK2) to the SPI2 module are

swapped. Therefore the SS2 input is related to PH6 and the SCK2 input is
related to PH7. The output connections related to both pins are not
affected.

Master mode operation is unaffected if using SS as output (MODFEN and
SSOE asserted). In applications, master/slave mode switching must not be
done due to fixed system pin connections.


Workaround


Restrict the use of SPI2 on Port H to either master mode or slave mode.

Slave mode operation requires that the layout of the SS2 and SCK2 traces
on PortH be swapped round. Master/slave mode switching is not possible
due to swapped signal connections.



SPTEF flag set erroneouslyMUCts00702

Description

When the SPI is enabled in master mode, with CPHA bit set, back to back

transmissions are possible.

When a transmission completes and a further byte is available in the SPI
Data Register, the second transmission begins direclty after "minimum
trailing time".

The problem occurs, when after the SPTEF flag has been set a further
byte is written into the SPI Data Register during the "1st pulse" of a
subsequent transmission.

|--> next tx
7th pulse 8th pulse 1st pulse
SCK _______|^^^^^^^|_______|^^^^^^^|_______|^^^^^^^|_______

SPTEF _____________________________________|^^|____|^^^^^^^^
^ ^ ^
| | |
| | SPTEF flag set again
| | (WRONG)
| |
| Write to SPIDR during
| "1st pulse"
|
End of tx SPTEF flag is
set

Then the SPTEF flag is set at the falling SCK edge of the "1st
pulse" and data is transfered from the SPI Data Register to the transmit
shift register. The result is that the transmission is corrupted.


Workaround


After the SPTEF flag has been set, a delay of 1/2 SCK period has to be

added, before storing data into the SPI Data Register.



ATD: Flags in ATDSTAT0 do not clear by writing '1', ETORF erroneously setMUCts00741

Description

For the flags SCF, ETORF and FIFOR in ATDSTAT0 it is specified that

writing a '1' to the respective flag clears it. This does not work.
Writing '1' to the respective flag has no effect.

The ETORF flag is also set by a non-active edge, e.g. falling edge
trigger (ETRILE=0, ETRIGP=0). ETORF is set on both falling edges and
rising edges while conversion is in progress.

Workaround


SCF 

1. Use the alternative flag clearing mechanisms:
a. Write to ATDCTL5 (a new conversion sequence is started)
b. If AFFC=1 a result register is read
ETORF
1. Use the alternative flag clearing mechanisms:
a. Write to ATDCTL2, ATDCTL3 or ATDCTL4 (a conversion sequence
is aborted)
b. Write to ATDCTL5 (a new conversion sequence is started)
2. Avoid external trigger edges during conversion process by using short
pulses
3. Ignore ETROF flag

FIFOR
1. Use the alternative flag clearing mechanism:
a. Start a new conversion sequence
(write to ATDCTL5 or external trigger)



SPI in Mode Fault state, but MISO output buffer not disabled.MUCts00747

Description

When the SPI is in Mode Fault state (MODF flag set), according to the

specification, all SPI output buffers (SS, SCK, MOSI, MISO) should be
disabled. However, the MISO output buffer is not disabled.

Workaround


None.



ATD: Write to ATDCTL5 may not clear SCF, CCF and ASCIF flagsMUCts00792

Description

If a write to ATDCTL5 happens at exactly the bus cycle when an ongoing

conversion sequence ends, the SCF, CCF and (if ASCIE=1)
ASCIF flags remain set and are NOT cleared by a write to ATDCTL5.

Workaround


1. Make sure the device is protected from interrupts (temporarily

disable interrupts with the I mask bit).
2. Write to ATDCTL5 twice.



MISO not kept after sixteenth SCK edge.MUCts00794

Description

In SPI slave mode with CPHA set, MISO can change erroneously after a

transmission, two to three bus clock cycles after the sixteenth SCK
edge. This can lead to a hold time violation on the SPI master.


Workaround


There are two possible workarounds for this problem: 


1. Decrease the bus clock of the slave SPI to satisfy the "Master
MISO Hold Time".
Tbus(Slave) >= 0.5 * "Master MISO Hold Time"

2. Software workaround:
The slave has to transmit a dummy byte after each data byte,
which must fulfil the following requirements:

- The first bit of the dummy byte to be transmitted (depending on
LSBFE bit) must be equal to the last bit of the data byte
transmitted before. The dummy byte has to be stored into SPIDR
during the transmission of the corresponding data byte.
=> MISO does not change after the data byte.

- The Master has to receive two bytes, the data byte and the dummy
byte.
=> Master receives the data byte correctly and has to skip the
dummy byte.



ECT: Input pulse shorter than delay counter period recognised as a validMUCts00811

Description

According to the observation, input pulse (high/low) whose pulse width

is shorter than delay counter window is mistakenly recognized as as
valid pulse. Hence the ic flags will be set and may result in an IRQ if
IRQ is enabled.



Workaround


A software workaround is available.


User software should check the logic level of the input capture pin
within the interrupt service routine and compare this with the logic
level when the input is not asserted. This can be performed using the
appropriate registers in the port integration module.

If the pin reads the logic level of the inactive state, the pulse is
shorter than the time defined in the delay counter control register
plus the interrupt latency. In this case, the pulse triggering the
input capture is not valid (too short), hence the interrupt can be
acknowledged and exited without further action taking place. If the pin
reads the logic level of the active state, the input pulse is valid and
the interrupt should be acknowledged and the correct input capture
service routine executed.

The effectiveness of this workaround must be evaluated by identifying
the worst case latency involved in the call of the ISR. To maximise the
effectiveness of pulse rejection, users must consider checking the
value in the capture register against the free-running timer on every
new capture.



PLL: If osc_clock is 2 to 3 times pll_clock, STOP can cause SCM or resetMUCts00814

Description

This Erratum applies only to systems where PLL is used to divide down

the osc_clock by a ratio between 2 and 3.

If

1) pll_clock (PLLON=1) is running
and
2) 2 < osc_clock/pll_clock < 3
and
3) full stop mode is entered (STOP instruction with PSTP Bit =0)

there is a small possibility that when entering full stop mode the chip
reacts as follows:
1) if self clock mode is disabled (SCME=0) monitor reset is asserted.
The system does NOT enter stop mode.
or
2) if self clode mode and SCM interrupt are enabled (SCME=1 and SCMIE=1)
a self clock mode interrupt is generated. The SCMIF flag is set.
The system does NOT enter stop mode.
or
3) if SCME=1 and SCMIE=0 the system will enter full stop mode.
But after wakeup self clock mode is entered without doing the
specified clock quality check. The SCMIF flag is set.

Workaround


1) Avoid osc_clock/pll_clock ratios between 2 and 3.

or
2) if you really require osc_clock/pll_clock ratio between 2 and 3
do the following before going into stop.
a) deselect PLL (PLLSEL=0)
b) turn off PLL (PLLON=0)
c) enter stop
d) exiting stop: turn on PLL again (PLLON=1)



Flash: ACCERR is not set for a Byte AccessMUCts00844

Description

Starting a command sequence with a MOVB array write instruction (Byte

Write) will not generate an access error. The command is processed
normally programming the array according to the content (word) of the
data register while only the high byte in the FDATA register holds valid
information.

Workaround


Avoid the use of MOVB instruction for array program operations.  




EE: ACCERR is not generated for a Byte AccessMUCts00868

Description

Starting a command sequence with a MOVB array write instruction (Byte

Write) will not generate an access error. The command is processed
normally programming the array according to the content (word) of the
data register while only the high byte in the FDATA register holds valid
information.

Workaround


Avoid the use of MOVB instruction for array program operations. 




CCIF command complete flag may be erroneously set.MUCts00973

Description

When pipeline programming the flash NVM array, the CCIF (command

complete flag) may be momentarily set between pipelined commands. This
is due to a bug with the physical flash block interface which restarts
the next command as a new sequence when transitioning from one physical
flash row to the next, rather than recognising the next command as part
of an ongoing command sequence. Since the location of physical flash row
boundaries differs between devices, it is difficult to specify whether
CCIF flag set instances are erroneous or not. The workaround should be
closely followed to avoid this issue.

Workaround


The code which is checking for the end of command operations should

check for both CBEIF (Command Buffer Empty Interrupt Flag) and CCIF
(Command Complete Interrupt Flag) to be set, as an indication of the end
of operations, rather than just the CCIF Flag.



CCIF command complete flag may be erroneously set.MUCts00974

Description

When pipeline programming the EEPROM NVM array, the CCIF (command

complete flag) may be momentarily set between pipelined commands. This
is due to a bug with the physical EEPROM block interface which restarts
the next command as a new sequence when transitioning from one physical
EEPROM row to the next, rather than recognising the next command as part
of an ongoing command sequence. Since the location of physical EEPROM
row boundaries differs between devices, it is difficult to specify
whether CCIF flag set instances are erroneous or not. The workaround
should be closely followed to avoid this issue.

Workaround


The code which is checking for the end of command operations should

check for both CBEIF (Command Buffer Empty Interrupt Flag) and CCIF
(Command Complete Interrupt Flag) to be set, as an indication of the end
of operations, rather than just the CCIF Flag.



STOP instruction may set flash ACCERR flag.MUCts00978

Description

If the FCLKDIV flash clock divider register has been loaded, and the

flash is not executing a command (flash CCIF command complete flag is
set), the execution of a STOP instruction will erroneously set the
ACCERR access error bit in the FSTAT flash status register.

Workaround


The ACCERR bit in the FSTAT register must be cleared after the execution

of a STOP instruction if the FCLKDIV register has been loaded.



STOP instruction may set EEPROM ACCERR flag.MUCts00985

Description

If the ECLKDIV EEPROM clock divider register has been loaded, and the

EEPROM is not executing a command (EEPROM CCIF command complete flag is
set), the execution of a STOP instruction will erroneously set the
ACCERR access error bit in the ESTAT EEPROM status register.

Workaround


The ACCERR bit in the ESTAT register must be cleared after the execution

of a STOP instruction if the ECLKDIV register has been loaded.



CCF flags in ATDSTAT1 register might fail to setMUCts01032

Description

The setting of the CCF7-0 flags in ATDSTAT1 register

is not independent of the clearing.
A clear on CCFx (e.g. Bit AFFC=1 and read of ATDDRx)
which occurs in exactly the same bus cycle as the setting of any other
flag CCFy (x,y = 0,1,..,7; x!=y) masks the setting of CCFy.
CCFy will not set in this special case although the corresponding
conversion has completed and the result (ATDDRy) is valid.

Workaround


None.



ATD: Clearing of CCF flags in ATDSTAT1 by write of ATDCTL5 might not workMUCts01043

Description

Starting a new conversion by writing to the ATDCTL5 register should

clear all CCF flags in the ATDSTAT1 register.
This does not always work if the write to ATDCTL5 register
occurs near the end of an ongoing conversion.
Although all CCF flags are cleared one CCF flag might be
set again within the 1st ATD clock period of the new conversion.

Workaround


If the unexpected setting of one CCF flag can not be

accepted by the application one of the following
workarounds can be taken:
1) Abort conversion (e.g. by write to ATDCTL3)
Pause for 2 ATD clock periods
Start new conversion
2) Ignore first conversion sequence and clear CCF flags




MSCAN: Data byte corrupted in receive bufferMUCts01086

Description

When the foreground receive buffer (RxFG) is read with the Receiver Full

Flag (RXF) set, the value of one or more data bytes may be incorrect due
to corruption after the message reception. The corruption can occur at
the end of a message transmission from any of the three transmit message
buffers of the same msCAN module. The affected data byte is overwritten
by a byte of the corrupting transmit buffer's Time Stamp Register, TSRH
for even, TSRL for odd addresses affected, respectively. The value
written is zero ($00) if the internal timer has not been enabled (TIME=0
in CANCTL0).

The corruption can only occur if all of the following three conditions
are met:

1. Rx and Tx message length relationship
If the number of data bytes transmitted, n, is five or less, Data
Segment Register (n+2) in RxFG is corrupted, i.e. DSR2 if n=0, .., DSR7
if n=5.
No corruption occurs for n > 5. Also, DSR0 and DSR1 are never affected.

2. Timing
A received message may contain corrupted data if RxFG is read after the
end of a message transmission from the same msCAN module.
No corruption is seen if all received messages are read within the time
window beginning when RXF is set and ending with the completion of
transmission of a subsequent message by the same msCAN module (the
'green window'). The width of the green window depends on many factors:
application software (Tx message scheduling, Rx/Tx interrupt priorities,
etc.), bus load, baud rate, and transmit message length. The minimum
(guaranteed) green window width is 376us for 125kbps, for example. This
minimum value occurs only in case of a transmit message following
back-to-back to the receive message, and for zero data bytes and zero
stuff bits. The green window width inversely scales with the baud rate.

3. Receive FIFO Buffer #
Only receive buffer 0 (Rx0) of the 5-stage FIFO can be affected.
At least four out of every five messages received are not affected.

Workaround


In affected systems where the lengths of messages can be adjusted, using

six or more bytes for transmission eliminates the issue completely.
Systems using an MCU with unused msCAN modules should use one to
transmit only and one to receive only, to completely avoid the issue.
For other systems the likelihood of problem occurrence can be further
reduced by maximizing the receive interrupt priority, i.e. use CAN0 for
the most critical bus in a multi-bus application, and/or promoting the
msCAN receive interrupt to highest priority using the HPRIO register.
In (control) systems where the signal representation can be adjusted,
and the time stamp is not used (TIME=0), mapping $00 to an 'illegal'
signal would allow problem detection and appropriate software means of
reaction.
In systems where all byte values are legal (e.g. data download),
checksums and/or parities can be used to signal problem occurrence and
allow for proper handling (e.g. request for retransmission).
Alternatively, the use of data filter algorithms may suppress or at
least reduce the effect of the problem.



MSCAN: Time stamp corrupted in receive bufferMUCts01090

Description

When the foreground receive buffer (RxFG) is read, with the Receiver

Full Flag (RXF) set, the value of the Time Stamp Register may be
incorrect due to corruption. The Time Stamp Register is written
correctly when the message is received, but may be overwritten by the
timer value at the end of a subsequent reception. The corruption can
only occur close to a data overrun, when the receive buffer FIFO is
full.

The problem occurs whenever the following two conditions are met:

1. Receive buffer system is full
All five receive buffers contain valid messages waiting to be read by
the application.

2. Another valid message is seen on the bus. This message must be sent
from another node, i.e. it must not be transmitted from the respective
msCAN module itself.

At the end of the message in 2. the Time Stamp Register of the oldest
message in the receive FIFO is overwritten.

Note: if the message in 2. passes the message filter system the Overrun
Interrupt Flag (OVRIF) is also set.

Workaround


The application software has to ensure to read the receive messages in

due time to avoid data overrun in any case. This will automatically
minimize the risk of a Time Stamp Register overwrite event.



MSCAN: Message erroneously accepted if bus error in bit 6 of EOFMUCts01367

Description

If a particular error condition occurs within the end of frame segment

(EOF) of a CAN message, the msCAN module recognises and accepts a
non-valid message as being valid, contrary to the CAN specification. The
msCAN module incorrectly validates messages after five recessive bits of
the end of frame instead of after six bits. If a bus error occurs during
the sixth bit of end of frame, the msCAN module will already have
accepted the message as valid, even although an error frame is
transmitted and the receive error counter is incremented.

The CAN protocol states that message validation differs between bus
transmitter and receiver devices (refer to part B, section 5 of CAN
protocol for details). In the case where the 7th bit of the EOF segment
is dominant, the message is valid for the receiver but not for the
transmitter. This erratum extends this case to the 6th bit of the EOF
segment.

Workaround


This erratum will not be an issue if the application software is

protected against the known double receive problem of the CAN protocol.
This problem occurs when a message is not recognised as valid by the
transmitter, but is recognised as valid by a receiver, as described
above. When this happens, the message is re-transmitted and hence the
receiver will receive the same message twice.



ECT_16B8C: Output compare pulse is inaccurateMUCts01532

Description

The pulse width of an output compare (which resets the free running

counter when TCRE = 1) will measure one more bus clock cycle than
expected.



Workaround


The specification has been updated. Please refer to revision 01.06 (28

Apr 2010) or later.

In description of bitfield TCRE in register TSCR2,a note has been added:
TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler
counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to
0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it
will last only one bus cycle then reset to 0.







Possible manipulation of return address when exiting BDM active modeMUCts01968

Description

Upon leaving BDM active mode, the CPU return address is stored

temporarily for a few cycles in the BDM shift register. If a BDM command
transmission is detected during this time, the return address will be
manipulated in the BDM shift register. This situation is likely to occur
when a CPU BGND instruction is executed in user code during debugging
under the following conditions:

(i) The BDM module is not enabled AND
(ii) BDM commands are sent from the host

If this situation occurs, the CPU will execute BDM firmware and will
check the status of the ENBDM bit in the BDMSTS register. If the BDM is
disabled, the ENBDM bit will be clear, and hence the BDM firmware will
be exited and the shift register manipulation described above will occur.

Workaround


Avoid using the BGND instruction when the ENBDM bit in the BDMSTS

register is cleared.



MEBI: Missing ECLK edge on first external access after mode switchingMUCts02345

Description

If the ECLK is used as an external bus control signal (ESTR=1) the first

external access is lost after switching from a single chip mode with
enabled ECLK output to an expanded mode. The ECLK is erroneously held in
the high phase thus the first external bus access does not generate a
rising ECLK edge for the external logic to latch the address. The ECLK
stretches low after the lost access resulting in all following external
accesses to be valid.

Workaround


Enter expanded mode with ECLK output disabled (NECLK=1). Enable the ECLK

after switching the mode before executing the first external access.



ATD: In FIFO mode, write to ATDCTL5 does not clear CC2-0MUCts02718

Description

In FIFO mode (FIFO=1 in ATDCTL3) the conversion results counter CC2-0

(in ATDSTAT0)
is not cleared by writing to ATDCTL5 to start a new conversion sequence
(and abort any ongoing one).
This means that in the new conversion sequence the first result will not
be placed in result register 0 (ATDDR0) but in the result register
indicated by the existing conversion counter value (CC2-0).

This erratum only affects the behaviour of FIFO mode when initialising a
new conversion sequence. In a continuous conversion sequence (SCAN = 1)
FIFO mode behaves as specified with the results conversion counter not
cleared following each sequential conversion.

Note: Version V02.12 of ATD_10B8C block guide was updated for
clarification of the FIFO mode behaviour.


Workaround


In FIFO mode, precede any write to ATDCTL5 with a write to one of the

control registers ATDCTL4, ATDCTL3 or ATDCTL2 (which will clear the
results counter CC2-0).



EEPROM Program Failure during Sector-ModifyMUCts03194

Description

At oscillator frequencies above 4MHz the Program step of the EEPROM

Sector-Modify command can fail depending on the bus frequency. As a
result, no programming of the EEPROM occurs. There is no impact to the
Erase step of the Sector-Modify command. Since a partial programming of
the word cannot occur, there is not a reliability issue caused by the
Sector-Modify command if the programmed word is verified.

Oscillator Bus
Frequency Frequency
---------- ----------------------
4MHz No Issue
8MHz Fbus <20MHz : No issue
16MHz Fbus <16MHz : No issue




Workaround


Use seperate Erase and Program commands in place of the Sector-Modify

command. If the Sector-Modify command is used and fails the program step
as confirmed by a user verification step, a Program command alone can be
used to effectively complete the operation since the erase step does
successfully erase the sector.



EETS4K: Erase Verify impact on subsequent Erase operationsMUCts03345

Description

If the Erase Verify ($05) command is issued on an array that is not

erased as indicated by the FSTAT/ESTAT BLANK bit not being set upon
command completion, the execution of the Sector Erase ($40) or Mass
Erase ($41) command will not properly erase the intended region. The
Program ($20) command will execute properly.

Workaround


If the Erase Verify ($05) command is issued on an array that is not

erased, subsequent Sector Erase ($40) or Mass Erase ($41) commands must
be issued twice before the intended region is properly erased.



MSCAN: Corrupt ID may be sent in early-SOF conditionMUCts03575

Description

The initial eight ID bits will be corrupted if a message is set up for

transmission during the third bit of INTERMISSION and a dominant bit is
sampled leading to an early-SOF*.

The CRC is calculated from the resulting bit stream so that the
receiving nodes will still validate the message.

An early-SOF condition may only occur if the oscillators in the network
operate at a tolerance range which could lead to a cumulated phase error
after 11 bit times larger than phase segment 2.

In case arbitration is lost during transmission of the corrupt
identifier, a non-corrupted ID will be sent with the next attempt if the
transmit request remains active.

*The CAN protocol condition referred to as 'early-SOF' in this erratum
is detailed in "Bosch CAN Specification Version 2.0" Part A, section 9,
and a Note to section 3.2.5 INTERFRAME SPACING – INTERMISSION in Part B.

Workaround


Due to increased oscillator tolerance a transmission start in the third

bit of intermission is possible and allowed. The errata can be avoided
when calculating the maximum oscillator tolerance of the overall CAN
system. The phase error after 11 bit times due to the oscillator
tolerance should be smaller than phase segment 2.

If an early-SOF cannot be avoided the following methods will provide
prevention:

- Assigning the same value to all upper eight ID bits in the network
- Allocating dedicated data length codes (DLC) to every identifier used
in the network and checking for correspondence after reception
- Assigning only IDs (x) which do not consist of a combination of other
assigned IDs (y,z) and using the acceptance filters to reject
erroneous messages, i.e.
- for standard frames: IDx[11:0] != {IDy[11:3], IDz[2:0]}
- for extended frames: IDx[28:21] != {IDy[28:21],IDz[20:0]}



PWM: Emergency shutdown input can be overruledMUCts04075

Description

If the PWM emergency shutdown feature is enabled (PWM7ENA=1) and PWM

channel 7 is disabled (PWME7=0) another lower priority function
available on the related pin can take control over the data direction.
This does not lead to a problem if input mode is maintained. If the
alternative function switches to output mode the shutdown function may
unintentionally be triggered by the output data.


Workaround


When using the PWM emergency shutdown feature the GPIO function on the

pin associated with PWM channel 7 should be selected as an input.

In the case that this pin is selected as an output or where an
alternative function is enabled which could drive it as an output,
enable PWM channel 7 by setting the PWME7 bit. This prevents an
active shutdown level driven on the (output) pin from resulting in an
emergency shutdown of the enabled PWM channels.




ECT: Channel 0 - 3 Input Capture interrupts inhibited when BUFEN=1, LATQ=0 and NOVWx=1MUCts04109

Description

Channel 0 – 3 Input Capture interrupts are inhibited when BUFEN=1, 

LATQ=0 and NOVWx=1 if an Input Capture edge occurs during or between a
read of TCx and TCxH or between a read of TCx/TCxH and clearing of CxF.


Details:

When any of the buffered input capture channels 0 - 3 are configured
for buffered/queue mode (BUFEN=1, LATQ=0) each of the channel’s input
capture holding registers and each channel’s associated pulse
accumulator and its holding register are enabled. When the input
capture channel is enabled by writing to a channel’s EDGxB and EDGxA
bits, both the input capture and input capture holding register are
considered empty. The first valid edge received after enabling a
channel will latch the ECT’s free running counter into the input
capture register (TCx) without setting the channel’s associated CxF
interrupt flag. The second valid edge received will transfer the value
of the input capture register, TCx, into the channel’s TCxH holding
register, latch the current value of the free running timer into the
input capture register and set the channel’s associated CxF interrupt
flag. In this condition, both the TCx and TCxH registers are
considered ‘full’.

If a corresponding channel’s NOVWx bit in the ICOVW register is set,
the capture register or its holding register cannot be written by a
valid edge at the input pin unless they are first emptied by reading
the TCx and TCxH registers. The act of reading the TCx and TCxH
registers and clearing the channel’s associated CxF interrupt flag
involves three separate operations. Two 16-bit read operations and an 8-
bit write operation.

If a channel’s associated CxF interrupt flag is cleared before reading
the TCx and TCxH registers and if a valid input edge occurs during or
between the reading of the capture and holding register, a channel’s
associated CxF interrupt flag will no longer be set as the result of
valid input edges. For example:

Clear CxF
|
|
V
Read TCx <----+
| |
|<--------+--- Valid Input Edge Occurs
V |
Read TCxH <---+

If the TCx and TCxH registers are read before a channel’s associated
CxF interrupt flag is cleared and if a valid input edge occurs between
the reading of TCx/TCxH and the clearing of a channel’s associated CxF
interrupt flag, a channel’s associated CxF interrupt flag will no
longer be set as the result of valid input edges. For example:

Clear CxF
|
|
V
Read TCx
|
|<------------ Valid Input Edge Occurs
V
Read TCxH


Systems that service the interrupt request and read the TCx and TCxH
registers before the next valid edge occurs at a channel’s associated
input pin will avoid the conditions under which the errata will occur.

Workaround


A simple workaround exists for this errata:


1. Clear the input capture channel’s associated CxF bit.
2. Disable the input capture function by writing 0:0 to a channel’s
EDGxB and EDGxA bits.
3. Read TCx
4. Read TCxH
5. Re-enable the input capture function by writing to a channel’s EDGxB
and EDGxA bits.


Code Example:

unsigned char ICSave;
unsigned int TC0Val;
unsigned int TC0HVal;

ICSave = TCTL4 & 0x03; /* save state of EDG0B and EDG0A */
TFLG1 = 0x01; /* clear ECT Channel 0 flag */
TCTL4 &= 0xfc; /* disable Channel 0 input capture function */
TC0Val = TC0; /* Read value of TC0 */
TC0HVal = TC0H; /* Read value of TC0H */
TCTL4 |= ICSave; /* Restore Channel 0 input capture function */



PWM: Wrong output level after shutdown restart in 16bit concatenated channel modeMUCts04215

Description

When the PWM is used in 16-bit (concatenation) channel and the emergency

shutdown feature is being used, after de-asserting PWM channel 7
(note:PWMRSTRT should be set) the PWM channels (PP0-PP6) do not show the
state which is set by PWMLVL bit when the 16-bit counter is non-zero.


Workaround


None. 




PWM: Wrong output value after restart from stop or wait modeMUCts04219

Description

In low power modes (stop/p-stop/wait – PSWAI=1) and during PWM PP7

de-assert and when PWM counter reaching 0, the PWM channel outputs
(PP0-PP6) cannot keep the state which is set by PWMLVL bit.



Workaround


None. 



© NXP Semiconductors, Inc., 2011. All rights reserved.