NXP® SemiconductorsMSE9S12E128_0L08M
Mask Set ErrataRev. February 13, 2011



MC9S12E128, Mask 0L08M


Introduction
This errata sheet applies to the following devices:

MC9S12E128



MCU Device Mask Set Identification

The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1K79X. All standard devices are marked with a mask set number and a date code.



MCU Device Date Codes

Device markings indicate the week of manufacture and the mask set used. The date is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the work week. For instance, the date code "0201" indicates the first week of the year 2002.



MCU Device Part Number Prefixes

Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix.



Errata System Tracking Numbers

MUCtsXXXXX is the tracking number for device errata. It can be used with the mask set and date code to identify a specific erratum.



Errata Summary


Errata NumberModule affectedBrief DescriptionWork-
around
MUCts00677 pim_9e128 PIM - PORTQ[3:0], GPIO functionality YES
MUCts00678 pmf_15b6c PMF - Manual Correction in complementary mode YES
MUCts00679 pmf_15b6c PMF - Deadtime Generation causes glitches on PMF outputs YES
MUCts00681 S12_bdm Spurious SYNC pulse YES
MUCts00696 sci Polarity of Infrared RX and TX data is inverted compared to IrDA spec YES
MUCts00699 pmf_15b6c PMF - Non-zero prescalar causes slightly reduced deadtime insertion YES
MUCts00708 spi SPTEF flag set erroneously YES
MUCts00736 atd_10b16c flags in ATDSTAT0 do not clear by writing '1', ETORF erroneously set YES
MUCts00742 spi SPI in Mode Fault state, but MISO output buffer not disabled. NO
MUCts00762 S12_cpu DBG: CPU erroneously causes BSRs to be recorded in trace buffer YES
MUCts00763 S12_dbg DBG full mode triggers do not work properly in register space writes NO
MUCts00765 S12_dbg Forced trigger delay before taking effect YES
MUCts00779 S12_dbg DBG: LOOP1 mode with break to BDM captures all change of flow instructions YES
MUCts00799 spi MISO not kept after sixteenth SCK edge. YES
MUCts00801 atd_10b16c Write to ATDCTL5 may not clear SCF, CCF and ASCIF flags YES
MUCts00820 crg PLL: If osc_clock is 2 to 3 times pll_clock, STOP can cause SCM or reset YES
MUCts00856 fts128k1 Flash: ACCERR is not set for a Byte Access YES
MUCts00992 fts128k1 STOP instruction may set flash ACCERR flag. YES
MUCts00994 fts128k1 FTS128k1: Flash block protect transitions unlimited NO
MUCts00995 fts128k1 Additional write protection exists via mirroring NO
MUCts01009 fts128k1 Array writes immediately after FPROT write do not set PVIOL flag. YES
MUCts01024 atd_10b16c CCF flags in ATDSTAT2/1 registers might fail to set NO
MUCts01034 atd_10b16c Clearing of CCF flags in ATDSTAT2/1 by write of ATDCTL5 might not work YES
MUCts01053 spi SPIDR can be written without reading SPTEF flag as set YES
MUCts01079 S12_dbg DBG: BDM firmware code execution may erroneously cause forced trigger YES
MUCts01430 S12_cpu Tagged breakpoints missed if tag attach and interrupt are simultaneous NO
MUCts01965 S12_bdm Possible manipulation of return address when exiting BDM active mode YES
MUCts02143 mcu_9e128 Reduced flash program temperature range and increased programming time NO
MUCts02415 S12_mebi MEBI: Missing ECLK edge on first external access after mode switching YES
MUCts03793 S12_mmc S12_mmc: /XCS is erroneously asserted on accesses to internal BDM resources NO
MUCts04076 pwm_8b6c PWM: Emergency shutdown input can be overruled YES
MUCts04162 tim_16b4c TIM_16B4C: Output compare pulse is inaccurate YES
MUCts04223 pwm_8b6c PWM: Wrong output level after shutdown restart in 16bit concatenated channel mode NO
MUCts04225 pwm_8b6c PWM: Wrong output value after restart from stop or wait mode NO



PIM - PORTQ[3:0], GPIO functionalityMUCts00677

Description

General purpose input/output functionality will not be available for

pins, PORTQ[3:0], if fault function is enabled on any one of these 4
pins. The fault function for a fault pin is enabled by setting the
corresponding bit in PMF Fault Pin Enable register (PMFFPIN).

Workaround


Do not use General purpose I/O functionality when any one of the 4 fault

pins (PORTQ[3:0]) are enabled for fault functionality.




PMF - Manual Correction in complementary modeMUCts00678

Description

The PMF manual correction method is one of the 2 methods used to correct

distortion during deadtime generation. Deadtime generation is done only
during complementary mode. This method does not work for Generators B &
C, but works for generator A.

Workaround


PortQ[4] can be used for testing manual correction control in

complementary mode - both manual and automatic methods.
This pin can also be used as GPIO.
PortQ[4] pin is the current sense pin for generator A.




PMF - Deadtime Generation causes glitches on PMF outputsMUCts00679

Description

Using deadtime in complementary mode causes glitches in the PMF output

pins, PP[5:0]. At the start of deadtime, prior to the output rising
edges, glitches of 3-4 ns duration are seen at the PMF outputs.



Workaround


There are 3 types of workaround for this issue:

1. A filter can be used at the pins, which blocks the glitches. The use
of a filter also reduces the pulse-widths of the actual PMF outputs.
Hence, do not use a very low duty cycle in this case.

2. The complementary outputs with deadtime insertion can be mimicked by
using the output control feature of the PMF. Just set the OUTCTLx bits
in the PMF Output Control Register (PMFOUTC) for the corresponding
channels. Then, write the desired value to the corresponding bits in
the PMF Output control Bit Register (PMFOUTB). Included with this
errata is an example of how to write to the PMFOUTB Register to achieve
the emulated deadtime effect.

3. Complementary mode can be used without using deadtime.







Spurious SYNC pulseMUCts00681

Description

A spurious BDM SYNC pulse could be transmitted if the delay between 

commands is such that the first negative edge of a new command occurs
exactly 128 cycles after the last negative edge of the previous command.

Workaround


Keep the delay between commands greater than 128 cycles. 




Polarity of Infrared RX and TX data is inverted compared to IrDA specMUCts00696

Description

  The polarity of Infrared TX and RX data are inverted compared to what

is defined in IrDA spec. A zero is represented by a narrow low
pulse instead of a narrow high pulse.



Workaround


  If same polarity is required as is defined in IrDA specification, an

external inverter is needed for RXD and TXD pin respectively when
Infrared is enabled.






PMF - Non-zero prescalar causes slightly reduced deadtime insertionMUCts00699

Description

A non-zero prescalar value in PRSCx bit positions in the PMFFQCx (x can

be A, B or C) registers, can cause a slightly reduced deadtime value to
be inserted. The deadtime value is one bus cycle less than the correct
value.

Workaround


A "00" data value in the PRSCx bit positions in the PMFFQCx (x can be A,

B or C) can be used for correct deadtime insertion. A, B and C pertain
to the three generator pairs. In this case, the PWM clock frequency is
equal to the bus frequency.



SPTEF flag set erroneouslyMUCts00708

Description

When the SPI is enabled in master mode, with CPHA bit set, back to back

transmissions are possible.

When a transmission completes and a further byte is available in the SPI
Data Register, the second transmission begins direclty after "minimum
trailing time".

The problem occurs, when after the SPTEF flag has been set a further
byte is written into the SPI Data Register during the "1st pulse" of a
subsequent transmission.

|--> next tx
7th pulse 8th pulse 1st pulse
SCK _______|^^^^^^^|_______|^^^^^^^|_______|^^^^^^^|_______

SPTEF _____________________________________|^^|____|^^^^^^^^
^ ^ ^
| | |
| | SPTEF flag set again
| | (WRONG)
| |
| Write to SPIDR during
| "1st pulse"
|
End of tx SPTEF flag is
set

Then the SPTEF flag is set at the falling SCK edge of the "1st
pulse" and data is transfered from the SPI Data Register to the transmit
shift register. The result is that the transmission is corrupted.


Workaround


After the SPTEF flag has been set, a delay of 1/2 SCK period has to be

added before storing data into the SPI Data Register.




flags in ATDSTAT0 do not clear by writing '1', ETORF erroneously setMUCts00736

Description

For the flags SCF, ETORF and FIFOR in ATDSTAT0 it is specified that

writing a '1' to the respective flag clears it. This does not work.
Writing '1' to the respective flag has no effect.

The ETORF flag is also set by a non-active edge, e.g. falling edge
trigger (ETRILE=0, ETRIGP=0). ETORF is set on both falling edges and
rising edges while conversion is in progress.

Workaround


SCF 

1. Use the alternative flag clearing mechanisms:
a. Write to ATDCTL5 (a new conversion sequence is started)
b. If AFFC=1 a result register is read
ETORF
1. Use the alternative flag clearing mechanisms:
a. Write to ATDCTL2, ATDCTL3 or ATDCTL4 (a conversion sequence
is aborted)
b. Write to ATDCTL5 (a new conversion sequence is started)
2. Avoid external trigger edges during conversion process by using short
pulses
3. Ignore ETROF flag

FIFOR
1. Use the alternative flag clearing mechanism:
a. Start a new conversion sequence
(write to ATDCTL5 or external trigger)



SPI in Mode Fault state, but MISO output buffer not disabled.MUCts00742

Description

When the SPI is in Mode Fault state (MODF flag set), according to the

specification, all SPI output buffers (SS, SCK, MOSI, MISO) should be
disabled. However, the MISO output buffer is not disabled.


Workaround


None.



DBG: CPU erroneously causes BSRs to be recorded in trace bufferMUCts00762

Description

The BSR instruction is recognized as a change of flow instruction and

thus causes the trace buffer to be loaded with its destination address.
Since the BSR instruction always branches to the relative address
specified in the instruction, the information stored in the trace buffer
at a BSR is not useful. Thus code making regular use of the BSR
instruction will result in considerable redundancy in trace buffer
contents.


Workaround


The severity of this bug is directly related to the frequency of BSR 

instruction use. Thus to reduce the impact of this bug, use of the BSR
instruction should be avoided wherever possible.





DBG full mode triggers do not work properly in register space writesMUCts00763

Description

Write accesses to the registers can cause erroneous trigger action when 

using full mode (address AND data) triggers.

A AND B Trigger Mode
Writing to the registers using the A AND B trigger mode may not trigger
the start of FIFO capture even though a valid successful compare should
have occurred. Rarely, the same bug will cause an erroneous successful
trigger even though an address and data match has not occurred.

A AND NOT B Trigger Mode
Writing to the registers using the A AND NOT B trigger mode may cause
an erroneous successful trigger even though an address and data match
has not occurred. Rarely, the same bug will prevent a trigger from
being generated, even though a valid successful compare should have
occurred. Reads of registers and reads and writes to non-register space
are not affected by this erratum.

Workaround


No workaround exists






Forced trigger delay before taking effectMUCts00765

Description

Several cycles are required after enabling a forced trigger before it

takes effect.

This is expected behavior but not clearly noted in the user guide. Thus
it is classed as customer information (as opposed to errata).

Workaround


Take into account that extra cycles are required when using forced

breakpoints.



DBG: LOOP1 mode with break to BDM captures all change of flow instructionsMUCts00779

Description

When using LOOP1 debug mode with break to BDM, the trace buffer captures

all change of flow instructions, as if operating in normal capture mode.
This bug is restricted to LOOP1 mode with break to BDM activated, break
to SWI mode is unaffected by this erratum.


Workaround


When using LOOP1 mode use only break to SWI, not break to BDM. This 

will guarantee correct operation.



MISO not kept after sixteenth SCK edge.MUCts00799

Description

In SPI slave mode with CPHA set, MISO can change erroneously after a

transmission, two to three bus clock cycles after the sixteenth SCK
edge. This can lead to a hold time violation on the SPI master.




Workaround


There are two possible workarounds for this problem: 


1. Decrease the bus clock of the slave SPI to satisfy the "Master
MISO Hold Time".
Tbus(Slave) >= 0.5 * "Master MISO Hold Time"

2. Software workaround:
The slave has to transmit a dummy byte after each data byte,
which must fulfil the following requirements:

- The first bit of the dummy byte to be transmitted (depending on
LSBFE bit) must be equal to the last bit of the data byte
transmitted before. The dummy byte has to be stored into SPIDR
during the transmission of the corresponding data byte.
=> MISO does not change after the data byte.

- The Master has to receive two bytes, the data byte and the dummy
byte.
=> Master receives the data byte correctly and has to skip the
dummy byte.



Write to ATDCTL5 may not clear SCF, CCF and ASCIF flagsMUCts00801

Description

If a write to ATDCTL5 happens at exactly the bus cycle when an ongoing

conversion sequence ends, the SCF, CCF and (if ASCIE=1)
ASCIF flags remain set and are NOT cleared by a write to ATDCTL5.

Workaround


1. Make sure the device is protected from interrupts (temporarily

disable interrupts with the I mask bit).
2. Write to ATDCTL5 twice.



PLL: If osc_clock is 2 to 3 times pll_clock, STOP can cause SCM or resetMUCts00820

Description

This Erratum applies only to systems where PLL is used to divide down

the osc_clock by a ratio between 2 and 3.

If

1) pll_clock (PLLON=1) is running
and
2) 2 < osc_clock/pll_clock < 3
and
3) full stop mode is entered (STOP instruction with PSTP Bit =0)

there is a small possibility that when entering full stop mode the chip
reacts as follows:
1) if self clock mode is disabled (SCME=0) monitor reset is asserted.
The system does NOT enter stop mode.
or
2) if self clode mode and SCM interrupt are enabled (SCME=1 and SCMIE=1)
a self clock mode interrupt is generated. The SCMIF flag is set.
The system does NOT enter stop mode.
or
3) if SCME=1 and SCMIE=0 the system will enter full stop mode.
But after wakeup self clock mode is entered without doing the
specified clock quality check. The SCMIF flag is set.

Workaround


1) Avoid osc_clock/pll_clock ratios between 2 and 3.

or
2) if you really require osc_clock/pll_clock ratio between 2 and 3
do the following before going into stop.
a) deselect PLL (PLLSEL=0)
b) turn off PLL (PLLON=0)
c) enter stop
d) exiting stop: turn on PLL again (PLLON=1)



Flash: ACCERR is not set for a Byte AccessMUCts00856

Description

Starting a command sequence with a MOVB array write instruction (Byte

Write) will not generate an access error. The command is processed
normally programming the array according to the content (word) of the
data register while only the high byte in the FDATA register holds valid
information.

Workaround


Avoid the use of MOVB instruction for array program operations. 




STOP instruction may set flash ACCERR flag.MUCts00992

Description

If the FCLKDIV flash clock divider register has been loaded, and the

flash is not executing a command (flash CCIF command complete flag is
set), the execution of a STOP instruction will erroneously set the
ACCERR access error bit in the FSTAT flash status register.

Workaround


The ACCERR bit in the FSTAT register must be cleared after the execution

of a STOP instruction if the FCLKDIV register has been loaded.



FTS128k1: Flash block protect transitions unlimitedMUCts00994

Description

The flash block protect mechanism allows any FPROT transition in normal

single chip mode. This should not be the case. According to the user
guide FPROT transitions in normal single chip mode should be restricted
to only allow more protection to be added and prohibit transitions to
less protection.

Workaround


None.



Additional write protection exists via mirroringMUCts00995

Description

Flash protection is mirrored once (hence appears twice) in every flash

block. The mirrored protection will occur four pages lower than the
intended protection. For example, if flash page $3F is protected, the
mirrored protection, specified by the FPROT register setting for the
respective block, will occur in flash page $3B. If flash page $3E is
protected, the mirrored protection will occur in page $3A.


Workaround


None.



Array writes immediately after FPROT write do not set PVIOL flag.MUCts01009

Description

A write to the flash protection register that is immediately followed by

a flash array write will not set the PVIOL protection violation flag.

Example:
MOVB #$FB FPROT //protect lower portion of flash page $3E
STD #$55AA #$8080 //write to protected address (PVIOL flag expected,
but does not occur)

Workaround


Perform a legal write of a register immediately after writing to the

FPROT register, before writing to the flash array.

Example:
MOVB #$FB FPROT //protect lower portion of flash page $3E
MOVB #$30 FSTAT //clear error flags (legal write to register)
STD #$55AA #$8080 //write to protected address (PVIOL flag sets to show
protection violation)



CCF flags in ATDSTAT2/1 registers might fail to setMUCts01024

Description

The setting of the CCF15-0 flags in ATDSTAT2/1 registers

is not independent of the clearing.
A clear on CCFx (e.g. Bit AFFC=1 and read of ATDDRx)
which occurs in exactly the same bus cycle as the setting of any other
flag CCFy (x,y = 0,1,..,15; x!=y) masks the setting of CCFy.
CCFy will not set in this special case although the corresponding
conversion has completed and the result (ATDDRy) is valid.

Workaround


None.



Clearing of CCF flags in ATDSTAT2/1 by write of ATDCTL5 might not workMUCts01034

Description

Starting a new conversion by writing to the ATDCTL5 register should

clear all CCF flags in the ATDSTAT2/1 registers.
This does not always work if the write to ATDCTL5 register
occurs near the end of an ongoing conversion.
Although all CCF flags are cleared one CCF flag might be
set again within the 1st ATD clock period of the new conversion.


Workaround


If the unexpected setting of one CCF flag can not be

accepted by the application one of the following
workarounds can be taken:
1) o Abort conversion (e.g. by write to ATDCTL3)
o pause for 2 ATD clock periods
o Start new conversion
2) o ignore first conversion sequence and clear CCF flags



SPIDR can be written without reading SPTEF flag as set MUCts01053

Description

On the first instance after MCU reset, the SPIDR data register can be

written without reading the SPISR status register with the SPTEF
transmit buffer empty flag set. This is contrary to the specification
which states that writes to the SPIDR are ignored if the SPISR is not
previously read as being set.

Workaround


Do not attempt to write the SPIDR data register without first checking

the SPTEF transmit buffer empty flag as set.



DBG: BDM firmware code execution may erroneously cause forced triggerMUCts01079

Description

Breakpoints are temporarily disabled while the MCU is executing BDM

firmware code when operating in active BDM mode. It logically follows
that debug module triggers are disabled in the same manner. While tagged
triggers are disabled, forced triggers are not and therefore may cause
the debug module to trigger erroneously.

In most circumstances this will only be a problem in outside range
trigger mode. In order to see an erroneous trigger in another trigger
mode, a forced trigger must be configured in the BDM firmware address
range ($FF00-$FF80) and an exact address bus match must occur. This
memory area would typically contain interrupts, vectors or program code,
and would therefore be a very unlikely location for the configuration of
a forced trigger address.

Workaround


Outside range trigger mode should not be used when configuring forced

triggers if the trigger range contains the memory area where the BDM
firmware code resides ($FF00-$FF80) and the user intends to operate the
MCU in active BDM mode.





Tagged breakpoints missed if tag attach and interrupt are simultaneous MUCts01430

Description

The problem concerns the DBG-CPU interface in DBG mode whilst tagging if

an interrupt occurs at the moment that a tag is attached to an opcode
being loaded into the instruction queue.

If the DBG module is configured with BDM=DBGBRK=1, BEGIN=0 an event
causing a flag to be set should cause a break to BDM. The symptom is
that the flag gets set but the part does not enter active BDM mode. The
CPU executes the interrupt service routine instead and returns to the
correct position in the program flow but the breakpoint to BDM is
missed.

The problem does not occur if the DBG module is configured for operation
in BKP mode (BKABEN=1). This is because even if the flag bit is set,
BKABEN bit is not cleared. Thus on returning from the interrupt service
routine the tag is re-applied when the PC is fetched after the interrupt
service routine. Thus the part enters BDM after the interrupt service
routine.

In BKP mode with TRGSEL=0 no flags are set when a taghit occurs.
In BKP mode with TRGSEL=1 the flag is also set erroneously, on entering
the interrupt service routine. However the user would typically not
notice the flag being set early unless the service routine were
exceptionally long, because of the large time needed to read out the
DBGSR (flag bits) over the BKGD pin. In the meantime the part would
typically have entered active BDM anyway when the tag is re-applied.

Furthermore this does not occur on the older BKP module which does not
feature flags to indicate tag hits.

Workaround


None.



Possible manipulation of return address when exiting BDM active modeMUCts01965

Description

Upon leaving BDM active mode, the CPU return address is stored

temporarily for a few cycles in the BDM shift register. If a BDM command
transmission is detected during this time, the return address will be
manipulated in the BDM shift register. This situation is likely to occur
when a CPU BGND instruction is executed in user code during debugging
under the following conditions:

(i) The BDM module is not enabled AND
(ii) BDM commands are sent from the host

If this situation occurs, the CPU will execute BDM firmware and will
check the status of the ENBDM bit in the BDMSTS register. If the BDM is
disabled, the ENBDM bit will be clear, and hence the BDM firmware will
be exited and the shift register manipulation described above will occur.

Workaround


Avoid using the BGND instruction when the ENBDM bit in the BDMSTS

register is cleared.



Reduced flash program temperature range and increased programming timeMUCts02143

Description

The flash program temperature range specification has been reduced. The

specification now stipulates that flash program operations must take
place between temperatures of 0C and 125C ambient.

In addition, the flash program times have been increased as follows:

Programming Time
Min. Max.
Single Word Program (Tswpgm) 66.0us 99.2us
Flash Row Program - Consecutive Word (Tbwpgm) 40.4us 57.8us
Flash Row Program - 64 words (Tbrpgm) 2608.7us 3742.7us

Actual programming time will vary between the above bounds depending on
flash clock and bus clock frequencies.

Important Notes:
1) Program time is internally controlled by the flash state machine.
No action needs to be taken by users in connection with this erratum.
2) Both flash erase and flash read temperature specifications and
operation times are unaffected by this erratum.
3) EEPROM is unaffected by this erratum.
~



Workaround


None.



MEBI: Missing ECLK edge on first external access after mode switchingMUCts02415

Description

If the ECLK is used as an external bus control signal (ESTR=1) the first

external access is lost after switching from a single chip mode with
enabled ECLK output to an expanded mode. The ECLK is erroneously held in
the high phase thus the first external bus access does not generate a
rising ECLK edge for the external logic to latch the address. The ECLK
stretches low after the lost access resulting in all following external
accesses to be valid.

Workaround


Enter expanded mode with ECLK output disabled (NECLK=1). Enable the ECLK

after switching the mode before executing the first external access.



S12_mmc: /XCS is erroneously asserted on accesses to internal BDM resourcesMUCts03793

Description

When writing or reading the internal BDM resources (address range $FF00

to $FFFF) via BDM hardware commands, the /XCS Chip Select signal is
erroneously driven low during the BDM access.

The /XCS signal is also driven low for CPU accesses performed to execute
BDM firmware when the CPU is in BDM active mode (BDMACT=1). This
includes the specific read/write cycle of the BDM firmware commands
READ_NEXT and WRITE_NEXT to access the targeted address of BDM firmware.

The R/W signal remains in read state in all these cases. The data
received by the above false external read accesses are discarded by the MCU.


Workaround


None. 




PWM: Emergency shutdown input can be overruledMUCts04076

Description

If the PWM emergency shutdown feature is enabled (PWM5ENA=1) and PWM

channel 5 is disabled (PWME5=0) another lower priority function
available on the related pin can take control over the data direction.
This does not lead to a problem if input mode is maintained. If the
alternative function switches to output mode the shutdown function may
unintentionally be triggered by the output data.



Workaround


When using the PWM emergency shutdown feature the GPIO function on the

pin associated with PWM channel 5 should be selected as an input.

In the case that this pin is selected as an output or where an
alternative function is enabled which could drive it as an output,
enable PWM channel 5 by setting the PWME5 bit. This prevents an
active shutdown level driven on the (output) pin from resulting in an
emergency shutdown of the enabled PWM channels.





TIM_16B4C: Output compare pulse is inaccurateMUCts04162

Description

The pulse width of an output compare (which resets the free running

counter when TCRE = 1) will measure one more bus clock cycle than
expected.



Workaround


The specification has been updated. Please refer to revision 01.02 (06 

May 2010) or later.

In description of bitfield TCRE in register TSCR2,a note has been added:
TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler
counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to
0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it
will last only one bus cycle then reset to 0.










PWM: Wrong output level after shutdown restart in 16bit concatenated channel modeMUCts04223

Description

When the PWM is used in 16-bit (concatenation) channel and the 

emergency
shutdown feature is being used, after de-asserting PWM channel 5
(note:PWMRSTRT should be set) the PWM channels (PP0-PP4) do not show
the
state which is set by PWMLVL bit when the 16-bit counter is non-zero.



Workaround


None. 




PWM: Wrong output value after restart from stop or wait modeMUCts04225

Description

In low power modes (stop/p-stop/wait ?PSWAI=1) and during PWM PP5

de-assert and when PWM counter reaching 0, the PWM channel outputs
(PP0-PP4) cannot keep the state which is set by PWMLVL bit.




Workaround


None. 



© NXP Semiconductors, Inc., 2011. All rights reserved.