|Mask Set Errata||Rev. April 17, 2012|
|MC9S12NE64, Mask 1L19S|
|This errata sheet applies to the following devices:|
|The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1K79X. All standard devices are marked with a mask set number and a date code.|
|Device markings indicate the week of manufacture and the mask set used. The date is coded as four
numerical digits where the first two digits indicate the year and the last two digits indicate the work week.
For instance, the date code "0201" indicates the first week of the year 2002.|
|Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix.|
|MUCtsXXXXX is the tracking number for device errata. It can be used with the mask set and date code to identify a specific erratum.|
|Errata Number||Module affected||Brief Description||Work-|
|MUCts01084||S12_dbg||DBG: BDM firmware code execution may erroneously cause forced trigger||YES|
|MUCts01493||S12_cpu||Tagged breakpoints missed if tag attach and interrupt are simultaneous||NO|
|MUCts01898||ephy||EPHY- Active LED flashes when data received||YES|
|MUCts01899||ephy||EPHY - NOT accepting valid LTP when greater than 100 ns||YES|
|MUCts01900||ephy||EPHY: MDIO write requires 3 MDC clocks to complete transaction||YES|
|MUCts01937||ephy||EPHY - UNH Test #14.3.6.a: Link Fail Effect on the Receive Functions.||YES|
|MUCts01938||ephy||EPHY formed 10Base-T link when less than "lc_max NLPs" received.||YES|
|MUCts01967||S12_bdm||Possible manipulation of return address when exiting BDM active mode||YES|
|MUCts02415||S12_mebi||MEBI: Missing ECLK edge on first external access after mode switching||YES|
|MUCts03403||spi||SPI: Disabling slave SPI together with clearing CPHA while SS low locks transmit shift register for the next transmission||YES|
|MUCts03468||atd_10b8c||ATD: Abort of an A/D conversion sequence with write to ATDxCTL0/1/2/3 may not work||YES|
|MUCts03527||fts64k||FTS64K: Blind Spot in Data Compress Command Algorithm||YES|
|MUCts03685||atd_10b8c||ADC: conversion does not start with 2 consecutive writes to ATDCTL5||YES|
|MUCts03793||S12_mmc||S12_mmc: /XCS is erroneously asserted on accesses to internal BDM resources||NO|
|MUCts04163||tim_16b4c||TIM_16B4C: Output compare pulse is inaccurate||YES|
|MUCts04247||sci||SCI: RXEDGIF occurs more times than expected in IR mode||YES|
|DBG: BDM firmware code execution may erroneously cause forced trigger||MUCts01084|
Breakpoints are temporarily disabled while the MCU is executing BDM
Outside range trigger mode should not be used when configuring forced
|Tagged breakpoints missed if tag attach and interrupt are simultaneous||MUCts01493|
The errata concerns the DBG-CPU interface in DBG mode whilst configured
|EPHY- Active LED flashes when data received||MUCts01898|
When the EPHY is enabled and receiving data the
The LED pin can be controlled via software.
|EPHY - NOT accepting valid LTP when greater than 100 ns||MUCts01899|
If a link partner's LTP is greater than 100 ns, using auto-negotiation,
Disable Auto-negotiation and configure the EPHY or link partner to
|EPHY: MDIO write requires 3 MDC clocks to complete transaction||MUCts01900|
At the end of a write cycle 3 additional MDC clocks must be supplied
Follow a MDIO write with an MDIO read of any MDIO register.
|EPHY - UNH Test #14.3.6.a: Link Fail Effect on the Receive Functions.||MUCts01937|
The EPHY sometimes passes the 1st frame of of valid data to MAC when in
1st frame of of valid data to should be filtered by the software stack.
|EPHY formed 10Base-T link when less than "lc_max NLPs" received.||MUCts01938|
New UNH test Last Modification on April 23, 2003.
1. The Auto-Negotiation feature can be by passed if the line speed is known.
|Possible manipulation of return address when exiting BDM active mode||MUCts01967|
Upon leaving BDM active mode, the CPU return address is stored
Avoid using the BGND instruction when the ENBDM bit in the BDMSTS
|MEBI: Missing ECLK edge on first external access after mode switching||MUCts02415|
If the ECLK is used as an external bus control signal (ESTR=1) the first
Enter expanded mode with ECLK output disabled (NECLK=1). Enable the ECLK
|SPI: Disabling slave SPI together with clearing CPHA while SS low locks transmit shift register for the next transmission||MUCts03403|
With the SPI configured as a slave, clearing the SPE bit (to disable
When disabling the slave SPI, CPHA should not be cleared at the same time.
|ATD: Abort of an A/D conversion sequence with write to ATDxCTL0/1/2/3 may not work||MUCts03468|
Starting a conversion with a write to ATDxCTL5 or on an external
Only write to ATDxCTL4 to abort an ongoing conversion sequence.
|FTS64K: Blind Spot in Data Compress Command Algorithm||MUCts03527|
If the range of Flash addresses to be compressed is 32K or greater, the
Limit range of addresses to be compressed to less than 32K addresses.
|ADC: conversion does not start with 2 consecutive writes to ATDCTL5||MUCts03685|
When the ATD is started with write to ATDCTL5
Only write once to ATDCTL5 when starting a conversion.
|S12_mmc: /XCS is erroneously asserted on accesses to internal BDM resources||MUCts03793|
When writing or reading the internal BDM resources (address range $FF00
|TIM_16B4C: Output compare pulse is inaccurate||MUCts04163|
The pulse width of an output compare (which resets the free running
The specification has been updated. Please refer to revision 1.1 (06
|SCI: RXEDGIF occurs more times than expected in IR mode||MUCts04247|
Configured for Infrared Receive mode, the SCI may incorrectly set the
Case 1 and case 2 may occurs at same time. To avoid those unexpected