NXP® SemiconductorsMSE9S12P128_0M01N
Mask Set ErrataRev. April 16, 2012



MC9S12P128, Mask 0M01N


Introduction
This errata sheet applies to the following devices:

MC9S12P128, MC9S12P64, MC9S12P32



MCU Device Mask Set Identification

The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1K79X. All standard devices are marked with a mask set number and a date code.



MCU Device Date Codes

Device markings indicate the week of manufacture and the mask set used. The date is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the work week. For instance, the date code "0201" indicates the first week of the year 2002.



MCU Device Part Number Prefixes

Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix.



Errata System Tracking Numbers

MUCtsXXXXX is the tracking number for device errata. It can be used with the mask set and date code to identify a specific erratum.



Errata Summary


Errata NumberModule affectedBrief DescriptionWork-
around
MUCts04076 pwm_8b6c PWM: Emergency shutdown input can be overruled YES
MUCts04088 s12_cpmu API interrupt flag sets unexpectedly upon entering STOP mode YES
MUCts04150 s12_cpmu CPMU: High probabilty of PLL Loss of LOCK and UPOSC status change when using Adaptive Oscillator Filter with OSCBW=0 and high VCOCLK frequency YES
MUCts04157 tim_16b8c TIM_16B8C: Output compare pulse is inaccurate YES
MUCts04190 s12_cpmu S12_CPMU: Possible Clock Monitor Reset after writing CPMUOSC register YES
MUCts04223 pwm_8b6c PWM: Wrong output level after shutdown restart in 16bit concatenated channel mode NO
MUCts04225 pwm_8b6c PWM: Wrong output value after restart from stop or wait mode NO
MUCts04243 sci SCI: RXEDGIF occurs more times than expected in IR mode YES



PWM: Emergency shutdown input can be overruledMUCts04076

Description

If the PWM emergency shutdown feature is enabled (PWM5ENA=1) and PWM

channel 5 is disabled (PWME5=0) another lower priority function
available on the related pin can take control over the data direction.
This does not lead to a problem if input mode is maintained. If the
alternative function switches to output mode the shutdown function may
unintentionally be triggered by the output data.



Workaround


When using the PWM emergency shutdown feature the GPIO function on the

pin associated with PWM channel 5 should be selected as an input.

In the case that this pin is selected as an output or where an
alternative function is enabled which could drive it as an output,
enable PWM channel 5 by setting the PWME5 bit. This prevents an
active shutdown level driven on the (output) pin from resulting in an
emergency shutdown of the enabled PWM channels.





API interrupt flag sets unexpectedly upon entering STOP modeMUCts04088

Description

The problem occurs when API is active and using the RC API clock as

source for the periodic interrupt (Register CPMUAPICTL, Address =
0x02F2, Bit APICLK=0) and re-initialising the device from STOP mode. If
re-entering STOP mode prior to one API CLK period since the last time
the API interrupt flag has been set, then the API interrupt flag will
erroneously set immediately upon entering STOP mode.

The ACLK period (1/fACLK) is typically about 100us, but depends on the
trim values set in CPMUAPITR register.


Workaround


Add in a software delay so that STOP mode is re-entered at least 120us

after the last API interrupt.




CPMU: High probabilty of PLL Loss of LOCK and UPOSC status change when using Adaptive Oscillator Filter with OSCBW=0 and high VCOCLK frequencyMUCts04150

Description

A PLL configuration using the Adaptive Oscillator Filter with narrow

bandwidth setting (OSCBW = 0) together with a high VCOCLK frequency
(>=25 MHz) shows a high probability of losing LOCK and UPOSC status.
The probability increases with higher PLL synthesizer values because of
increased PLL jitter.

If the Adaptive Oscillator Filter is enabled (OSCFILT[4:0] > 0) the
detection logic included qualifies the incoming external oscillator
clock based on the VCOCLK for certain OSCFILT[4:0] settings (see S12CPMU
Block Guide). If noise disturbances occur which can not be filtered the
detection logic clears UPOSC status followed by clear of LOCK status.

The detection logic samples the incoming external oscillator clock
(EXTAL) with the VCOCLK frequency. A time window is defined during which
an edge of the OSCCLK is expected. In case of OSCBW =1 the width of this
window is three VCOCLK cycles, if the OSCBW = 0 it is one VCOCLK cycle.


Workaround


The issue can be avoided by using wide bandwidth setting (OSCBW = 1 in

the CPMUOSC register) in such PLL configurations.



TIM_16B8C: Output compare pulse is inaccurateMUCts04157

Description

The pulse width of an output compare (which resets the free running

counter when TCRE = 1) will measure one more bus clock cycle than
expected.



Workaround


The specification has been updated. Please refer to revision V02.07 (04

May 2010) or later.

In description of bitfield TCRE in register TSCR2,a note has been added:
TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler
counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to
0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it
will last only one bus cycle then reset to 0.







S12_CPMU: Possible Clock Monitor Reset after writing CPMUOSC registerMUCts04190

Description

An unexpected clock monitor reset can occur when:

I. The POSTDIV register is set to $00 or $01
II. The external oscillator gets enabled by writing the CPMUOSC register
while the PLL is locked (LOCK=1) based on the internal reference clock
(IRC1M)

Following general CPMU configuration sequence is assumed:
1. Configure PLL according to application needs (access CPMUSYNR,
CPMUREFDIV)
2. Configure CPMUPOSTDIV
3. Enable the external oscillator by writing the CPMUOSC register.
4. Wait for PLL lock

The issue could be annoying during debugging as above CPMU configuration
sequence is working in application (seamlessly executed by CPU) but
breaks due to clock monitor reset if Single Stepping done via debugger.

The issue might occur if the CPMU configuration sequence can be
interrupted (especially between Step 1. and 2. or 2. and 3.)and PLL
reaches locked state (LOCK=1).


Workaround


In case a PLL lock occurs between Step 1.to 3. (see assumed general CPMU

setup sequence in the errata description):
a) Use a POSTDIV value higher than $01 at Step 2.
b) After PLL has locked (Step 4.) any value can be written to the
POSTDIV register without causing a reset.
Above workaround is recommended to avoid issues during debugging with
instruction Single Step or if the CPMU setup sequence can be interrupted.



PWM: Wrong output level after shutdown restart in 16bit concatenated channel modeMUCts04223

Description

When the PWM is used in 16-bit (concatenation) channel and the 

emergency
shutdown feature is being used, after de-asserting PWM channel 5
(note:PWMRSTRT should be set) the PWM channels (PP0-PP4) do not show
the
state which is set by PWMLVL bit when the 16-bit counter is non-zero.



Workaround


None. 




PWM: Wrong output value after restart from stop or wait modeMUCts04225

Description

In low power modes (stop/p-stop/wait ?PSWAI=1) and during PWM PP5

de-assert and when PWM counter reaching 0, the PWM channel outputs
(PP0-PP4) cannot keep the state which is set by PWMLVL bit.




Workaround


None. 




SCI: RXEDGIF occurs more times than expected in IR modeMUCts04243

Description

Configured for Infrared Receive mode, the SCI may incorrectly set the 

RXEDGIF bit if there are consecutive '00' data bits. There are two
cases:

Case 1: due to re-sync of the RXD input, the received edge may be
delayed by one bus cycle. If an edge (bit = '0') is detected near
an SCI clock edge, the next edge (bit = '0') may be detected one
SCI clock later than expected due to re-sync logic.

Case 2: if external baud is slower than SCI receiver, the next edge
may be detected later than expected.

This glitch can be detected by the RXEDGIF circuit, but it does not
impact the final data result because the SCI receive and data recovery
logic takes samples at RT8, RT9, and RT10.




Workaround


Case 1 and case 2 may occurs at same time. To avoid those unexpected 

RXEDGIF at IR mode, the external baud should be kept a little bit
faster than receiver baud by:
P > (1/16)/(SBR)
or
(P)(SBR)(16)> 1

Where SBR is baud of receiver, P is external baud faster ratio.
For example:
1.- When SBR = 16, P = 0.4%, this means the external baud should be at
least 0.4% faster than receiver.
2.- When SBR = 4, P = 1.6%, this means the external baud should be at
least 1.6% faster than receiver.

Case 1 will cover case 2, i.e. case 1 is the worst case. If case1 is
solved, case 2 is also solved.


© NXP Semiconductors, Inc., 2012. All rights reserved.