NXP® SemiconductorsMSE9S12T64_0L24K
Mask Set ErrataRev. February 13, 2011



MC9S12T64, Mask 0L24K


Introduction
This errata sheet applies to the following devices:

MC9S12T64



MCU Device Mask Set Identification

The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1K79X. All standard devices are marked with a mask set number and a date code.



MCU Device Date Codes

Device markings indicate the week of manufacture and the mask set used. The date is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the work week. For instance, the date code "0201" indicates the first week of the year 2002.



MCU Device Part Number Prefixes

Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix.



Errata System Tracking Numbers

MUCtsXXXXX is the tracking number for device errata. It can be used with the mask set and date code to identify a specific erratum.



Errata Summary


Errata NumberModule affectedBrief DescriptionWork-
around
MUCts00468 S12_bkp Breakpoint Module: potential extraneous data match NO
MUCts00589 ect_16b8c ECT: can't use channel 0-3 for OC if queuing is enabled YES
MUCts00703 spi SPIDR is writeable though the SPTEF flag is cleared. YES
MUCts00707 spi SPTEF flag set erroneously YES
MUCts00729 mcu_9t64 S12_mebi: Missing external ECLK during reset vector fetch NO
MUCts00731 fts64k2 Program & Erase of flash blocked in Normal Single Chip Mode when secure YES
MUCts00739 atd_10b8c flags in ATDSTAT0 do not clear by writing '1', ETORF erroneously set YES
MUCts00743 spi SPI in Mode Fault state, but MISO output buffer not disabled. NO
MUCts00762 S12_cpu DBG: CPU erroneously causes BSRs to be recorded in trace buffer YES
MUCts00790 atd_10b8c Write to ATDCTL5 may not clear SCF, CCF and ASCIF flags YES
MUCts00798 spi MISO not kept after sixteenth SCK edge. YES
MUCts00811 ect_16b8c ECT: Input pulse shorter than delay counter period recognised as a valid YES
MUCts00817 crg PLL: If osc_clock is 2 to 3 times pll_clock, STOP can cause SCM or reset YES
MUCts00826 fts64k2 STOP instruction may set flash ACCERR flag. YES
MUCts00859 fts64k2 Flash: ACCERR is not set for a Byte Access YES
MUCts01030 atd_10b8c CCF flags in ATDSTAT1 register might fail to set NO
MUCts01041 atd_10b8c ATD: Clearing of CCF flags in ATDSTAT1 by write of ATDCTL5 might not work YES
MUCts01532 ect_16b8c ECT_16B8C: Output compare pulse is inaccurate YES
MUCts02415 S12_mebi MEBI: Missing ECLK edge on first external access after mode switching YES
MUCts04073 pwm_8b8c PWM: Emergency shutdown input can be overruled YES
MUCts04109 ect_16b8c ECT: Channel 0 - 3 Input Capture interrupts inhibited when BUFEN=1, LATQ=0 and NOVWx=1 YES
MUCts04199 pwm_8b8c PWM: Wrong output value after restart from stop or wait mode YES
MUCts04203 pwm_8b8c PWM: Wrong output level after shutdown restart in 16bit concatenated channel mode YES



Breakpoint Module: potential extraneous data matchMUCts00468

Description

When using the breakpoint in full mode, there is a chance of a false

match. Internally there
is a separate read data bus and write data bus. When in full mode
with the read/write match function is disabled, both buses are always
compared to the contents of data match register. The circuit should only
match the active bus on any particular bus cycle. The false match can
occur if the address matches on a read cycle and matching data is on the
write data bus or the address matches on a write cycle and the matching
data is on the read data bus.




ECT: can't use channel 0-3 for OC if queuing is enabledMUCts00589

Description

When using one or more of channels 0-3 as output compare, while using

the remaining channels 0-3 in the enhanced input capture mode
(TFMOD=1,BUFEN = 1, LATQ = 0 in ICSYS register), the output compare(s)
will take place, but the output compare flag(s) will not be set.



Workaround


If a customer wants to use less than the maximum of 4 Input capture

channels in this mode the other channels left in 0-3 can not be
used as output compares since the OCIF flag never gets set.






SPIDR is writeable though the SPTEF flag is cleared.MUCts00703

Description

Data can be placed into the SPI Data Register (SPIDR) even though the

SPTEF flag is cleared. The SPTEF flag indicates whether the transmit
buffer is empty (SPTEF=1) or full (SPTEF=0). Data can be placed into the
SPI Data Register by reading SPISR with SPTEF=1 followed by a write to
the SPI Data Register. If SPTEF=0, a write to the SPI Data Register
should be ignored, according to the SPI specification. This is not true
for the current implementation, where data can be placed into the SPI
Data Register though SPTEF=0.




Workaround


Do not write to the SPI Data Register until you have

read SPISR with SPTEF=1.



SPTEF flag set erroneouslyMUCts00707

Description

When the SPI is enabled in master mode, with CPHA bit set, back to back

transmissions are possible.

When a transmission completes and a further byte is available in the SPI
Data Register, the second transmission begins direclty after "minimum
trailing time".

The problem occurs, when after the SPTEF flag has been set a further
byte is written into the SPI Data Register during the "1st pulse" of a
subsequent transmission.

|--> next tx
7th pulse 8th pulse 1st pulse
SCK _______|^^^^^^^|_______|^^^^^^^|_______|^^^^^^^|_______

SPTEF _____________________________________|^^|____|^^^^^^^^
^ ^ ^
| | |
| | SPTEF flag set again
| | (WRONG)
| |
| Write to SPIDR during
| "1st pulse"
|
End of tx SPTEF flag is
set

Then the SPTEF flag is set at the falling SCK edge of the "1st
pulse" and data is transfered from the SPI Data Register to the transmit
shift register. The result is that the transmission is corrupted.


Workaround


After the SPTEF flag has been set, a delay of 1/2 SCK period has to be

added before storing data into the SPI Data Register.




S12_mebi: Missing external ECLK during reset vector fetchMUCts00729

Description

The reset conditions of the ECLK control logic in the MEBI 

inhibit the generation of 1 ECLK pulse during the reset
vector fetch. This can prevent the external logic from
latching the reset vector address.

Workaround


None.



Program & Erase of flash blocked in Normal Single Chip Mode when secureMUCts00731

Description

In normal single chip mode, when security is enabled, it is not 

possible to launch the Program ($20), Sector-Erase ($40) and Erase-
Verify ($05) commands in the flash. The Mass-Erase
($41) command can be launched.

Workaround


To enable the Program ($20), Sector-Erase ($40) 

and Erase-Verify ($05) commands in the flash, security must be
disabled via the backdoor key sequence. See Flash User Guide for
details of the backdoor key operation.



flags in ATDSTAT0 do not clear by writing '1', ETORF erroneously setMUCts00739

Description

For the flags SCF, ETORF and FIFOR in ATDSTAT0 it is specified that

writing a '1' to the respective flag clears it. This does not work.
Writing '1' to the respective flag has no effect.

The ETORF flag is also set by a non-active edge, e.g. falling edge
trigger (ETRILE=0, ETRIGP=0). ETORF is set on both falling edges and
rising edges while conversion is in progress.

Workaround


SCF 

1. Use the alternative flag clearing mechanisms:
a. Write to ATDCTL5 (a new conversion sequence is started)
b. If AFFC=1 a result register is read
ETORF
1. Use the alternative flag clearing mechanisms:
a. Write to ATDCTL2, ATDCTL3 or ATDCTL4 (a conversion sequence
is aborted)
b. Write to ATDCTL5 (a new conversion sequence is started)
2. Avoid external trigger edges during conversion process by using short
pulses
3. Ignore ETROF flag

FIFOR
1. Use the alternative flag clearing mechanism:
a. Start a new conversion sequence
(write to ATDCTL5 or external trigger)





SPI in Mode Fault state, but MISO output buffer not disabled.MUCts00743

Description

When the SPI is in Mode Fault state (MODF flag set), according to the

specification, all SPI output buffers (SS, SCK, MOSI, MISO) should be
disabled. However, the MISO output buffer is not disabled.

Workaround


None.



DBG: CPU erroneously causes BSRs to be recorded in trace bufferMUCts00762

Description

The BSR instruction is recognized as a change of flow instruction and

thus causes the trace buffer to be loaded with its destination address.
Since the BSR instruction always branches to the relative address
specified in the instruction, the information stored in the trace buffer
at a BSR is not useful. Thus code making regular use of the BSR
instruction will result in considerable redundancy in trace buffer
contents.


Workaround


The severity of this bug is directly related to the frequency of BSR 

instruction use. Thus to reduce the impact of this bug, use of the BSR
instruction should be avoided wherever possible.





Write to ATDCTL5 may not clear SCF, CCF and ASCIF flagsMUCts00790

Description

If a write to ATDCTL5 happens at exactly the bus cycle when an ongoing

conversion sequence ends, the SCF, CCF and (if ASCIE=1)
ASCIF flags remain set and are NOT cleared by a write to ATDCTL5.

Workaround


1. Make sure the device is protected from interrupts (temporarily

disable interrupts with the I mask bit).
2. Write to ATDCTL5 twice.



MISO not kept after sixteenth SCK edge.MUCts00798

Description

In SPI slave mode with CPHA set, MISO can change erroneously after a

transmission, two to three bus clock cycles after the sixteenth SCK
edge. This can lead to a hold time violation on the SPI master.



Workaround


There are two possible workarounds for this problem: 


1. Decrease the bus clock of the slave SPI to satisfy the "Master
MISO Hold Time".
Tbus(Slave) >= 0.5 * "Master MISO Hold Time"

2. Software workaround:
The slave has to transmit a dummy byte after each data byte,
which must fulfil the following requirements:

- The first bit of the dummy byte to be transmitted (depending on
LSBFE bit) must be equal to the last bit of the data byte
transmitted before. The dummy byte has to be stored into SPIDR
during the transmission of the corresponding data byte.
=> MISO does not change after the data byte.

- The Master has to receive two bytes, the data byte and the dummy
byte.
=> Master receives the data byte correctly and has to skip the
dummy byte.



ECT: Input pulse shorter than delay counter period recognised as a validMUCts00811

Description

According to the observation, input pulse (high/low) whose pulse width

is shorter than delay counter window is mistakenly recognized as as
valid pulse. Hence the ic flags will be set and may result in an IRQ if
IRQ is enabled.



Workaround


A software workaround is available.


User software should check the logic level of the input capture pin
within the interrupt service routine and compare this with the logic
level when the input is not asserted. This can be performed using the
appropriate registers in the port integration module.

If the pin reads the logic level of the inactive state, the pulse is
shorter than the time defined in the delay counter control register
plus the interrupt latency. In this case, the pulse triggering the
input capture is not valid (too short), hence the interrupt can be
acknowledged and exited without further action taking place. If the pin
reads the logic level of the active state, the input pulse is valid and
the interrupt should be acknowledged and the correct input capture
service routine executed.

The effectiveness of this workaround must be evaluated by identifying
the worst case latency involved in the call of the ISR. To maximise the
effectiveness of pulse rejection, users must consider checking the
value in the capture register against the free-running timer on every
new capture.



PLL: If osc_clock is 2 to 3 times pll_clock, STOP can cause SCM or resetMUCts00817

Description

This Erratum applies only to systems where PLL is used to divide down

the osc_clock by a ratio between 2 and 3.

If

1) pll_clock (PLLON=1) is running
and
2) 2 < osc_clock/pll_clock < 3
and
3) full stop mode is entered (STOP instruction with PSTP Bit =0)

there is a small possibility that when entering full stop mode the chip
reacts as follows:
1) if self clock mode is disabled (SCME=0) monitor reset is asserted.
The system does NOT enter stop mode.
or
2) if self clode mode and SCM interrupt are enabled (SCME=1 and SCMIE=1)
a self clock mode interrupt is generated. The SCMIF flag is set.
The system does NOT enter stop mode.
or
3) if SCME=1 and SCMIE=0 the system will enter full stop mode.
But after wakeup self clock mode is entered without doing the
specified clock quality check. The SCMIF flag is set.

Workaround


1) Avoid osc_clock/pll_clock ratios between 2 and 3.

or
2) if you really require osc_clock/pll_clock ratio between 2 and 3
do the following before going into stop.
a) deselect PLL (PLLSEL=0)
b) turn off PLL (PLLON=0)
c) enter stop
d) exiting stop: turn on PLL again (PLLON=1)



STOP instruction may set flash ACCERR flag.MUCts00826

Description

If the FCLKDIV flash clock divider register has been loaded, and the

flash is not executing a command (flash CCIF command complete flag is
set), the execution of a STOP instruction will erroneously set the
ACCERR access error bit in the FSTAT flash status register.

Workaround


The ACCERR bit in the FSTAT register must be cleared after the execution

of a STOP instruction if the FCLKDIV register has been loaded.



Flash: ACCERR is not set for a Byte AccessMUCts00859

Description

Starting a command sequence with a MOVB array write instruction (Byte

Write) will not generate an access error. The command is processed
normally programming the array according to the content (word) of the
data register while only the high byte in the FDATA register holds valid
information.

Workaround


Avoid the use of MOVB instruction for array program operations.  




CCF flags in ATDSTAT1 register might fail to setMUCts01030

Description

The setting of the CCF7-0 flags in ATDSTAT1 register

is not independent of the clearing.
A clear on CCFx (e.g. Bit AFFC=1 and read of ATDDRx)
which occurs in exactly the same bus cycle as the setting of any other
flag CCFy (x,y = 0,1,..,7; x!=y) masks the setting of CCFy.
CCFy will not set in this special case although the corresponding
conversion has completed and the result (ATDDRy) is valid.

Workaround


None.



ATD: Clearing of CCF flags in ATDSTAT1 by write of ATDCTL5 might not workMUCts01041

Description

Starting a new conversion by writing to the ATDCTL5 register should

clear all CCF flags in the ATDSTAT1 register.
This does not always work if the write to ATDCTL5 register
occurs near the end of an ongoing conversion.
Although all CCF flags are cleared one CCF flag might be
set again within the 1st ATD clock period of the new conversion.

Workaround


If the unexpected setting of one CCF flag can not be

accepted by the application one of the following
workarounds can be taken:
1) Abort conversion (e.g. by write to ATDCTL3)
Pause for 2 ATD clock periods
Start new conversion
2) Ignore first conversion sequence and clear CCF flags




ECT_16B8C: Output compare pulse is inaccurateMUCts01532

Description

The pulse width of an output compare (which resets the free running

counter when TCRE = 1) will measure one more bus clock cycle than
expected.



Workaround


The specification has been updated. Please refer to revision 01.06 (28

Apr 2010) or later.

In description of bitfield TCRE in register TSCR2,a note has been added:
TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler
counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to
0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it
will last only one bus cycle then reset to 0.







MEBI: Missing ECLK edge on first external access after mode switchingMUCts02415

Description

If the ECLK is used as an external bus control signal (ESTR=1) the first

external access is lost after switching from a single chip mode with
enabled ECLK output to an expanded mode. The ECLK is erroneously held in
the high phase thus the first external bus access does not generate a
rising ECLK edge for the external logic to latch the address. The ECLK
stretches low after the lost access resulting in all following external
accesses to be valid.

Workaround


Enter expanded mode with ECLK output disabled (NECLK=1). Enable the ECLK

after switching the mode before executing the first external access.



PWM: Emergency shutdown input can be overruledMUCts04073

Description

If the PWM emergency shutdown feature is enabled (PWM7ENA=1) and PWM

channel 7 is disabled (PWME7=0) another lower priority function
available on the related pin can take control over the data direction.
This does not lead to a problem if input mode is maintained. If the
alternative function switches to output mode the shutdown function may
unintentionally be triggered by the output data.


Workaround


When using the PWM emergency shutdown feature the GPIO function on the

pin associated with PWM channel 7 should be selected as an input.

In the case that this pin is selected as an output or where an
alternative function is enabled which could drive it as an output,
enable PWM channel 7 by setting the PWME7 bit. This prevents an
active shutdown level driven on the (output) pin from resulting in an
emergency shutdown of the enabled PWM channels.




ECT: Channel 0 - 3 Input Capture interrupts inhibited when BUFEN=1, LATQ=0 and NOVWx=1MUCts04109

Description

Channel 0 – 3 Input Capture interrupts are inhibited when BUFEN=1, 

LATQ=0 and NOVWx=1 if an Input Capture edge occurs during or between a
read of TCx and TCxH or between a read of TCx/TCxH and clearing of CxF.


Details:

When any of the buffered input capture channels 0 - 3 are configured
for buffered/queue mode (BUFEN=1, LATQ=0) each of the channel’s input
capture holding registers and each channel’s associated pulse
accumulator and its holding register are enabled. When the input
capture channel is enabled by writing to a channel’s EDGxB and EDGxA
bits, both the input capture and input capture holding register are
considered empty. The first valid edge received after enabling a
channel will latch the ECT’s free running counter into the input
capture register (TCx) without setting the channel’s associated CxF
interrupt flag. The second valid edge received will transfer the value
of the input capture register, TCx, into the channel’s TCxH holding
register, latch the current value of the free running timer into the
input capture register and set the channel’s associated CxF interrupt
flag. In this condition, both the TCx and TCxH registers are
considered ‘full’.

If a corresponding channel’s NOVWx bit in the ICOVW register is set,
the capture register or its holding register cannot be written by a
valid edge at the input pin unless they are first emptied by reading
the TCx and TCxH registers. The act of reading the TCx and TCxH
registers and clearing the channel’s associated CxF interrupt flag
involves three separate operations. Two 16-bit read operations and an 8-
bit write operation.

If a channel’s associated CxF interrupt flag is cleared before reading
the TCx and TCxH registers and if a valid input edge occurs during or
between the reading of the capture and holding register, a channel’s
associated CxF interrupt flag will no longer be set as the result of
valid input edges. For example:

Clear CxF
|
|
V
Read TCx <----+
| |
|<--------+--- Valid Input Edge Occurs
V |
Read TCxH <---+

If the TCx and TCxH registers are read before a channel’s associated
CxF interrupt flag is cleared and if a valid input edge occurs between
the reading of TCx/TCxH and the clearing of a channel’s associated CxF
interrupt flag, a channel’s associated CxF interrupt flag will no
longer be set as the result of valid input edges. For example:

Clear CxF
|
|
V
Read TCx
|
|<------------ Valid Input Edge Occurs
V
Read TCxH


Systems that service the interrupt request and read the TCx and TCxH
registers before the next valid edge occurs at a channel’s associated
input pin will avoid the conditions under which the errata will occur.

Workaround


A simple workaround exists for this errata:


1. Clear the input capture channel’s associated CxF bit.
2. Disable the input capture function by writing 0:0 to a channel’s
EDGxB and EDGxA bits.
3. Read TCx
4. Read TCxH
5. Re-enable the input capture function by writing to a channel’s EDGxB
and EDGxA bits.


Code Example:

unsigned char ICSave;
unsigned int TC0Val;
unsigned int TC0HVal;

ICSave = TCTL4 & 0x03; /* save state of EDG0B and EDG0A */
TFLG1 = 0x01; /* clear ECT Channel 0 flag */
TCTL4 &= 0xfc; /* disable Channel 0 input capture function */
TC0Val = TC0; /* Read value of TC0 */
TC0HVal = TC0H; /* Read value of TC0H */
TCTL4 |= ICSave; /* Restore Channel 0 input capture function */



PWM: Wrong output value after restart from stop or wait modeMUCts04199

Description

In low power modes (stop/p-stop/wait – PSWAI=1) and during PWM PP7

de-assert and when PWM counter reaching 0, the PWM channel outputs
(PP0-PP6) cannot keep the state which is set by PWMLVL bit.



Workaround


Before entering low power modes, user can disable the related PWM 

channels and set the corresponding general-purpose IO to be the PWM
LVL value. After a intend period, restart the PWM channels.




PWM: Wrong output level after shutdown restart in 16bit concatenated channel modeMUCts04203

Description

When the PWM is used in 16-bit (concatenation) channel and the emergency

shutdown feature is being used, after de-asserting PWM channel 7
(note:PWMRSTRT should be set) the PWM channels (PP0-PP6) do not show the
state which is set by PWMLVL bit when the 16-bit counter is non-zero.


Workaround


If emergency shutdown mode is required:


In 16-bit concatenation mode, user can disable the related PWM
channels and set the corresponding general-purpose IO to be the PWM
LVL value. After a intend period, restart the PWM channels.




© NXP Semiconductors, Inc., 2011. All rights reserved.