NXP® SemiconductorsMSE9S12XHY256_0M23Y
Mask Set ErrataRev. April 16, 2012

MC9S12XHY256, Mask 0M23Y

This errata sheet applies to the following devices:


MCU Device Mask Set Identification

The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1K79X. All standard devices are marked with a mask set number and a date code.

MCU Device Date Codes

Device markings indicate the week of manufacture and the mask set used. The date is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the work week. For instance, the date code "0201" indicates the first week of the year 2002.

MCU Device Part Number Prefixes

Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix.

Errata System Tracking Numbers

MUCtsXXXXX is the tracking number for device errata. It can be used with the mask set and date code to identify a specific erratum.

Errata Summary

Errata NumberModule affectedBrief DescriptionWork-
MUCts04147 s12xhy_pim Cannot read WOMM Register YES
MUCts04158 tim_16b8c TIM_16B8C: Output compare pulse is inaccurate YES
MUCts04180 s12xe_crg s12xe_crg: Possible PLL premature LOCK followed by an UN-LOCK in conjunction with STOP instruction YES
MUCts04202 pwm_8b8c PWM: Wrong output value after restart from stop or wait mode YES
MUCts04205 pwm_8b8c PWM: Wrong output level after shutdown restart in 16bit concatenated channel mode YES
MUCts04243 sci SCI: RXEDGIF occurs more times than expected in IR mode YES

Cannot read WOMM RegisterMUCts04147


Port M wired-Or mode register, WOMM, should be read at address 0x257

instead of address 0x256. Any read to address 0x256 will return an error
of 0x00.


If WOMM is required to be read it should be done at address 0x257.

TIM_16B8C: Output compare pulse is inaccurateMUCts04158


The pulse width of an output compare (which resets the free running

counter when TCRE = 1) will measure one more bus clock cycle than


The specification has been updated. Please refer to revision V02.07 (04

May 2010) or later.

In description of bitfield TCRE in register TSCR2,a note has been added:
TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler
counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to
0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it
will last only one bus cycle then reset to 0.

s12xe_crg: Possible PLL premature LOCK followed by an UN-LOCK in conjunction with STOP instructionMUCts04180


If the PLL is manually turned off (PLLCTL_ PLLON = 0) before a STOP

instruction and the PLL is manually turned on (PLLCTL_PLLON=1) after
execution of the STOP instruction, the PLL might have a premature lock
condition in the case of a STOP instruction being executed with a
pending interrupt and the corresponding interrupt is enabled. In this
case the STOP is executed similar to NOP instruction.

Due to the manual control of the PLL, the VCO clock is switched on and
off. The PLL lock detection logic uses the VCO clock as well as the
reference clock (based on the external oscillator). The external
oscillator is not stopped because the STOP instruction is executed like
a NOP instruction, which keeps the reference clock running.

This causes the logic in the PLL lock detection being uncorrelated and
thus resulting in a possible premature LOCK condition (CRGFLG_LOCK=1).

After the next lock detection cycle the lock is lost (CRGFLG_LOCK=0)
because the VCO clock frequency has not reached the correct value. Some
lock detection cycles later the correct lock condition is reached (VCO
clock frequency reached the correct value) and the LOCK bit is set again
(CRGFLG_LOCK=1). Each transition of the LOCK bit is indicated by the
lock interrupt flag (CRGFLG_LOCKIF).


Do not modify the PLLON bit around the STOP instruction. 

The clock control and power down/up sequencing is automatically done by
the device CRG module. Only the system clock source selection after exit
from STOP must be controlled by software (CLKSEL_PLLSEL bit) as
described in the Reference Manual.

Depending on the application if the fast wake-up feature is used the
software also needs to control the bit FSTWKP and bit SCME (both located
in the PLLCTL register) as described in the device Reference Manual when
STOP Mode is entered or exited.

PWM: Wrong output value after restart from stop or wait modeMUCts04202


In low power modes (stop/p-stop/wait – PSWAI=1) and during PWM PP7

de-assert and when PWM counter reaching 0, the PWM channel outputs
(PP0-PP6) cannot keep the state which is set by PWMLVL bit.


User software can be used to force the port PTP to the same level as


PWM: Wrong output level after shutdown restart in 16bit concatenated channel modeMUCts04205


When the PWM is used in 16-bit (concatenation) channel and the emergency

shutdown feature is being used, after de-asserting PWM channel 7
(note:PWMRSTRT should be set) the PWM channels do
not show the state which is set by PWMLVL bit when the 16-bit counter is


If emergency shutdown mode is required: 

1) Enable PWM channels in 8-bit unconcatenate mode.


2) If 16-bit concatenate mode is required user software can force the
appropriate PWM port to the same level as PWMLVL.

SCI: RXEDGIF occurs more times than expected in IR modeMUCts04243


Configured for Infrared Receive mode, the SCI may incorrectly set the 

RXEDGIF bit if there are consecutive '00' data bits. There are two

Case 1: due to re-sync of the RXD input, the received edge may be
delayed by one bus cycle. If an edge (bit = '0') is detected near
an SCI clock edge, the next edge (bit = '0') may be detected one
SCI clock later than expected due to re-sync logic.

Case 2: if external baud is slower than SCI receiver, the next edge
may be detected later than expected.

This glitch can be detected by the RXEDGIF circuit, but it does not
impact the final data result because the SCI receive and data recovery
logic takes samples at RT8, RT9, and RT10.


Case 1 and case 2 may occurs at same time. To avoid those unexpected 

RXEDGIF at IR mode, the external baud should be kept a little bit
faster than receiver baud by:
P > (1/16)/(SBR)
(P)(SBR)(16)> 1

Where SBR is baud of receiver, P is external baud faster ratio.
For example:
1.- When SBR = 16, P = 0.4%, this means the external baud should be at
least 0.4% faster than receiver.
2.- When SBR = 4, P = 1.6%, this means the external baud should be at
least 1.6% faster than receiver.

Case 1 will cover case 2, i.e. case 1 is the worst case. If case1 is
solved, case 2 is also solved.

© NXP Semiconductors, Inc., 2012. All rights reserved.