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ISF
1.1
Intelligent Sensing Framework
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00001 /*! 00002 ***************************************************************** 00003 * File: isf_i2cconf_types.h 00004 * 00005 * Copyright (c) 2012, Freescale Semiconductor, Inc. 00006 * 00007 ******************************************************************/ 00008 /*! 00009 * @file isf_i2cconf_types.h 00010 * @brief \b isf_i2cconf_types.h describes the definitions and types for the Intelligent Sensing Framework (ISF) I2C configuration. 00011 */ 00012 00013 #ifndef I2CCONF_TYPES_H_ 00014 #define I2CCONF_TYPES_H_ 00015 #include <fxlc95000.h> 00016 #include <isf.h> 00017 #include <isf_i2c.h> 00018 #include <lwevent.h> 00019 /*! @brief This structure defines the I2C register layout. 00020 * The layout of the register is the same for similar types of masters such as the I2C master in FXLC95000CL. 00021 * 00022 */ 00023 // Byte alignment used for structures. 00024 #pragma pack(push) 00025 #pragma pack(1) 00026 00027 typedef struct i2c_RegLayout_struct 00028 { 00029 volatile IICA1STR addressReg; /*!< The address register.*/ 00030 volatile IICFSTR frequencyReg; /*!< The frequency divider register.*/ 00031 volatile IICC1STR ctrl1Reg; /*!< The control one register. */ 00032 volatile IICSSTR statusReg; /*!< The status register.*/ 00033 volatile IICDSTR dataReg; /*!< The data register.*/ 00034 volatile IICC2STR ctrl2Reg; /*!< The control two register.*/ 00035 volatile IICFLTSTR filterReg; /*!< The filter register.*/ 00036 00037 }i2c_RegLayout_t; 00038 00039 /*! @brief This structure defines the I2C bus register information. 00040 * 00041 */ 00042 typedef struct i2c_BusRegInfo_struct{ 00043 volatile i2c_RegLayout_t* regBase; /*!< The base address of the registers.*/ 00044 volatile uint8* pinMuxReg; /*!< The pin muxing register.*/ 00045 volatile uint16* gpioReg; /*!< The GPIO enable/disable register.*/ 00046 volatile uint8* stopFCReg; /*!< The peripheral clock register for STOPfc mode.*/ 00047 volatile uint8* runReg; /*!< The peripheral clock register for RUN mode.*/ 00048 int8* pBusName; /*!< The bus name.*/ 00049 uint8 pinConfig; /*!< The pin configuration value for selecting different pins for SCL1 and SDA1.*/ 00050 uint8 pinMaskVal; /*!< The pin mask value.*/ 00051 uint16 gpioConfig; /*!< The GPIO configuration value for SCL1 and SDA1.*/ 00052 uint16 gpioMaskVal; /*!< The GPIO mask value.*/ 00053 uint8 vectorNumber; /*!< The vector number of the I2C master.*/ 00054 }i2c_BusRegInfo_t; 00055 00056 /*! @brief This structure defines the I2C state. 00057 * 00058 */ 00059 typedef struct i2c_State_struct{ 00060 uint8 busState; /*!< The bus state.*/ 00061 uint8 cDriverState; /*!< The current driver state.*/ 00062 uint8 writeRead; /*!< The flag for read and write in a single transaction.*/ 00063 uint8 isRestart; /*!< The flag for restart.*/ 00064 }i2c_State_t; 00065 00066 /*! @brief This structure defines the I2C bus information. 00067 * 00068 */ 00069 typedef struct i2c_BusInfo_struct{ 00070 const i2c_BusRegInfo_t* pbusRegInfo; /*!< The current bus register information.*/ 00071 i2c_BusConfig_t busConfig; /*!< The current bus configuration.*/ 00072 volatile i2c_State_t state; /*!< The current I2C state.*/ 00073 i2c_Command_t* pcCommand; /*!< The current command being processed.*/ 00074 i2c_MessageBuffer_t* pcReceiveBuff; /*!< The receive buffer being used.*/ 00075 uint16 cBufferIndex; /*!< The current buffer index.*/ 00076 LWEVENT_STRUCT i2cEventHandler; /*!< The handler defined for internal I2C events.*/ 00077 i2c_AddrHint_t cAddr; /*!< The current slave address being communicated.*/ 00078 volatile uint8 is10bitAddressing; /*!< The flag for 10-bit addressing.*/ 00079 uint8 isrBusId; /*!< The bus number of the bus causing the triggered ISR.*/ 00080 }i2c_BusInfo_t; 00081 00082 #pragma pack(pop) 00083 #endif /* I2CCONF_TYPES_H_ */ 00084 00085