ISF  1.1
Intelligent Sensing Framework
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Defines
Include/psp/fxlc95000.h
Go to the documentation of this file.
00001 /* Based on CPU DB FXLC95000, version 3.00.000 (RegistersPrg V2.33) */
00002 /*
00003 ** ###################################################################
00004 **     Filename  : fxlc95000.h
00005 **     Processor : FXLC95000
00006 **     FileFormat: V2.33
00007 **     DataSheet : Galla 3-Axis Accelerometer Product Specification, REV 0.5, May 4, 2011
00008 **     Compiler  : CodeWarrior compiler
00009 **     Date/Time : 20.4.2012, 9:51
00010 **     Abstract  :
00011 **         This header implements the mapping of I/O devices.
00012 **
00013 **     Copyright : 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
00014 **     
00015 **     http      : www.freescale.com
00016 **     mail      : support@freescale.com
00017 **
00018 **     CPU Registers Revisions:
00019 **               - none
00020 **
00021 **     File-Format-Revisions:
00022 **      - 15.09.2010, V2.33 :
00023 **               - Empty union is not generated for data overlapping registers, cause there is no bit access
00024 **
00025 **     Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific
00026 **     derivative device. To avoid extra current drain from floating input pins, the user’s reset
00027 **     initialization routine in the application program must either enable on-chip pull-up devices
00028 **     or change the direction of unconnected pins to outputs so the pins do not float.
00029 ** ###################################################################
00030 */
00031 
00032 #ifndef _FXLC95000_H
00033 #define _FXLC95000_H
00034 
00035 /*lint -save  -e950 -esym(960,18.4) -e46 -esym(961,19.7) Disable MISRA rule (1.1,18.4,6.4,19.7) checking. */
00036 /*lint -save  -e621 Disable MISRA rule (5.1) checking. */
00037 /* Types definition */
00038 typedef unsigned char byte;
00039 typedef unsigned short word;
00040 typedef unsigned long dword;
00041 
00042 /* Watchdog reset macro */
00043 #ifndef __RESET_WATCHDOG
00044 #ifdef _lint
00045   #define __RESET_WATCHDOG()  /* empty */
00046 #else
00047   #define __RESET_WATCHDOG()  /* This derivative does not contain watchdog */
00048 #endif
00049 #endif /* __RESET_WATCHDOG */
00050 
00051 #pragma options align=packed
00052 
00053 /**************** interrupt vector numbers ****************/
00054 #define VectorNumber_INITSP             0U
00055 #define VectorNumber_INITPC             1U
00056 #define VectorNumber_Vaccerr            2U
00057 #define VectorNumber_Vadderr            3U
00058 #define VectorNumber_Viinstr            4U
00059 #define VectorNumber_VReserved5         5U
00060 #define VectorNumber_VReserved6         6U
00061 #define VectorNumber_VReserved7         7U
00062 #define VectorNumber_Vprviol            8U
00063 #define VectorNumber_Vtrace             9U
00064 #define VectorNumber_Vunilaop           10U
00065 #define VectorNumber_Vunilfop           11U
00066 #define VectorNumber_Vdbgi              12U
00067 #define VectorNumber_VReserved13        13U
00068 #define VectorNumber_Vferror            14U
00069 #define VectorNumber_VReserved15        15U
00070 #define VectorNumber_VReserved16        16U
00071 #define VectorNumber_VReserved17        17U
00072 #define VectorNumber_VReserved18        18U
00073 #define VectorNumber_VReserved19        19U
00074 #define VectorNumber_VReserved20        20U
00075 #define VectorNumber_VReserved21        21U
00076 #define VectorNumber_VReserved22        22U
00077 #define VectorNumber_VReserved23        23U
00078 #define VectorNumber_Vspuri             24U
00079 #define VectorNumber_VReserved25        25U
00080 #define VectorNumber_VReserved26        26U
00081 #define VectorNumber_VReserved27        27U
00082 #define VectorNumber_VReserved28        28U
00083 #define VectorNumber_VReserved29        29U
00084 #define VectorNumber_VReserved30        30U
00085 #define VectorNumber_VReserved31        31U
00086 #define VectorNumber_Vtrap0             32U
00087 #define VectorNumber_Vtrap1             33U
00088 #define VectorNumber_Vtrap2             34U
00089 #define VectorNumber_Vtrap3             35U
00090 #define VectorNumber_Vtrap4             36U
00091 #define VectorNumber_Vtrap5             37U
00092 #define VectorNumber_Vtrap6             38U
00093 #define VectorNumber_Vtrap7             39U
00094 #define VectorNumber_Vtrap8             40U
00095 #define VectorNumber_Vtrap9             41U
00096 #define VectorNumber_Vtrap10            42U
00097 #define VectorNumber_Vtrap11            43U
00098 #define VectorNumber_Vtrap12            44U
00099 #define VectorNumber_Vtrap13            45U
00100 #define VectorNumber_Vtrap14            46U
00101 #define VectorNumber_Vtrap15            47U
00102 #define VectorNumber_VReserved48        48U
00103 #define VectorNumber_VReserved49        49U
00104 #define VectorNumber_VReserved50        50U
00105 #define VectorNumber_VReserved51        51U
00106 #define VectorNumber_VReserved52        52U
00107 #define VectorNumber_VReserved53        53U
00108 #define VectorNumber_VReserved54        54U
00109 #define VectorNumber_VReserved55        55U
00110 #define VectorNumber_VReserved56        56U
00111 #define VectorNumber_VReserved57        57U
00112 #define VectorNumber_VReserved58        58U
00113 #define VectorNumber_VReserved59        59U
00114 #define VectorNumber_VReserved60        60U
00115 #define VectorNumber_Vunsinstr          61U
00116 #define VectorNumber_VReserved62        62U
00117 #define VectorNumber_VReserved63        63U
00118 #define VectorNumber_Virq               64U
00119 #define VectorNumber_Vframe_err         65U
00120 #define VectorNumber_VReserved66        66U
00121 #define VectorNumber_VReserved67        67U
00122 #define VectorNumber_VReserved68        68U
00123 #define VectorNumber_VReserved69        69U
00124 #define VectorNumber_Vtpm1ovf           70U
00125 #define VectorNumber_Vtpm1ch0           71U
00126 #define VectorNumber_Vtpm1ch1           72U
00127 #define VectorNumber_VReserved73        73U
00128 #define VectorNumber_VReserved74        74U
00129 #define VectorNumber_Vmtim              75U
00130 #define VectorNumber_Vpdb_a             76U
00131 #define VectorNumber_Vpdb_b             77U
00132 #define VectorNumber_VReserved78        78U
00133 #define VectorNumber_VReserved79        79U
00134 #define VectorNumber_VReserved80        80U
00135 #define VectorNumber_VReserved81        81U
00136 #define VectorNumber_Vsp_wake           82U
00137 #define VectorNumber_VReserved83        83U
00138 #define VectorNumber_VReserved84        84U
00139 #define VectorNumber_VReserved85        85U
00140 #define VectorNumber_VReserved86        86U
00141 #define VectorNumber_VReserved87        87U
00142 #define VectorNumber_VReserved88        88U
00143 #define VectorNumber_VReserved89        89U
00144 #define VectorNumber_Vsp_to_0           90U
00145 #define VectorNumber_Vsp_to_1           91U
00146 #define VectorNumber_VReserved92        92U
00147 #define VectorNumber_VReserved93        93U
00148 #define VectorNumber_VReserved94        94U
00149 #define VectorNumber_Vstart_of_frame    95U
00150 #define VectorNumber_Vconversion_complete 96U
00151 #define VectorNumber_VReserved97        97U
00152 #define VectorNumber_VReserved98        98U
00153 #define VectorNumber_VReserved99        99U
00154 #define VectorNumber_VReserved100       100U
00155 #define VectorNumber_Vmaster_i2c        101U
00156 #define VectorNumber_VReserved102       102U
00157 #define VectorNumber_VL7swi             103U
00158 #define VectorNumber_VL6swi             104U
00159 #define VectorNumber_VL5swi             105U
00160 #define VectorNumber_VL4swi             106U
00161 #define VectorNumber_VL3swi             107U
00162 #define VectorNumber_VL2swi             108U
00163 #define VectorNumber_VL1swi             109U
00164 #define VectorNumber_Vqspi_tx_empty     110U
00165 #define VectorNumber_Vqspi_rx_full      111U
00166 #define VectorNumber_VReserved112       112U
00167 #define VectorNumber_VReserved113       113U
00168 #define VectorNumber_VReserved114       114U
00169 
00170 /**************** interrupt vector table ****************/
00171 #define INITSP                          0x0000U
00172 #define INITPC                          0x0004U
00173 #define Vaccerr                         0x0008U
00174 #define Vadderr                         0x000CU
00175 #define Viinstr                         0x0010U
00176 #define VReserved5                      0x0014U
00177 #define VReserved6                      0x0018U
00178 #define VReserved7                      0x001CU
00179 #define Vprviol                         0x0020U
00180 #define Vtrace                          0x0024U
00181 #define Vunilaop                        0x0028U
00182 #define Vunilfop                        0x002CU
00183 #define Vdbgi                           0x0030U
00184 #define VReserved13                     0x0034U
00185 #define Vferror                         0x0038U
00186 #define VReserved15                     0x003CU
00187 #define VReserved16                     0x0040U
00188 #define VReserved17                     0x0044U
00189 #define VReserved18                     0x0048U
00190 #define VReserved19                     0x004CU
00191 #define VReserved20                     0x0050U
00192 #define VReserved21                     0x0054U
00193 #define VReserved22                     0x0058U
00194 #define VReserved23                     0x005CU
00195 #define Vspuri                          0x0060U
00196 #define VReserved25                     0x0064U
00197 #define VReserved26                     0x0068U
00198 #define VReserved27                     0x006CU
00199 #define VReserved28                     0x0070U
00200 #define VReserved29                     0x0074U
00201 #define VReserved30                     0x0078U
00202 #define VReserved31                     0x007CU
00203 #define Vtrap0                          0x0080U
00204 #define Vtrap1                          0x0084U
00205 #define Vtrap2                          0x0088U
00206 #define Vtrap3                          0x008CU
00207 #define Vtrap4                          0x0090U
00208 #define Vtrap5                          0x0094U
00209 #define Vtrap6                          0x0098U
00210 #define Vtrap7                          0x009CU
00211 #define Vtrap8                          0x00A0U
00212 #define Vtrap9                          0x00A4U
00213 #define Vtrap10                         0x00A8U
00214 #define Vtrap11                         0x00ACU
00215 #define Vtrap12                         0x00B0U
00216 #define Vtrap13                         0x00B4U
00217 #define Vtrap14                         0x00B8U
00218 #define Vtrap15                         0x00BCU
00219 #define VReserved48                     0x00C0U
00220 #define VReserved49                     0x00C4U
00221 #define VReserved50                     0x00C8U
00222 #define VReserved51                     0x00CCU
00223 #define VReserved52                     0x00D0U
00224 #define VReserved53                     0x00D4U
00225 #define VReserved54                     0x00D8U
00226 #define VReserved55                     0x00DCU
00227 #define VReserved56                     0x00E0U
00228 #define VReserved57                     0x00E4U
00229 #define VReserved58                     0x00E8U
00230 #define VReserved59                     0x00ECU
00231 #define VReserved60                     0x00F0U
00232 #define Vunsinstr                       0x00F4U
00233 #define VReserved62                     0x00F8U
00234 #define VReserved63                     0x00FCU
00235 #define Virq                            0x0100U
00236 #define Vframe_err                      0x0104U
00237 #define VReserved66                     0x0108U
00238 #define VReserved67                     0x010CU
00239 #define VReserved68                     0x0110U
00240 #define VReserved69                     0x0114U
00241 #define Vtpm1ovf                        0x0118U
00242 #define Vtpm1ch0                        0x011CU
00243 #define Vtpm1ch1                        0x0120U
00244 #define VReserved73                     0x0124U
00245 #define VReserved74                     0x0128U
00246 #define Vmtim                           0x012CU
00247 #define Vpdb_a                          0x0130U
00248 #define Vpdb_b                          0x0134U
00249 #define VReserved78                     0x0138U
00250 #define VReserved79                     0x013CU
00251 #define VReserved80                     0x0140U
00252 #define VReserved81                     0x0144U
00253 #define Vsp_wake                        0x0148U
00254 #define VReserved83                     0x014CU
00255 #define VReserved84                     0x0150U
00256 #define VReserved85                     0x0154U
00257 #define VReserved86                     0x0158U
00258 #define VReserved87                     0x015CU
00259 #define VReserved88                     0x0160U
00260 #define VReserved89                     0x0164U
00261 #define Vsp_to_0                        0x0168U
00262 #define Vsp_to_1                        0x016CU
00263 #define VReserved92                     0x0170U
00264 #define VReserved93                     0x0174U
00265 #define VReserved94                     0x0178U
00266 #define Vstart_of_frame                 0x017CU
00267 #define Vconversion_complete            0x0180U
00268 #define VReserved97                     0x0184U
00269 #define VReserved98                     0x0188U
00270 #define VReserved99                     0x018CU
00271 #define VReserved100                    0x0190U
00272 #define Vmaster_i2c                     0x0194U
00273 #define VReserved102                    0x0198U
00274 #define VL7swi                          0x019CU
00275 #define VL6swi                          0x01A0U
00276 #define VL5swi                          0x01A4U
00277 #define VL4swi                          0x01A8U
00278 #define VL3swi                          0x01ACU
00279 #define VL2swi                          0x01B0U
00280 #define VL1swi                          0x01B4U
00281 #define Vqspi_tx_empty                  0x01B8U
00282 #define Vqspi_rx_full                   0x01BCU
00283 #define VReserved112                    0x01C0U
00284 #define VReserved113                    0x01C4U
00285 #define VReserved114                    0x01C8U
00286 
00287 /**************** registers I/O map ****************/
00288 
00289 /*** CRC - Expected flash checksum; 0x0001FFFC ***/
00290 typedef union {
00291   word Word;
00292   struct {
00293     word CRC0        :1;                                       /* CRC bit 0 */
00294     word CRC1        :1;                                       /* CRC bit 1 */
00295     word CRC2        :1;                                       /* CRC bit 2 */
00296     word CRC3        :1;                                       /* CRC bit 3 */
00297     word CRC4        :1;                                       /* CRC bit 4 */
00298     word CRC5        :1;                                       /* CRC bit 5 */
00299     word CRC6        :1;                                       /* CRC bit 6 */
00300     word CRC7        :1;                                       /* CRC bit 7 */
00301     word CRC8        :1;                                       /* CRC bit 8 */
00302     word CRC9        :1;                                       /* CRC bit 9 */
00303     word CRC10       :1;                                       /* CRC bit 10 */
00304     word CRC11       :1;                                       /* CRC bit 11 */
00305     word CRC12       :1;                                       /* CRC bit 12 */
00306     word CRC13       :1;                                       /* CRC bit 13 */
00307     word CRC14       :1;                                       /* CRC bit 14 */
00308     word CRC15       :1;                                       /* CRC bit 15 */
00309   } Bits;
00310 } CRCSTR;
00311 /* Tip for register initialization in the user code:  const word CRC_INIT @0x0001FFFC = <CRC_INITVAL>; */
00312 #define _CRC (*(const CRCSTR *)0x0001FFFC)
00313 #define CRC                             _CRC.Word
00314 #define CRC_CRC0                        _CRC.Bits.CRC0
00315 #define CRC_CRC1                        _CRC.Bits.CRC1
00316 #define CRC_CRC2                        _CRC.Bits.CRC2
00317 #define CRC_CRC3                        _CRC.Bits.CRC3
00318 #define CRC_CRC4                        _CRC.Bits.CRC4
00319 #define CRC_CRC5                        _CRC.Bits.CRC5
00320 #define CRC_CRC6                        _CRC.Bits.CRC6
00321 #define CRC_CRC7                        _CRC.Bits.CRC7
00322 #define CRC_CRC8                        _CRC.Bits.CRC8
00323 #define CRC_CRC9                        _CRC.Bits.CRC9
00324 #define CRC_CRC10                       _CRC.Bits.CRC10
00325 #define CRC_CRC11                       _CRC.Bits.CRC11
00326 #define CRC_CRC12                       _CRC.Bits.CRC12
00327 #define CRC_CRC13                       _CRC.Bits.CRC13
00328 #define CRC_CRC14                       _CRC.Bits.CRC14
00329 #define CRC_CRC15                       _CRC.Bits.CRC15
00330 
00331 #define CRC_CRC0_MASK                   1U
00332 #define CRC_CRC1_MASK                   2U
00333 #define CRC_CRC2_MASK                   4U
00334 #define CRC_CRC3_MASK                   8U
00335 #define CRC_CRC4_MASK                   16U
00336 #define CRC_CRC5_MASK                   32U
00337 #define CRC_CRC6_MASK                   64U
00338 #define CRC_CRC7_MASK                   128U
00339 #define CRC_CRC8_MASK                   256U
00340 #define CRC_CRC9_MASK                   512U
00341 #define CRC_CRC10_MASK                  1024U
00342 #define CRC_CRC11_MASK                  2048U
00343 #define CRC_CRC12_MASK                  4096U
00344 #define CRC_CRC13_MASK                  8192U
00345 #define CRC_CRC14_MASK                  16384U
00346 #define CRC_CRC15_MASK                  32768U
00347 
00348 
00349 /*** NVBOPT - Nonvolatile Flash Protection Register; 0x0001FFFE ***/
00350 typedef union {
00351   byte Byte;
00352   struct {
00353     byte Bit0        :1;                                       /* Bit0 */
00354     byte Bit1        :1;                                       /* Bit1 */
00355     byte Bit2        :1;                                       /* Bit2 */
00356     byte Bit3        :1;                                       /* Bit3 */
00357     byte Bit4        :1;                                       /* Bit4 */
00358     byte Bit5        :1;                                       /* Bit5 */
00359     byte Bit6        :1;                                       /* Bit6 */
00360     byte Bit7        :1;                                       /* Bit7 */
00361   } Bits;
00362 } NVBOPTSTR;
00363 /* Tip for register initialization in the user code:  const byte NVBOPT_INIT @0x0001FFFE = <NVBOPT_INITVAL>; */
00364 #define _NVBOPT (*(const NVBOPTSTR *)0x0001FFFE)
00365 #define NVBOPT                          _NVBOPT.Byte
00366 #define NVBOPT_Bit0                     _NVBOPT.Bits.Bit0
00367 #define NVBOPT_Bit1                     _NVBOPT.Bits.Bit1
00368 #define NVBOPT_Bit2                     _NVBOPT.Bits.Bit2
00369 #define NVBOPT_Bit3                     _NVBOPT.Bits.Bit3
00370 #define NVBOPT_Bit4                     _NVBOPT.Bits.Bit4
00371 #define NVBOPT_Bit5                     _NVBOPT.Bits.Bit5
00372 #define NVBOPT_Bit6                     _NVBOPT.Bits.Bit6
00373 #define NVBOPT_Bit7                     _NVBOPT.Bits.Bit7
00374 
00375 #define NVBOPT_Bit0_MASK                1U
00376 #define NVBOPT_Bit1_MASK                2U
00377 #define NVBOPT_Bit2_MASK                4U
00378 #define NVBOPT_Bit3_MASK                8U
00379 #define NVBOPT_Bit4_MASK                16U
00380 #define NVBOPT_Bit5_MASK                32U
00381 #define NVBOPT_Bit6_MASK                64U
00382 #define NVBOPT_Bit7_MASK                128U
00383 
00384 
00385 /*** NVOPT - Nonvolatile Flash Options Register; 0x0001FFFF ***/
00386 typedef union {
00387   byte Byte;
00388   struct {
00389     byte SSC0        :1;                                       /* Security State Bit 0 */
00390     byte SSC1        :1;                                       /* Security State Bit 1 */
00391     byte SSW         :1;                                       /* Security State Writable */
00392     byte             :1; 
00393     byte PROTB       :1;                                       /* Active Low Write Protect */
00394     byte PW          :1;                                       /* PROTB Writable */
00395     byte             :1; 
00396     byte             :1; 
00397   } Bits;
00398   struct {
00399     byte grpSSC  :2;
00400     byte         :1;
00401     byte         :1;
00402     byte         :1;
00403     byte         :1;
00404     byte         :1;
00405     byte         :1;
00406   } MergedBits;
00407 } NVOPTSTR;
00408 /* Tip for register initialization in the user code:  const byte NVOPT_INIT @0x0001FFFF = <NVOPT_INITVAL>; */
00409 #define _NVOPT (*(const NVOPTSTR *)0x0001FFFF)
00410 #define NVOPT                           _NVOPT.Byte
00411 #define NVOPT_SSC0                      _NVOPT.Bits.SSC0
00412 #define NVOPT_SSC1                      _NVOPT.Bits.SSC1
00413 #define NVOPT_SSW                       _NVOPT.Bits.SSW
00414 #define NVOPT_PROTB                     _NVOPT.Bits.PROTB
00415 #define NVOPT_PW                        _NVOPT.Bits.PW
00416 #define NVOPT_SSC                       _NVOPT.MergedBits.grpSSC
00417 
00418 #define NVOPT_SSC0_MASK                 1U
00419 #define NVOPT_SSC1_MASK                 2U
00420 #define NVOPT_SSW_MASK                  4U
00421 #define NVOPT_PROTB_MASK                16U
00422 #define NVOPT_PW_MASK                   32U
00423 #define NVOPT_SSC_MASK                  3U
00424 #define NVOPT_SSC_BITNUM                0U
00425 
00426 
00427 /*** RGPIO_DIR - RGPIO Data Direction Register; 0x00C00000 ***/
00428 typedef union {
00429   word Word;
00430   struct {
00431     word DIR0        :1;                                       /* RGPIO data direction bit 0 */
00432     word DIR1        :1;                                       /* RGPIO data direction bit 1 */
00433     word DIR2        :1;                                       /* RGPIO data direction bit 2 */
00434     word DIR3        :1;                                       /* RGPIO data direction bit 3 */
00435     word DIR4        :1;                                       /* RGPIO data direction bit 4 */
00436     word DIR5        :1;                                       /* RGPIO data direction bit 5 */
00437     word DIR6        :1;                                       /* RGPIO data direction bit 6 */
00438     word DIR7        :1;                                       /* RGPIO data direction bit 7 */
00439     word DIR8        :1;                                       /* RGPIO data direction bit 8 */
00440     word DIR9        :1;                                       /* RGPIO data direction bit 9 */
00441     word DIR10       :1;                                       /* RGPIO data direction bit 10 */
00442     word DIR11       :1;                                       /* RGPIO data direction bit 11 */
00443     word DIR12       :1;                                       /* RGPIO data direction bit 12 */
00444     word DIR13       :1;                                       /* RGPIO data direction bit 13 */
00445     word DIR14       :1;                                       /* RGPIO data direction bit 14 */
00446     word DIR15       :1;                                       /* RGPIO data direction bit 15 */
00447   } Bits;
00448 } RGPIO_DIRSTR;
00449 extern volatile RGPIO_DIRSTR _RGPIO_DIR @0x00C00000;
00450 #define RGPIO_DIR                       _RGPIO_DIR.Word
00451 #define RGPIO_DIR_DIR0                  _RGPIO_DIR.Bits.DIR0
00452 #define RGPIO_DIR_DIR1                  _RGPIO_DIR.Bits.DIR1
00453 #define RGPIO_DIR_DIR2                  _RGPIO_DIR.Bits.DIR2
00454 #define RGPIO_DIR_DIR3                  _RGPIO_DIR.Bits.DIR3
00455 #define RGPIO_DIR_DIR4                  _RGPIO_DIR.Bits.DIR4
00456 #define RGPIO_DIR_DIR5                  _RGPIO_DIR.Bits.DIR5
00457 #define RGPIO_DIR_DIR6                  _RGPIO_DIR.Bits.DIR6
00458 #define RGPIO_DIR_DIR7                  _RGPIO_DIR.Bits.DIR7
00459 #define RGPIO_DIR_DIR8                  _RGPIO_DIR.Bits.DIR8
00460 #define RGPIO_DIR_DIR9                  _RGPIO_DIR.Bits.DIR9
00461 #define RGPIO_DIR_DIR10                 _RGPIO_DIR.Bits.DIR10
00462 #define RGPIO_DIR_DIR11                 _RGPIO_DIR.Bits.DIR11
00463 #define RGPIO_DIR_DIR12                 _RGPIO_DIR.Bits.DIR12
00464 #define RGPIO_DIR_DIR13                 _RGPIO_DIR.Bits.DIR13
00465 #define RGPIO_DIR_DIR14                 _RGPIO_DIR.Bits.DIR14
00466 #define RGPIO_DIR_DIR15                 _RGPIO_DIR.Bits.DIR15
00467 
00468 #define RGPIO_DIR_DIR0_MASK             1U
00469 #define RGPIO_DIR_DIR1_MASK             2U
00470 #define RGPIO_DIR_DIR2_MASK             4U
00471 #define RGPIO_DIR_DIR3_MASK             8U
00472 #define RGPIO_DIR_DIR4_MASK             16U
00473 #define RGPIO_DIR_DIR5_MASK             32U
00474 #define RGPIO_DIR_DIR6_MASK             64U
00475 #define RGPIO_DIR_DIR7_MASK             128U
00476 #define RGPIO_DIR_DIR8_MASK             256U
00477 #define RGPIO_DIR_DIR9_MASK             512U
00478 #define RGPIO_DIR_DIR10_MASK            1024U
00479 #define RGPIO_DIR_DIR11_MASK            2048U
00480 #define RGPIO_DIR_DIR12_MASK            4096U
00481 #define RGPIO_DIR_DIR13_MASK            8192U
00482 #define RGPIO_DIR_DIR14_MASK            16384U
00483 #define RGPIO_DIR_DIR15_MASK            32768U
00484 
00485 
00486 /*** RGPIO_DATA - RGPIO Data Register; 0x00C00002 ***/
00487 typedef union {
00488   word Word;
00489   struct {
00490     word DATA0       :1;                                       /* RGPIO data bit 0 */
00491     word DATA1       :1;                                       /* RGPIO data bit 1 */
00492     word DATA2       :1;                                       /* RGPIO data bit 2 */
00493     word DATA3       :1;                                       /* RGPIO data bit 3 */
00494     word DATA4       :1;                                       /* RGPIO data bit 4 */
00495     word DATA5       :1;                                       /* RGPIO data bit 5 */
00496     word DATA6       :1;                                       /* RGPIO data bit 6 */
00497     word DATA7       :1;                                       /* RGPIO data bit 7 */
00498     word DATA8       :1;                                       /* RGPIO data bit 8 */
00499     word DATA9       :1;                                       /* RGPIO data bit 9 */
00500     word DATA10      :1;                                       /* RGPIO data bit 10 */
00501     word DATA11      :1;                                       /* RGPIO data bit 11 */
00502     word DATA12      :1;                                       /* RGPIO data bit 12 */
00503     word DATA13      :1;                                       /* RGPIO data bit 13 */
00504     word DATA14      :1;                                       /* RGPIO data bit 14 */
00505     word DATA15      :1;                                       /* RGPIO data bit 15 */
00506   } Bits;
00507 } RGPIO_DATASTR;
00508 extern volatile RGPIO_DATASTR _RGPIO_DATA @0x00C00002;
00509 #define RGPIO_DATA                      _RGPIO_DATA.Word
00510 #define RGPIO_DATA_DATA0                _RGPIO_DATA.Bits.DATA0
00511 #define RGPIO_DATA_DATA1                _RGPIO_DATA.Bits.DATA1
00512 #define RGPIO_DATA_DATA2                _RGPIO_DATA.Bits.DATA2
00513 #define RGPIO_DATA_DATA3                _RGPIO_DATA.Bits.DATA3
00514 #define RGPIO_DATA_DATA4                _RGPIO_DATA.Bits.DATA4
00515 #define RGPIO_DATA_DATA5                _RGPIO_DATA.Bits.DATA5
00516 #define RGPIO_DATA_DATA6                _RGPIO_DATA.Bits.DATA6
00517 #define RGPIO_DATA_DATA7                _RGPIO_DATA.Bits.DATA7
00518 #define RGPIO_DATA_DATA8                _RGPIO_DATA.Bits.DATA8
00519 #define RGPIO_DATA_DATA9                _RGPIO_DATA.Bits.DATA9
00520 #define RGPIO_DATA_DATA10               _RGPIO_DATA.Bits.DATA10
00521 #define RGPIO_DATA_DATA11               _RGPIO_DATA.Bits.DATA11
00522 #define RGPIO_DATA_DATA12               _RGPIO_DATA.Bits.DATA12
00523 #define RGPIO_DATA_DATA13               _RGPIO_DATA.Bits.DATA13
00524 #define RGPIO_DATA_DATA14               _RGPIO_DATA.Bits.DATA14
00525 #define RGPIO_DATA_DATA15               _RGPIO_DATA.Bits.DATA15
00526 
00527 #define RGPIO_DATA_DATA0_MASK           1U
00528 #define RGPIO_DATA_DATA1_MASK           2U
00529 #define RGPIO_DATA_DATA2_MASK           4U
00530 #define RGPIO_DATA_DATA3_MASK           8U
00531 #define RGPIO_DATA_DATA4_MASK           16U
00532 #define RGPIO_DATA_DATA5_MASK           32U
00533 #define RGPIO_DATA_DATA6_MASK           64U
00534 #define RGPIO_DATA_DATA7_MASK           128U
00535 #define RGPIO_DATA_DATA8_MASK           256U
00536 #define RGPIO_DATA_DATA9_MASK           512U
00537 #define RGPIO_DATA_DATA10_MASK          1024U
00538 #define RGPIO_DATA_DATA11_MASK          2048U
00539 #define RGPIO_DATA_DATA12_MASK          4096U
00540 #define RGPIO_DATA_DATA13_MASK          8192U
00541 #define RGPIO_DATA_DATA14_MASK          16384U
00542 #define RGPIO_DATA_DATA15_MASK          32768U
00543 
00544 
00545 /*** RGPIO_ENB - RGPIO Pin Enable Register; 0x00C00004 ***/
00546 typedef union {
00547   word Word;
00548   struct {
00549     word ENB0        :1;                                       /* RGPIO enable bit 0 */
00550     word ENB1        :1;                                       /* RGPIO enable bit 1 */
00551     word ENB2        :1;                                       /* RGPIO enable bit 2 */
00552     word ENB3        :1;                                       /* RGPIO enable bit 3 */
00553     word ENB4        :1;                                       /* RGPIO enable bit 4 */
00554     word ENB5        :1;                                       /* RGPIO enable bit 5 */
00555     word ENB6        :1;                                       /* RGPIO enable bit 6 */
00556     word ENB7        :1;                                       /* RGPIO enable bit 7 */
00557     word ENB8        :1;                                       /* RGPIO enable bit 8 */
00558     word ENB9        :1;                                       /* RGPIO enable bit 9 */
00559     word ENB10       :1;                                       /* RGPIO enable bit 10 */
00560     word ENB11       :1;                                       /* RGPIO enable bit 11 */
00561     word ENB12       :1;                                       /* RGPIO enable bit 12 */
00562     word ENB13       :1;                                       /* RGPIO enable bit 13 */
00563     word ENB14       :1;                                       /* RGPIO enable bit 14 */
00564     word ENB15       :1;                                       /* RGPIO enable bit 15 */
00565   } Bits;
00566 } RGPIO_ENBSTR;
00567 extern volatile RGPIO_ENBSTR _RGPIO_ENB @0x00C00004;
00568 #define RGPIO_ENB                       _RGPIO_ENB.Word
00569 #define RGPIO_ENB_ENB0                  _RGPIO_ENB.Bits.ENB0
00570 #define RGPIO_ENB_ENB1                  _RGPIO_ENB.Bits.ENB1
00571 #define RGPIO_ENB_ENB2                  _RGPIO_ENB.Bits.ENB2
00572 #define RGPIO_ENB_ENB3                  _RGPIO_ENB.Bits.ENB3
00573 #define RGPIO_ENB_ENB4                  _RGPIO_ENB.Bits.ENB4
00574 #define RGPIO_ENB_ENB5                  _RGPIO_ENB.Bits.ENB5
00575 #define RGPIO_ENB_ENB6                  _RGPIO_ENB.Bits.ENB6
00576 #define RGPIO_ENB_ENB7                  _RGPIO_ENB.Bits.ENB7
00577 #define RGPIO_ENB_ENB8                  _RGPIO_ENB.Bits.ENB8
00578 #define RGPIO_ENB_ENB9                  _RGPIO_ENB.Bits.ENB9
00579 #define RGPIO_ENB_ENB10                 _RGPIO_ENB.Bits.ENB10
00580 #define RGPIO_ENB_ENB11                 _RGPIO_ENB.Bits.ENB11
00581 #define RGPIO_ENB_ENB12                 _RGPIO_ENB.Bits.ENB12
00582 #define RGPIO_ENB_ENB13                 _RGPIO_ENB.Bits.ENB13
00583 #define RGPIO_ENB_ENB14                 _RGPIO_ENB.Bits.ENB14
00584 #define RGPIO_ENB_ENB15                 _RGPIO_ENB.Bits.ENB15
00585 
00586 #define RGPIO_ENB_ENB0_MASK             1U
00587 #define RGPIO_ENB_ENB1_MASK             2U
00588 #define RGPIO_ENB_ENB2_MASK             4U
00589 #define RGPIO_ENB_ENB3_MASK             8U
00590 #define RGPIO_ENB_ENB4_MASK             16U
00591 #define RGPIO_ENB_ENB5_MASK             32U
00592 #define RGPIO_ENB_ENB6_MASK             64U
00593 #define RGPIO_ENB_ENB7_MASK             128U
00594 #define RGPIO_ENB_ENB8_MASK             256U
00595 #define RGPIO_ENB_ENB9_MASK             512U
00596 #define RGPIO_ENB_ENB10_MASK            1024U
00597 #define RGPIO_ENB_ENB11_MASK            2048U
00598 #define RGPIO_ENB_ENB12_MASK            4096U
00599 #define RGPIO_ENB_ENB13_MASK            8192U
00600 #define RGPIO_ENB_ENB14_MASK            16384U
00601 #define RGPIO_ENB_ENB15_MASK            32768U
00602 
00603 
00604 /*** RGPIO_CLR - RGPIO Clear Data Register; 0x00C00006 ***/
00605 typedef union {
00606   word Word;
00607   struct {
00608     word CLR0        :1;                                       /* RGPIO clear data bit 0 */
00609     word CLR1        :1;                                       /* RGPIO clear data bit 1 */
00610     word CLR2        :1;                                       /* RGPIO clear data bit 2 */
00611     word CLR3        :1;                                       /* RGPIO clear data bit 3 */
00612     word CLR4        :1;                                       /* RGPIO clear data bit 4 */
00613     word CLR5        :1;                                       /* RGPIO clear data bit 5 */
00614     word CLR6        :1;                                       /* RGPIO clear data bit 6 */
00615     word CLR7        :1;                                       /* RGPIO clear data bit 7 */
00616     word CLR8        :1;                                       /* RGPIO clear data bit 8 */
00617     word CLR9        :1;                                       /* RGPIO clear data bit 9 */
00618     word CLR10       :1;                                       /* RGPIO clear data bit 10 */
00619     word CLR11       :1;                                       /* RGPIO clear data bit 11 */
00620     word CLR12       :1;                                       /* RGPIO clear data bit 12 */
00621     word CLR13       :1;                                       /* RGPIO clear data bit 13 */
00622     word CLR14       :1;                                       /* RGPIO clear data bit 14 */
00623     word CLR15       :1;                                       /* RGPIO clear data bit 15 */
00624   } Bits;
00625 } RGPIO_CLRSTR;
00626 extern volatile RGPIO_CLRSTR _RGPIO_CLR @0x00C00006;
00627 #define RGPIO_CLR                       _RGPIO_CLR.Word
00628 #define RGPIO_CLR_CLR0                  _RGPIO_CLR.Bits.CLR0
00629 #define RGPIO_CLR_CLR1                  _RGPIO_CLR.Bits.CLR1
00630 #define RGPIO_CLR_CLR2                  _RGPIO_CLR.Bits.CLR2
00631 #define RGPIO_CLR_CLR3                  _RGPIO_CLR.Bits.CLR3
00632 #define RGPIO_CLR_CLR4                  _RGPIO_CLR.Bits.CLR4
00633 #define RGPIO_CLR_CLR5                  _RGPIO_CLR.Bits.CLR5
00634 #define RGPIO_CLR_CLR6                  _RGPIO_CLR.Bits.CLR6
00635 #define RGPIO_CLR_CLR7                  _RGPIO_CLR.Bits.CLR7
00636 #define RGPIO_CLR_CLR8                  _RGPIO_CLR.Bits.CLR8
00637 #define RGPIO_CLR_CLR9                  _RGPIO_CLR.Bits.CLR9
00638 #define RGPIO_CLR_CLR10                 _RGPIO_CLR.Bits.CLR10
00639 #define RGPIO_CLR_CLR11                 _RGPIO_CLR.Bits.CLR11
00640 #define RGPIO_CLR_CLR12                 _RGPIO_CLR.Bits.CLR12
00641 #define RGPIO_CLR_CLR13                 _RGPIO_CLR.Bits.CLR13
00642 #define RGPIO_CLR_CLR14                 _RGPIO_CLR.Bits.CLR14
00643 #define RGPIO_CLR_CLR15                 _RGPIO_CLR.Bits.CLR15
00644 
00645 #define RGPIO_CLR_CLR0_MASK             1U
00646 #define RGPIO_CLR_CLR1_MASK             2U
00647 #define RGPIO_CLR_CLR2_MASK             4U
00648 #define RGPIO_CLR_CLR3_MASK             8U
00649 #define RGPIO_CLR_CLR4_MASK             16U
00650 #define RGPIO_CLR_CLR5_MASK             32U
00651 #define RGPIO_CLR_CLR6_MASK             64U
00652 #define RGPIO_CLR_CLR7_MASK             128U
00653 #define RGPIO_CLR_CLR8_MASK             256U
00654 #define RGPIO_CLR_CLR9_MASK             512U
00655 #define RGPIO_CLR_CLR10_MASK            1024U
00656 #define RGPIO_CLR_CLR11_MASK            2048U
00657 #define RGPIO_CLR_CLR12_MASK            4096U
00658 #define RGPIO_CLR_CLR13_MASK            8192U
00659 #define RGPIO_CLR_CLR14_MASK            16384U
00660 #define RGPIO_CLR_CLR15_MASK            32768U
00661 
00662 
00663 /*** RGPIO_SET - RGPIO Set Data Register; 0x00C0000A ***/
00664 typedef union {
00665   word Word;
00666   struct {
00667     word SET0        :1;                                       /* RGPIO set data bit 0 */
00668     word SET1        :1;                                       /* RGPIO set data bit 1 */
00669     word SET2        :1;                                       /* RGPIO set data bit 2 */
00670     word SET3        :1;                                       /* RGPIO set data bit 3 */
00671     word SET4        :1;                                       /* RGPIO set data bit 4 */
00672     word SET5        :1;                                       /* RGPIO set data bit 5 */
00673     word SET6        :1;                                       /* RGPIO set data bit 6 */
00674     word SET7        :1;                                       /* RGPIO set data bit 7 */
00675     word SET8        :1;                                       /* RGPIO set data bit 8 */
00676     word SET9        :1;                                       /* RGPIO set data bit 9 */
00677     word SET10       :1;                                       /* RGPIO set data bit 10 */
00678     word SET11       :1;                                       /* RGPIO set data bit 11 */
00679     word SET12       :1;                                       /* RGPIO set data bit 12 */
00680     word SET13       :1;                                       /* RGPIO set data bit 13 */
00681     word SET14       :1;                                       /* RGPIO set data bit 14 */
00682     word SET15       :1;                                       /* RGPIO set data bit 15 */
00683   } Bits;
00684 } RGPIO_SETSTR;
00685 extern volatile RGPIO_SETSTR _RGPIO_SET @0x00C0000A;
00686 #define RGPIO_SET                       _RGPIO_SET.Word
00687 #define RGPIO_SET_SET0                  _RGPIO_SET.Bits.SET0
00688 #define RGPIO_SET_SET1                  _RGPIO_SET.Bits.SET1
00689 #define RGPIO_SET_SET2                  _RGPIO_SET.Bits.SET2
00690 #define RGPIO_SET_SET3                  _RGPIO_SET.Bits.SET3
00691 #define RGPIO_SET_SET4                  _RGPIO_SET.Bits.SET4
00692 #define RGPIO_SET_SET5                  _RGPIO_SET.Bits.SET5
00693 #define RGPIO_SET_SET6                  _RGPIO_SET.Bits.SET6
00694 #define RGPIO_SET_SET7                  _RGPIO_SET.Bits.SET7
00695 #define RGPIO_SET_SET8                  _RGPIO_SET.Bits.SET8
00696 #define RGPIO_SET_SET9                  _RGPIO_SET.Bits.SET9
00697 #define RGPIO_SET_SET10                 _RGPIO_SET.Bits.SET10
00698 #define RGPIO_SET_SET11                 _RGPIO_SET.Bits.SET11
00699 #define RGPIO_SET_SET12                 _RGPIO_SET.Bits.SET12
00700 #define RGPIO_SET_SET13                 _RGPIO_SET.Bits.SET13
00701 #define RGPIO_SET_SET14                 _RGPIO_SET.Bits.SET14
00702 #define RGPIO_SET_SET15                 _RGPIO_SET.Bits.SET15
00703 
00704 #define RGPIO_SET_SET0_MASK             1U
00705 #define RGPIO_SET_SET1_MASK             2U
00706 #define RGPIO_SET_SET2_MASK             4U
00707 #define RGPIO_SET_SET3_MASK             8U
00708 #define RGPIO_SET_SET4_MASK             16U
00709 #define RGPIO_SET_SET5_MASK             32U
00710 #define RGPIO_SET_SET6_MASK             64U
00711 #define RGPIO_SET_SET7_MASK             128U
00712 #define RGPIO_SET_SET8_MASK             256U
00713 #define RGPIO_SET_SET9_MASK             512U
00714 #define RGPIO_SET_SET10_MASK            1024U
00715 #define RGPIO_SET_SET11_MASK            2048U
00716 #define RGPIO_SET_SET12_MASK            4096U
00717 #define RGPIO_SET_SET13_MASK            8192U
00718 #define RGPIO_SET_SET14_MASK            16384U
00719 #define RGPIO_SET_SET15_MASK            32768U
00720 
00721 
00722 /*** RGPIO_TOG - RGPIO Toggle Data Register; 0x00C0000E ***/
00723 typedef union {
00724   word Word;
00725   struct {
00726     word TOG0        :1;                                       /* RGPIO toggle data bit 0 */
00727     word TOG1        :1;                                       /* RGPIO toggle data bit 1 */
00728     word TOG2        :1;                                       /* RGPIO toggle data bit 2 */
00729     word TOG3        :1;                                       /* RGPIO toggle data bit 3 */
00730     word TOG4        :1;                                       /* RGPIO toggle data bit 4 */
00731     word TOG5        :1;                                       /* RGPIO toggle data bit 5 */
00732     word TOG6        :1;                                       /* RGPIO toggle data bit 6 */
00733     word TOG7        :1;                                       /* RGPIO toggle data bit 7 */
00734     word TOG8        :1;                                       /* RGPIO toggle data bit 8 */
00735     word TOG9        :1;                                       /* RGPIO toggle data bit 9 */
00736     word TOG10       :1;                                       /* RGPIO toggle data bit 10 */
00737     word TOG11       :1;                                       /* RGPIO toggle data bit 11 */
00738     word TOG12       :1;                                       /* RGPIO toggle data bit 12 */
00739     word TOG13       :1;                                       /* RGPIO toggle data bit 13 */
00740     word TOG14       :1;                                       /* RGPIO toggle data bit 14 */
00741     word TOG15       :1;                                       /* RGPIO toggle data bit 15 */
00742   } Bits;
00743 } RGPIO_TOGSTR;
00744 extern volatile RGPIO_TOGSTR _RGPIO_TOG @0x00C0000E;
00745 #define RGPIO_TOG                       _RGPIO_TOG.Word
00746 #define RGPIO_TOG_TOG0                  _RGPIO_TOG.Bits.TOG0
00747 #define RGPIO_TOG_TOG1                  _RGPIO_TOG.Bits.TOG1
00748 #define RGPIO_TOG_TOG2                  _RGPIO_TOG.Bits.TOG2
00749 #define RGPIO_TOG_TOG3                  _RGPIO_TOG.Bits.TOG3
00750 #define RGPIO_TOG_TOG4                  _RGPIO_TOG.Bits.TOG4
00751 #define RGPIO_TOG_TOG5                  _RGPIO_TOG.Bits.TOG5
00752 #define RGPIO_TOG_TOG6                  _RGPIO_TOG.Bits.TOG6
00753 #define RGPIO_TOG_TOG7                  _RGPIO_TOG.Bits.TOG7
00754 #define RGPIO_TOG_TOG8                  _RGPIO_TOG.Bits.TOG8
00755 #define RGPIO_TOG_TOG9                  _RGPIO_TOG.Bits.TOG9
00756 #define RGPIO_TOG_TOG10                 _RGPIO_TOG.Bits.TOG10
00757 #define RGPIO_TOG_TOG11                 _RGPIO_TOG.Bits.TOG11
00758 #define RGPIO_TOG_TOG12                 _RGPIO_TOG.Bits.TOG12
00759 #define RGPIO_TOG_TOG13                 _RGPIO_TOG.Bits.TOG13
00760 #define RGPIO_TOG_TOG14                 _RGPIO_TOG.Bits.TOG14
00761 #define RGPIO_TOG_TOG15                 _RGPIO_TOG.Bits.TOG15
00762 
00763 #define RGPIO_TOG_TOG0_MASK             1U
00764 #define RGPIO_TOG_TOG1_MASK             2U
00765 #define RGPIO_TOG_TOG2_MASK             4U
00766 #define RGPIO_TOG_TOG3_MASK             8U
00767 #define RGPIO_TOG_TOG4_MASK             16U
00768 #define RGPIO_TOG_TOG5_MASK             32U
00769 #define RGPIO_TOG_TOG6_MASK             64U
00770 #define RGPIO_TOG_TOG7_MASK             128U
00771 #define RGPIO_TOG_TOG8_MASK             256U
00772 #define RGPIO_TOG_TOG9_MASK             512U
00773 #define RGPIO_TOG_TOG10_MASK            1024U
00774 #define RGPIO_TOG_TOG11_MASK            2048U
00775 #define RGPIO_TOG_TOG12_MASK            4096U
00776 #define RGPIO_TOG_TOG13_MASK            8192U
00777 #define RGPIO_TOG_TOG14_MASK            16384U
00778 #define RGPIO_TOG_TOG15_MASK            32768U
00779 
00780 
00781 /*** SP_MB0_dword - Mailbox Register 0, 32 bit; 0xFFFF8000 ***/
00782 typedef union {
00783   dword Dword;
00784    /* Overlapped registers: */
00785   struct {
00786     /*** SP_MB0_word - Mailbox Register 0, 16 bit; 0xFFFF8000 ***/
00787     union {
00788       word Word;
00789        /* Overlapped registers: */
00790       struct {
00791         /*** SP_MB0 - Mailbox Register0; 0xFFFF8000 ***/
00792         union {
00793           byte Byte;
00794         } SP_MB0STR;
00795         #define SP_MB0                  _SP_MB0_dword.Overlap_STR.SP_MB0_wordSTR.Overlap_STR.SP_MB0STR.Byte
00796         /* SP_MB_ARR: Access 32 SP_MBx registers in an array */
00797         #define SP_MB_ARR               ((volatile byte *) &SP_MB0)
00798         
00799     
00800         /*** SP_MB1 - Mailbox Register1; 0xFFFF8001 ***/
00801         union {
00802           byte Byte;
00803         } SP_MB1STR;
00804         #define SP_MB1                  _SP_MB0_dword.Overlap_STR.SP_MB0_wordSTR.Overlap_STR.SP_MB1STR.Byte
00805         
00806       } Overlap_STR;
00807     
00808     } SP_MB0_wordSTR;
00809     #define SP_MB0_word                 _SP_MB0_dword.Overlap_STR.SP_MB0_wordSTR.Word
00810     
00811 
00812     /*** SP_MB1_word - Mailbox Register 1, 16 bit; 0xFFFF8002 ***/
00813     union {
00814       word Word;
00815        /* Overlapped registers: */
00816       struct {
00817         /*** SP_MB2 - Mailbox Register2; 0xFFFF8002 ***/
00818         union {
00819           byte Byte;
00820         } SP_MB2STR;
00821         #define SP_MB2                  _SP_MB0_dword.Overlap_STR.SP_MB1_wordSTR.Overlap_STR.SP_MB2STR.Byte
00822         
00823     
00824         /*** SP_MB3 - Mailbox Register3; 0xFFFF8003 ***/
00825         union {
00826           byte Byte;
00827         } SP_MB3STR;
00828         #define SP_MB3                  _SP_MB0_dword.Overlap_STR.SP_MB1_wordSTR.Overlap_STR.SP_MB3STR.Byte
00829         
00830       } Overlap_STR;
00831     
00832     } SP_MB1_wordSTR;
00833     #define SP_MB1_word                 _SP_MB0_dword.Overlap_STR.SP_MB1_wordSTR.Word
00834     
00835   } Overlap_STR;
00836 
00837 } SP_MB0_dwordSTR;
00838 extern volatile SP_MB0_dwordSTR _SP_MB0_dword @0xFFFF8000;
00839 #define SP_MB0_dword                    _SP_MB0_dword.Dword
00840 
00841 
00842 /*** SP_MB1_dword - Mailbox Register 1, 32 bit; 0xFFFF8004 ***/
00843 typedef union {
00844   dword Dword;
00845    /* Overlapped registers: */
00846   struct {
00847     /*** SP_MB2_word - Mailbox Register 2, 16 bit; 0xFFFF8004 ***/
00848     union {
00849       word Word;
00850        /* Overlapped registers: */
00851       struct {
00852         /*** SP_MB4 - Mailbox Register4; 0xFFFF8004 ***/
00853         union {
00854           byte Byte;
00855         } SP_MB4STR;
00856         #define SP_MB4                  _SP_MB1_dword.Overlap_STR.SP_MB2_wordSTR.Overlap_STR.SP_MB4STR.Byte
00857         
00858     
00859         /*** SP_MB5 - Mailbox Register5; 0xFFFF8005 ***/
00860         union {
00861           byte Byte;
00862         } SP_MB5STR;
00863         #define SP_MB5                  _SP_MB1_dword.Overlap_STR.SP_MB2_wordSTR.Overlap_STR.SP_MB5STR.Byte
00864         
00865       } Overlap_STR;
00866     
00867     } SP_MB2_wordSTR;
00868     #define SP_MB2_word                 _SP_MB1_dword.Overlap_STR.SP_MB2_wordSTR.Word
00869     
00870 
00871     /*** SP_MB3_word - Mailbox Register 3, 16 bit; 0xFFFF8006 ***/
00872     union {
00873       word Word;
00874        /* Overlapped registers: */
00875       struct {
00876         /*** SP_MB6 - Mailbox Register6; 0xFFFF8006 ***/
00877         union {
00878           byte Byte;
00879         } SP_MB6STR;
00880         #define SP_MB6                  _SP_MB1_dword.Overlap_STR.SP_MB3_wordSTR.Overlap_STR.SP_MB6STR.Byte
00881         
00882     
00883         /*** SP_MB7 - Mailbox Register7; 0xFFFF8007 ***/
00884         union {
00885           byte Byte;
00886         } SP_MB7STR;
00887         #define SP_MB7                  _SP_MB1_dword.Overlap_STR.SP_MB3_wordSTR.Overlap_STR.SP_MB7STR.Byte
00888         
00889       } Overlap_STR;
00890     
00891     } SP_MB3_wordSTR;
00892     #define SP_MB3_word                 _SP_MB1_dword.Overlap_STR.SP_MB3_wordSTR.Word
00893     
00894   } Overlap_STR;
00895 
00896 } SP_MB1_dwordSTR;
00897 extern volatile SP_MB1_dwordSTR _SP_MB1_dword @0xFFFF8004;
00898 #define SP_MB1_dword                    _SP_MB1_dword.Dword
00899 
00900 
00901 /*** SP_MB2_dword - Mailbox Register 2, 32 bit; 0xFFFF8008 ***/
00902 typedef union {
00903   dword Dword;
00904    /* Overlapped registers: */
00905   struct {
00906     /*** SP_MB4_word - Mailbox Register 4, 16 bit; 0xFFFF8008 ***/
00907     union {
00908       word Word;
00909        /* Overlapped registers: */
00910       struct {
00911         /*** SP_MB8 - Mailbox Register8; 0xFFFF8008 ***/
00912         union {
00913           byte Byte;
00914         } SP_MB8STR;
00915         #define SP_MB8                  _SP_MB2_dword.Overlap_STR.SP_MB4_wordSTR.Overlap_STR.SP_MB8STR.Byte
00916         
00917     
00918         /*** SP_MB9 - Mailbox Register9; 0xFFFF8009 ***/
00919         union {
00920           byte Byte;
00921         } SP_MB9STR;
00922         #define SP_MB9                  _SP_MB2_dword.Overlap_STR.SP_MB4_wordSTR.Overlap_STR.SP_MB9STR.Byte
00923         
00924       } Overlap_STR;
00925     
00926     } SP_MB4_wordSTR;
00927     #define SP_MB4_word                 _SP_MB2_dword.Overlap_STR.SP_MB4_wordSTR.Word
00928     
00929 
00930     /*** SP_MB5_word - Mailbox Register 5, 16 bit; 0xFFFF800A ***/
00931     union {
00932       word Word;
00933        /* Overlapped registers: */
00934       struct {
00935         /*** SP_MB10 - Mailbox Register10; 0xFFFF800A ***/
00936         union {
00937           byte Byte;
00938         } SP_MB10STR;
00939         #define SP_MB10                 _SP_MB2_dword.Overlap_STR.SP_MB5_wordSTR.Overlap_STR.SP_MB10STR.Byte
00940         
00941     
00942         /*** SP_MB11 - Mailbox Register11; 0xFFFF800B ***/
00943         union {
00944           byte Byte;
00945         } SP_MB11STR;
00946         #define SP_MB11                 _SP_MB2_dword.Overlap_STR.SP_MB5_wordSTR.Overlap_STR.SP_MB11STR.Byte
00947         
00948       } Overlap_STR;
00949     
00950     } SP_MB5_wordSTR;
00951     #define SP_MB5_word                 _SP_MB2_dword.Overlap_STR.SP_MB5_wordSTR.Word
00952     
00953   } Overlap_STR;
00954 
00955 } SP_MB2_dwordSTR;
00956 extern volatile SP_MB2_dwordSTR _SP_MB2_dword @0xFFFF8008;
00957 #define SP_MB2_dword                    _SP_MB2_dword.Dword
00958 
00959 
00960 /*** SP_MB3_dword - Mailbox Register 3, 32 bit; 0xFFFF800C ***/
00961 typedef union {
00962   dword Dword;
00963    /* Overlapped registers: */
00964   struct {
00965     /*** SP_MB6_word - Mailbox Register 6, 16 bit; 0xFFFF800C ***/
00966     union {
00967       word Word;
00968        /* Overlapped registers: */
00969       struct {
00970         /*** SP_MB12 - Mailbox Register12; 0xFFFF800C ***/
00971         union {
00972           byte Byte;
00973         } SP_MB12STR;
00974         #define SP_MB12                 _SP_MB3_dword.Overlap_STR.SP_MB6_wordSTR.Overlap_STR.SP_MB12STR.Byte
00975         
00976     
00977         /*** SP_MB13 - Mailbox Register13; 0xFFFF800D ***/
00978         union {
00979           byte Byte;
00980         } SP_MB13STR;
00981         #define SP_MB13                 _SP_MB3_dword.Overlap_STR.SP_MB6_wordSTR.Overlap_STR.SP_MB13STR.Byte
00982         
00983       } Overlap_STR;
00984     
00985     } SP_MB6_wordSTR;
00986     #define SP_MB6_word                 _SP_MB3_dword.Overlap_STR.SP_MB6_wordSTR.Word
00987     
00988 
00989     /*** SP_MB7_word - Mailbox Register 7, 16 bit; 0xFFFF800E ***/
00990     union {
00991       word Word;
00992        /* Overlapped registers: */
00993       struct {
00994         /*** SP_MB14 - Mailbox Register14; 0xFFFF800E ***/
00995         union {
00996           byte Byte;
00997         } SP_MB14STR;
00998         #define SP_MB14                 _SP_MB3_dword.Overlap_STR.SP_MB7_wordSTR.Overlap_STR.SP_MB14STR.Byte
00999         
01000     
01001         /*** SP_MB15 - Mailbox Register15; 0xFFFF800F ***/
01002         union {
01003           byte Byte;
01004         } SP_MB15STR;
01005         #define SP_MB15                 _SP_MB3_dword.Overlap_STR.SP_MB7_wordSTR.Overlap_STR.SP_MB15STR.Byte
01006         
01007       } Overlap_STR;
01008     
01009     } SP_MB7_wordSTR;
01010     #define SP_MB7_word                 _SP_MB3_dword.Overlap_STR.SP_MB7_wordSTR.Word
01011     
01012   } Overlap_STR;
01013 
01014 } SP_MB3_dwordSTR;
01015 extern volatile SP_MB3_dwordSTR _SP_MB3_dword @0xFFFF800C;
01016 #define SP_MB3_dword                    _SP_MB3_dword.Dword
01017 
01018 
01019 /*** SP_MB4_dword - Mailbox Register 4, 32 bit; 0xFFFF8010 ***/
01020 typedef union {
01021   dword Dword;
01022    /* Overlapped registers: */
01023   struct {
01024     /*** SP_MB8_word - Mailbox Register 8, 16 bit; 0xFFFF8010 ***/
01025     union {
01026       word Word;
01027        /* Overlapped registers: */
01028       struct {
01029         /*** SP_MB16 - Mailbox Register16; 0xFFFF8010 ***/
01030         union {
01031           byte Byte;
01032         } SP_MB16STR;
01033         #define SP_MB16                 _SP_MB4_dword.Overlap_STR.SP_MB8_wordSTR.Overlap_STR.SP_MB16STR.Byte
01034         
01035     
01036         /*** SP_MB17 - Mailbox Register17; 0xFFFF8011 ***/
01037         union {
01038           byte Byte;
01039         } SP_MB17STR;
01040         #define SP_MB17                 _SP_MB4_dword.Overlap_STR.SP_MB8_wordSTR.Overlap_STR.SP_MB17STR.Byte
01041         
01042       } Overlap_STR;
01043     
01044     } SP_MB8_wordSTR;
01045     #define SP_MB8_word                 _SP_MB4_dword.Overlap_STR.SP_MB8_wordSTR.Word
01046     
01047 
01048     /*** SP_MB9_word - Mailbox Register 9, 16 bit; 0xFFFF8012 ***/
01049     union {
01050       word Word;
01051        /* Overlapped registers: */
01052       struct {
01053         /*** SP_MB18 - Mailbox Register18; 0xFFFF8012 ***/
01054         union {
01055           byte Byte;
01056         } SP_MB18STR;
01057         #define SP_MB18                 _SP_MB4_dword.Overlap_STR.SP_MB9_wordSTR.Overlap_STR.SP_MB18STR.Byte
01058         
01059     
01060         /*** SP_MB19 - Mailbox Register19; 0xFFFF8013 ***/
01061         union {
01062           byte Byte;
01063         } SP_MB19STR;
01064         #define SP_MB19                 _SP_MB4_dword.Overlap_STR.SP_MB9_wordSTR.Overlap_STR.SP_MB19STR.Byte
01065         
01066       } Overlap_STR;
01067     
01068     } SP_MB9_wordSTR;
01069     #define SP_MB9_word                 _SP_MB4_dword.Overlap_STR.SP_MB9_wordSTR.Word
01070     
01071   } Overlap_STR;
01072 
01073 } SP_MB4_dwordSTR;
01074 extern volatile SP_MB4_dwordSTR _SP_MB4_dword @0xFFFF8010;
01075 #define SP_MB4_dword                    _SP_MB4_dword.Dword
01076 
01077 
01078 /*** SP_MB5_dword - Mailbox Register 5, 32 bit; 0xFFFF8014 ***/
01079 typedef union {
01080   dword Dword;
01081    /* Overlapped registers: */
01082   struct {
01083     /*** SP_MB10_word - Mailbox Register 10, 16 bit; 0xFFFF8014 ***/
01084     union {
01085       word Word;
01086        /* Overlapped registers: */
01087       struct {
01088         /*** SP_MB20 - Mailbox Register20; 0xFFFF8014 ***/
01089         union {
01090           byte Byte;
01091         } SP_MB20STR;
01092         #define SP_MB20                 _SP_MB5_dword.Overlap_STR.SP_MB10_wordSTR.Overlap_STR.SP_MB20STR.Byte
01093         
01094     
01095         /*** SP_MB21 - Mailbox Register21; 0xFFFF8015 ***/
01096         union {
01097           byte Byte;
01098         } SP_MB21STR;
01099         #define SP_MB21                 _SP_MB5_dword.Overlap_STR.SP_MB10_wordSTR.Overlap_STR.SP_MB21STR.Byte
01100         
01101       } Overlap_STR;
01102     
01103     } SP_MB10_wordSTR;
01104     #define SP_MB10_word                _SP_MB5_dword.Overlap_STR.SP_MB10_wordSTR.Word
01105     
01106 
01107     /*** SP_MB11_word - Mailbox Register 11, 16 bit; 0xFFFF8016 ***/
01108     union {
01109       word Word;
01110        /* Overlapped registers: */
01111       struct {
01112         /*** SP_MB22 - Mailbox Register22; 0xFFFF8016 ***/
01113         union {
01114           byte Byte;
01115         } SP_MB22STR;
01116         #define SP_MB22                 _SP_MB5_dword.Overlap_STR.SP_MB11_wordSTR.Overlap_STR.SP_MB22STR.Byte
01117         
01118     
01119         /*** SP_MB23 - Mailbox Register23; 0xFFFF8017 ***/
01120         union {
01121           byte Byte;
01122         } SP_MB23STR;
01123         #define SP_MB23                 _SP_MB5_dword.Overlap_STR.SP_MB11_wordSTR.Overlap_STR.SP_MB23STR.Byte
01124         
01125       } Overlap_STR;
01126     
01127     } SP_MB11_wordSTR;
01128     #define SP_MB11_word                _SP_MB5_dword.Overlap_STR.SP_MB11_wordSTR.Word
01129     
01130   } Overlap_STR;
01131 
01132 } SP_MB5_dwordSTR;
01133 extern volatile SP_MB5_dwordSTR _SP_MB5_dword @0xFFFF8014;
01134 #define SP_MB5_dword                    _SP_MB5_dword.Dword
01135 
01136 
01137 /*** SP_MB6_dword - Mailbox Register 6, 32 bit; 0xFFFF8018 ***/
01138 typedef union {
01139   dword Dword;
01140    /* Overlapped registers: */
01141   struct {
01142     /*** SP_MB12_word - Mailbox Register 12, 16 bit; 0xFFFF8018 ***/
01143     union {
01144       word Word;
01145        /* Overlapped registers: */
01146       struct {
01147         /*** SP_MB24 - Mailbox Register24; 0xFFFF8018 ***/
01148         union {
01149           byte Byte;
01150         } SP_MB24STR;
01151         #define SP_MB24                 _SP_MB6_dword.Overlap_STR.SP_MB12_wordSTR.Overlap_STR.SP_MB24STR.Byte
01152         
01153     
01154         /*** SP_MB25 - Mailbox Register25; 0xFFFF8019 ***/
01155         union {
01156           byte Byte;
01157         } SP_MB25STR;
01158         #define SP_MB25                 _SP_MB6_dword.Overlap_STR.SP_MB12_wordSTR.Overlap_STR.SP_MB25STR.Byte
01159         
01160       } Overlap_STR;
01161     
01162     } SP_MB12_wordSTR;
01163     #define SP_MB12_word                _SP_MB6_dword.Overlap_STR.SP_MB12_wordSTR.Word
01164     
01165 
01166     /*** SP_MB13_word - Mailbox Register 13, 16 bit; 0xFFFF801A ***/
01167     union {
01168       word Word;
01169        /* Overlapped registers: */
01170       struct {
01171         /*** SP_MB26 - Mailbox Register26; 0xFFFF801A ***/
01172         union {
01173           byte Byte;
01174         } SP_MB26STR;
01175         #define SP_MB26                 _SP_MB6_dword.Overlap_STR.SP_MB13_wordSTR.Overlap_STR.SP_MB26STR.Byte
01176         
01177     
01178         /*** SP_MB27 - Mailbox Register27; 0xFFFF801B ***/
01179         union {
01180           byte Byte;
01181         } SP_MB27STR;
01182         #define SP_MB27                 _SP_MB6_dword.Overlap_STR.SP_MB13_wordSTR.Overlap_STR.SP_MB27STR.Byte
01183         
01184       } Overlap_STR;
01185     
01186     } SP_MB13_wordSTR;
01187     #define SP_MB13_word                _SP_MB6_dword.Overlap_STR.SP_MB13_wordSTR.Word
01188     
01189   } Overlap_STR;
01190 
01191 } SP_MB6_dwordSTR;
01192 extern volatile SP_MB6_dwordSTR _SP_MB6_dword @0xFFFF8018;
01193 #define SP_MB6_dword                    _SP_MB6_dword.Dword
01194 
01195 
01196 /*** SP_MB7_dword - Mailbox Register 7, 32 bit; 0xFFFF801C ***/
01197 typedef union {
01198   dword Dword;
01199    /* Overlapped registers: */
01200   struct {
01201     /*** SP_MB14_word - Mailbox Register 14, 16 bit; 0xFFFF801C ***/
01202     union {
01203       word Word;
01204        /* Overlapped registers: */
01205       struct {
01206         /*** SP_MB28 - Mailbox Register28; 0xFFFF801C ***/
01207         union {
01208           byte Byte;
01209         } SP_MB28STR;
01210         #define SP_MB28                 _SP_MB7_dword.Overlap_STR.SP_MB14_wordSTR.Overlap_STR.SP_MB28STR.Byte
01211         
01212     
01213         /*** SP_MB29 - Mailbox Register29; 0xFFFF801D ***/
01214         union {
01215           byte Byte;
01216         } SP_MB29STR;
01217         #define SP_MB29                 _SP_MB7_dword.Overlap_STR.SP_MB14_wordSTR.Overlap_STR.SP_MB29STR.Byte
01218         
01219       } Overlap_STR;
01220     
01221     } SP_MB14_wordSTR;
01222     #define SP_MB14_word                _SP_MB7_dword.Overlap_STR.SP_MB14_wordSTR.Word
01223     
01224 
01225     /*** SP_MB15_word - Mailbox Register 15, 16 bit; 0xFFFF801E ***/
01226     union {
01227       word Word;
01228        /* Overlapped registers: */
01229       struct {
01230         /*** SP_MB30 - Mailbox Register30; 0xFFFF801E ***/
01231         union {
01232           byte Byte;
01233         } SP_MB30STR;
01234         #define SP_MB30                 _SP_MB7_dword.Overlap_STR.SP_MB15_wordSTR.Overlap_STR.SP_MB30STR.Byte
01235         
01236     
01237         /*** SP_MB31 - Mailbox Register31; 0xFFFF801F ***/
01238         union {
01239           byte Byte;
01240         } SP_MB31STR;
01241         #define SP_MB31                 _SP_MB7_dword.Overlap_STR.SP_MB15_wordSTR.Overlap_STR.SP_MB31STR.Byte
01242         
01243       } Overlap_STR;
01244     
01245     } SP_MB15_wordSTR;
01246     #define SP_MB15_word                _SP_MB7_dword.Overlap_STR.SP_MB15_wordSTR.Word
01247     
01248   } Overlap_STR;
01249 
01250 } SP_MB7_dwordSTR;
01251 extern volatile SP_MB7_dwordSTR _SP_MB7_dword @0xFFFF801C;
01252 #define SP_MB7_dword                    _SP_MB7_dword.Dword
01253 
01254 
01255 /*** SP_MUTEX0 - Binary Semaphore (Mutex) Register 0; 0xFFFF8020 ***/
01256 typedef union {
01257   byte Byte;
01258   struct {
01259     byte SSTS0       :1;                                       /* SSTS Semaphore Status, bit 0 */
01260     byte SSTS1       :1;                                       /* SSTS Semaphore Status, bit 1 */
01261     byte             :1; 
01262     byte             :1; 
01263     byte             :1; 
01264     byte             :1; 
01265     byte             :1; 
01266     byte             :1; 
01267   } Bits;
01268   struct {
01269     byte grpSSTS :2;
01270     byte         :1;
01271     byte         :1;
01272     byte         :1;
01273     byte         :1;
01274     byte         :1;
01275     byte         :1;
01276   } MergedBits;
01277 } SP_MUTEX0STR;
01278 extern volatile SP_MUTEX0STR _SP_MUTEX0 @0xFFFF8020;
01279 #define SP_MUTEX0                       _SP_MUTEX0.Byte
01280 #define SP_MUTEX0_SSTS0                 _SP_MUTEX0.Bits.SSTS0
01281 #define SP_MUTEX0_SSTS1                 _SP_MUTEX0.Bits.SSTS1
01282 /* SP_MUTEX_ARR: Access 2 SP_MUTEXx registers in an array */
01283 #define SP_MUTEX_ARR                    ((volatile byte *) &SP_MUTEX0)
01284 #define SP_MUTEX0_SSTS                  _SP_MUTEX0.MergedBits.grpSSTS
01285 
01286 #define SP_MUTEX0_SSTS0_MASK            1U
01287 #define SP_MUTEX0_SSTS1_MASK            2U
01288 #define SP_MUTEX0_SSTS_MASK             3U
01289 #define SP_MUTEX0_SSTS_BITNUM           0U
01290 
01291 
01292 /*** SP_MUTEX1 - Binary Semaphore (Mutex) Register 1; 0xFFFF8021 ***/
01293 typedef union {
01294   byte Byte;
01295   struct {
01296     byte SSTS0       :1;                                       /* SSTS Semaphore Status, bit 0 */
01297     byte SSTS1       :1;                                       /* SSTS Semaphore Status, bit 1 */
01298     byte             :1; 
01299     byte             :1; 
01300     byte             :1; 
01301     byte             :1; 
01302     byte             :1; 
01303     byte             :1; 
01304   } Bits;
01305   struct {
01306     byte grpSSTS :2;
01307     byte         :1;
01308     byte         :1;
01309     byte         :1;
01310     byte         :1;
01311     byte         :1;
01312     byte         :1;
01313   } MergedBits;
01314 } SP_MUTEX1STR;
01315 extern volatile SP_MUTEX1STR _SP_MUTEX1 @0xFFFF8021;
01316 #define SP_MUTEX1                       _SP_MUTEX1.Byte
01317 #define SP_MUTEX1_SSTS0                 _SP_MUTEX1.Bits.SSTS0
01318 #define SP_MUTEX1_SSTS1                 _SP_MUTEX1.Bits.SSTS1
01319 #define SP_MUTEX1_SSTS                  _SP_MUTEX1.MergedBits.grpSSTS
01320 
01321 #define SP_MUTEX1_SSTS0_MASK            1U
01322 #define SP_MUTEX1_SSTS1_MASK            2U
01323 #define SP_MUTEX1_SSTS_MASK             3U
01324 #define SP_MUTEX1_SSTS_BITNUM           0U
01325 
01326 
01327 /*** SP_ADDR - Slave I2C Address Register; 0xFFFF8022 ***/
01328 typedef union {
01329   byte Byte;
01330   struct {
01331     byte ADDR        :7;                                       /* Slave I2C Address, bit 0 */
01332     byte             :1; 
01333   } Bits;
01334 } SP_ADDRSTR;
01335 extern volatile SP_ADDRSTR _SP_ADDR @0xFFFF8022;
01336 #define SP_ADDR                         _SP_ADDR.Byte
01337 #define SP_ADDR_ADDR                    _SP_ADDR.Bits.ADDR
01338 
01339 #define SP_ADDR_ADDR_MASK               127U
01340 #define SP_ADDR_ADDR_BITNUM             0U
01341 
01342 
01343 /*** SP_SCR - Slave Port Status and Control Register; 0xFFFF8023 ***/
01344 typedef union {
01345   byte Byte;
01346   struct {
01347     byte WUP0        :1;                                       /* Wakeup Configuration, bit 0 */
01348     byte WUP1        :1;                                       /* Wakeup Configuration, bit 1 */
01349     byte WIE         :1;                                       /* Write Interrupt Enable */
01350     byte RIE         :1;                                       /* Read Interrupt Enable */
01351     byte STOP_EN     :1;                                       /* Interrupt STOP Enable */
01352     byte ACTIVE_CSR  :1;                                       /* Slave port is active / Clear Read and Write Status Registers */
01353     byte PS          :1;                                       /* Port Select */
01354     byte EN          :1;                                       /* Slave Port Enable */
01355   } Bits;
01356   struct {
01357     byte grpWUP  :2;
01358     byte         :1;
01359     byte         :1;
01360     byte         :1;
01361     byte         :1;
01362     byte         :1;
01363     byte         :1;
01364   } MergedBits;
01365 } SP_SCRSTR;
01366 extern volatile SP_SCRSTR _SP_SCR @0xFFFF8023;
01367 #define SP_SCR                          _SP_SCR.Byte
01368 #define SP_SCR_WUP0                     _SP_SCR.Bits.WUP0
01369 #define SP_SCR_WUP1                     _SP_SCR.Bits.WUP1
01370 #define SP_SCR_WIE                      _SP_SCR.Bits.WIE
01371 #define SP_SCR_RIE                      _SP_SCR.Bits.RIE
01372 #define SP_SCR_STOP_EN                  _SP_SCR.Bits.STOP_EN
01373 #define SP_SCR_ACTIVE_CSR               _SP_SCR.Bits.ACTIVE_CSR
01374 #define SP_SCR_PS                       _SP_SCR.Bits.PS
01375 #define SP_SCR_EN                       _SP_SCR.Bits.EN
01376 #define SP_SCR_WUP                      _SP_SCR.MergedBits.grpWUP
01377 
01378 #define SP_SCR_WUP0_MASK                1U
01379 #define SP_SCR_WUP1_MASK                2U
01380 #define SP_SCR_WIE_MASK                 4U
01381 #define SP_SCR_RIE_MASK                 8U
01382 #define SP_SCR_STOP_EN_MASK             16U
01383 #define SP_SCR_ACTIVE_CSR_MASK          32U
01384 #define SP_SCR_PS_MASK                  64U
01385 #define SP_SCR_EN_MASK                  128U
01386 #define SP_SCR_WUP_MASK                 3U
01387 #define SP_SCR_WUP_BITNUM               0U
01388 
01389 
01390 /*** SP_WSTS0 - Write Status Register 0; 0xFFFF8024 ***/
01391 typedef union {
01392   byte Byte;
01393   struct {
01394     byte D24         :1;                                       /* SP_MB24 write status */
01395     byte D25         :1;                                       /* SP_MB25 write status */
01396     byte D26         :1;                                       /* SP_MB26 write status */
01397     byte D27         :1;                                       /* SP_MB27 write status */
01398     byte D28         :1;                                       /* SP_MB28 write status */
01399     byte D29         :1;                                       /* SP_MB29 write status */
01400     byte D30         :1;                                       /* SP_MB30 write status */
01401     byte D31         :1;                                       /* SP_MB31 write status */
01402   } Bits;
01403 } SP_WSTS0STR;
01404 extern volatile SP_WSTS0STR _SP_WSTS0 @0xFFFF8024;
01405 #define SP_WSTS0                        _SP_WSTS0.Byte
01406 #define SP_WSTS0_D24                    _SP_WSTS0.Bits.D24
01407 #define SP_WSTS0_D25                    _SP_WSTS0.Bits.D25
01408 #define SP_WSTS0_D26                    _SP_WSTS0.Bits.D26
01409 #define SP_WSTS0_D27                    _SP_WSTS0.Bits.D27
01410 #define SP_WSTS0_D28                    _SP_WSTS0.Bits.D28
01411 #define SP_WSTS0_D29                    _SP_WSTS0.Bits.D29
01412 #define SP_WSTS0_D30                    _SP_WSTS0.Bits.D30
01413 #define SP_WSTS0_D31                    _SP_WSTS0.Bits.D31
01414 /* SP_WSTS_ARR: Access 4 SP_WSTSx registers in an array */
01415 #define SP_WSTS_ARR                     ((volatile byte *) &SP_WSTS0)
01416 
01417 #define SP_WSTS0_D24_MASK               1U
01418 #define SP_WSTS0_D25_MASK               2U
01419 #define SP_WSTS0_D26_MASK               4U
01420 #define SP_WSTS0_D27_MASK               8U
01421 #define SP_WSTS0_D28_MASK               16U
01422 #define SP_WSTS0_D29_MASK               32U
01423 #define SP_WSTS0_D30_MASK               64U
01424 #define SP_WSTS0_D31_MASK               128U
01425 
01426 
01427 /*** SP_WSTS1 - Write Status Register 1; 0xFFFF8025 ***/
01428 typedef union {
01429   byte Byte;
01430   struct {
01431     byte D16         :1;                                       /* SP_MB16 write status */
01432     byte D17         :1;                                       /* SP_MB17 write status */
01433     byte D18         :1;                                       /* SP_MB18 write status */
01434     byte D19         :1;                                       /* SP_MB19 write status */
01435     byte D20         :1;                                       /* SP_MB20 write status */
01436     byte D21         :1;                                       /* SP_MB21 write status */
01437     byte D22         :1;                                       /* SP_MB22 write status */
01438     byte D23         :1;                                       /* SP_MB23 write status */
01439   } Bits;
01440 } SP_WSTS1STR;
01441 extern volatile SP_WSTS1STR _SP_WSTS1 @0xFFFF8025;
01442 #define SP_WSTS1                        _SP_WSTS1.Byte
01443 #define SP_WSTS1_D16                    _SP_WSTS1.Bits.D16
01444 #define SP_WSTS1_D17                    _SP_WSTS1.Bits.D17
01445 #define SP_WSTS1_D18                    _SP_WSTS1.Bits.D18
01446 #define SP_WSTS1_D19                    _SP_WSTS1.Bits.D19
01447 #define SP_WSTS1_D20                    _SP_WSTS1.Bits.D20
01448 #define SP_WSTS1_D21                    _SP_WSTS1.Bits.D21
01449 #define SP_WSTS1_D22                    _SP_WSTS1.Bits.D22
01450 #define SP_WSTS1_D23                    _SP_WSTS1.Bits.D23
01451 
01452 #define SP_WSTS1_D16_MASK               1U
01453 #define SP_WSTS1_D17_MASK               2U
01454 #define SP_WSTS1_D18_MASK               4U
01455 #define SP_WSTS1_D19_MASK               8U
01456 #define SP_WSTS1_D20_MASK               16U
01457 #define SP_WSTS1_D21_MASK               32U
01458 #define SP_WSTS1_D22_MASK               64U
01459 #define SP_WSTS1_D23_MASK               128U
01460 
01461 
01462 /*** SP_WSTS2 - Write Status Register 2; 0xFFFF8026 ***/
01463 typedef union {
01464   byte Byte;
01465   struct {
01466     byte D8          :1;                                       /* SP_MB8 write status */
01467     byte D9          :1;                                       /* SP_MB9 write status */
01468     byte D10         :1;                                       /* SP_MB10 write status */
01469     byte D11         :1;                                       /* SP_MB11 write status */
01470     byte D12         :1;                                       /* SP_MB12 write status */
01471     byte D13         :1;                                       /* SP_MB13 write status */
01472     byte D14         :1;                                       /* SP_MB14 write status */
01473     byte D15         :1;                                       /* SP_MB15 write status */
01474   } Bits;
01475 } SP_WSTS2STR;
01476 extern volatile SP_WSTS2STR _SP_WSTS2 @0xFFFF8026;
01477 #define SP_WSTS2                        _SP_WSTS2.Byte
01478 #define SP_WSTS2_D8                     _SP_WSTS2.Bits.D8
01479 #define SP_WSTS2_D9                     _SP_WSTS2.Bits.D9
01480 #define SP_WSTS2_D10                    _SP_WSTS2.Bits.D10
01481 #define SP_WSTS2_D11                    _SP_WSTS2.Bits.D11
01482 #define SP_WSTS2_D12                    _SP_WSTS2.Bits.D12
01483 #define SP_WSTS2_D13                    _SP_WSTS2.Bits.D13
01484 #define SP_WSTS2_D14                    _SP_WSTS2.Bits.D14
01485 #define SP_WSTS2_D15                    _SP_WSTS2.Bits.D15
01486 
01487 #define SP_WSTS2_D8_MASK                1U
01488 #define SP_WSTS2_D9_MASK                2U
01489 #define SP_WSTS2_D10_MASK               4U
01490 #define SP_WSTS2_D11_MASK               8U
01491 #define SP_WSTS2_D12_MASK               16U
01492 #define SP_WSTS2_D13_MASK               32U
01493 #define SP_WSTS2_D14_MASK               64U
01494 #define SP_WSTS2_D15_MASK               128U
01495 
01496 
01497 /*** SP_WSTS3 - Write Status Register 3; 0xFFFF8027 ***/
01498 typedef union {
01499   byte Byte;
01500   struct {
01501     byte D0          :1;                                       /* SP_MB0 write status */
01502     byte D1          :1;                                       /* SP_MB1 write status */
01503     byte D2          :1;                                       /* SP_MB2 write status */
01504     byte D3          :1;                                       /* SP_MB3 write status */
01505     byte D4          :1;                                       /* SP_MB4 write status */
01506     byte D5          :1;                                       /* SP_MB5 write status */
01507     byte D6          :1;                                       /* SP_MB6 write status */
01508     byte D7          :1;                                       /* SP_MB7 write status */
01509   } Bits;
01510 } SP_WSTS3STR;
01511 extern volatile SP_WSTS3STR _SP_WSTS3 @0xFFFF8027;
01512 #define SP_WSTS3                        _SP_WSTS3.Byte
01513 #define SP_WSTS3_D0                     _SP_WSTS3.Bits.D0
01514 #define SP_WSTS3_D1                     _SP_WSTS3.Bits.D1
01515 #define SP_WSTS3_D2                     _SP_WSTS3.Bits.D2
01516 #define SP_WSTS3_D3                     _SP_WSTS3.Bits.D3
01517 #define SP_WSTS3_D4                     _SP_WSTS3.Bits.D4
01518 #define SP_WSTS3_D5                     _SP_WSTS3.Bits.D5
01519 #define SP_WSTS3_D6                     _SP_WSTS3.Bits.D6
01520 #define SP_WSTS3_D7                     _SP_WSTS3.Bits.D7
01521 
01522 #define SP_WSTS3_D0_MASK                1U
01523 #define SP_WSTS3_D1_MASK                2U
01524 #define SP_WSTS3_D2_MASK                4U
01525 #define SP_WSTS3_D3_MASK                8U
01526 #define SP_WSTS3_D4_MASK                16U
01527 #define SP_WSTS3_D5_MASK                32U
01528 #define SP_WSTS3_D6_MASK                64U
01529 #define SP_WSTS3_D7_MASK                128U
01530 
01531 
01532 /*** SP_RSTS0 - Read Status Register 0; 0xFFFF8028 ***/
01533 typedef union {
01534   byte Byte;
01535   struct {
01536     byte D24         :1;                                       /* SP_MB24 read status */
01537     byte D25         :1;                                       /* SP_MB25 read status */
01538     byte D26         :1;                                       /* SP_MB26 read status */
01539     byte D27         :1;                                       /* SP_MB27 read status */
01540     byte D28         :1;                                       /* SP_MB28 read status */
01541     byte D29         :1;                                       /* SP_MB29 read status */
01542     byte D30         :1;                                       /* SP_MB30 read status */
01543     byte D31         :1;                                       /* SP_MB31 read status */
01544   } Bits;
01545 } SP_RSTS0STR;
01546 extern volatile SP_RSTS0STR _SP_RSTS0 @0xFFFF8028;
01547 #define SP_RSTS0                        _SP_RSTS0.Byte
01548 #define SP_RSTS0_D24                    _SP_RSTS0.Bits.D24
01549 #define SP_RSTS0_D25                    _SP_RSTS0.Bits.D25
01550 #define SP_RSTS0_D26                    _SP_RSTS0.Bits.D26
01551 #define SP_RSTS0_D27                    _SP_RSTS0.Bits.D27
01552 #define SP_RSTS0_D28                    _SP_RSTS0.Bits.D28
01553 #define SP_RSTS0_D29                    _SP_RSTS0.Bits.D29
01554 #define SP_RSTS0_D30                    _SP_RSTS0.Bits.D30
01555 #define SP_RSTS0_D31                    _SP_RSTS0.Bits.D31
01556 /* SP_RSTS_ARR: Access 4 SP_RSTSx registers in an array */
01557 #define SP_RSTS_ARR                     ((volatile byte *) &SP_RSTS0)
01558 
01559 #define SP_RSTS0_D24_MASK               1U
01560 #define SP_RSTS0_D25_MASK               2U
01561 #define SP_RSTS0_D26_MASK               4U
01562 #define SP_RSTS0_D27_MASK               8U
01563 #define SP_RSTS0_D28_MASK               16U
01564 #define SP_RSTS0_D29_MASK               32U
01565 #define SP_RSTS0_D30_MASK               64U
01566 #define SP_RSTS0_D31_MASK               128U
01567 
01568 
01569 /*** SP_RSTS1 - Read Status Register 1; 0xFFFF8029 ***/
01570 typedef union {
01571   byte Byte;
01572   struct {
01573     byte D16         :1;                                       /* SP_MB16 read status */
01574     byte D17         :1;                                       /* SP_MB17 read status */
01575     byte D18         :1;                                       /* SP_MB18 read status */
01576     byte D19         :1;                                       /* SP_MB19 read status */
01577     byte D20         :1;                                       /* SP_MB20 read status */
01578     byte D21         :1;                                       /* SP_MB21 read status */
01579     byte D22         :1;                                       /* SP_MB22 read status */
01580     byte D23         :1;                                       /* SP_MB23 read status */
01581   } Bits;
01582 } SP_RSTS1STR;
01583 extern volatile SP_RSTS1STR _SP_RSTS1 @0xFFFF8029;
01584 #define SP_RSTS1                        _SP_RSTS1.Byte
01585 #define SP_RSTS1_D16                    _SP_RSTS1.Bits.D16
01586 #define SP_RSTS1_D17                    _SP_RSTS1.Bits.D17
01587 #define SP_RSTS1_D18                    _SP_RSTS1.Bits.D18
01588 #define SP_RSTS1_D19                    _SP_RSTS1.Bits.D19
01589 #define SP_RSTS1_D20                    _SP_RSTS1.Bits.D20
01590 #define SP_RSTS1_D21                    _SP_RSTS1.Bits.D21
01591 #define SP_RSTS1_D22                    _SP_RSTS1.Bits.D22
01592 #define SP_RSTS1_D23                    _SP_RSTS1.Bits.D23
01593 
01594 #define SP_RSTS1_D16_MASK               1U
01595 #define SP_RSTS1_D17_MASK               2U
01596 #define SP_RSTS1_D18_MASK               4U
01597 #define SP_RSTS1_D19_MASK               8U
01598 #define SP_RSTS1_D20_MASK               16U
01599 #define SP_RSTS1_D21_MASK               32U
01600 #define SP_RSTS1_D22_MASK               64U
01601 #define SP_RSTS1_D23_MASK               128U
01602 
01603 
01604 /*** SP_RSTS2 - Read Status Register 2; 0xFFFF802A ***/
01605 typedef union {
01606   byte Byte;
01607   struct {
01608     byte D8          :1;                                       /* SP_MB8 read status */
01609     byte D9          :1;                                       /* SP_MB9 read status */
01610     byte D10         :1;                                       /* SP_MB10 read status */
01611     byte D11         :1;                                       /* SP_MB11 read status */
01612     byte D12         :1;                                       /* SP_MB12 read status */
01613     byte D13         :1;                                       /* SP_MB13 read status */
01614     byte D14         :1;                                       /* SP_MB14 read status */
01615     byte D15         :1;                                       /* SP_MB15 read status */
01616   } Bits;
01617 } SP_RSTS2STR;
01618 extern volatile SP_RSTS2STR _SP_RSTS2 @0xFFFF802A;
01619 #define SP_RSTS2                        _SP_RSTS2.Byte
01620 #define SP_RSTS2_D8                     _SP_RSTS2.Bits.D8
01621 #define SP_RSTS2_D9                     _SP_RSTS2.Bits.D9
01622 #define SP_RSTS2_D10                    _SP_RSTS2.Bits.D10
01623 #define SP_RSTS2_D11                    _SP_RSTS2.Bits.D11
01624 #define SP_RSTS2_D12                    _SP_RSTS2.Bits.D12
01625 #define SP_RSTS2_D13                    _SP_RSTS2.Bits.D13
01626 #define SP_RSTS2_D14                    _SP_RSTS2.Bits.D14
01627 #define SP_RSTS2_D15                    _SP_RSTS2.Bits.D15
01628 
01629 #define SP_RSTS2_D8_MASK                1U
01630 #define SP_RSTS2_D9_MASK                2U
01631 #define SP_RSTS2_D10_MASK               4U
01632 #define SP_RSTS2_D11_MASK               8U
01633 #define SP_RSTS2_D12_MASK               16U
01634 #define SP_RSTS2_D13_MASK               32U
01635 #define SP_RSTS2_D14_MASK               64U
01636 #define SP_RSTS2_D15_MASK               128U
01637 
01638 
01639 /*** SP_RSTS3 - Read Status Register 3; 0xFFFF802B ***/
01640 typedef union {
01641   byte Byte;
01642   struct {
01643     byte D0          :1;                                       /* SP_MB0 read status */
01644     byte D1          :1;                                       /* SP_MB1 read status */
01645     byte D2          :1;                                       /* SP_MB2 read status */
01646     byte D3          :1;                                       /* SP_MB3 read status */
01647     byte D4          :1;                                       /* SP_MB4 read status */
01648     byte D5          :1;                                       /* SP_MB5 read status */
01649     byte D6          :1;                                       /* SP_MB6 read status */
01650     byte D7          :1;                                       /* SP_MB7 read status */
01651   } Bits;
01652 } SP_RSTS3STR;
01653 extern volatile SP_RSTS3STR _SP_RSTS3 @0xFFFF802B;
01654 #define SP_RSTS3                        _SP_RSTS3.Byte
01655 #define SP_RSTS3_D0                     _SP_RSTS3.Bits.D0
01656 #define SP_RSTS3_D1                     _SP_RSTS3.Bits.D1
01657 #define SP_RSTS3_D2                     _SP_RSTS3.Bits.D2
01658 #define SP_RSTS3_D3                     _SP_RSTS3.Bits.D3
01659 #define SP_RSTS3_D4                     _SP_RSTS3.Bits.D4
01660 #define SP_RSTS3_D5                     _SP_RSTS3.Bits.D5
01661 #define SP_RSTS3_D6                     _SP_RSTS3.Bits.D6
01662 #define SP_RSTS3_D7                     _SP_RSTS3.Bits.D7
01663 
01664 #define SP_RSTS3_D0_MASK                1U
01665 #define SP_RSTS3_D1_MASK                2U
01666 #define SP_RSTS3_D2_MASK                4U
01667 #define SP_RSTS3_D3_MASK                8U
01668 #define SP_RSTS3_D4_MASK                16U
01669 #define SP_RSTS3_D5_MASK                32U
01670 #define SP_RSTS3_D6_MASK                64U
01671 #define SP_RSTS3_D7_MASK                128U
01672 
01673 
01674 /*** SP_MTOR0 - Mutext Timeout Register 0; 0xFFFF802C ***/
01675 typedef union {
01676   byte Byte;
01677   struct {
01678     byte MTE         :5;                                       /* Mutext Timeout Exponent, bit 0 */
01679     byte EN          :1;                                       /* Mutext Timeout Enable */
01680     byte TOSTS       :1;                                       /* Mutext Timeout Status */
01681     byte             :1; 
01682   } Bits;
01683 } SP_MTOR0STR;
01684 extern volatile SP_MTOR0STR _SP_MTOR0 @0xFFFF802C;
01685 #define SP_MTOR0                        _SP_MTOR0.Byte
01686 #define SP_MTOR0_MTE                    _SP_MTOR0.Bits.MTE
01687 #define SP_MTOR0_EN                     _SP_MTOR0.Bits.EN
01688 #define SP_MTOR0_TOSTS                  _SP_MTOR0.Bits.TOSTS
01689 /* SP_MTOR_ARR: Access 2 SP_MTORx registers in an array */
01690 #define SP_MTOR_ARR                     ((volatile byte *) &SP_MTOR0)
01691 
01692 #define SP_MTOR0_MTE_MASK               31U
01693 #define SP_MTOR0_MTE_BITNUM             0U
01694 #define SP_MTOR0_EN_MASK                32U
01695 #define SP_MTOR0_TOSTS_MASK             64U
01696 
01697 
01698 /*** SP_MTOR1 - Mutext Timeout Register 1; 0xFFFF802D ***/
01699 typedef union {
01700   byte Byte;
01701   struct {
01702     byte MTE         :5;                                       /* Mutext Timeout Exponent, bit 0 */
01703     byte EN          :1;                                       /* Mutext Timeout Enable */
01704     byte TOSTS       :1;                                       /* Mutext Timeout Status */
01705     byte             :1; 
01706   } Bits;
01707 } SP_MTOR1STR;
01708 extern volatile SP_MTOR1STR _SP_MTOR1 @0xFFFF802D;
01709 #define SP_MTOR1                        _SP_MTOR1.Byte
01710 #define SP_MTOR1_MTE                    _SP_MTOR1.Bits.MTE
01711 #define SP_MTOR1_EN                     _SP_MTOR1.Bits.EN
01712 #define SP_MTOR1_TOSTS                  _SP_MTOR1.Bits.TOSTS
01713 
01714 #define SP_MTOR1_MTE_MASK               31U
01715 #define SP_MTOR1_MTE_BITNUM             0U
01716 #define SP_MTOR1_EN_MASK                32U
01717 #define SP_MTOR1_TOSTS_MASK             64U
01718 
01719 
01720 /*** SP_OIC - Slave Port Output Interrupt (INT_O) Control Register; 0xFFFF802E ***/
01721 typedef union {
01722   byte Byte;
01723   struct {
01724     byte SET_INT_O   :1;                                       /* Set / Assert / Current value of INT_O function */
01725     byte CLR         :1;                                       /* Clear / De-Assert */
01726     byte POL         :1;                                       /* Output Polarity */
01727     byte             :1; 
01728     byte             :1; 
01729     byte             :1; 
01730     byte             :1; 
01731     byte             :1; 
01732   } Bits;
01733 } SP_OICSTR;
01734 extern volatile SP_OICSTR _SP_OIC @0xFFFF802E;
01735 #define SP_OIC                          _SP_OIC.Byte
01736 #define SP_OIC_SET_INT_O                _SP_OIC.Bits.SET_INT_O
01737 #define SP_OIC_CLR                      _SP_OIC.Bits.CLR
01738 #define SP_OIC_POL                      _SP_OIC.Bits.POL
01739 
01740 #define SP_OIC_SET_INT_O_MASK           1U
01741 #define SP_OIC_CLR_MASK                 2U
01742 #define SP_OIC_POL_MASK                 4U
01743 
01744 
01745 /*** IICA1 - IIC Address Register; 0xFFFF8040 ***/
01746 typedef union {
01747   byte Byte;
01748   union { /* Several registers at the same address */
01749     /*** IICA1 - IIC Address Register; Several registers at the same address ***/
01750     union {
01751       struct {
01752         byte             :1; 
01753         byte AD1         :1;                                       /* Slave Address Bit 1 */
01754         byte AD2         :1;                                       /* Slave Address Bit 2 */
01755         byte AD3         :1;                                       /* Slave Address Bit 3 */
01756         byte AD4         :1;                                       /* Slave Address Bit 4 */
01757         byte AD5         :1;                                       /* Slave Address Bit 5 */
01758         byte AD6         :1;                                       /* Slave Address Bit 6 */
01759         byte AD7         :1;                                       /* Slave Address Bit 7 */
01760       } Bits;
01761       struct {
01762         byte     :1;
01763         byte grpAD_1 :7;
01764       } MergedBits;
01765     } IICA1STR;
01766     #define IICA1                       _IICA1.Byte
01767     #define IICA1_AD1                   _IICA1.SameAddr_STR.IICA1STR.Bits.AD1
01768     #define IICA1_AD2                   _IICA1.SameAddr_STR.IICA1STR.Bits.AD2
01769     #define IICA1_AD3                   _IICA1.SameAddr_STR.IICA1STR.Bits.AD3
01770     #define IICA1_AD4                   _IICA1.SameAddr_STR.IICA1STR.Bits.AD4
01771     #define IICA1_AD5                   _IICA1.SameAddr_STR.IICA1STR.Bits.AD5
01772     #define IICA1_AD6                   _IICA1.SameAddr_STR.IICA1STR.Bits.AD6
01773     #define IICA1_AD7                   _IICA1.SameAddr_STR.IICA1STR.Bits.AD7
01774     #define IICA1_AD_1                  _IICA1.SameAddr_STR.IICA1STR.MergedBits.grpAD_1
01775     #define IICA1_AD                    IICA1_AD_1
01776     
01777     #define IICA1_AD1_MASK              2U
01778     #define IICA1_AD2_MASK              4U
01779     #define IICA1_AD3_MASK              8U
01780     #define IICA1_AD4_MASK              16U
01781     #define IICA1_AD5_MASK              32U
01782     #define IICA1_AD6_MASK              64U
01783     #define IICA1_AD7_MASK              128U
01784     #define IICA1_AD_1_MASK             254U
01785     #define IICA1_AD_1_BITNUM           1U
01786     
01787     /*** IICA - IIC Address Register; Several registers at the same address ***/
01788     union {
01789       struct {
01790         byte             :1; 
01791         byte AD1         :1;                                       /* Slave Address Bit 1 */
01792         byte AD2         :1;                                       /* Slave Address Bit 2 */
01793         byte AD3         :1;                                       /* Slave Address Bit 3 */
01794         byte AD4         :1;                                       /* Slave Address Bit 4 */
01795         byte AD5         :1;                                       /* Slave Address Bit 5 */
01796         byte AD6         :1;                                       /* Slave Address Bit 6 */
01797         byte AD7         :1;                                       /* Slave Address Bit 7 */
01798       } Bits;
01799       struct {
01800         byte     :1;
01801         byte grpAD_1 :7;
01802       } MergedBits;
01803     } IICASTR;
01804     #define IICA                        _IICA1.Byte
01805     #define IICA_AD1                    _IICA1.SameAddr_STR.IICASTR.Bits.AD1
01806     #define IICA_AD2                    _IICA1.SameAddr_STR.IICASTR.Bits.AD2
01807     #define IICA_AD3                    _IICA1.SameAddr_STR.IICASTR.Bits.AD3
01808     #define IICA_AD4                    _IICA1.SameAddr_STR.IICASTR.Bits.AD4
01809     #define IICA_AD5                    _IICA1.SameAddr_STR.IICASTR.Bits.AD5
01810     #define IICA_AD6                    _IICA1.SameAddr_STR.IICASTR.Bits.AD6
01811     #define IICA_AD7                    _IICA1.SameAddr_STR.IICASTR.Bits.AD7
01812     #define IICA_AD_1                   _IICA1.SameAddr_STR.IICASTR.MergedBits.grpAD_1
01813     #define IICA_AD                     IICA_AD_1
01814     
01815     #define IICA_AD1_MASK               2U
01816     #define IICA_AD2_MASK               4U
01817     #define IICA_AD3_MASK               8U
01818     #define IICA_AD4_MASK               16U
01819     #define IICA_AD5_MASK               32U
01820     #define IICA_AD6_MASK               64U
01821     #define IICA_AD7_MASK               128U
01822     #define IICA_AD_1_MASK              254U
01823     #define IICA_AD_1_BITNUM            1U
01824     
01825   } SameAddr_STR; /*Several registers at the same address */
01826 
01827 } IICA1STR;
01828 extern volatile IICA1STR _IICA1 @0xFFFF8040;
01829 
01830 
01831 /*** IICF - IIC Frequency Divider Register; 0xFFFF8041 ***/
01832 typedef union {
01833   byte Byte;
01834   struct {
01835     byte ICR0        :1;                                       /* IIC Clock Rate Bit 0 */
01836     byte ICR1        :1;                                       /* IIC Clock Rate Bit 1 */
01837     byte ICR2        :1;                                       /* IIC Clock Rate Bit 2 */
01838     byte ICR3        :1;                                       /* IIC Clock Rate Bit 3 */
01839     byte ICR4        :1;                                       /* IIC Clock Rate Bit 4 */
01840     byte ICR5        :1;                                       /* IIC Clock Rate Bit 5 */
01841     byte MULT0       :1;                                       /* Multiplier Factor Bit 0 */
01842     byte MULT1       :1;                                       /* Multiplier Factor Bit 1 */
01843   } Bits;
01844   struct {
01845     byte grpICR  :6;
01846     byte grpMULT :2;
01847   } MergedBits;
01848 } IICFSTR;
01849 extern volatile IICFSTR _IICF @0xFFFF8041;
01850 #define IICF                            _IICF.Byte
01851 #define IICF_ICR0                       _IICF.Bits.ICR0
01852 #define IICF_ICR1                       _IICF.Bits.ICR1
01853 #define IICF_ICR2                       _IICF.Bits.ICR2
01854 #define IICF_ICR3                       _IICF.Bits.ICR3
01855 #define IICF_ICR4                       _IICF.Bits.ICR4
01856 #define IICF_ICR5                       _IICF.Bits.ICR5
01857 #define IICF_MULT0                      _IICF.Bits.MULT0
01858 #define IICF_MULT1                      _IICF.Bits.MULT1
01859 #define IICF_ICR                        _IICF.MergedBits.grpICR
01860 #define IICF_MULT                       _IICF.MergedBits.grpMULT
01861 
01862 #define IICF_ICR0_MASK                  1U
01863 #define IICF_ICR1_MASK                  2U
01864 #define IICF_ICR2_MASK                  4U
01865 #define IICF_ICR3_MASK                  8U
01866 #define IICF_ICR4_MASK                  16U
01867 #define IICF_ICR5_MASK                  32U
01868 #define IICF_MULT0_MASK                 64U
01869 #define IICF_MULT1_MASK                 128U
01870 #define IICF_ICR_MASK                   63U
01871 #define IICF_ICR_BITNUM                 0U
01872 #define IICF_MULT_MASK                  192U
01873 #define IICF_MULT_BITNUM                6U
01874 
01875 
01876 /*** IICC1 - IIC Control Register 1; 0xFFFF8042 ***/
01877 typedef union {
01878   byte Byte;
01879   union { /* Several registers at the same address */
01880     /*** IICC1 - IIC Control Register 1; Several registers at the same address ***/
01881     union {
01882       struct {
01883         byte             :1; 
01884         byte WUEN        :1;                                       /* Wake-up Enable */
01885         byte RSTA        :1;                                       /* Repeat START */
01886         byte TXAK        :1;                                       /* Transmit Acknowledge Enable */
01887         byte TX          :1;                                       /* Transmit Mode Select */
01888         byte MST         :1;                                       /* Master Mode Select */
01889         byte IICIE       :1;                                       /* IIC Interrupt Enable */
01890         byte IICEN       :1;                                       /* IIC Enable */
01891       } Bits;
01892     } IICC1STR;
01893     #define IICC1                       _IICC1.Byte
01894     #define IICC1_WUEN                  _IICC1.SameAddr_STR.IICC1STR.Bits.WUEN
01895     #define IICC1_RSTA                  _IICC1.SameAddr_STR.IICC1STR.Bits.RSTA
01896     #define IICC1_TXAK                  _IICC1.SameAddr_STR.IICC1STR.Bits.TXAK
01897     #define IICC1_TX                    _IICC1.SameAddr_STR.IICC1STR.Bits.TX
01898     #define IICC1_MST                   _IICC1.SameAddr_STR.IICC1STR.Bits.MST
01899     #define IICC1_IICIE                 _IICC1.SameAddr_STR.IICC1STR.Bits.IICIE
01900     #define IICC1_IICEN                 _IICC1.SameAddr_STR.IICC1STR.Bits.IICEN
01901     
01902     #define IICC1_WUEN_MASK             2U
01903     #define IICC1_RSTA_MASK             4U
01904     #define IICC1_TXAK_MASK             8U
01905     #define IICC1_TX_MASK               16U
01906     #define IICC1_MST_MASK              32U
01907     #define IICC1_IICIE_MASK            64U
01908     #define IICC1_IICEN_MASK            128U
01909     
01910     /*** IICC - IIC Control Register; Several registers at the same address ***/
01911     union {
01912       struct {
01913         byte             :1; 
01914         byte WUEN        :1;                                       /* Wake-up Enable */
01915         byte RSTA        :1;                                       /* Repeat START */
01916         byte TXAK        :1;                                       /* Transmit Acknowledge Enable */
01917         byte TX          :1;                                       /* Transmit Mode Select */
01918         byte MST         :1;                                       /* Master Mode Select */
01919         byte IICIE       :1;                                       /* IIC Interrupt Enable */
01920         byte IICEN       :1;                                       /* IIC Enable */
01921       } Bits;
01922     } IICCSTR;
01923     #define IICC                        _IICC1.Byte
01924     #define IICC_WUEN                   _IICC1.SameAddr_STR.IICCSTR.Bits.WUEN
01925     #define IICC_RSTA                   _IICC1.SameAddr_STR.IICCSTR.Bits.RSTA
01926     #define IICC_TXAK                   _IICC1.SameAddr_STR.IICCSTR.Bits.TXAK
01927     #define IICC_TX                     _IICC1.SameAddr_STR.IICCSTR.Bits.TX
01928     #define IICC_MST                    _IICC1.SameAddr_STR.IICCSTR.Bits.MST
01929     #define IICC_IICIE                  _IICC1.SameAddr_STR.IICCSTR.Bits.IICIE
01930     #define IICC_IICEN                  _IICC1.SameAddr_STR.IICCSTR.Bits.IICEN
01931     
01932     #define IICC_WUEN_MASK              2U
01933     #define IICC_RSTA_MASK              4U
01934     #define IICC_TXAK_MASK              8U
01935     #define IICC_TX_MASK                16U
01936     #define IICC_MST_MASK               32U
01937     #define IICC_IICIE_MASK             64U
01938     #define IICC_IICEN_MASK             128U
01939     
01940   } SameAddr_STR; /*Several registers at the same address */
01941 
01942 } IICC1STR;
01943 extern volatile IICC1STR _IICC1 @0xFFFF8042;
01944 
01945 
01946 /*** IICS - IIC Status Register; 0xFFFF8043 ***/
01947 typedef union {
01948   byte Byte;
01949   struct {
01950     byte RXAK        :1;                                       /* Receive Acknowledge */
01951     byte IICIF       :1;                                       /* IIC Interrupt Flag */
01952     byte SRW         :1;                                       /* Slave Read/Write */
01953     byte             :1; 
01954     byte ARBL        :1;                                       /* Arbitration Lost */
01955     byte BUSY        :1;                                       /* Bus Busy */
01956     byte IAAS        :1;                                       /* Addressed as a Slave */
01957     byte TCF         :1;                                       /* Transfer Complete Flag */
01958   } Bits;
01959 } IICSSTR;
01960 extern volatile IICSSTR _IICS @0xFFFF8043;
01961 #define IICS                            _IICS.Byte
01962 #define IICS_RXAK                       _IICS.Bits.RXAK
01963 #define IICS_IICIF                      _IICS.Bits.IICIF
01964 #define IICS_SRW                        _IICS.Bits.SRW
01965 #define IICS_ARBL                       _IICS.Bits.ARBL
01966 #define IICS_BUSY                       _IICS.Bits.BUSY
01967 #define IICS_IAAS                       _IICS.Bits.IAAS
01968 #define IICS_TCF                        _IICS.Bits.TCF
01969 
01970 #define IICS_RXAK_MASK                  1U
01971 #define IICS_IICIF_MASK                 2U
01972 #define IICS_SRW_MASK                   4U
01973 #define IICS_ARBL_MASK                  16U
01974 #define IICS_BUSY_MASK                  32U
01975 #define IICS_IAAS_MASK                  64U
01976 #define IICS_TCF_MASK                   128U
01977 
01978 
01979 /*** IICD - IIC Data I/O Register; 0xFFFF8044 ***/
01980 typedef union {
01981   byte Byte;
01982   struct {
01983     byte DATA0       :1;                                       /* IIC Data Bit 0 */
01984     byte DATA1       :1;                                       /* IIC Data Bit 1 */
01985     byte DATA2       :1;                                       /* IIC Data Bit 2 */
01986     byte DATA3       :1;                                       /* IIC Data Bit 3 */
01987     byte DATA4       :1;                                       /* IIC Data Bit 4 */
01988     byte DATA5       :1;                                       /* IIC Data Bit 5 */
01989     byte DATA6       :1;                                       /* IIC Data Bit 6 */
01990     byte DATA7       :1;                                       /* IIC Data Bit 7 */
01991   } Bits;
01992 } IICDSTR;
01993 extern volatile IICDSTR _IICD @0xFFFF8044;
01994 #define IICD                            _IICD.Byte
01995 #define IICD_DATA0                      _IICD.Bits.DATA0
01996 #define IICD_DATA1                      _IICD.Bits.DATA1
01997 #define IICD_DATA2                      _IICD.Bits.DATA2
01998 #define IICD_DATA3                      _IICD.Bits.DATA3
01999 #define IICD_DATA4                      _IICD.Bits.DATA4
02000 #define IICD_DATA5                      _IICD.Bits.DATA5
02001 #define IICD_DATA6                      _IICD.Bits.DATA6
02002 #define IICD_DATA7                      _IICD.Bits.DATA7
02003 
02004 #define IICD_DATA0_MASK                 1U
02005 #define IICD_DATA1_MASK                 2U
02006 #define IICD_DATA2_MASK                 4U
02007 #define IICD_DATA3_MASK                 8U
02008 #define IICD_DATA4_MASK                 16U
02009 #define IICD_DATA5_MASK                 32U
02010 #define IICD_DATA6_MASK                 64U
02011 #define IICD_DATA7_MASK                 128U
02012 
02013 
02014 /*** IICC2 - IIC Control Register 2; 0xFFFF8045 ***/
02015 typedef union {
02016   byte Byte;
02017   struct {
02018     byte AD8         :1;                                       /* Slave Address Bit 8 */
02019     byte AD9         :1;                                       /* Slave Address Bit 9 */
02020     byte AD10        :1;                                       /* Slave Address Bit 10 */
02021     byte             :1; 
02022     byte             :1; 
02023     byte             :1; 
02024     byte ADEXT       :1;                                       /* Address Extension */
02025     byte GCAEN       :1;                                       /* General Call Address Enable */
02026   } Bits;
02027   struct {
02028     byte grpAD_8 :3;
02029     byte         :1;
02030     byte         :1;
02031     byte         :1;
02032     byte         :1;
02033     byte         :1;
02034   } MergedBits;
02035 } IICC2STR;
02036 extern volatile IICC2STR _IICC2 @0xFFFF8045;
02037 #define IICC2                           _IICC2.Byte
02038 #define IICC2_AD8                       _IICC2.Bits.AD8
02039 #define IICC2_AD9                       _IICC2.Bits.AD9
02040 #define IICC2_AD10                      _IICC2.Bits.AD10
02041 #define IICC2_ADEXT                     _IICC2.Bits.ADEXT
02042 #define IICC2_GCAEN                     _IICC2.Bits.GCAEN
02043 #define IICC2_AD_8                      _IICC2.MergedBits.grpAD_8
02044 #define IICC2_AD                        IICC2_AD_8
02045 
02046 #define IICC2_AD8_MASK                  1U
02047 #define IICC2_AD9_MASK                  2U
02048 #define IICC2_AD10_MASK                 4U
02049 #define IICC2_ADEXT_MASK                64U
02050 #define IICC2_GCAEN_MASK                128U
02051 #define IICC2_AD_8_MASK                 7U
02052 #define IICC2_AD_8_BITNUM               0U
02053 
02054 
02055 /*** IICFLT - IIC Filter register; 0xFFFF8046 ***/
02056 typedef union {
02057   byte Byte;
02058   struct {
02059     byte FLT0        :1;                                       /* Filter value bit 0 */
02060     byte FLT1        :1;                                       /* Filter value bit 1 */
02061     byte FLT2        :1;                                       /* Filter value bit 2 */
02062     byte FLT3        :1;                                       /* Filter value bit 3 */
02063     byte FLT4        :1;                                       /* Filter value bit 4 */
02064     byte             :1; 
02065     byte             :1; 
02066     byte             :1; 
02067   } Bits;
02068   struct {
02069     byte grpFLT  :5;
02070     byte         :1;
02071     byte         :1;
02072     byte         :1;
02073   } MergedBits;
02074 } IICFLTSTR;
02075 extern volatile IICFLTSTR _IICFLT @0xFFFF8046;
02076 #define IICFLT                          _IICFLT.Byte
02077 #define IICFLT_FLT0                     _IICFLT.Bits.FLT0
02078 #define IICFLT_FLT1                     _IICFLT.Bits.FLT1
02079 #define IICFLT_FLT2                     _IICFLT.Bits.FLT2
02080 #define IICFLT_FLT3                     _IICFLT.Bits.FLT3
02081 #define IICFLT_FLT4                     _IICFLT.Bits.FLT4
02082 #define IICFLT_FLT                      _IICFLT.MergedBits.grpFLT
02083 
02084 #define IICFLT_FLT0_MASK                1U
02085 #define IICFLT_FLT1_MASK                2U
02086 #define IICFLT_FLT2_MASK                4U
02087 #define IICFLT_FLT3_MASK                8U
02088 #define IICFLT_FLT4_MASK                16U
02089 #define IICFLT_FLT_MASK                 31U
02090 #define IICFLT_FLT_BITNUM               0U
02091 
02092 
02093 /*** STOPCR - STOP Control Register; 0xFFFF8060 ***/
02094 typedef union {
02095   byte Byte;
02096   struct {
02097     byte SCtoFC      :1;                                       /* Slow Clock to Fast Clock STOP Transition Enabled */
02098     byte NC          :1;                                       /* STOP Mode Enable for STOP With No Clock */
02099     byte SC          :1;                                       /* STOP Mode Enable for STOP With Slow Clock */
02100     byte FC          :1;                                       /* STOP Mode Enable for STOP With Fast Clock */
02101     byte             :1; 
02102     byte             :1; 
02103     byte             :1; 
02104     byte             :1; 
02105   } Bits;
02106 } STOPCRSTR;
02107 extern volatile STOPCRSTR _STOPCR @0xFFFF8060;
02108 #define STOPCR                          _STOPCR.Byte
02109 #define STOPCR_SCtoFC                   _STOPCR.Bits.SCtoFC
02110 #define STOPCR_NC                       _STOPCR.Bits.NC
02111 #define STOPCR_SC                       _STOPCR.Bits.SC
02112 #define STOPCR_FC                       _STOPCR.Bits.FC
02113 
02114 #define STOPCR_SCtoFC_MASK              1U
02115 #define STOPCR_NC_MASK                  2U
02116 #define STOPCR_SC_MASK                  4U
02117 #define STOPCR_FC_MASK                  8U
02118 
02119 
02120 /*** FCSR - Frame Control and Status Register; 0xFFFF8061 ***/
02121 typedef union {
02122   byte Byte;
02123   struct {
02124     byte SF          :1;                                       /* Start Frame */
02125     byte SFDIE       :1;                                       /* Start FD Interrupt Enable */
02126     byte FE          :1;                                       /* Frame Error */
02127     byte SFEIE       :2;                                       /* Start Frame Error Interrupt Enable */
02128     byte A_EN        :1;                                       /* FA Enable */
02129     byte             :1; 
02130     byte             :1; 
02131   } Bits;
02132 } FCSRSTR;
02133 extern volatile FCSRSTR _FCSR @0xFFFF8061;
02134 #define FCSR                            _FCSR.Byte
02135 #define FCSR_SF                         _FCSR.Bits.SF
02136 #define FCSR_SFDIE                      _FCSR.Bits.SFDIE
02137 #define FCSR_FE                         _FCSR.Bits.FE
02138 #define FCSR_SFEIE                      _FCSR.Bits.SFEIE
02139 #define FCSR_A_EN                       _FCSR.Bits.A_EN
02140 
02141 #define FCSR_SF_MASK                    1U
02142 #define FCSR_SFDIE_MASK                 2U
02143 #define FCSR_FE_MASK                    4U
02144 #define FCSR_SFEIE_MASK                 24U
02145 #define FCSR_SFEIE_BITNUM               3U
02146 #define FCSR_A_EN_MASK                  32U
02147 
02148 
02149 /*** RCSR - Reset Control and Status Register; 0xFFFF8062 ***/
02150 typedef union {
02151   byte Byte;
02152   struct {
02153     byte POR         :1;                                       /* STOP Mode Enable for STOP With Fast Clock */
02154     byte PIN         :1;                                       /* External Pin Reset */
02155     byte ILAD        :1;                                       /* Illegal Address Reset */
02156     byte ILOP        :1;                                       /* Illegal Opcode Reset */
02157     byte SW          :1;                                       /* Software Reset */
02158     byte ASR         :1;                                       /* Assert Software Reset */
02159     byte DR          :1;                                       /* Drive Reset Pin */
02160     byte             :1; 
02161   } Bits;
02162 } RCSRSTR;
02163 extern volatile RCSRSTR _RCSR @0xFFFF8062;
02164 #define RCSR                            _RCSR.Byte
02165 #define RCSR_POR                        _RCSR.Bits.POR
02166 #define RCSR_PIN                        _RCSR.Bits.PIN
02167 #define RCSR_ILAD                       _RCSR.Bits.ILAD
02168 #define RCSR_ILOP                       _RCSR.Bits.ILOP
02169 #define RCSR_SW                         _RCSR.Bits.SW
02170 #define RCSR_ASR                        _RCSR.Bits.ASR
02171 #define RCSR_DR                         _RCSR.Bits.DR
02172 
02173 #define RCSR_POR_MASK                   1U
02174 #define RCSR_PIN_MASK                   2U
02175 #define RCSR_ILAD_MASK                  4U
02176 #define RCSR_ILOP_MASK                  8U
02177 #define RCSR_SW_MASK                    16U
02178 #define RCSR_ASR_MASK                   32U
02179 #define RCSR_DR_MASK                    64U
02180 
02181 
02182 /*** SIM_TR - SIM Test Probe Register; 0xFFFF8063 ***/
02183 typedef union {
02184   byte Byte;
02185   struct {
02186     byte TP0         :4;                                       /* Test Point Zero */
02187     byte TP1         :4;                                       /* Test Point One */
02188   } Bits;
02189 } SIM_TRSTR;
02190 extern volatile SIM_TRSTR _SIM_TR @0xFFFF8063;
02191 #define SIM_TR                          _SIM_TR.Byte
02192 #define SIM_TR_TP0                      _SIM_TR.Bits.TP0
02193 #define SIM_TR_TP1                      _SIM_TR.Bits.TP1
02194 
02195 #define SIM_TR_TP0_MASK                 15U
02196 #define SIM_TR_TP0_BITNUM               0U
02197 #define SIM_TR_TP1_MASK                 240U
02198 #define SIM_TR_TP1_BITNUM               4U
02199 
02200 
02201 /*** PCESFC0 - Peripheral Clock in STOPFC Mode Enable  Register 0; 0xFFFF8064 ***/
02202 typedef union {
02203   byte Byte;
02204   struct {
02205     byte FLSH        :1;                                       /* Flash Controller Clock Enable */
02206     byte PCTRL       :1;                                       /* Port Control Clock Enable */
02207     byte AFE         :1;                                       /* Analog Front End Clock Enable */
02208     byte IRQ         :1;                                       /* IRQ Clock Enable */
02209     byte T0          :1;                                       /* Timer 0 Clock Enable */
02210     byte T1          :1;                                       /* Timer 1 Clock Enable */
02211     byte T2          :1;                                       /* Timer 2 Clock Enable */
02212     byte             :1; 
02213   } Bits;
02214   struct {
02215     byte         :1;
02216     byte         :1;
02217     byte         :1;
02218     byte         :1;
02219     byte grpT    :3;
02220     byte         :1;
02221   } MergedBits;
02222 } PCESFC0STR;
02223 extern volatile PCESFC0STR _PCESFC0 @0xFFFF8064;
02224 #define PCESFC0                         _PCESFC0.Byte
02225 #define PCESFC0_FLSH                    _PCESFC0.Bits.FLSH
02226 #define PCESFC0_PCTRL                   _PCESFC0.Bits.PCTRL
02227 #define PCESFC0_AFE                     _PCESFC0.Bits.AFE
02228 #define PCESFC0_IRQ                     _PCESFC0.Bits.IRQ
02229 #define PCESFC0_T0                      _PCESFC0.Bits.T0
02230 #define PCESFC0_T1                      _PCESFC0.Bits.T1
02231 #define PCESFC0_T2                      _PCESFC0.Bits.T2
02232 /* PCESFC_ARR: Access 2 PCESFCx registers in an array */
02233 #define PCESFC_ARR                      ((volatile byte *) &PCESFC0)
02234 #define PCESFC0_T                       _PCESFC0.MergedBits.grpT
02235 
02236 #define PCESFC0_FLSH_MASK               1U
02237 #define PCESFC0_PCTRL_MASK              2U
02238 #define PCESFC0_AFE_MASK                4U
02239 #define PCESFC0_IRQ_MASK                8U
02240 #define PCESFC0_T0_MASK                 16U
02241 #define PCESFC0_T1_MASK                 32U
02242 #define PCESFC0_T2_MASK                 64U
02243 #define PCESFC0_T_MASK                  112U
02244 #define PCESFC0_T_BITNUM                4U
02245 
02246 
02247 /*** PCESFC1 - Peripheral Clock in STOPFC Mode Enable  Register 0; 0xFFFF8065 ***/
02248 typedef union {
02249   byte Byte;
02250   struct {
02251     byte SLAVE       :1;                                       /* Slave Port Clock Enable */
02252     byte MI2C        :1;                                       /* Master I2C Clock Enable */
02253     byte MSPI        :1;                                       /* Master SPI Clock Enable */
02254     byte             :1; 
02255     byte             :1; 
02256     byte             :1; 
02257     byte             :1; 
02258     byte             :1; 
02259   } Bits;
02260 } PCESFC1STR;
02261 extern volatile PCESFC1STR _PCESFC1 @0xFFFF8065;
02262 #define PCESFC1                         _PCESFC1.Byte
02263 #define PCESFC1_SLAVE                   _PCESFC1.Bits.SLAVE
02264 #define PCESFC1_MI2C                    _PCESFC1.Bits.MI2C
02265 #define PCESFC1_MSPI                    _PCESFC1.Bits.MSPI
02266 
02267 #define PCESFC1_SLAVE_MASK              1U
02268 #define PCESFC1_MI2C_MASK               2U
02269 #define PCESFC1_MSPI_MASK               4U
02270 
02271 
02272 /*** PCESSC0 - Peripheral Clock in STOPSC Mode Enable  Register 0; 0xFFFF8066 ***/
02273 typedef union {
02274   byte Byte;
02275   struct {
02276     byte FLSH        :1;                                       /* Flash Controller Clock Enable */
02277     byte PCTRL       :1;                                       /* Port Control Clock Enable */
02278     byte AFE         :1;                                       /* Analog Front End Clock Enable */
02279     byte IRQ         :1;                                       /* IRQ Clock Enable */
02280     byte T0          :1;                                       /* Timer 0 Clock Enable */
02281     byte T1          :1;                                       /* Timer 1 Clock Enable */
02282     byte T2          :1;                                       /* Timer 2 Clock Enable */
02283     byte             :1; 
02284   } Bits;
02285   struct {
02286     byte         :1;
02287     byte         :1;
02288     byte         :1;
02289     byte         :1;
02290     byte grpT    :3;
02291     byte         :1;
02292   } MergedBits;
02293 } PCESSC0STR;
02294 extern volatile PCESSC0STR _PCESSC0 @0xFFFF8066;
02295 #define PCESSC0                         _PCESSC0.Byte
02296 #define PCESSC0_FLSH                    _PCESSC0.Bits.FLSH
02297 #define PCESSC0_PCTRL                   _PCESSC0.Bits.PCTRL
02298 #define PCESSC0_AFE                     _PCESSC0.Bits.AFE
02299 #define PCESSC0_IRQ                     _PCESSC0.Bits.IRQ
02300 #define PCESSC0_T0                      _PCESSC0.Bits.T0
02301 #define PCESSC0_T1                      _PCESSC0.Bits.T1
02302 #define PCESSC0_T2                      _PCESSC0.Bits.T2
02303 /* PCESSC_ARR: Access 2 PCESSCx registers in an array */
02304 #define PCESSC_ARR                      ((volatile byte *) &PCESSC0)
02305 #define PCESSC0_T                       _PCESSC0.MergedBits.grpT
02306 
02307 #define PCESSC0_FLSH_MASK               1U
02308 #define PCESSC0_PCTRL_MASK              2U
02309 #define PCESSC0_AFE_MASK                4U
02310 #define PCESSC0_IRQ_MASK                8U
02311 #define PCESSC0_T0_MASK                 16U
02312 #define PCESSC0_T1_MASK                 32U
02313 #define PCESSC0_T2_MASK                 64U
02314 #define PCESSC0_T_MASK                  112U
02315 #define PCESSC0_T_BITNUM                4U
02316 
02317 
02318 /*** PCESSC1 - Peripheral Clock in STOPSC Mode Enable  Register 0; 0xFFFF8067 ***/
02319 typedef union {
02320   byte Byte;
02321   struct {
02322     byte SLAVE       :1;                                       /* Slave Port Clock Enable */
02323     byte MI2C        :1;                                       /* Master I2C Clock Enable */
02324     byte MSPI        :1;                                       /* Master SPI Clock Enable */
02325     byte             :1; 
02326     byte             :1; 
02327     byte             :1; 
02328     byte             :1; 
02329     byte             :1; 
02330   } Bits;
02331 } PCESSC1STR;
02332 extern volatile PCESSC1STR _PCESSC1 @0xFFFF8067;
02333 #define PCESSC1                         _PCESSC1.Byte
02334 #define PCESSC1_SLAVE                   _PCESSC1.Bits.SLAVE
02335 #define PCESSC1_MI2C                    _PCESSC1.Bits.MI2C
02336 #define PCESSC1_MSPI                    _PCESSC1.Bits.MSPI
02337 
02338 #define PCESSC1_SLAVE_MASK              1U
02339 #define PCESSC1_MI2C_MASK               2U
02340 #define PCESSC1_MSPI_MASK               4U
02341 
02342 
02343 /*** PCERUN0 - Peripheral Clock in RUN Mode Enable  Register 0; 0xFFFF8068 ***/
02344 typedef union {
02345   byte Byte;
02346   struct {
02347     byte FLSH        :1;                                       /* Flash Controller Clock Enable */
02348     byte PCTRL       :1;                                       /* Port Control Clock Enable */
02349     byte AFE         :1;                                       /* Analog Front End Clock Enable */
02350     byte IRQ         :1;                                       /* IRQ Clock Enable */
02351     byte T0          :1;                                       /* Timer 0 Clock Enable */
02352     byte T1          :1;                                       /* Timer 1 Clock Enable */
02353     byte T2          :1;                                       /* Timer 2 Clock Enable */
02354     byte             :1; 
02355   } Bits;
02356   struct {
02357     byte         :1;
02358     byte         :1;
02359     byte         :1;
02360     byte         :1;
02361     byte grpT    :3;
02362     byte         :1;
02363   } MergedBits;
02364 } PCERUN0STR;
02365 extern volatile PCERUN0STR _PCERUN0 @0xFFFF8068;
02366 #define PCERUN0                         _PCERUN0.Byte
02367 #define PCERUN0_FLSH                    _PCERUN0.Bits.FLSH
02368 #define PCERUN0_PCTRL                   _PCERUN0.Bits.PCTRL
02369 #define PCERUN0_AFE                     _PCERUN0.Bits.AFE
02370 #define PCERUN0_IRQ                     _PCERUN0.Bits.IRQ
02371 #define PCERUN0_T0                      _PCERUN0.Bits.T0
02372 #define PCERUN0_T1                      _PCERUN0.Bits.T1
02373 #define PCERUN0_T2                      _PCERUN0.Bits.T2
02374 /* PCERUN_ARR: Access 2 PCERUNx registers in an array */
02375 #define PCERUN_ARR                      ((volatile byte *) &PCERUN0)
02376 #define PCERUN0_T                       _PCERUN0.MergedBits.grpT
02377 
02378 #define PCERUN0_FLSH_MASK               1U
02379 #define PCERUN0_PCTRL_MASK              2U
02380 #define PCERUN0_AFE_MASK                4U
02381 #define PCERUN0_IRQ_MASK                8U
02382 #define PCERUN0_T0_MASK                 16U
02383 #define PCERUN0_T1_MASK                 32U
02384 #define PCERUN0_T2_MASK                 64U
02385 #define PCERUN0_T_MASK                  112U
02386 #define PCERUN0_T_BITNUM                4U
02387 
02388 
02389 /*** PCERUN1 - Peripheral Clock in RUN Mode Enable  Register 0; 0xFFFF8069 ***/
02390 typedef union {
02391   byte Byte;
02392   struct {
02393     byte SLAVE       :1;                                       /* Slave Port Clock Enable */
02394     byte MI2C        :1;                                       /* Master I2C Clock Enable */
02395     byte MSPI        :1;                                       /* Master SPI Clock Enable */
02396     byte             :1; 
02397     byte             :1; 
02398     byte             :1; 
02399     byte             :1; 
02400     byte             :1; 
02401   } Bits;
02402 } PCERUN1STR;
02403 extern volatile PCERUN1STR _PCERUN1 @0xFFFF8069;
02404 #define PCERUN1                         _PCERUN1.Byte
02405 #define PCERUN1_SLAVE                   _PCERUN1.Bits.SLAVE
02406 #define PCERUN1_MI2C                    _PCERUN1.Bits.MI2C
02407 #define PCERUN1_MSPI                    _PCERUN1.Bits.MSPI
02408 
02409 #define PCERUN1_SLAVE_MASK              1U
02410 #define PCERUN1_MI2C_MASK               2U
02411 #define PCERUN1_MSPI_MASK               4U
02412 
02413 
02414 /*** PMCR0 - Pin Mux Control Register 0; 0xFFFF806A ***/
02415 typedef union {
02416   byte Byte;
02417   struct {
02418     byte A4          :1;                                       /* RGPIO Bit 4 Pin Function Select */
02419     byte             :1; 
02420     byte A6          :2;                                       /* RGPIO Bit 6 Pin Function Select */
02421     byte A7          :2;                                       /* RGPIO Bit 7 Pin Function Select */
02422     byte A8          :1;                                       /* RGPIO Bit 8 Pin Function Select */
02423     byte A9          :1;                                       /* RGPIO Bit 9 Pin Function Select */
02424   } Bits;
02425   struct {
02426     byte grpA_4  :1;
02427     byte         :1;
02428     byte         :2;
02429     byte         :2;
02430     byte grpA_8  :2;
02431   } MergedBits;
02432 } PMCR0STR;
02433 extern volatile PMCR0STR _PMCR0 @0xFFFF806A;
02434 #define PMCR0                           _PMCR0.Byte
02435 #define PMCR0_A4                        _PMCR0.Bits.A4
02436 #define PMCR0_A6                        _PMCR0.Bits.A6
02437 #define PMCR0_A7                        _PMCR0.Bits.A7
02438 #define PMCR0_A8                        _PMCR0.Bits.A8
02439 #define PMCR0_A9                        _PMCR0.Bits.A9
02440 /* PMCR_ARR: Access 3 PMCRx registers in an array */
02441 #define PMCR_ARR                        ((volatile byte *) &PMCR0)
02442 #define PMCR0_A_8                       _PMCR0.MergedBits.grpA_8
02443 #define PMCR0_A                         PMCR0_A_8
02444 
02445 #define PMCR0_A4_MASK                   1U
02446 #define PMCR0_A6_MASK                   12U
02447 #define PMCR0_A6_BITNUM                 2U
02448 #define PMCR0_A7_MASK                   48U
02449 #define PMCR0_A7_BITNUM                 4U
02450 #define PMCR0_A8_MASK                   64U
02451 #define PMCR0_A9_MASK                   128U
02452 #define PMCR0_A_8_MASK                  192U
02453 #define PMCR0_A_8_BITNUM                6U
02454 
02455 
02456 /*** PMCR1 - Pin Mux Control Register 1; 0xFFFF806B ***/
02457 typedef union {
02458   byte Byte;
02459   struct {
02460     byte A0          :2;                                       /* RGPIO Bit 0 Pin Function Select */
02461     byte A1          :2;                                       /* RGPIO Bit 1 Pin Function Select */
02462     byte A2          :2;                                       /* RGPIO Bit 2 Pin Function Select */
02463     byte A3          :2;                                       /* RGPIO Bit 3 Pin Function Select */
02464   } Bits;
02465 } PMCR1STR;
02466 extern volatile PMCR1STR _PMCR1 @0xFFFF806B;
02467 #define PMCR1                           _PMCR1.Byte
02468 #define PMCR1_A0                        _PMCR1.Bits.A0
02469 #define PMCR1_A1                        _PMCR1.Bits.A1
02470 #define PMCR1_A2                        _PMCR1.Bits.A2
02471 #define PMCR1_A3                        _PMCR1.Bits.A3
02472 
02473 #define PMCR1_A0_MASK                   3U
02474 #define PMCR1_A0_BITNUM                 0U
02475 #define PMCR1_A1_MASK                   12U
02476 #define PMCR1_A1_BITNUM                 2U
02477 #define PMCR1_A2_MASK                   48U
02478 #define PMCR1_A2_BITNUM                 4U
02479 #define PMCR1_A3_MASK                   192U
02480 #define PMCR1_A3_BITNUM                 6U
02481 
02482 
02483 /*** PMCR2 - Pin Mux Control Register 2; 0xFFFF806C ***/
02484 typedef union {
02485   byte Byte;
02486   struct {
02487     byte A5          :2;                                       /* RGPIO Bit 5 Pin Function Select */
02488     byte             :1; 
02489     byte             :1; 
02490     byte             :1; 
02491     byte             :1; 
02492     byte             :1; 
02493     byte             :1; 
02494   } Bits;
02495 } PMCR2STR;
02496 extern volatile PMCR2STR _PMCR2 @0xFFFF806C;
02497 #define PMCR2                           _PMCR2.Byte
02498 #define PMCR2_A5                        _PMCR2.Bits.A5
02499 
02500 #define PMCR2_A5_MASK                   3U
02501 #define PMCR2_A5_BITNUM                 0U
02502 
02503 
02504 /*** TCR - SIM Test Control Register; 0xFFFF806D ***/
02505 typedef union {
02506   byte Byte;
02507   struct {
02508     byte TLF         :1;                                       /* Trim Low Frequency Mode of on-chip oscillator */
02509     byte TLF_DIV     :1;                                       /* Divider Select for Trim Low Frequency Mode of on-chip oscillator */
02510     byte             :1; 
02511     byte             :1; 
02512     byte             :1; 
02513     byte             :1; 
02514     byte LOCK0       :1;                                       /* LOCK SIM Test Control Register Bits, bit 0 */
02515     byte LOCK1       :1;                                       /* LOCK SIM Test Control Register Bits, bit 1 */
02516   } Bits;
02517   struct {
02518     byte         :1;
02519     byte         :1;
02520     byte         :1;
02521     byte         :1;
02522     byte         :1;
02523     byte         :1;
02524     byte grpLOCK :2;
02525   } MergedBits;
02526 } TCRSTR;
02527 extern volatile TCRSTR _TCR @0xFFFF806D;
02528 #define TCR                             _TCR.Byte
02529 #define TCR_TLF                         _TCR.Bits.TLF
02530 #define TCR_TLF_DIV                     _TCR.Bits.TLF_DIV
02531 #define TCR_LOCK0                       _TCR.Bits.LOCK0
02532 #define TCR_LOCK1                       _TCR.Bits.LOCK1
02533 #define TCR_LOCK                        _TCR.MergedBits.grpLOCK
02534 
02535 #define TCR_TLF_MASK                    1U
02536 #define TCR_TLF_DIV_MASK                2U
02537 #define TCR_LOCK0_MASK                  64U
02538 #define TCR_LOCK1_MASK                  128U
02539 #define TCR_LOCK_MASK                   192U
02540 #define TCR_LOCK_BITNUM                 6U
02541 
02542 
02543 /*** CK_OSCTRL - Oscillator Control Registerr; 0xFFFF8080 ***/
02544 typedef union {
02545   byte Byte;
02546   struct {
02547     byte FLE         :5;                                       /* Frame Length Exponent */
02548     byte FFSEN       :1;                                       /* Fixed Frequency Clock STOP Enable */
02549     byte FFCEN       :1;                                       /* Fixed Frequency Clock Enable */
02550     byte FCEN        :1;                                       /* Frame Counter Enable */
02551   } Bits;
02552 } CK_OSCTRLSTR;
02553 extern volatile CK_OSCTRLSTR _CK_OSCTRL @0xFFFF8080;
02554 #define CK_OSCTRL                       _CK_OSCTRL.Byte
02555 #define CK_OSCTRL_FLE                   _CK_OSCTRL.Bits.FLE
02556 #define CK_OSCTRL_FFSEN                 _CK_OSCTRL.Bits.FFSEN
02557 #define CK_OSCTRL_FFCEN                 _CK_OSCTRL.Bits.FFCEN
02558 #define CK_OSCTRL_FCEN                  _CK_OSCTRL.Bits.FCEN
02559 
02560 #define CK_OSCTRL_FLE_MASK              31U
02561 #define CK_OSCTRL_FLE_BITNUM            0U
02562 #define CK_OSCTRL_FFSEN_MASK            32U
02563 #define CK_OSCTRL_FFCEN_MASK            64U
02564 #define CK_OSCTRL_FCEN_MASK             128U
02565 
02566 
02567 /*** CK_TRIM - Frequency Trim Value; 0xFFFF8084 ***/
02568 typedef union {
02569   dword Dword;
02570    /* Overlapped registers: */
02571   struct {
02572     /*** CK_TRIML - Low Frequency Trim Value; 0xFFFF8084 ***/
02573     union {
02574       word Word;
02575        /* Overlapped registers: */
02576       struct {
02577         /*** CK_TRIMLM - Low Frequency Trim Value - Most Significant Byte; 0xFFFF8084 ***/
02578         union {
02579           byte Byte;
02580         } CK_TRIMLMSTR;
02581         #define CK_TRIMLM               _CK_TRIM.Overlap_STR.CK_TRIMLSTR.Overlap_STR.CK_TRIMLMSTR.Byte
02582         
02583     
02584         /*** CK_TRIMLL - Low Frequency Trim Value - Least Significant Byte; 0xFFFF8085 ***/
02585         union {
02586           byte Byte;
02587         } CK_TRIMLLSTR;
02588         #define CK_TRIMLL               _CK_TRIM.Overlap_STR.CK_TRIMLSTR.Overlap_STR.CK_TRIMLLSTR.Byte
02589         
02590       } Overlap_STR;
02591     
02592     } CK_TRIMLSTR;
02593     #define CK_TRIML                    _CK_TRIM.Overlap_STR.CK_TRIMLSTR.Word
02594     
02595 
02596     /*** CK_TRIMH - High Frequency Trim Value; 0xFFFF8086 ***/
02597     union {
02598       word Word;
02599        /* Overlapped registers: */
02600       struct {
02601         /*** CK_TRIMHM - High Frequency Trim Value - Most Significant Byte; 0xFFFF8086 ***/
02602         union {
02603           byte Byte;
02604         } CK_TRIMHMSTR;
02605         #define CK_TRIMHM               _CK_TRIM.Overlap_STR.CK_TRIMHSTR.Overlap_STR.CK_TRIMHMSTR.Byte
02606         
02607     
02608         /*** CK_TRIMHL - High Frequency Trim Value - Least Significant Byte; 0xFFFF8087 ***/
02609         union {
02610           byte Byte;
02611         } CK_TRIMHLSTR;
02612         #define CK_TRIMHL               _CK_TRIM.Overlap_STR.CK_TRIMHSTR.Overlap_STR.CK_TRIMHLSTR.Byte
02613         
02614       } Overlap_STR;
02615     
02616     } CK_TRIMHSTR;
02617     #define CK_TRIMH                    _CK_TRIM.Overlap_STR.CK_TRIMHSTR.Word
02618     
02619   } Overlap_STR;
02620 
02621   struct {
02622     dword TRIML      :16;                                      /* Low Frequency Trim Value */
02623     dword TRIMH      :16;                                      /* High Frequency Trim Value */
02624   } Bits;
02625 } CK_TRIMSTR;
02626 extern volatile CK_TRIMSTR _CK_TRIM @0xFFFF8084;
02627 #define CK_TRIM                         _CK_TRIM.Dword
02628 #define CK_TRIM_TRIML                   _CK_TRIM.Bits.TRIML
02629 #define CK_TRIM_TRIMH                   _CK_TRIM.Bits.TRIMH
02630 
02631 #define CK_TRIM_TRIML_MASK              65535UL
02632 #define CK_TRIM_TRIML_BITNUM            0UL
02633 #define CK_TRIM_TRIMH_MASK              4294901760UL
02634 #define CK_TRIM_TRIMH_BITNUM            16UL
02635 
02636 
02637 /*** MTIM16SC - MTIM16 Status and Control Register; 0xFFFF80A0 ***/
02638 typedef union {
02639   byte Byte;
02640   struct {
02641     byte             :1; 
02642     byte             :1; 
02643     byte             :1; 
02644     byte             :1; 
02645     byte TSTP        :1;                                       /* MTIM16 Counter Stop */
02646     byte TRST        :1;                                       /* MTIM16 Counter Reset */
02647     byte TOIE        :1;                                       /* MTIM16 Overflow Interrupt Enable */
02648     byte TOF         :1;                                       /* MTIM16 Overflow Flag */
02649   } Bits;
02650 } MTIM16SCSTR;
02651 extern volatile MTIM16SCSTR _MTIM16SC @0xFFFF80A0;
02652 #define MTIM16SC                        _MTIM16SC.Byte
02653 #define MTIM16SC_TSTP                   _MTIM16SC.Bits.TSTP
02654 #define MTIM16SC_TRST                   _MTIM16SC.Bits.TRST
02655 #define MTIM16SC_TOIE                   _MTIM16SC.Bits.TOIE
02656 #define MTIM16SC_TOF                    _MTIM16SC.Bits.TOF
02657 
02658 #define MTIM16SC_TSTP_MASK              16U
02659 #define MTIM16SC_TRST_MASK              32U
02660 #define MTIM16SC_TOIE_MASK              64U
02661 #define MTIM16SC_TOF_MASK               128U
02662 
02663 
02664 /*** MTIM16CLK - MTIM16 Clock Configuration Register; 0xFFFF80A1 ***/
02665 typedef union {
02666   byte Byte;
02667   struct {
02668     byte PS0         :1;                                       /* Clock source Prescaler Bit 0 */
02669     byte PS1         :1;                                       /* Clock source Prescaler Bit 1 */
02670     byte PS2         :1;                                       /* Clock source Prescaler Bit 2 */
02671     byte PS3         :1;                                       /* Clock source Prescaler Bit 3 */
02672     byte CLKS0       :1;                                       /* Clock source Select Bit 0 */
02673     byte CLKS1       :1;                                       /* Clock source Select Bit 1 */
02674     byte             :1; 
02675     byte             :1; 
02676   } Bits;
02677   struct {
02678     byte grpPS   :4;
02679     byte grpCLKS :2;
02680     byte         :1;
02681     byte         :1;
02682   } MergedBits;
02683 } MTIM16CLKSTR;
02684 extern volatile MTIM16CLKSTR _MTIM16CLK @0xFFFF80A1;
02685 #define MTIM16CLK                       _MTIM16CLK.Byte
02686 #define MTIM16CLK_PS0                   _MTIM16CLK.Bits.PS0
02687 #define MTIM16CLK_PS1                   _MTIM16CLK.Bits.PS1
02688 #define MTIM16CLK_PS2                   _MTIM16CLK.Bits.PS2
02689 #define MTIM16CLK_PS3                   _MTIM16CLK.Bits.PS3
02690 #define MTIM16CLK_CLKS0                 _MTIM16CLK.Bits.CLKS0
02691 #define MTIM16CLK_CLKS1                 _MTIM16CLK.Bits.CLKS1
02692 #define MTIM16CLK_PS                    _MTIM16CLK.MergedBits.grpPS
02693 #define MTIM16CLK_CLKS                  _MTIM16CLK.MergedBits.grpCLKS
02694 
02695 #define MTIM16CLK_PS0_MASK              1U
02696 #define MTIM16CLK_PS1_MASK              2U
02697 #define MTIM16CLK_PS2_MASK              4U
02698 #define MTIM16CLK_PS3_MASK              8U
02699 #define MTIM16CLK_CLKS0_MASK            16U
02700 #define MTIM16CLK_CLKS1_MASK            32U
02701 #define MTIM16CLK_PS_MASK               15U
02702 #define MTIM16CLK_PS_BITNUM             0U
02703 #define MTIM16CLK_CLKS_MASK             48U
02704 #define MTIM16CLK_CLKS_BITNUM           4U
02705 
02706 
02707 /*** MTIM16CNT - MTIM16 Counter Register; 0xFFFF80A2 ***/
02708 typedef union {
02709   word Word;
02710    /* Overlapped registers: */
02711   struct {
02712     /*** MTIM16CNTH - MTIM16 Counter Register High; 0xFFFF80A2 ***/
02713     union {
02714       byte Byte;
02715     } MTIM16CNTHSTR;
02716     #define MTIM16CNTH                  _MTIM16CNT.Overlap_STR.MTIM16CNTHSTR.Byte
02717     
02718 
02719     /*** MTIM16CNTL - MTIM16 Counter Register Low; 0xFFFF80A3 ***/
02720     union {
02721       byte Byte;
02722     } MTIM16CNTLSTR;
02723     #define MTIM16CNTL                  _MTIM16CNT.Overlap_STR.MTIM16CNTLSTR.Byte
02724     
02725   } Overlap_STR;
02726 
02727 } MTIM16CNTSTR;
02728 extern volatile MTIM16CNTSTR _MTIM16CNT @0xFFFF80A2;
02729 #define MTIM16CNT                       _MTIM16CNT.Word
02730 
02731 
02732 /*** MTIM16MOD - MTIM16 Modulo Register; 0xFFFF80A4 ***/
02733 typedef union {
02734   word Word;
02735    /* Overlapped registers: */
02736   struct {
02737     /*** MTIM16MODH - MTIM16 Modulo Register High; 0xFFFF80A4 ***/
02738     union {
02739       byte Byte;
02740     } MTIM16MODHSTR;
02741     #define MTIM16MODH                  _MTIM16MOD.Overlap_STR.MTIM16MODHSTR.Byte
02742     
02743 
02744     /*** MTIM16MODL - MTIM16 Modulo Register Low; 0xFFFF80A5 ***/
02745     union {
02746       byte Byte;
02747     } MTIM16MODLSTR;
02748     #define MTIM16MODL                  _MTIM16MOD.Overlap_STR.MTIM16MODLSTR.Byte
02749     
02750   } Overlap_STR;
02751 
02752 } MTIM16MODSTR;
02753 extern volatile MTIM16MODSTR _MTIM16MOD @0xFFFF80A4;
02754 #define MTIM16MOD                       _MTIM16MOD.Word
02755 
02756 
02757 /*** IRQSC - Interrupt request status and control register; 0xFFFF80C0 ***/
02758 typedef union {
02759   byte Byte;
02760   struct {
02761     byte IRQMOD      :1;                                       /* IRQ Detection Mode */
02762     byte IRQIE       :1;                                       /* IRQ Interrupt Enable */
02763     byte IRQACK      :1;                                       /* IRQ Acknowledge */
02764     byte IRQF        :1;                                       /* IRQ Flag */
02765     byte IRQPE       :1;                                       /* IRQ Pin Enable */
02766     byte IRQEDG      :1;                                       /* IRQ Edge Select */
02767     byte IRQPDD      :1;                                       /* IRQ Pull Device Disable */
02768     byte             :1; 
02769   } Bits;
02770 } IRQSCSTR;
02771 extern volatile IRQSCSTR _IRQSC @0xFFFF80C0;
02772 #define IRQSC                           _IRQSC.Byte
02773 #define IRQSC_IRQMOD                    _IRQSC.Bits.IRQMOD
02774 #define IRQSC_IRQIE                     _IRQSC.Bits.IRQIE
02775 #define IRQSC_IRQACK                    _IRQSC.Bits.IRQACK
02776 #define IRQSC_IRQF                      _IRQSC.Bits.IRQF
02777 #define IRQSC_IRQPE                     _IRQSC.Bits.IRQPE
02778 #define IRQSC_IRQEDG                    _IRQSC.Bits.IRQEDG
02779 #define IRQSC_IRQPDD                    _IRQSC.Bits.IRQPDD
02780 
02781 #define IRQSC_IRQMOD_MASK               1U
02782 #define IRQSC_IRQIE_MASK                2U
02783 #define IRQSC_IRQACK_MASK               4U
02784 #define IRQSC_IRQF_MASK                 8U
02785 #define IRQSC_IRQPE_MASK                16U
02786 #define IRQSC_IRQEDG_MASK               32U
02787 #define IRQSC_IRQPDD_MASK               64U
02788 
02789 
02790 /*** PC0PE - Pull Enable Register; 0xFFFF80E0 ***/
02791 typedef union {
02792   byte Byte;
02793   struct {
02794     byte PE0         :1;                                       /* Internal Pull Enable, bit 0 */
02795     byte PE1         :1;                                       /* Internal Pull Enable, bit 1 */
02796     byte PE2         :1;                                       /* Internal Pull Enable, bit 2 */
02797     byte PE3         :1;                                       /* Internal Pull Enable, bit 3 */
02798     byte PE4         :1;                                       /* Internal Pull Enable, bit 4 */
02799     byte PE5         :1;                                       /* Internal Pull Enable, bit 5 */
02800     byte PE6         :1;                                       /* Internal Pull Enable, bit 6 */
02801     byte PE7         :1;                                       /* Internal Pull Enable, bit 7 */
02802   } Bits;
02803 } PC0PESTR;
02804 extern volatile PC0PESTR _PC0PE @0xFFFF80E0;
02805 #define PC0PE                           _PC0PE.Byte
02806 #define PC0PE_PE0                       _PC0PE.Bits.PE0
02807 #define PC0PE_PE1                       _PC0PE.Bits.PE1
02808 #define PC0PE_PE2                       _PC0PE.Bits.PE2
02809 #define PC0PE_PE3                       _PC0PE.Bits.PE3
02810 #define PC0PE_PE4                       _PC0PE.Bits.PE4
02811 #define PC0PE_PE5                       _PC0PE.Bits.PE5
02812 #define PC0PE_PE6                       _PC0PE.Bits.PE6
02813 #define PC0PE_PE7                       _PC0PE.Bits.PE7
02814 
02815 #define PC0PE_PE0_MASK                  1U
02816 #define PC0PE_PE1_MASK                  2U
02817 #define PC0PE_PE2_MASK                  4U
02818 #define PC0PE_PE3_MASK                  8U
02819 #define PC0PE_PE4_MASK                  16U
02820 #define PC0PE_PE5_MASK                  32U
02821 #define PC0PE_PE6_MASK                  64U
02822 #define PC0PE_PE7_MASK                  128U
02823 
02824 
02825 /*** PC0SE - Slew Rate Enable Register; 0xFFFF80E1 ***/
02826 typedef union {
02827   byte Byte;
02828   struct {
02829     byte SE0         :1;                                       /* Output Slew Rate Enable, bit 0 */
02830     byte SE1         :1;                                       /* Output Slew Rate Enable, bit 1 */
02831     byte SE2         :1;                                       /* Output Slew Rate Enable, bit 2 */
02832     byte SE3         :1;                                       /* Output Slew Rate Enable, bit 3 */
02833     byte SE4         :1;                                       /* Output Slew Rate Enable, bit 4 */
02834     byte SE5         :1;                                       /* Output Slew Rate Enable, bit 5 */
02835     byte SE6         :1;                                       /* Output Slew Rate Enable, bit 6 */
02836     byte SE7         :1;                                       /* Output Slew Rate Enable, bit 7 */
02837   } Bits;
02838 } PC0SESTR;
02839 extern volatile PC0SESTR _PC0SE @0xFFFF80E1;
02840 #define PC0SE                           _PC0SE.Byte
02841 #define PC0SE_SE0                       _PC0SE.Bits.SE0
02842 #define PC0SE_SE1                       _PC0SE.Bits.SE1
02843 #define PC0SE_SE2                       _PC0SE.Bits.SE2
02844 #define PC0SE_SE3                       _PC0SE.Bits.SE3
02845 #define PC0SE_SE4                       _PC0SE.Bits.SE4
02846 #define PC0SE_SE5                       _PC0SE.Bits.SE5
02847 #define PC0SE_SE6                       _PC0SE.Bits.SE6
02848 #define PC0SE_SE7                       _PC0SE.Bits.SE7
02849 
02850 #define PC0SE_SE0_MASK                  1U
02851 #define PC0SE_SE1_MASK                  2U
02852 #define PC0SE_SE2_MASK                  4U
02853 #define PC0SE_SE3_MASK                  8U
02854 #define PC0SE_SE4_MASK                  16U
02855 #define PC0SE_SE5_MASK                  32U
02856 #define PC0SE_SE6_MASK                  64U
02857 #define PC0SE_SE7_MASK                  128U
02858 
02859 
02860 /*** PC0DS - Drive Strength Selection Register; 0xFFFF80E2 ***/
02861 typedef union {
02862   byte Byte;
02863   struct {
02864     byte DS0         :1;                                       /* Output Drive Strength Selection, bit 0 */
02865     byte DS1         :1;                                       /* Output Drive Strength Selection, bit 1 */
02866     byte DS2         :1;                                       /* Output Drive Strength Selection, bit 2 */
02867     byte DS3         :1;                                       /* Output Drive Strength Selection, bit 3 */
02868     byte DS4         :1;                                       /* Output Drive Strength Selection, bit 4 */
02869     byte DS5         :1;                                       /* Output Drive Strength Selection, bit 5 */
02870     byte DS6         :1;                                       /* Output Drive Strength Selection, bit 6 */
02871     byte DS7         :1;                                       /* Output Drive Strength Selection, bit 7 */
02872   } Bits;
02873 } PC0DSSTR;
02874 extern volatile PC0DSSTR _PC0DS @0xFFFF80E2;
02875 #define PC0DS                           _PC0DS.Byte
02876 #define PC0DS_DS0                       _PC0DS.Bits.DS0
02877 #define PC0DS_DS1                       _PC0DS.Bits.DS1
02878 #define PC0DS_DS2                       _PC0DS.Bits.DS2
02879 #define PC0DS_DS3                       _PC0DS.Bits.DS3
02880 #define PC0DS_DS4                       _PC0DS.Bits.DS4
02881 #define PC0DS_DS5                       _PC0DS.Bits.DS5
02882 #define PC0DS_DS6                       _PC0DS.Bits.DS6
02883 #define PC0DS_DS7                       _PC0DS.Bits.DS7
02884 
02885 #define PC0DS_DS0_MASK                  1U
02886 #define PC0DS_DS1_MASK                  2U
02887 #define PC0DS_DS2_MASK                  4U
02888 #define PC0DS_DS3_MASK                  8U
02889 #define PC0DS_DS4_MASK                  16U
02890 #define PC0DS_DS5_MASK                  32U
02891 #define PC0DS_DS6_MASK                  64U
02892 #define PC0DS_DS7_MASK                  128U
02893 
02894 
02895 /*** PC0IFE - Input Filter Enable Register; 0xFFFF80E3 ***/
02896 typedef union {
02897   byte Byte;
02898   struct {
02899     byte IFE0        :1;                                       /* Input Filter Enable, bit 0 */
02900     byte IFE1        :1;                                       /* Input Filter Enable, bit 1 */
02901     byte IFE2        :1;                                       /* Input Filter Enable, bit 2 */
02902     byte IFE3        :1;                                       /* Input Filter Enable, bit 3 */
02903     byte IFE4        :1;                                       /* Input Filter Enable, bit 4 */
02904     byte IFE5        :1;                                       /* Input Filter Enable, bit 5 */
02905     byte IFE6        :1;                                       /* Input Filter Enable, bit 6 */
02906     byte IFE7        :1;                                       /* Input Filter Enable, bit 7 */
02907   } Bits;
02908 } PC0IFESTR;
02909 extern volatile PC0IFESTR _PC0IFE @0xFFFF80E3;
02910 #define PC0IFE                          _PC0IFE.Byte
02911 #define PC0IFE_IFE0                     _PC0IFE.Bits.IFE0
02912 #define PC0IFE_IFE1                     _PC0IFE.Bits.IFE1
02913 #define PC0IFE_IFE2                     _PC0IFE.Bits.IFE2
02914 #define PC0IFE_IFE3                     _PC0IFE.Bits.IFE3
02915 #define PC0IFE_IFE4                     _PC0IFE.Bits.IFE4
02916 #define PC0IFE_IFE5                     _PC0IFE.Bits.IFE5
02917 #define PC0IFE_IFE6                     _PC0IFE.Bits.IFE6
02918 #define PC0IFE_IFE7                     _PC0IFE.Bits.IFE7
02919 
02920 #define PC0IFE_IFE0_MASK                1U
02921 #define PC0IFE_IFE1_MASK                2U
02922 #define PC0IFE_IFE2_MASK                4U
02923 #define PC0IFE_IFE3_MASK                8U
02924 #define PC0IFE_IFE4_MASK                16U
02925 #define PC0IFE_IFE5_MASK                32U
02926 #define PC0IFE_IFE6_MASK                64U
02927 #define PC0IFE_IFE7_MASK                128U
02928 
02929 
02930 /*** PC1PE - Pull Enable Register; 0xFFFF8100 ***/
02931 typedef union {
02932   byte Byte;
02933   struct {
02934     byte PE0         :1;                                       /* Internal Pull Enable, bit 0 */
02935     byte PE1         :1;                                       /* Internal Pull Enable, bit 1 */
02936     byte PE2         :1;                                       /* Internal Pull Enable, bit 2 */
02937     byte PE3         :1;                                       /* Internal Pull Enable, bit 3 */
02938     byte PE4         :1;                                       /* Internal Pull Enable, bit 4 */
02939     byte PE5         :1;                                       /* Internal Pull Enable, bit 5 */
02940     byte PE6         :1;                                       /* Internal Pull Enable, bit 6 */
02941     byte PE7         :1;                                       /* Internal Pull Enable, bit 7 */
02942   } Bits;
02943 } PC1PESTR;
02944 extern volatile PC1PESTR _PC1PE @0xFFFF8100;
02945 #define PC1PE                           _PC1PE.Byte
02946 #define PC1PE_PE0                       _PC1PE.Bits.PE0
02947 #define PC1PE_PE1                       _PC1PE.Bits.PE1
02948 #define PC1PE_PE2                       _PC1PE.Bits.PE2
02949 #define PC1PE_PE3                       _PC1PE.Bits.PE3
02950 #define PC1PE_PE4                       _PC1PE.Bits.PE4
02951 #define PC1PE_PE5                       _PC1PE.Bits.PE5
02952 #define PC1PE_PE6                       _PC1PE.Bits.PE6
02953 #define PC1PE_PE7                       _PC1PE.Bits.PE7
02954 
02955 #define PC1PE_PE0_MASK                  1U
02956 #define PC1PE_PE1_MASK                  2U
02957 #define PC1PE_PE2_MASK                  4U
02958 #define PC1PE_PE3_MASK                  8U
02959 #define PC1PE_PE4_MASK                  16U
02960 #define PC1PE_PE5_MASK                  32U
02961 #define PC1PE_PE6_MASK                  64U
02962 #define PC1PE_PE7_MASK                  128U
02963 
02964 
02965 /*** PC1SE - Slew Rate Enable Register; 0xFFFF8101 ***/
02966 typedef union {
02967   byte Byte;
02968   struct {
02969     byte SE0         :1;                                       /* Output Slew Rate Enable, bit 0 */
02970     byte SE1         :1;                                       /* Output Slew Rate Enable, bit 1 */
02971     byte SE2         :1;                                       /* Output Slew Rate Enable, bit 2 */
02972     byte SE3         :1;                                       /* Output Slew Rate Enable, bit 3 */
02973     byte SE4         :1;                                       /* Output Slew Rate Enable, bit 4 */
02974     byte SE5         :1;                                       /* Output Slew Rate Enable, bit 5 */
02975     byte SE6         :1;                                       /* Output Slew Rate Enable, bit 6 */
02976     byte SE7         :1;                                       /* Output Slew Rate Enable, bit 7 */
02977   } Bits;
02978 } PC1SESTR;
02979 extern volatile PC1SESTR _PC1SE @0xFFFF8101;
02980 #define PC1SE                           _PC1SE.Byte
02981 #define PC1SE_SE0                       _PC1SE.Bits.SE0
02982 #define PC1SE_SE1                       _PC1SE.Bits.SE1
02983 #define PC1SE_SE2                       _PC1SE.Bits.SE2
02984 #define PC1SE_SE3                       _PC1SE.Bits.SE3
02985 #define PC1SE_SE4                       _PC1SE.Bits.SE4
02986 #define PC1SE_SE5                       _PC1SE.Bits.SE5
02987 #define PC1SE_SE6                       _PC1SE.Bits.SE6
02988 #define PC1SE_SE7                       _PC1SE.Bits.SE7
02989 
02990 #define PC1SE_SE0_MASK                  1U
02991 #define PC1SE_SE1_MASK                  2U
02992 #define PC1SE_SE2_MASK                  4U
02993 #define PC1SE_SE3_MASK                  8U
02994 #define PC1SE_SE4_MASK                  16U
02995 #define PC1SE_SE5_MASK                  32U
02996 #define PC1SE_SE6_MASK                  64U
02997 #define PC1SE_SE7_MASK                  128U
02998 
02999 
03000 /*** PC1DS - Drive Strength Selection Register; 0xFFFF8102 ***/
03001 typedef union {
03002   byte Byte;
03003   struct {
03004     byte DS0         :1;                                       /* Output Drive Strength Selection, bit 0 */
03005     byte DS1         :1;                                       /* Output Drive Strength Selection, bit 1 */
03006     byte DS2         :1;                                       /* Output Drive Strength Selection, bit 2 */
03007     byte DS3         :1;                                       /* Output Drive Strength Selection, bit 3 */
03008     byte DS4         :1;                                       /* Output Drive Strength Selection, bit 4 */
03009     byte DS5         :1;                                       /* Output Drive Strength Selection, bit 5 */
03010     byte DS6         :1;                                       /* Output Drive Strength Selection, bit 6 */
03011     byte DS7         :1;                                       /* Output Drive Strength Selection, bit 7 */
03012   } Bits;
03013 } PC1DSSTR;
03014 extern volatile PC1DSSTR _PC1DS @0xFFFF8102;
03015 #define PC1DS                           _PC1DS.Byte
03016 #define PC1DS_DS0                       _PC1DS.Bits.DS0
03017 #define PC1DS_DS1                       _PC1DS.Bits.DS1
03018 #define PC1DS_DS2                       _PC1DS.Bits.DS2
03019 #define PC1DS_DS3                       _PC1DS.Bits.DS3
03020 #define PC1DS_DS4                       _PC1DS.Bits.DS4
03021 #define PC1DS_DS5                       _PC1DS.Bits.DS5
03022 #define PC1DS_DS6                       _PC1DS.Bits.DS6
03023 #define PC1DS_DS7                       _PC1DS.Bits.DS7
03024 
03025 #define PC1DS_DS0_MASK                  1U
03026 #define PC1DS_DS1_MASK                  2U
03027 #define PC1DS_DS2_MASK                  4U
03028 #define PC1DS_DS3_MASK                  8U
03029 #define PC1DS_DS4_MASK                  16U
03030 #define PC1DS_DS5_MASK                  32U
03031 #define PC1DS_DS6_MASK                  64U
03032 #define PC1DS_DS7_MASK                  128U
03033 
03034 
03035 /*** PC1IFE - Input Filter Enable Register; 0xFFFF8103 ***/
03036 typedef union {
03037   byte Byte;
03038   struct {
03039     byte IFE0        :1;                                       /* Input Filter Enable, bit 0 */
03040     byte IFE1        :1;                                       /* Input Filter Enable, bit 1 */
03041     byte IFE2        :1;                                       /* Input Filter Enable, bit 2 */
03042     byte IFE3        :1;                                       /* Input Filter Enable, bit 3 */
03043     byte IFE4        :1;                                       /* Input Filter Enable, bit 4 */
03044     byte IFE5        :1;                                       /* Input Filter Enable, bit 5 */
03045     byte IFE6        :1;                                       /* Input Filter Enable, bit 6 */
03046     byte IFE7        :1;                                       /* Input Filter Enable, bit 7 */
03047   } Bits;
03048 } PC1IFESTR;
03049 extern volatile PC1IFESTR _PC1IFE @0xFFFF8103;
03050 #define PC1IFE                          _PC1IFE.Byte
03051 #define PC1IFE_IFE0                     _PC1IFE.Bits.IFE0
03052 #define PC1IFE_IFE1                     _PC1IFE.Bits.IFE1
03053 #define PC1IFE_IFE2                     _PC1IFE.Bits.IFE2
03054 #define PC1IFE_IFE3                     _PC1IFE.Bits.IFE3
03055 #define PC1IFE_IFE4                     _PC1IFE.Bits.IFE4
03056 #define PC1IFE_IFE5                     _PC1IFE.Bits.IFE5
03057 #define PC1IFE_IFE6                     _PC1IFE.Bits.IFE6
03058 #define PC1IFE_IFE7                     _PC1IFE.Bits.IFE7
03059 
03060 #define PC1IFE_IFE0_MASK                1U
03061 #define PC1IFE_IFE1_MASK                2U
03062 #define PC1IFE_IFE2_MASK                4U
03063 #define PC1IFE_IFE3_MASK                8U
03064 #define PC1IFE_IFE4_MASK                16U
03065 #define PC1IFE_IFE5_MASK                32U
03066 #define PC1IFE_IFE6_MASK                64U
03067 #define PC1IFE_IFE7_MASK                128U
03068 
03069 
03070 /*** TPMSC - TPM Status and Control Register; 0xFFFF8120 ***/
03071 typedef union {
03072   byte Byte;
03073   struct {
03074     byte PS0         :1;                                       /* Prescale Divisor Select Bit 0 */
03075     byte PS1         :1;                                       /* Prescale Divisor Select Bit 1 */
03076     byte PS2         :1;                                       /* Prescale Divisor Select Bit 2 */
03077     byte CLKSA       :1;                                       /* Clock Source Select A */
03078     byte CLKSB       :1;                                       /* Clock Source Select B */
03079     byte CPWMS       :1;                                       /* Center-Aligned PWM Select */
03080     byte TOIE        :1;                                       /* Timer Overflow Interrupt Enable */
03081     byte TOF         :1;                                       /* Timer Overflow Flag */
03082   } Bits;
03083   struct {
03084     byte grpPS   :3;
03085     byte grpCLKSx :2;
03086     byte         :1;
03087     byte         :1;
03088     byte         :1;
03089   } MergedBits;
03090 } TPMSCSTR;
03091 extern volatile TPMSCSTR _TPMSC @0xFFFF8120;
03092 #define TPMSC                           _TPMSC.Byte
03093 #define TPMSC_PS0                       _TPMSC.Bits.PS0
03094 #define TPMSC_PS1                       _TPMSC.Bits.PS1
03095 #define TPMSC_PS2                       _TPMSC.Bits.PS2
03096 #define TPMSC_CLKSA                     _TPMSC.Bits.CLKSA
03097 #define TPMSC_CLKSB                     _TPMSC.Bits.CLKSB
03098 #define TPMSC_CPWMS                     _TPMSC.Bits.CPWMS
03099 #define TPMSC_TOIE                      _TPMSC.Bits.TOIE
03100 #define TPMSC_TOF                       _TPMSC.Bits.TOF
03101 #define TPMSC_PS                        _TPMSC.MergedBits.grpPS
03102 #define TPMSC_CLKSx                     _TPMSC.MergedBits.grpCLKSx
03103 
03104 #define TPMSC_PS0_MASK                  1U
03105 #define TPMSC_PS1_MASK                  2U
03106 #define TPMSC_PS2_MASK                  4U
03107 #define TPMSC_CLKSA_MASK                8U
03108 #define TPMSC_CLKSB_MASK                16U
03109 #define TPMSC_CPWMS_MASK                32U
03110 #define TPMSC_TOIE_MASK                 64U
03111 #define TPMSC_TOF_MASK                  128U
03112 #define TPMSC_PS_MASK                   7U
03113 #define TPMSC_PS_BITNUM                 0U
03114 #define TPMSC_CLKSx_MASK                24U
03115 #define TPMSC_CLKSx_BITNUM              3U
03116 
03117 
03118 /*** TPMCNT - TPM Timer Counter Register; 0xFFFF8121 ***/
03119 typedef union {
03120   word Word;
03121    /* Overlapped registers: */
03122   struct {
03123     /*** TPMCNTH - TPM Timer Counter Register High; 0xFFFF8121 ***/
03124     union {
03125       byte Byte;
03126     } TPMCNTHSTR;
03127     #define TPMCNTH                     _TPMCNT.Overlap_STR.TPMCNTHSTR.Byte
03128     
03129 
03130     /*** TPMCNTL - TPM Timer Counter Register Low; 0xFFFF8122 ***/
03131     union {
03132       byte Byte;
03133     } TPMCNTLSTR;
03134     #define TPMCNTL                     _TPMCNT.Overlap_STR.TPMCNTLSTR.Byte
03135     
03136   } Overlap_STR;
03137 
03138 } TPMCNTSTR;
03139 extern volatile TPMCNTSTR _TPMCNT @0xFFFF8121;
03140 #define TPMCNT                          _TPMCNT.Word
03141 
03142 
03143 /*** TPMMOD - TPM Timer Counter Modulo Register; 0xFFFF8123 ***/
03144 typedef union {
03145   word Word;
03146    /* Overlapped registers: */
03147   struct {
03148     /*** TPMMODH - TPM Timer Counter Modulo Register High; 0xFFFF8123 ***/
03149     union {
03150       byte Byte;
03151     } TPMMODHSTR;
03152     #define TPMMODH                     _TPMMOD.Overlap_STR.TPMMODHSTR.Byte
03153     
03154 
03155     /*** TPMMODL - TPM Timer Counter Modulo Register Low; 0xFFFF8124 ***/
03156     union {
03157       byte Byte;
03158     } TPMMODLSTR;
03159     #define TPMMODL                     _TPMMOD.Overlap_STR.TPMMODLSTR.Byte
03160     
03161   } Overlap_STR;
03162 
03163 } TPMMODSTR;
03164 extern volatile TPMMODSTR _TPMMOD @0xFFFF8123;
03165 #define TPMMOD                          _TPMMOD.Word
03166 
03167 
03168 /*** TPMC0SC - TPM Timer Channel 0 Status and Control Register; 0xFFFF8125 ***/
03169 typedef union {
03170   byte Byte;
03171   struct {
03172     byte             :1; 
03173     byte             :1; 
03174     byte ELS0A       :1;                                       /* Edge/Level Select Bit A */
03175     byte ELS0B       :1;                                       /* Edge/Level Select Bit B */
03176     byte MS0A        :1;                                       /* Mode Select A for TPM Channel 0 */
03177     byte MS0B        :1;                                       /* Mode Select B for TPM Channel 0 */
03178     byte CH0IE       :1;                                       /* Channel 0 Interrupt Enable */
03179     byte CH0F        :1;                                       /* Channel 0 Flag */
03180   } Bits;
03181   struct {
03182     byte         :1;
03183     byte         :1;
03184     byte grpELS0x :2;
03185     byte grpMS0x :2;
03186     byte         :1;
03187     byte         :1;
03188   } MergedBits;
03189 } TPMC0SCSTR;
03190 extern volatile TPMC0SCSTR _TPMC0SC @0xFFFF8125;
03191 #define TPMC0SC                         _TPMC0SC.Byte
03192 #define TPMC0SC_ELS0A                   _TPMC0SC.Bits.ELS0A
03193 #define TPMC0SC_ELS0B                   _TPMC0SC.Bits.ELS0B
03194 #define TPMC0SC_MS0A                    _TPMC0SC.Bits.MS0A
03195 #define TPMC0SC_MS0B                    _TPMC0SC.Bits.MS0B
03196 #define TPMC0SC_CH0IE                   _TPMC0SC.Bits.CH0IE
03197 #define TPMC0SC_CH0F                    _TPMC0SC.Bits.CH0F
03198 #define TPMC0SC_ELS0x                   _TPMC0SC.MergedBits.grpELS0x
03199 #define TPMC0SC_MS0x                    _TPMC0SC.MergedBits.grpMS0x
03200 
03201 #define TPMC0SC_ELS0A_MASK              4U
03202 #define TPMC0SC_ELS0B_MASK              8U
03203 #define TPMC0SC_MS0A_MASK               16U
03204 #define TPMC0SC_MS0B_MASK               32U
03205 #define TPMC0SC_CH0IE_MASK              64U
03206 #define TPMC0SC_CH0F_MASK               128U
03207 #define TPMC0SC_ELS0x_MASK              12U
03208 #define TPMC0SC_ELS0x_BITNUM            2U
03209 #define TPMC0SC_MS0x_MASK               48U
03210 #define TPMC0SC_MS0x_BITNUM             4U
03211 
03212 
03213 /*** TPMC0V - TPM Timer Channel 0 Value Register; 0xFFFF8126 ***/
03214 typedef union {
03215   word Word;
03216    /* Overlapped registers: */
03217   struct {
03218     /*** TPMC0VH - TPM Timer Channel 0 Value Register High; 0xFFFF8126 ***/
03219     union {
03220       byte Byte;
03221     } TPMC0VHSTR;
03222     #define TPMC0VH                     _TPMC0V.Overlap_STR.TPMC0VHSTR.Byte
03223     
03224 
03225     /*** TPMC0VL - TPM Timer Channel 0 Value Register Low; 0xFFFF8127 ***/
03226     union {
03227       byte Byte;
03228     } TPMC0VLSTR;
03229     #define TPMC0VL                     _TPMC0V.Overlap_STR.TPMC0VLSTR.Byte
03230     
03231   } Overlap_STR;
03232 
03233 } TPMC0VSTR;
03234 extern volatile TPMC0VSTR _TPMC0V @0xFFFF8126;
03235 #define TPMC0V                          _TPMC0V.Word
03236 
03237 
03238 /*** TPMC1SC - TPM Timer Channel 1 Status and Control Register; 0xFFFF8128 ***/
03239 typedef union {
03240   byte Byte;
03241   struct {
03242     byte             :1; 
03243     byte             :1; 
03244     byte ELS1A       :1;                                       /* Edge/Level Select Bit A */
03245     byte ELS1B       :1;                                       /* Edge/Level Select Bit B */
03246     byte MS1A        :1;                                       /* Mode Select A for TPM Channel 1 */
03247     byte MS1B        :1;                                       /* Mode Select B for TPM Channel 1 */
03248     byte CH1IE       :1;                                       /* Channel 1 Interrupt Enable */
03249     byte CH1F        :1;                                       /* Channel 1 Flag */
03250   } Bits;
03251   struct {
03252     byte         :1;
03253     byte         :1;
03254     byte grpELS1x :2;
03255     byte grpMS1x :2;
03256     byte         :1;
03257     byte         :1;
03258   } MergedBits;
03259 } TPMC1SCSTR;
03260 extern volatile TPMC1SCSTR _TPMC1SC @0xFFFF8128;
03261 #define TPMC1SC                         _TPMC1SC.Byte
03262 #define TPMC1SC_ELS1A                   _TPMC1SC.Bits.ELS1A
03263 #define TPMC1SC_ELS1B                   _TPMC1SC.Bits.ELS1B
03264 #define TPMC1SC_MS1A                    _TPMC1SC.Bits.MS1A
03265 #define TPMC1SC_MS1B                    _TPMC1SC.Bits.MS1B
03266 #define TPMC1SC_CH1IE                   _TPMC1SC.Bits.CH1IE
03267 #define TPMC1SC_CH1F                    _TPMC1SC.Bits.CH1F
03268 #define TPMC1SC_ELS1x                   _TPMC1SC.MergedBits.grpELS1x
03269 #define TPMC1SC_MS1x                    _TPMC1SC.MergedBits.grpMS1x
03270 
03271 #define TPMC1SC_ELS1A_MASK              4U
03272 #define TPMC1SC_ELS1B_MASK              8U
03273 #define TPMC1SC_MS1A_MASK               16U
03274 #define TPMC1SC_MS1B_MASK               32U
03275 #define TPMC1SC_CH1IE_MASK              64U
03276 #define TPMC1SC_CH1F_MASK               128U
03277 #define TPMC1SC_ELS1x_MASK              12U
03278 #define TPMC1SC_ELS1x_BITNUM            2U
03279 #define TPMC1SC_MS1x_MASK               48U
03280 #define TPMC1SC_MS1x_BITNUM             4U
03281 
03282 
03283 /*** TPMC1V - TPM Timer Channel 1 Value Register; 0xFFFF8129 ***/
03284 typedef union {
03285   word Word;
03286    /* Overlapped registers: */
03287   struct {
03288     /*** TPMC1VH - TPM Timer Channel 1 Value Register High; 0xFFFF8129 ***/
03289     union {
03290       byte Byte;
03291     } TPMC1VHSTR;
03292     #define TPMC1VH                     _TPMC1V.Overlap_STR.TPMC1VHSTR.Byte
03293     
03294 
03295     /*** TPMC1VL - TPM Timer Channel 1 Value Register Low; 0xFFFF812A ***/
03296     union {
03297       byte Byte;
03298     } TPMC1VLSTR;
03299     #define TPMC1VL                     _TPMC1V.Overlap_STR.TPMC1VLSTR.Byte
03300     
03301   } Overlap_STR;
03302 
03303 } TPMC1VSTR;
03304 extern volatile TPMC1VSTR _TPMC1V @0xFFFF8129;
03305 #define TPMC1V                          _TPMC1V.Word
03306 
03307 
03308 /*** PDB_SCR - PDB Status and Control Register; 0xFFFFEC00 ***/
03309 typedef union {
03310   word Word;
03311   struct {
03312     word EN          :1;                                       /* Module Enable */
03313     word TRIGSEL0    :1;                                       /* Input Trigger Select, bit 0 */
03314     word TRIGSEL1    :1;                                       /* Input Trigger Select, bit 1 */
03315     word SWTRIG      :1;                                       /* Software Trigger */
03316     word CONT        :1;                                       /* Continuous Mode Enable */
03317     word AOS0        :1;                                       /* A Output Select, bit 0 */
03318     word AOS1        :1;                                       /* A Output Select, bit 1 */
03319     word BOS0        :1;                                       /* B Output Select, bit 0 */
03320     word BOS1        :1;                                       /* B Output Select, bit 1 */
03321     word IENA        :1;                                       /* Interrupt Enable A */
03322     word IENB        :1;                                       /* Interrupt Enable B */
03323     word SA          :1;                                       /* Sticky A */
03324     word SB          :1;                                       /* Sticky B */
03325     word PRESCALER0  :1;                                       /* Clock Prescaler Select, bit 0 */
03326     word PRESCALER1  :1;                                       /* Clock Prescaler Select, bit 1 */
03327     word PRESCALER2  :1;                                       /* Clock Prescaler Select, bit 2 */
03328   } Bits;
03329   struct {
03330     word         :1;
03331     word grpTRIGSEL :2;
03332     word         :1;
03333     word         :1;
03334     word grpAOS  :2;
03335     word grpBOS  :2;
03336     word grpIENx :2;
03337     word grpSx   :2;
03338     word grpPRESCALER :3;
03339   } MergedBits;
03340 } PDB_SCRSTR;
03341 extern volatile PDB_SCRSTR _PDB_SCR @0xFFFFEC00;
03342 #define PDB_SCR                         _PDB_SCR.Word
03343 #define PDB_SCR_EN                      _PDB_SCR.Bits.EN
03344 #define PDB_SCR_TRIGSEL0                _PDB_SCR.Bits.TRIGSEL0
03345 #define PDB_SCR_TRIGSEL1                _PDB_SCR.Bits.TRIGSEL1
03346 #define PDB_SCR_SWTRIG                  _PDB_SCR.Bits.SWTRIG
03347 #define PDB_SCR_CONT                    _PDB_SCR.Bits.CONT
03348 #define PDB_SCR_AOS0                    _PDB_SCR.Bits.AOS0
03349 #define PDB_SCR_AOS1                    _PDB_SCR.Bits.AOS1
03350 #define PDB_SCR_BOS0                    _PDB_SCR.Bits.BOS0
03351 #define PDB_SCR_BOS1                    _PDB_SCR.Bits.BOS1
03352 #define PDB_SCR_IENA                    _PDB_SCR.Bits.IENA
03353 #define PDB_SCR_IENB                    _PDB_SCR.Bits.IENB
03354 #define PDB_SCR_SA                      _PDB_SCR.Bits.SA
03355 #define PDB_SCR_SB                      _PDB_SCR.Bits.SB
03356 #define PDB_SCR_PRESCALER0              _PDB_SCR.Bits.PRESCALER0
03357 #define PDB_SCR_PRESCALER1              _PDB_SCR.Bits.PRESCALER1
03358 #define PDB_SCR_PRESCALER2              _PDB_SCR.Bits.PRESCALER2
03359 #define PDB_SCR_TRIGSEL                 _PDB_SCR.MergedBits.grpTRIGSEL
03360 #define PDB_SCR_AOS                     _PDB_SCR.MergedBits.grpAOS
03361 #define PDB_SCR_BOS                     _PDB_SCR.MergedBits.grpBOS
03362 #define PDB_SCR_IENx                    _PDB_SCR.MergedBits.grpIENx
03363 #define PDB_SCR_Sx                      _PDB_SCR.MergedBits.grpSx
03364 #define PDB_SCR_PRESCALER               _PDB_SCR.MergedBits.grpPRESCALER
03365 
03366 #define PDB_SCR_EN_MASK                 1U
03367 #define PDB_SCR_TRIGSEL0_MASK           2U
03368 #define PDB_SCR_TRIGSEL1_MASK           4U
03369 #define PDB_SCR_SWTRIG_MASK             8U
03370 #define PDB_SCR_CONT_MASK               16U
03371 #define PDB_SCR_AOS0_MASK               32U
03372 #define PDB_SCR_AOS1_MASK               64U
03373 #define PDB_SCR_BOS0_MASK               128U
03374 #define PDB_SCR_BOS1_MASK               256U
03375 #define PDB_SCR_IENA_MASK               512U
03376 #define PDB_SCR_IENB_MASK               1024U
03377 #define PDB_SCR_SA_MASK                 2048U
03378 #define PDB_SCR_SB_MASK                 4096U
03379 #define PDB_SCR_PRESCALER0_MASK         8192U
03380 #define PDB_SCR_PRESCALER1_MASK         16384U
03381 #define PDB_SCR_PRESCALER2_MASK         32768U
03382 #define PDB_SCR_TRIGSEL_MASK            6U
03383 #define PDB_SCR_TRIGSEL_BITNUM          1U
03384 #define PDB_SCR_AOS_MASK                96U
03385 #define PDB_SCR_AOS_BITNUM              5U
03386 #define PDB_SCR_BOS_MASK                384U
03387 #define PDB_SCR_BOS_BITNUM              7U
03388 #define PDB_SCR_IENx_MASK               1536U
03389 #define PDB_SCR_IENx_BITNUM             9U
03390 #define PDB_SCR_Sx_MASK                 6144U
03391 #define PDB_SCR_Sx_BITNUM               11U
03392 #define PDB_SCR_PRESCALER_MASK          57344U
03393 #define PDB_SCR_PRESCALER_BITNUM        13U
03394 
03395 
03396 /*** PDB_DELAYA - PDB Delay A Register; 0xFFFFEC02 ***/
03397 typedef union {
03398   word Word;
03399 } PDB_DELAYASTR;
03400 extern volatile PDB_DELAYASTR _PDB_DELAYA @0xFFFFEC02;
03401 #define PDB_DELAYA                      _PDB_DELAYA.Word
03402 
03403 
03404 /*** PDB_DELAYB - PDB Delay B Register; 0xFFFFEC04 ***/
03405 typedef union {
03406   word Word;
03407 } PDB_DELAYBSTR;
03408 extern volatile PDB_DELAYBSTR _PDB_DELAYB @0xFFFFEC04;
03409 #define PDB_DELAYB                      _PDB_DELAYB.Word
03410 
03411 
03412 /*** PDB_MOD - PDB Counter Modulus Register; 0xFFFFEC06 ***/
03413 typedef union {
03414   word Word;
03415 } PDB_MODSTR;
03416 extern volatile PDB_MODSTR _PDB_MOD @0xFFFFEC06;
03417 #define PDB_MOD                         _PDB_MOD.Word
03418 
03419 
03420 /*** PDB_COUNT - PDB Counter Value Register; 0xFFFFEC08 ***/
03421 typedef union {
03422   word Word;
03423 } PDB_COUNTSTR;
03424 extern volatile PDB_COUNTSTR _PDB_COUNT @0xFFFFEC08;
03425 #define PDB_COUNT                       _PDB_COUNT.Word
03426 
03427 
03428 /*** FOPT - Flash Options Register; 0xFFFFEC20 ***/
03429 typedef union {
03430   word Word;
03431   struct {
03432     word SSC0        :1;                                       /* Security State Bit 0 */
03433     word SSC1        :1;                                       /* Security State Bit 1 */
03434     word SSW         :1;                                       /* Security State Writable */
03435     word             :1; 
03436     word PROTB       :1;                                       /* Active Low Write Protect */
03437     word PW          :1;                                       /* PROTB Writable */
03438     word             :1; 
03439     word             :1; 
03440     word CHECKB0     :1;                                       /* Perform Flash Checksum Bit0 */
03441     word CHECKB1     :1;                                       /* Perform Flash Checksum Bit1 */
03442     word MECFB       :1;                                       /* Mass Erase on CRC Failure */
03443     word             :1; 
03444     word             :1; 
03445     word BF          :1;                                       /* Boot from FLASH */
03446     word             :1; 
03447     word CSR1        :1;                                       /* Clear Security Request Bit */
03448   } Bits;
03449   struct {
03450     word grpSSC  :2;
03451     word         :1;
03452     word         :1;
03453     word         :1;
03454     word         :1;
03455     word         :1;
03456     word         :1;
03457     word grpCHECKB :2;
03458     word         :1;
03459     word         :1;
03460     word         :1;
03461     word         :1;
03462     word         :1;
03463     word grpCSR_1 :1;
03464   } MergedBits;
03465 } FOPTSTR;
03466 extern volatile FOPTSTR _FOPT @0xFFFFEC20;
03467 #define FOPT                            _FOPT.Word
03468 #define FOPT_SSC0                       _FOPT.Bits.SSC0
03469 #define FOPT_SSC1                       _FOPT.Bits.SSC1
03470 #define FOPT_SSW                        _FOPT.Bits.SSW
03471 #define FOPT_PROTB                      _FOPT.Bits.PROTB
03472 #define FOPT_PW                         _FOPT.Bits.PW
03473 #define FOPT_CHECKB0                    _FOPT.Bits.CHECKB0
03474 #define FOPT_CHECKB1                    _FOPT.Bits.CHECKB1
03475 #define FOPT_MECFB                      _FOPT.Bits.MECFB
03476 #define FOPT_BF                         _FOPT.Bits.BF
03477 #define FOPT_CSR1                       _FOPT.Bits.CSR1
03478 #define FOPT_SSC                        _FOPT.MergedBits.grpSSC
03479 #define FOPT_CHECKB                     _FOPT.MergedBits.grpCHECKB
03480 
03481 #define FOPT_SSC0_MASK                  1U
03482 #define FOPT_SSC1_MASK                  2U
03483 #define FOPT_SSW_MASK                   4U
03484 #define FOPT_PROTB_MASK                 16U
03485 #define FOPT_PW_MASK                    32U
03486 #define FOPT_CHECKB0_MASK               256U
03487 #define FOPT_CHECKB1_MASK               512U
03488 #define FOPT_MECFB_MASK                 1024U
03489 #define FOPT_BF_MASK                    8192U
03490 #define FOPT_CSR1_MASK                  32768U
03491 #define FOPT_SSC_MASK                   3U
03492 #define FOPT_SSC_BITNUM                 0U
03493 #define FOPT_CHECKB_MASK                768U
03494 #define FOPT_CHECKB_BITNUM              8U
03495 
03496 
03497 /*** FLCSR - Flash Control and Status Register; 0xFFFFEC22 ***/
03498 typedef union {
03499   word Word;
03500   struct {
03501     word PROG        :1;                                       /* Program Control bit */
03502     word ERASE       :1;                                       /* Page Erase Control bit */
03503     word MAS1        :1;                                       /* Mass erase control bit */
03504     word NVSTR       :1;                                       /* Information block enable */
03505     word IFREN       :1;                                       /* Information block enable */
03506     word             :1; 
03507     word             :1; 
03508     word ERR         :1;                                       /* Access error violation */
03509     word XE          :1;                                       /* X address enable */
03510     word YE          :1;                                       /* Y address enable */
03511     word SE          :1;                                       /* Sense amplifier enable */
03512     word TMR         :1;                                       /* Register reset for flash test mode */
03513     word             :1; 
03514     word             :1; 
03515     word TMPEN       :1;                                       /* TM Signals Routing to Pad Enable */
03516     word FTME        :1;                                       /* Flash Test Mode Enable */
03517   } Bits;
03518 } FLCSRSTR;
03519 extern volatile FLCSRSTR _FLCSR @0xFFFFEC22;
03520 #define FLCSR                           _FLCSR.Word
03521 #define FLCSR_PROG                      _FLCSR.Bits.PROG
03522 #define FLCSR_ERASE                     _FLCSR.Bits.ERASE
03523 #define FLCSR_MAS1                      _FLCSR.Bits.MAS1
03524 #define FLCSR_NVSTR                     _FLCSR.Bits.NVSTR
03525 #define FLCSR_IFREN                     _FLCSR.Bits.IFREN
03526 #define FLCSR_ERR                       _FLCSR.Bits.ERR
03527 #define FLCSR_XE                        _FLCSR.Bits.XE
03528 #define FLCSR_YE                        _FLCSR.Bits.YE
03529 #define FLCSR_SE                        _FLCSR.Bits.SE
03530 #define FLCSR_TMR                       _FLCSR.Bits.TMR
03531 #define FLCSR_TMPEN                     _FLCSR.Bits.TMPEN
03532 #define FLCSR_FTME                      _FLCSR.Bits.FTME
03533 
03534 #define FLCSR_PROG_MASK                 1U
03535 #define FLCSR_ERASE_MASK                2U
03536 #define FLCSR_MAS1_MASK                 4U
03537 #define FLCSR_NVSTR_MASK                8U
03538 #define FLCSR_IFREN_MASK                16U
03539 #define FLCSR_ERR_MASK                  128U
03540 #define FLCSR_XE_MASK                   256U
03541 #define FLCSR_YE_MASK                   512U
03542 #define FLCSR_SE_MASK                   1024U
03543 #define FLCSR_TMR_MASK                  2048U
03544 #define FLCSR_TMPEN_MASK                16384U
03545 #define FLCSR_FTME_MASK                 32768U
03546 
03547 
03548 /*** AFE_CSR - AFE Control and Status Register; 0xFFFFEC40 ***/
03549 typedef union {
03550   word Word;
03551   struct {
03552     word TT          :1;                                       /* Trigger Type */
03553     word SWTRIG      :1;                                       /* Software Trigger */
03554     word COCO        :1;                                       /* Conversion Complete */
03555     word CCIEN       :1;                                       /* Conversion Complete Interrupt Enable */
03556     word EP          :1;                                       /* Eve - Proton G-cell Select */
03557     word             :1; 
03558     word             :1; 
03559     word ST          :1;                                       /* Self Test Enable */
03560     word AAF         :1;                                       /* Low Power Mode Enable */
03561     word             :1; 
03562     word CM0         :1;                                       /* Conversion Mode, bit 0 */
03563     word CM1         :1;                                       /* Conversion Mode, bit 1 */
03564     word C4S0        :1;                                       /* Conversion 4 Selection, bit 0 */
03565     word C4S1        :1;                                       /* Conversion 4 Selection, bit 1 */
03566     word FS0         :1;                                       /* Full Scale Selection, bit 0 */
03567     word FS1         :1;                                       /* Full Scale Selection, bit 1 */
03568   } Bits;
03569   struct {
03570     word         :1;
03571     word         :1;
03572     word         :1;
03573     word         :1;
03574     word         :1;
03575     word         :1;
03576     word         :1;
03577     word         :1;
03578     word         :1;
03579     word         :1;
03580     word grpCM   :2;
03581     word grpC4S  :2;
03582     word grpFS   :2;
03583   } MergedBits;
03584 } AFE_CSRSTR;
03585 extern volatile AFE_CSRSTR _AFE_CSR @0xFFFFEC40;
03586 #define AFE_CSR                         _AFE_CSR.Word
03587 #define AFE_CSR_TT                      _AFE_CSR.Bits.TT
03588 #define AFE_CSR_SWTRIG                  _AFE_CSR.Bits.SWTRIG
03589 #define AFE_CSR_COCO                    _AFE_CSR.Bits.COCO
03590 #define AFE_CSR_CCIEN                   _AFE_CSR.Bits.CCIEN
03591 #define AFE_CSR_EP                      _AFE_CSR.Bits.EP
03592 #define AFE_CSR_ST                      _AFE_CSR.Bits.ST
03593 #define AFE_CSR_AAF                     _AFE_CSR.Bits.AAF
03594 #define AFE_CSR_CM0                     _AFE_CSR.Bits.CM0
03595 #define AFE_CSR_CM1                     _AFE_CSR.Bits.CM1
03596 #define AFE_CSR_C4S0                    _AFE_CSR.Bits.C4S0
03597 #define AFE_CSR_C4S1                    _AFE_CSR.Bits.C4S1
03598 #define AFE_CSR_FS0                     _AFE_CSR.Bits.FS0
03599 #define AFE_CSR_FS1                     _AFE_CSR.Bits.FS1
03600 #define AFE_CSR_CM                      _AFE_CSR.MergedBits.grpCM
03601 #define AFE_CSR_C4S                     _AFE_CSR.MergedBits.grpC4S
03602 #define AFE_CSR_FS                      _AFE_CSR.MergedBits.grpFS
03603 
03604 #define AFE_CSR_TT_MASK                 1U
03605 #define AFE_CSR_SWTRIG_MASK             2U
03606 #define AFE_CSR_COCO_MASK               4U
03607 #define AFE_CSR_CCIEN_MASK              8U
03608 #define AFE_CSR_EP_MASK                 16U
03609 #define AFE_CSR_ST_MASK                 128U
03610 #define AFE_CSR_AAF_MASK                256U
03611 #define AFE_CSR_CM0_MASK                1024U
03612 #define AFE_CSR_CM1_MASK                2048U
03613 #define AFE_CSR_C4S0_MASK               4096U
03614 #define AFE_CSR_C4S1_MASK               8192U
03615 #define AFE_CSR_FS0_MASK                16384U
03616 #define AFE_CSR_FS1_MASK                32768U
03617 #define AFE_CSR_CM_MASK                 3072U
03618 #define AFE_CSR_CM_BITNUM               10U
03619 #define AFE_CSR_C4S_MASK                12288U
03620 #define AFE_CSR_C4S_BITNUM              12U
03621 #define AFE_CSR_FS_MASK                 49152U
03622 #define AFE_CSR_FS_BITNUM               14U
03623 
03624 
03625 /*** AFE_XACC - X Acceleration Value; 0xFFFFEC42 ***/
03626 typedef union {
03627   word Word;
03628 } AFE_XACCSTR;
03629 extern volatile AFE_XACCSTR _AFE_XACC @0xFFFFEC42;
03630 #define AFE_XACC                        _AFE_XACC.Word
03631 
03632 
03633 /*** AFE_YACC - Y Acceleration Value; 0xFFFFEC44 ***/
03634 typedef union {
03635   word Word;
03636 } AFE_YACCSTR;
03637 extern volatile AFE_YACCSTR _AFE_YACC @0xFFFFEC44;
03638 #define AFE_YACC                        _AFE_YACC.Word
03639 
03640 
03641 /*** AFE_ZACC - Z Acceleration Value; 0xFFFFEC46 ***/
03642 typedef union {
03643   word Word;
03644 } AFE_ZACCSTR;
03645 extern volatile AFE_ZACCSTR _AFE_ZACC @0xFFFFEC46;
03646 #define AFE_ZACC                        _AFE_ZACC.Word
03647 
03648 
03649 /*** AFE_TEMP - Temperature Sensor Value; 0xFFFFEC48 ***/
03650 typedef union {
03651   word Word;
03652 } AFE_TEMPSTR;
03653 extern volatile AFE_TEMPSTR _AFE_TEMP @0xFFFFEC48;
03654 #define AFE_TEMP                        _AFE_TEMP.Word
03655 
03656 
03657 /*** AFE_EIC - External Input Voltage Result Register; 0xFFFFEC4A ***/
03658 typedef union {
03659   word Word;
03660 } AFE_EICSTR;
03661 extern volatile AFE_EICSTR _AFE_EIC @0xFFFFEC4A;
03662 #define AFE_EIC                         _AFE_EIC.Word
03663 
03664 
03665 /*** AFE_PRES - Pressure Result Register; 0xFFFFEC4C ***/
03666 typedef union {
03667   word Word;
03668 } AFE_PRESSTR;
03669 extern volatile AFE_PRESSTR _AFE_PRES @0xFFFFEC4C;
03670 #define AFE_PRES                        _AFE_PRES.Word
03671 
03672 
03673 /*** AFE_GAINX - X Acceleration Gain Trim Register; 0xFFFFEC50 ***/
03674 typedef union {
03675   word Word;
03676 } AFE_GAINXSTR;
03677 extern volatile AFE_GAINXSTR _AFE_GAINX @0xFFFFEC50;
03678 #define AFE_GAINX                       _AFE_GAINX.Word
03679 
03680 
03681 /*** AFE_GAINY - Y Acceleration Gain Trim Register; 0xFFFFEC52 ***/
03682 typedef union {
03683   word Word;
03684 } AFE_GAINYSTR;
03685 extern volatile AFE_GAINYSTR _AFE_GAINY @0xFFFFEC52;
03686 #define AFE_GAINY                       _AFE_GAINY.Word
03687 
03688 
03689 /*** AFE_GAINZ - Z Acceleration Gain Trim Register; 0xFFFFEC54 ***/
03690 typedef union {
03691   word Word;
03692 } AFE_GAINZSTR;
03693 extern volatile AFE_GAINZSTR _AFE_GAINZ @0xFFFFEC54;
03694 #define AFE_GAINZ                       _AFE_GAINZ.Word
03695 
03696 
03697 /*** AFE_OFFX - X Acceleration Offset Trim Register; 0xFFFFEC5C ***/
03698 typedef union {
03699   word Word;
03700 } AFE_OFFXSTR;
03701 extern volatile AFE_OFFXSTR _AFE_OFFX @0xFFFFEC5C;
03702 #define AFE_OFFX                        _AFE_OFFX.Word
03703 
03704 
03705 /*** AFE_OFFY - Y Acceleration Offset Trim Register; 0xFFFFEC5E ***/
03706 typedef union {
03707   word Word;
03708 } AFE_OFFYSTR;
03709 extern volatile AFE_OFFYSTR _AFE_OFFY @0xFFFFEC5E;
03710 #define AFE_OFFY                        _AFE_OFFY.Word
03711 
03712 
03713 /*** AFE_OFFZ - Z Acceleration Offset Trim Register; 0xFFFFEC60 ***/
03714 typedef union {
03715   word Word;
03716 } AFE_OFFZSTR;
03717 extern volatile AFE_OFFZSTR _AFE_OFFZ @0xFFFFEC60;
03718 #define AFE_OFFZ                        _AFE_OFFZ.Word
03719 
03720 
03721 /*** AFE_BIAS - DC Bias Trim Register; 0xFFFFEC68 ***/
03722 typedef union {
03723   word Word;
03724   struct {
03725     word IREF_TRIM0  :1;                                       /* Reserved */
03726     word IREF_TRIM1  :1;                                       /* Reserved */
03727     word IREF_TRIM2  :1;                                       /* Reserved */
03728     word IREF_TRIM3  :1;                                       /* Reserved */
03729     word IREF_TRIM4  :1;                                       /* Reserved */
03730     word             :1; 
03731     word             :1; 
03732     word             :1; 
03733     word             :1; 
03734     word             :1; 
03735     word             :1; 
03736     word POR_HYST_CTRL0 :1;                                    /* POR Hysteresis Control, bit 0 */
03737     word POR_HYST_CTRL1 :1;                                    /* POR Hysteresis Control, bit 1 */
03738     word OSC_SEL     :1;                                       /* Oscillator Select */
03739     word SPOL_TGL    :1;                                       /* Signal Chain Polarity Control */
03740     word SINGLE_EN   :1;                                       /* Single Mode Enable */
03741   } Bits;
03742   struct {
03743     word grpIREF_TRIM :5;
03744     word         :1;
03745     word         :1;
03746     word         :1;
03747     word         :1;
03748     word         :1;
03749     word         :1;
03750     word grpPOR_HYST_CTRL :2;
03751     word         :1;
03752     word         :1;
03753     word         :1;
03754   } MergedBits;
03755 } AFE_BIASSTR;
03756 extern volatile AFE_BIASSTR _AFE_BIAS @0xFFFFEC68;
03757 #define AFE_BIAS                        _AFE_BIAS.Word
03758 #define AFE_BIAS_IREF_TRIM0             _AFE_BIAS.Bits.IREF_TRIM0
03759 #define AFE_BIAS_IREF_TRIM1             _AFE_BIAS.Bits.IREF_TRIM1
03760 #define AFE_BIAS_IREF_TRIM2             _AFE_BIAS.Bits.IREF_TRIM2
03761 #define AFE_BIAS_IREF_TRIM3             _AFE_BIAS.Bits.IREF_TRIM3
03762 #define AFE_BIAS_IREF_TRIM4             _AFE_BIAS.Bits.IREF_TRIM4
03763 #define AFE_BIAS_POR_HYST_CTRL0         _AFE_BIAS.Bits.POR_HYST_CTRL0
03764 #define AFE_BIAS_POR_HYST_CTRL1         _AFE_BIAS.Bits.POR_HYST_CTRL1
03765 #define AFE_BIAS_OSC_SEL                _AFE_BIAS.Bits.OSC_SEL
03766 #define AFE_BIAS_SPOL_TGL               _AFE_BIAS.Bits.SPOL_TGL
03767 #define AFE_BIAS_SINGLE_EN              _AFE_BIAS.Bits.SINGLE_EN
03768 #define AFE_BIAS_IREF_TRIM              _AFE_BIAS.MergedBits.grpIREF_TRIM
03769 #define AFE_BIAS_POR_HYST_CTRL          _AFE_BIAS.MergedBits.grpPOR_HYST_CTRL
03770 
03771 #define AFE_BIAS_IREF_TRIM0_MASK        1U
03772 #define AFE_BIAS_IREF_TRIM1_MASK        2U
03773 #define AFE_BIAS_IREF_TRIM2_MASK        4U
03774 #define AFE_BIAS_IREF_TRIM3_MASK        8U
03775 #define AFE_BIAS_IREF_TRIM4_MASK        16U
03776 #define AFE_BIAS_POR_HYST_CTRL0_MASK    2048U
03777 #define AFE_BIAS_POR_HYST_CTRL1_MASK    4096U
03778 #define AFE_BIAS_OSC_SEL_MASK           8192U
03779 #define AFE_BIAS_SPOL_TGL_MASK          16384U
03780 #define AFE_BIAS_SINGLE_EN_MASK         32768U
03781 #define AFE_BIAS_IREF_TRIM_MASK         31U
03782 #define AFE_BIAS_IREF_TRIM_BITNUM       0U
03783 #define AFE_BIAS_POR_HYST_CTRL_MASK     6144U
03784 #define AFE_BIAS_POR_HYST_CTRL_BITNUM   11U
03785 
03786 
03787 /*** AFE_TEST1 - AFE Test Register 1; 0xFFFFEC70 ***/
03788 typedef union {
03789   word Word;
03790   struct {
03791     word ATM0        :1;                                       /* Analog Test Mode, bit 0 */
03792     word ATM1        :1;                                       /* Analog Test Mode, bit 1 */
03793     word ATM2        :1;                                       /* Analog Test Mode, bit 2 */
03794     word ATM3        :1;                                       /* Analog Test Mode, bit 3 */
03795     word ATM4        :1;                                       /* Analog Test Mode, bit 4 */
03796     word             :1; 
03797     word             :1; 
03798     word             :1; 
03799     word DTM0        :1;                                       /* Digital Test Mode, bit 0 */
03800     word DTM1        :1;                                       /* Digital Test Mode, bit 1 */
03801     word DTM2        :1;                                       /* Digital Test Mode, bit 2 */
03802     word DTM3        :1;                                       /* Digital Test Mode, bit 3 */
03803     word INT1_TCFG0  :1;                                       /* INT1 Test Configuration, bit 0 */
03804     word INT1_TCFG1  :1;                                       /* INT1 Test Configuration, bit 1 */
03805     word INT2_TCFG0  :1;                                       /* INT2 Test Configuration, bit 0 */
03806     word INT2_TCFG1  :1;                                       /* INT2 Test Configuration, bit 1 */
03807   } Bits;
03808   struct {
03809     word grpATM  :5;
03810     word         :1;
03811     word         :1;
03812     word         :1;
03813     word grpDTM  :4;
03814     word grpINT1_TCFG :2;
03815     word grpINT2_TCFG :2;
03816   } MergedBits;
03817 } AFE_TEST1STR;
03818 extern volatile AFE_TEST1STR _AFE_TEST1 @0xFFFFEC70;
03819 #define AFE_TEST1                       _AFE_TEST1.Word
03820 #define AFE_TEST1_ATM0                  _AFE_TEST1.Bits.ATM0
03821 #define AFE_TEST1_ATM1                  _AFE_TEST1.Bits.ATM1
03822 #define AFE_TEST1_ATM2                  _AFE_TEST1.Bits.ATM2
03823 #define AFE_TEST1_ATM3                  _AFE_TEST1.Bits.ATM3
03824 #define AFE_TEST1_ATM4                  _AFE_TEST1.Bits.ATM4
03825 #define AFE_TEST1_DTM0                  _AFE_TEST1.Bits.DTM0
03826 #define AFE_TEST1_DTM1                  _AFE_TEST1.Bits.DTM1
03827 #define AFE_TEST1_DTM2                  _AFE_TEST1.Bits.DTM2
03828 #define AFE_TEST1_DTM3                  _AFE_TEST1.Bits.DTM3
03829 #define AFE_TEST1_INT1_TCFG0            _AFE_TEST1.Bits.INT1_TCFG0
03830 #define AFE_TEST1_INT1_TCFG1            _AFE_TEST1.Bits.INT1_TCFG1
03831 #define AFE_TEST1_INT2_TCFG0            _AFE_TEST1.Bits.INT2_TCFG0
03832 #define AFE_TEST1_INT2_TCFG1            _AFE_TEST1.Bits.INT2_TCFG1
03833 #define AFE_TEST1_ATM                   _AFE_TEST1.MergedBits.grpATM
03834 #define AFE_TEST1_DTM                   _AFE_TEST1.MergedBits.grpDTM
03835 #define AFE_TEST1_INT1_TCFG             _AFE_TEST1.MergedBits.grpINT1_TCFG
03836 #define AFE_TEST1_INT2_TCFG             _AFE_TEST1.MergedBits.grpINT2_TCFG
03837 
03838 #define AFE_TEST1_ATM0_MASK             1U
03839 #define AFE_TEST1_ATM1_MASK             2U
03840 #define AFE_TEST1_ATM2_MASK             4U
03841 #define AFE_TEST1_ATM3_MASK             8U
03842 #define AFE_TEST1_ATM4_MASK             16U
03843 #define AFE_TEST1_DTM0_MASK             256U
03844 #define AFE_TEST1_DTM1_MASK             512U
03845 #define AFE_TEST1_DTM2_MASK             1024U
03846 #define AFE_TEST1_DTM3_MASK             2048U
03847 #define AFE_TEST1_INT1_TCFG0_MASK       4096U
03848 #define AFE_TEST1_INT1_TCFG1_MASK       8192U
03849 #define AFE_TEST1_INT2_TCFG0_MASK       16384U
03850 #define AFE_TEST1_INT2_TCFG1_MASK       32768U
03851 #define AFE_TEST1_ATM_MASK              31U
03852 #define AFE_TEST1_ATM_BITNUM            0U
03853 #define AFE_TEST1_DTM_MASK              3840U
03854 #define AFE_TEST1_DTM_BITNUM            8U
03855 #define AFE_TEST1_INT1_TCFG_MASK        12288U
03856 #define AFE_TEST1_INT1_TCFG_BITNUM      12U
03857 #define AFE_TEST1_INT2_TCFG_MASK        49152U
03858 #define AFE_TEST1_INT2_TCFG_BITNUM      14U
03859 
03860 
03861 /*** AFE_TEST2 - AFE Test Register 2; 0xFFFFEC72 ***/
03862 typedef union {
03863   word Word;
03864   struct {
03865     word CVIS0       :1;                                       /* C2V Input Select, bit 0 */
03866     word CVIS1       :1;                                       /* C2V Input Select, bit 1 */
03867     word INC_TEST    :1;                                       /* This bit controls c2v_inc_test port */
03868     word MM_EN       :1;                                       /* This bit controls c2v_mm_en port */
03869     word POL_FH      :1;                                       /* Polarity Force High */
03870     word CHOP_DIS    :1;                                       /* This bit disabled the chopping signal in the signal chain */
03871     word             :1; 
03872     word             :1; 
03873     word AAF_OFF     :1;                                       /* This bit provides a feature to disable AAF function */
03874     word C2V_OFF     :1;                                       /* C2V Block Off */
03875     word _2ND_OFF    :1;                                       /* 2nd State Block Off */
03876     word             :1; 
03877     word             :1; 
03878     word             :1; 
03879     word AAF_NOFIL   :1;                                       /* AAF No Filter */
03880     word POR_DIS     :1;                                       /* Power On Reset Disable */
03881   } Bits;
03882   struct {
03883     word grpCVIS :2;
03884     word         :1;
03885     word         :1;
03886     word         :1;
03887     word         :1;
03888     word         :1;
03889     word         :1;
03890     word         :1;
03891     word         :1;
03892     word         :1;
03893     word         :1;
03894     word         :1;
03895     word         :1;
03896     word         :1;
03897     word         :1;
03898   } MergedBits;
03899 } AFE_TEST2STR;
03900 extern volatile AFE_TEST2STR _AFE_TEST2 @0xFFFFEC72;
03901 #define AFE_TEST2                       _AFE_TEST2.Word
03902 #define AFE_TEST2_CVIS0                 _AFE_TEST2.Bits.CVIS0
03903 #define AFE_TEST2_CVIS1                 _AFE_TEST2.Bits.CVIS1
03904 #define AFE_TEST2_INC_TEST              _AFE_TEST2.Bits.INC_TEST
03905 #define AFE_TEST2_MM_EN                 _AFE_TEST2.Bits.MM_EN
03906 #define AFE_TEST2_POL_FH                _AFE_TEST2.Bits.POL_FH
03907 #define AFE_TEST2_CHOP_DIS              _AFE_TEST2.Bits.CHOP_DIS
03908 #define AFE_TEST2_AAF_OFF               _AFE_TEST2.Bits.AAF_OFF
03909 #define AFE_TEST2_C2V_OFF               _AFE_TEST2.Bits.C2V_OFF
03910 #define AFE_TEST2_2ND_OFF               _AFE_TEST2.Bits._2ND_OFF
03911 #define AFE_TEST2_AAF_NOFIL             _AFE_TEST2.Bits.AAF_NOFIL
03912 #define AFE_TEST2_POR_DIS               _AFE_TEST2.Bits.POR_DIS
03913 #define AFE_TEST2_CVIS                  _AFE_TEST2.MergedBits.grpCVIS
03914 
03915 #define AFE_TEST2_CVIS0_MASK            1U
03916 #define AFE_TEST2_CVIS1_MASK            2U
03917 #define AFE_TEST2_INC_TEST_MASK         4U
03918 #define AFE_TEST2_MM_EN_MASK            8U
03919 #define AFE_TEST2_POL_FH_MASK           16U
03920 #define AFE_TEST2_CHOP_DIS_MASK         32U
03921 #define AFE_TEST2_AAF_OFF_MASK          256U
03922 #define AFE_TEST2_C2V_OFF_MASK          512U
03923 #define AFE_TEST2_2ND_OFF_MASK          1024U
03924 #define AFE_TEST2_AAF_NOFIL_MASK        16384U
03925 #define AFE_TEST2_POR_DIS_MASK          32768U
03926 #define AFE_TEST2_CVIS_MASK             3U
03927 #define AFE_TEST2_CVIS_BITNUM           0U
03928 
03929 
03930 /*** AFE_TEST3 - AFE Test Register 3; 0xFFFFEC74 ***/
03931 typedef union {
03932   word Word;
03933   struct {
03934     word IREF_ON     :1;                                       /* IREF On */
03935     word VBG_ON      :1;                                       /* VBG On */
03936     word VREG_ON     :1;                                       /* VREG On */
03937     word OSC_ON      :1;                                       /* OSC On */
03938     word OSC_HF      :1;                                       /* OSC High Frequency */
03939     word             :1; 
03940     word             :1; 
03941     word IBIAS_SEL   :3;                                       /* Bias Current Select, bit 0 */
03942     word INV_OUT     :1;                                       /* Invert Digital Output */
03943     word SWAP_IN     :1;                                       /* ADC Input Swap Enable */
03944     word             :1; 
03945     word             :1; 
03946     word OVF_EN      :1;                                       /* ADC Overflow Enable */
03947     word SDO_EN      :1;                                       /* ADC Serial Data Output Enable */
03948   } Bits;
03949 } AFE_TEST3STR;
03950 extern volatile AFE_TEST3STR _AFE_TEST3 @0xFFFFEC74;
03951 #define AFE_TEST3                       _AFE_TEST3.Word
03952 #define AFE_TEST3_IREF_ON               _AFE_TEST3.Bits.IREF_ON
03953 #define AFE_TEST3_VBG_ON                _AFE_TEST3.Bits.VBG_ON
03954 #define AFE_TEST3_VREG_ON               _AFE_TEST3.Bits.VREG_ON
03955 #define AFE_TEST3_OSC_ON                _AFE_TEST3.Bits.OSC_ON
03956 #define AFE_TEST3_OSC_HF                _AFE_TEST3.Bits.OSC_HF
03957 #define AFE_TEST3_IBIAS_SEL             _AFE_TEST3.Bits.IBIAS_SEL
03958 #define AFE_TEST3_INV_OUT               _AFE_TEST3.Bits.INV_OUT
03959 #define AFE_TEST3_SWAP_IN               _AFE_TEST3.Bits.SWAP_IN
03960 #define AFE_TEST3_OVF_EN                _AFE_TEST3.Bits.OVF_EN
03961 #define AFE_TEST3_SDO_EN                _AFE_TEST3.Bits.SDO_EN
03962 
03963 #define AFE_TEST3_IREF_ON_MASK          1U
03964 #define AFE_TEST3_VBG_ON_MASK           2U
03965 #define AFE_TEST3_VREG_ON_MASK          4U
03966 #define AFE_TEST3_OSC_ON_MASK           8U
03967 #define AFE_TEST3_OSC_HF_MASK           16U
03968 #define AFE_TEST3_IBIAS_SEL_MASK        896U
03969 #define AFE_TEST3_IBIAS_SEL_BITNUM      7U
03970 #define AFE_TEST3_INV_OUT_MASK          1024U
03971 #define AFE_TEST3_SWAP_IN_MASK          2048U
03972 #define AFE_TEST3_OVF_EN_MASK           16384U
03973 #define AFE_TEST3_SDO_EN_MASK           32768U
03974 
03975 
03976 /*** SPI_SPSCR - SPI Status and Control Register; 0xFFFFEC80 ***/
03977 typedef union {
03978   word Word;
03979   struct {
03980     word SPTE        :1;                                       /* SPI Transmitter Empty */
03981     word MODF        :1;                                       /* Mode Fault */
03982     word OVRF        :1;                                       /* Overflow */
03983     word SPRF        :1;                                       /* SPI Receiver Full */
03984     word SPTIE       :1;                                       /* SPI Transmit Interrupt Enable */
03985     word SPE         :1;                                       /* SPI Enable */
03986     word CPHA        :1;                                       /* Clock Phase */
03987     word CPOL        :1;                                       /* Clock Polarity */
03988     word SPMSTR      :1;                                       /* SPI Master */
03989     word SPRIE       :1;                                       /* SPI Receiver Interrupt Enable */
03990     word MODFEN      :1;                                       /* Mode Fault Enable */
03991     word ERRIE       :1;                                       /* Error Interrupt Enable */
03992     word DSO         :1;                                       /* Data Shift Order */
03993     word SPR0        :1;                                       /* PI Baud Rate Select bit 0 */
03994     word SPR1        :1;                                       /* PI Baud Rate Select bit 1 */
03995     word SPR2        :1;                                       /* PI Baud Rate Select bit 2 */
03996   } Bits;
03997   struct {
03998     word         :1;
03999     word         :1;
04000     word         :1;
04001     word         :1;
04002     word         :1;
04003     word         :1;
04004     word grpCPHx :1;
04005     word         :1;
04006     word         :1;
04007     word         :1;
04008     word         :1;
04009     word         :1;
04010     word         :1;
04011     word grpSPR  :3;
04012   } MergedBits;
04013 } SPI_SPSCRSTR;
04014 extern volatile SPI_SPSCRSTR _SPI_SPSCR @0xFFFFEC80;
04015 #define SPI_SPSCR                       _SPI_SPSCR.Word
04016 #define SPI_SPSCR_SPTE                  _SPI_SPSCR.Bits.SPTE
04017 #define SPI_SPSCR_MODF                  _SPI_SPSCR.Bits.MODF
04018 #define SPI_SPSCR_OVRF                  _SPI_SPSCR.Bits.OVRF
04019 #define SPI_SPSCR_SPRF                  _SPI_SPSCR.Bits.SPRF
04020 #define SPI_SPSCR_SPTIE                 _SPI_SPSCR.Bits.SPTIE
04021 #define SPI_SPSCR_SPE                   _SPI_SPSCR.Bits.SPE
04022 #define SPI_SPSCR_CPHA                  _SPI_SPSCR.Bits.CPHA
04023 #define SPI_SPSCR_CPOL                  _SPI_SPSCR.Bits.CPOL
04024 #define SPI_SPSCR_SPMSTR                _SPI_SPSCR.Bits.SPMSTR
04025 #define SPI_SPSCR_SPRIE                 _SPI_SPSCR.Bits.SPRIE
04026 #define SPI_SPSCR_MODFEN                _SPI_SPSCR.Bits.MODFEN
04027 #define SPI_SPSCR_ERRIE                 _SPI_SPSCR.Bits.ERRIE
04028 #define SPI_SPSCR_DSO                   _SPI_SPSCR.Bits.DSO
04029 #define SPI_SPSCR_SPR0                  _SPI_SPSCR.Bits.SPR0
04030 #define SPI_SPSCR_SPR1                  _SPI_SPSCR.Bits.SPR1
04031 #define SPI_SPSCR_SPR2                  _SPI_SPSCR.Bits.SPR2
04032 #define SPI_SPSCR_SPR                   _SPI_SPSCR.MergedBits.grpSPR
04033 
04034 #define SPI_SPSCR_SPTE_MASK             1U
04035 #define SPI_SPSCR_MODF_MASK             2U
04036 #define SPI_SPSCR_OVRF_MASK             4U
04037 #define SPI_SPSCR_SPRF_MASK             8U
04038 #define SPI_SPSCR_SPTIE_MASK            16U
04039 #define SPI_SPSCR_SPE_MASK              32U
04040 #define SPI_SPSCR_CPHA_MASK             64U
04041 #define SPI_SPSCR_CPOL_MASK             128U
04042 #define SPI_SPSCR_SPMSTR_MASK           256U
04043 #define SPI_SPSCR_SPRIE_MASK            512U
04044 #define SPI_SPSCR_MODFEN_MASK           1024U
04045 #define SPI_SPSCR_ERRIE_MASK            2048U
04046 #define SPI_SPSCR_DSO_MASK              4096U
04047 #define SPI_SPSCR_SPR0_MASK             8192U
04048 #define SPI_SPSCR_SPR1_MASK             16384U
04049 #define SPI_SPSCR_SPR2_MASK             32768U
04050 #define SPI_SPSCR_SPR_MASK              57344U
04051 #define SPI_SPSCR_SPR_BITNUM            13U
04052 
04053 
04054 /*** SPI_SPDSR - SPI Data Size and Control Register; 0xFFFFEC82 ***/
04055 typedef union {
04056   word Word;
04057   struct {
04058     word DS0         :1;                                       /* Transaction data size bit 0 */
04059     word DS1         :1;                                       /* Transaction data size bit 1 */
04060     word DS2         :1;                                       /* Transaction data size bit 2 */
04061     word DS3         :1;                                       /* Transaction data size bit 3 */
04062     word SPR3        :1;                                       /* SPI Baud Rate Select */
04063     word SSB_OVER    :1;                                       /* SS_B Override Register */
04064     word SSB_STRB    :1;                                       /* SS_B Strobe Mode */
04065     word SSB_DDR     :1;                                       /* SS_B Data Direction Register */
04066     word SSB_AUTO    :1;                                       /* SS_B Automatic */
04067     word SSB_ODM     :1;                                       /* SS_B Open Drain Mode */
04068     word SSB_DATA    :1;                                       /* SS_B Data */
04069     word SSB_IN      :1;                                       /* SS_B Input */
04070     word BD2X        :1;                                       /* Baud Divisor Times 2 */
04071     word             :1; 
04072     word             :1; 
04073     word WOM         :1;                                       /* Wired-OR Mode */
04074   } Bits;
04075   struct {
04076     word grpDS   :4;
04077     word grpSPR_3 :1;
04078     word         :1;
04079     word         :1;
04080     word         :1;
04081     word         :1;
04082     word         :1;
04083     word grpSSB_DATx :1;
04084     word         :1;
04085     word         :1;
04086     word         :1;
04087     word         :1;
04088     word         :1;
04089   } MergedBits;
04090 } SPI_SPDSRSTR;
04091 extern volatile SPI_SPDSRSTR _SPI_SPDSR @0xFFFFEC82;
04092 #define SPI_SPDSR                       _SPI_SPDSR.Word
04093 #define SPI_SPDSR_DS0                   _SPI_SPDSR.Bits.DS0
04094 #define SPI_SPDSR_DS1                   _SPI_SPDSR.Bits.DS1
04095 #define SPI_SPDSR_DS2                   _SPI_SPDSR.Bits.DS2
04096 #define SPI_SPDSR_DS3                   _SPI_SPDSR.Bits.DS3
04097 #define SPI_SPDSR_SPR3                  _SPI_SPDSR.Bits.SPR3
04098 #define SPI_SPDSR_SSB_OVER              _SPI_SPDSR.Bits.SSB_OVER
04099 #define SPI_SPDSR_SSB_STRB              _SPI_SPDSR.Bits.SSB_STRB
04100 #define SPI_SPDSR_SSB_DDR               _SPI_SPDSR.Bits.SSB_DDR
04101 #define SPI_SPDSR_SSB_AUTO              _SPI_SPDSR.Bits.SSB_AUTO
04102 #define SPI_SPDSR_SSB_ODM               _SPI_SPDSR.Bits.SSB_ODM
04103 #define SPI_SPDSR_SSB_DATA              _SPI_SPDSR.Bits.SSB_DATA
04104 #define SPI_SPDSR_SSB_IN                _SPI_SPDSR.Bits.SSB_IN
04105 #define SPI_SPDSR_BD2X                  _SPI_SPDSR.Bits.BD2X
04106 #define SPI_SPDSR_WOM                   _SPI_SPDSR.Bits.WOM
04107 #define SPI_SPDSR_DS                    _SPI_SPDSR.MergedBits.grpDS
04108 
04109 #define SPI_SPDSR_DS0_MASK              1U
04110 #define SPI_SPDSR_DS1_MASK              2U
04111 #define SPI_SPDSR_DS2_MASK              4U
04112 #define SPI_SPDSR_DS3_MASK              8U
04113 #define SPI_SPDSR_SPR3_MASK             16U
04114 #define SPI_SPDSR_SSB_OVER_MASK         32U
04115 #define SPI_SPDSR_SSB_STRB_MASK         64U
04116 #define SPI_SPDSR_SSB_DDR_MASK          128U
04117 #define SPI_SPDSR_SSB_AUTO_MASK         256U
04118 #define SPI_SPDSR_SSB_ODM_MASK          512U
04119 #define SPI_SPDSR_SSB_DATA_MASK         1024U
04120 #define SPI_SPDSR_SSB_IN_MASK           2048U
04121 #define SPI_SPDSR_BD2X_MASK             4096U
04122 #define SPI_SPDSR_WOM_MASK              32768U
04123 #define SPI_SPDSR_DS_MASK               15U
04124 #define SPI_SPDSR_DS_BITNUM             0U
04125 
04126 
04127 /*** SPI_SPDRR - SPI Data Receive Register; 0xFFFFEC84 ***/
04128 typedef union {
04129   word Word;
04130   struct {
04131     word R0          :1;                                       /* Receive Data Bit 0 */
04132     word R1          :1;                                       /* Receive Data Bit 1 */
04133     word R2          :1;                                       /* Receive Data Bit 2 */
04134     word R3          :1;                                       /* Receive Data Bit 3 */
04135     word R4          :1;                                       /* Receive Data Bit 4 */
04136     word R5          :1;                                       /* Receive Data Bit 5 */
04137     word R6          :1;                                       /* Receive Data Bit 6 */
04138     word R7          :1;                                       /* Receive Data Bit 7 */
04139     word R8          :1;                                       /* Receive Data Bit 8 */
04140     word R9          :1;                                       /* Receive Data Bit 9 */
04141     word R10         :1;                                       /* Receive Data Bit 10 */
04142     word R11         :1;                                       /* Receive Data Bit 11 */
04143     word R12         :1;                                       /* Receive Data Bit 12 */
04144     word R13         :1;                                       /* Receive Data Bit 13 */
04145     word R14         :1;                                       /* Receive Data Bit 14 */
04146     word R15         :1;                                       /* Receive Data Bit 15 */
04147   } Bits;
04148 } SPI_SPDRRSTR;
04149 extern volatile SPI_SPDRRSTR _SPI_SPDRR @0xFFFFEC84;
04150 #define SPI_SPDRR                       _SPI_SPDRR.Word
04151 #define SPI_SPDRR_R0                    _SPI_SPDRR.Bits.R0
04152 #define SPI_SPDRR_R1                    _SPI_SPDRR.Bits.R1
04153 #define SPI_SPDRR_R2                    _SPI_SPDRR.Bits.R2
04154 #define SPI_SPDRR_R3                    _SPI_SPDRR.Bits.R3
04155 #define SPI_SPDRR_R4                    _SPI_SPDRR.Bits.R4
04156 #define SPI_SPDRR_R5                    _SPI_SPDRR.Bits.R5
04157 #define SPI_SPDRR_R6                    _SPI_SPDRR.Bits.R6
04158 #define SPI_SPDRR_R7                    _SPI_SPDRR.Bits.R7
04159 #define SPI_SPDRR_R8                    _SPI_SPDRR.Bits.R8
04160 #define SPI_SPDRR_R9                    _SPI_SPDRR.Bits.R9
04161 #define SPI_SPDRR_R10                   _SPI_SPDRR.Bits.R10
04162 #define SPI_SPDRR_R11                   _SPI_SPDRR.Bits.R11
04163 #define SPI_SPDRR_R12                   _SPI_SPDRR.Bits.R12
04164 #define SPI_SPDRR_R13                   _SPI_SPDRR.Bits.R13
04165 #define SPI_SPDRR_R14                   _SPI_SPDRR.Bits.R14
04166 #define SPI_SPDRR_R15                   _SPI_SPDRR.Bits.R15
04167 
04168 #define SPI_SPDRR_R0_MASK               1U
04169 #define SPI_SPDRR_R1_MASK               2U
04170 #define SPI_SPDRR_R2_MASK               4U
04171 #define SPI_SPDRR_R3_MASK               8U
04172 #define SPI_SPDRR_R4_MASK               16U
04173 #define SPI_SPDRR_R5_MASK               32U
04174 #define SPI_SPDRR_R6_MASK               64U
04175 #define SPI_SPDRR_R7_MASK               128U
04176 #define SPI_SPDRR_R8_MASK               256U
04177 #define SPI_SPDRR_R9_MASK               512U
04178 #define SPI_SPDRR_R10_MASK              1024U
04179 #define SPI_SPDRR_R11_MASK              2048U
04180 #define SPI_SPDRR_R12_MASK              4096U
04181 #define SPI_SPDRR_R13_MASK              8192U
04182 #define SPI_SPDRR_R14_MASK              16384U
04183 #define SPI_SPDRR_R15_MASK              32768U
04184 
04185 
04186 /*** SPI_SPDTR - SPI Data Transmit Register; 0xFFFFEC86 ***/
04187 typedef union {
04188   word Word;
04189   struct {
04190     word T0          :1;                                       /* Transmit Data Bit 0 */
04191     word T1          :1;                                       /* Transmit Data Bit 1 */
04192     word T2          :1;                                       /* Transmit Data Bit 2 */
04193     word T3          :1;                                       /* Transmit Data Bit 3 */
04194     word T4          :1;                                       /* Transmit Data Bit 4 */
04195     word T5          :1;                                       /* Transmit Data Bit 5 */
04196     word T6          :1;                                       /* Transmit Data Bit 6 */
04197     word T7          :1;                                       /* Transmit Data Bit 7 */
04198     word T8          :1;                                       /* Transmit Data Bit 8 */
04199     word T9          :1;                                       /* Transmit Data Bit 9 */
04200     word T10         :1;                                       /* Transmit Data Bit 10 */
04201     word T11         :1;                                       /* Transmit Data Bit 11 */
04202     word T12         :1;                                       /* Transmit Data Bit 12 */
04203     word T13         :1;                                       /* Transmit Data Bit 13 */
04204     word T14         :1;                                       /* Transmit Data Bit 14 */
04205     word T15         :1;                                       /* Transmit Data Bit 15 */
04206   } Bits;
04207 } SPI_SPDTRSTR;
04208 extern volatile SPI_SPDTRSTR _SPI_SPDTR @0xFFFFEC86;
04209 #define SPI_SPDTR                       _SPI_SPDTR.Word
04210 #define SPI_SPDTR_T0                    _SPI_SPDTR.Bits.T0
04211 #define SPI_SPDTR_T1                    _SPI_SPDTR.Bits.T1
04212 #define SPI_SPDTR_T2                    _SPI_SPDTR.Bits.T2
04213 #define SPI_SPDTR_T3                    _SPI_SPDTR.Bits.T3
04214 #define SPI_SPDTR_T4                    _SPI_SPDTR.Bits.T4
04215 #define SPI_SPDTR_T5                    _SPI_SPDTR.Bits.T5
04216 #define SPI_SPDTR_T6                    _SPI_SPDTR.Bits.T6
04217 #define SPI_SPDTR_T7                    _SPI_SPDTR.Bits.T7
04218 #define SPI_SPDTR_T8                    _SPI_SPDTR.Bits.T8
04219 #define SPI_SPDTR_T9                    _SPI_SPDTR.Bits.T9
04220 #define SPI_SPDTR_T10                   _SPI_SPDTR.Bits.T10
04221 #define SPI_SPDTR_T11                   _SPI_SPDTR.Bits.T11
04222 #define SPI_SPDTR_T12                   _SPI_SPDTR.Bits.T12
04223 #define SPI_SPDTR_T13                   _SPI_SPDTR.Bits.T13
04224 #define SPI_SPDTR_T14                   _SPI_SPDTR.Bits.T14
04225 #define SPI_SPDTR_T15                   _SPI_SPDTR.Bits.T15
04226 
04227 #define SPI_SPDTR_T0_MASK               1U
04228 #define SPI_SPDTR_T1_MASK               2U
04229 #define SPI_SPDTR_T2_MASK               4U
04230 #define SPI_SPDTR_T3_MASK               8U
04231 #define SPI_SPDTR_T4_MASK               16U
04232 #define SPI_SPDTR_T5_MASK               32U
04233 #define SPI_SPDTR_T6_MASK               64U
04234 #define SPI_SPDTR_T7_MASK               128U
04235 #define SPI_SPDTR_T8_MASK               256U
04236 #define SPI_SPDTR_T9_MASK               512U
04237 #define SPI_SPDTR_T10_MASK              1024U
04238 #define SPI_SPDTR_T11_MASK              2048U
04239 #define SPI_SPDTR_T12_MASK              4096U
04240 #define SPI_SPDTR_T13_MASK              8192U
04241 #define SPI_SPDTR_T14_MASK              16384U
04242 #define SPI_SPDTR_T15_MASK              32768U
04243 
04244 
04245 /*** SPI_SPFIFO - SPI FIFO Control Register; 0xFFFFEC88 ***/
04246 typedef union {
04247   word Word;
04248   struct {
04249     word FIFO_ENA    :1;                                       /* FIFO Enable */
04250     word             :1; 
04251     word RFWM0       :1;                                       /* Rx FIFO Watermark bit 0 */
04252     word RFWM1       :1;                                       /* Rx FIFO Watermark bit 1 */
04253     word             :1; 
04254     word TFWM0       :1;                                       /* Tx FIFO Watermark bit 0 */
04255     word TFWM1       :1;                                       /* Tx FIFO Watermark bit 1 */
04256     word             :1; 
04257     word RFCNT0      :1;                                       /* Rx FIFO Level bit 0 */
04258     word RFCNT1      :1;                                       /* Rx FIFO Level bit 1 */
04259     word RFCNT2      :1;                                       /* Rx FIFO Level bit 2 */
04260     word             :1; 
04261     word TFCNT0      :1;                                       /* Tx FIFO Level bit 0 */
04262     word TFCNT1      :1;                                       /* Tx FIFO Level bit 1 */
04263     word TFCNT2      :1;                                       /* Tx FIFO Level bit 2 */
04264     word             :1; 
04265   } Bits;
04266   struct {
04267     word grpFIFO_ENx :1;
04268     word         :1;
04269     word grpRFWM :2;
04270     word         :1;
04271     word grpTFWM :2;
04272     word         :1;
04273     word grpRFCNT :3;
04274     word         :1;
04275     word grpTFCNT :3;
04276     word         :1;
04277   } MergedBits;
04278 } SPI_SPFIFOSTR;
04279 extern volatile SPI_SPFIFOSTR _SPI_SPFIFO @0xFFFFEC88;
04280 #define SPI_SPFIFO                      _SPI_SPFIFO.Word
04281 #define SPI_SPFIFO_FIFO_ENA             _SPI_SPFIFO.Bits.FIFO_ENA
04282 #define SPI_SPFIFO_RFWM0                _SPI_SPFIFO.Bits.RFWM0
04283 #define SPI_SPFIFO_RFWM1                _SPI_SPFIFO.Bits.RFWM1
04284 #define SPI_SPFIFO_TFWM0                _SPI_SPFIFO.Bits.TFWM0
04285 #define SPI_SPFIFO_TFWM1                _SPI_SPFIFO.Bits.TFWM1
04286 #define SPI_SPFIFO_RFCNT0               _SPI_SPFIFO.Bits.RFCNT0
04287 #define SPI_SPFIFO_RFCNT1               _SPI_SPFIFO.Bits.RFCNT1
04288 #define SPI_SPFIFO_RFCNT2               _SPI_SPFIFO.Bits.RFCNT2
04289 #define SPI_SPFIFO_TFCNT0               _SPI_SPFIFO.Bits.TFCNT0
04290 #define SPI_SPFIFO_TFCNT1               _SPI_SPFIFO.Bits.TFCNT1
04291 #define SPI_SPFIFO_TFCNT2               _SPI_SPFIFO.Bits.TFCNT2
04292 #define SPI_SPFIFO_RFWM                 _SPI_SPFIFO.MergedBits.grpRFWM
04293 #define SPI_SPFIFO_TFWM                 _SPI_SPFIFO.MergedBits.grpTFWM
04294 #define SPI_SPFIFO_RFCNT                _SPI_SPFIFO.MergedBits.grpRFCNT
04295 #define SPI_SPFIFO_TFCNT                _SPI_SPFIFO.MergedBits.grpTFCNT
04296 
04297 #define SPI_SPFIFO_FIFO_ENA_MASK        1U
04298 #define SPI_SPFIFO_RFWM0_MASK           4U
04299 #define SPI_SPFIFO_RFWM1_MASK           8U
04300 #define SPI_SPFIFO_TFWM0_MASK           32U
04301 #define SPI_SPFIFO_TFWM1_MASK           64U
04302 #define SPI_SPFIFO_RFCNT0_MASK          256U
04303 #define SPI_SPFIFO_RFCNT1_MASK          512U
04304 #define SPI_SPFIFO_RFCNT2_MASK          1024U
04305 #define SPI_SPFIFO_TFCNT0_MASK          4096U
04306 #define SPI_SPFIFO_TFCNT1_MASK          8192U
04307 #define SPI_SPFIFO_TFCNT2_MASK          16384U
04308 #define SPI_SPFIFO_RFWM_MASK            12U
04309 #define SPI_SPFIFO_RFWM_BITNUM          2U
04310 #define SPI_SPFIFO_TFWM_MASK            96U
04311 #define SPI_SPFIFO_TFWM_BITNUM          5U
04312 #define SPI_SPFIFO_RFCNT_MASK           1792U
04313 #define SPI_SPFIFO_RFCNT_BITNUM         8U
04314 #define SPI_SPFIFO_TFCNT_MASK           28672U
04315 #define SPI_SPFIFO_TFCNT_BITNUM         12U
04316 
04317 
04318 /*** SPI_SPWAIT - SPI Word Delay Register; 0xFFFFEC8A ***/
04319 typedef union {
04320   word Word;
04321   struct {
04322     word WAIT0       :1;                                       /* Wait Delay Bit 0 */
04323     word WAIT1       :1;                                       /* Wait Delay Bit 1 */
04324     word WAIT2       :1;                                       /* Wait Delay Bit 2 */
04325     word WAIT3       :1;                                       /* Wait Delay Bit 3 */
04326     word WAIT4       :1;                                       /* Wait Delay Bit 4 */
04327     word WAIT5       :1;                                       /* Wait Delay Bit 5 */
04328     word WAIT6       :1;                                       /* Wait Delay Bit 6 */
04329     word WAIT7       :1;                                       /* Wait Delay Bit 7 */
04330     word WAIT8       :1;                                       /* Wait Delay Bit 8 */
04331     word WAIT9       :1;                                       /* Wait Delay Bit 9 */
04332     word WAIT10      :1;                                       /* Wait Delay Bit 10 */
04333     word WAIT11      :1;                                       /* Wait Delay Bit 11 */
04334     word WAIT12      :1;                                       /* Wait Delay Bit 12 */
04335     word             :1; 
04336     word             :1; 
04337     word             :1; 
04338   } Bits;
04339   struct {
04340     word grpWAIT :13;
04341     word         :1;
04342     word         :1;
04343     word         :1;
04344   } MergedBits;
04345 } SPI_SPWAITSTR;
04346 extern volatile SPI_SPWAITSTR _SPI_SPWAIT @0xFFFFEC8A;
04347 #define SPI_SPWAIT                      _SPI_SPWAIT.Word
04348 #define SPI_SPWAIT_WAIT0                _SPI_SPWAIT.Bits.WAIT0
04349 #define SPI_SPWAIT_WAIT1                _SPI_SPWAIT.Bits.WAIT1
04350 #define SPI_SPWAIT_WAIT2                _SPI_SPWAIT.Bits.WAIT2
04351 #define SPI_SPWAIT_WAIT3                _SPI_SPWAIT.Bits.WAIT3
04352 #define SPI_SPWAIT_WAIT4                _SPI_SPWAIT.Bits.WAIT4
04353 #define SPI_SPWAIT_WAIT5                _SPI_SPWAIT.Bits.WAIT5
04354 #define SPI_SPWAIT_WAIT6                _SPI_SPWAIT.Bits.WAIT6
04355 #define SPI_SPWAIT_WAIT7                _SPI_SPWAIT.Bits.WAIT7
04356 #define SPI_SPWAIT_WAIT8                _SPI_SPWAIT.Bits.WAIT8
04357 #define SPI_SPWAIT_WAIT9                _SPI_SPWAIT.Bits.WAIT9
04358 #define SPI_SPWAIT_WAIT10               _SPI_SPWAIT.Bits.WAIT10
04359 #define SPI_SPWAIT_WAIT11               _SPI_SPWAIT.Bits.WAIT11
04360 #define SPI_SPWAIT_WAIT12               _SPI_SPWAIT.Bits.WAIT12
04361 #define SPI_SPWAIT_WAIT                 _SPI_SPWAIT.MergedBits.grpWAIT
04362 
04363 #define SPI_SPWAIT_WAIT0_MASK           1U
04364 #define SPI_SPWAIT_WAIT1_MASK           2U
04365 #define SPI_SPWAIT_WAIT2_MASK           4U
04366 #define SPI_SPWAIT_WAIT3_MASK           8U
04367 #define SPI_SPWAIT_WAIT4_MASK           16U
04368 #define SPI_SPWAIT_WAIT5_MASK           32U
04369 #define SPI_SPWAIT_WAIT6_MASK           64U
04370 #define SPI_SPWAIT_WAIT7_MASK           128U
04371 #define SPI_SPWAIT_WAIT8_MASK           256U
04372 #define SPI_SPWAIT_WAIT9_MASK           512U
04373 #define SPI_SPWAIT_WAIT10_MASK          1024U
04374 #define SPI_SPWAIT_WAIT11_MASK          2048U
04375 #define SPI_SPWAIT_WAIT12_MASK          4096U
04376 #define SPI_SPWAIT_WAIT_MASK            8191U
04377 #define SPI_SPWAIT_WAIT_BITNUM          0U
04378 
04379 
04380 /*** INTC_FRC - INTC Force Interrupt Register; 0xFFFFFFD0 ***/
04381 typedef union {
04382   byte Byte;
04383   struct {
04384     byte LVL7        :1;                                       /* Force Level 7 interrupt */
04385     byte LVL6        :1;                                       /* Force Level 6 interrupt */
04386     byte LVL5        :1;                                       /* Force Level 5 interrupt */
04387     byte LVL4        :1;                                       /* Force Level 4 interrupt */
04388     byte LVL3        :1;                                       /* Force Level 3 interrupt */
04389     byte LVL2        :1;                                       /* Force Level 2 interrupt */
04390     byte LVL1        :1;                                       /* Force Level 1 interrupt */
04391     byte             :1; 
04392   } Bits;
04393 } INTC_FRCSTR;
04394 extern volatile INTC_FRCSTR _INTC_FRC @0xFFFFFFD0;
04395 #define INTC_FRC                        _INTC_FRC.Byte
04396 #define INTC_FRC_LVL7                   _INTC_FRC.Bits.LVL7
04397 #define INTC_FRC_LVL6                   _INTC_FRC.Bits.LVL6
04398 #define INTC_FRC_LVL5                   _INTC_FRC.Bits.LVL5
04399 #define INTC_FRC_LVL4                   _INTC_FRC.Bits.LVL4
04400 #define INTC_FRC_LVL3                   _INTC_FRC.Bits.LVL3
04401 #define INTC_FRC_LVL2                   _INTC_FRC.Bits.LVL2
04402 #define INTC_FRC_LVL1                   _INTC_FRC.Bits.LVL1
04403 
04404 #define INTC_FRC_LVL7_MASK              1U
04405 #define INTC_FRC_LVL6_MASK              2U
04406 #define INTC_FRC_LVL5_MASK              4U
04407 #define INTC_FRC_LVL4_MASK              8U
04408 #define INTC_FRC_LVL3_MASK              16U
04409 #define INTC_FRC_LVL2_MASK              32U
04410 #define INTC_FRC_LVL1_MASK              64U
04411 
04412 
04413 /*** INTC_PL6P7 - INTC Programmable Level 6, Priority 7 Register; 0xFFFFFFD8 ***/
04414 typedef union {
04415   byte Byte;
04416   struct {
04417     byte REQN0       :1;                                       /* Request number, bit 0 */
04418     byte REQN1       :1;                                       /* Request number, bit 1 */
04419     byte REQN2       :1;                                       /* Request number, bit 2 */
04420     byte REQN3       :1;                                       /* Request number, bit 3 */
04421     byte REQN4       :1;                                       /* Request number, bit 4 */
04422     byte REQN5       :1;                                       /* Request number, bit 5 */
04423     byte             :1; 
04424     byte             :1; 
04425   } Bits;
04426   struct {
04427     byte grpREQN :6;
04428     byte         :1;
04429     byte         :1;
04430   } MergedBits;
04431 } INTC_PL6P7STR;
04432 extern volatile INTC_PL6P7STR _INTC_PL6P7 @0xFFFFFFD8;
04433 #define INTC_PL6P7                      _INTC_PL6P7.Byte
04434 #define INTC_PL6P7_REQN0                _INTC_PL6P7.Bits.REQN0
04435 #define INTC_PL6P7_REQN1                _INTC_PL6P7.Bits.REQN1
04436 #define INTC_PL6P7_REQN2                _INTC_PL6P7.Bits.REQN2
04437 #define INTC_PL6P7_REQN3                _INTC_PL6P7.Bits.REQN3
04438 #define INTC_PL6P7_REQN4                _INTC_PL6P7.Bits.REQN4
04439 #define INTC_PL6P7_REQN5                _INTC_PL6P7.Bits.REQN5
04440 #define INTC_PL6P7_REQN                 _INTC_PL6P7.MergedBits.grpREQN
04441 
04442 #define INTC_PL6P7_REQN0_MASK           1U
04443 #define INTC_PL6P7_REQN1_MASK           2U
04444 #define INTC_PL6P7_REQN2_MASK           4U
04445 #define INTC_PL6P7_REQN3_MASK           8U
04446 #define INTC_PL6P7_REQN4_MASK           16U
04447 #define INTC_PL6P7_REQN5_MASK           32U
04448 #define INTC_PL6P7_REQN_MASK            63U
04449 #define INTC_PL6P7_REQN_BITNUM          0U
04450 
04451 
04452 /*** INTC_PL6P6 - INTC Programmable Level 6, Priority 6 Register; 0xFFFFFFD9 ***/
04453 typedef union {
04454   byte Byte;
04455   struct {
04456     byte REQN0       :1;                                       /* Request number, bit 0 */
04457     byte REQN1       :1;                                       /* Request number, bit 1 */
04458     byte REQN2       :1;                                       /* Request number, bit 2 */
04459     byte REQN3       :1;                                       /* Request number, bit 3 */
04460     byte REQN4       :1;                                       /* Request number, bit 4 */
04461     byte REQN5       :1;                                       /* Request number, bit 5 */
04462     byte             :1; 
04463     byte             :1; 
04464   } Bits;
04465   struct {
04466     byte grpREQN :6;
04467     byte         :1;
04468     byte         :1;
04469   } MergedBits;
04470 } INTC_PL6P6STR;
04471 extern volatile INTC_PL6P6STR _INTC_PL6P6 @0xFFFFFFD9;
04472 #define INTC_PL6P6                      _INTC_PL6P6.Byte
04473 #define INTC_PL6P6_REQN0                _INTC_PL6P6.Bits.REQN0
04474 #define INTC_PL6P6_REQN1                _INTC_PL6P6.Bits.REQN1
04475 #define INTC_PL6P6_REQN2                _INTC_PL6P6.Bits.REQN2
04476 #define INTC_PL6P6_REQN3                _INTC_PL6P6.Bits.REQN3
04477 #define INTC_PL6P6_REQN4                _INTC_PL6P6.Bits.REQN4
04478 #define INTC_PL6P6_REQN5                _INTC_PL6P6.Bits.REQN5
04479 #define INTC_PL6P6_REQN                 _INTC_PL6P6.MergedBits.grpREQN
04480 
04481 #define INTC_PL6P6_REQN0_MASK           1U
04482 #define INTC_PL6P6_REQN1_MASK           2U
04483 #define INTC_PL6P6_REQN2_MASK           4U
04484 #define INTC_PL6P6_REQN3_MASK           8U
04485 #define INTC_PL6P6_REQN4_MASK           16U
04486 #define INTC_PL6P6_REQN5_MASK           32U
04487 #define INTC_PL6P6_REQN_MASK            63U
04488 #define INTC_PL6P6_REQN_BITNUM          0U
04489 
04490 
04491 /*** INTC_WCR - INTC Wake-up Control Register; 0xFFFFFFDB ***/
04492 typedef union {
04493   byte Byte;
04494   struct {
04495     byte MASK0       :1;                                       /* Interrupt mask level, bit 0 */
04496     byte MASK1       :1;                                       /* Interrupt mask level, bit 1 */
04497     byte MASK2       :1;                                       /* Interrupt mask level, bit 2 */
04498     byte             :1; 
04499     byte             :1; 
04500     byte             :1; 
04501     byte             :1; 
04502     byte ENB         :1;                                       /* Enable */
04503   } Bits;
04504   struct {
04505     byte grpMASK :3;
04506     byte         :1;
04507     byte         :1;
04508     byte         :1;
04509     byte         :1;
04510     byte         :1;
04511   } MergedBits;
04512 } INTC_WCRSTR;
04513 extern volatile INTC_WCRSTR _INTC_WCR @0xFFFFFFDB;
04514 #define INTC_WCR                        _INTC_WCR.Byte
04515 #define INTC_WCR_MASK0                  _INTC_WCR.Bits.MASK0
04516 #define INTC_WCR_MASK1                  _INTC_WCR.Bits.MASK1
04517 #define INTC_WCR_MASK2                  _INTC_WCR.Bits.MASK2
04518 #define INTC_WCR_ENB                    _INTC_WCR.Bits.ENB
04519 #define INTC_WCR_MASK                   _INTC_WCR.MergedBits.grpMASK
04520 
04521 #define INTC_WCR_MASK0_MASK             1U
04522 #define INTC_WCR_MASK1_MASK             2U
04523 #define INTC_WCR_MASK2_MASK             4U
04524 #define INTC_WCR_ENB_MASK               128U
04525 #define INTC_WCR_MASK_MASK              7U
04526 #define INTC_WCR_MASK_BITNUM            0U
04527 
04528 
04529 /*** INTC_SFRC - INTC Set Interrupt Force Register; 0xFFFFFFDE ***/
04530 typedef union {
04531   byte Byte;
04532   struct {
04533     byte SET0        :1;                                       /* Sets corresponding bits in the INTC_FRC register, bit 0 */
04534     byte SET1        :1;                                       /* Sets corresponding bits in the INTC_FRC register, bit 1 */
04535     byte SET2        :1;                                       /* Sets corresponding bits in the INTC_FRC register, bit 2 */
04536     byte SET3        :1;                                       /* Sets corresponding bits in the INTC_FRC register, bit 3 */
04537     byte SET4        :1;                                       /* Sets corresponding bits in the INTC_FRC register, bit 4 */
04538     byte SET5        :1;                                       /* Sets corresponding bits in the INTC_FRC register, bit 5 */
04539     byte             :1; 
04540     byte             :1; 
04541   } Bits;
04542   struct {
04543     byte grpSET  :6;
04544     byte         :1;
04545     byte         :1;
04546   } MergedBits;
04547 } INTC_SFRCSTR;
04548 extern volatile INTC_SFRCSTR _INTC_SFRC @0xFFFFFFDE;
04549 #define INTC_SFRC                       _INTC_SFRC.Byte
04550 #define INTC_SFRC_SET0                  _INTC_SFRC.Bits.SET0
04551 #define INTC_SFRC_SET1                  _INTC_SFRC.Bits.SET1
04552 #define INTC_SFRC_SET2                  _INTC_SFRC.Bits.SET2
04553 #define INTC_SFRC_SET3                  _INTC_SFRC.Bits.SET3
04554 #define INTC_SFRC_SET4                  _INTC_SFRC.Bits.SET4
04555 #define INTC_SFRC_SET5                  _INTC_SFRC.Bits.SET5
04556 #define INTC_SFRC_SET                   _INTC_SFRC.MergedBits.grpSET
04557 
04558 #define INTC_SFRC_SET0_MASK             1U
04559 #define INTC_SFRC_SET1_MASK             2U
04560 #define INTC_SFRC_SET2_MASK             4U
04561 #define INTC_SFRC_SET3_MASK             8U
04562 #define INTC_SFRC_SET4_MASK             16U
04563 #define INTC_SFRC_SET5_MASK             32U
04564 #define INTC_SFRC_SET_MASK              63U
04565 #define INTC_SFRC_SET_BITNUM            0U
04566 
04567 
04568 /*** INTC_CFRC - INTC Clear Interrupt Force Register; 0xFFFFFFDF ***/
04569 typedef union {
04570   byte Byte;
04571   struct {
04572     byte CLR0        :1;                                       /* Clears corresponding bits in the INTC_FRC register, bit 0 */
04573     byte CLR1        :1;                                       /* Clears corresponding bits in the INTC_FRC register, bit 1 */
04574     byte CLR2        :1;                                       /* Clears corresponding bits in the INTC_FRC register, bit 2 */
04575     byte CLR3        :1;                                       /* Clears corresponding bits in the INTC_FRC register, bit 3 */
04576     byte CLR4        :1;                                       /* Clears corresponding bits in the INTC_FRC register, bit 4 */
04577     byte CLR5        :1;                                       /* Clears corresponding bits in the INTC_FRC register, bit 5 */
04578     byte             :1; 
04579     byte             :1; 
04580   } Bits;
04581   struct {
04582     byte grpCLR  :6;
04583     byte         :1;
04584     byte         :1;
04585   } MergedBits;
04586 } INTC_CFRCSTR;
04587 extern volatile INTC_CFRCSTR _INTC_CFRC @0xFFFFFFDF;
04588 #define INTC_CFRC                       _INTC_CFRC.Byte
04589 #define INTC_CFRC_CLR0                  _INTC_CFRC.Bits.CLR0
04590 #define INTC_CFRC_CLR1                  _INTC_CFRC.Bits.CLR1
04591 #define INTC_CFRC_CLR2                  _INTC_CFRC.Bits.CLR2
04592 #define INTC_CFRC_CLR3                  _INTC_CFRC.Bits.CLR3
04593 #define INTC_CFRC_CLR4                  _INTC_CFRC.Bits.CLR4
04594 #define INTC_CFRC_CLR5                  _INTC_CFRC.Bits.CLR5
04595 #define INTC_CFRC_CLR                   _INTC_CFRC.MergedBits.grpCLR
04596 
04597 #define INTC_CFRC_CLR0_MASK             1U
04598 #define INTC_CFRC_CLR1_MASK             2U
04599 #define INTC_CFRC_CLR2_MASK             4U
04600 #define INTC_CFRC_CLR3_MASK             8U
04601 #define INTC_CFRC_CLR4_MASK             16U
04602 #define INTC_CFRC_CLR5_MASK             32U
04603 #define INTC_CFRC_CLR_MASK              63U
04604 #define INTC_CFRC_CLR_BITNUM            0U
04605 
04606 
04607 /*** INTC_SWIACK - INTC Software IACK Register; 0xFFFFFFE0 ***/
04608 typedef union {
04609   byte Byte;
04610   struct {
04611     byte VECN0       :1;                                       /* Vector number, bit 0 */
04612     byte VECN1       :1;                                       /* Vector number, bit 1 */
04613     byte VECN2       :1;                                       /* Vector number, bit 2 */
04614     byte VECN3       :1;                                       /* Vector number, bit 3 */
04615     byte VECN4       :1;                                       /* Vector number, bit 4 */
04616     byte VECN5       :1;                                       /* Vector number, bit 5 */
04617     byte VECN6       :1;                                       /* Vector number, bit 6 */
04618     byte             :1; 
04619   } Bits;
04620   struct {
04621     byte grpVECN :7;
04622     byte         :1;
04623   } MergedBits;
04624 } INTC_SWIACKSTR;
04625 extern volatile INTC_SWIACKSTR _INTC_SWIACK @0xFFFFFFE0;
04626 #define INTC_SWIACK                     _INTC_SWIACK.Byte
04627 #define INTC_SWIACK_VECN0               _INTC_SWIACK.Bits.VECN0
04628 #define INTC_SWIACK_VECN1               _INTC_SWIACK.Bits.VECN1
04629 #define INTC_SWIACK_VECN2               _INTC_SWIACK.Bits.VECN2
04630 #define INTC_SWIACK_VECN3               _INTC_SWIACK.Bits.VECN3
04631 #define INTC_SWIACK_VECN4               _INTC_SWIACK.Bits.VECN4
04632 #define INTC_SWIACK_VECN5               _INTC_SWIACK.Bits.VECN5
04633 #define INTC_SWIACK_VECN6               _INTC_SWIACK.Bits.VECN6
04634 #define INTC_SWIACK_VECN                _INTC_SWIACK.MergedBits.grpVECN
04635 
04636 #define INTC_SWIACK_VECN0_MASK          1U
04637 #define INTC_SWIACK_VECN1_MASK          2U
04638 #define INTC_SWIACK_VECN2_MASK          4U
04639 #define INTC_SWIACK_VECN3_MASK          8U
04640 #define INTC_SWIACK_VECN4_MASK          16U
04641 #define INTC_SWIACK_VECN5_MASK          32U
04642 #define INTC_SWIACK_VECN6_MASK          64U
04643 #define INTC_SWIACK_VECN_MASK           127U
04644 #define INTC_SWIACK_VECN_BITNUM         0U
04645 
04646 
04647 /*** INTC_LVL1IACK - INTC Level 1 IACK Register; 0xFFFFFFE4 ***/
04648 typedef union {
04649   byte Byte;
04650   struct {
04651     byte VECN0       :1;                                       /* Vector number, bit 0 */
04652     byte VECN1       :1;                                       /* Vector number, bit 1 */
04653     byte VECN2       :1;                                       /* Vector number, bit 2 */
04654     byte VECN3       :1;                                       /* Vector number, bit 3 */
04655     byte VECN4       :1;                                       /* Vector number, bit 4 */
04656     byte VECN5       :1;                                       /* Vector number, bit 5 */
04657     byte VECN6       :1;                                       /* Vector number, bit 6 */
04658     byte             :1; 
04659   } Bits;
04660   struct {
04661     byte grpVECN :7;
04662     byte         :1;
04663   } MergedBits;
04664 } INTC_LVL1IACKSTR;
04665 extern volatile INTC_LVL1IACKSTR _INTC_LVL1IACK @0xFFFFFFE4;
04666 #define INTC_LVL1IACK                   _INTC_LVL1IACK.Byte
04667 #define INTC_LVL1IACK_VECN0             _INTC_LVL1IACK.Bits.VECN0
04668 #define INTC_LVL1IACK_VECN1             _INTC_LVL1IACK.Bits.VECN1
04669 #define INTC_LVL1IACK_VECN2             _INTC_LVL1IACK.Bits.VECN2
04670 #define INTC_LVL1IACK_VECN3             _INTC_LVL1IACK.Bits.VECN3
04671 #define INTC_LVL1IACK_VECN4             _INTC_LVL1IACK.Bits.VECN4
04672 #define INTC_LVL1IACK_VECN5             _INTC_LVL1IACK.Bits.VECN5
04673 #define INTC_LVL1IACK_VECN6             _INTC_LVL1IACK.Bits.VECN6
04674 #define INTC_LVL1IACK_VECN              _INTC_LVL1IACK.MergedBits.grpVECN
04675 
04676 #define INTC_LVL1IACK_VECN0_MASK        1U
04677 #define INTC_LVL1IACK_VECN1_MASK        2U
04678 #define INTC_LVL1IACK_VECN2_MASK        4U
04679 #define INTC_LVL1IACK_VECN3_MASK        8U
04680 #define INTC_LVL1IACK_VECN4_MASK        16U
04681 #define INTC_LVL1IACK_VECN5_MASK        32U
04682 #define INTC_LVL1IACK_VECN6_MASK        64U
04683 #define INTC_LVL1IACK_VECN_MASK         127U
04684 #define INTC_LVL1IACK_VECN_BITNUM       0U
04685 
04686 
04687 /*** INTC_LVL2IACK - INTC Level 2 IACK Register; 0xFFFFFFE8 ***/
04688 typedef union {
04689   byte Byte;
04690   struct {
04691     byte VECN0       :1;                                       /* Vector number, bit 0 */
04692     byte VECN1       :1;                                       /* Vector number, bit 1 */
04693     byte VECN2       :1;                                       /* Vector number, bit 2 */
04694     byte VECN3       :1;                                       /* Vector number, bit 3 */
04695     byte VECN4       :1;                                       /* Vector number, bit 4 */
04696     byte VECN5       :1;                                       /* Vector number, bit 5 */
04697     byte VECN6       :1;                                       /* Vector number, bit 6 */
04698     byte             :1; 
04699   } Bits;
04700   struct {
04701     byte grpVECN :7;
04702     byte         :1;
04703   } MergedBits;
04704 } INTC_LVL2IACKSTR;
04705 extern volatile INTC_LVL2IACKSTR _INTC_LVL2IACK @0xFFFFFFE8;
04706 #define INTC_LVL2IACK                   _INTC_LVL2IACK.Byte
04707 #define INTC_LVL2IACK_VECN0             _INTC_LVL2IACK.Bits.VECN0
04708 #define INTC_LVL2IACK_VECN1             _INTC_LVL2IACK.Bits.VECN1
04709 #define INTC_LVL2IACK_VECN2             _INTC_LVL2IACK.Bits.VECN2
04710 #define INTC_LVL2IACK_VECN3             _INTC_LVL2IACK.Bits.VECN3
04711 #define INTC_LVL2IACK_VECN4             _INTC_LVL2IACK.Bits.VECN4
04712 #define INTC_LVL2IACK_VECN5             _INTC_LVL2IACK.Bits.VECN5
04713 #define INTC_LVL2IACK_VECN6             _INTC_LVL2IACK.Bits.VECN6
04714 #define INTC_LVL2IACK_VECN              _INTC_LVL2IACK.MergedBits.grpVECN
04715 
04716 #define INTC_LVL2IACK_VECN0_MASK        1U
04717 #define INTC_LVL2IACK_VECN1_MASK        2U
04718 #define INTC_LVL2IACK_VECN2_MASK        4U
04719 #define INTC_LVL2IACK_VECN3_MASK        8U
04720 #define INTC_LVL2IACK_VECN4_MASK        16U
04721 #define INTC_LVL2IACK_VECN5_MASK        32U
04722 #define INTC_LVL2IACK_VECN6_MASK        64U
04723 #define INTC_LVL2IACK_VECN_MASK         127U
04724 #define INTC_LVL2IACK_VECN_BITNUM       0U
04725 
04726 
04727 /*** INTC_LVL3IACK - INTC Level 3 IACK Register; 0xFFFFFFEC ***/
04728 typedef union {
04729   byte Byte;
04730   struct {
04731     byte VECN0       :1;                                       /* Vector number, bit 0 */
04732     byte VECN1       :1;                                       /* Vector number, bit 1 */
04733     byte VECN2       :1;                                       /* Vector number, bit 2 */
04734     byte VECN3       :1;                                       /* Vector number, bit 3 */
04735     byte VECN4       :1;                                       /* Vector number, bit 4 */
04736     byte VECN5       :1;                                       /* Vector number, bit 5 */
04737     byte VECN6       :1;                                       /* Vector number, bit 6 */
04738     byte             :1; 
04739   } Bits;
04740   struct {
04741     byte grpVECN :7;
04742     byte         :1;
04743   } MergedBits;
04744 } INTC_LVL3IACKSTR;
04745 extern volatile INTC_LVL3IACKSTR _INTC_LVL3IACK @0xFFFFFFEC;
04746 #define INTC_LVL3IACK                   _INTC_LVL3IACK.Byte
04747 #define INTC_LVL3IACK_VECN0             _INTC_LVL3IACK.Bits.VECN0
04748 #define INTC_LVL3IACK_VECN1             _INTC_LVL3IACK.Bits.VECN1
04749 #define INTC_LVL3IACK_VECN2             _INTC_LVL3IACK.Bits.VECN2
04750 #define INTC_LVL3IACK_VECN3             _INTC_LVL3IACK.Bits.VECN3
04751 #define INTC_LVL3IACK_VECN4             _INTC_LVL3IACK.Bits.VECN4
04752 #define INTC_LVL3IACK_VECN5             _INTC_LVL3IACK.Bits.VECN5
04753 #define INTC_LVL3IACK_VECN6             _INTC_LVL3IACK.Bits.VECN6
04754 #define INTC_LVL3IACK_VECN              _INTC_LVL3IACK.MergedBits.grpVECN
04755 
04756 #define INTC_LVL3IACK_VECN0_MASK        1U
04757 #define INTC_LVL3IACK_VECN1_MASK        2U
04758 #define INTC_LVL3IACK_VECN2_MASK        4U
04759 #define INTC_LVL3IACK_VECN3_MASK        8U
04760 #define INTC_LVL3IACK_VECN4_MASK        16U
04761 #define INTC_LVL3IACK_VECN5_MASK        32U
04762 #define INTC_LVL3IACK_VECN6_MASK        64U
04763 #define INTC_LVL3IACK_VECN_MASK         127U
04764 #define INTC_LVL3IACK_VECN_BITNUM       0U
04765 
04766 
04767 /*** INTC_LVL4IACK - INTC Level 4 IACK Register; 0xFFFFFFF0 ***/
04768 typedef union {
04769   byte Byte;
04770   struct {
04771     byte VECN0       :1;                                       /* Vector number, bit 0 */
04772     byte VECN1       :1;                                       /* Vector number, bit 1 */
04773     byte VECN2       :1;                                       /* Vector number, bit 2 */
04774     byte VECN3       :1;                                       /* Vector number, bit 3 */
04775     byte VECN4       :1;                                       /* Vector number, bit 4 */
04776     byte VECN5       :1;                                       /* Vector number, bit 5 */
04777     byte VECN6       :1;                                       /* Vector number, bit 6 */
04778     byte             :1; 
04779   } Bits;
04780   struct {
04781     byte grpVECN :7;
04782     byte         :1;
04783   } MergedBits;
04784 } INTC_LVL4IACKSTR;
04785 extern volatile INTC_LVL4IACKSTR _INTC_LVL4IACK @0xFFFFFFF0;
04786 #define INTC_LVL4IACK                   _INTC_LVL4IACK.Byte
04787 #define INTC_LVL4IACK_VECN0             _INTC_LVL4IACK.Bits.VECN0
04788 #define INTC_LVL4IACK_VECN1             _INTC_LVL4IACK.Bits.VECN1
04789 #define INTC_LVL4IACK_VECN2             _INTC_LVL4IACK.Bits.VECN2
04790 #define INTC_LVL4IACK_VECN3             _INTC_LVL4IACK.Bits.VECN3
04791 #define INTC_LVL4IACK_VECN4             _INTC_LVL4IACK.Bits.VECN4
04792 #define INTC_LVL4IACK_VECN5             _INTC_LVL4IACK.Bits.VECN5
04793 #define INTC_LVL4IACK_VECN6             _INTC_LVL4IACK.Bits.VECN6
04794 #define INTC_LVL4IACK_VECN              _INTC_LVL4IACK.MergedBits.grpVECN
04795 
04796 #define INTC_LVL4IACK_VECN0_MASK        1U
04797 #define INTC_LVL4IACK_VECN1_MASK        2U
04798 #define INTC_LVL4IACK_VECN2_MASK        4U
04799 #define INTC_LVL4IACK_VECN3_MASK        8U
04800 #define INTC_LVL4IACK_VECN4_MASK        16U
04801 #define INTC_LVL4IACK_VECN5_MASK        32U
04802 #define INTC_LVL4IACK_VECN6_MASK        64U
04803 #define INTC_LVL4IACK_VECN_MASK         127U
04804 #define INTC_LVL4IACK_VECN_BITNUM       0U
04805 
04806 
04807 /*** INTC_LVL5IACK - INTC Level 5 IACK Register; 0xFFFFFFF4 ***/
04808 typedef union {
04809   byte Byte;
04810   struct {
04811     byte VECN0       :1;                                       /* Vector number, bit 0 */
04812     byte VECN1       :1;                                       /* Vector number, bit 1 */
04813     byte VECN2       :1;                                       /* Vector number, bit 2 */
04814     byte VECN3       :1;                                       /* Vector number, bit 3 */
04815     byte VECN4       :1;                                       /* Vector number, bit 4 */
04816     byte VECN5       :1;                                       /* Vector number, bit 5 */
04817     byte VECN6       :1;                                       /* Vector number, bit 6 */
04818     byte             :1; 
04819   } Bits;
04820   struct {
04821     byte grpVECN :7;
04822     byte         :1;
04823   } MergedBits;
04824 } INTC_LVL5IACKSTR;
04825 extern volatile INTC_LVL5IACKSTR _INTC_LVL5IACK @0xFFFFFFF4;
04826 #define INTC_LVL5IACK                   _INTC_LVL5IACK.Byte
04827 #define INTC_LVL5IACK_VECN0             _INTC_LVL5IACK.Bits.VECN0
04828 #define INTC_LVL5IACK_VECN1             _INTC_LVL5IACK.Bits.VECN1
04829 #define INTC_LVL5IACK_VECN2             _INTC_LVL5IACK.Bits.VECN2
04830 #define INTC_LVL5IACK_VECN3             _INTC_LVL5IACK.Bits.VECN3
04831 #define INTC_LVL5IACK_VECN4             _INTC_LVL5IACK.Bits.VECN4
04832 #define INTC_LVL5IACK_VECN5             _INTC_LVL5IACK.Bits.VECN5
04833 #define INTC_LVL5IACK_VECN6             _INTC_LVL5IACK.Bits.VECN6
04834 #define INTC_LVL5IACK_VECN              _INTC_LVL5IACK.MergedBits.grpVECN
04835 
04836 #define INTC_LVL5IACK_VECN0_MASK        1U
04837 #define INTC_LVL5IACK_VECN1_MASK        2U
04838 #define INTC_LVL5IACK_VECN2_MASK        4U
04839 #define INTC_LVL5IACK_VECN3_MASK        8U
04840 #define INTC_LVL5IACK_VECN4_MASK        16U
04841 #define INTC_LVL5IACK_VECN5_MASK        32U
04842 #define INTC_LVL5IACK_VECN6_MASK        64U
04843 #define INTC_LVL5IACK_VECN_MASK         127U
04844 #define INTC_LVL5IACK_VECN_BITNUM       0U
04845 
04846 
04847 /*** INTC_LVL6IACK - INTC Level 6 IACK Register; 0xFFFFFFF8 ***/
04848 typedef union {
04849   byte Byte;
04850   struct {
04851     byte VECN0       :1;                                       /* Vector number, bit 0 */
04852     byte VECN1       :1;                                       /* Vector number, bit 1 */
04853     byte VECN2       :1;                                       /* Vector number, bit 2 */
04854     byte VECN3       :1;                                       /* Vector number, bit 3 */
04855     byte VECN4       :1;                                       /* Vector number, bit 4 */
04856     byte VECN5       :1;                                       /* Vector number, bit 5 */
04857     byte VECN6       :1;                                       /* Vector number, bit 6 */
04858     byte             :1; 
04859   } Bits;
04860   struct {
04861     byte grpVECN :7;
04862     byte         :1;
04863   } MergedBits;
04864 } INTC_LVL6IACKSTR;
04865 extern volatile INTC_LVL6IACKSTR _INTC_LVL6IACK @0xFFFFFFF8;
04866 #define INTC_LVL6IACK                   _INTC_LVL6IACK.Byte
04867 #define INTC_LVL6IACK_VECN0             _INTC_LVL6IACK.Bits.VECN0
04868 #define INTC_LVL6IACK_VECN1             _INTC_LVL6IACK.Bits.VECN1
04869 #define INTC_LVL6IACK_VECN2             _INTC_LVL6IACK.Bits.VECN2
04870 #define INTC_LVL6IACK_VECN3             _INTC_LVL6IACK.Bits.VECN3
04871 #define INTC_LVL6IACK_VECN4             _INTC_LVL6IACK.Bits.VECN4
04872 #define INTC_LVL6IACK_VECN5             _INTC_LVL6IACK.Bits.VECN5
04873 #define INTC_LVL6IACK_VECN6             _INTC_LVL6IACK.Bits.VECN6
04874 #define INTC_LVL6IACK_VECN              _INTC_LVL6IACK.MergedBits.grpVECN
04875 
04876 #define INTC_LVL6IACK_VECN0_MASK        1U
04877 #define INTC_LVL6IACK_VECN1_MASK        2U
04878 #define INTC_LVL6IACK_VECN2_MASK        4U
04879 #define INTC_LVL6IACK_VECN3_MASK        8U
04880 #define INTC_LVL6IACK_VECN4_MASK        16U
04881 #define INTC_LVL6IACK_VECN5_MASK        32U
04882 #define INTC_LVL6IACK_VECN6_MASK        64U
04883 #define INTC_LVL6IACK_VECN_MASK         127U
04884 #define INTC_LVL6IACK_VECN_BITNUM       0U
04885 
04886 
04887 /*** INTC_LVL7IACK - INTC Level 7 IACK Register; 0xFFFFFFFC ***/
04888 typedef union {
04889   byte Byte;
04890   struct {
04891     byte VECN0       :1;                                       /* Vector number, bit 0 */
04892     byte VECN1       :1;                                       /* Vector number, bit 1 */
04893     byte VECN2       :1;                                       /* Vector number, bit 2 */
04894     byte VECN3       :1;                                       /* Vector number, bit 3 */
04895     byte VECN4       :1;                                       /* Vector number, bit 4 */
04896     byte VECN5       :1;                                       /* Vector number, bit 5 */
04897     byte VECN6       :1;                                       /* Vector number, bit 6 */
04898     byte             :1; 
04899   } Bits;
04900   struct {
04901     byte grpVECN :7;
04902     byte         :1;
04903   } MergedBits;
04904 } INTC_LVL7IACKSTR;
04905 extern volatile INTC_LVL7IACKSTR _INTC_LVL7IACK @0xFFFFFFFC;
04906 #define INTC_LVL7IACK                   _INTC_LVL7IACK.Byte
04907 #define INTC_LVL7IACK_VECN0             _INTC_LVL7IACK.Bits.VECN0
04908 #define INTC_LVL7IACK_VECN1             _INTC_LVL7IACK.Bits.VECN1
04909 #define INTC_LVL7IACK_VECN2             _INTC_LVL7IACK.Bits.VECN2
04910 #define INTC_LVL7IACK_VECN3             _INTC_LVL7IACK.Bits.VECN3
04911 #define INTC_LVL7IACK_VECN4             _INTC_LVL7IACK.Bits.VECN4
04912 #define INTC_LVL7IACK_VECN5             _INTC_LVL7IACK.Bits.VECN5
04913 #define INTC_LVL7IACK_VECN6             _INTC_LVL7IACK.Bits.VECN6
04914 #define INTC_LVL7IACK_VECN              _INTC_LVL7IACK.MergedBits.grpVECN
04915 
04916 #define INTC_LVL7IACK_VECN0_MASK        1U
04917 #define INTC_LVL7IACK_VECN1_MASK        2U
04918 #define INTC_LVL7IACK_VECN2_MASK        4U
04919 #define INTC_LVL7IACK_VECN3_MASK        8U
04920 #define INTC_LVL7IACK_VECN4_MASK        16U
04921 #define INTC_LVL7IACK_VECN5_MASK        32U
04922 #define INTC_LVL7IACK_VECN6_MASK        64U
04923 #define INTC_LVL7IACK_VECN_MASK         127U
04924 #define INTC_LVL7IACK_VECN_BITNUM       0U
04925 
04926 
04927 
04928 /***********************************************/
04929 /**   D E P R E C I A T E D   S Y M B O L S   **/
04930 /***********************************************/
04931 #pragma options align=reset
04932 
04933 #endif
04934 /*lint -restore Enable MISRA rule (5.1) checking. */
04935 /*lint -restore  +esym(960,18.4) +esym(961,19.7) Enable MISRA rule (1.1,18.4,6.4,19.7) checking. */