ISF
1.1
Intelligent Sensing Framework
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- s -
SIM_TR :
fxlc95000.h
SIM_TR_TP0 :
fxlc95000.h
SIM_TR_TP0_BITNUM :
fxlc95000.h
SIM_TR_TP0_MASK :
fxlc95000.h
SIM_TR_TP1 :
fxlc95000.h
SIM_TR_TP1_BITNUM :
fxlc95000.h
SIM_TR_TP1_MASK :
fxlc95000.h
SM_API_ALTERNATE_OFFERED :
isf_sm_api.h
SM_API_ERR_ALREADY_BEGUN :
isf_sm_api.h
SM_API_ERR_FIFO_OVER_LIMIT :
isf_sm_api.h
SM_API_ERR_NO_MEMORY :
isf_sm_api.h
SM_API_ERR_NOT_YET_BEGUN :
isf_sm_api.h
SM_API_ERR_SAMPLE_TAP_RATE :
isf_sm_api.h
SM_API_ERR_SENSOR_ALREADY_INITIALIZED :
isf_sm_api.h
SM_API_ERR_SENSOR_ID :
isf_sm_api.h
SM_API_ERR_SENSOR_INIT_FAILED :
isf_sm_api.h
SM_API_ERR_SENSOR_NOT_AVAIL :
isf_sm_api.h
SM_API_ERR_SETTINGS_TO_USE :
isf_sm_api.h
SM_API_ERR_SUBSCRIBER_COUNT :
isf_sm_api.h
SM_API_ERR_TOKEN_ID :
isf_sm_api.h
SM_MAX_FIFO_DEPTH :
isf_sm_api.h
SM_MAX_SUBSCRIBERS_PER_SENSOR :
isf_sm_api.h
SP_ADDR :
fxlc95000.h
SP_ADDR_ADDR :
fxlc95000.h
SP_ADDR_ADDR_BITNUM :
fxlc95000.h
SP_ADDR_ADDR_MASK :
fxlc95000.h
SP_MB0 :
fxlc95000.h
SP_MB0_dword :
fxlc95000.h
SP_MB0_word :
fxlc95000.h
SP_MB1 :
fxlc95000.h
SP_MB10 :
fxlc95000.h
SP_MB10_word :
fxlc95000.h
SP_MB11 :
fxlc95000.h
SP_MB11_word :
fxlc95000.h
SP_MB12 :
fxlc95000.h
SP_MB12_word :
fxlc95000.h
SP_MB13 :
fxlc95000.h
SP_MB13_word :
fxlc95000.h
SP_MB14 :
fxlc95000.h
SP_MB14_word :
fxlc95000.h
SP_MB15 :
fxlc95000.h
SP_MB15_word :
fxlc95000.h
SP_MB16 :
fxlc95000.h
SP_MB17 :
fxlc95000.h
SP_MB18 :
fxlc95000.h
SP_MB19 :
fxlc95000.h
SP_MB1_dword :
fxlc95000.h
SP_MB1_word :
fxlc95000.h
SP_MB2 :
fxlc95000.h
SP_MB20 :
fxlc95000.h
SP_MB21 :
fxlc95000.h
SP_MB22 :
fxlc95000.h
SP_MB23 :
fxlc95000.h
SP_MB24 :
fxlc95000.h
SP_MB25 :
fxlc95000.h
SP_MB26 :
fxlc95000.h
SP_MB27 :
fxlc95000.h
SP_MB28 :
fxlc95000.h
SP_MB29 :
fxlc95000.h
SP_MB2_dword :
fxlc95000.h
SP_MB2_word :
fxlc95000.h
SP_MB3 :
fxlc95000.h
SP_MB30 :
fxlc95000.h
SP_MB31 :
fxlc95000.h
SP_MB3_dword :
fxlc95000.h
SP_MB3_word :
fxlc95000.h
SP_MB4 :
fxlc95000.h
SP_MB4_dword :
fxlc95000.h
SP_MB4_word :
fxlc95000.h
SP_MB5 :
fxlc95000.h
SP_MB5_dword :
fxlc95000.h
SP_MB5_word :
fxlc95000.h
SP_MB6 :
fxlc95000.h
SP_MB6_dword :
fxlc95000.h
SP_MB6_word :
fxlc95000.h
SP_MB7 :
fxlc95000.h
SP_MB7_dword :
fxlc95000.h
SP_MB7_word :
fxlc95000.h
SP_MB8 :
fxlc95000.h
SP_MB8_word :
fxlc95000.h
SP_MB9 :
fxlc95000.h
SP_MB9_word :
fxlc95000.h
SP_MB_ARR :
fxlc95000.h
SP_MTOR0 :
fxlc95000.h
SP_MTOR0_EN :
fxlc95000.h
SP_MTOR0_EN_MASK :
fxlc95000.h
SP_MTOR0_MTE :
fxlc95000.h
SP_MTOR0_MTE_BITNUM :
fxlc95000.h
SP_MTOR0_MTE_MASK :
fxlc95000.h
SP_MTOR0_TOSTS :
fxlc95000.h
SP_MTOR0_TOSTS_MASK :
fxlc95000.h
SP_MTOR1 :
fxlc95000.h
SP_MTOR1_EN :
fxlc95000.h
SP_MTOR1_EN_MASK :
fxlc95000.h
SP_MTOR1_MTE :
fxlc95000.h
SP_MTOR1_MTE_BITNUM :
fxlc95000.h
SP_MTOR1_MTE_MASK :
fxlc95000.h
SP_MTOR1_TOSTS :
fxlc95000.h
SP_MTOR1_TOSTS_MASK :
fxlc95000.h
SP_MTOR_ARR :
fxlc95000.h
SP_MUTEX0 :
fxlc95000.h
SP_MUTEX0_SSTS :
fxlc95000.h
SP_MUTEX0_SSTS0 :
fxlc95000.h
SP_MUTEX0_SSTS0_MASK :
fxlc95000.h
SP_MUTEX0_SSTS1 :
fxlc95000.h
SP_MUTEX0_SSTS1_MASK :
fxlc95000.h
SP_MUTEX0_SSTS_BITNUM :
fxlc95000.h
SP_MUTEX0_SSTS_MASK :
fxlc95000.h
SP_MUTEX1 :
fxlc95000.h
SP_MUTEX1_SSTS :
fxlc95000.h
SP_MUTEX1_SSTS0 :
fxlc95000.h
SP_MUTEX1_SSTS0_MASK :
fxlc95000.h
SP_MUTEX1_SSTS1 :
fxlc95000.h
SP_MUTEX1_SSTS1_MASK :
fxlc95000.h
SP_MUTEX1_SSTS_BITNUM :
fxlc95000.h
SP_MUTEX1_SSTS_MASK :
fxlc95000.h
SP_MUTEX_ARR :
fxlc95000.h
SP_OIC :
fxlc95000.h
SP_OIC_CLR :
fxlc95000.h
SP_OIC_CLR_MASK :
fxlc95000.h
SP_OIC_POL :
fxlc95000.h
SP_OIC_POL_MASK :
fxlc95000.h
SP_OIC_SET_INT_O :
fxlc95000.h
SP_OIC_SET_INT_O_MASK :
fxlc95000.h
SP_RSTS0 :
fxlc95000.h
SP_RSTS0_D24 :
fxlc95000.h
SP_RSTS0_D24_MASK :
fxlc95000.h
SP_RSTS0_D25 :
fxlc95000.h
SP_RSTS0_D25_MASK :
fxlc95000.h
SP_RSTS0_D26 :
fxlc95000.h
SP_RSTS0_D26_MASK :
fxlc95000.h
SP_RSTS0_D27 :
fxlc95000.h
SP_RSTS0_D27_MASK :
fxlc95000.h
SP_RSTS0_D28 :
fxlc95000.h
SP_RSTS0_D28_MASK :
fxlc95000.h
SP_RSTS0_D29 :
fxlc95000.h
SP_RSTS0_D29_MASK :
fxlc95000.h
SP_RSTS0_D30 :
fxlc95000.h
SP_RSTS0_D30_MASK :
fxlc95000.h
SP_RSTS0_D31 :
fxlc95000.h
SP_RSTS0_D31_MASK :
fxlc95000.h
SP_RSTS1 :
fxlc95000.h
SP_RSTS1_D16 :
fxlc95000.h
SP_RSTS1_D16_MASK :
fxlc95000.h
SP_RSTS1_D17 :
fxlc95000.h
SP_RSTS1_D17_MASK :
fxlc95000.h
SP_RSTS1_D18 :
fxlc95000.h
SP_RSTS1_D18_MASK :
fxlc95000.h
SP_RSTS1_D19 :
fxlc95000.h
SP_RSTS1_D19_MASK :
fxlc95000.h
SP_RSTS1_D20 :
fxlc95000.h
SP_RSTS1_D20_MASK :
fxlc95000.h
SP_RSTS1_D21 :
fxlc95000.h
SP_RSTS1_D21_MASK :
fxlc95000.h
SP_RSTS1_D22 :
fxlc95000.h
SP_RSTS1_D22_MASK :
fxlc95000.h
SP_RSTS1_D23 :
fxlc95000.h
SP_RSTS1_D23_MASK :
fxlc95000.h
SP_RSTS2 :
fxlc95000.h
SP_RSTS2_D10 :
fxlc95000.h
SP_RSTS2_D10_MASK :
fxlc95000.h
SP_RSTS2_D11 :
fxlc95000.h
SP_RSTS2_D11_MASK :
fxlc95000.h
SP_RSTS2_D12 :
fxlc95000.h
SP_RSTS2_D12_MASK :
fxlc95000.h
SP_RSTS2_D13 :
fxlc95000.h
SP_RSTS2_D13_MASK :
fxlc95000.h
SP_RSTS2_D14 :
fxlc95000.h
SP_RSTS2_D14_MASK :
fxlc95000.h
SP_RSTS2_D15 :
fxlc95000.h
SP_RSTS2_D15_MASK :
fxlc95000.h
SP_RSTS2_D8 :
fxlc95000.h
SP_RSTS2_D8_MASK :
fxlc95000.h
SP_RSTS2_D9 :
fxlc95000.h
SP_RSTS2_D9_MASK :
fxlc95000.h
SP_RSTS3 :
fxlc95000.h
SP_RSTS3_D0 :
fxlc95000.h
SP_RSTS3_D0_MASK :
fxlc95000.h
SP_RSTS3_D1 :
fxlc95000.h
SP_RSTS3_D1_MASK :
fxlc95000.h
SP_RSTS3_D2 :
fxlc95000.h
SP_RSTS3_D2_MASK :
fxlc95000.h
SP_RSTS3_D3 :
fxlc95000.h
SP_RSTS3_D3_MASK :
fxlc95000.h
SP_RSTS3_D4 :
fxlc95000.h
SP_RSTS3_D4_MASK :
fxlc95000.h
SP_RSTS3_D5 :
fxlc95000.h
SP_RSTS3_D5_MASK :
fxlc95000.h
SP_RSTS3_D6 :
fxlc95000.h
SP_RSTS3_D6_MASK :
fxlc95000.h
SP_RSTS3_D7 :
fxlc95000.h
SP_RSTS3_D7_MASK :
fxlc95000.h
SP_RSTS_ARR :
fxlc95000.h
SP_SCR :
fxlc95000.h
SP_SCR_ACTIVE_CSR :
fxlc95000.h
SP_SCR_ACTIVE_CSR_MASK :
fxlc95000.h
SP_SCR_EN :
fxlc95000.h
SP_SCR_EN_MASK :
fxlc95000.h
SP_SCR_PS :
fxlc95000.h
SP_SCR_PS_MASK :
fxlc95000.h
SP_SCR_RIE :
fxlc95000.h
SP_SCR_RIE_MASK :
fxlc95000.h
SP_SCR_STOP_EN :
fxlc95000.h
SP_SCR_STOP_EN_MASK :
fxlc95000.h
SP_SCR_WIE :
fxlc95000.h
SP_SCR_WIE_MASK :
fxlc95000.h
SP_SCR_WUP :
fxlc95000.h
SP_SCR_WUP0 :
fxlc95000.h
SP_SCR_WUP0_MASK :
fxlc95000.h
SP_SCR_WUP1 :
fxlc95000.h
SP_SCR_WUP1_MASK :
fxlc95000.h
SP_SCR_WUP_BITNUM :
fxlc95000.h
SP_SCR_WUP_MASK :
fxlc95000.h
SP_WSTS0 :
fxlc95000.h
SP_WSTS0_D24 :
fxlc95000.h
SP_WSTS0_D24_MASK :
fxlc95000.h
SP_WSTS0_D25 :
fxlc95000.h
SP_WSTS0_D25_MASK :
fxlc95000.h
SP_WSTS0_D26 :
fxlc95000.h
SP_WSTS0_D26_MASK :
fxlc95000.h
SP_WSTS0_D27 :
fxlc95000.h
SP_WSTS0_D27_MASK :
fxlc95000.h
SP_WSTS0_D28 :
fxlc95000.h
SP_WSTS0_D28_MASK :
fxlc95000.h
SP_WSTS0_D29 :
fxlc95000.h
SP_WSTS0_D29_MASK :
fxlc95000.h
SP_WSTS0_D30 :
fxlc95000.h
SP_WSTS0_D30_MASK :
fxlc95000.h
SP_WSTS0_D31 :
fxlc95000.h
SP_WSTS0_D31_MASK :
fxlc95000.h
SP_WSTS1 :
fxlc95000.h
SP_WSTS1_D16 :
fxlc95000.h
SP_WSTS1_D16_MASK :
fxlc95000.h
SP_WSTS1_D17 :
fxlc95000.h
SP_WSTS1_D17_MASK :
fxlc95000.h
SP_WSTS1_D18 :
fxlc95000.h
SP_WSTS1_D18_MASK :
fxlc95000.h
SP_WSTS1_D19 :
fxlc95000.h
SP_WSTS1_D19_MASK :
fxlc95000.h
SP_WSTS1_D20 :
fxlc95000.h
SP_WSTS1_D20_MASK :
fxlc95000.h
SP_WSTS1_D21 :
fxlc95000.h
SP_WSTS1_D21_MASK :
fxlc95000.h
SP_WSTS1_D22 :
fxlc95000.h
SP_WSTS1_D22_MASK :
fxlc95000.h
SP_WSTS1_D23 :
fxlc95000.h
SP_WSTS1_D23_MASK :
fxlc95000.h
SP_WSTS2 :
fxlc95000.h
SP_WSTS2_D10 :
fxlc95000.h
SP_WSTS2_D10_MASK :
fxlc95000.h
SP_WSTS2_D11 :
fxlc95000.h
SP_WSTS2_D11_MASK :
fxlc95000.h
SP_WSTS2_D12 :
fxlc95000.h
SP_WSTS2_D12_MASK :
fxlc95000.h
SP_WSTS2_D13 :
fxlc95000.h
SP_WSTS2_D13_MASK :
fxlc95000.h
SP_WSTS2_D14 :
fxlc95000.h
SP_WSTS2_D14_MASK :
fxlc95000.h
SP_WSTS2_D15 :
fxlc95000.h
SP_WSTS2_D15_MASK :
fxlc95000.h
SP_WSTS2_D8 :
fxlc95000.h
SP_WSTS2_D8_MASK :
fxlc95000.h
SP_WSTS2_D9 :
fxlc95000.h
SP_WSTS2_D9_MASK :
fxlc95000.h
SP_WSTS3 :
fxlc95000.h
SP_WSTS3_D0 :
fxlc95000.h
SP_WSTS3_D0_MASK :
fxlc95000.h
SP_WSTS3_D1 :
fxlc95000.h
SP_WSTS3_D1_MASK :
fxlc95000.h
SP_WSTS3_D2 :
fxlc95000.h
SP_WSTS3_D2_MASK :
fxlc95000.h
SP_WSTS3_D3 :
fxlc95000.h
SP_WSTS3_D3_MASK :
fxlc95000.h
SP_WSTS3_D4 :
fxlc95000.h
SP_WSTS3_D4_MASK :
fxlc95000.h
SP_WSTS3_D5 :
fxlc95000.h
SP_WSTS3_D5_MASK :
fxlc95000.h
SP_WSTS3_D6 :
fxlc95000.h
SP_WSTS3_D6_MASK :
fxlc95000.h
SP_WSTS3_D7 :
fxlc95000.h
SP_WSTS3_D7_MASK :
fxlc95000.h
SP_WSTS_ARR :
fxlc95000.h
SPI_SPDRR :
fxlc95000.h
SPI_SPDRR_R0 :
fxlc95000.h
SPI_SPDRR_R0_MASK :
fxlc95000.h
SPI_SPDRR_R1 :
fxlc95000.h
SPI_SPDRR_R10 :
fxlc95000.h
SPI_SPDRR_R10_MASK :
fxlc95000.h
SPI_SPDRR_R11 :
fxlc95000.h
SPI_SPDRR_R11_MASK :
fxlc95000.h
SPI_SPDRR_R12 :
fxlc95000.h
SPI_SPDRR_R12_MASK :
fxlc95000.h
SPI_SPDRR_R13 :
fxlc95000.h
SPI_SPDRR_R13_MASK :
fxlc95000.h
SPI_SPDRR_R14 :
fxlc95000.h
SPI_SPDRR_R14_MASK :
fxlc95000.h
SPI_SPDRR_R15 :
fxlc95000.h
SPI_SPDRR_R15_MASK :
fxlc95000.h
SPI_SPDRR_R1_MASK :
fxlc95000.h
SPI_SPDRR_R2 :
fxlc95000.h
SPI_SPDRR_R2_MASK :
fxlc95000.h
SPI_SPDRR_R3 :
fxlc95000.h
SPI_SPDRR_R3_MASK :
fxlc95000.h
SPI_SPDRR_R4 :
fxlc95000.h
SPI_SPDRR_R4_MASK :
fxlc95000.h
SPI_SPDRR_R5 :
fxlc95000.h
SPI_SPDRR_R5_MASK :
fxlc95000.h
SPI_SPDRR_R6 :
fxlc95000.h
SPI_SPDRR_R6_MASK :
fxlc95000.h
SPI_SPDRR_R7 :
fxlc95000.h
SPI_SPDRR_R7_MASK :
fxlc95000.h
SPI_SPDRR_R8 :
fxlc95000.h
SPI_SPDRR_R8_MASK :
fxlc95000.h
SPI_SPDRR_R9 :
fxlc95000.h
SPI_SPDRR_R9_MASK :
fxlc95000.h
SPI_SPDSR :
fxlc95000.h
SPI_SPDSR_BD2X :
fxlc95000.h
SPI_SPDSR_BD2X_MASK :
fxlc95000.h
SPI_SPDSR_DS :
fxlc95000.h
SPI_SPDSR_DS0 :
fxlc95000.h
SPI_SPDSR_DS0_MASK :
fxlc95000.h
SPI_SPDSR_DS1 :
fxlc95000.h
SPI_SPDSR_DS1_MASK :
fxlc95000.h
SPI_SPDSR_DS2 :
fxlc95000.h
SPI_SPDSR_DS2_MASK :
fxlc95000.h
SPI_SPDSR_DS3 :
fxlc95000.h
SPI_SPDSR_DS3_MASK :
fxlc95000.h
SPI_SPDSR_DS_BITNUM :
fxlc95000.h
SPI_SPDSR_DS_MASK :
fxlc95000.h
SPI_SPDSR_SPR3 :
fxlc95000.h
SPI_SPDSR_SPR3_MASK :
fxlc95000.h
SPI_SPDSR_SSB_AUTO :
fxlc95000.h
SPI_SPDSR_SSB_AUTO_MASK :
fxlc95000.h
SPI_SPDSR_SSB_DATA :
fxlc95000.h
SPI_SPDSR_SSB_DATA_MASK :
fxlc95000.h
SPI_SPDSR_SSB_DDR :
fxlc95000.h
SPI_SPDSR_SSB_DDR_MASK :
fxlc95000.h
SPI_SPDSR_SSB_IN :
fxlc95000.h
SPI_SPDSR_SSB_IN_MASK :
fxlc95000.h
SPI_SPDSR_SSB_ODM :
fxlc95000.h
SPI_SPDSR_SSB_ODM_MASK :
fxlc95000.h
SPI_SPDSR_SSB_OVER :
fxlc95000.h
SPI_SPDSR_SSB_OVER_MASK :
fxlc95000.h
SPI_SPDSR_SSB_STRB :
fxlc95000.h
SPI_SPDSR_SSB_STRB_MASK :
fxlc95000.h
SPI_SPDSR_WOM :
fxlc95000.h
SPI_SPDSR_WOM_MASK :
fxlc95000.h
SPI_SPDTR :
fxlc95000.h
SPI_SPDTR_T0 :
fxlc95000.h
SPI_SPDTR_T0_MASK :
fxlc95000.h
SPI_SPDTR_T1 :
fxlc95000.h
SPI_SPDTR_T10 :
fxlc95000.h
SPI_SPDTR_T10_MASK :
fxlc95000.h
SPI_SPDTR_T11 :
fxlc95000.h
SPI_SPDTR_T11_MASK :
fxlc95000.h
SPI_SPDTR_T12 :
fxlc95000.h
SPI_SPDTR_T12_MASK :
fxlc95000.h
SPI_SPDTR_T13 :
fxlc95000.h
SPI_SPDTR_T13_MASK :
fxlc95000.h
SPI_SPDTR_T14 :
fxlc95000.h
SPI_SPDTR_T14_MASK :
fxlc95000.h
SPI_SPDTR_T15 :
fxlc95000.h
SPI_SPDTR_T15_MASK :
fxlc95000.h
SPI_SPDTR_T1_MASK :
fxlc95000.h
SPI_SPDTR_T2 :
fxlc95000.h
SPI_SPDTR_T2_MASK :
fxlc95000.h
SPI_SPDTR_T3 :
fxlc95000.h
SPI_SPDTR_T3_MASK :
fxlc95000.h
SPI_SPDTR_T4 :
fxlc95000.h
SPI_SPDTR_T4_MASK :
fxlc95000.h
SPI_SPDTR_T5 :
fxlc95000.h
SPI_SPDTR_T5_MASK :
fxlc95000.h
SPI_SPDTR_T6 :
fxlc95000.h
SPI_SPDTR_T6_MASK :
fxlc95000.h
SPI_SPDTR_T7 :
fxlc95000.h
SPI_SPDTR_T7_MASK :
fxlc95000.h
SPI_SPDTR_T8 :
fxlc95000.h
SPI_SPDTR_T8_MASK :
fxlc95000.h
SPI_SPDTR_T9 :
fxlc95000.h
SPI_SPDTR_T9_MASK :
fxlc95000.h
SPI_SPFIFO :
fxlc95000.h
SPI_SPFIFO_FIFO_ENA :
fxlc95000.h
SPI_SPFIFO_FIFO_ENA_MASK :
fxlc95000.h
SPI_SPFIFO_RFCNT :
fxlc95000.h
SPI_SPFIFO_RFCNT0 :
fxlc95000.h
SPI_SPFIFO_RFCNT0_MASK :
fxlc95000.h
SPI_SPFIFO_RFCNT1 :
fxlc95000.h
SPI_SPFIFO_RFCNT1_MASK :
fxlc95000.h
SPI_SPFIFO_RFCNT2 :
fxlc95000.h
SPI_SPFIFO_RFCNT2_MASK :
fxlc95000.h
SPI_SPFIFO_RFCNT_BITNUM :
fxlc95000.h
SPI_SPFIFO_RFCNT_MASK :
fxlc95000.h
SPI_SPFIFO_RFWM :
fxlc95000.h
SPI_SPFIFO_RFWM0 :
fxlc95000.h
SPI_SPFIFO_RFWM0_MASK :
fxlc95000.h
SPI_SPFIFO_RFWM1 :
fxlc95000.h
SPI_SPFIFO_RFWM1_MASK :
fxlc95000.h
SPI_SPFIFO_RFWM_BITNUM :
fxlc95000.h
SPI_SPFIFO_RFWM_MASK :
fxlc95000.h
SPI_SPFIFO_TFCNT :
fxlc95000.h
SPI_SPFIFO_TFCNT0 :
fxlc95000.h
SPI_SPFIFO_TFCNT0_MASK :
fxlc95000.h
SPI_SPFIFO_TFCNT1 :
fxlc95000.h
SPI_SPFIFO_TFCNT1_MASK :
fxlc95000.h
SPI_SPFIFO_TFCNT2 :
fxlc95000.h
SPI_SPFIFO_TFCNT2_MASK :
fxlc95000.h
SPI_SPFIFO_TFCNT_BITNUM :
fxlc95000.h
SPI_SPFIFO_TFCNT_MASK :
fxlc95000.h
SPI_SPFIFO_TFWM :
fxlc95000.h
SPI_SPFIFO_TFWM0 :
fxlc95000.h
SPI_SPFIFO_TFWM0_MASK :
fxlc95000.h
SPI_SPFIFO_TFWM1 :
fxlc95000.h
SPI_SPFIFO_TFWM1_MASK :
fxlc95000.h
SPI_SPFIFO_TFWM_BITNUM :
fxlc95000.h
SPI_SPFIFO_TFWM_MASK :
fxlc95000.h
SPI_SPSCR :
fxlc95000.h
SPI_SPSCR_CPHA :
fxlc95000.h
SPI_SPSCR_CPHA_MASK :
fxlc95000.h
SPI_SPSCR_CPOL :
fxlc95000.h
SPI_SPSCR_CPOL_MASK :
fxlc95000.h
SPI_SPSCR_DSO :
fxlc95000.h
SPI_SPSCR_DSO_MASK :
fxlc95000.h
SPI_SPSCR_ERRIE :
fxlc95000.h
SPI_SPSCR_ERRIE_MASK :
fxlc95000.h
SPI_SPSCR_MODF :
fxlc95000.h
SPI_SPSCR_MODF_MASK :
fxlc95000.h
SPI_SPSCR_MODFEN :
fxlc95000.h
SPI_SPSCR_MODFEN_MASK :
fxlc95000.h
SPI_SPSCR_OVRF :
fxlc95000.h
SPI_SPSCR_OVRF_MASK :
fxlc95000.h
SPI_SPSCR_SPE :
fxlc95000.h
SPI_SPSCR_SPE_MASK :
fxlc95000.h
SPI_SPSCR_SPMSTR :
fxlc95000.h
SPI_SPSCR_SPMSTR_MASK :
fxlc95000.h
SPI_SPSCR_SPR :
fxlc95000.h
SPI_SPSCR_SPR0 :
fxlc95000.h
SPI_SPSCR_SPR0_MASK :
fxlc95000.h
SPI_SPSCR_SPR1 :
fxlc95000.h
SPI_SPSCR_SPR1_MASK :
fxlc95000.h
SPI_SPSCR_SPR2 :
fxlc95000.h
SPI_SPSCR_SPR2_MASK :
fxlc95000.h
SPI_SPSCR_SPR_BITNUM :
fxlc95000.h
SPI_SPSCR_SPR_MASK :
fxlc95000.h
SPI_SPSCR_SPRF :
fxlc95000.h
SPI_SPSCR_SPRF_MASK :
fxlc95000.h
SPI_SPSCR_SPRIE :
fxlc95000.h
SPI_SPSCR_SPRIE_MASK :
fxlc95000.h
SPI_SPSCR_SPTE :
fxlc95000.h
SPI_SPSCR_SPTE_MASK :
fxlc95000.h
SPI_SPSCR_SPTIE :
fxlc95000.h
SPI_SPSCR_SPTIE_MASK :
fxlc95000.h
SPI_SPWAIT :
fxlc95000.h
SPI_SPWAIT_WAIT :
fxlc95000.h
SPI_SPWAIT_WAIT0 :
fxlc95000.h
SPI_SPWAIT_WAIT0_MASK :
fxlc95000.h
SPI_SPWAIT_WAIT1 :
fxlc95000.h
SPI_SPWAIT_WAIT10 :
fxlc95000.h
SPI_SPWAIT_WAIT10_MASK :
fxlc95000.h
SPI_SPWAIT_WAIT11 :
fxlc95000.h
SPI_SPWAIT_WAIT11_MASK :
fxlc95000.h
SPI_SPWAIT_WAIT12 :
fxlc95000.h
SPI_SPWAIT_WAIT12_MASK :
fxlc95000.h
SPI_SPWAIT_WAIT1_MASK :
fxlc95000.h
SPI_SPWAIT_WAIT2 :
fxlc95000.h
SPI_SPWAIT_WAIT2_MASK :
fxlc95000.h
SPI_SPWAIT_WAIT3 :
fxlc95000.h
SPI_SPWAIT_WAIT3_MASK :
fxlc95000.h
SPI_SPWAIT_WAIT4 :
fxlc95000.h
SPI_SPWAIT_WAIT4_MASK :
fxlc95000.h
SPI_SPWAIT_WAIT5 :
fxlc95000.h
SPI_SPWAIT_WAIT5_MASK :
fxlc95000.h
SPI_SPWAIT_WAIT6 :
fxlc95000.h
SPI_SPWAIT_WAIT6_MASK :
fxlc95000.h
SPI_SPWAIT_WAIT7 :
fxlc95000.h
SPI_SPWAIT_WAIT7_MASK :
fxlc95000.h
SPI_SPWAIT_WAIT8 :
fxlc95000.h
SPI_SPWAIT_WAIT8_MASK :
fxlc95000.h
SPI_SPWAIT_WAIT9 :
fxlc95000.h
SPI_SPWAIT_WAIT9_MASK :
fxlc95000.h
SPI_SPWAIT_WAIT_BITNUM :
fxlc95000.h
SPI_SPWAIT_WAIT_MASK :
fxlc95000.h
STOPCR :
fxlc95000.h
STOPCR_FC :
fxlc95000.h
STOPCR_FC_MASK :
fxlc95000.h
STOPCR_NC :
fxlc95000.h
STOPCR_NC_MASK :
fxlc95000.h
STOPCR_SC :
fxlc95000.h
STOPCR_SC_MASK :
fxlc95000.h
STOPCR_SCtoFC :
fxlc95000.h
STOPCR_SCtoFC_MASK :
fxlc95000.h
© Freescale Semiconductor, Inc. 2014. All Rights Reserved.