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Vectors_Config.h
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1 /** ###################################################################
2 ** Filename : Vectors_Config.h
3 ** Processor : MK64FN1M0VLL12
4 ** Version : 1.00
5 **
6 ** Copyright : 1997 - 2014 Freescale Semiconductor, Inc.
7 ** All Rights Reserved.
8 **
9 ** Redistribution and use in source and binary forms, with or without modification,
10 ** are permitted provided that the following conditions are met:
11 **
12 ** o Redistributions of source code must retain the above copyright notice, this list
13 ** of conditions and the following disclaimer.
14 **
15 ** o Redistributions in binary form must reproduce the above copyright notice, this
16 ** list of conditions and the following disclaimer in the documentation and/or
17 ** other materials provided with the distribution.
18 **
19 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
20 ** contributors may be used to endorse or promote products derived from this
21 ** software without specific prior written permission.
22 **
23 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
24 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
27 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 **
34 ** http: www.freescale.com
35 ** mail: support@freescale.com
36 ** ###################################################################*/
37 /*!
38 ** @file Vectors_Config.h
39 ** @version 01.00
40 */
41 /*!
42 ** @addtogroup Vectors_Config_module Vectors_Config module documentation
43 ** @{
44 */
45
46 #ifndef __Vectors_Config_H
47 #define __Vectors_Config_H
48
49 /* MODULE Vectors_Config.h */
50
51 #include "Cpu.h"
52 #include "Pins1.h"
53 #include "MQX1.h"
54 #include "SystemTimer1.h"
55 #include "I2C_CH1.h"
56 #include "I2CBUS1.h"
57 #include "UART_CH1.h"
58 #include "Serial_ISF_UART1.h"
59 #include "ISFCore1.h"
60 #include "ISFBusManager1.h"
61 #include "BMTimer1.h"
62 #include "CommChannelConfig1.h"
63 #include "SPI_CH1.h"
64 #include "SPIMasterBus1.h"
65 #include "MAG3110_1.h"
66 #include "FXOS8700_1.h"
67 #include "FXAS21002_1.h"
68 #include "ORIENT_1.h"
69 #include "FXLS8471_1.h"
70 #include "GPIO1.h"
71 #include "MPL3115_1.h"
72 #include "MMA865x_1.h"
73 #include "RLI1.h"
74 #include "Protocol1.h"
75 #include "App1.h"
76 #include "Events.h"
77 #include "mqx_tasks.h"
78 #include "App1_Functions.h"
79
80 #ifdef __cplusplus
81 extern "C" {
82 #endif
83
84 #define PEX_VECTOR_TABLE 0x01U /* Vector table is managed by PEx */
85
86 /* Vector Address No. Pri Name Description */
87 #define VECTOR_SP_MAIN &__SP_INIT /* 0x00 - ivINT_Initial_Stack_Pointer used by PE */
88 #define VECTOR_1 (tIsrFunc)&__boot /* 0x01 - ivINT_Initial_Program_Counter used by PE */
89 #define VECTOR_2 (tIsrFunc)&UnhandledInterrupt /* 0x02 -2 ivINT_NMI unused by PE */
90 #define VECTOR_3 (tIsrFunc)&UnhandledInterrupt /* 0x03 -1 ivINT_Hard_Fault unused by PE */
91 #define VECTOR_4 (tIsrFunc)&UnhandledInterrupt /* 0x04 - ivINT_Mem_Manage_Fault unused by PE */
92 #define VECTOR_5 (tIsrFunc)&UnhandledInterrupt /* 0x05 - ivINT_Bus_Fault unused by PE */
93 #define VECTOR_6 (tIsrFunc)&UnhandledInterrupt /* 0x06 - ivINT_Usage_Fault unused by PE */
94 #define VECTOR_7 (tIsrFunc)&UnhandledInterrupt /* 0x07 - ivINT_Reserved7 unused by PE */
95 #define VECTOR_8 (tIsrFunc)&UnhandledInterrupt /* 0x08 - ivINT_Reserved8 unused by PE */
96 #define VECTOR_9 (tIsrFunc)&UnhandledInterrupt /* 0x09 - ivINT_Reserved9 unused by PE */
97 #define VECTOR_10 (tIsrFunc)&UnhandledInterrupt /* 0x0A - ivINT_Reserved10 unused by PE */
98 #define VECTOR_11 (tIsrFunc)&_svc_handler /* 0x0B - ivINT_SVCall used by PE */
99 #define VECTOR_12 (tIsrFunc)&UnhandledInterrupt /* 0x0C - ivINT_DebugMonitor unused by PE */
100 #define VECTOR_13 (tIsrFunc)&UnhandledInterrupt /* 0x0D - ivINT_Reserved13 unused by PE */
101 #define VECTOR_14 (tIsrFunc)&_pend_svc /* 0x0E - ivINT_PendableSrvReq used by PE */
102 #define VECTOR_15 (tIsrFunc)&_int_kernel_isr /* 0x0F 112 ivINT_SysTick used by PE */
103 #define VECTOR_16 (tIsrFunc)&_int_kernel_isr /* 0x10 - ivINT_DMA0 used by PE */
104 #define VECTOR_17 (tIsrFunc)&_int_kernel_isr /* 0x11 - ivINT_DMA1 used by PE */
105 #define VECTOR_18 (tIsrFunc)&_int_kernel_isr /* 0x12 - ivINT_DMA2 used by PE */
106 #define VECTOR_19 (tIsrFunc)&_int_kernel_isr /* 0x13 - ivINT_DMA3 used by PE */
107 #define VECTOR_20 (tIsrFunc)&_int_kernel_isr /* 0x14 - ivINT_DMA4 used by PE */
108 #define VECTOR_21 (tIsrFunc)&_int_kernel_isr /* 0x15 - ivINT_DMA5 used by PE */
109 #define VECTOR_22 (tIsrFunc)&_int_kernel_isr /* 0x16 - ivINT_DMA6 used by PE */
110 #define VECTOR_23 (tIsrFunc)&_int_kernel_isr /* 0x17 - ivINT_DMA7 used by PE */
111 #define VECTOR_24 (tIsrFunc)&_int_kernel_isr /* 0x18 - ivINT_DMA8 used by PE */
112 #define VECTOR_25 (tIsrFunc)&_int_kernel_isr /* 0x19 - ivINT_DMA9 used by PE */
113 #define VECTOR_26 (tIsrFunc)&_int_kernel_isr /* 0x1A - ivINT_DMA10 used by PE */
114 #define VECTOR_27 (tIsrFunc)&_int_kernel_isr /* 0x1B - ivINT_DMA11 used by PE */
115 #define VECTOR_28 (tIsrFunc)&_int_kernel_isr /* 0x1C - ivINT_DMA12 used by PE */
116 #define VECTOR_29 (tIsrFunc)&_int_kernel_isr /* 0x1D - ivINT_DMA13 used by PE */
117 #define VECTOR_30 (tIsrFunc)&_int_kernel_isr /* 0x1E - ivINT_DMA14 used by PE */
118 #define VECTOR_31 (tIsrFunc)&_int_kernel_isr /* 0x1F - ivINT_DMA15 used by PE */
119 #define VECTOR_32 (tIsrFunc)&_int_kernel_isr /* 0x20 - ivINT_DMA_Error used by PE */
120 #define VECTOR_33 (tIsrFunc)&_int_kernel_isr /* 0x21 - ivINT_MCM used by PE */
121 #define VECTOR_34 (tIsrFunc)&_int_kernel_isr /* 0x22 - ivINT_FTFE used by PE */
122 #define VECTOR_35 (tIsrFunc)&_int_kernel_isr /* 0x23 - ivINT_Read_Collision used by PE */
123 #define VECTOR_36 (tIsrFunc)&_int_kernel_isr /* 0x24 - ivINT_LVD_LVW used by PE */
124 #define VECTOR_37 (tIsrFunc)&_int_kernel_isr /* 0x25 - ivINT_LLW used by PE */
125 #define VECTOR_38 (tIsrFunc)&_int_kernel_isr /* 0x26 - ivINT_Watchdog used by PE */
126 #define VECTOR_39 (tIsrFunc)&_int_kernel_isr /* 0x27 - ivINT_RNG used by PE */
127 #define VECTOR_40 (tIsrFunc)&_int_kernel_isr /* 0x28 - ivINT_I2C0 used by PE */
128 #define VECTOR_41 (tIsrFunc)&_int_kernel_isr /* 0x29 112 ivINT_I2C1 used by PE */
129 #define VECTOR_42 (tIsrFunc)&_int_kernel_isr /* 0x2A 112 ivINT_SPI0 used by PE */
130 #define VECTOR_43 (tIsrFunc)&_int_kernel_isr /* 0x2B - ivINT_SPI1 used by PE */
131 #define VECTOR_44 (tIsrFunc)&_int_kernel_isr /* 0x2C - ivINT_I2S0_Tx used by PE */
132 #define VECTOR_45 (tIsrFunc)&_int_kernel_isr /* 0x2D - ivINT_I2S0_Rx used by PE */
133 #define VECTOR_46 (tIsrFunc)&_int_kernel_isr /* 0x2E - ivINT_UART0_LON used by PE */
134 #define VECTOR_47 (tIsrFunc)&_int_kernel_isr /* 0x2F 112 ivINT_UART0_RX_TX used by PE */
135 #define VECTOR_48 (tIsrFunc)&_int_kernel_isr /* 0x30 112 ivINT_UART0_ERR used by PE */
136 #define VECTOR_49 (tIsrFunc)&_int_kernel_isr /* 0x31 - ivINT_UART1_RX_TX used by PE */
137 #define VECTOR_50 (tIsrFunc)&_int_kernel_isr /* 0x32 - ivINT_UART1_ERR used by PE */
138 #define VECTOR_51 (tIsrFunc)&_int_kernel_isr /* 0x33 - ivINT_UART2_RX_TX used by PE */
139 #define VECTOR_52 (tIsrFunc)&_int_kernel_isr /* 0x34 - ivINT_UART2_ERR used by PE */
140 #define VECTOR_53 (tIsrFunc)&_int_kernel_isr /* 0x35 - ivINT_UART3_RX_TX used by PE */
141 #define VECTOR_54 (tIsrFunc)&_int_kernel_isr /* 0x36 - ivINT_UART3_ERR used by PE */
142 #define VECTOR_55 (tIsrFunc)&_int_kernel_isr /* 0x37 - ivINT_ADC0 used by PE */
143 #define VECTOR_56 (tIsrFunc)&_int_kernel_isr /* 0x38 - ivINT_CMP0 used by PE */
144 #define VECTOR_57 (tIsrFunc)&_int_kernel_isr /* 0x39 - ivINT_CMP1 used by PE */
145 #define VECTOR_58 (tIsrFunc)&_int_kernel_isr /* 0x3A - ivINT_FTM0 used by PE */
146 #define VECTOR_59 (tIsrFunc)&_int_kernel_isr /* 0x3B - ivINT_FTM1 used by PE */
147 #define VECTOR_60 (tIsrFunc)&_int_kernel_isr /* 0x3C - ivINT_FTM2 used by PE */
148 #define VECTOR_61 (tIsrFunc)&_int_kernel_isr /* 0x3D - ivINT_CMT used by PE */
149 #define VECTOR_62 (tIsrFunc)&_int_kernel_isr /* 0x3E - ivINT_RTC used by PE */
150 #define VECTOR_63 (tIsrFunc)&_int_kernel_isr /* 0x3F - ivINT_RTC_Seconds used by PE */
151 #define VECTOR_64 (tIsrFunc)&_int_kernel_isr /* 0x40 112 ivINT_PIT0 used by PE */
152 #define VECTOR_65 (tIsrFunc)&_int_kernel_isr /* 0x41 - ivINT_PIT1 used by PE */
153 #define VECTOR_66 (tIsrFunc)&_int_kernel_isr /* 0x42 - ivINT_PIT2 used by PE */
154 #define VECTOR_67 (tIsrFunc)&_int_kernel_isr /* 0x43 - ivINT_PIT3 used by PE */
155 #define VECTOR_68 (tIsrFunc)&_int_kernel_isr /* 0x44 - ivINT_PDB0 used by PE */
156 #define VECTOR_69 (tIsrFunc)&_int_kernel_isr /* 0x45 - ivINT_USB0 used by PE */
157 #define VECTOR_70 (tIsrFunc)&_int_kernel_isr /* 0x46 - ivINT_USBDCD used by PE */
158 #define VECTOR_71 (tIsrFunc)&_int_kernel_isr /* 0x47 - ivINT_Reserved71 used by PE */
159 #define VECTOR_72 (tIsrFunc)&_int_kernel_isr /* 0x48 - ivINT_DAC0 used by PE */
160 #define VECTOR_73 (tIsrFunc)&_int_kernel_isr /* 0x49 - ivINT_MCG used by PE */
161 #define VECTOR_74 (tIsrFunc)&_int_kernel_isr /* 0x4A - ivINT_LPTimer used by PE */
162 #define VECTOR_75 (tIsrFunc)&_int_kernel_isr /* 0x4B - ivINT_PORTA used by PE */
163 #define VECTOR_76 (tIsrFunc)&_int_kernel_isr /* 0x4C - ivINT_PORTB used by PE */
164 #define VECTOR_77 (tIsrFunc)&_int_kernel_isr /* 0x4D - ivINT_PORTC used by PE */
165 #define VECTOR_78 (tIsrFunc)&_int_kernel_isr /* 0x4E - ivINT_PORTD used by PE */
166 #define VECTOR_79 (tIsrFunc)&_int_kernel_isr /* 0x4F - ivINT_PORTE used by PE */
167 #define VECTOR_80 (tIsrFunc)&_int_kernel_isr /* 0x50 - ivINT_SWI used by PE */
168 #define VECTOR_81 (tIsrFunc)&_int_kernel_isr /* 0x51 - ivINT_SPI2 used by PE */
169 #define VECTOR_82 (tIsrFunc)&_int_kernel_isr /* 0x52 - ivINT_UART4_RX_TX used by PE */
170 #define VECTOR_83 (tIsrFunc)&_int_kernel_isr /* 0x53 - ivINT_UART4_ERR used by PE */
171 #define VECTOR_84 (tIsrFunc)&_int_kernel_isr /* 0x54 - ivINT_UART5_RX_TX used by PE */
172 #define VECTOR_85 (tIsrFunc)&_int_kernel_isr /* 0x55 - ivINT_UART5_ERR used by PE */
173 #define VECTOR_86 (tIsrFunc)&_int_kernel_isr /* 0x56 - ivINT_CMP2 used by PE */
174 #define VECTOR_87 (tIsrFunc)&_int_kernel_isr /* 0x57 - ivINT_FTM3 used by PE */
175 #define VECTOR_88 (tIsrFunc)&_int_kernel_isr /* 0x58 - ivINT_Reserved88 used by PE */
176 #define VECTOR_89 (tIsrFunc)&_int_kernel_isr /* 0x59 - ivINT_ADC1 used by PE */
177 #define VECTOR_90 (tIsrFunc)&_int_kernel_isr /* 0x5A - ivINT_I2C2 used by PE */
178 #define VECTOR_91 (tIsrFunc)&_int_kernel_isr /* 0x5B - ivINT_CAN0_ORed_Message_buffer used by PE */
179 #define VECTOR_92 (tIsrFunc)&_int_kernel_isr /* 0x5C - ivINT_CAN0_Bus_Off used by PE */
180 #define VECTOR_93 (tIsrFunc)&_int_kernel_isr /* 0x5D - ivINT_CAN0_Error used by PE */
181 #define VECTOR_94 (tIsrFunc)&_int_kernel_isr /* 0x5E - ivINT_CAN0_Tx_Warning used by PE */
182 #define VECTOR_95 (tIsrFunc)&_int_kernel_isr /* 0x5F - ivINT_CAN0_Rx_Warning used by PE */
183 #define VECTOR_96 (tIsrFunc)&_int_kernel_isr /* 0x60 - ivINT_CAN0_Wake_Up used by PE */
184 #define VECTOR_97 (tIsrFunc)&_int_kernel_isr /* 0x61 - ivINT_SDHC used by PE */
185 #define VECTOR_98 (tIsrFunc)&_int_kernel_isr /* 0x62 - ivINT_ENET_1588_Timer used by PE */
186 #define VECTOR_99 (tIsrFunc)&_int_kernel_isr /* 0x63 - ivINT_ENET_Transmit used by PE */
187 #define VECTOR_100 (tIsrFunc)&_int_kernel_isr /* 0x64 - ivINT_ENET_Receive used by PE */
188 #define VECTOR_101 (tIsrFunc)&_int_kernel_isr /* 0x65 - ivINT_ENET_Error used by PE */
189
190 #ifdef __cplusplus
191 }
192 #endif
193
194 /* END Vectors_Config.h */
195
196 #endif /* __Vectors_Config_H */
197
198 /*!
199 ** @}
200 */
201 /*
202 ** ###################################################################
203 **
204 ** This file is a part of Processor Expert static initialization
205 ** library for the Freescale Kinetis series of microcontrollers.
206 **
207 ** ###################################################################
208 */
ISFCore1.h
FXAS21002_1.h
CommChannelConfig1.h
App1.h
ORIENT_1.h
MPL3115_1.h
RLI1.h
Protocol1.h
ISFBusManager1.h
I2C_CH1.h
BMTimer1.h
This TimerUnit component provides a low level API for unified hardware access across various timer de...
Serial_ISF_UART1.h
This component "Serial_LDD" implements an asynchronous serial communication. The component supports d...
MAG3110_1.h
FXLS8471_1.h
MMA865x_1.h
MQX1.h
MQX Lite RTOS Adapter component.
FXOS8700_1.h
UART_CH1.h
SPI_CH1.h
- © Freescale Semiconductor, Inc. 2015. All Rights Reserved.