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fsl_pit_features.h
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1 /*
2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * o Redistributions of source code must retain the above copyright notice, this list
9 * of conditions and the following disclaimer.
10 *
11 * o Redistributions in binary form must reproduce the above copyright notice, this
12 * list of conditions and the following disclaimer in the documentation and/or
13 * other materials provided with the distribution.
14 *
15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30 #if !defined(__FSL_PIT_FEATURES_H__)
31 #define __FSL_PIT_FEATURES_H__
32
33 // NOTE: Cpu type is defined as part of the project configuration.
34
35 #if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
36 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
37 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
38 defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
39 defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
40 defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
41 defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
42 defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \
43 defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
44 defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
45 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn).*/
46 #define FSL_FEATURE_PIT_TIMER_COUNT (4)
47 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H).*/
48 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0)
49 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]).*/
50 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (0)
51 #elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
52 defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \
53 defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FN1M0VDC12) || \
54 defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VMD12) || \
55 defined(CPU_MK64FX512VMD12) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31FN512VLH12) || \
56 defined(CPU_MKV31F512VLL12)
57 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn).*/
58 #define FSL_FEATURE_PIT_TIMER_COUNT (4)
59 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H).*/
60 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0)
61 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]).*/
62 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
63 #elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \
64 defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18)
65 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn).*/
66 #define FSL_FEATURE_PIT_TIMER_COUNT (4)
67 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H).*/
68 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
69 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]).*/
70 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
71 #elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
72 defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
73 defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL25Z32VFM4) || \
74 defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \
75 defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
76 defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL46Z128VLH4) || \
77 defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || \
78 defined(CPU_MKL46Z256VMC4)
79 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn).*/
80 #define FSL_FEATURE_PIT_TIMER_COUNT (2)
81 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H).*/
82 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
83 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]).*/
84 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
85 #else
86 #error "No valid CPU defined!"
87 #endif
88
89 #endif /* __FSL_PIT_FEATURES_H__*/
90 /*******************************************************************************
91 * EOF
92 ******************************************************************************/
93
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- © Freescale Semiconductor, Inc. 2015. All Rights Reserved.