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ci_protocol_mbox.h
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1 /*
2 *
3 * Copyright (c) 2015, Freescale Semiconductor, Inc.
4 *
5 */
6
7 /*!
8 * @file ci_protocol_mbox.h
9 *
10 * @brief Command interpreter header file for the legacy mailbox protocol.
11 *
12 */
13
14
15 #ifndef CI_PROTOCOL_MBOX_H_
16 #define CI_PROTOCOL_MBOX_H_
17
18
19
20
21 //#include <IO_Map.h>
22 #include "isf.h"
23
24
25
26 /*! @brief Define to enable CRC check. When enabled, CRC calculation is performed and CRC bytes
27 * are included in packets sent to the host. Also, CRC check is performed on receiving packets.
28 */
29 //#define MBOX_ENABLE_CRC
30
31
32 #ifdef MBOX_ENABLE_CRC
33 #define MBOX_CRC_BYTE_SIZE (2)
34 #else
35 #define MBOX_CRC_BYTE_SIZE (0)
36 #endif
37
38
39 #define SP_MB0 (0)
40 #define SP_MB1 (1)
41 #define SP_MB2 (2)
42 #define SP_MB3 (3)
43 #define SP_MB4 (4)
44 #define ISF_APP_ID_NULL (0)
45
46
47
48 /*!
49 * @brief Mailbox designation for host command packet for read/write.
50 *
51 */
52
53 // Write command message format. Host requesting to write.
54 #define MB_HOST_APP_ID pciMailboxes[0]
55 #define MB_HOST_CMD pciMailboxes[1]
56 #define MB_HOST_OFFSET pciMailboxes[2]
57 #define MB_HOST_COUNT pciMailboxes[3]
58 #define MB_HOST_CMD_SIZE(x) (GET_EXTENSION_BIT(x) == 0) ? 4 : 5 // Host command is 4 bytes normal mode, 6 is for extension mode, MB0-3
59 #define MB_HOST_OFFSET_EXT (uint16)((pciMailboxes[2] << 8) | pciMailboxes[3])
60 #define MB_HOST_COUNT_EXT pciMailboxes[4]
61 #define MB_HOST_WR_DATA_START (4)
62
63 // Read command message format. Host requesting to read.
64 #define MB_RESP_APP_ID pciMailboxes[0]
65 #define MB_RESP_STATUS_CC pciMailboxes[1]
66 #define MB_RESP_BYTES_XFER pciMailboxes[2]
67 #define MB_RESP_COUNT pciMailboxes[3]
68 #define MB_RESP_INDEX_APP_ID (0)
69 #define MB_RESP_INDEX_STATUS_CC (1)
70 #define MB_RESP_INDEX_BYTES_XFER (2)
71 #define MB_RESP_INDEX_COUNT (3)
72
73 #define MB_APP_RESP_SIZE (4) // App response is 4 bytes, MB0-3
74 #define MB_APP_RESP_DATA_START (4)
75
76 #define CI_STREAMING_MODE (1)
77 #define CI_NON_STREAMING_MODE (0)
78
79
80
81
82
83 /*!
84 * @brief Mailboxes write bit. Bit setting for the 4 byte \n
85 * command packet from host. Bit position has same meaning \n
86 * as the SP_WSTS0 register.
87 */
88 #define CMD_PACKET_BITS (0x0000000f) /// MB3 - MB0
89
90
91 /*!
92 * @brief Mailbox COCO bit position and mask.
93 *
94 */
95 #define COCO_BIT (7) // Bit position (starting at 0)
96 #define COCO_BIT_MASK (1 << COCO_BIT)
97
98 /*!
99 * @brief Extension for length and offset.
100 */
101 #define EXTENSION_LENGTH_BIT (1) // Bit for 1 byte extension for offset and length
102 #define EXTENSION_LENGTH_BIT_BIT_MASK (1 << 7)
103 #define GET_EXTENSION_BIT(x) (((x) & EXTENSION_LENGTH_BIT_BIT_MASK )>> 7)
104
105 /*!
106 * @brief Command byte partition. Command byte contains instruction \n
107 * value in all bits. This\n
108 * command is written by host to MB0.
109 */
110 #define WR_CMD_RSHIFT (0)
111 #define WR_CMD_MASK (0xff) // b[6:0]
112 #define WR_CMD_ID_MASK (0x7f)
113
114
115
116
117 /*! @brief Number of mailboxes available on this system.
118 */
119 #define MAX_NUM_MAILBOXES (32)
120
121 /*! @brief Number of output buffer available on this system.
122 */
123 #define MAX_NUM_OUT_BUFFER (256)
124
125
126 /*!
127 * @brief First mailbox number for data transfer at powerup.\n
128 * Note that the actual first mailbox available for data transfer\n
129 * depends on how the host configures the mailboxes for quick\n
130 * read.
131 */
132 #define FIRST_DATA_MAILBOX_NUM (4) // First 4 mailboxes (0-3) reserved for command packet
133
134 /*!
135 * @brief Maximum number of mailboxes available on this system for \n
136 * data from/to host. Note that not all mailboxes designated for \n
137 * data payload may be available since the host could configure
138 * them for quick read.
139 */
140 #define NUM_DATA_MAILBOXES (MAX_NUM_MAILBOXES-FIRST_DATA_MAILBOX_NUM)
141
142
143 /*!
144 * @brief First mailbox number that can be configured for quick\n
145 * read data. Quick read data can be written to this mailbox\n
146 * mailbox number up 31.
147 */
148 #define FIRST_QR_MAILBOX_NUM (4) // First 4 mailboxes (0-3) reserved for command packet
149
150 /*!
151 * @brief Quick read mask that is applied to mailboxes read by host\n
152 * to mask out mailboxes read by the host but not configured for\n
153 * quick read.
154 */
155 #define QR_MAILBOX_MASK ((uint32)0xffffffff << FIRST_QR_MAILBOX_NUM)
156
157
158 /*!
159 * @brief Maximum number of mailboxes available on this system for \n
160 * quick read. Note that not all mailboxes designated for \n
161 * data payload may be available since the host could configure
162 * them for quick read.
163 */
164 #define NUM_QR_MAILBOXES (MAX_NUM_MAILBOXES-FIRST_QR_MAILBOX_NUM)
165
166
167 #if (FIRST_QR_MAILBOX_NUM < FIRST_DATA_MAILBOX_NUM)
168 ERROR: Quick read starting mailbox cannot be less than first data mailbox!
169 #endif
170
171
172
173
174
175 /*!
176 * @brief This structure holds the quick read configuration for all \n
177 * applicable mailboxes. The first 4 mailboxes are used for the \n
178 * command packet read/write. All other mailboxes can be configured \n
179 * as quick read.
180 *
181 * Note that this structure must be 2 bytes per Eve's command interpreter \n
182 * spec.
183 *
184 * @struct qr_config_t
185 */
186 typedef struct
187 {
188 uint8 appId;
189 uint8 byte_id;
190 } qr_config_t;
191
192
193
194
195 /*!
196 * @brief Command Interpreter Control Register Structure. \n
197 *
198 * reserved1 : Reserved Bits \n
199 * reserved2 : Reserved Bits \n
200 * blockTransferMode : 1 - Streaming mode enabled. 0 - Streaming mode disabled. \n
201 * reserved3 : Reserved Bits
202 *
203 * @struct ci_ctrl_reg_t
204 */
205 typedef union {
206 uint8 reg;
207 struct {
208 uint8 reserved1 :1; // Reserved
209 uint8 reserved2 :1; // Reserved
210 uint8 blockTransferMode :1; // Block Transfer mode
211 uint8 reserved3 :5; // Reserved
212 } Bits;
213 } ci_ctrl_reg_t;
214
215
216 /*!
217 * @brief Command Interpreter Registers Structure. Contains all CI registers. \n
218 *
219 * @struct ci_regs_t
220 */
221 typedef struct
222 {
223 qr_config_t qr_config[NUM_QR_MAILBOXES];
224 ci_ctrl_reg_t ciCtrlReg;
225 } ci_regs_t;
226
227
228 /*! @brief Debug commands */
229 #define CI_CMD_DEBUG_LOOPBACK (120) // Must be greater than CI_CMD_LAST
230
231
232 extern isf_status_t ci_mbox_init(uint8 aprotocolID, void *apInitData);
233 extern isf_status_t ci_protocol_CB_mbox(uint32 anumBytes, uint8 *apSrc, uint32 *apnumDestBytes, uint8 *apDest);
234
235
236 #define ci_get_wr_appid() ((uint8)MB_HOST_APP_ID)
237 #define ci_get_wr_appid() ((uint8)MB_HOST_APP_ID)
238 #define ci_get_wr_cmd() ((uint8)((MB_HOST_CMD & WR_CMD_MASK) >> WR_CMD_RSHIFT))
239 #define ci_get_wr_cmdId() ((uint8)((MB_HOST_CMD & WR_CMD_ID_MASK) >> WR_CMD_RSHIFT))
240 #define ci_get_wr_offset(x) (GET_EXTENSION_BIT(x) == 0)? (uint16)(MB_HOST_OFFSET) : (uint16)(MB_HOST_OFFSET_EXT)
241 #define ci_get_wr_cnt(x) (GET_EXTENSION_BIT(x) == 0)? (uint16)(MB_HOST_COUNT) : (uint16)(MB_HOST_COUNT_EXT)
242 #define ci_get_first_mailbox(x) (GET_EXTENSION_BIT(x) == 0)? 4 : 5
243
244
245 // Initialize quick read configuration. Use a unique loop counter name so that
246 // it does not conflict with variables already in the function.
247 #define qr_config_clear() { \
248 int iii = MAX_NUM_MAILBOXES-1; \
249 do \
250 { \
251 ciRegisters.qr_config[iii].appId = 0; \
252 ciRegisters.qr_config[iii].byte_id = 0; \
253 } while(--iii >= 0); \
254 }
255
256 // Note that the msb of the CRC value comes first. The CRC value is placed at the
257 // end of the buffer.
258 #define ci_insert_crc(insert_offset, crc16_value, pBuf) { \
259 pBuf[insert_offset + 0] = (uint8)((uint16)(crc16_value & 0xff00) >> 8);\
260 pBuf[insert_offset + 1] = (uint8)(crc16_value & 0xff);\
261 }
262
263
264
265
266
267
268
269 #endif // CI_PROTOCOL_MBOX_H_
uint8
unsigned char uint8
Definition: isf_types.h:76
ci_ctrl_reg_t::reg
uint8 reg
Definition: ci_protocol_mbox.h:206
ci_regs_t
Command Interpreter Registers Structure. Contains all CI registers. .
Definition: ci_protocol_mbox.h:221
ci_regs_t::ciCtrlReg
ci_ctrl_reg_t ciCtrlReg
Definition: ci_protocol_mbox.h:224
NUM_QR_MAILBOXES
#define NUM_QR_MAILBOXES
Maximum number of mailboxes available on this system for quick read. Note that not all mailboxes de...
Definition: ci_protocol_mbox.h:164
qr_config_t::byte_id
uint8 byte_id
Definition: ci_protocol_mbox.h:189
qr_config_t
This structure holds the quick read configuration for all applicable mailboxes. The first 4 mailbox...
Definition: ci_protocol_mbox.h:186
ci_ctrl_reg_t
Command Interpreter Control Register Structure. .
Definition: ci_protocol_mbox.h:205
qr_config_t::appId
uint8 appId
Definition: ci_protocol_mbox.h:188
ci_mbox_init
isf_status_t ci_mbox_init(uint8 aprotocolID, void *apInitData)
Definition: ci_protocol_mbox.c:528
isf.h
Main ISF header file. Contains code common to all ISF components.
isf_status_t
int32 isf_status_t
ISF return status type.
Definition: isf.h:76
uint32
unsigned long int uint32
Definition: isf_types.h:78
ci_protocol_CB_mbox
isf_status_t ci_protocol_CB_mbox(uint32 anumBytes, uint8 *apSrc, uint32 *apnumDestBytes, uint8 *apDest)
Definition: ci_protocol_mbox.c:795
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