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mma865x.h
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1 /**
2 * @file mma865x.h
3 * @brief The \b mma865x.h contains the MMA865x Accelerometer register definitions, access macros, and
4 * device access functions.
5 *
6 * @copyright Copyright (c) 2015, Freescale Semiconductor, Inc.
7 */
8
9 #ifndef MMA865x_H_
10 #define MMA865x_H_
11
12 /**
13 * @brief The MMA865x types
14 */
15
16 /**
17 **
18 ** @brief The MMA865x Sensor Internal Register Map.
19 */
20 enum {
21 MMA865x_STATUS_00 = 0, // 0x00 - MMA865x only
22 MMA865x_OUT_X_MSB, // 0x01 - data registers
23 MMA865x_OUT_X_LSB, // 0x02 - data registers
24 MMA865x_OUT_Y_MSB, // 0x03 - data registers
25 MMA865x_OUT_Y_lSB, // 0x04 - data registers
26 MMA865x_OUT_Z_MSB, // 0x05 - data registers
27 MMA865x_OUT_Z_LSB, // 0x06 - data registers
28 MMA865x_RSVD_0, // 0x07 - Reserved
29 MMA865x_RSVD_1, // 0x08 - Reserved
30 MMA865x_F_SETUP, // 0x09 - MMA865x only,F_SETUP FIFO Setup register
31 MMA865x_TRIG_CFG, // 0x0A - MMA865x only,TRIG_CFG Trigger Configuration register
32 MMA865x_SYSMOD, // 0x0B - SYSMOD System Mode register
33 MMA865x_INT_SOURCE, // 0x0C - INT_SOURCE System Interrupt Status register
34 MMA865x_WHO_AM_I, // 0x0D - WHO_AM_I Device ID register
35 MMA865x_XYZ_DATA_CFG, // 0x0E - XYZ_DATA_CFG register
36 MMA865x_HP_FILTER_CUTOFF, // 0x0F - MMA865x only
37 MMA865x_PL_STATUS, // 0x10 - PL_STATUS Portrait/Landscape Status register
38 MMA865x_PL_CFG, // 0x11 - Portrait/Landscape Configuration register
39 MMA865x_PL_COUNT, // 0x12 - Portrait/Landscape Debounce register
40 MMA865x_PL_BF_ZCOMP, // 0x13 - PL_BF_ZCOMP Back/Front and Z Compensation register
41 MMA865x_PL_P_L_THS, // 0x14 - P_L_THS_REG Portrait/Landscape Threshold and Hysteresis register
42 MMA865x_FF_MT_CFG, // 0x15 - FF_MT_CFG Freefall/Motion Configuration register
43 MMA865x_FF_MT_SRC, // 0x16 - FF_MT_SRC Freefall/Motion Source register
44 MMA865x_FF_MT_THS, // 0x17 - FF_MT_THS Freefall and Motion Threshold register
45 MMA865x_FF_MT_COUNT, // 0x18 - FF_MT_COUNT Debounce register
46 MMA865x_RSVD_2, // 0x19 - Reserved
47 MMA865x_RSVD_3, // 0x1A - Reserved
48 MMA865x_RSVD_4, // 0x1B - Reserved
49 MMA865x_RSVD_5, // 0x1C - Reserved
50 MMA865x_TRANSIENT_CFG, // 0x1D - MMA865x only,Transient_CFG register
51 MMA865x_TRANSIENT_SRC, // 0x1E - MMA865x only,TRANSIENT_SRC register
52 MMA865x_TRANSIENT_THS, // 0x1F - MMA865x only,TRANSIENT_THS register
53 MMA865x_TRANSIENT_COUNT, // 0x20 - MMA865x only,TRANSIENT_COUNT register
54 MMA865x_PULSE_CFG, // 0x21 - MMA865x only,PULSE_CFG Pulse Configuration register
55 MMA865x_PULSE_SRC, // 0x22 - MMA865x only,PULSE_SRC Pulse Source register
56 MMA865x_PULSE_THSX, // 0x23 - MMA865x only,PULSE_THSX, Y, Z Pulse Threshold for X, Y and Z registers
57 MMA865x_PULSE_THSY, // 0x24 - MMA865x only,PULSE_THSX, Y, Z Pulse Threshold for X, Y and Z registers
58 MMA865x_PULSE_THSZ, // 0x25 - MMA865x only,PULSE_THSX, Y, Z Pulse Threshold for X, Y and Z registers
59 MMA865x_PULSE_TMLT, // 0x26 - MMA865x only,PULSE_TMLT Pulse Time Window 1 register
60 MMA865x_PULSE_LTCY, // 0x27 - MMA865x only,PULSE_LTCY Pulse Latency Timer register
61 MMA865x_PULSE_WIND, // 0x28 - MMA865x only,PULSE_WIND register (Read/Write)
62 MMA865x_ASLP_COUNT, // 0x29 - ASLP_COUNT, Auto-WAKE/SLEEP Detection register (Read/Write)
63 MMA865x_CTRL_REG1, // 0x2A - CTRL_REG1 System Control 1 register
64 MMA865x_CTRL_REG2, // 0x2B - CTRL_REG2 System Control 1 register
65 MMA865x_CTRL_REG3, // 0x2C - CTRL_REG3 Interrupt Control register
66 MMA865x_CTRL_REG4, // 0x2D - CTRL_REG4 Interrupt Enable register (Read/Write)
67 MMA865x_CTRL_REG5, // 0x2E - CTRL_REG5 Interrupt Configuration register (Read/Write)
68 MMA865x_OFF_X, // 0x2F - OFF_X Offset Correction X register
69 MMA865x_OFF_Y, // 0x30 - OFF_Y Offset Correction Y register
70 MMA865x_OFF_Z // 0x31 - OFF_Z Offset Correction Z register
71 };
72
73 #define MMA865x_WHOAMI_VALUE_8652 (0x4A)
74 #define MMA865x_WHOAMI_VALUE_8653 (0x5A)
75 /*
76 * General purpose macros to set/get a specific bit field within a register.
77 * The macro assumes that the root identifier for the field is a consistent character string (e.g., "BIT_FIELD").
78 * The bit field mask is the character string followed by "_MASK" (e.g., BIT_FIELD_MASK).
79 * The bit field shift is the character string followed by "_SHIFT" (e.g., BIT_FIELD_SHIFT).
80 */
81 #define MMA865x_SET_FIELD(name,val) (((val)<<MMA865x_##name##_SHIFT)&(MMA865x_##name##_MASK))
82 #define MMA865x_GET_FIELD(name,val) ((val&MMA865x_##name##_MASK)>>MMA865x_##name##_SHIFT)
83
84 /*
85 ** STATUS Register
86 */
87 #define MMA865x_ZYXOW_MASK 0x80
88 #define MMA865x_ZYXOW_SHIFT 7
89 #define MMA865x_ZOW_MASK 0x40
90 #define MMA865x_YOW_MASK 0x20
91 #define MMA865x_XOW_MASK 0x10
92 #define MMA865x_ZYXDR_MASK 0x08
93 #define MMA865x_ZYXDR_SHIFT 3
94 #define MMA865x_ZDR_MASK 0x04
95 #define MMA865x_YDR_MASK 0x02
96 #define MMA865x_XDR_MASK 0x01
97
98
99 /*
100 * Output Data Registers
101 */
102
103 /*
104 ** F_STATUS FIFO Status Register
105 ** MMA865x only - when F_MODE != 0
106 */
107 #define MMA865x_F_OVF_MASK 0x80
108 #define MMA865x_F_WMRK_FLAG_MASK 0x40
109 #define MMA865x_F_CNT5_MASK 0x20
110 #define MMA865x_F_CNT4_MASK 0x10
111 #define MMA865x_F_CNT3_MASK 0x08
112 #define MMA865x_F_CNT2_MASK 0x04
113 #define MMA865x_F_CNT1_MASK 0x02
114 #define MMA865x_F_CNT0_MASK 0x01
115 #define MMA865x_F_CNT_MASK 0x3F
116
117 /*
118 ** F_SETUP FIFO Setup Register
119 ** MMA865x only
120 */
121 #define MMA865x_F_MODE1_MASK 0x80
122 #define MMA865x_F_MODE0_MASK 0x40
123 #define MMA865x_F_WMRK5_MASK 0x20
124 #define MMA865x_F_WMRK4_MASK 0x10
125 #define MMA865x_F_WMRK3_MASK 0x08
126 #define MMA865x_F_WMRK2_MASK 0x04
127 #define MMA865x_F_WMRK1_MASK 0x02
128 #define MMA865x_F_WMRK0_MASK 0x01
129 #define MMA865x_F_MODE_MASK 0xC0
130 #define MMA865x_F_WMRK_MASK 0x3F
131 //
132 #define MMA865x_F_MODE_DISABLED 0x00
133 #define MMA865x_F_MODE_CIRCULAR (MMA865x_F_MODE0_MASK)
134 #define MMA865x_F_MODE_FILL (MMA865x_F_MODE1_MASK)
135 #define MMA865x_F_MODE_TRIGGER (MMA865x_F_MODE1_MASK+MMA865x_F_MODE0_MASK)
136
137 /*
138 ** TRIG_CFG FIFO Trigger Configuration Register
139 ** MMA865x only
140 */
141 #define MMA865x_TRIG_TRANS_MASK 0x20
142 #define MMA865x_TRIG_LNDPRT_MASK 0x10
143 #define MMA865x_TRIG_PULSE_MASK 0x08
144 #define MMA865x_TRIG_FF_MT_MASK 0x04
145
146 /*
147 ** SYSMOD System Mode Register
148 ** MMA865x only
149 */
150 #define MMA865x_FGERR_MASK 0x80
151 #define MMA865x_FGT_4_MASK 0x40
152 #define MMA865x_FGT_3_MASK 0x20
153 #define MMA865x_FGT_2_MASK 0x10
154 #define MMA865x_FGT_1_MASK 0x08
155 #define MMA865x_FGT_0_MASK 0x04
156 #define MMA865x_FGT_MASK 0x7C
157 #define MMA865x_SYSMOD_MASK 0x03
158 //
159 #define MMA865x_SYSMOD_STANDBY 0x00
160 #define MMA865x_SYSMOD_WAKE 0x01
161 #define MMA865x_SYSMOD_SLEEP 0x02
162
163 /*
164 ** INT_SOURCE System Interrupt Status Register
165 */
166 #define MMA865x_SRC_ASLP_MASK 0x80
167 #define MMA865x_SRC_FIFO_MASK 0x40 // MMA865x only
168 #define MMA865x_SRC_TRANS_MASK 0x20
169 #define MMA865x_SRC_LNDPRT_MASK 0x10
170 #define MMA865x_SRC_PULSE_MASK 0x08
171 #define MMA865x_SRC_FF_MT_MASK 0x04
172 #define MMA865x_SRC_DRDY_MASK 0x01
173
174 /*
175 ** WHO_AM_I Device ID Register
176 */
177 #define MMA865x_MMA865xQ 0x0D
178
179
180 /*
181 ** XYZ_DATA_CFG Sensor Data Configuration Register
182 */
183 #define MMA865x_HPF_OUT_MASK 0x10 // MMA865x only
184 #define MMA865x_HPF_OUT_SHIFT 4
185 #define MMA865x_FS1_MASK 0x02
186 #define MMA865x_FS0_MASK 0x01
187 #define MMA865x_FS_MASK 0x03
188 #define MMA865x_FS_SHIFT 0
189 //
190 #define MMA865x_FULL_SCALE_2G 0x00
191 #define MMA865x_FULL_SCALE_4G (MMA865x_FS0_MASK)
192 #define MMA865x_FULL_SCALE_8G (MMA865x_FS1_MASK)
193
194 /*
195 ** HP_FILTER_CUTOFF High Pass Filter Register
196 ** MMA865x only
197 */
198 #define MMA865x_PULSE_HPF_BYP_MASK 0x20
199 #define MMA865x_PULSE_HPF_BYP_SHIFT 5
200 #define MMA865x_PULSE_LPF_EN_MASK 0x10
201 #define MMA865x_PULSE_LPF_EN_SHIFT 4
202 #define MMA865x_SEL1_MASK 0x02
203 #define MMA865x_SEL0_MASK 0x01
204 #define MMA865x_SEL_MASK 0x03
205 #define MMA865x_SEL_SHIFT 0
206
207 /*
208 ** PL_STATUS Portrait/Landscape Status Register
209 */
210 #define MMA865x_NEWLP_MASK 0x80
211 #define MMA865x_LO_MASK 0x40
212 #define MMA865x_LO_SHIFT 6
213 #define MMA865x_LAPO1_MASK 0x04
214 #define MMA865x_LAPO0_MASK 0x02
215 #define MMA865x_LAPO_MASK 0x06
216 #define MMA865x_LAPO_SHIFT 1
217 #define MMA865x_BAFRO_MASK 0x01
218 #define MMA865x_BAFRO_SHIFT 0
219 /*
220 ** PL_CFG Portrait/Landscape Configuration Register
221 */
222 #define MMA865x_DBCNTM_MASK 0x80
223 #define MMA865x_DBCNTM_SHIFT 7
224 #define MMA865x_PL_EN_MASK 0x40
225 #define MMA865x_PL_EN_SHIFT 6
226
227 /*
228 ** PL_BF_ZCOMP Back/Front and Z Compensation Register
229 */
230 #define MMA865x_BKFR1_MASK 0x80
231 #define MMA865x_BKFR0_MASK 0x40
232 #define MMA865x_ZLOCK2_MASK 0x04
233 #define MMA865x_ZLOCK1_MASK 0x02
234 #define MMA865x_ZLOCK0_MASK 0x01
235 #define MMA865x_BKFR_MASK 0xC0
236 #define MMA865x_BKFR_SHIFT 6
237 #define MMA865x_ZLOCK_MASK 0x07
238 #define MMA865x_ZLOCK_SHIFT 0
239
240 /*
241 ** PL_P_L_THS Portrait to Landscape Threshold Register
242 */
243 #define MMA865x_P_L_THS4_MASK 0x80
244 #define MMA865x_P_L_THS3_MASK 0x40
245 #define MMA865x_P_L_THS2_MASK 0x20
246 #define MMA865x_P_L_THS1_MASK 0x10
247 #define MMA865x_P_L_THS0_MASK 0x08
248 #define MMA865x_HYS2_MASK 0x04
249 #define MMA865x_HYS1_MASK 0x02
250 #define MMA865x_HYS0_MASK 0x01
251 #define MMA865x_P_L_THS_MASK 0xF8
252 #define MMA865x_P_L_THS_SHIFT 3
253 #define MMA865x_HYS_MASK 0x07
254 #define MMA865x_HYS_SHIFT 0
255
256 /*
257 ** FF_MT_CFG Freefall and Motion Configuration Register
258 */
259 #define MMA865x_ELE_MASK 0x80
260 #define MMA865x_ELE_SHIFT 7
261 #define MMA865x_OAE_MASK 0x40
262 #define MMA865x_OAE_SHIFT 6
263 #define MMA865x_ZEFE_MASK 0x20
264 #define MMA865x_ZEFE_SHIFT 5
265 #define MMA865x_YEFE_MASK 0x10
266 #define MMA865x_YEFE_SHIFT 4
267 #define MMA865x_XEFE_MASK 0x08
268 #define MMA865x_XEFE_SHIFT 3
269 /*
270 ** FF_MT_SRC Freefall and Motion Source Registers
271 */
272 #define MMA865x_EA_MASK 0x80
273 #define MMA865x_ZHE_MASK 0x20
274 #define MMA865x_ZHP_MASK 0x10
275 #define MMA865x_YHE_MASK 0x08
276 #define MMA865x_YHP_MASK 0x04
277 #define MMA865x_XHE_MASK 0x02
278 #define MMA865x_XHP_MASK 0x01
279 /*
280 ** FF_MT_THS Freefall and Motion Threshold Registers
281 ** TRANSIENT_THS Transient Threshold Register
282 */
283 #define MMA865x_DBCNTM_MASK 0x80
284 #define MMA865x_DBCNTM_SHIFT 7
285 #define MMA865x_THS6_MASK 0x40
286 #define MMA865x_THS5_MASK 0x20
287 #define MMA865x_THS4_MASK 0x10
288 #define MMA865x_THS3_MASK 0x08
289 #define MMA865x_THS2_MASK 0x04
290 #define MMA865x_TXS1_MASK 0x02
291 #define MMA865x_THS0_MASK 0x01
292 #define MMA865x_THS_MASK 0x7F
293 #define MMA865x_THS_SHIFT 0
294
295 /*
296 ** TRANSIENT_CFG Transient Configuration Register
297 ** MMA865x only
298 */
299 #define MMA865x_TELE_MASK 0x10
300 #define MMA865x_TELE_SHIFT 4
301 #define MMA865x_ZTEFE_MASK 0x08
302 #define MMA865x_ZTEFE_SHIFT 3
303 #define MMA865x_YTEFE_MASK 0x04
304 #define MMA865x_YTEFE_SHIFT 2
305 #define MMA865x_XTEFE_MASK 0x02
306 #define MMA865x_XTEFE_SHIFT 1
307 #define MMA865x_HPF_BYP_MASK 0x01
308 #define MMA865x_HPF_BYP_SHIFT 0
309
310 /*
311 ** TRANSIENT_SRC Transient Source Register
312 ** MMA865x only
313 */
314 #define MMA865x_TEA_MASK 0x40
315 #define MMA865x_ZTRANSE_MASK 0x20
316 #define MMA865x_Z_TRANS_POL_MASK 0x10
317 #define MMA865x_YTRANSE_MASK 0x08
318 #define MMA865x_Y_TRANS_POL_MASK 0x04
319 #define MMA865x_XTRANSE_MASK 0x02
320 #define MMA865x_X_TRANS_POL_MASK 0x01
321
322 /*
323 ** PULSE_CFG Pulse Configuration Register
324 ** MMA865x only
325 */
326 #define MMA865x_DPA_MASK 0x80
327 #define MMA865x_DPA_SHIFT 7
328 #define MMA865x_PELE_MASK 0x40
329 #define MMA865x_PELE_SHIFT 6
330 #define MMA865x_ZDPEFE_MASK 0x20
331 #define MMA865x_ZDPEFE_SHIFT 5
332 #define MMA865x_ZSPEFE_MASK 0x10
333 #define MMA865x_ZSPEFE_SHIFT 4
334 #define MMA865x_YDPEFE_MASK 0x08
335 #define MMA865x_YDPEFE_SHIFT 3
336 #define MMA865x_YSPEFE_MASK 0x04
337 #define MMA865x_YSPEFE_SHIFT 2
338 #define MMA865x_XDPEFE_MASK 0x02
339 #define MMA865x_XDPEFE_SHIFT 1
340 #define MMA865x_XSPEFE_MASK 0x01
341 #define MMA865x_XSPEFE_SHIFT 0
342 /*
343 ** PULSE_SRC Pulse Source Register
344 ** MMA865x only
345 */
346 #define MMA865x_PEA_MASK 0x80
347 #define MMA865x_AXZ_MASK 0x40
348 #define MMA865x_AXY_MASK 0x20
349 #define MMA865x_AXX_MASK 0x10
350 #define MMA865x_DPE_MASK 0x08
351 #define MMA865x_POLZ_MASK 0x04
352 #define MMA865x_POLY_MASK 0x02
353 #define MMA865x_POLX_MASK 0x01
354 /*
355 ** PULSE_THS XYZ Pulse Threshold Registers
356 ** MMA865x only
357 */
358 #define MMA865x_PTHS_MASK 0x7F
359 #define MMA865x_PTHS_SHIFT 0
360
361 /*
362 ** CTRL_REG1 System Control 1 Register
363 */
364 #define MMA865x_ASLP_RATE1_MASK 0x80
365 #define MMA865x_ASLP_RATE0_MASK 0x40
366 #define MMA865x_DR2_MASK 0x20
367 #define MMA865x_DR1_MASK 0x10
368 #define MMA865x_DR0_MASK 0x08
369 #define MMA865x_LNOISE_MASK 0x04
370 #define MMA865x_FREAD_MASK 0x02
371 #define MMA865x_FREAD_SHIFT 1
372 #define MMA865x_ACTIVE_MASK 0x01
373 #define MMA865x_ASLP_RATE_MASK 0xC0
374 #define MMA865x_ASLP_RATE_SHIFT 6
375 #define MMA865x_DR_MASK 0x38
376 #define MMA865x_DR_SHIFT 3
377 //
378 #define MMA865x_ASLP_RATE_20MS 0x00
379 #define MMA865x_ASLP_RATE_80MS (MMA865x_ASLP_RATE0_MASK)
380 #define MMA865x_ASLP_RATE_160MS (MMA865x_ASLP_RATE1_MASK)
381 #define MMA865x_ASLP_RATE_640MS (MMA865x_ASLP_RATE1_MASK+MMA865x_ASLP_RATE0_MASK)
382 //
383 #define MMA865x_ASLP_RATE_50HZ (MMA865x_ASLP_RATE_20MS)
384 #define MMA865x_ASLP_RATE_12_5HZ (MMA865x_ASLP_RATE_80MS)
385 #define MMA865x_ASLP_RATE_6_25HZ (MMA865x_ASLP_RATE_160MS)
386 #define MMA865x_ASLP_RATE_1_56HZ (MMA865x_ASLP_RATE_640MS)
387 //
388 #define MMA865x_DATA_RATE_1250US 0x00
389 #define MMA865x_DATA_RATE_2500US (MMA865x_DR0_MASK)
390 #define MMA865x_DATA_RATE_5MS (MMA865x_DR1_MASK)
391 #define MMA865x_DATA_RATE_10MS (MMA865x_DR1_MASK+MMA865x_DR0_MASK)
392 #define MMA865x_DATA_RATE_20MS (MMA865x_DR2_MASK)
393 #define MMA865x_DATA_RATE_80MS (MMA865x_DR2_MASK+MMA865x_DR0_MASK)
394 #define MMA865x_DATA_RATE_160MS (MMA865x_DR2_MASK+MMA865x_DR1_MASK)
395 #define MMA865x_DATA_RATE_640MS (MMA865x_DR2_MASK+MMA865x_DR1_MASK+MMA865x_DR0_MASK)
396 //
397 #define MMA865x_DATA_RATE_800HZ (MMA865x_DATA_RATE_1250US)
398 #define MMA865x_DATA_RATE_400HZ (MMA865x_DATA_RATE_2500US)
399 #define MMA865x_DATA_RATE_200HZ (MMA865x_DATA_RATE_5MS)
400 #define MMA865x_DATA_RATE_100HZ (MMA865x_DATA_RATE_10MS)
401 #define MMA865x_DATA_RATE_50HZ (MMA865x_DATA_RATE_20MS)
402 #define MMA865x_DATA_RATE_12_5HZ (MMA865x_DATA_RATE_80MS)
403 #define MMA865x_DATA_RATE_6_25HZ (MMA865x_DATA_RATE_160MS)
404 #define MMA865x_DATA_RATE_1_56HZ (MMA865x_DATA_RATE_640MS)
405 //
406 #define MMA865x_ACTIVE (MMA865x_ACTIVE_MASK)
407 #define MMA865x_STANDBY 0x00
408
409 /*
410 ** CTRL_REG2 System Control 2 Register
411 */
412 #define MMA865x_ST_MASK 0x80
413 #define MMA865x_ST_SHIFT 7
414 #define MMA865x_RST_MASK 0x40
415 #define MMA865x_RST_SHIFT 6
416 #define MMA865x_SMODS1_MASK 0x10
417 #define MMA865x_SMODS0_MASK 0x08
418 #define MMA865x_SLPE_MASK 0x04
419 #define MMA865x_SLPE_SHIFT 2
420 #define MMA865x_MODS1_MASK 0x02
421 #define MMA865x_MODS0_MASK 0x01
422 #define MMA865x_SMODS_MASK 0x18
423 #define MMA865x_SMODS_SHIFT 3
424 #define MMA865x_MODS_MASK 0x03
425 #define MMA865x_MODS_SHIFT 0
426 //
427 #define MMA865x_SMOD_NORMAL 0x00
428 #define MMA865x_SMOD_LOW_NOISE (MMA865x_SMODS0_MASK)
429 #define MMA865x_SMOD_HIGH_RES (MMA865x_SMODS1_MASK)
430 #define MMA865x_SMOD_LOW_POWER (MMA865x_SMODS1_MASK+MMA865x_SMODS0_MASK)
431 //
432 #define MMA865x_MOD_NORMAL 0x00
433 #define MMA865x_MOD_LOW_NOISE (MMA865x_MODS0_MASK)
434 #define MMA865x_MOD_HIGH_RES (MMA865x_MODS1_MASK)
435 #define MMA865x_MOD_LOW_POWER (MMA865x_MODS1_MASK+MMA865x_MODS0_MASK)
436
437 /*
438 ** CTRL_REG3 Interrupt Control Register
439 */
440 #define MMA865x_FIFO_GATE_MASK 0x80 // MMA865x only
441 #define MMA865x_FIFO_GATE_SHIFT 7
442 #define MMA865x_WAKE_TRANS_MASK 0x40 // MMA865x only
443 #define MMA865x_WAKE_TRANS_SHIFT 6
444 #define MMA865x_WAKE_LNDPRT_MASK 0x20
445 #define MMA865x_WAKE_LNDPRT_SHIFT 5
446 #define MMA865x_WAKE_PULSE_MASK 0x10 // MMA865x only
447 #define MMA865x_WAKE_PULSE_SHIFT 4
448 #define MMA865x_WAKE_FF_MT_MASK 0x08
449 #define MMA865x_WAKE_FF_MT_SHIFT 3
450 #define MMA865x_IPOL_MASK 0x02
451 #define MMA865x_IPOL_SHIFT 1
452 #define MMA865x_PP_OD_MASK 0x01
453 #define MMA865x_PP_OD_SHIFT 0
454 /*
455 ** CTRL_REG4 Interrupt Enable Register
456 */
457 #define MMA865x_INT_EN_ASLP_MASK 0x80
458 #define MMA865x_INT_EN_ASLP_SHIFT 7
459 #define MMA865x_INT_EN_FIFO_MASK 0x40 // MMA865x only
460 #define MMA865x_INT_EN_FIFO_SHIFT 6
461 #define MMA865x_INT_EN_TRANS_MASK 0x20 // MMA865x only
462 #define MMA865x_INT_EN_TRANS_SHIFT 5
463 #define MMA865x_INT_EN_LNDPRT_MASK 0x10
464 #define MMA865x_INT_EN_LNDPRT_SHIFT 4
465 #define MMA865x_INT_EN_PULSE_MASK 0x08 // MMA865x only
466 #define MMA865x_INT_EN_PULSE_SHIFT 3
467 #define MMA865x_INT_EN_FF_MT_MASK 0x04
468 #define MMA865x_INT_EN_FF_MT_SHIFT 2
469 #define MMA865x_INT_EN_DRDY_MASK 0x01
470 #define MMA865x_INT_EN_DRDY_SHIFT 0
471
472 /*
473 ** CTRL_REG5 Interrupt Configuration Register
474 */
475 #define MMA865x_INT_CFG_ASLP_MASK 0x80
476 #define MMA865x_INT_CFG_ASLP_SHIFT 7
477 #define MMA865x_INT_CFG_FIFO_MASK 0x40 // MMA865x only
478 #define MMA865x_INT_CFG_FIFO_SHIFT 6
479 #define MMA865x_INT_CFG_TRANS_MASK 0x20 // MMA865x only
480 #define MMA865x_INT_CFG_TRANS_SHIFT 5
481 #define MMA865x_INT_CFG_LNDPRT_MASK 0x10
482 #define MMA865x_INT_CFG_LNDPRT_SHIFT 4
483 #define MMA865x_INT_CFG_PULSE_MASK 0x08 // MMA865x only
484 #define MMA865x_INT_CFG_PULSE_SHIFT 3
485 #define MMA865x_INT_CFG_FF_MT_MASK 0x04
486 #define MMA865x_INT_CFG_FF_MT_SHIFT 2
487 #define MMA865x_INT_CFG_DRDY_MASK 0x01
488 #define MMA865x_INT_CFG_DRDY_SHIFT 0
489
490 // Define the output enable flag masks
491 #define MMA865x_PL_OUTPUT_EN 0x01
492 #define MMA865x_FFMT_OUTPUT_EN 0x02
493 #define MMA865x_TRANS_OUTPUT_EN 0x04
494 #define MMA865x_PULSE_OUTPUT_EN 0x08
495
496
497 /*
498 * Public Types
499 */
500
501
502 // Define the MMA865X functional interface status return type.
503 enum
504 {
505 MMA865x_SUCCESS,
506 MMA865x_DATA_OVERWRITE,
507 MMA865x_ERROR
508 };
509
510 typedef struct
511 {
512 uint8 regAddr;
513 uint8 regValue;
514 } mma865x_Sensor_Specific_Reg_t;
515
516 typedef struct
517 {
518 uint8 accelFullScaleRange;
519 uint32 regCount;
520 mma865x_Sensor_Specific_Reg_t regPairs[];
521 } mma865x_Sensor_Specific_Settings_t;
522
523 #endif /* MMA865x_H_ */
MMA865x_WHO_AM_I
Definition: mma865x.h:34
MMA865x_XYZ_DATA_CFG
Definition: mma865x.h:35
uint8
unsigned char uint8
Definition: isf_types.h:76
MMA865x_OUT_X_LSB
Definition: mma865x.h:23
MMA865x_OFF_Y
Definition: mma865x.h:69
mma865x_Sensor_Specific_Settings_t::accelFullScaleRange
uint8 accelFullScaleRange
Definition: mma865x.h:518
MMA865x_CTRL_REG4
Definition: mma865x.h:66
MMA865x_CTRL_REG1
Definition: mma865x.h:63
MMA865x_PULSE_SRC
Definition: mma865x.h:55
MMA865x_TRANSIENT_SRC
Definition: mma865x.h:51
MMA865x_FF_MT_CFG
Definition: mma865x.h:42
MMA865x_OUT_Y_MSB
Definition: mma865x.h:24
MMA865x_OUT_Z_LSB
Definition: mma865x.h:27
MMA865x_TRANSIENT_COUNT
Definition: mma865x.h:53
MMA865x_ERROR
Definition: mma865x.h:507
mma865x_Sensor_Specific_Reg_t::regAddr
uint8 regAddr
Definition: mma865x.h:512
MMA865x_TRIG_CFG
Definition: mma865x.h:31
mma865x_Sensor_Specific_Reg_t
Definition: mma865x.h:510
MMA865x_TRANSIENT_THS
Definition: mma865x.h:52
MMA865x_OUT_X_MSB
Definition: mma865x.h:22
MMA865x_RSVD_1
Definition: mma865x.h:29
MMA865x_RSVD_3
Definition: mma865x.h:47
MMA865x_PULSE_WIND
Definition: mma865x.h:61
MMA865x_PULSE_TMLT
Definition: mma865x.h:59
MMA865x_PULSE_THSZ
Definition: mma865x.h:58
MMA865x_RSVD_2
Definition: mma865x.h:46
MMA865x_PULSE_CFG
Definition: mma865x.h:54
MMA865x_OFF_X
Definition: mma865x.h:68
MMA865x_CTRL_REG2
Definition: mma865x.h:64
MMA865x_PL_STATUS
Definition: mma865x.h:37
mma865x_Sensor_Specific_Settings_t
Definition: mma865x.h:516
MMA865x_F_SETUP
Definition: mma865x.h:30
MMA865x_OFF_Z
Definition: mma865x.h:70
MMA865x_OUT_Y_lSB
Definition: mma865x.h:25
MMA865x_INT_SOURCE
Definition: mma865x.h:33
MMA865x_HP_FILTER_CUTOFF
Definition: mma865x.h:36
MMA865x_ASLP_COUNT
Definition: mma865x.h:62
MMA865x_FF_MT_THS
Definition: mma865x.h:44
MMA865x_DATA_OVERWRITE
Definition: mma865x.h:506
MMA865x_TRANSIENT_CFG
Definition: mma865x.h:50
MMA865x_OUT_Z_MSB
Definition: mma865x.h:26
MMA865x_RSVD_4
Definition: mma865x.h:48
MMA865x_PL_COUNT
Definition: mma865x.h:39
MMA865x_SYSMOD
Definition: mma865x.h:32
MMA865x_RSVD_0
Definition: mma865x.h:28
MMA865x_SUCCESS
Definition: mma865x.h:505
MMA865x_PULSE_THSX
Definition: mma865x.h:56
MMA865x_FF_MT_SRC
Definition: mma865x.h:43
MMA865x_PL_BF_ZCOMP
Definition: mma865x.h:40
MMA865x_PULSE_LTCY
Definition: mma865x.h:60
MMA865x_PL_CFG
Definition: mma865x.h:38
MMA865x_PULSE_THSY
Definition: mma865x.h:57
MMA865x_RSVD_5
Definition: mma865x.h:49
MMA865x_STATUS_00
Definition: mma865x.h:21
MMA865x_FF_MT_COUNT
Definition: mma865x.h:45
uint32
unsigned long int uint32
Definition: isf_types.h:78
MMA865x_CTRL_REG3
Definition: mma865x.h:65
mma865x_Sensor_Specific_Settings_t::regCount
uint32 regCount
Definition: mma865x.h:519
mma865x_Sensor_Specific_Reg_t::regValue
uint8 regValue
Definition: mma865x.h:513
MMA865x_CTRL_REG5
Definition: mma865x.h:67
MMA865x_PL_P_L_THS
Definition: mma865x.h:41
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