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clockMan1.c
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1 /* ###################################################################
2 ** This component module is generated by Processor Expert. Do not modify it.
3 ** Filename : clockMan1.c
4 ** Project : ISF2P2_K64F_MQX_PROJ
5 ** Processor : MK64FN1M0VLL12
6 ** Component : fsl_clock_manager
7 ** Version : Component 1.2.0, Driver 01.00, CPU db: 3.00.000
8 ** Repository : KSDK 1.2.0
9 ** Compiler : GNU C Compiler
10 ** Date/Time : 2016-10-06, 13:38, # CodeGen: 0
11 **
12 ** Copyright : 1997 - 2015 Freescale Semiconductor, Inc.
13 ** All Rights Reserved.
14 **
15 ** Redistribution and use in source and binary forms, with or without modification,
16 ** are permitted provided that the following conditions are met:
17 **
18 ** o Redistributions of source code must retain the above copyright notice, this list
19 ** of conditions and the following disclaimer.
20 **
21 ** o Redistributions in binary form must reproduce the above copyright notice, this
22 ** list of conditions and the following disclaimer in the documentation and/or
23 ** other materials provided with the distribution.
24 **
25 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
26 ** contributors may be used to endorse or promote products derived from this
27 ** software without specific prior written permission.
28 **
29 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
30 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
31 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
33 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
34 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
35 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
36 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
38 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 **
40 ** http: www.freescale.com
41 ** mail: support@freescale.com
42 ** ###################################################################*/
43 /*!
44 ** @file clockMan1.c
45 ** @version 01.00
46 */
47 /*!
48 ** @addtogroup clockMan1_module clockMan1 module documentation
49 ** @{
50 */
51
52 /* clockMan1. */
53
54 #include "clockMan1.h"
55
56 /*! @brief OSC Initialization Configuration Structure */
57 osc_user_config_t clockMan1_osc0_Config = {
58 .freq = 50000000U,
59 .range = kOscRangeVeryHigh1,
60 .erefs = kOscSrcExt,
61
62 /*! @brief Configuration for OSCERCLK */
63 .oscerConfig =
64 {
65 .enable = true,
66 .enableInStop = false,
67 },
68 };
69
70 /* *************************************************************************
71 * Configuration structure for Clock Configuration 0
72 * ************************************************************************* */
73 /*! @brief User Configuration structure SpeedMode0 */
74 clock_manager_user_config_t clockMan1_InitConfig0 = {
75 /*! @brief Configuration of MCG */
76 .mcgConfig =
77 {
78 .mcg_mode = kMcgModeFEI, /*!< FEI mode */
79 /* ------------------ MCGIRCCLK settings ---------------------- */
80 .irclkEnable = true, /*!< MCGIRCLK enable */
81 .irclkEnableInStop = false, /*!< MCGIRCLK enable in stop mode */
82 .ircs = kMcgIrcSlow, /*!< Slow internal reference clock selected */
83 .fcrdiv = 0U,
84
85 /* -------------------- MCG FLL settings ---------------------- */
86 .frdiv = 0, /*!< MCG_C1[FRDIV] */
87 .drs = kMcgDcoRangeSelLow, /*!< MCG_C4[DRST_DRS] */
88 .dmx32 = kMcgDmx32Default, /*!< MCG_C4[DMX32] */
89 .oscsel = kMcgOscselOsc, /*!< Selects System Oscillator (OSCCLK) */
90
91 /* -------------------- MCG PLL settings ---------------------- */
92 .pll0EnableInFllMode = false, /*!< PLL0 enable in FLL mode */
93 .pll0EnableInStop = false, /*!< PLL0 enable in stop mode */
94 .prdiv0 = 0U, /*!< PRDIV0 */
95 .vdiv0 = 0U, /*!< VDIV0 */
96 },
97
98 /*! @brief Configuration of OSCERCLK */
99 .oscerConfig =
100 {
101 .enable = true, /*!< OSCERCLK enable or not */
102 .enableInStop = false, /*!< OSCERCLK enable or not in stop mode */
103 },
104
105 /*! @brief Configuration of SIM module */
106 .simConfig =
107 {
108 .pllFllSel = kClockPllFllSelFll, /*!< Fll clock */
109 .er32kSrc = kClockEr32kSrcRtc, /*!< ERCLK32K source selection */
110 .outdiv1 = 0U, /*!< OUTDIV1 setting */
111 .outdiv2 = 0U, /*!< OUTDIV2 setting */
112 .outdiv3 = 1U, /*!< OUTDIV3 setting */
113 .outdiv4 = 1U, /*!< OUTDIV4 setting */
114 }
115 };
116 /* *************************************************************************
117 * Configuration structure for Clock Configuration 1
118 * ************************************************************************* */
119 /*! @brief User Configuration structure SpeedMode1 */
120 clock_manager_user_config_t clockMan1_InitConfig1 = {
121 /*! @brief Configuration of MCG */
122 .mcgConfig =
123 {
124 .mcg_mode = kMcgModePEE, /*!< PEE mode */
125 /* ------------------ MCGIRCCLK settings ---------------------- */
126 .irclkEnable = true, /*!< MCGIRCLK enable */
127 .irclkEnableInStop = false, /*!< MCGIRCLK enable in stop mode */
128 .ircs = kMcgIrcSlow, /*!< Slow internal reference clock selected */
129 .fcrdiv = 0U,
130
131 /* -------------------- MCG FLL settings ---------------------- */
132 .frdiv = 0, /*!< MCG_C1[FRDIV] */
133 .drs = kMcgDcoRangeSelLow, /*!< MCG_C4[DRST_DRS] */
134 .dmx32 = kMcgDmx32Default, /*!< MCG_C4[DMX32] */
135 .oscsel = kMcgOscselOsc, /*!< Selects System Oscillator (OSCCLK) */
136
137 /* -------------------- MCG PLL settings ---------------------- */
138 .pll0EnableInFllMode = true, /*!< PLL0 enable in FLL mode */
139 .pll0EnableInStop = false, /*!< PLL0 enable in stop mode */
140 .prdiv0 = 19U, /*!< PRDIV0 */
141 .vdiv0 = 24U, /*!< VDIV0 */
142 },
143
144 /*! @brief Configuration of OSCERCLK */
145 .oscerConfig =
146 {
147 .enable = true, /*!< OSCERCLK enable or not */
148 .enableInStop = false, /*!< OSCERCLK enable or not in stop mode */
149 },
150
151 /*! @brief Configuration of SIM module */
152 .simConfig =
153 {
154 .pllFllSel = kClockPllFllSelPll, /*!< Pll0 clock */
155 .er32kSrc = kClockEr32kSrcRtc, /*!< ERCLK32K source selection */
156 .outdiv1 = 0U, /*!< OUTDIV1 setting */
157 .outdiv2 = 1U, /*!< OUTDIV2 setting */
158 .outdiv3 = 1U, /*!< OUTDIV3 setting */
159 .outdiv4 = 4U, /*!< OUTDIV4 setting */
160 }
161 };
162 /* *************************************************************************
163 * Configuration structure for Clock Configuration 2
164 * ************************************************************************* */
165 /*! @brief User Configuration structure SpeedMode2 */
166 clock_manager_user_config_t clockMan1_InitConfig2 = {
167 /*! @brief Configuration of MCG */
168 .mcgConfig =
169 {
170 .mcg_mode = kMcgModeBLPI, /*!< BLPI mode */
171 /* ------------------ MCGIRCCLK settings ---------------------- */
172 .irclkEnable = true, /*!< MCGIRCLK enable */
173 .irclkEnableInStop = false, /*!< MCGIRCLK enable in stop mode */
174 .ircs = kMcgIrcFast, /*!< Fast internal reference clock selected */
175 .fcrdiv = 0U, /*!< MCG_SC[FCRDIV] */
176
177 /* -------------------- MCG FLL settings ---------------------- */
178 .frdiv = 0, /*!< MCG_C1[FRDIV] */
179 .drs = kMcgDcoRangeSelLow, /*!< MCG_C4[DRST_DRS] */
180 .dmx32 = kMcgDmx32Default, /*!< MCG_C4[DMX32] */
181 .oscsel = kMcgOscselOsc, /*!< Selects System Oscillator (OSCCLK) */
182
183 /* -------------------- MCG PLL settings ---------------------- */
184 .pll0EnableInFllMode = false, /*!< PLL0 enable in FLL mode */
185 .pll0EnableInStop = false, /*!< PLL0 enable in stop mode */
186 .prdiv0 = 0U, /*!< PRDIV0 */
187 .vdiv0 = 0U, /*!< VDIV0 */
188 },
189
190 /*! @brief Configuration of OSCERCLK */
191 .oscerConfig =
192 {
193 .enable = true, /*!< OSCERCLK enable or not */
194 .enableInStop = false, /*!< OSCERCLK enable or not in stop mode */
195 },
196
197 /*! @brief Configuration of SIM module */
198 .simConfig =
199 {
200 .pllFllSel = kClockPllFllSelIrc48M, /*!< IRC48MCLK */
201 .er32kSrc = kClockEr32kSrcRtc, /*!< ERCLK32K source selection */
202 .outdiv1 = 0U, /*!< OUTDIV1 setting */
203 .outdiv2 = 0U, /*!< OUTDIV2 setting */
204 .outdiv3 = 0U, /*!< OUTDIV3 setting */
205 .outdiv4 = 3U, /*!< OUTDIV4 setting */
206 }
207 };
208 /* *************************************************************************
209 * Configuration structure for Clock Configuration 3
210 * ************************************************************************* */
211 /*! @brief User Configuration structure SpeedMode3 */
212 clock_manager_user_config_t clockMan1_InitConfig3 = {
213 /*! @brief Configuration of MCG */
214 .mcgConfig =
215 {
216 .mcg_mode = kMcgModeBLPE, /*!< BLPE mode */
217 /* ------------------ MCGIRCCLK settings ---------------------- */
218 .irclkEnable = true, /*!< MCGIRCLK enable */
219 .irclkEnableInStop = false, /*!< MCGIRCLK enable in stop mode */
220 .ircs = kMcgIrcFast, /*!< Fast internal reference clock selected */
221 .fcrdiv = 0U, /*!< MCG_SC[FCRDIV] */
222
223 /* -------------------- MCG FLL settings ---------------------- */
224 .frdiv = 0, /*!< MCG_C1[FRDIV] */
225 .drs = kMcgDcoRangeSelLow, /*!< MCG_C4[DRST_DRS] */
226 .dmx32 = kMcgDmx32Default, /*!< MCG_C4[DMX32] */
227 .oscsel = kMcgOscselRtc, /*!< Selects 32 kHz RTC Oscillator */
228
229 /* -------------------- MCG PLL settings ---------------------- */
230 .pll0EnableInFllMode = false, /*!< PLL0 enable in FLL mode */
231 .pll0EnableInStop = false, /*!< PLL0 enable in stop mode */
232 .prdiv0 = 0U, /*!< PRDIV0 */
233 .vdiv0 = 0U, /*!< VDIV0 */
234 },
235
236 /*! @brief Configuration of OSCERCLK */
237 .oscerConfig =
238 {
239 .enable = true, /*!< OSCERCLK enable or not */
240 .enableInStop = false, /*!< OSCERCLK enable or not in stop mode */
241 },
242
243 /*! @brief Configuration of SIM module */
244 .simConfig =
245 {
246 .pllFllSel = kClockPllFllSelIrc48M, /*!< IRC48MCLK */
247 .er32kSrc = kClockEr32kSrcRtc, /*!< ERCLK32K source selection */
248 .outdiv1 = 0U, /*!< OUTDIV1 setting */
249 .outdiv2 = 0U, /*!< OUTDIV2 setting */
250 .outdiv3 = 0U, /*!< OUTDIV3 setting */
251 .outdiv4 = 0U, /*!< OUTDIV4 setting */
252 }
253 };
254 /* *************************************************************************
255 * Configuration structure for Clock Configuration 4
256 * ************************************************************************* */
257 /*! @brief User Configuration structure SpeedMode4 */
258 clock_manager_user_config_t clockMan1_InitConfig4 = {
259 /*! @brief Configuration of MCG */
260 .mcgConfig =
261 {
262 .mcg_mode = kMcgModePEE, /*!< PEE mode */
263 /* ------------------ MCGIRCCLK settings ---------------------- */
264 .irclkEnable = true, /*!< MCGIRCLK enable */
265 .irclkEnableInStop = false, /*!< MCGIRCLK enable in stop mode */
266 .ircs = kMcgIrcFast, /*!< Fast internal reference clock selected */
267 .fcrdiv = 1U, /*!< MCG_SC[FCRDIV] */
268
269 /* -------------------- MCG FLL settings ---------------------- */
270 .frdiv = 0, /*!< MCG_C1[FRDIV] */
271 .drs = kMcgDcoRangeSelHigh, /*!< MCG_C4[DRST_DRS] */
272 .dmx32 = kMcgDmx32Default, /*!< MCG_C4[DMX32] */
273 .oscsel = kMcgOscselOsc, /*!< Selects System Oscillator (OSCCLK) */
274
275 /* -------------------- MCG PLL settings ---------------------- */
276 .pll0EnableInFllMode = true, /*!< PLL0 enable in FLL mode */
277 .pll0EnableInStop = false, /*!< PLL0 enable in stop mode */
278 .prdiv0 = 24U, /*!< PRDIV0 */
279 .vdiv0 = 0U, /*!< VDIV0 */
280 },
281
282 /*! @brief Configuration of OSCERCLK */
283 .oscerConfig =
284 {
285 .enable = true, /*!< OSCERCLK enable or not */
286 .enableInStop = false, /*!< OSCERCLK enable or not in stop mode */
287 },
288
289 /*! @brief Configuration of SIM module */
290 .simConfig =
291 {
292 .pllFllSel = kClockPllFllSelPll, /*!< Pll0 clock */
293 .er32kSrc = kClockEr32kSrcRtc, /*!< ERCLK32K source selection */
294 .outdiv1 = 0U, /*!< OUTDIV1 setting */
295 .outdiv2 = 1U, /*!< OUTDIV2 setting */
296 .outdiv3 = 1U, /*!< OUTDIV3 setting */
297 .outdiv4 = 1U, /*!< OUTDIV4 setting */
298 }
299 };
300 /* *************************************************************************
301 * Configuration structure for Clock Configuration 5
302 * ************************************************************************* */
303 /*! @brief User Configuration structure SpeedMode5 */
304 clock_manager_user_config_t clockMan1_InitConfig5 = {
305 /*! @brief Configuration of MCG */
306 .mcgConfig =
307 {
308 .mcg_mode = kMcgModePEE, /*!< PEE mode */
309 /* ------------------ MCGIRCCLK settings ---------------------- */
310 .irclkEnable = true, /*!< MCGIRCLK enable */
311 .irclkEnableInStop = false, /*!< MCGIRCLK enable in stop mode */
312 .ircs = kMcgIrcSlow, /*!< Slow internal reference clock selected */
313 .fcrdiv = 0U,
314
315 /* -------------------- MCG FLL settings ---------------------- */
316 .frdiv = 0, /*!< MCG_C1[FRDIV] */
317 .drs = kMcgDcoRangeSelLow, /*!< MCG_C4[DRST_DRS] */
318 .dmx32 = kMcgDmx32Default, /*!< MCG_C4[DMX32] */
319 .oscsel = kMcgOscselOsc, /*!< Selects System Oscillator (OSCCLK) */
320
321 /* -------------------- MCG PLL settings ---------------------- */
322 .pll0EnableInFllMode = true, /*!< PLL0 enable in FLL mode */
323 .pll0EnableInStop = false, /*!< PLL0 enable in stop mode */
324 .prdiv0 = 15U, /*!< PRDIV0 */
325 .vdiv0 = 8U, /*!< VDIV0 */
326 },
327
328 /*! @brief Configuration of OSCERCLK */
329 .oscerConfig =
330 {
331 .enable = true, /*!< OSCERCLK enable or not */
332 .enableInStop = false, /*!< OSCERCLK enable or not in stop mode */
333 },
334
335 /*! @brief Configuration of SIM module */
336 .simConfig =
337 {
338 .pllFllSel = kClockPllFllSelPll, /*!< Pll0 clock */
339 .er32kSrc = kClockEr32kSrcRtc, /*!< ERCLK32K source selection */
340 .outdiv1 = 0U, /*!< OUTDIV1 setting */
341 .outdiv2 = 1U, /*!< OUTDIV2 setting */
342 .outdiv3 = 1U, /*!< OUTDIV3 setting */
343 .outdiv4 = 3U, /*!< OUTDIV4 setting */
344 }
345 };
346
347 /*! @brief Array of pointers to User configuration structures */
348 clock_manager_user_config_t const * g_clockManConfigsArr[] = {
349 &clockMan1_InitConfig0,
350 &clockMan1_InitConfig1,
351 &clockMan1_InitConfig2,
352 &clockMan1_InitConfig3,
353 &clockMan1_InitConfig4,
354 &clockMan1_InitConfig5
355 };
356 /*! @brief Array of pointers to User defined Callbacks configuration structures */
357 clock_manager_callback_user_config_t * g_clockManCallbacksArr[] = {NULL};
358 /* END clockMan1. */
359
360 /*!
361 ** @}
362 */
363 /*
364 ** ###################################################################
365 **
366 ** This file was created by Processor Expert 10.5 [05.21]
367 ** for the Freescale Kinetis series of microcontrollers.
368 **
369 ** ###################################################################
370 */
clockMan1_InitConfig1
clock_manager_user_config_t clockMan1_InitConfig1
User Configuration structure SpeedMode1.
Definition: clockMan1.c:120
clockMan1.h
g_clockManCallbacksArr
clock_manager_callback_user_config_t * g_clockManCallbacksArr[]
Array of pointers to User defined Callbacks configuration structures.
Definition: clockMan1.c:357
clockMan1_InitConfig5
clock_manager_user_config_t clockMan1_InitConfig5
User Configuration structure SpeedMode5.
Definition: clockMan1.c:304
clockMan1_osc0_Config
osc_user_config_t clockMan1_osc0_Config
OSC Initialization Configuration Structure.
Definition: clockMan1.c:57
clockMan1_InitConfig3
clock_manager_user_config_t clockMan1_InitConfig3
User Configuration structure SpeedMode3.
Definition: clockMan1.c:212
g_clockManConfigsArr
clock_manager_user_config_t const * g_clockManConfigsArr[]
Array of pointers to User configuration structures.
Definition: clockMan1.c:348
clockMan1_InitConfig0
clock_manager_user_config_t clockMan1_InitConfig0
User Configuration structure SpeedMode0.
Definition: clockMan1.c:74
clockMan1_InitConfig4
clock_manager_user_config_t clockMan1_InitConfig4
User Configuration structure SpeedMode4.
Definition: clockMan1.c:258
clockMan1_InitConfig2
clock_manager_user_config_t clockMan1_InitConfig2
User Configuration structure SpeedMode2.
Definition: clockMan1.c:166
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