ISF  2.2 rev 5
Intelligent Sensing Framework for Kinetis with Processor Expert
mpl3115.h
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1 /**
2  * @file mpl3115.h
3  * @brief The \b mpl3115.h contains the MPL3115 Pressure sensor register definitions, access macros, and
4  * device access functions.
5  *
6  * @copyright Copyright (c) 2015, Freescale Semiconductor, Inc.
7  */
8 #ifndef _MPL3115_H_
9 #define _MPL3115_H_
10 
11 #include "isf.h"
12 #include "isf_devmsg.h"
14 
15 /***********************************************************************************************\
16  * Public macros
17 \***********************************************************************************************/
18 
19 #define MPL3115_IIC_ADDRESS 0x60 /*MPL3115A2 Address*/
20 
21 /***********************************************************************************************
22  **
23  ** MPL3115 Sensor Internal Registers
24  */
25 enum
26 {
27  MPL3115_STATUS_00 = 0, // 0x00
41  MPL3115_F_DATA, // 0x0E
42  MPL3115_F_SETUP, // 0x0F
44  MPL3115_SYSMOD, // 0x11
51  MPL3115_T_ARM, // 0x18
70  MPL3115_OFF_P, // 0x2B
71  MPL3115_OFF_T, // 0x2C
72  MPL3115_OFF_H // 0x2D
73 };
74 
75 /*
76  * General purpose macros to set/get a specific bit field within a register.
77  * The macro assumes that the root identifier for the field is a consistent character string (e.g., "BIT_FIELD").
78  * The bit field mask is the character string followed by "_MASK" (e.g., BIT_FIELD_MASK).
79  * The bit field shift is the character string followed by "_SHIFT" (e.g., BIT_FIELD_SHIFT).
80  */
81 #define MPL3115_SET_FIELD(name,val) (((val)<<MPL3115_##name##_SHIFT)&(MPL3115_##name##_MASK))
82 #define MPL3115_GET_FIELD(name,val) ((val&MPL3115_##name##_MASK)>>MPL3115_##name##_SHIFT)
83 
84 /*
85  ** STATUS_00 Register
86  */
87 #define STATUS_00_REG 0x00
88 #define DR_STATUS_00_REG 0x06
89 //
90 #define MPL3115_PTOW_MASK 0x80
91 #define MPL3115_PTOW_SHIFT 7
92 #define MPL3115_PTDR_MASK 0x08
93 #define MPL3115_PTDR_SHIFT 3
94 #define MPL3115_PDR_MASK 0x04
95 #define MPL3115_PDR_SHIFT 2
96 #define MPL3115_TDR_MASK 0x02
97 #define MPL3115_TDR_SHIFT 1
98 /*
99  ** WHO_AM_I Register
100  */
101 #define MPL3115_WHOAMI_VALUE 0xC4
102 
103 /*
104  ** SYSMOD System Mode Register
105  */
106 #define MPL3115_SYSMOD_MASK 0x01
107 #define MPL3115_SYSMOD_SHIFT 0
108 #define MPL3115_ACTIVE_MASK 1
109 
110 /*
111  ** INT_SOURCE System Interrupt Status Register
112  */
113 #define MPL3115_SRC_DRDY_MASK 0x80
114 #define MPL3115_SRC_DRDY_SHIFT 7
115 #define MPL3115_SRC_PW_MASK 0x20
116 #define MPL3115_SRC_PW_SHIFT 5
117 #define MPL3115_SRC_TW_MASK 0x10
118 #define MPL3115_SRC_TW_SHIFT 4
119 #define MPL3115_SRC_PTH_MASK 0x08
120 #define MPL3115_SRC_PTH_SHIFT 3
121 #define MPL3115_SRC_TTH_MASK 0x04
122 #define MPL3115_SRC_TTH_SHIFT 2
123 #define MPL3115_SRC_PCHG_MASK 0x02
124 #define MPL3115_SRC_PCHG_SHIFT 1
125 #define MPL3115_SRC_TCHG_MASK 0x01
126 #define MPL3115_SRC_TCHG_SHIFT 0
127 
128 /*
129  ** PT_DATA_CFG Sensor Data Configuration Register
130  */
131 #define MPL3115_DREM_MASK 0x04
132 #define MPL3115_DREM_SHIFT 2
133 #define MPL3115_PDEFE_MASK 0x02
134 #define MPL3115_PDEFE_SHIFT 1
135 #define MPL3115_TDEFE_MASK 0x01
136 #define MPL3115_TDEFE_SHIFT 0
137 
138 /*
139  ** CTRL_REG1 Interrupt Control Register
140  */
141 #define MPL3115_ALT_MASK 0x80
142 #define MPL3115_ALT_SHIFT 7
143 #define MPL3115_RAW_MASK 0x40
144 #define MPL3115_RAW_SHIFT 6
145 #define MPL3115_OS_MASK 0x38
146 #define MPL3115_OS_SHIFT 3
147 #define MPL3115_RST_MASK 0x04
148 #define MPL3115_RST_SHIFT 2
149 #define MPL3115_OST_MASK 0x02
150 #define MPL3115_OST_SHIFT 1
151 #define MPL3115_SBYB_MASK 0x01
152 #define MPL3115_SBYB_SHIFT 0
153 
154 /*
155  ** CTRL_REG2 Interrupt Control Register
156  */
157 #define MPL3115_LOAD_OUT_MASK 0x20
158 #define MPL3115_LOAD_OUT_SHIFT 5
159 #define MPL3115_ALARM_SEL_MASK 0x10
160 #define MPL3115_ALARM_SEL_SHIFT 4
161 #define MPL3115_ST_MASK 0x0F
162 #define MPL3115_ST_SHIFT 0
163 
164 /*
165  ** CTRL_REG3 Interrupt Control Register
166  */
167 #define MPL3115_IPOL1_MASK 0x20
168 #define MPL3115_IPOL1_SHIFT 5
169 #define MPL3115_PP_OD1_MASK 0x10
170 #define MPL3115_PP_OD1_SHIFT 4
171 #define MPL3115_IPOL2_MASK 0x02
172 #define MPL3115_IPOL2_SHIFT 1
173 #define MPL3115_PP_OD2_MASK 0x01
174 #define MPL3115_PP_OD2_SHIFT 0
175 
176 /*
177  ** CTRL_REG4 Interrupt Control Register
178  */
179 #define MPL3115_INT_EN_DRDY_MASK 0x80
180 #define MPL3115_INT_EN_DRDY_SHIFT 7
181 #define MPL3115_INT_EN_PW_MASK 0x20
182 #define MPL3115_INT_EN_PW_SHIFT 5
183 #define MPL3115_INT_EN_TW_MASK 0x10
184 #define MPL3115_INT_EN_TW_SHIFT 4
185 #define MPL3115_INT_EN_PTH_MASK 0x08
186 #define MPL3115_INT_EN_PTH_SHIFT 3
187 #define MPL3115_INT_EN_TTH_MASK 0x04
188 #define MPL3115_INT_EN_TTH_SHIFT 2
189 #define MPL3115_INT_EN_PCHG_MASK 0x02
190 #define MPL3115_INT_EN_PCHG_SHIFT 1
191 #define MPL3115_INT_EN_TCHG_MASK 0x01
192 #define MPL3115_INT_EN_TCHG_SHIFT 0
193 /*
194  ** CTRL_REG5 Interrupt Control Register
195  */
196 #define MPL3115_INT_CFG_DRDY_MASK 0x80
197 #define MPL3115_INT_CFG_DRDY_SHIFT 7
198 #define MPL3115_INT_CFG_PW_MASK 0x20
199 #define MPL3115_INT_CFG_PW_SHIFT 5
200 #define MPL3115_INT_CFG_TW_MASK 0x10
201 #define MPL3115_INT_CFG_TW_SHIFT 4
202 #define MPL3115_INT_CFG_PTH_MASK 0x08
203 #define MPL3115_INT_CFG_PTH_SHIFT 3
204 #define MPL3115_INT_CFG_TTH_MASK 0x04
205 #define MPL3115_INT_CFG_TTH_SHIFT 2
206 #define MPL3115_INT_CFG_PCHG_MASK 0x02
207 #define MPL3115_INT_CFG_PCHG_SHIFT 1
208 #define MPL3115_INT_CFG_TCHG_MASK 0x01
209 #define MPL3115_INT_CFG_TCHG_SHIFT 0
210 
211 
212 
213 /*
214  * Public Types
215  */
216 
217 // Define the MPL3115 functional interface status return type.
218 typedef enum
219 {
223 
224 typedef struct
225 {
229 
230 typedef struct
231 {
235 
236 
237 #endif /* _MPL3115_H_ */
unsigned char uint8
Definition: isf_types.h:76
mpl3115_status_t
Definition: mpl3115.h:218
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Definition: isf_types.h:78
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