//PF8150 - OTP Editor
//file generated on ܶ 9 23 13:24:21 2025
//Device Type : PF8150-QM
//OTP ID : EU
//Part Marking : PC32PF8150EUTS
//Customer : NXP

SET_DPIN:PF8150:PWRON:low
SET_DPIN:PF8150:WDI:low
SET_DPIN:PF8150:TBBEN:high

//MAIN_OTP
SET_REG:PF8150:OTP_MIRROR:OTP_FSOB_SELECT:0x00
SET_REG:PF8150:OTP_MIRROR:OTP_I2C:0x00
SET_REG:PF8150:OTP_MIRROR:OTP_CTRL1:0x03
SET_REG:PF8150:OTP_MIRROR:OTP_CTRL2:0x45
SET_REG:PF8150:OTP_MIRROR:OTP_CTRL3:0x00
SET_REG:PF8150:OTP_MIRROR:OTP_FREQ_CTRL:0x80
SET_REG:PF8150:OTP_MIRROR:OTP_COINCELL_CTRL:0x0b
SET_REG:PF8150:OTP_MIRROR:OTP_PWRON:0x00
SET_REG:PF8150:OTP_MIRROR:OTP_WD_CONFIG:0x20
SET_REG:PF8150:OTP_MIRROR:OTP_WD_EXPIRE:0x07
SET_REG:PF8150:OTP_MIRROR:OTP_WD_COUNTER:0xaf
SET_REG:PF8150:OTP_MIRROR:OTP_FAULT_COUNTER:0x00
SET_REG:PF8150:OTP_MIRROR:OTP_FAULT_TIMERS:0x0f
SET_REG:PF8150:OTP_MIRROR:OTP_PWRDN_DLY1:0x00
SET_REG:PF8150:OTP_MIRROR:OTP_PWRDN_DLY2:0x81
SET_REG:PF8150:OTP_MIRROR:OTP_PWRUP_CTRL:0x03
SET_REG:PF8150:OTP_MIRROR:OTP_RESETBMCU_PWRUP:0x55
SET_REG:PF8150:OTP_MIRROR:OTP_PGOOD_PWRUP:0x00
SET_REG:PF8150:OTP_MIRROR:OTP_SW1_VOLT:0x40
SET_REG:PF8150:OTP_MIRROR:OTP_SW1_PWRUP:0x15
SET_REG:PF8150:OTP_MIRROR:OTP_SW1_CONFIG1:0x53
SET_REG:PF8150:OTP_MIRROR:OTP_SW1_CONFIG2:0x3a
SET_REG:PF8150:OTP_MIRROR:OTP_SW2_VOLT:0x50
SET_REG:PF8150:OTP_MIRROR:OTP_SW2_PWRUP:0x19
SET_REG:PF8150:OTP_MIRROR:OTP_SW2_CONFIG1:0x53
SET_REG:PF8150:OTP_MIRROR:OTP_SW2_CONFIG2:0x22
SET_REG:PF8150:OTP_MIRROR:OTP_SW3_VOLT:0x50
SET_REG:PF8150:OTP_MIRROR:OTP_SW3_PWRUP:0x1d
SET_REG:PF8150:OTP_MIRROR:OTP_SW3_CONFIG1:0x53
SET_REG:PF8150:OTP_MIRROR:OTP_SW3_CONFIG2:0x3a
SET_REG:PF8150:OTP_MIRROR:OTP_SW4_VOLT:0xb1
SET_REG:PF8150:OTP_MIRROR:OTP_SW4_PWRUP:0x23
SET_REG:PF8150:OTP_MIRROR:OTP_SW4_CONFIG1:0x53
SET_REG:PF8150:OTP_MIRROR:OTP_SW4_CONFIG2:0x2a
SET_REG:PF8150:OTP_MIRROR:OTP_SW5_VOLT:0x40
SET_REG:PF8150:OTP_MIRROR:OTP_SW5_PWRUP:0x19
SET_REG:PF8150:OTP_MIRROR:OTP_SW5_CONFIG1:0x53
SET_REG:PF8150:OTP_MIRROR:OTP_SW5_CONFIG2:0x32
SET_REG:PF8150:OTP_MIRROR:OTP_SW6_VOLT:0x70
SET_REG:PF8150:OTP_MIRROR:OTP_SW6_PWRUP:0x25
SET_REG:PF8150:OTP_MIRROR:OTP_SW6_CONFIG1:0x53
SET_REG:PF8150:OTP_MIRROR:OTP_SW6_CONFIG2:0x12
SET_REG:PF8150:OTP_MIRROR:OTP_SW7_VOLT:0x15
SET_REG:PF8150:OTP_MIRROR:OTP_SW7_PWRUP:0x29
SET_REG:PF8150:OTP_MIRROR:OTP_SW7_CONFIG1:0x53
SET_REG:PF8150:OTP_MIRROR:OTP_SW7_CONFIG2:0x02
SET_REG:PF8150:OTP_MIRROR:OTP_LDO1_VOLT:0x5b
SET_REG:PF8150:OTP_MIRROR:OTP_LDO1_PWRUP:0x21
SET_REG:PF8150:OTP_MIRROR:OTP_LDO1_CONFIG:0x04
SET_REG:PF8150:OTP_MIRROR:OTP_LDO2_VOLT:0x5b
SET_REG:PF8150:OTP_MIRROR:OTP_LDO2_PWRUP:0x29
SET_REG:PF8150:OTP_MIRROR:OTP_LDO2_CONFIG:0x34
SET_REG:PF8150:OTP_MIRROR:OTP_LDO3_VOLT:0x52
SET_REG:PF8150:OTP_MIRROR:OTP_LDO3_PWRUP:0x19
SET_REG:PF8150:OTP_MIRROR:OTP_LDO3_CONFIG:0x04
SET_REG:PF8150:OTP_MIRROR:OTP_LDO4_VOLT:0x52
SET_REG:PF8150:OTP_MIRROR:OTP_LDO4_PWRUP:0x1d
SET_REG:PF8150:OTP_MIRROR:OTP_LDO4_CONFIG:0x04
SET_REG:PF8150:OTP_MIRROR:OTP_VSNVS_CONFIG:0x01
SET_REG:PF8150:OTP_MIRROR:OTP_OV_BYPASS1:0x00
SET_REG:PF8150:OTP_MIRROR:OTP_OV_BYPASS2:0x00
SET_REG:PF8150:OTP_MIRROR:OTP_UV_BYPASS1:0x00
SET_REG:PF8150:OTP_MIRROR:OTP_UV_BYPASS2:0x00
SET_REG:PF8150:OTP_MIRROR:OTP_ILIM_BYPASS1:0x00
SET_REG:PF8150:OTP_MIRROR:OTP_ILIM_BYPASS2:0x00
SET_REG:PF8150:OTP_MIRROR:OTP_PROG_IDH:0x04
SET_REG:PF8150:OTP_MIRROR:OTP_PROG_IDL:0x1c
SET_REG:PF8150:OTP_MIRROR:OTP_DEBUG1:0x01
SET_REG:PF8150:OTP_MIRROR:OTP_SW_COMP1:0x00
SET_REG:PF8150:OTP_MIRROR:OTP_SW_COMP2:0x00
SET_REG:PF8150:OTP_MIRROR:OTP_SW_COMP3:0x00
SET_DPIN:PF8150:TBBEN:low
SET_DPIN:PF8150:PWRON:high


//Rev,A