Enclosed are some user's guide type notes for the following issues which 
have been stumbling blocks to some initial 68EN302 customers.

- Illegal addresses (also when ethernet is in reset)
- 8-bit mode
- DRAM address and mask field settings
- CS and DRAM control (past designs w/ external DRAM needed CS)
- SCC and external memory (FC)


1. In the 68302 DTACK is returned when any location within internal register 
or RAM space is accessed. In the 68EN302 DTACK is NOT returned for all 
locations within the 4kbyte space whose location is defined by the MOBA field
in the MOBAR register. Exceptions are the following:

	- Unimplemented registers (for examble MOBA + 020 hex)
	- Address Recognition RAM (MOBA + A00 to BFF) when RESET bit in 
	  ECNTRL register = 0.
	- Buffer Descriptor RAM (MOBA + C00 to FFF) when RESET bit in 
	  ECNTRL register = 0. 


2. 8-Bit Chip Selects
Reference section 2.6 of the MC68EN302 reference manual and section 3.6
of the MC68302 user's manual.

The 68EN302 added dynamic bus sizing, allowing accesses to 8-bit external
devices via the CS0,1,2 and 3 pins. When using chip selects in 16-bit mode, 
the chip select is controlled by the ORx and BRx register (x = 0,1,2 or 3) 
in the 302 core. When using a chip select in 8-bit mode it is controlled by 
the corresponding CSERx register as well as the ORx and BRx registers. 
The 302 core in the 68EN302 always operates in 16-bit mode independent of 
whether the associated CS is in 8-bit or 16-bit mode.

A chip select may be put into 8-bit mode in one of two ways. 

(a) Selecting 8-bit mode during reset (8-bit boot ROM)
If the PARITY1/BUSW pin is held low during a system reset then the EN8 bit is
asserted in all four CSER3-CSER0 registers. In addition the DTACK field in OR0
is set to 111 (external DTACK). The 302 core operates in 16-bit mode and
depends on "external" logic to generate DTACK. The "external" logic is
the CSER0 logic which may provide the DTACK or if DT = 111 in CSER0 the
DTACK must be provided from logic external to the chip. The dynamic bus
sizing logic associated with the CSER0 register provides bus control to
interface between the 8-bit external bus (D15:8) and the 16-bit 302 core bus.

Following a reset selecting 8-bit mode the EN bits in BR1,2 and 3 in the 302
core are set = 0. CS1,2 and 3 may then be enabled by software for either
8-bit or 16-bit mode. If 8-bit mode is desired the DTACK field in the 
corresponding ORx register must be set to 111, the EN bit set = 1 in the
corresponding BRx register and the FCE/DT fields in the CSERx register
set for the desired wait state behavior.

If 16-bit mode is desired on CS1,2 or 3 then the EN8 bit in the corresponding
CSERx register must be cleared (=0) and the EN bit in the corresponding
BR1,2 or 3 register must be set = 1.

(b) Selecting 8-bit mode when boot rom is 16-bits wide.
Following a reset where the PARITY1/BUSW is held high, the EN8 bit is cleared
in all four CSER3-CSER0 registers. At that point the four chip select lines
are controlled by the OR3-OR0 and BR3-BR0 registers. Any given CS may be
put into 8-bit mode by setting the DTACK field in the corresponding ORx
register to 111, setting the EN8 bit in the CSERx register and putting
the desired value into the FCE/DT[2:0] fields in the CSERx register.


A final note on the CSER registers. The CSPE bit in these registers is valid
for either 16-bit or 8-bit modes. The other fields (FCE,DT,EN8) only apply
to 8-bit mode and are ignored when EN8 = 0.


3. DRAM address and mask field settings
Reference section 3 of the MC68EN302 user's manual.

Control of the RAS and CAS lines for the two DRAM banks is via the DCR and
DBA0/1 registers. Refresh timing is via the DRFRSH register. 

The DCR provides the following options:
	- Refresh enable (E1/E0 bits) - per bank

	- Parity enable (PE1/PE0 bits) - per bank

	- RAS precharch timing (P[1:0] - one field which applies to both banks)

	- Wait states (W[1:0] - one field which applies to both banks)
	  This controls when DTACK is generated by the dram controller for
	  accesses to the DRAM banks.

	- Write Protect(WP1/WP0 bits) - per bank

	- FC decode (S/U1 and S/U0 bits) - per bank 
	  The FC field must be either 6 or 5 (S/U1-0 = 0) or
	  6/5/2/1 (S/U1-0 = 1). The source of the bus transaction to DRAM
	  must insure the FC field is driven compatible with the setting
	  of the S/U1 or S/U0 bits. If the source is the ethernet dma
	  controller the FC field is determined by the MFC[2:0] field in
	  the MBCTL register (offset 0 from MOBA).

The DBA1 and DBA0 registers define the base address and size of the dram
banks. They are analogous to the OR0-3 and BR0-3 registers for the chip
select pins. The fields of the DBA1/0 registers are explained below:

The A[23:17] field of the DBA1/DBA0 registers defines the dram bank base
address on 128 kbyte boundaries. Make sure that the chip select logic 
does not map one of the chip selects into the same memory space as the 
dram (via the BRx and ORx register settings).

The M[22:17] field of the DBA1/DBA0 registers defines the size/location
of the dram bank. M23 cannot be programmed, it is equal to 1 by design.

The V bit must be set = 1 to enable accesses to the DRAM bank. The DCR and
DRFRSH registers should be initialized prior to asserting the V bit for
a given bank (the refresh rate can be changed during operation without
deasserting the V bit). Examples of dram controller initialization follows:

Example 1. Bank 0, base address = $000_000, size = 4 MBytes
	* Address range = $000_000 through $3FF_FFF
	* DBA0 = $0041

Example 2. Bank 0, base address = $200_000, size = 1 MBytes
	* Address range = $200_000 through $2FF_FFF
	* DBA0 = $2071



4. CS and DRAM control (past designs w/ external DRAM needed CS)
In porting a 68302 based design with an external DRAM controller to a
68EN302 based design, several changes must be made in the programming
of the 68302 core registers.

Assuming CS1 was used in the 68302 based design to select DRAM memory
space, the following changes need to be made (assume bank 0 of the
dram controller will be used):

	- Disable CS1 by clearing the EN bit in the BR1 register or
	  use CS1 for some other function, setting the BR1 and OR1 registers
	  so they do not overlap in memory space with the dram.

	- Setup the DCR register as follows
		* E1 = 0, E0 = 1
		* PE1 = 0, PE0 = 1 for DRAM with parity, 0 for no parity
		* P[1:0] - set as needed for RAS precharge time between cycles
		* W[1:0] - set as needed for DRAM access time. This replaces
		  the DTACK[2:0] field in the OR1 register.
		* WP1 = 0, WP0 = 0 to allow writes to DRAM, 
		  1 to allow read only
		* S/U1 = 0, S/U0 = 0 or 1 as needed, defined by FC value
		  provided by source of transaction to DRAM. This replaces
		  the FC[2:0] field in the BR1 register

	- Setup the DRFRSH register for the desired refresh rate

	- Setup the DBA0 register as follows
		* Set A[23:17] same as the BR1, base address A[23:17]
	 	  in the 68302 based design
		* Set M[22:17] same as the M[22:17] bits in the OR1 register
		  in the 68302 based design. In the DBA0 design M23 is 1
		  by design.
		* Set V = 1


5. Using SDMA to move data between an SCC and external memory (FC)

5.1 External RAM under control of a CS pin
Programming of the SDMA, SCC and chip select logic is the same in the
68EN302 as it would be in a 68302 based design if the external ram is
16 bits wide. The 68EN302 CSERx register corresponding to the chip select
must have the EN8 bit cleared (=0).

If external RAM is 8 bits wide, then the following must be done
	- set DTACK[2:0] = 111 in the corresponding ORx register
	- set EN8 = 1 in the corresponding CSERx register
	- set the FCE and DT[2:0] fields in the CSERx register to
	  determine the number of wait states. If DTACK is to be generated
	  by logic external to the chip then set FCE = 0, DT[2:0] = 111
	  in the CSERx register.

5.2 External DRAM using the 68EN302 dram controller logic
	Set up the DRAM controller as described in notes 3 and 4 above.
Pay attention to the SDMA TFCR and RFCR register settings (function code
for SDMA transfers) and to the DCR register S/U1 or S/U0 settings to
insure function code compatability.
	Also insure that no chip select is mapped to the same memory space
as the DRAM controller as the chip select logic and the dram control
logic independently decode address space.


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