|
| Freescale Semiconductor MCU Glossary |
|
|
|
|
|
| ACIM |
| A/C Induction Motor |
| |
| A/D: Digital to Analog Converter |
| The Analog to Digital (A/D) converter is an on-chip module that periodically samples external analog signals and produces corresponding digital values. The A/D converter is typically used to measure analog inputs like motor speed, temperature, and pressure or fluid levels. |
| |
| ADC |
| Analog-to-Digital Converter |
| |
| ADC Clock |
| The ADC blocks run at a slower speed than the rest of the system. A separate ADC clock is derived from the system IPBus clock based upon the divisor specified in the ADC Control Register 2 (ADCR2). |
| |
| ADCR |
| ADC Control Register |
| |
| ADDR |
| Address |
| |
| ADHLMT |
| ADC High Limit Registers |
| |
| ADLLMT |
| ADC Low Limit Registers |
| |
| ADLST |
| ADC Channel List Registers |
| |
|
|
|
|
| CAN: Controller Area Network |
The Controller Area Network, or CAN, protocol is a serial communication
protocol originally developed by Robert Bosch GmbH for use in serial
communication networks in vehicles. Several major auto manufacturers are
either currently using CAN networks in their vehicles or are developing them
for future vehicles. In addition, CAN is becoming very popular for use in
factory-floor automation-type industrial networks. The major players in
industrial automation, including Allen-Bradley, Honeywell and Eaton
Cutler-Hammer are all manufacturing CAN-based industrial control systems, and
are publicizing their beliefs that the CAN protocol is the best solution for
this type of control network.
The CAN specification addresses the lowest two layers of the ISO's Open
Systems Interconnect (OSI) Reference model for communication protocols, the
Data Link Layer and the Physical Layer. However, while certain aspects of the
Physical Layer are addressed by the CAN protocol, its primary purpose is to
define the aspects of the Media Access Control (MAC) sublayer and a small part
of the Logical Link Control (LLC) sublayer of the Data Link Layer. Almost all
aspects of the Physical Layer (data rate, choice of media, etc) are left to
the user.
Some properties of the CAN protocol:
- CAN is a multi-master protocol which utilizes non-destructive collision
resolution to ensure the highest priority message is transmitted
- The message prioritization is defined by the user, with a guaranteed
maximum latency for the highest priority messages
- A flexible system configuration allows the user to create the network
which best fits the application
- Error detection and error signaling features are built into the CAN
protocol, along with automatic retransmission of corrupted messages
- A distinction between temporary errors and permanent node failures
prevents faulty nodes from causing long-term disruptions of network traffic
CAN
Specification ver. 2.0: The most recent version of the CAN specification
is version 2.0, released in 1991. This version is divided into 2 parts,
cleverly named Part A and Part B. Part A is simply a restatement of the
previous revision (version 1.2), while Part B adds the definition of the
29-bit Extended Identifier message format to the existing 11-bit Standard
Identifier message format defined in the earlier CAN specifications. All
current Freescale Semiconductor HC05-based CAN devices support only the 11-bit identifier,
and therefore are considered to be compliant with the CAN specification
version 2.0 Part A. |
|
|
|
|
| CCTV: Closed Caption Television |
|
The closed caption television (CCTV) module is used in television
receivers, set-top decoders, or VCRs conforming to the NTSC standard. A
programmable data slicer (DSL) extracts closed-caption compatible data from an
NTSC composite video signal for closed-caption and extended data services
applications. Once the data is extracted an on-screen display system (OSD)
displays the data on the television screen. |
|
|
| CGM: Clock Generator Module |
|
The Clock Generator Module (CGM) is a 68HC08 module that generates two
different clock signals from a user-selected source. The crystal clock signal
is buffered by the CGM and used by the SCI baud rate generator and the COP
watchdog timer. In addition, the output clock of the CGM, generated by either
the crystal clock or an on-board phased-lock loop clock, is used by the SIM,
which drives internal bus clocks. The on-board phased-lock loop can be used to
generate maximum bus speed (8 MHz) cost-effectively (1 MHz to 16 MHz external
crystal). |
|
|
COP: Computer Operating Properly
WDOG: Watch Dog Timer |
|
The Computer Operating Properly (COP) watchdog timer is designed to detect
software errors. When the COP is being used, the user's software is
responsible for regularly resetting the COP timer; if this does not happen,
the CPU assumes there is a problem and resets to a known condition. It's
typically used to prevent CPU runaway. |
|
|
| CPU: Central Processing Unit |
The Central Processing Unit (CPU) processes information in accordance with
a program of instructions and data in a particular language called "machine
code". The CPU controls all the system operations and provides control signals
for enabling and disabling the various peripherals and I/O devices.
The 68HC05 CPU core is the most popular 8-bit microcontroller architecture
in the world with well over 1 BILLION units shipped. The accumulator based
HC05 CPU is a relatively easy to program and understand architecture. In
addition to the accumulator, the CPU's core has an index register, a 5-bit
stack pointer, and a 5-bit condition code register. The instruction set
features 10 uncomplicated addressing modes including 8 and 16-bit indexing
from the 16-bit program counter. Bit manipulation instructions are provided to
set, clear, test, or jump based on a bit value anywhere in the memory map.
Math functions include add, subtract, and multiply.
The HC05 CPU is a fully static low power HCMOS design that features
flexible power management capabilities. Wait mode reduces power consumption by
approximately 50% by discontinuing CPU processing. The clock continues to run
in wait mode inorder to service interrupts immediately. Stop mode stops the
clock and all internal processing to reduce power consumption to micoroamps.
Both modes maintain memory and enable an interrupt to wake up the CPU. |
|
|
|
|
| D/A: Digital to Analog Converter |
|
The Digital to Analog (D/A) module accepts a series of binary numbers from
the CPU and produces a corresponding analog signal. This is usually performed
by pulse width modulation (PWM) that requires external filtering. A typical
example of a D/A application would be the volume control on a television set. |
|
|
| DMA: Direct Memory Access |
The Direct Memory Access (DMA) module is a co-processor that can transfer
data between any two CPU-addressable locations without CPU intervention. Since
I/O registers are memory-mapped, the DMA can read from or write to peripherals
(such as SCI, SPI, or Timer) in two to four bus cycles - a vast improvement
over the minimum 16 bus cycles needed for a traditional CPU interrupt
routine.
Additional features of the DMA include up to seven independent channels, up
to 8 transfer sources, byte or word transfer capability, block or loop
transfers, programmable bus bandwidth, CPU interrupt capability on transfer
completion, and memory stretch capability for addresses beyond the 64 Kbyte
internal memory map. |
|
|
| DTMF: Dual-Tone Multi-Frequency |
Dual-Tone Multiple Frequency (DTMF) transmitters incorporate a
multi-functional tone generator which supports:
- DTMF dialing (the tone you hear when you press a number on a touch tone
telephone)
- Melody-on-hold (generate a simple melody when you are on hold)
- Pacifier tone functions (acknowledge button pressed)
Dual-Tone Multiple Frequency (DTMF) receivers can detect and qualify DTMF
signals. The 68HC05F5 DTMF utilizes a switched capacitor technology for
filtering. Included is a Pre-emphasis filter (for high frequency gain) and two
band separation filters (for high and low frequencies). There are an
additional eight bandpass filters for final frequency selection. |
|
|
|
|
| EBI: External Bus Interface |
|
The 68HC05CO is an expandable 68HC05 microcontroller which does not have
any on-chip user-programmable ROM. The EBI can address up to 64k of external
memory using either a multiplexed or non-multiplexed external bus. As such,
they are available off the shelf without mask charge or delay. |
|
|
EEPROM: Electrically Eraseable Programmable Read Only Memory
EPROM:
Eraseable Programmable Read Only Memory |
|
Electrically Erasable Programmable Read Only Memory (EEPROM) and Erasable
Programmable Read Only Memory (EPROM) are both types of ROM that can be
programmed by the user. EPROM can be erased by exposing it to ultraviolet
light, whereas EEPROM can be erased electrically (i.e., in the application).
Once erased, EPROMs and EEPROMs may be reprogrammed with new instructions and
data. EEPROM and EPROM information is non-volatile in that it does not change
when power is removed. |
|
|
|
|
| IC: Input Capture (Timer Function) |
|
The input capture (IC) mechanism of a timer can be used to detect the time
of an event or measure the period of an input signal. When the selected edge
occurs, the current value of the free-running counter is captured by the input
capture register, which can later be read by the CPU. This is the timer
mechanism typically used in the timing of external events. |
|
|
| I2C: Inter-Integrated Circuit |
|
The inter-integrated circuit (I2C) is a synchronous bi-directional serial
bus which provides a simple, efficient way for data exchange between devices
at up to 100Kbit/s. The maximum communication distance and number of devices
that can be connected is limited by the maximum bus capacitance of 400pF. |
|
|
i/o: Bi-directional Input and Output Port Pins
i: Input Only Port
Pins
o: Output Only Port Pins |
|
Bi-directional Input and Output (I/O) ports couple the microcontroller to
external devices. This interface can operate in parallel or serial form and is
usually digital (0 to +5Vdc) logic. Parallel interfaces allow I/O data
transfer of eight bits at a time to parallel ports on the microcontroller. The
technology is typically used to transfer data between the microcontroller and
the external logic it controls. |
|
|
|
|
| KBI: Key Board Interrupt |
Typical microcontroller applications have some sort of user input in the
form of pressing a button or keypad. In battery powered applications it is
desirable to have the MCU in a low power wait or stop mode while waiting for
key pad input. When a user presses a key on the keypad an interrupt is
generated. The interrupt wakes the MCU out of low power mode to execute the
code that is appropriate for the key that was pressed. The KBI port pins
eliminate glue logic by having pull-up resistors and logic that generates an
interrupt if any of the port pins are pulled low.
A typical MCU key matrix has the ROW lines connected to the KBI input port
pins and the COLUMN lines connected to MCU output port pins.
If any key in the matrix is pressed:
- The row of the key is pulled low, generating an interrupt that wakes the
MCU up from low-power mode
- Software debounces and scans the columns to determine which key was
depressed
|
|
|
|
|
| LCD: Liquid Crystal Display |
|
There are several different liquid crystal display (LCD) modules in the
68HC05 and 68HC08 family that directly drive liquid crystal displays of sizes
ranging from 45 segments to over 20,000 bit mapped pixel displays. |
|
|
| LVI: Low-Voltage Interrupt |
|
The low voltage interrupt (LVI) circuit monitors the operating voltage of
the MCU and generates an interrupt to the MCU if the voltage drops below a
predefined minimum. MCUs can continue to operate below the specified minimum
voltage rating but may experience unpredictable operation before they fail.
The LVI circuit generates an interrupt where software can cause an orderly
shutdown before unpredictable behavior can occur. |
|
|
| LVPI: Low Voltage Program Inhibit |
|
The low voltage program inhibit (LVPI) circuit monitors the operating
voltage of the MCU and inhibits programming of the MCU if the voltage drops
below a predefined minimum. MCUs can continue to program below the specified
minimum voltage rating but may experience unpredictable operation before
programming fails. The LVPI circuit inhibits programming before any
unpredictable behavior can occur. |
|
|
| LVR: Low Voltage Reset |
|
The low voltage reset (LVR) circuit monitors the operating voltage of the
MCU and forces a reset of the MCU if the voltage drops below a predefined
minimum. MCUs can continue to operate below the specified minimum voltage
rating but may experience unpredictable operation before they fail. The LVR
circuit places the MCU in the reset state before any unpredictable behavior
can occur. |
|
|
|
|
| MCU: Microcontroller Unit |
A microcontroller unit (MCU) is an integrated circuit (IC) that contains
many of the functions found in a typical computer system. A microcontroller
uses a microprocessor as its central processing unit and incorporates features
such as memory, a timing reference, and input/output peripherals, all on the
same chip.
Microcontrollers are very useful in any application in which many decisions
or calculations are required. In most cases, it is easier to use the
computational power of an MCU rather than use discrete logic. The cost of the initial software development is more than offset
by the continued savings in hardware cost and reduced board space.
Typical Microcontroller Application Examples:
- Telephones
- Answering Machines
- Pagers
- Motor Control
- Appliances
- Factory Automation
- Mouse
- Keyboards
- Stereos
- Televisions
- Remote Controls
- Toys
- Smartcards
- Multiplexed Systems
- Anti-lock Braking Systems
|
|
|
| MDLC: Message Data Link Controller (J1850 Multiplex) |
The Message Data Link Controller (MDLC) incorporates a serial
communication multiplex bus that operates according to the SAE J1850 Protocol.
Multiple microcontrollers with the MDLC module can communicate over a single
or dual wire bus, eliminating the weight and bulk of wire harnesses and adding
diagnostic capability.
Some properties of the mdlc module:
- Single Transmit Buffer
- Dual Ping Pong Receive Buffers
- Integrated J1850 VPW Physical Interface
- Supports Messages of Unlimited Length
- Optional CPU Interrupt Capability
- Automatic Transmission Retry Following Loss Of Arbitration
- Supports 10.4KBPS J1850-VPW Communication Only
- Very Low CPU Overhead, Typically 5%
- Power Saving Module Stop and Wait Modes With Optional WakeUp on Network
Activity
SAE Standard J1850 Class B Data Communication Network Interface (J1850)
The J1850 protocol encompasses the lowest two layers of the International
Standards Organization (ISO) open system interconnect (OSI) model, the data
link layer and the physical layer. It is a multi-master system, utilizing the
concept of carrier sense multiple access with collision resolution (CSMA/CR),
whereby any node can transmit if it has determined the bus to be free.
Non-destructive arbitration is performed on a bit-by-bit basis whenever
multiple nodes begin to transmit simultaneously. J1850 allows for the use of a
single or dual wire bus, two data rates (10.4 kbps or 41.7 kbps), and two bit
encoding techniques (pulse width modulation (PWM) or variable pulse width
modulation (VPW)).
A J1850 message, or frame, consists of a start of frame (SOF) delimiter, a
one- or three-byte header, zero to eight data bytes, a cyclical redundancy
check (CRC) byte, an end of data (EOD) delimiter, and an optional in-frame
response, followed by an end of frame (EOF) delimiter. Frames using a single
byte header are transmitted at 10.4 kbps, using VPW modulation, and contain a
CRC byte for error detection. Frames using a one-byte consolidated header or a
three-byte consolidated header can be transmitted at either 41.7 kbps or 10.4
kbps, using either PWM or VPW modulation techniques, and also contain a CRC
byte for error detection.
Each frame can contain up to 12 bytes (VPW) or 101 bit times (PWM), with
each byte transmitted MSB first. The optional in-frame response can contain
either a single byte or multiple bytes, with or without a CRC byte. The
requirements of each individual network determine which features are used. |
|
|
| MFT: Multi Function Timer |
|
The timer system is used to measure time and to produce signals of
specific frequency periods. Timers can be used in multiple ways: The CPU can
control the timing of output signals through the output compare mechanism and
monitor incoming signals through the input capture mechanism, and the CPU can
use the timer system as an internal reference (e.g., delay loops or
multiplexing between various software tasks). The timer can be used for
virtually any timing function, including waveform generation, simple D/A
conversion, and so on. |
|
|
|
|
| OC: Output Compare (Timer Function) |
|
The output compare (OC) mechanism of a timer can be used to schedule an
output change to occur at a specific time in a timer cycle. The planned output
change occurs when the free-running counter matches the value in the output
compare register. This is the timer mechanism typically used for control of
outgoing timing references. |
|
|
| OSD: On-Screen Display |
|
The on-screen display (OSD) module converts programmed character addresses
and control information into digital color and blanking outputs to display
user defined characters on a television screen for on-screen programming and
closed-captioning applications. |
|
|
| OTPROM: One Time Programmable Read Only Memory |
|
One-time Programmable Read Only Memory (OTPROM) is an EPROM that does not
have a window on top of the package, which means that the memory cannot be
exposed to ultraviolet light and therefore cannot be erased and reprogrammed.
OTPROM versions of most microcontrollers are available to support your
development and production needs. OTP information is non-volatile in that it
does not change when power is removed. |
|
|
|
|
PEP: Personality EPROM
PEEP: Personality EEPROM |
Mask ROM MCUs are typically lower in cost compared to OTP, EPROM, or
EEPROM MCUs in high volume applications. OTP, EPROM, and EEPROM MCUs have the
advantage of being able to customize each microcontroller whereas a mask ROM
MCU must have the same code.
Personality EPROM (PEP) is a small block of EPROM organized serially that
can be added to mask ROM MCUs. While more expensive than mask ROM parts, they
are typically cheaper than all EPROM or OTP parts and retain the advantage of
customization.
Personality EEPROM (PEEP) is identical in function to PEP except the EPROM
is replaced by EEPROM.
Typical applications of PEP and PEEP include:
- Storage of electronic I.D. (serial number)
- RF security systems (remote car locks, home alarm, etc)
- Configuration data
- Increase reliability and lower cost by eliminating dip switches
- Allow more user friendly set-up and use
- Calibration data
- Correct for system variation at manufacturing or in the field
|
|
|
| PLL: Phase-Lock Loop |
|
The phase-locked loop (PLL) is a frequency generator that takes an input
clock frequency and multiples it to a much higher frequency. The 68HC08 has
two different PLL modules, one uses a 32Khz crystal as its input and another
uses a 1 - 4 Mhz crystal. Both versions generate the internal clocks used to
support 8Mhz bus operation. Without the PLL, 68HC08s would require a 32Mhz
oscillator which is expensive and can potentially generate unwanted noise in
the MCU application. The 68HC05 has several different PLL modules used to
generate the high frequencies needed for on screen displays and
closed-captioning. |
|
|
| PWM: Pulse-Width Modulation |
|
The pulse width modulate (PWM) mechanism is useful for generating signals
to control motors, gauge drivers, switching power supplies, and low cost D/A
converters. A typical D/A application would configure the PWM module to a
generate a waveform with a fixed period and to set the duty cycle (the
relative time the signal is high vs low) to specify the desired analog
value. |
|
|
|
|
| ROM: Read Only Memory |
|
Read Only Memory (ROM) is a permanent form of memory that is written to
during manufacture. The CPU can read information from a ROM location, but
cannot write information into it. ROM information is non-volatile in that it
does not change when power is removed. |
|
|
| RTC: Real-Time Clock |
|
The real-time clock (RTC) mechanism is similar to the RTI although with
some software it can easily be used to keep time in hours, minutes, days, etc.
|
|
|
| RTI: Real-Time Interrupt |
|
The real-time interrupt (RTI) mechanism is useful for generating a
periodic interrupt automatically every x (programmable) amount of time. This
can be useful for executing diagnostics, maintenance routines, and polling i/o
or events.
|
|
|
|
|
| SCI: Serial Communications Interface (Asynchronous) |
|
The Serial Communications Interface (SCI) is an independent serial I/O
subsystem (full-duplex UART-type asynchronous system). The SCI can be used for
communications between the microcontroller and a terminal, PC, or other
microcontrollers in the form of a network. An on-chip baud rate generator
derives standard baud-rate frequencies from the microcontroller oscillator. A
typical SCI application is long-distance communications (RS-232).
|
|
|
| SCI+: Serial Communications Interface (Asynchronous and
Synchronous) |
|
|
The SCI+ is similar to the SCI with additional support for synchronous
serial communications. A transmitter clock output is used to transfer data
synchronously to SPI like peripherals.
|
|
|
| SIM: System Interface Module |
|
|
The System Interface Module (SIM) functions as a system state controller
handling CPU event timing with internal and external modules as well as
exception control timing. Some of the SIM's responsibilities include control
of mode selection, master reset control, bus clock generation, STOP/WAIT/RESET
entry and recovery, and control of interrupt execution and timing.
|
|
|
| SIOP: Simple Serial I/O Port (Synchronous) |
|
|
The Simple Serial I/O Port (SIOP) is a simpler implementation of the SPI.
The serial clock has fixed polarity and no slave select pin is provided.
|
|
|
| SPI: Serial Peripheral Interface (Synchronous) |
|
|
The Serial Peripheral Interface (SPI) is similar to the SCI, although it
is used to communicate synchronously over shorter distances at up to 4 Mbit/s.
The SPI allows the microcontroller to communicate with peripheral devices,
which could be anything from a simple TTL shift register to a complete
subsystem such as an LCD display or an A/D converter system. The SPI is
flexible enough to interface directly with numerous standard peripherals from
many manufacturers. SPIs can also be used to expand the number of inputs and
outputs of the microcontroller with the minimum number of pins. Typical
applications are in peripheral communications.
|
|
|
|
|
| USB: Universal Serial Bus |
|
Universal Serial Bus (USB) is a protocol for computer peripherals to
communicate with their host computers. Peripherals include digital audio,
telephone interfaces, cable boxes, printers, monitors, keyboard, mice and
scanners. USB supports both low (1.5 Mbs) and medium (12.5 Mbs) speeds, such
that keyboards and mice can use the low speed, while digital cameras and
printers needing faster throughput can use the higher speed.
USB may be implemented for communications activities, thereby allowing for
easy interconnecting of computers and telephony, including digital telephones,
modems and answering machines. USB enables new devices that were previously
unused in computers, such as digital cameras. As the connection of
communication systems and computers becomes more prevalent, USB will allow for
a consistent, well-defined peripheral development.
One significant benefit of USB is the USB standard, so that true "plug and
play" can be a reality. If a consumer buys a USB joystick or mouse, they can
plug it into their USB systems and immediately begin using it. This is
possible because USB peripherals are self-identifying. There is much less
cabling because all the peripherals can communicate on the same bus, instead
of each of them requiring its own cabling. This also allows for an expansion
in the number of peripherals possible, because more ports are made
available.
Another advantage is the ease of integration and design. Someone that
builds a lot of peripherals doesn't have to learn a new protocol for each one.
Although digital cameras and keyboards require different speeds, they can use
the same USB standard.
USB permits real-time data for audio and compressed video, as well as the
versatility to handle both periodic and irregular data transfers. Storage
FIFOs can be increased as needed for the application. USB will increase the
capabilities of the PC and greatly simplify the introduction of new
peripherals.
Up to 127 devices with bandwidths up to 12.5 Mbs, can be sustained by USB.
The same bundle of wires can manage multiple isochronous and asynchronous
transfers between the host and the peripheral devices.
More information on USB, including technical specs, can be found at the
Universal Serial Bus Implementers Forum web site at http://www.usb.org/.
|
|
|
|
|
| VFD: Vacuum Fluorescent Display |
|
|
The vacuum fluorescent display (VFD) module can directly drive VFD grids
and anodes.
|
|
|
|
|
| Package Options |
B: Plastic Shrink DIP (70 mil spacing)
DW: Small Outline
Integrated Circuit (Wide-Body SOIC)
FA: 7 x 7 mm Quad Flat Pack
(QFP)
FB: 10 x 10 mm Quad Flat Pack (QFP)
FE: Windowed
Ceramic Quad Flat Pack (CQFP) - Samples Only
FN: Plastic Leaded Chip
Carrier (PLCC)
FS: Windowed Ceramic Leaded Chip Carrier (CLCC) -
Samples Only
FT: 28 x 28 mm Quad Flat Pack (QFP)
FU: 14 x
14 mm Quad Flat Pack (QFP)
FZ: Windowed Ceramic Quad Flat Pack
(CQFP) - Samples Only
K: Windowed Ceramic Shrink DIP (cersdip) -
Samples Only
L: Ceramic Sidebraze DIP
P: Plastic DIP (100
mil spacing)
PU: 14 x 14 mm Thin Quad Flat Pack (TQFP)
PV:
20 x 20 mm Thin Quad Flat Pack (TQFP)
S: Windowed Ceramic DIP
(Cerdip) - Samples Only
|
|
|
