// Device Configuration: PF8100
// Customer: Horizon
// Program: Journey 3 Rereference board 
// Sample marking: SC33PF8100JCES
// Date: 2021/10/11
// Time: 16:03:00
// Generated from Spreadsheet Revision: 3.14
SET_DPIN:PF8100:PWRON:low
SET_DPIN:PF8100:WDI:low
SET_DPIN:PF8100:TBBEN:high
SET_REG:PF8100:OTP_MIRROR:OTP_FSOB_SELECT:0x07
SET_REG:PF8100:OTP_MIRROR:OTP_I2C:0x09
SET_REG:PF8100:OTP_MIRROR:OTP_CTRL1:0x02
SET_REG:PF8100:OTP_MIRROR:OTP_CTRL2:0x9D
SET_REG:PF8100:OTP_MIRROR:OTP_CTRL3:0x00
SET_REG:PF8100:OTP_MIRROR:OTP_FREQ_CTRL:0x80
SET_REG:PF8100:OTP_MIRROR:OTP_COINCELL_CTRL:0x0F
SET_REG:PF8100:OTP_MIRROR:OTP_PWRON:0x00
SET_REG:PF8100:OTP_MIRROR:OTP_WD_CONFIG:0x31
SET_REG:PF8100:OTP_MIRROR:OTP_WD_EXPIRE:0x07
SET_REG:PF8100:OTP_MIRROR:OTP_WD_COUNTER:0xAF
SET_REG:PF8100:OTP_MIRROR:OTP_FAULT_COUNTER:0x00
SET_REG:PF8100:OTP_MIRROR:OTP_FAULT_TIMERS:0x0F
SET_REG:PF8100:OTP_MIRROR:OTP_PWRDN_DLY1:0x55
SET_REG:PF8100:OTP_MIRROR:OTP_PWRDN_DLY2:0x82
SET_REG:PF8100:OTP_MIRROR:OTP_PWRUP_CTRL:0x42
SET_REG:PF8100:OTP_MIRROR:OTP_RESETBMCU_PWRUP:0x65
SET_REG:PF8100:OTP_MIRROR:OTP_PGOOD_PWRUP:0x00
SET_REG:PF8100:OTP_MIRROR:OTP_SW1_VOLT:0x40
SET_REG:PF8100:OTP_MIRROR:OTP_SW1_PWRUP:0x0A
SET_REG:PF8100:OTP_MIRROR:OTP_SW1_CONFIG1:0x5B
SET_REG:PF8100:OTP_MIRROR:OTP_SW1_CONFIG2:0x3A
SET_REG:PF8100:OTP_MIRROR:OTP_SW2_VOLT:0x40
SET_REG:PF8100:OTP_MIRROR:OTP_SW2_PWRUP:0x0A
SET_REG:PF8100:OTP_MIRROR:OTP_SW2_CONFIG1:0x5B
SET_REG:PF8100:OTP_MIRROR:OTP_SW2_CONFIG2:0x1A
SET_REG:PF8100:OTP_MIRROR:OTP_SW3_VOLT:0x40
SET_REG:PF8100:OTP_MIRROR:OTP_SW3_PWRUP:0x0E
SET_REG:PF8100:OTP_MIRROR:OTP_SW3_CONFIG1:0x5F
SET_REG:PF8100:OTP_MIRROR:OTP_SW3_CONFIG2:0x0A
SET_REG:PF8100:OTP_MIRROR:OTP_SW4_VOLT:0x40
SET_REG:PF8100:OTP_MIRROR:OTP_SW4_PWRUP:0x06
SET_REG:PF8100:OTP_MIRROR:OTP_SW4_CONFIG1:0x57
SET_REG:PF8100:OTP_MIRROR:OTP_SW4_CONFIG2:0x2A
SET_REG:PF8100:OTP_MIRROR:OTP_SW5_VOLT:0x40
SET_REG:PF8100:OTP_MIRROR:OTP_SW5_PWRUP:0x0A
SET_REG:PF8100:OTP_MIRROR:OTP_SW5_CONFIG1:0x5B
SET_REG:PF8100:OTP_MIRROR:OTP_SW5_CONFIG2:0x02
SET_REG:PF8100:OTP_MIRROR:OTP_SW6_VOLT:0x40
SET_REG:PF8100:OTP_MIRROR:OTP_SW6_PWRUP:0x0A
SET_REG:PF8100:OTP_MIRROR:OTP_SW6_CONFIG1:0x5B
SET_REG:PF8100:OTP_MIRROR:OTP_SW6_CONFIG2:0x12
SET_REG:PF8100:OTP_MIRROR:OTP_SW7_VOLT:0x08
SET_REG:PF8100:OTP_MIRROR:OTP_SW7_PWRUP:0x02
SET_REG:PF8100:OTP_MIRROR:OTP_SW7_CONFIG1:0x53
SET_REG:PF8100:OTP_MIRROR:OTP_SW7_CONFIG2:0x22
SET_REG:PF8100:OTP_MIRROR:OTP_LDO1_VOLT:0x5B
SET_REG:PF8100:OTP_MIRROR:OTP_LDO1_PWRUP:0x02
SET_REG:PF8100:OTP_MIRROR:OTP_LDO1_CONFIG:0x04
SET_REG:PF8100:OTP_MIRROR:OTP_LDO2_VOLT:0x5B
SET_REG:PF8100:OTP_MIRROR:OTP_LDO2_PWRUP:0x02
SET_REG:PF8100:OTP_MIRROR:OTP_LDO2_CONFIG:0x34
SET_REG:PF8100:OTP_MIRROR:OTP_LDO3_VOLT:0x5B
SET_REG:PF8100:OTP_MIRROR:OTP_LDO3_PWRUP:0x0E
SET_REG:PF8100:OTP_MIRROR:OTP_LDO3_CONFIG:0xC4
SET_REG:PF8100:OTP_MIRROR:OTP_LDO4_VOLT:0x52
SET_REG:PF8100:OTP_MIRROR:OTP_LDO4_PWRUP:0x0E
SET_REG:PF8100:OTP_MIRROR:OTP_LDO4_CONFIG:0xC4
SET_REG:PF8100:OTP_MIRROR:OTP_VSNVS_CONFIG:0x00
SET_REG:PF8100:OTP_MIRROR:OTP_OV_BYPASS1:0x00
SET_REG:PF8100:OTP_MIRROR:OTP_OV_BYPASS2:0x00
SET_REG:PF8100:OTP_MIRROR:OTP_UV_BYPASS1:0x00
SET_REG:PF8100:OTP_MIRROR:OTP_UV_BYPASS2:0x00
SET_REG:PF8100:OTP_MIRROR:OTP_ILIM_BYPASS1:0x00
SET_REG:PF8100:OTP_MIRROR:OTP_ILIM_BYPASS2:0x00
SET_REG:PF8100:OTP_MIRROR:OTP_PROG_IDH:0x08
SET_REG:PF8100:OTP_MIRROR:OTP_PROG_IDL:0x8C
SET_REG:PF8100:OTP_MIRROR:OTP_DEBUG1:0x00
SET_REG:PF8100:OTP_MIRROR:OTP_SW_COMP1:0x00
SET_REG:PF8100:OTP_MIRROR:OTP_SW_COMP2:0x00
SET_REG:PF8100:OTP_MIRROR:OTP_SW_COMP3:0x00
SET_DPIN:PF8100:TBBEN:low
SET_DPIN:PF8100:PWRON:high
