/*!
  \page AD1 AD1 (ADC_LDD)
**         This device "ADC_LDD" implements an A/D converter,
**         its control methods and interrupt/event handling procedure.
**

- \subpage AD1_settings
- \subpage AD1_regs_overview  
- \subpage AD1_regs_details
- \ref AD1_module "Component documentation" 
\page AD1_regs_overview Registers Initialization Overview
This page contains the initialization values for the registers of the peripheral(s) configured
by the component. 
<table>
<tr><td colspan="4" class="ttitle1">AD1 Initialization</td></tr>
<tr><td class="ttitle2">Address</td><td class="ttitle2">Register</td><td class="ttitle2">Register Value</td><td class="ttitle2">Register Description</td></tr>
<tr><td>0x4003C000</td><td>ADC1_SC1A</td>
<td class="regNotResetVal">0x0000000B</td>
 <td>ADC1_SC1A register, peripheral AD1.</td></tr>
<tr><td>0x4004803C</td><td>SIM_SCGC6</td>
<td class="regNotResetVal">0x10001001</td>
 <td>SIM_SCGC6 register, peripheral AD1.</td></tr>
<tr><td>0x40048038</td><td>SIM_SCGC5</td>
<td class="regNotResetVal">0x00041980</td>
 <td>SIM_SCGC5 register, peripheral AD1.</td></tr>
<tr><td>0x4004B000</td><td>PORTC_PCR0</td>
<td class="regResetVal">0x00000001</td>
 <td>PORTC_PCR0 register, peripheral AD1.</td></tr>
<tr><td>0x4003C020</td><td>ADC1_SC2</td>
<td class="regResetVal">0x00000000</td>
 <td>ADC1_SC2 register, peripheral AD1.</td></tr>
<tr><td>0x4003C008</td><td>ADC1_CFG1</td>
<td class="regNotResetVal">0x0000004C</td>
 <td>ADC1_CFG1 register, peripheral AD1.</td></tr>
<tr><td>0x4003C00C</td><td>ADC1_CFG2</td>
<td class="regResetVal">0x00000000</td>
 <td>ADC1_CFG2 register, peripheral AD1.</td></tr>
<tr><td>0x4003C024</td><td>ADC1_SC3</td>
<td class="regNotResetVal">0x00000040</td>
 <td>ADC1_SC3 register, peripheral AD1.</td></tr>
</table>
Color Denotes Reset Value
<br/>
\page AD1_regs_details Register Initialization Details
This page contains detailed description of initialization values for the 
registers of the peripheral(s) configured by the component. 

<div class="reghdr1">ADC1_SC1A</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="1">COCO</td>
<td colspan="1" rowspan="2">AIEN</td><td colspan="1" rowspan="2">DIFF</td><td colspan="5" rowspan="2">ADCH</td>
</tr>
<tr>
<td class="trd1c">W</td>
<td colspan="1"></td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x4003C000</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x0000000B</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x0000001F</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>7</td><td>COCO</td><td>0x00</td><td>Conversion Complete Flag</td>
<tr><td>6</td><td>AIEN</td><td>0x00</td><td>Interrupt Enable</td>
<tr><td>5</td><td>DIFF</td><td>0x00</td><td>Differential Mode Enable</td>
<tr><td>0 - 4</td><td>ADCH</td><td>0x00</td><td>Input channel select</td>
</tr></table>
<div class="reghdr1">SIM_SCGC6</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">DAC0</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">ADC1</td><td colspan="1" rowspan="2">ADC0</td>
<td colspan="1" rowspan="2">FTM2</td><td colspan="1" rowspan="2">FTM1</td><td colspan="1" rowspan="2">FTM0</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">PDB</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">CRC</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">SPI0</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">DMAMUX</td>
<td colspan="1" rowspan="2">FTF</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x4004803C</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x10001001</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00000001</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>31</td><td>DAC0</td><td>0x00</td><td>DAC0 Clock Gate Control</td>
<tr><td>28</td><td>ADC1</td><td>0x01</td><td>ADC1 Clock Gate Control</td>
<tr><td>27</td><td>ADC0</td><td>0x00</td><td>ADC0 Clock Gate Control</td>
<tr><td>26</td><td>FTM2</td><td>0x00</td><td>FTM2 Clock Gate Control</td>
<tr><td>25</td><td>FTM1</td><td>0x00</td><td>FTM1 Clock Gate Control</td>
<tr><td>24</td><td>FTM0</td><td>0x00</td><td>FTM0 Clock Gate Control</td>
<tr><td>22</td><td>PDB</td><td>0x00</td><td>PDB Clock Gate Control</td>
<tr><td>18</td><td>CRC</td><td>0x00</td><td>CRC Clock Gate Control</td>
<tr><td>12</td><td>SPI0</td><td>0x01</td><td>SPI0 Clock Gate Control</td>
<tr><td>1</td><td>DMAMUX</td><td>0x00</td><td>DMA Mux Clock Gate Control</td>
<tr><td>0</td><td>FTF</td><td>0x01</td><td>Flash Memory Clock Gate Control</td>
</tr></table>
<div class="reghdr1">SIM_SCGC5</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">PORTE</td><td colspan="1" rowspan="2">PORTD</td><td colspan="1" rowspan="2">PORTC</td>
<td colspan="1" rowspan="2">PORTB</td><td colspan="1" rowspan="2">PORTA</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">LPTMR</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x40048038</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x00041980</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00040180</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>13</td><td>PORTE</td><td>0x00</td><td>Port E Clock Gate Control</td>
<tr><td>12</td><td>PORTD</td><td>0x01</td><td>Port D Clock Gate Control</td>
<tr><td>11</td><td>PORTC</td><td>0x01</td><td>Port C Clock Gate Control</td>
<tr><td>10</td><td>PORTB</td><td>0x00</td><td>Port B Clock Gate Control</td>
<tr><td>9</td><td>PORTA</td><td>0x00</td><td>Port A Clock Gate Control</td>
<tr><td>0</td><td>LPTMR</td><td>0x00</td><td>Low Power Timer Clock Gate Control</td>
</tr></table>
<div class="reghdr1">PORTC_PCR0</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">ISF</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="4" rowspan="2">IRQC</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="3" rowspan="2">MUX</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">DSE</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">PFE</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">SRE</td>
<td colspan="1" rowspan="2">PE</td><td colspan="1" rowspan="2">PS</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x4004B000</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x00000001</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00000001</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>24</td><td>ISF</td><td>0x00</td><td>Interrupt Status Flag</td>
<tr><td>16 - 19</td><td>IRQC</td><td>0x00</td><td>Interrupt Configuration</td>
<tr><td>8 - 10</td><td>MUX</td><td>0x00</td><td>Pin Mux Control</td>
<tr><td>6</td><td>DSE</td><td>0x00</td><td>Drive Strength Enable</td>
<tr><td>4</td><td>PFE</td><td>0x00</td><td>Passive Filter Enable</td>
<tr><td>2</td><td>SRE</td><td>0x00</td><td>Slew Rate Enable</td>
<tr><td>1</td><td>PE</td><td>0x00</td><td>Pull Enable</td>
<tr><td>0</td><td>PS</td><td>0x01</td><td>Pull Select</td>
</tr></table>
<div class="reghdr1">ADC1_SC2</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="1">ADACT</td>
<td colspan="1" rowspan="2">ADTRG</td><td colspan="1" rowspan="2">ACFE</td><td colspan="1" rowspan="2">ACFGT</td>
<td colspan="1" rowspan="2">ACREN</td><td colspan="1" rowspan="2">DMAEN</td><td colspan="2" rowspan="2">REFSEL</td>
</tr>
<tr>
<td class="trd1c">W</td>
<td colspan="1"></td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x4003C020</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x00000000</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00000000</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>7</td><td>ADACT</td><td>0x00</td><td>Conversion Active</td>
<tr><td>6</td><td>ADTRG</td><td>0x00</td><td>Conversion Trigger Select</td>
<tr><td>5</td><td>ACFE</td><td>0x00</td><td>Compare Function Enable</td>
<tr><td>4</td><td>ACFGT</td><td>0x00</td><td>Compare Function Greater Than Enable</td>
<tr><td>3</td><td>ACREN</td><td>0x00</td><td>Compare Function Range Enable</td>
<tr><td>2</td><td>DMAEN</td><td>0x00</td><td>DMA Enable</td>
<tr><td>0 - 1</td><td>REFSEL</td><td>0x00</td><td>Voltage Reference Selection</td>
</tr></table>
<div class="reghdr1">ADC1_CFG1</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">ADLPC</td>
<td colspan="2" rowspan="2">ADIV</td><td colspan="1" rowspan="2">ADLSMP</td><td colspan="2" rowspan="2">MODE</td>
<td colspan="2" rowspan="2">ADICLK</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x4003C008</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x0000004C</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00000000</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>7</td><td>ADLPC</td><td>0x00</td><td>Low-Power Configuration</td>
<tr><td>5 - 6</td><td>ADIV</td><td>0x02</td><td>Clock Divide Select</td>
<tr><td>4</td><td>ADLSMP</td><td>0x00</td><td>Sample Time Configuration</td>
<tr><td>2 - 3</td><td>MODE</td><td>0x02</td><td>Conversion mode selection</td>
<tr><td>0 - 1</td><td>ADICLK</td><td>0x00</td><td>Input Clock Select</td>
</tr></table>
<div class="reghdr1">ADC1_CFG2</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">MUXSEL</td>
<td colspan="1" rowspan="2">ADACKEN</td><td colspan="1" rowspan="2">ADHSC</td><td colspan="2" rowspan="2">ADLSTS</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x4003C00C</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x00000000</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00000000</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>4</td><td>MUXSEL</td><td>0x00</td><td>ADC Mux Select</td>
<tr><td>3</td><td>ADACKEN</td><td>0x00</td><td>Asynchronous Clock Output Enable</td>
<tr><td>2</td><td>ADHSC</td><td>0x00</td><td>High-Speed Configuration</td>
<tr><td>0 - 1</td><td>ADLSTS</td><td>0x00</td><td>Long Sample Time Select</td>
</tr></table>
<div class="reghdr1">ADC1_SC3</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">CAL</td>
<td colspan="1" rowspan="2">CALF</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">ADCO</td><td colspan="1" rowspan="2">AVGE</td><td colspan="2" rowspan="2">AVGS</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x4003C024</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x00000040</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00000000</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>7</td><td>CAL</td><td>0x00</td><td>Calibration</td>
<tr><td>6</td><td>CALF</td><td>0x01</td><td>Calibration Failed Flag</td>
<tr><td>3</td><td>ADCO</td><td>0x00</td><td>Continuous Conversion Enable</td>
<tr><td>2</td><td>AVGE</td><td>0x00</td><td>Hardware Average Enable</td>
<tr><td>0 - 1</td><td>AVGS</td><td>0x00</td><td>Hardware Average Select</td>
</tr></table>
*/
/*!
\page AD1_settings Component Settings
\code
**          Component name                                 : AD1
**          A/D converter                                  : ADC1
**          Discontinuous mode                             : no
**          Interrupt service/event                        : Disabled
**          DMA                                            : Disabled
**          A/D channel list                               : 1
**            Channel 0                                    : 
**              Channel mode                               : Single Ended
**                Input                                    : 
**                  A/D channel (pin)                      : ADC1_SE11/PTC0/SPI0_PCS4/PDB0_EXTRG/CMP0_OUT/FTM0_FLT0/SPI0_PCS0/SS_b
**          Static sample groups                           : Enabled
**            Sample group list                            : 1
**              Group 0                                    : 
**                Sample list                              : 1
**                  Sample 0                               : Enabled
**                    Channel index                        : 0
**          Max. samples                                   : 8
**          A/D resolution                                 : Autoselect
**          Low-power mode                                 : Disabled
**          High-speed conversion mode                     : Disabled
**          Asynchro clock output                          : Disabled
**          Sample time                                    : 4 clock periods
**          Number of conversions                          : 1
**          Conversion time                                : 4.768372 µs
**          ADC clock                                      : 5.242 MHz (190.735 ns)
**          Single conversion time - Single-ended          : 5.96 us
**          Single conversion time - Differential          : 7.677 us
**          Additional conversion time - Single-ended      : 4.768 us
**          Additional conversion time - Differential      : 6.484 us
**          Result type                                    : unsigned 16 bits, right justified
**          Trigger                                        : Disabled
**          Voltage reference                              : 
**            High voltage reference                       : 
**              Volt. ref. pin                             : VREFH
**            Low voltage reference                        : 
**              Volt. ref. pin                             : VREFL
**          Initialization                                 : 
**            Enabled in init. code                        : yes
**            Auto initialization                          : yes
**            Event mask                                   : 
**              OnMeasurementComplete                      : Disabled
**              OnError                                    : Disabled
**          CPU clock/configuration selection              : 
**            Clock configuration 0                        : This component enabled
**            Clock configuration 1                        : This component disabled
**            Clock configuration 2                        : This component disabled
**            Clock configuration 3                        : This component disabled
**            Clock configuration 4                        : This component disabled
**            Clock configuration 5                        : This component disabled
**            Clock configuration 6                        : This component disabled
**            Clock configuration 7                        : This component disabled
<h1>
\endcode
*/
