/*!
  \page SM1 SM1 (SPIMaster_LDD)
**         This component "SPIMaster_LDD" implements MASTER part of synchronous
**         serial master-slave communication.
**

- \subpage SM1_settings
- \subpage SM1_regs_overview  
- \subpage SM1_regs_details
- \ref SM1_module "Component documentation" 
\page SM1_regs_overview Registers Initialization Overview
This page contains the initialization values for the registers of the peripheral(s) configured
by the component. 
<table>
<tr><td colspan="4" class="ttitle1">SM1 Initialization</td></tr>
<tr><td class="ttitle2">Address</td><td class="ttitle2">Register</td><td class="ttitle2">Register Value</td><td class="ttitle2">Register Description</td></tr>
<tr><td>0x4004803C</td><td>SIM_SCGC6</td>
<td class="regNotResetVal">0x40001001</td>
 <td>SIM_SCGC6 register, peripheral SM1.</td></tr>
<tr><td>0xE000E41A</td><td>NVICIP26</td>
<td class="regNotResetVal">0x00000070</td>
 <td>NVICIP26 register, peripheral SM1.</td></tr>
<tr><td>0xE000E100</td><td>NVICISER0</td>
<td class="regNotResetVal">0x04000000</td>
 <td>NVICISER0 register, peripheral SM1.</td></tr>
<tr><td>0x40048038</td><td>SIM_SCGC5</td>
<td class="regNotResetVal">0x00041182</td>
 <td>SIM_SCGC5 register, peripheral SM1.</td></tr>
<tr><td>0x4004C00C</td><td>PORTD_PCR3</td>
<td class="regNotResetVal">0x00000204</td>
 <td>PORTD_PCR3 register, peripheral SM1.</td></tr>
<tr><td>0x4004C008</td><td>PORTD_PCR2</td>
<td class="regNotResetVal">0x00000204</td>
 <td>PORTD_PCR2 register, peripheral SM1.</td></tr>
<tr><td>0x4004C004</td><td>PORTD_PCR1</td>
<td class="regNotResetVal">0x00000204</td>
 <td>PORTD_PCR1 register, peripheral SM1.</td></tr>
<tr><td>0x4002C000</td><td>SPI0_MCR</td>
<td class="regNotResetVal">0x81003C01</td>
 <td>SPI0_MCR register, peripheral SM1.</td></tr>
<tr><td>0x4002C00C</td><td>SPI0_CTAR0</td>
<td class="regNotResetVal">0xBA570001</td>
 <td>SPI0_CTAR0 register, peripheral SM1.</td></tr>
<tr><td>0x4002C02C</td><td>SPI0_SR</td>
<td class="regNotResetVal">0x9A2A0000</td>
 <td>SPI0_SR register, peripheral SM1.</td></tr>
<tr><td>0x4002C030</td><td>SPI0_RSER</td>
<td class="regNotResetVal">0x00020000</td>
 <td>SPI0_RSER register, peripheral SM1.</td></tr>
</table>
Color Denotes Reset Value
<br/>
\page SM1_regs_details Register Initialization Details
This page contains detailed description of initialization values for the 
registers of the peripheral(s) configured by the component. 

<div class="reghdr1">SIM_SCGC6</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">DAC0</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">RTC</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">ADC0</td>
<td colspan="1" rowspan="2">FTM2</td><td colspan="1" rowspan="2">FTM1</td><td colspan="1" rowspan="2">FTM0</td>
<td colspan="1" rowspan="2">PIT</td><td colspan="1" rowspan="2">PDB</td><td colspan="1" rowspan="2">USBDCD</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">CRC</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">I2S</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">SPI1</td><td colspan="1" rowspan="2">SPI0</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">RNGA</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">FLEXCAN0</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">DMAMUX</td><td colspan="1" rowspan="2">FTF</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x4004803C</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x40001001</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x40000001</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>31</td><td>DAC0</td><td>0x00</td><td>DAC0 Clock Gate Control</td>
<tr><td>29</td><td>RTC</td><td>0x00</td><td>RTC Access Control</td>
<tr><td>27</td><td>ADC0</td><td>0x00</td><td>ADC0 Clock Gate Control</td>
<tr><td>26</td><td>FTM2</td><td>0x00</td><td>FTM2 Clock Gate Control</td>
<tr><td>25</td><td>FTM1</td><td>0x00</td><td>FTM1 Clock Gate Control</td>
<tr><td>24</td><td>FTM0</td><td>0x00</td><td>FTM0 Clock Gate Control</td>
<tr><td>23</td><td>PIT</td><td>0x00</td><td>PIT Clock Gate Control</td>
<tr><td>22</td><td>PDB</td><td>0x00</td><td>PDB Clock Gate Control</td>
<tr><td>21</td><td>USBDCD</td><td>0x00</td><td>USB DCD Clock Gate Control</td>
<tr><td>18</td><td>CRC</td><td>0x00</td><td>CRC Clock Gate Control</td>
<tr><td>15</td><td>I2S</td><td>0x00</td><td>I2S Clock Gate Control</td>
<tr><td>13</td><td>SPI1</td><td>0x00</td><td>SPI1 Clock Gate Control</td>
<tr><td>12</td><td>SPI0</td><td>0x01</td><td>SPI0 Clock Gate Control</td>
<tr><td>9</td><td>RNGA</td><td>0x00</td><td>RNGA Clock Gate Control</td>
<tr><td>4</td><td>FLEXCAN0</td><td>0x00</td><td>FlexCAN0 Clock Gate Control</td>
<tr><td>1</td><td>DMAMUX</td><td>0x00</td><td>DMA Mux Clock Gate Control</td>
<tr><td>0</td><td>FTF</td><td>0x01</td><td>Flash Memory Clock Gate Control</td>
</tr></table>
<div class="reghdr1">NVICIP26</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="8" rowspan="2">PRI26</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0xE000E41A</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x00000070</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00000000</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>0 - 7</td><td>PRI26</td><td>0x00</td><td>Priority of interrupt 26</td>
</tr></table>
<div class="reghdr1">NVICISER0</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="16" rowspan="2">SETENA</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="32" rowspan="2">SETENA</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0xE000E100</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x04000000</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00000000</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>0 - 31</td><td>SETENA</td><td>0x00</td><td>Interrupt set enable bits</td>
</tr></table>
<div class="reghdr1">SIM_SCGC5</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">PORTE</td><td colspan="1" rowspan="2">PORTD</td><td colspan="1" rowspan="2">PORTC</td>
<td colspan="1" rowspan="2">PORTB</td><td colspan="1" rowspan="2">PORTA</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">LPTMR</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x40048038</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x00041182</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00040182</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>13</td><td>PORTE</td><td>0x00</td><td>Port E Clock Gate Control</td>
<tr><td>12</td><td>PORTD</td><td>0x01</td><td>Port D Clock Gate Control</td>
<tr><td>11</td><td>PORTC</td><td>0x00</td><td>Port C Clock Gate Control</td>
<tr><td>10</td><td>PORTB</td><td>0x00</td><td>Port B Clock Gate Control</td>
<tr><td>9</td><td>PORTA</td><td>0x00</td><td>Port A Clock Gate Control</td>
<tr><td>0</td><td>LPTMR</td><td>0x00</td><td>Low Power Timer Access Control</td>
</tr></table>
<div class="reghdr1">PORTD_PCR3</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">ISF</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="4" rowspan="2">IRQC</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">LK</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="3" rowspan="2">MUX</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">DSE</td><td colspan="1" rowspan="2">ODE</td>
<td colspan="1" rowspan="2">PFE</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">SRE</td>
<td colspan="1" rowspan="2">PE</td><td colspan="1" rowspan="2">PS</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x4004C00C</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x00000204</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00000004</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>24</td><td>ISF</td><td>0x00</td><td>Interrupt Status Flag</td>
<tr><td>16 - 19</td><td>IRQC</td><td>0x00</td><td>Interrupt Configuration</td>
<tr><td>15</td><td>LK</td><td>0x00</td><td>Lock Register</td>
<tr><td>8 - 10</td><td>MUX</td><td>0x00</td><td>Pin Mux Control</td>
<tr><td>6</td><td>DSE</td><td>0x00</td><td>Drive Strength Enable</td>
<tr><td>5</td><td>ODE</td><td>0x00</td><td>Open Drain Enable</td>
<tr><td>4</td><td>PFE</td><td>0x00</td><td>Passive Filter Enable</td>
<tr><td>2</td><td>SRE</td><td>0x01</td><td>Slew Rate Enable</td>
<tr><td>1</td><td>PE</td><td>0x00</td><td>Pull Enable</td>
<tr><td>0</td><td>PS</td><td>0x00</td><td>Pull Select</td>
</tr></table>
<div class="reghdr1">PORTD_PCR2</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">ISF</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="4" rowspan="2">IRQC</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">LK</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="3" rowspan="2">MUX</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">DSE</td><td colspan="1" rowspan="2">ODE</td>
<td colspan="1" rowspan="2">PFE</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">SRE</td>
<td colspan="1" rowspan="2">PE</td><td colspan="1" rowspan="2">PS</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x4004C008</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x00000204</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00000004</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>24</td><td>ISF</td><td>0x00</td><td>Interrupt Status Flag</td>
<tr><td>16 - 19</td><td>IRQC</td><td>0x00</td><td>Interrupt Configuration</td>
<tr><td>15</td><td>LK</td><td>0x00</td><td>Lock Register</td>
<tr><td>8 - 10</td><td>MUX</td><td>0x00</td><td>Pin Mux Control</td>
<tr><td>6</td><td>DSE</td><td>0x00</td><td>Drive Strength Enable</td>
<tr><td>5</td><td>ODE</td><td>0x00</td><td>Open Drain Enable</td>
<tr><td>4</td><td>PFE</td><td>0x00</td><td>Passive Filter Enable</td>
<tr><td>2</td><td>SRE</td><td>0x01</td><td>Slew Rate Enable</td>
<tr><td>1</td><td>PE</td><td>0x00</td><td>Pull Enable</td>
<tr><td>0</td><td>PS</td><td>0x00</td><td>Pull Select</td>
</tr></table>
<div class="reghdr1">PORTD_PCR1</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">ISF</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="4" rowspan="2">IRQC</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">LK</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="3" rowspan="2">MUX</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">DSE</td><td colspan="1" rowspan="2">ODE</td>
<td colspan="1" rowspan="2">PFE</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">SRE</td>
<td colspan="1" rowspan="2">PE</td><td colspan="1" rowspan="2">PS</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x4004C004</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x00000204</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00000004</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>24</td><td>ISF</td><td>0x00</td><td>Interrupt Status Flag</td>
<tr><td>16 - 19</td><td>IRQC</td><td>0x00</td><td>Interrupt Configuration</td>
<tr><td>15</td><td>LK</td><td>0x00</td><td>Lock Register</td>
<tr><td>8 - 10</td><td>MUX</td><td>0x00</td><td>Pin Mux Control</td>
<tr><td>6</td><td>DSE</td><td>0x00</td><td>Drive Strength Enable</td>
<tr><td>5</td><td>ODE</td><td>0x00</td><td>Open Drain Enable</td>
<tr><td>4</td><td>PFE</td><td>0x00</td><td>Passive Filter Enable</td>
<tr><td>2</td><td>SRE</td><td>0x01</td><td>Slew Rate Enable</td>
<tr><td>1</td><td>PE</td><td>0x00</td><td>Pull Enable</td>
<tr><td>0</td><td>PS</td><td>0x00</td><td>Pull Select</td>
</tr></table>
<div class="reghdr1">SPI0_MCR</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">MSTR</td><td colspan="1" rowspan="2">CONT_SCKE</td>
<td colspan="2" rowspan="1">DCONF</td><td colspan="1" rowspan="2">FRZ</td><td colspan="1" rowspan="2">MTFE</td>
<td colspan="1" rowspan="2">PCSSE</td><td colspan="1" rowspan="2">ROOE</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="6" rowspan="2">PCSIS</td>
</tr>
<tr>
<td class="trd1c">W</td>
<td colspan="2"></td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">DOZE</td><td colspan="1" rowspan="2">MDIS</td>
<td colspan="1" rowspan="2">DIS_TXF</td><td colspan="1" rowspan="2">DIS_RXF</td><td colspan="1"></td><td colspan="1"></td>
<td colspan="2" rowspan="2">SMPL_PT</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">HALT</td>
</tr>
<tr>
<td class="trd1c">W</td>
<td colspan="1">CLR_TXF</td><td colspan="1">CLR_RXF</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x4002C000</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x81003C01</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00004001</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>31</td><td>MSTR</td><td>0x01</td><td>Master/Slave Mode Select</td>
<tr><td>30</td><td>CONT_SCKE</td><td>0x00</td><td>Continuous SCK Enable</td>
<tr><td>28 - 29</td><td>DCONF</td><td>0x00</td><td>SPI Configuration</td>
<tr><td>27</td><td>FRZ</td><td>0x00</td><td>Freeze</td>
<tr><td>26</td><td>MTFE</td><td>0x00</td><td>Modified Timing Format Enable</td>
<tr><td>25</td><td>PCSSE</td><td>0x00</td><td>Peripheral Chip Select Strobe Enable</td>
<tr><td>24</td><td>ROOE</td><td>0x01</td><td>Receive FIFO Overflow Overwrite Enable</td>
<tr><td>16 - 21</td><td>PCSIS</td><td>0x00</td><td>Peripheral Chip Select x Inactive State</td>
<tr><td>15</td><td>DOZE</td><td>0x00</td><td>Doze Enable</td>
<tr><td>14</td><td>MDIS</td><td>0x00</td><td>Module Disable</td>
<tr><td>13</td><td>DIS_TXF</td><td>0x01</td><td>Disable Transmit FIFO</td>
<tr><td>12</td><td>DIS_RXF</td><td>0x01</td><td>Disable Receive FIFO</td>
<tr><td>11</td><td>CLR_TXF</td><td>0x01</td><td>Clear TX FIFO</td>
<tr><td>10</td><td>CLR_RXF</td><td>0x01</td><td>Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The CLR_RXF bit is always read as zero</td>
<tr><td>8 - 9</td><td>SMPL_PT</td><td>0x00</td><td>Sample Point</td>
<tr><td>0</td><td>HALT</td><td>0x01</td><td>Halt</td>
</tr></table>
<div class="reghdr1">SPI0_CTAR0</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">DBR</td><td colspan="4" rowspan="2">FMSZ</td>
<td colspan="1" rowspan="2">CPOL</td><td colspan="1" rowspan="2">CPHA</td><td colspan="1" rowspan="2">LSBFE</td>
<td colspan="2" rowspan="2">PCSSCK</td><td colspan="2" rowspan="2">PASC</td><td colspan="2" rowspan="2">PDT</td>
<td colspan="2" rowspan="2">PBR</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="4" rowspan="2">CSSCK</td><td colspan="4" rowspan="2">ASC</td>
<td colspan="4" rowspan="2">DT</td><td colspan="4" rowspan="2">BR</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x4002C00C</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0xBA570001</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x78000000</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>31</td><td>DBR</td><td>0x01</td><td>Double Baud Rate</td>
<tr><td>27 - 30</td><td>FMSZ</td><td>0x00</td><td>Frame Size</td>
<tr><td>26</td><td>CPOL</td><td>0x00</td><td>Clock Polarity</td>
<tr><td>25</td><td>CPHA</td><td>0x01</td><td>Clock Phase</td>
<tr><td>24</td><td>LSBFE</td><td>0x00</td><td>LSB First</td>
<tr><td>22 - 23</td><td>PCSSCK</td><td>0x00</td><td>PCS to SCK Delay Prescaler</td>
<tr><td>20 - 21</td><td>PASC</td><td>0x00</td><td>After SCK Delay Prescaler</td>
<tr><td>18 - 19</td><td>PDT</td><td>0x00</td><td>Delay after Transfer Prescaler</td>
<tr><td>16 - 17</td><td>PBR</td><td>0x02</td><td>Baud Rate Prescaler</td>
<tr><td>12 - 15</td><td>CSSCK</td><td>0x00</td><td>PCS to SCK Delay Scaler</td>
<tr><td>8 - 11</td><td>ASC</td><td>0x00</td><td>After SCK Delay Scaler</td>
<tr><td>4 - 7</td><td>DT</td><td>0x00</td><td>Delay After Transfer Scaler</td>
<tr><td>0 - 3</td><td>BR</td><td>0x00</td><td>Baud Rate Scaler</td>
</tr></table>
<div class="reghdr1">SPI0_SR</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">TCF</td><td colspan="1" rowspan="2">TXRXS</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">EOQF</td><td colspan="1" rowspan="2">TFUF</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">TFFF</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">RFOF</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">RFDF</td><td colspan="1" rowspan="2">-</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="4" rowspan="1">TXCTR</td><td colspan="4" rowspan="1">TXNXTPTR</td>
<td colspan="4" rowspan="1">RXCTR</td><td colspan="4" rowspan="1">POPNXTPTR</td>
</tr>
<tr>
<td class="trd1c">W</td>
<td colspan="4"></td><td colspan="4"></td><td colspan="4"></td><td colspan="4"></td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x4002C02C</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x9A2A0000</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x02000000</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>31</td><td>TCF</td><td>0x01</td><td>Transfer Complete Flag</td>
<tr><td>30</td><td>TXRXS</td><td>0x00</td><td>TX and RX Status</td>
<tr><td>28</td><td>EOQF</td><td>0x01</td><td>End of Queue Flag</td>
<tr><td>27</td><td>TFUF</td><td>0x01</td><td>Transmit FIFO Underflow Flag</td>
<tr><td>25</td><td>TFFF</td><td>0x01</td><td>Transmit FIFO Fill Flag</td>
<tr><td>19</td><td>RFOF</td><td>0x01</td><td>Receive FIFO Overflow Flag</td>
<tr><td>17</td><td>RFDF</td><td>0x01</td><td>Receive FIFO Drain Flag</td>
<tr><td>12 - 15</td><td>TXCTR</td><td>0x00</td><td>TX FIFO Counter</td>
<tr><td>8 - 11</td><td>TXNXTPTR</td><td>0x00</td><td>Transmit Next Pointer</td>
<tr><td>4 - 7</td><td>RXCTR</td><td>0x00</td><td>RX FIFO Counter</td>
<tr><td>0 - 3</td><td>POPNXTPTR</td><td>0x00</td><td>Pop Next Pointer</td>
</tr></table>
<div class="reghdr1">SPI0_RSER</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">TCF_RE</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">EOQF_RE</td><td colspan="1" rowspan="2">TFUF_RE</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">TFFF_RE</td><td colspan="1" rowspan="2">TFFF_DIRS</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">RFOF_RE</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">RFDF_RE</td><td colspan="1" rowspan="2">RFDF_DIRS</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x4002C030</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x00020000</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00000000</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>31</td><td>TCF_RE</td><td>0x00</td><td>Transmission Complete Request Enable</td>
<tr><td>28</td><td>EOQF_RE</td><td>0x00</td><td>Finished Request Enable</td>
<tr><td>27</td><td>TFUF_RE</td><td>0x00</td><td>Transmit FIFO Underflow Request Enable</td>
<tr><td>25</td><td>TFFF_RE</td><td>0x00</td><td>Transmit FIFO Fill Request Enable</td>
<tr><td>24</td><td>TFFF_DIRS</td><td>0x00</td><td>Transmit FIFO Fill DMA or Interrupt Request Select</td>
<tr><td>19</td><td>RFOF_RE</td><td>0x00</td><td>Receive FIFO Overflow Request Enable</td>
<tr><td>17</td><td>RFDF_RE</td><td>0x01</td><td>Receive FIFO Drain Request Enable</td>
<tr><td>16</td><td>RFDF_DIRS</td><td>0x00</td><td>Receive FIFO Drain DMA or Interrupt Request Select</td>
</tr></table>
*/
/*!
\page SM1_settings Component Settings
\code
**          Component name                                 : SM1
**          Device                                         : SPI0
**          Interrupt service/event                        : Enabled
**            Input interrupt                              : INT_SPI0
**            Input interrupt priority                     : medium priority
**            Output interrupt                             : INT_SPI0
**            Output interrupt priority                    : medium priority
**          Settings                                       : 
**            Input pin                                    : Enabled
**              Pin                                        : PTD3/SPI0_SIN/UART2_TX/FTM3_CH3/FB_AD3/I2C0_SDA
**            Output pin                                   : Enabled
**              Pin                                        : PTD2/LLWU_P13/SPI0_SOUT/UART2_RX/FTM3_CH2/FB_AD4/I2C0_SCL
**            Clock pin                                    : 
**              Pin                                        : ADC0_SE5b/PTD1/SPI0_SCK/UART2_CTS_b/FTM3_CH1/FB_CS0_b
**            Chip select list                             : 0
**            CS external demultiplexer                    : Disabled
**            Attribute set list                           : 1
**              Attribute set 0                            : 
**                Width                                    : 8 bits
**                MSB first                                : yes
**                Clock polarity                           : Low
**                Clock phase                              : Change on leading edge
**                Parity                                   : None
**                Chip select toggling                     : no
**                Clock rate index                         : 0
**                Delay after transfer index               : 0
**                CS to CLK delay index                    : 0
**                CLK to CS delay index                    : 0
**            Clock rate                                   : 0.667572 µs
**            Delay after transfer                         : 0.286102 µs
**            CS to CLK delay                              : 0.286102 µs
**            CLK to CS delay                              : 0.286102 µs
**            HW input buffer size                         : 1
**            HW input watermark                           : 1
**            HW output buffer size                        : 1
**            HW output watermark                          : 1
**          Initialization                                 : 
**            Initial chip select                          : 0
**            Initial attribute set                        : 0
**            Enabled in init. code                        : yes
**            Auto initialization                          : yes
**            Event mask                                   : 
**              OnBlockSent                                : Enabled
**              OnBlockReceived                            : Enabled
**              OnError                                    : Disabled
**          CPU clock/configuration selection              : 
**            Clock configuration 0                        : This component enabled
**            Clock configuration 1                        : This component disabled
**            Clock configuration 2                        : This component disabled
**            Clock configuration 3                        : This component disabled
**            Clock configuration 4                        : This component disabled
**            Clock configuration 5                        : This component disabled
**            Clock configuration 6                        : This component disabled
**            Clock configuration 7                        : This component disabled
<h1>
\endcode
*/
