/* ###################################################################
**     This component module is generated by Processor Expert. Do not modify it.
**     Filename    : PWMB.c
**     Project     : MAPS-MC-2IN1_DualServo_release
**     Processor   : MC56F84789VLL
**     Component   : Init_eFlexPWM
**     Version     : Component 01.000, Driver 01.00, CPU db: 3.50.001
**     Compiler    : CodeWarrior DSP C Compiler
**     Date/Time   : 2019-04-03, 17:51, # CodeGen: 0
**     Abstract    :
**          This file implements the eFlexPWM (PWMB) module initialization
**          according to the Peripheral Initialization settings, and
**          defines interrupt service routines prototypes.
**     Settings    :
**          Component name                                 : PWMB
**          Device                                         : PWMB
**          Settings                                       : 
**            Submodule 0                                  : Enabled
**              Clock setting                              : 
**                PWM clock source                         : IP Bus clock
**                PWM generator clock                      : Disabled
**                PWM prescaler                            : 1
**                Module clock                             : 100 MHz
**                Init counter value                       : F3CB
**                PWM value 0 - half cycle point           : 0
**                PWM value 1 - counter modulo             : 3124
**                Fractional circuit power up              : Disabled
**                Fractional value 1 circuit               : Disabled
**                Fractional value 1                       : 0
**                Dead time value 0                        : 30
**                Dead time value 1                        : 30
**                PWM frequency                            : 16.0000 kHz
**                PWM period                               : 62.5000 us
**                PWM dead time 0                          : 0.300 us
**                PWM dead time 1                          : 0.300 us
**              Enabled in Wait mode                       : no
**              Enabled in Debug mode                      : no
**              Channel settings                           : 
**                Mode of PWM ch A and B                   : Complementary
**                Complementary PWM source                 : PWM23
**                Double switching                         : Disabled
**                Channel A (PWM23)                        : 
**                  PWM function                           : 
**                    PWM value 2                          : F9E6
**                    Fractional value 2 and 3 circuit     : Disabled
**                    Fractional value 2                   : 0
**                    PWM value 3                          : 1562
**                    Fractional value 3                   : 0
**                    SW output                            : Logic 0
**                    Deadtime source                      : Generated PWM
**                    Output fault state                   : Forced to 0 prior to output polarity
**                    Output polarity                      : Not inverted
**                    Channel masked                       : no
**                    Channel output                       : Disabled
**                    Fault channel 0                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : yes
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                    Fault channel 1                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : no
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                  E-capture function                     : 
**                    FIFOs water mark level               : 0
**                    Edge counter                         : Disabled
**                    Edge compare                         : 0
**                    Input select A                       : Raw PWMA input signal
**                    Capture 0 circuitry                  : Disabled
**                    Capture 1 circuitry                  : Disabled
**                    Capture circuitry mode               : Free running
**                    Input capture process                : Disabled
**                Channel B (PWM45)                        : 
**                  PWM function                           : 
**                    PWM value 4                          : F3EA
**                    Fractional value 4 and 5 circuit     : Disabled
**                    Fractional value 4                   : 0
**                    PWM value 5                          : 0
**                    Fractional value 5                   : 0
**                    SW output                            : Logic 0
**                    Deadtime source                      : Generated PWM
**                    Output fault state                   : Forced to 0 prior to output polarity
**                    Output polarity                      : Not inverted
**                    Channel masked                       : no
**                    Channel output                       : Disabled
**                    Fault channel 0                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : yes
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                    Fault channel 1                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : no
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                  E-capture function                     : 
**                    FIFOs water mark level               : 0
**                    Edge counter                         : Disabled
**                    Edge compare                         : 0
**                    Input select B                       : Raw PWMB input signal
**                    Capture 0 circuitry                  : Disabled
**                    Capture 1 circuitry                  : Disabled
**                    Capture circuitry mode               : Free running
**                    Input capture process                : Disabled
**                Channel X (PWM01)                        : 
**                  PWM function                           : 
**                    Output fault state                   : Forced to 0 prior to output polarity
**                    Output polarity                      : Not inverted
**                    Channel masked                       : no
**                    X Double switching                   : Disabled
**                    Channel output                       : Disabled
**                    Fault channel 0                      : 
**                      Disable by fault 0                 : yes
**                      Disable by fault 1                 : no
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                    Fault channel 1                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : no
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                  E-capture function                     : 
**                    FIFOs water mark level               : 0
**                    Edge counter                         : Disabled
**                    Edge compare                         : 0
**                    Input select X                       : Raw PWMX input signal
**                    Capture 0 circuitry                  : Disabled
**                    Capture 1 circuitry                  : Disabled
**                    Capture circuitry mode               : Free running
**                    Input capture process                : Disabled
**              Output trigger settings                    : 
**                Output trigger 0 source select           : OUT_TRIG0 signal
**                Output trigger 1 source select           : OUT_TRIG1 signal
**                OUT_TRIG0 signal settings                : 
**                  Output trigger for Val 0               : Disabled
**                  Output trigger for Val 2               : Disabled
**                  Output trigger for Val 4               : Enabled
**                OUT_TRIG1 signal settings                : 
**                  Output trigger for Val 1               : Disabled
**                  Output trigger for Val 3               : Disabled
**                  Output trigger for Val 5               : Disabled
**              Reload settings                            : 
**                Reload source                            : Local reload signal
**                Reload frequency                         : 1
**                Half cycle reload                        : Enabled
**                Full cycle reload                        : Disabled
**                Load mode                                : Load at next PWM reload if LDOK is set
**              Force and initialization settings          : 
**                Initialization source                    : External sync signal
**                Force initialization                     : Enabled
**                Force source                             : Local force signal
**                Init value ch A                          : Low
**                Init value ch B                          : Low
**                Init value ch X                          : Low
**            Submodule 1                                  : Enabled
**              Clock setting                              : 
**                PWM clock source                         : Submodule 0's clock
**                PWM generator clock                      : Disabled
**                PWM prescaler                            : 1
**                Module clock                             : 100 MHz
**                Init counter value                       : F3CB
**                PWM value 0 - half cycle point           : 0
**                PWM value 1 - counter modulo             : 3124
**                Fractional circuit power up              : Disabled
**                Fractional value 1 circuit               : Disabled
**                Fractional value 1                       : 0
**                Dead time value 0                        : 30
**                Dead time value 1                        : 30
**                PWM frequency                            : 16.0000 kHz
**                PWM period                               : 62.5000 us
**                PWM dead time 0                          : 0.300 us
**                PWM dead time 1                          : 0.300 us
**              Enabled in Wait mode                       : no
**              Enabled in Debug mode                      : no
**              Channel settings                           : 
**                Mode of PWM ch A and B                   : Complementary
**                Complementary PWM source                 : PWM23
**                Double switching                         : Disabled
**                Channel A (PWM23)                        : 
**                  PWM function                           : 
**                    PWM value 2                          : F9E6
**                    Fractional value 2 and 3 circuit     : Disabled
**                    Fractional value 2                   : 0
**                    PWM value 3                          : 1562
**                    Fractional value 3                   : 0
**                    SW output                            : Logic 0
**                    Deadtime source                      : Generated PWM
**                    Output fault state                   : Forced to 0 prior to output polarity
**                    Output polarity                      : Not inverted
**                    Channel masked                       : no
**                    Channel output                       : Disabled
**                    Fault channel 0                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : yes
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                    Fault channel 1                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : no
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                  E-capture function                     : 
**                    FIFOs water mark level               : 0
**                    Edge counter                         : Disabled
**                    Edge compare                         : 0
**                    Input select A                       : Raw PWMA input signal
**                    Capture 0 circuitry                  : Disabled
**                    Capture 1 circuitry                  : Disabled
**                    Capture circuitry mode               : Free running
**                    Input capture process                : Disabled
**                Channel B (PWM45)                        : 
**                  PWM function                           : 
**                    PWM value 4                          : 0
**                    Fractional value 4 and 5 circuit     : Disabled
**                    Fractional value 4                   : 0
**                    PWM value 5                          : 0
**                    Fractional value 5                   : 0
**                    SW output                            : Logic 0
**                    Deadtime source                      : Generated PWM
**                    Output fault state                   : Forced to 0 prior to output polarity
**                    Output polarity                      : Not inverted
**                    Channel masked                       : no
**                    Channel output                       : Disabled
**                    Fault channel 0                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : yes
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                    Fault channel 1                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : no
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                  E-capture function                     : 
**                    FIFOs water mark level               : 0
**                    Edge counter                         : Disabled
**                    Edge compare                         : 0
**                    Input select B                       : Raw PWMB input signal
**                    Capture 0 circuitry                  : Disabled
**                    Capture 1 circuitry                  : Disabled
**                    Capture circuitry mode               : Free running
**                    Input capture process                : Disabled
**                Channel X (PWM01)                        : 
**                  PWM function                           : 
**                    Output fault state                   : Forced to 0 prior to output polarity
**                    Output polarity                      : Not inverted
**                    Channel masked                       : no
**                    X Double switching                   : Disabled
**                    Channel output                       : Disabled
**                    Fault channel 0                      : 
**                      Disable by fault 0                 : yes
**                      Disable by fault 1                 : yes
**                      Disable by fault 2                 : yes
**                      Disable by fault 3                 : yes
**                    Fault channel 1                      : 
**                      Disable by fault 0                 : yes
**                      Disable by fault 1                 : yes
**                      Disable by fault 2                 : yes
**                      Disable by fault 3                 : yes
**                  E-capture function                     : 
**                    FIFOs water mark level               : 0
**                    Edge counter                         : Disabled
**                    Edge compare                         : 0
**                    Input select X                       : Raw PWMX input signal
**                    Capture 0 circuitry                  : Disabled
**                    Capture 1 circuitry                  : Disabled
**                    Capture circuitry mode               : Free running
**                    Input capture process                : Disabled
**              Output trigger settings                    : 
**                Output trigger 0 source select           : OUT_TRIG0 signal
**                Output trigger 1 source select           : OUT_TRIG1 signal
**                OUT_TRIG0 signal settings                : 
**                  Output trigger for Val 0               : Disabled
**                  Output trigger for Val 2               : Disabled
**                  Output trigger for Val 4               : Disabled
**                OUT_TRIG1 signal settings                : 
**                  Output trigger for Val 1               : Disabled
**                  Output trigger for Val 3               : Disabled
**                  Output trigger for Val 5               : Disabled
**              Reload settings                            : 
**                Reload source                            : Master reload signal
**                Reload frequency                         : 1
**                Half cycle reload                        : Enabled
**                Full cycle reload                        : Disabled
**                Load mode                                : Load at next PWM reload if LDOK is set
**              Force and initialization settings          : 
**                Initialization source                    : External sync signal
**                Force initialization                     : Enabled
**                Force source                             : Master force signal
**                Init value ch A                          : Low
**                Init value ch B                          : Low
**                Init value ch X                          : Low
**            Submodule 2                                  : Enabled
**              Clock setting                              : 
**                PWM clock source                         : Submodule 0's clock
**                PWM generator clock                      : Disabled
**                PWM prescaler                            : 1
**                Module clock                             : 100 MHz
**                Init counter value                       : F3CB
**                PWM value 0 - half cycle point           : 0
**                PWM value 1 - counter modulo             : 3124
**                Fractional circuit power up              : Disabled
**                Fractional value 1 circuit               : Disabled
**                Fractional value 1                       : 0
**                Dead time value 0                        : 30
**                Dead time value 1                        : 30
**                PWM frequency                            : 16.0000 kHz
**                PWM period                               : 62.5000 us
**                PWM dead time 0                          : 0.300 us
**                PWM dead time 1                          : 0.300 us
**              Enabled in Wait mode                       : no
**              Enabled in Debug mode                      : no
**              Channel settings                           : 
**                Mode of PWM ch A and B                   : Complementary
**                Complementary PWM source                 : PWM23
**                Double switching                         : Disabled
**                Channel A (PWM23)                        : 
**                  PWM function                           : 
**                    PWM value 2                          : F9E6
**                    Fractional value 2 and 3 circuit     : Disabled
**                    Fractional value 2                   : 0
**                    PWM value 3                          : 1562
**                    Fractional value 3                   : 0
**                    SW output                            : Logic 0
**                    Deadtime source                      : Generated PWM
**                    Output fault state                   : Forced to 0 prior to output polarity
**                    Output polarity                      : Not inverted
**                    Channel masked                       : no
**                    Channel output                       : Disabled
**                    Fault channel 0                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : yes
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                    Fault channel 1                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : no
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                  E-capture function                     : 
**                    FIFOs water mark level               : 0
**                    Edge counter                         : Disabled
**                    Edge compare                         : 0
**                    Input select A                       : Raw PWMA input signal
**                    Capture 0 circuitry                  : Disabled
**                    Capture 1 circuitry                  : Disabled
**                    Capture circuitry mode               : Free running
**                    Input capture process                : Disabled
**                Channel B (PWM45)                        : 
**                  PWM function                           : 
**                    PWM value 4                          : 0
**                    Fractional value 4 and 5 circuit     : Disabled
**                    Fractional value 4                   : 0
**                    PWM value 5                          : 0
**                    Fractional value 5                   : 0
**                    SW output                            : Logic 0
**                    Deadtime source                      : Generated PWM
**                    Output fault state                   : Forced to 0 prior to output polarity
**                    Output polarity                      : Not inverted
**                    Channel masked                       : no
**                    Channel output                       : Disabled
**                    Fault channel 0                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : yes
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                    Fault channel 1                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : no
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                  E-capture function                     : 
**                    FIFOs water mark level               : 0
**                    Edge counter                         : Disabled
**                    Edge compare                         : 0
**                    Input select B                       : Raw PWMB input signal
**                    Capture 0 circuitry                  : Disabled
**                    Capture 1 circuitry                  : Disabled
**                    Capture circuitry mode               : Free running
**                    Input capture process                : Disabled
**                Channel X (PWM01)                        : 
**                  PWM function                           : 
**                    Output fault state                   : Forced to 0 prior to output polarity
**                    Output polarity                      : Not inverted
**                    Channel masked                       : no
**                    X Double switching                   : Disabled
**                    Channel output                       : Disabled
**                    Fault channel 0                      : 
**                      Disable by fault 0                 : yes
**                      Disable by fault 1                 : yes
**                      Disable by fault 2                 : yes
**                      Disable by fault 3                 : yes
**                    Fault channel 1                      : 
**                      Disable by fault 0                 : yes
**                      Disable by fault 1                 : yes
**                      Disable by fault 2                 : yes
**                      Disable by fault 3                 : yes
**                  E-capture function                     : 
**                    FIFOs water mark level               : 0
**                    Edge counter                         : Disabled
**                    Edge compare                         : 0
**                    Input select X                       : Raw PWMX input signal
**                    Capture 0 circuitry                  : Disabled
**                    Capture 1 circuitry                  : Disabled
**                    Capture circuitry mode               : Free running
**                    Input capture process                : Disabled
**              Output trigger settings                    : 
**                Output trigger 0 source select           : OUT_TRIG0 signal
**                Output trigger 1 source select           : OUT_TRIG1 signal
**                OUT_TRIG0 signal settings                : 
**                  Output trigger for Val 0               : Disabled
**                  Output trigger for Val 2               : Disabled
**                  Output trigger for Val 4               : Disabled
**                OUT_TRIG1 signal settings                : 
**                  Output trigger for Val 1               : Disabled
**                  Output trigger for Val 3               : Disabled
**                  Output trigger for Val 5               : Disabled
**              Reload settings                            : 
**                Reload source                            : Master reload signal
**                Reload frequency                         : 1
**                Half cycle reload                        : Enabled
**                Full cycle reload                        : Disabled
**                Load mode                                : Load at next PWM reload if LDOK is set
**              Force and initialization settings          : 
**                Initialization source                    : External sync signal
**                Force initialization                     : Enabled
**                Force source                             : Master force signal
**                Init value ch A                          : Low
**                Init value ch B                          : Low
**                Init value ch X                          : Low
**            Submodule 3                                  : Disabled
**            Fault channel 0 protection settings          : 
**              Common fault settings                      : 
**                Input filter                             : Enabled
**                  Sample count                           : 10
**                  Sample period                          : 15
**                Fault Glitch Stretch                     : Disabled
**              Fault 0                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**              Fault 1                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : yes
**              Fault 2                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**              Fault 3                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**            Fault channel 1 protection settings          : 
**              Common fault settings                      : 
**                Input filter                             : Disabled
**                Fault Glitch Stretch                     : Disabled
**              Fault 0                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**              Fault 1                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**              Fault 2                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**              Fault 3                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**          Pins                                           : 
**            SM0 pins                                     : Enabled
**              PWM/Input capture channels                 : 
**                Channel A                                : Enabled
**                  PWM/Input capture pin A                : GPIOG3/PWMB_0A/XB_OUT5
**                  PWM/Input capture pin A signal         : 
**                Channel B                                : Enabled
**                  PWM/Input capture pin B                : GPIOG2/PWMB_0B/XB_OUT4
**                  PWM/Input capture pin B signal         : 
**                Channel X                                : Disabled
**              External control A - EXTA                  : Disabled
**              External control B - EXTB                  : Disabled
**              External synchronization                   : Enabled
**                External sync input                      : PWMA0_TRG0
**                External sync input signal               : 
**              Output trigger 0 or 1                      : Enabled
**                PWM_OUT_TRIG0 OR PWM_OUT_TRIG1           : GPIOC15/SCL0/XB_OUT5
**                PWM_OUT_TRIG0 OR PWM_OUT_TRIG1 signal    : 
**            SM1 pins                                     : Enabled
**              PWM/Input capture channels                 : 
**                Channel A                                : Enabled
**                  PWM/Input capture pin A                : GPIOG1/PWMB_1A/XB_OUT7
**                  PWM/Input capture pin A signal         : 
**                Channel B                                : Enabled
**                  PWM/Input capture pin B                : GPIOG0/PWMB_1B/XB_OUT6
**                  PWM/Input capture pin B signal         : 
**                Channel X                                : Disabled
**              External control A - EXTA                  : Disabled
**              External control B - EXTB                  : Disabled
**              External synchronization                   : Enabled
**                External sync input                      : PWMA0_TRG0
**                External sync input signal               : 
**              Output trigger 0 or 1                      : Disabled
**            SM2 pins                                     : Enabled
**              PWM/Input capture channels                 : 
**                Channel A                                : Enabled
**                  PWM/Input capture pin A                : GPIOE9/PWMB_2A/PWMA_FAULT1
**                  PWM/Input capture pin A signal         : 
**                Channel B                                : Enabled
**                  PWM/Input capture pin B                : GPIOE8/PWMB_2B/PWMA_FAULT0
**                  PWM/Input capture pin B signal         : 
**                Channel X                                : Disabled
**              External control A - EXTA                  : Disabled
**              External control B - EXTB                  : Disabled
**              External synchronization                   : Enabled
**                External sync input                      : PWMA0_TRG0
**                External sync input signal               : 
**              Output trigger 0 or 1                      : Disabled
**            SM3 pins                                     : Disabled
**            PWM Faults                                   : 
**              Fault channel 0                            : 
**                Fault 0                                  : Disabled
**                Fault 1                                  : Enabled
**                  Fault pin 1                            : GPIOC8/MISO0/RXD0/XB_IN9
**                  Fault pin 1 signal                     : 
**                Fault 2                                  : Disabled
**                Fault 3                                  : Disabled
**              Fault channel 1                            : 
**            External clock                               : 
**              External clock                             : Disabled
**              External clock frequency                   : 1
**            External force                               : Disabled
**          Interrupts/DMA                                 : 
**            SM0 Interrupts/DMA                           : Disabled
**            SM1 Interrupts/DMA                           : Disabled
**            SM2 Interrupts/DMA                           : Disabled
**            SM3 Interrupts/DMA                           : Disabled
**            Fault interrupt                              : 
**              Interrupt                                  : INT_eFlexPWMB_FAULT
**              Interrupt priority                         : 2
**              ISR Name                                   : PWMB_Fault_Isr
**              Channel 0 fault 0 interrupt                : Disabled
**              Channel 0 fault 1 interrupt                : Enabled
**              Channel 0 fault 2 interrupt                : Disabled
**              Channel 0 fault 3 interrupt                : Disabled
**              Channel 1 Fault 0 interrupt                : Disabled
**              Channel 1 Fault 1 interrupt                : Disabled
**              Channel 1 Fault 2 interrupt                : Disabled
**              Channel 1 Fault 3 interrupt                : Disabled
**          Initialization                                 : 
**            Load values after init into SM0              : yes
**            Load values after init into SM1              : yes
**            Load values after init into SM2              : yes
**            Load values after init into SM3              : yes
**            Enable peripheral clock for SM0              : yes
**            Enable peripheral clock for SM1              : yes
**            Enable peripheral clock for SM2              : yes
**            Enable peripheral clock for SM3              : yes
**            Fault channel 0 test                         : No simulated fault
**            Fault channel 1 test                         : No simulated fault
**            Fault flag clearing                          : 
**              Fault channel 0 flag 0                     : Clear
**              Fault channel 0 flag 1                     : Clear
**              Fault channel 0 flag 2                     : Clear
**              Fault channel 0 flag 3                     : Clear
**              Fault channel 1 flag 0                     : Clear
**              Fault channel 1 flag 1                     : Clear
**              Fault channel 1 flag 2                     : Clear
**              Fault channel 1 flag 3                     : Clear
**            Call Init method                             : yes
**     Contents    :
**         Init - void PWMB_Init(void);
**
**     Copyright : 1997 - 2014 Freescale Semiconductor, Inc. 
**     All Rights Reserved.
**     
**     Redistribution and use in source and binary forms, with or without modification,
**     are permitted provided that the following conditions are met:
**     
**     o Redistributions of source code must retain the above copyright notice, this list
**       of conditions and the following disclaimer.
**     
**     o Redistributions in binary form must reproduce the above copyright notice, this
**       list of conditions and the following disclaimer in the documentation and/or
**       other materials provided with the distribution.
**     
**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
**       contributors may be used to endorse or promote products derived from this
**       software without specific prior written permission.
**     
**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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** ###################################################################*/
/*!
** @file PWMB.c
** @version 01.00
** @brief
**          This file implements the eFlexPWM (PWMB) module initialization
**          according to the Peripheral Initialization settings, and
**          defines interrupt service routines prototypes.
*/         
/*!
**  @addtogroup PWMB_module PWMB module documentation
**  @{
*/         

/* MODULE PWMB. */

#include "PWMB.h"
  /* Including shared modules, which are used in the whole project */
#include "PE_Types.h"
#include "PE_Error.h"
#include "PE_Const.h"
#include "IO_Map.h"
#include "Cpu.h"


/*
** ===================================================================
**     Method      :  PWMB_Init (component Init_eFlexPWM)
**     Description :
**         This method initializes registers of the eFlexPWM module
**         according to the Peripheral Initialization settings.
**         Call this method in user code to initialize the module. By
**         default, the method is called by PE automatically; see "Call
**         Init method" property of the component for more details.
**     Parameters  : None
**     Returns     : Nothing
** ===================================================================
*/
void PWMB_Init(void)
{
  /* PWMB_MCTRL: IPOL&=~7,RUN&=~7,CLDOK|=7,LDOK&=~7 */
  clrSetReg16Bits(PWMB_MCTRL, 0x7707U, 0x70U); 
  /* PWMB_SM0INTEN: ??=0,??=0,REIE=0,RIE=0,CA1IE=0,CA0IE=0,CB1IE=0,CB0IE=0,CX1IE=0,CX0IE=0,CMPIE=0 */
  setReg16(PWMB_SM0INTEN, 0x00U);       
  /* PWMB_SM1INTEN: ??=0,??=0,REIE=0,RIE=0,CA1IE=0,CA0IE=0,CB1IE=0,CB0IE=0,CX1IE=0,CX0IE=0,CMPIE=0 */
  setReg16(PWMB_SM1INTEN, 0x00U);       
  /* PWMB_SM2INTEN: ??=0,??=0,REIE=0,RIE=0,CA1IE=0,CA0IE=0,CB1IE=0,CB0IE=0,CX1IE=0,CX0IE=0,CMPIE=0 */
  setReg16(PWMB_SM2INTEN, 0x00U);       
  /* PWMB_FCTRL0: FLVL=0,FAUTO=0,FSAFE=0,FIE=0 */
  setReg16(PWMB_FCTRL0, 0x00U);         
  /* PWMB_FCTRL1: FLVL=0,FAUTO=0,FSAFE=0,FIE=0 */
  setReg16(PWMB_FCTRL1, 0x00U);         
  /* PWMB_SM0OCTRL: PWMA_IN=0,PWMB_IN=0,PWMX_IN=0,??=0,??=0,POLA=0,POLB=0,POLX=0,??=0,??=0,PWMAFS=0,PWMBFS=0,PWMXFS=0 */
  setReg16(PWMB_SM0OCTRL, 0x00U);       
  /* PWMB_SM1OCTRL: PWMA_IN=0,PWMB_IN=0,PWMX_IN=0,??=0,??=0,POLA=0,POLB=0,POLX=0,??=0,??=0,PWMAFS=0,PWMBFS=0,PWMXFS=0 */
  setReg16(PWMB_SM1OCTRL, 0x00U);       
  /* PWMB_SM2OCTRL: PWMA_IN=0,PWMB_IN=0,PWMX_IN=0,??=0,??=0,POLA=0,POLB=0,POLX=0,??=0,??=0,PWMAFS=0,PWMBFS=0,PWMXFS=0 */
  setReg16(PWMB_SM2OCTRL, 0x00U);       
  /* PWMB_SM0INIT: INIT=0xF3CB */
  setReg16(PWMB_SM0INIT, 0xF3CBU);      
  /* PWMB_SM1INIT: INIT=0xF3CB */
  setReg16(PWMB_SM1INIT, 0xF3CBU);      
  /* PWMB_SM2INIT: INIT=0xF3CB */
  setReg16(PWMB_SM2INIT, 0xF3CBU);      
  /* PWMB_SM0CTRL2: DBGEN=0,WAITEN=0,INDEP=0,PWM23_INIT=0,PWM45_INIT=0,PWMX_INIT=0,INIT_SEL=3,FRCEN=1,FORCE=0,FORCE_SEL=0,RELOAD_SEL=0,CLK_SEL=0 */
  setReg16(PWMB_SM0CTRL2, 0x0380U);     
  /* PWMB_SM1CTRL2: DBGEN=0,WAITEN=0,INDEP=0,PWM23_INIT=0,PWM45_INIT=0,PWMX_INIT=0,INIT_SEL=3,FRCEN=1,FORCE=0,FORCE_SEL=1,RELOAD_SEL=1,CLK_SEL=2 */
  setReg16(PWMB_SM1CTRL2, 0x038EU);     
  /* PWMB_SM2CTRL2: DBGEN=0,WAITEN=0,INDEP=0,PWM23_INIT=0,PWM45_INIT=0,PWMX_INIT=0,INIT_SEL=3,FRCEN=1,FORCE=0,FORCE_SEL=1,RELOAD_SEL=1,CLK_SEL=2 */
  setReg16(PWMB_SM2CTRL2, 0x038EU);     
  /* PWMB_SM0CTRL: LDFQ=0,HALF=1,FULL=0,DT=0,??=0,PRSC=0,??=0,LDMOD=0,DBLX=0,DBLEN=0 */
  setReg16(PWMB_SM0CTRL, 0x0800U);      
  /* PWMB_SM1CTRL: LDFQ=0,HALF=1,FULL=0,DT=0,??=0,PRSC=0,??=0,LDMOD=0,DBLX=0,DBLEN=0 */
  setReg16(PWMB_SM1CTRL, 0x0800U);      
  /* PWMB_SM2CTRL: LDFQ=0,HALF=1,FULL=0,DT=0,??=0,PRSC=0,??=0,LDMOD=0,DBLX=0,DBLEN=0 */
  setReg16(PWMB_SM2CTRL, 0x0800U);      
  /* PWMB_SM0TCTRL: PWAOT0=0,PWBOT1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUT_TRIG_EN=0x10 */
  setReg16(PWMB_SM0TCTRL, 0x10U);       
  /* PWMB_SM1TCTRL: PWAOT0=0,PWBOT1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUT_TRIG_EN=0 */
  setReg16(PWMB_SM1TCTRL, 0x00U);       
  /* PWMB_SM2TCTRL: PWAOT0=0,PWBOT1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUT_TRIG_EN=0 */
  setReg16(PWMB_SM2TCTRL, 0x00U);       
  /* PWMB_SM0VAL0: VAL0=0 */
  setReg16(PWMB_SM0VAL0, 0x00U);        
  /* PWMB_SM0VAL1: VAL1=0x0C34 */
  setReg16(PWMB_SM0VAL1, 0x0C34U);      
  /* PWMB_SM0VAL2: VAL2=0xF9E6 */
  setReg16(PWMB_SM0VAL2, 0xF9E6U);      
  /* PWMB_SM0VAL3: VAL3=0x061A */
  setReg16(PWMB_SM0VAL3, 0x061AU);      
  /* PWMB_SM0VAL4: VAL4=0xF3EA */
  setReg16(PWMB_SM0VAL4, 0xF3EAU);      
  /* PWMB_SM0VAL5: VAL5=0 */
  setReg16(PWMB_SM0VAL5, 0x00U);        
  /* PWMB_SM1VAL0: VAL0=0 */
  setReg16(PWMB_SM1VAL0, 0x00U);        
  /* PWMB_SM1VAL1: VAL1=0x0C34 */
  setReg16(PWMB_SM1VAL1, 0x0C34U);      
  /* PWMB_SM1VAL2: VAL2=0xF9E6 */
  setReg16(PWMB_SM1VAL2, 0xF9E6U);      
  /* PWMB_SM1VAL3: VAL3=0x061A */
  setReg16(PWMB_SM1VAL3, 0x061AU);      
  /* PWMB_SM1VAL4: VAL4=0 */
  setReg16(PWMB_SM1VAL4, 0x00U);        
  /* PWMB_SM1VAL5: VAL5=0 */
  setReg16(PWMB_SM1VAL5, 0x00U);        
  /* PWMB_SM2VAL0: VAL0=0 */
  setReg16(PWMB_SM2VAL0, 0x00U);        
  /* PWMB_SM2VAL1: VAL1=0x0C34 */
  setReg16(PWMB_SM2VAL1, 0x0C34U);      
  /* PWMB_SM2VAL2: VAL2=0xF9E6 */
  setReg16(PWMB_SM2VAL2, 0xF9E6U);      
  /* PWMB_SM2VAL3: VAL3=0x061A */
  setReg16(PWMB_SM2VAL3, 0x061AU);      
  /* PWMB_SM2VAL4: VAL4=0 */
  setReg16(PWMB_SM2VAL4, 0x00U);        
  /* PWMB_SM2VAL5: VAL5=0 */
  setReg16(PWMB_SM2VAL5, 0x00U);        
  /* PWMB_SM0FRACVAL1: FRACVAL1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMB_SM0FRACVAL1, 0x00U);    
  /* PWMB_SM0FRACVAL2: FRACVAL2=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMB_SM0FRACVAL2, 0x00U);    
  /* PWMB_SM0FRACVAL3: FRACVAL3=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMB_SM0FRACVAL3, 0x00U);    
  /* PWMB_SM0FRACVAL4: FRACVAL4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMB_SM0FRACVAL4, 0x00U);    
  /* PWMB_SM0FRACVAL5: FRACVAL5=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMB_SM0FRACVAL5, 0x00U);    
  /* PWMB_SM1FRACVAL1: FRACVAL1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMB_SM1FRACVAL1, 0x00U);    
  /* PWMB_SM1FRACVAL2: FRACVAL2=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMB_SM1FRACVAL2, 0x00U);    
  /* PWMB_SM1FRACVAL3: FRACVAL3=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMB_SM1FRACVAL3, 0x00U);    
  /* PWMB_SM1FRACVAL4: FRACVAL4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMB_SM1FRACVAL4, 0x00U);    
  /* PWMB_SM1FRACVAL5: FRACVAL5=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMB_SM1FRACVAL5, 0x00U);    
  /* PWMB_SM2FRACVAL1: FRACVAL1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMB_SM2FRACVAL1, 0x00U);    
  /* PWMB_SM2FRACVAL2: FRACVAL2=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMB_SM2FRACVAL2, 0x00U);    
  /* PWMB_SM2FRACVAL3: FRACVAL3=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMB_SM2FRACVAL3, 0x00U);    
  /* PWMB_SM2FRACVAL4: FRACVAL4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMB_SM2FRACVAL4, 0x00U);    
  /* PWMB_SM2FRACVAL5: FRACVAL5=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMB_SM2FRACVAL5, 0x00U);    
  /* PWMB_SM0FRCTRL: TEST=0,??=0,??=0,??=0,??=0,??=0,??=0,FRAC_PU=0,??=0,??=0,??=0,FRAC45_EN=0,??=0,FRAC23_EN=0,FRAC1_EN=0,??=0 */
  setReg16(PWMB_SM0FRCTRL, 0x00U);      
  /* PWMB_SM1FRCTRL: TEST=0,??=0,??=0,??=0,??=0,??=0,??=0,FRAC_PU=0,??=0,??=0,??=0,FRAC45_EN=0,??=0,FRAC23_EN=0,FRAC1_EN=0,??=0 */
  setReg16(PWMB_SM1FRCTRL, 0x00U);      
  /* PWMB_SM2FRCTRL: TEST=0,??=0,??=0,??=0,??=0,??=0,??=0,FRAC_PU=0,??=0,??=0,??=0,FRAC45_EN=0,??=0,FRAC23_EN=0,FRAC1_EN=0,??=0 */
  setReg16(PWMB_SM2FRCTRL, 0x00U);      
  /* PWMB_SM0DISMAP0: ??=1,??=1,??=1,??=1,DIS0X=1,DIS0B=2,DIS0A=2 */
  setReg16(PWMB_SM0DISMAP0, 0xF122U);   
  /* PWMB_SM0DISMAP1: ??=1,??=1,??=1,??=1,DIS1X=0,DIS1B=0,DIS1A=0 */
  setReg16(PWMB_SM0DISMAP1, 0xF000U);   
  /* PWMB_SM1DISMAP0: ??=1,??=1,??=1,??=1,DIS0X=0x0F,DIS0B=2,DIS0A=2 */
  setReg16(PWMB_SM1DISMAP0, 0xFF22U);   
  /* PWMB_SM1DISMAP1: ??=1,??=1,??=1,??=1,DIS1X=0x0F,DIS1B=0,DIS1A=0 */
  setReg16(PWMB_SM1DISMAP1, 0xFF00U);   
  /* PWMB_SM2DISMAP0: ??=1,??=1,??=1,??=1,DIS0X=0x0F,DIS0B=2,DIS0A=2 */
  setReg16(PWMB_SM2DISMAP0, 0xFF22U);   
  /* PWMB_SM2DISMAP1: ??=1,??=1,??=1,??=1,DIS1X=0x0F,DIS1B=0,DIS1A=0 */
  setReg16(PWMB_SM2DISMAP1, 0xFF00U);   
  /* PWMB_SM0DTCNT0: ??=0,??=0,??=0,??=0,??=0,DTCNT0=0x1E */
  setReg16(PWMB_SM0DTCNT0, 0x1EU);      
  /* PWMB_SM0DTCNT1: ??=0,??=0,??=0,??=0,??=0,DTCNT1=0x1E */
  setReg16(PWMB_SM0DTCNT1, 0x1EU);      
  /* PWMB_SM1DTCNT0: ??=0,??=0,??=0,??=0,??=0,DTCNT0=0x1E */
  setReg16(PWMB_SM1DTCNT0, 0x1EU);      
  /* PWMB_SM1DTCNT1: ??=0,??=0,??=0,??=0,??=0,DTCNT1=0x1E */
  setReg16(PWMB_SM1DTCNT1, 0x1EU);      
  /* PWMB_SM2DTCNT0: ??=0,??=0,??=0,??=0,??=0,DTCNT0=0x1E */
  setReg16(PWMB_SM2DTCNT0, 0x1EU);      
  /* PWMB_SM2DTCNT1: ??=0,??=0,??=0,??=0,??=0,DTCNT1=0x1E */
  setReg16(PWMB_SM2DTCNT1, 0x1EU);      
  /* PWMB_SM0CAPTCOMPA: EDGCNTA=0,EDGCMPA=0 */
  setReg16(PWMB_SM0CAPTCOMPA, 0x00U);   
  /* PWMB_SM0CAPTCOMPB: EDGCNTB=0,EDGCMPB=0 */
  setReg16(PWMB_SM0CAPTCOMPB, 0x00U);   
  /* PWMB_SM0CAPTCOMPX: EDGCNTX=0,EDGCMPX=0 */
  setReg16(PWMB_SM0CAPTCOMPX, 0x00U);   
  /* PWMB_SM1CAPTCOMPA: EDGCNTA=0,EDGCMPA=0 */
  setReg16(PWMB_SM1CAPTCOMPA, 0x00U);   
  /* PWMB_SM1CAPTCOMPB: EDGCNTB=0,EDGCMPB=0 */
  setReg16(PWMB_SM1CAPTCOMPB, 0x00U);   
  /* PWMB_SM1CAPTCOMPX: EDGCNTX=0,EDGCMPX=0 */
  setReg16(PWMB_SM1CAPTCOMPX, 0x00U);   
  /* PWMB_SM2CAPTCOMPA: EDGCNTA=0,EDGCMPA=0 */
  setReg16(PWMB_SM2CAPTCOMPA, 0x00U);   
  /* PWMB_SM2CAPTCOMPB: EDGCNTB=0,EDGCMPB=0 */
  setReg16(PWMB_SM2CAPTCOMPB, 0x00U);   
  /* PWMB_SM2CAPTCOMPX: EDGCNTX=0,EDGCMPX=0 */
  setReg16(PWMB_SM2CAPTCOMPX, 0x00U);   
  /* PWMB_FFILT0: GSTR=0,??=0,??=0,??=0,??=0,FILT_CNT=7,FILT_PER=0x0F */
  setReg16(PWMB_FFILT0, 0x070FU);       
  /* PWMB_FFILT1: GSTR=0,??=0,??=0,??=0,??=0,FILT_CNT=0,FILT_PER=0 */
  setReg16(PWMB_FFILT1, 0x00U);         
  /* PWMB_MASK: ??=0,??=0,??=0,??=0,MASKA&=~7,MASKB&=~7,MASKX&=~7 */
  clrReg16Bits(PWMB_MASK, 0xF777U);     
  /* PWMB_SWCOUT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,SM2OUT23=0,SM2OUT45=0,SM1OUT23=0,SM1OUT45=0,SM0OUT23=0,SM0OUT45=0 */
  clrReg16Bits(PWMB_SWCOUT, 0xFF3FU);   
  /* PWMB_DTSRCSEL: SM2SEL23=0,SM2SEL45=0,SM1SEL23=0,SM1SEL45=0,SM0SEL23=0,SM0SEL45=0 */
  clrReg16Bits(PWMB_DTSRCSEL, 0x0FFFU); 
  /* PWMB_OUTEN: ??=0,??=0,??=0,??=0,PWMA_EN&=~7,PWMB_EN&=~7,PWMX_EN&=~7 */
  clrReg16Bits(PWMB_OUTEN, 0xF777U);    
  /* PWMB_SM0CAPTCTRLA: CA1CNT=0,CA0CNT=0,CFAWM=0,EDGCNTA_EN=0,INP_SELA=0,EDGA1=0,EDGA0=0,ONESHOTA=0,ARMA=0 */
  setReg16(PWMB_SM0CAPTCTRLA, 0x00U);   
  /* PWMB_SM0CAPTCTRLB: CB1CNT=0,CB0CNT=0,CFBWM=0,EDGCNTB_EN=0,INP_SELB=0,EDGB1=0,EDGB0=0,ONESHOTB=0,ARMB=0 */
  setReg16(PWMB_SM0CAPTCTRLB, 0x00U);   
  /* PWMB_SM0CAPTCTRLX: CX1CNT=0,CX0CNT=0,CFXWM=0,EDGCNTX_EN=0,INP_SELX=0,EDGX1=0,EDGX0=0,ONESHOTX=0,ARMX=0 */
  setReg16(PWMB_SM0CAPTCTRLX, 0x00U);   
  /* PWMB_SM1CAPTCTRLA: CA1CNT=0,CA0CNT=0,CFAWM=0,EDGCNTA_EN=0,INP_SELA=0,EDGA1=0,EDGA0=0,ONESHOTA=0,ARMA=0 */
  setReg16(PWMB_SM1CAPTCTRLA, 0x00U);   
  /* PWMB_SM1CAPTCTRLB: CB1CNT=0,CB0CNT=0,CFBWM=0,EDGCNTB_EN=0,INP_SELB=0,EDGB1=0,EDGB0=0,ONESHOTB=0,ARMB=0 */
  setReg16(PWMB_SM1CAPTCTRLB, 0x00U);   
  /* PWMB_SM1CAPTCTRLX: CX1CNT=0,CX0CNT=0,CFXWM=0,EDGCNTX_EN=0,INP_SELX=0,EDGX1=0,EDGX0=0,ONESHOTX=0,ARMX=0 */
  setReg16(PWMB_SM1CAPTCTRLX, 0x00U);   
  /* PWMB_SM2CAPTCTRLA: CA1CNT=0,CA0CNT=0,CFAWM=0,EDGCNTA_EN=0,INP_SELA=0,EDGA1=0,EDGA0=0,ONESHOTA=0,ARMA=0 */
  setReg16(PWMB_SM2CAPTCTRLA, 0x00U);   
  /* PWMB_SM2CAPTCTRLB: CB1CNT=0,CB0CNT=0,CFBWM=0,EDGCNTB_EN=0,INP_SELB=0,EDGB1=0,EDGB0=0,ONESHOTB=0,ARMB=0 */
  setReg16(PWMB_SM2CAPTCTRLB, 0x00U);   
  /* PWMB_SM2CAPTCTRLX: CX1CNT=0,CX0CNT=0,CFXWM=0,EDGCNTX_EN=0,INP_SELX=0,EDGX1=0,EDGX0=0,ONESHOTX=0,ARMX=0 */
  setReg16(PWMB_SM2CAPTCTRLX, 0x00U);   
  /* PWMB_MCTRL: IPOL&=~7,RUN=0,LDOK=0x0F */
  clrSetReg16Bits(PWMB_MCTRL, 0x7F00U, 0x0FU); 
  /* PWMB_FSTS0: FHALF=0,FFPIN=0x0F,FFULL=2,FFLAG=0x0F */
  setReg16(PWMB_FSTS0, 0x0F2FU);        
  /* PWMB_FSTS1: FHALF=0,FFPIN=0x0F,FFULL=0,FFLAG=0x0F */
  setReg16(PWMB_FSTS1, 0x0F0FU);        
  /* PWMB_FCTRL0: FLVL=0,FAUTO=0,FSAFE=0,FIE=2 */
  setReg16(PWMB_FCTRL0, 0x02U);         
  /* PWMB_FCTRL1: FLVL=0,FAUTO=0,FSAFE=0,FIE=0 */
  setReg16(PWMB_FCTRL1, 0x00U);         
  /* PWMB_FTST0: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FTEST=0 */
  setReg16(PWMB_FTST0, 0x00U);          
  /* PWMB_FTST1: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FTEST=0 */
  setReg16(PWMB_FTST1, 0x00U);          
}

/*
** ###################################################################
**
**  The interrupt service routine(s) must be implemented
**  by user in one of the following user modules.
**
**  If the "Generate ISR" option is enabled, Processor Expert generates
**  ISR templates in the CPU event module.
**
**  User modules:
**      main.c
**      Events.c
**
** ###################################################################
#if defined(PWMB_Fault_Isr_FAST_INT)
#pragma interrupt fast
#elif defined(PWMB_Fault_Isr_VECT_TABLE_ISR_FAST_INT)
#pragma define_section interrupt_fast "interrupt_fast.text"  RX
#pragma section interrupt_fast begin
#pragma interrupt fast
#else
#pragma interrupt saveall
#endif
void PWMB_Fault_Isr(void)
{
// NOTE: The routine should include actions to clear the appropriate
//       interrupt flags.
//
}
*/


/* END PWMB. */
/*!
** @}
*/
/*
** ###################################################################
**
**     This file was created by Processor Expert 10.3 [05.09]
**     for the Freescale 56800 series of microcontrollers.
**
** ###################################################################
*/
