/*
 * Copyright 2019 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
/***********************************************************************************************************************
 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
 **********************************************************************************************************************/

#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_

/*!
 * @addtogroup pin_mux
 * @{
 */

/***********************************************************************************************************************
 * API
 **********************************************************************************************************************/

#if defined(__cplusplus)
extern "C" {
#endif

/*!
 * @brief Calls initialization functions.
 *
 */
void BOARD_InitBootPins(void);

#define IOPCTL_PIO_ANAMUX_DI 0x00u        /*!<@brief Analog mux is disabled */
#define IOPCTL_PIO_FULLDRIVE_DI 0x00u     /*!<@brief Normal drive */
#define IOPCTL_PIO_FUNC0 0x00u            /*!<@brief Selects pin function 0 */
#define IOPCTL_PIO_FUNC1 0x01u            /*!<@brief Selects pin function 1 */
#define IOPCTL_PIO_FUNC8 0x08u            /*!<@brief Selects pin function 8 */
#define IOPCTL_PIO_INBUF_DI 0x00u         /*!<@brief Disable input buffer function */
#define IOPCTL_PIO_INBUF_EN 0x40u         /*!<@brief Enables input buffer function */
#define IOPCTL_PIO_INV_DI 0x00u           /*!<@brief Input function is not inverted */
#define IOPCTL_PIO_PSEDRAIN_DI 0x00u      /*!<@brief Pseudo Output Drain is disabled */
#define IOPCTL_PIO_PULLDOWN_EN 0x00u      /*!<@brief Enable pull-down function */
#define IOPCTL_PIO_PUPD_DI 0x00u          /*!<@brief Disable pull-up / pull-down function */
#define IOPCTL_PIO_SLEW_RATE_NORMAL 0x00u /*!<@brief Normal mode */

/*! @name FC0_RXD_SDA_MOSI_DATA (coord G4), JP21[2]/U28[3]/U9[13]
  @{ */
                                                                     /* @} */

/*! @name FC0_TXD_SCL_MISO_WS (coord G2), J16[1]/U27[3]/U9[12]
  @{ */
                                                                   /* @} */

/*! @name PIO0_31 (coord A11), Q4[2]
  @{ */
#define BOARD_INITPINS_LED_RED_GPIO GPIO        /*!<@brief GPIO device name: GPIO */
#define BOARD_INITPINS_LED_RED_PORT 0U          /*!<@brief PORT device name: 0U */
#define BOARD_INITPINS_LED_RED_PIN 31U          /*!<@brief 0U pin index: 31 */
                                                /* @} */

/*! @name PIO0_14 (coord A3), Q4[5]
  @{ */
#define BOARD_INITPINS_LED_GREEN_GPIO GPIO        /*!<@brief GPIO device name: GPIO */
#define BOARD_INITPINS_LED_GREEN_PORT 0U          /*!<@brief PORT device name: 0U */
#define BOARD_INITPINS_LED_GREEN_PIN 14U          /*!<@brief 0U pin index: 14 */
                                                  /* @} */

/*! @name PIO0_26 (coord A2), Q3[2]
  @{ */
#define BOARD_INITPINS_LED_BLUE_GPIO GPIO        /*!<@brief GPIO device name: GPIO */
#define BOARD_INITPINS_LED_BLUE_PORT 0U          /*!<@brief PORT device name: 0U */
#define BOARD_INITPINS_LED_BLUE_PIN 26U          /*!<@brief 0U pin index: 26 */
                                                 /* @} */

/*! @name SWO (coord B6), J18[3]
  @{ */
                                                /* @} */

/*!
 * @brief Configures pin routing and optionally pin electrical features.
 *
 */
void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */

#if defined(__cplusplus)
}
#endif

/*!
 * @}
 */
#endif /* _PIN_MUX_H_ */

/***********************************************************************************************************************
 * EOF
 **********************************************************************************************************************/
