-- ***** COPYRIGHT (C) 2019 NXP Semiconductor, Inc. All Rights Reserved. ******* -- -- Boundary Scan Description Language (BSDL) File -- Generated by Synopsys Version K-2015.06-SP4 (Dec 01, 2015) at: Thu May 30 14:01:28 2019 -- -- Device: IMX8MM in 14X14 package -- Package Type: 14X14 -- Version: 2.2 -- Date:         3/19/2021 -- -- This BSDL has been validated for syntax and semantics compliance to -- IEEE 1149.1 using the JTAG Technologies CHKBSDL version 1.0.2.4. -- -- -- THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR -- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -- IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF -- THE POSSIBILITY OF SUCH DAMAGE. entity IMX8MM is generic (PHYSICAL_PIN_MAP : string := "IMX8MM_14X14"); -- PORT DESCRIPTION TERMS -- in = input only -- out = three-state output (0, Z, 1) -- buffer = two-state output (0, 1) -- inout = bidirectional -- linkage = OTHER (vdd, vss, analog) -- -- bit = single pin -- bit_vector = group of pins with suffix 0 to n port ( CLKIN1 : in bit; CLKIN2 : in bit; CLKOUT1 : in bit; CLKOUT2 : in bit; JTAG_TCK : in bit; JTAG_TDI : in bit; JTAG_TMS : in bit; JTAG_TRST_B : in bit; DRAM_AC00 : inout bit; DRAM_AC01 : inout bit; DRAM_AC02 : inout bit; DRAM_AC03 : inout bit; DRAM_AC04 : inout bit; DRAM_AC05 : inout bit; DRAM_AC06 : inout bit; DRAM_AC07 : inout bit; DRAM_AC08 : inout bit; DRAM_AC09 : inout bit; DRAM_AC10 : inout bit; DRAM_AC11 : inout bit; DRAM_AC12 : inout bit; DRAM_AC13 : inout bit; DRAM_AC14 : inout bit; DRAM_AC15 : inout bit; DRAM_AC16 : inout bit; DRAM_AC17 : inout bit; DRAM_AC19 : inout bit; DRAM_AC20 : inout bit; DRAM_AC21 : inout bit; DRAM_AC22 : inout bit; DRAM_AC23 : inout bit; DRAM_AC24 : inout bit; DRAM_AC25 : inout bit; DRAM_AC26 : inout bit; DRAM_AC27 : inout bit; DRAM_AC28 : inout bit; DRAM_AC29 : inout bit; DRAM_AC30 : inout bit; DRAM_AC31 : inout bit; DRAM_AC32 : inout bit; DRAM_AC33 : inout bit; DRAM_AC34 : inout bit; DRAM_AC35 : inout bit; DRAM_AC36 : inout bit; DRAM_AC37 : inout bit; DRAM_AC38 : inout bit; DRAM_ALERT_N : inout bit; DRAM_DM0 : inout bit; DRAM_DM1 : inout bit; DRAM_DM2 : inout bit; DRAM_DM3 : inout bit; DRAM_DQ00 : inout bit; DRAM_DQ01 : inout bit; DRAM_DQ02 : inout bit; DRAM_DQ03 : inout bit; DRAM_DQ04 : inout bit; DRAM_DQ05 : inout bit; DRAM_DQ06 : inout bit; DRAM_DQ07 : inout bit; DRAM_DQ08 : inout bit; DRAM_DQ09 : inout bit; DRAM_DQ10 : inout bit; DRAM_DQ11 : inout bit; DRAM_DQ12 : inout bit; DRAM_DQ13 : inout bit; DRAM_DQ14 : inout bit; DRAM_DQ15 : inout bit; DRAM_DQ16 : inout bit; DRAM_DQ17 : inout bit; DRAM_DQ18 : inout bit; DRAM_DQ19 : inout bit; DRAM_DQ20 : inout bit; DRAM_DQ21 : inout bit; DRAM_DQ22 : inout bit; DRAM_DQ23 : inout bit; DRAM_DQ24 : inout bit; DRAM_DQ25 : inout bit; DRAM_DQ26 : inout bit; DRAM_DQ27 : inout bit; DRAM_DQ28 : inout bit; DRAM_DQ29 : inout bit; DRAM_DQ30 : inout bit; DRAM_DQ31 : inout bit; DRAM_DQS0_N : inout bit; DRAM_DQS1_N : inout bit; DRAM_DQS2_N : inout bit; DRAM_DQS3_N : inout bit; DRAM_DQS0_P : inout bit; DRAM_DQS1_P : inout bit; DRAM_DQS2_P : inout bit; DRAM_DQS3_P : inout bit; ECSPI1_MISO : inout bit; ECSPI1_MOSI : inout bit; ECSPI1_SCLK : inout bit; ECSPI1_SS0 : inout bit; ECSPI2_MISO : inout bit; ECSPI2_MOSI : inout bit; ECSPI2_SCLK : inout bit; ECSPI2_SS0 : inout bit; ENET_MDC : inout bit; ENET_MDIO : inout bit; ENET_RD0 : inout bit; ENET_RD1 : inout bit; ENET_RD2 : inout bit; ENET_RD3 : inout bit; ENET_RXC : inout bit; ENET_RX_CTL : inout bit; ENET_TD0 : inout bit; ENET_TD1 : inout bit; ENET_TD2 : inout bit; ENET_TD3 : inout bit; ENET_TXC : inout bit; ENET_TX_CTL : inout bit; GPIO1_IO00 : inout bit; GPIO1_IO01 : inout bit; GPIO1_IO02 : inout bit; GPIO1_IO03 : inout bit; GPIO1_IO04 : inout bit; GPIO1_IO05 : inout bit; GPIO1_IO06 : inout bit; GPIO1_IO07 : inout bit; GPIO1_IO08 : inout bit; GPIO1_IO09 : inout bit; GPIO1_IO10 : inout bit; GPIO1_IO11 : inout bit; GPIO1_IO12 : inout bit; GPIO1_IO13 : inout bit; GPIO1_IO14 : inout bit; GPIO1_IO15 : inout bit; I2C1_SCL : inout bit; I2C1_SDA : inout bit; I2C2_SCL : inout bit; I2C2_SDA : inout bit; I2C3_SCL : inout bit; I2C3_SDA : inout bit; I2C4_SCL : inout bit; I2C4_SDA : inout bit; NAND_ALE : inout bit; NAND_CE0_B : inout bit; NAND_CE1_B : inout bit; NAND_CE2_B : inout bit; NAND_CE3_B : inout bit; NAND_CLE : inout bit; NAND_DATA00 : inout bit; NAND_DATA01 : inout bit; NAND_DATA02 : inout bit; NAND_DATA03 : inout bit; NAND_DATA04 : inout bit; NAND_DATA05 : inout bit; NAND_DATA06 : inout bit; NAND_DATA07 : inout bit; NAND_DQS : inout bit; NAND_READY_B : inout bit; NAND_RE_B : inout bit; NAND_WE_B : inout bit; NAND_WP_B : inout bit; SAI1_MCLK : inout bit; SAI1_RXC : inout bit; SAI1_RXD0 : inout bit; SAI1_RXD1 : inout bit; SAI1_RXD2 : inout bit; SAI1_RXD3 : inout bit; SAI1_RXD4 : inout bit; SAI1_RXD5 : inout bit; SAI1_RXD6 : inout bit; SAI1_RXD7 : inout bit; SAI1_RXFS : inout bit; SAI1_TXC : inout bit; SAI1_TXD0 : inout bit; SAI1_TXD1 : inout bit; SAI1_TXD2 : inout bit; SAI1_TXD3 : inout bit; SAI1_TXD4 : inout bit; SAI1_TXD5 : inout bit; SAI1_TXD6 : inout bit; SAI1_TXD7 : inout bit; SAI1_TXFS : inout bit; SAI2_MCLK : inout bit; SAI2_RXC : inout bit; SAI2_RXD0 : inout bit; SAI2_RXFS : inout bit; SAI2_TXC : inout bit; SAI2_TXD0 : inout bit; SAI2_TXFS : inout bit; SAI3_MCLK : inout bit; SAI3_RXC : inout bit; SAI3_RXD : inout bit; SAI3_RXFS : inout bit; SAI3_TXC : inout bit; SAI3_TXD : inout bit; SAI3_TXFS : inout bit; SAI5_MCLK : inout bit; SAI5_RXC : inout bit; SAI5_RXD0 : inout bit; SAI5_RXD1 : inout bit; SAI5_RXD2 : inout bit; SAI5_RXD3 : inout bit; SAI5_RXFS : inout bit; SD1_CLK : inout bit; SD1_CMD : inout bit; SD1_DATA0 : inout bit; SD1_DATA1 : inout bit; SD1_DATA2 : inout bit; SD1_DATA3 : inout bit; SD1_DATA4 : inout bit; SD1_DATA5 : inout bit; SD1_DATA6 : inout bit; SD1_DATA7 : inout bit; SD1_RESET_B : inout bit; SD1_STROBE : inout bit; SD2_CD_B : inout bit; SD2_CLK : inout bit; SD2_CMD : inout bit; SD2_DATA0 : inout bit; SD2_DATA1 : inout bit; SD2_DATA2 : inout bit; SD2_DATA3 : inout bit; SD2_RESET_B : inout bit; SD2_WP : inout bit; SPDIF_EXT_CLK : inout bit; SPDIF_RX : inout bit; SPDIF_TX : inout bit; UART1_RXD : inout bit; UART1_TXD : inout bit; UART2_RXD : inout bit; UART2_TXD : inout bit; UART3_RXD : inout bit; UART3_TXD : inout bit; UART4_RXD : inout bit; UART4_TXD : inout bit; JTAG_TDO : out bit; DRAM_RESET_N : buffer bit; BOOT_MODE0 : in bit; BOOT_MODE1 : in bit; DRAM_AC18 : linkage bit; -- NC(No Connect) Port DRAM_AC39 : linkage bit; -- NC Port DRAM_VREF : linkage bit; DRAM_ZN : linkage bit; DRAM_ZN_SENSE : linkage bit; EFUSE_VQPS : linkage bit; JTAG_MOD : in bit; MIPI_CSI_CLK_N : linkage bit; MIPI_CSI_CLK_P : linkage bit; MIPI_CSI_D0_N : linkage bit; MIPI_CSI_D0_P : linkage bit; MIPI_CSI_D1_N : linkage bit; MIPI_CSI_D1_P : linkage bit; MIPI_CSI_D2_N : linkage bit; MIPI_CSI_D2_P : linkage bit; MIPI_CSI_D3_N : linkage bit; MIPI_CSI_D3_P : linkage bit; MIPI_DSI_CLK_N : linkage bit; MIPI_DSI_CLK_P : linkage bit; MIPI_DSI_D0_N : linkage bit; MIPI_DSI_D0_P : linkage bit; MIPI_DSI_D1_N : linkage bit; MIPI_DSI_D1_P : linkage bit; MIPI_DSI_D2_N : linkage bit; MIPI_DSI_D2_P : linkage bit; MIPI_DSI_D3_N : linkage bit; MIPI_DSI_D3_P : linkage bit; MIPI_VREG : linkage bit; ONOFF : linkage bit; PCIE_P1_GND : linkage bit; PCIE_P1_REF_PAD_CLK_N : linkage bit; PCIE_P1_REF_PAD_CLK_P : linkage bit; PCIE_P1_RESREF : linkage bit; PCIE_P1_RXN_N : linkage bit; PCIE_P1_RXN_P : linkage bit; PCIE_P1_TXN_N : linkage bit; PCIE_P1_TXN_P : linkage bit; PCIE_P1_VP : linkage bit; PCIE_P1_VPH : linkage bit; PCIE_P1_VPTX : linkage bit; PMIC_ON_REQ : linkage bit; PMIC_STBY_REQ : linkage bit; POR_B : in bit; RTC_RESET_B : linkage bit; TEST_MODE : in bit; USB1_DM : linkage bit; USB1_DP : linkage bit; USB1_ID : linkage bit; USB1_TXRTUNE : linkage bit; USB1_VBUS : linkage bit; USB2_DN : linkage bit; USB2_DP : linkage bit; USB2_ID : linkage bit; USB2_TXRTUNE : linkage bit; USB2_VBUS : linkage bit; XTALI_24M : linkage bit; RTC_XTALI : linkage bit; XTALO_24M : linkage bit; RTC_XTALO : linkage bit ); use STD_1149_1_2001.all; attribute COMPONENT_CONFORMANCE of IMX8MM: entity is "STD_1149_1_2001"; attribute PIN_MAP of IMX8MM: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information is -- extracted from the port-to-pin map file that was read in using the -- "read_pin_map" command. constant IMX8MM_14X14: PIN_MAP_STRING := "CLKIN1 : H27," & "CLKIN2 : J27," & "CLKOUT1 : H26," & "CLKOUT2 : J26," & "JTAG_TCK : F26," & "JTAG_TDI : E27," & "JTAG_TMS : F27," & "JTAG_TRST_B : C27," & "DRAM_AC00 : F4," & "DRAM_AC01 : F5," & "DRAM_AC02 : K4," & "DRAM_AC03 : J4," & "DRAM_AC04 : L2," & "DRAM_AC05 : L1," & "DRAM_AC06 : F6," & "DRAM_AC07 : J5," & "DRAM_AC08 : J6," & "DRAM_AC09 : K6," & "DRAM_AC10 : E4," & "DRAM_AC11 : D5," & "DRAM_AC12 : N4," & "DRAM_AC13 : N5," & "DRAM_AC14 : K5," & "DRAM_AC15 : N6," & "DRAM_AC16 : M1," & "DRAM_AC17 : M2," & "DRAM_AC19 : N2," & "DRAM_AC20 : AB4," & "DRAM_AC21 : AB5," & "DRAM_AC22 : W4," & "DRAM_AC23 : V4," & "DRAM_AC24 : U2," & "DRAM_AC25 : U1," & "DRAM_AC26 : N1," & "DRAM_AC27 : R6," & "DRAM_AC28 : W6," & "DRAM_AC29 : V6," & "DRAM_AC30 : AC4," & "DRAM_AC31 : AD5," & "DRAM_AC32 : R4," & "DRAM_AC33 : R5," & "DRAM_AC34 : T1," & "DRAM_AC35 : T2," & "DRAM_AC36 : V5," & "DRAM_AC37 : W5," & "DRAM_AC38 : AB6," & "DRAM_ALERT_N : R2," & "DRAM_DM0 : A4," & "DRAM_DM1 : F1," & "DRAM_DM2 : AB1," & "DRAM_DM3 : AG4," & "DRAM_DQ00 : A5," & "DRAM_DQ01 : B5," & "DRAM_DQ02 : D2," & "DRAM_DQ03 : D1," & "DRAM_DQ04 : C1," & "DRAM_DQ05 : B1," & "DRAM_DQ06 : A3," & "DRAM_DQ07 : B4," & "DRAM_DQ08 : F2," & "DRAM_DQ09 : G2," & "DRAM_DQ10 : J1," & "DRAM_DQ11 : J2," & "DRAM_DQ12 : K2," & "DRAM_DQ13 : K1," & "DRAM_DQ14 : E1," & "DRAM_DQ15 : E2," & "DRAM_DQ16 : AB2," & "DRAM_DQ17 : AA2," & "DRAM_DQ18 : W1," & "DRAM_DQ19 : W2," & "DRAM_DQ20 : V2," & "DRAM_DQ21 : V1," & "DRAM_DQ22 : AC1," & "DRAM_DQ23 : AC2," & "DRAM_DQ24 : AG5," & "DRAM_DQ25 : AF5," & "DRAM_DQ26 : AD2," & "DRAM_DQ27 : AD1," & "DRAM_DQ28 : AE1," & "DRAM_DQ29 : AF1," & "DRAM_DQ30 : AG3," & "DRAM_DQ31 : AF4," & "DRAM_DQS0_N : B2," & "DRAM_DQS1_N : H1," & "DRAM_DQS2_N : Y1," & "DRAM_DQS3_N : AF2," & "DRAM_DQS0_P : A2," & "DRAM_DQS1_P : G1," & "DRAM_DQS2_P : AA1," & "DRAM_DQS3_P : AG2," & "ECSPI1_MISO : A7," & "ECSPI1_MOSI : B7," & "ECSPI1_SCLK : D6," & "ECSPI1_SS0 : B6," & "ECSPI2_MISO : A8," & "ECSPI2_MOSI : B8," & "ECSPI2_SCLK : E6," & "ECSPI2_SS0 : A6," & "ENET_MDC : AC27," & "ENET_MDIO : AB27," & "ENET_RD0 : AE27," & "ENET_RD1 : AD27," & "ENET_RD2 : AD26," & "ENET_RD3 : AC26," & "ENET_RXC : AE26," & "ENET_RX_CTL : AF27," & "ENET_TD0 : AG26," & "ENET_TD1 : AF26," & "ENET_TD2 : AG25," & "ENET_TD3 : AF25," & "ENET_TXC : AG24," & "ENET_TX_CTL : AF24," & "GPIO1_IO00 : AG14," & "GPIO1_IO01 : AF14," & "GPIO1_IO02 : AG13," & "GPIO1_IO03 : AF13," & "GPIO1_IO04 : AG12," & "GPIO1_IO05 : AF12," & "GPIO1_IO06 : AG11," & "GPIO1_IO07 : AF11," & "GPIO1_IO08 : AG10," & "GPIO1_IO09 : AF10," & "GPIO1_IO10 : AD10," & "GPIO1_IO11 : AC10," & "GPIO1_IO12 : AB10," & "GPIO1_IO13 : AD9," & "GPIO1_IO14 : AC9," & "GPIO1_IO15 : AB9," & "I2C1_SCL : E9," & "I2C1_SDA : F9," & "I2C2_SCL : D10," & "I2C2_SDA : D9," & "I2C3_SCL : E10," & "I2C3_SDA : F10," & "I2C4_SCL : D13," & "I2C4_SDA : E13," & "NAND_ALE : N22," & "NAND_CE0_B : N24," & "NAND_CE1_B : P27," & "NAND_CE2_B : M27," & "NAND_CE3_B : L27," & "NAND_CLE : K27," & "NAND_DATA00 : P23," & "NAND_DATA01 : K24," & "NAND_DATA02 : K23," & "NAND_DATA03 : N23," & "NAND_DATA04 : M26," & "NAND_DATA05 : L26," & "NAND_DATA06 : K26," & "NAND_DATA07 : N26," & "NAND_DQS : R22," & "NAND_READY_B : P26," & "NAND_RE_B : N27," & "NAND_WE_B : R26," & "NAND_WP_B : R27," & "SAI1_MCLK : AB18," & "SAI1_RXC : AF16," & "SAI1_RXD0 : AG15," & "SAI1_RXD1 : AF15," & "SAI1_RXD2 : AG17," & "SAI1_RXD3 : AF17," & "SAI1_RXD4 : AG18," & "SAI1_RXD5 : AF18," & "SAI1_RXD6 : AG19," & "SAI1_RXD7 : AF19," & "SAI1_RXFS : AG16," & "SAI1_TXC : AC18," & "SAI1_TXD0 : AG20," & "SAI1_TXD1 : AF20," & "SAI1_TXD2 : AG21," & "SAI1_TXD3 : AF21," & "SAI1_TXD4 : AG22," & "SAI1_TXD5 : AF22," & "SAI1_TXD6 : AG23," & "SAI1_TXD7 : AF23," & "SAI1_TXFS : AB19," & "SAI2_MCLK : AD19," & "SAI2_RXC : AB22," & "SAI2_RXD0 : AC24," & "SAI2_RXFS : AC19," & "SAI2_TXC : AD22," & "SAI2_TXD0 : AC22," & "SAI2_TXFS : AD23," & "SAI3_MCLK : AD6," & "SAI3_RXC : AG7," & "SAI3_RXD : AF7," & "SAI3_RXFS : AG8," & "SAI3_TXC : AG6," & "SAI3_TXD : AF6," & "SAI3_TXFS : AC6," & "SAI5_MCLK : AD15," & "SAI5_RXC : AC15," & "SAI5_RXD0 : AD18," & "SAI5_RXD1 : AC14," & "SAI5_RXD2 : AD13," & "SAI5_RXD3 : AC13," & "SAI5_RXFS : AB15," & "SD1_CLK : V26," & "SD1_CMD : V27," & "SD1_DATA0 : Y27," & "SD1_DATA1 : Y26," & "SD1_DATA2 : T27," & "SD1_DATA3 : T26," & "SD1_DATA4 : U27," & "SD1_DATA5 : U26," & "SD1_DATA6 : W27," & "SD1_DATA7 : W26," & "SD1_RESET_B : R23," & "SD1_STROBE : R24," & "SD2_CD_B : AA26," & "SD2_CLK : W23," & "SD2_CMD : W24," & "SD2_DATA0 : AB23," & "SD2_DATA1 : AB24," & "SD2_DATA2 : V24," & "SD2_DATA3 : V23," & "SD2_RESET_B : AB26," & "SD2_WP : AA27," & "SPDIF_EXT_CLK : AF8," & "SPDIF_RX : AG9," & "SPDIF_TX : AF9," & "UART1_RXD : E14," & "UART1_TXD : F13," & "UART2_RXD : F15," & "UART2_TXD : E15," & "UART3_RXD : E18," & "UART3_TXD : D18," & "UART4_RXD : F19," & "UART4_TXD : F18," & "JTAG_TDO : E26," & "DRAM_RESET_N : R1," & "BOOT_MODE0 : G26," & "BOOT_MODE1 : G27," & "DRAM_VREF : P1," & "DRAM_ZN : P2," & "JTAG_MOD : D27," & "ONOFF : A25," & "PMIC_ON_REQ : A24," & "PMIC_STBY_REQ : E24," & "POR_B : B24," & "RTC_RESET_B : F24," & "TEST_MODE : D26," & "XTALI_24M : B27," & "RTC_XTALI : A26," & "XTALO_24M : C26," & "RTC_XTALO : B25"; -- This section specifies the TAP ports. For the TAP TCK port, the parameters -- in the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of JTAG_TCK : signal is (10.0e6, BOTH); attribute TAP_SCAN_IN of JTAG_TDI : signal is true; attribute TAP_SCAN_MODE of JTAG_TMS : signal is true; attribute TAP_SCAN_OUT of JTAG_TDO : signal is true; attribute TAP_SCAN_RESET of JTAG_TRST_B: signal is true; -- Specifies the compliance enable patterns for the design. It lists a set of -- design ports and the values that they should be set to, in order to enable -- compliance to IEEE Std 1149.1 -- WDOG_B signal needs to be externally pulled up to NVCC_GPIO1 -- to prevent floating in boundary-scan mode attribute COMPLIANCE_PATTERNS of IMX8MM: entity is "(BOOT_MODE0, BOOT_MODE1, JTAG_MOD, TEST_MODE) (1101)"; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of IMX8MM: entity is 5; -- Specifies the boundary-scan instructions implemented in the design and -- their opcodes. attribute INSTRUCTION_OPCODE of IMX8MM: entity is "BYPASS (01111, 11111)," & "EXTEST (00010)," & "SAMPLE (00011)," & "PRELOAD (00011)," & "CLAMP (00110)," & "IDCODE (00100)," & "USERCODE (00101)"; -- Specifies the bit pattern that is loaded into the instruction register when -- the TAP controller passes through the Capture-IR state. The standard -- mandates that the two LSBs must be "01". The remaining bits are design -- specific. attribute INSTRUCTION_CAPTURE of IMX8MM: entity is "00001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID register during -- the IDCODE instruction when the TAP controller passes through the Capture- -- DR state. attribute IDCODE_REGISTER of IMX8MM: entity is "0001" & -- 4-bit version number "1100111110000000" & -- 16-bit part number "01010101001" & -- 11-bit identity of the manufacturer "1"; -- Required by IEEE Std 1149.1 attribute USERCODE_REGISTER of IMX8MM: entity is "1111" & "1100" & "1100" & "0000" & "1110" & "0101" & "0101" & "0000"; -- This section specifies the test data register placed between TDI and TDO -- for each implemented instruction. attribute REGISTER_ACCESS of IMX8MM: entity is "BYPASS (BYPASS, CLAMP)," & "BOUNDARY (EXTEST, SAMPLE, PRELOAD)," & "DEVICE_ID (IDCODE, USERCODE)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of IMX8MM: entity is 453; -- The following list specifies the characteristics of each cell in the -- boundary scan register from TDI to TDO. The following is a description of -- the label fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not have a port -- name. -- function: Is the function of the cell as defined by the standard. Is -- one of input, output2, output3, bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be loaded with -- for safe operation when the software might otherwise choose -- a random value. -- ccell : The control cell number. Specifies the control cell that -- drives the output enable for this port. -- disval : Specifies the value that is loaded into the control cell to -- disable the output enable for the corresponding port. -- rslt : Resulting state. Shows the state of the driver when it is -- disabled. attribute BOUNDARY_REGISTER of IMX8MM: entity is -- -- num cell port function safe [ccell disval rslt] -- "452 (BC_2, *, control, 0), " & "451 (BC_7, SAI3_RXFS, bidir, X, 452, 0, Z), " & "450 (BC_2, *, control, 0), " & "449 (BC_7, SAI3_TXD, bidir, X, 450, 0, Z), " & "448 (BC_2, *, control, 0), " & "447 (BC_7, SAI3_TXC, bidir, X, 448, 0, Z), " & "446 (BC_2, *, control, 0), " & "445 (BC_7, SPDIF_EXT_CLK, bidir, X, 446, 0, Z), " & "444 (BC_2, *, control, 0), " & "443 (BC_7, SAI3_MCLK, bidir, X, 444, 0, Z), " & "442 (BC_2, *, control, 0), " & "441 (BC_7, SAI3_RXC, bidir, X, 442, 0, Z), " & "440 (BC_2, *, control, 0), " & "439 (BC_7, SPDIF_RX, bidir, X, 440, 0, Z), " & "438 (BC_2, *, control, 0), " & "437 (BC_7, SAI3_RXD, bidir, X, 438, 0, Z), " & "436 (BC_2, *, control, 0), " & "435 (BC_7, SAI3_TXFS, bidir, X, 436, 0, Z), " & "434 (BC_2, *, control, 0), " & "433 (BC_7, SPDIF_TX, bidir, X, 434, 0, Z), " & "432 (BC_2, *, control, 0), " & "431 (BC_7, GPIO1_IO00, bidir, X, 432, 0, Z), " & "430 (BC_2, *, control, 0), " & "429 (BC_7, GPIO1_IO04, bidir, X, 430, 0, Z), " & "428 (BC_2, *, control, 0), " & "427 (BC_7, GPIO1_IO01, bidir, X, 428, 0, Z), " & "426 (BC_2, *, control, 0), " & "425 (BC_7, GPIO1_IO05, bidir, X, 426, 0, Z), " & "424 (BC_2, *, control, 0), " & "423 (BC_7, GPIO1_IO02, bidir, X, 424, 0, Z), " & "422 (BC_2, *, control, 0), " & "421 (BC_7, GPIO1_IO06, bidir, X, 422, 0, Z), " & "420 (BC_2, *, control, 0), " & "419 (BC_7, GPIO1_IO03, bidir, X, 420, 0, Z), " & "418 (BC_2, *, control, 0), " & "417 (BC_7, GPIO1_IO07, bidir, X, 418, 0, Z), " & "416 (BC_2, *, control, 0), " & "415 (BC_7, GPIO1_IO08, bidir, X, 416, 0, Z), " & "414 (BC_2, *, control, 0), " & "413 (BC_7, GPIO1_IO12, bidir, X, 414, 0, Z), " & "412 (BC_2, *, control, 0), " & "411 (BC_7, GPIO1_IO09, bidir, X, 412, 0, Z), " & "410 (BC_2, *, control, 0), " & "409 (BC_7, GPIO1_IO13, bidir, X, 410, 0, Z), " & "408 (BC_2, *, control, 0), " & "407 (BC_7, GPIO1_IO10, bidir, X, 408, 0, Z), " & "406 (BC_2, *, control, 0), " & "405 (BC_7, GPIO1_IO14, bidir, X, 406, 0, Z), " & "404 (BC_2, *, control, 0), " & "403 (BC_7, GPIO1_IO11, bidir, X, 404, 0, Z), " & "402 (BC_2, *, control, 0), " & "401 (BC_7, GPIO1_IO15, bidir, X, 402, 0, Z), " & "400 (BC_2, *, control, 0), " & "399 (BC_7, SAI5_MCLK, bidir, X, 400, 0, Z), " & "398 (BC_2, *, control, 0), " & "397 (BC_7, SAI5_RXD2, bidir, X, 398, 0, Z), " & "396 (BC_2, *, control, 0), " & "395 (BC_7, SAI5_RXC, bidir, X, 396, 0, Z), " & "394 (BC_2, *, control, 0), " & "393 (BC_7, SAI5_RXD3, bidir, X, 394, 0, Z), " & "392 (BC_2, *, control, 0), " & "391 (BC_7, SAI5_RXD0, bidir, X, 392, 0, Z), " & "390 (BC_2, *, control, 0), " & "389 (BC_7, SAI5_RXFS, bidir, X, 390, 0, Z), " & "388 (BC_2, *, control, 0), " & "387 (BC_7, SAI5_RXD1, bidir, X, 388, 0, Z), " & "386 (BC_2, *, control, 0), " & "385 (BC_7, SAI1_RXD2, bidir, X, 386, 0, Z), " & "384 (BC_2, *, control, 0), " & "383 (BC_7, SAI1_RXFS, bidir, X, 384, 0, Z), " & "382 (BC_2, *, control, 0), " & "381 (BC_7, SAI1_RXC, bidir, X, 382, 0, Z), " & "380 (BC_2, *, control, 0), " & "379 (BC_7, SAI1_RXD3, bidir, X, 380, 0, Z), " & "378 (BC_2, *, control, 0), " & "377 (BC_7, SAI1_RXD0, bidir, X, 378, 0, Z), " & "376 (BC_2, *, control, 0), " & "375 (BC_7, SAI1_RXD4, bidir, X, 376, 0, Z), " & "374 (BC_2, *, control, 0), " & "373 (BC_7, SAI1_RXD1, bidir, X, 374, 0, Z), " & "372 (BC_2, *, control, 0), " & "371 (BC_7, SAI1_RXD5, bidir, X, 372, 0, Z), " & "370 (BC_2, *, control, 0), " & "369 (BC_7, SAI1_RXD6, bidir, X, 370, 0, Z), " & "368 (BC_2, *, control, 0), " & "367 (BC_7, SAI1_TXD1, bidir, X, 368, 0, Z), " & "366 (BC_2, *, control, 0), " & "365 (BC_7, SAI1_RXD7, bidir, X, 366, 0, Z), " & "364 (BC_2, *, control, 0), " & "363 (BC_7, SAI1_TXD2, bidir, X, 364, 0, Z), " & "362 (BC_2, *, control, 0), " & "361 (BC_7, SAI1_TXC, bidir, X, 362, 0, Z), " & "360 (BC_2, *, control, 0), " & "359 (BC_7, SAI1_TXD3, bidir, X, 360, 0, Z), " & "358 (BC_2, *, control, 0), " & "357 (BC_7, SAI1_TXD0, bidir, X, 358, 0, Z), " & "356 (BC_2, *, control, 0), " & "355 (BC_7, SAI1_TXFS, bidir, X, 356, 0, Z), " & "354 (BC_2, *, control, 0), " & "353 (BC_7, SAI1_MCLK, bidir, X, 354, 0, Z), " & "352 (BC_2, *, control, 0), " & "351 (BC_7, SAI1_TXD7, bidir, X, 352, 0, Z), " & "350 (BC_2, *, control, 0), " & "349 (BC_7, SAI1_TXD4, bidir, X, 350, 0, Z), " & "348 (BC_2, *, control, 0), " & "347 (BC_7, SAI1_TXD5, bidir, X, 348, 0, Z), " & "346 (BC_2, *, control, 0), " & "345 (BC_7, SAI1_TXD6, bidir, X, 346, 0, Z), " & "344 (BC_2, *, control, 0), " & "343 (BC_7, SAI2_MCLK, bidir, X, 344, 0, Z), " & "342 (BC_2, *, control, 0), " & "341 (BC_7, SAI2_TXC, bidir, X, 342, 0, Z), " & "340 (BC_2, *, control, 0), " & "339 (BC_7, SAI2_RXC, bidir, X, 340, 0, Z), " & "338 (BC_2, *, control, 0), " & "337 (BC_7, SAI2_TXD0, bidir, X, 338, 0, Z), " & "336 (BC_2, *, control, 0), " & "335 (BC_7, SAI2_RXD0, bidir, X, 336, 0, Z), " & "334 (BC_2, *, control, 0), " & "333 (BC_7, SAI2_TXFS, bidir, X, 334, 0, Z), " & "332 (BC_2, *, control, 0), " & "331 (BC_7, SAI2_RXFS, bidir, X, 332, 0, Z), " & "330 (BC_2, *, control, 0), " & "329 (BC_7, ENET_RD1, bidir, X, 330, 0, Z), " & "328 (BC_2, *, control, 0), " & "327 (BC_7, ENET_RX_CTL, bidir, X, 328, 0, Z), " & "326 (BC_2, *, control, 0), " & "325 (BC_7, ENET_RD2, bidir, X, 326, 0, Z), " & "324 (BC_2, *, control, 0), " & "323 (BC_7, ENET_RXC, bidir, X, 324, 0, Z), " & "322 (BC_2, *, control, 0), " & "321 (BC_7, ENET_RD3, bidir, X, 322, 0, Z), " & "320 (BC_2, *, control, 0), " & "319 (BC_7, ENET_RD0, bidir, X, 320, 0, Z), " & "318 (BC_2, *, control, 0), " & "317 (BC_7, ENET_TXC, bidir, X, 318, 0, Z), " & "316 (BC_2, *, control, 0), " & "315 (BC_7, ENET_TD2, bidir, X, 316, 0, Z), " & "314 (BC_2, *, control, 0), " & "313 (BC_7, ENET_TX_CTL, bidir, X, 314, 0, Z), " & "312 (BC_2, *, control, 0), " & "311 (BC_7, ENET_TD3, bidir, X, 312, 0, Z), " & "310 (BC_2, *, control, 0), " & "309 (BC_7, ENET_TD0, bidir, X, 310, 0, Z), " & "308 (BC_2, *, control, 0), " & "307 (BC_7, ENET_MDIO, bidir, X, 308, 0, Z), " & "306 (BC_2, *, control, 0), " & "305 (BC_7, ENET_TD1, bidir, X, 306, 0, Z), " & "304 (BC_2, *, control, 0), " & "303 (BC_7, ENET_MDC, bidir, X, 304, 0, Z), " & "302 (BC_2, *, control, 0), " & "301 (BC_7, SD2_RESET_B, bidir, X, 302, 0, Z), " & "300 (BC_2, *, control, 0), " & "299 (BC_7, SD2_DATA0, bidir, X, 300, 0, Z), " & "298 (BC_2, *, control, 0), " & "297 (BC_7, SD2_DATA3, bidir, X, 298, 0, Z), " & "296 (BC_2, *, control, 0), " & "295 (BC_7, SD2_CMD, bidir, X, 296, 0, Z), " & "294 (BC_2, *, control, 0), " & "293 (BC_7, SD2_DATA2, bidir, X, 294, 0, Z), " & "292 (BC_2, *, control, 0), " & "291 (BC_7, SD2_CLK, bidir, X, 292, 0, Z), " & "290 (BC_2, *, control, 0), " & "289 (BC_7, SD2_DATA1, bidir, X, 290, 0, Z), " & "288 (BC_2, *, control, 0), " & "287 (BC_7, SD2_CD_B, bidir, X, 288, 0, Z), " & "286 (BC_2, *, control, 0), " & "285 (BC_7, SD2_WP, bidir, X, 286, 0, Z), " & "284 (BC_2, *, control, 0), " & "283 (BC_7, SD1_DATA6, bidir, X, 284, 0, Z), " & "282 (BC_2, *, control, 0), " & "281 (BC_7, SD1_DATA5, bidir, X, 282, 0, Z), " & "280 (BC_2, *, control, 0), " & "279 (BC_7, SD1_STROBE, bidir, X, 280, 0, Z), " & "278 (BC_2, *, control, 0), " & "277 (BC_7, SD1_CMD, bidir, X, 278, 0, Z), " & "276 (BC_2, *, control, 0), " & "275 (BC_7, SD1_RESET_B, bidir, X, 276, 0, Z), " & "274 (BC_2, *, control, 0), " & "273 (BC_7, SD1_CLK, bidir, X, 274, 0, Z), " & "272 (BC_2, *, control, 0), " & "271 (BC_7, SD1_DATA4, bidir, X, 272, 0, Z), " & "270 (BC_2, *, control, 0), " & "269 (BC_7, SD1_DATA3, bidir, X, 270, 0, Z), " & "268 (BC_2, *, control, 0), " & "267 (BC_7, SD1_DATA2, bidir, X, 268, 0, Z), " & "266 (BC_2, *, control, 0), " & "265 (BC_7, SD1_DATA0, bidir, X, 266, 0, Z), " & "264 (BC_2, *, control, 0), " & "263 (BC_7, SD1_DATA7, bidir, X, 264, 0, Z), " & "262 (BC_2, *, control, 0), " & "261 (BC_7, SD1_DATA1, bidir, X, 262, 0, Z), " & "260 (BC_2, *, control, 0), " & "259 (BC_7, NAND_DATA06, bidir, X, 260, 0, Z), " & "258 (BC_2, *, control, 0), " & "257 (BC_7, NAND_CE0_B, bidir, X, 258, 0, Z), " & "256 (BC_2, *, control, 0), " & "255 (BC_7, NAND_DATA02, bidir, X, 256, 0, Z), " & "254 (BC_2, *, control, 0), " & "253 (BC_7, NAND_DATA00, bidir, X, 254, 0, Z), " & "252 (BC_2, *, control, 0), " & "251 (BC_7, NAND_DATA04, bidir, X, 252, 0, Z), " & "250 (BC_2, *, control, 0), " & "249 (BC_7, NAND_CLE, bidir, X, 250, 0, Z), " & "248 (BC_2, *, control, 0), " & "247 (BC_7, NAND_DATA03, bidir, X, 248, 0, Z), " & "246 (BC_2, *, control, 0), " & "245 (BC_7, NAND_CE3_B, bidir, X, 246, 0, Z), " & "244 (BC_2, *, control, 0), " & "243 (BC_7, NAND_CE2_B, bidir, X, 244, 0, Z), " & "242 (BC_2, *, control, 0), " & "241 (BC_7, NAND_CE1_B, bidir, X, 242, 0, Z), " & "240 (BC_2, *, control, 0), " & "239 (BC_7, NAND_WP_B, bidir, X, 240, 0, Z), " & "238 (BC_2, *, control, 0), " & "237 (BC_7, NAND_READY_B, bidir, X, 238, 0, Z), " & "236 (BC_2, *, control, 0), " & "235 (BC_7, NAND_RE_B, bidir, X, 236, 0, Z), " & "234 (BC_2, *, control, 0), " & "233 (BC_7, NAND_DATA05, bidir, X, 234, 0, Z), " & "232 (BC_2, *, control, 0), " & "231 (BC_7, NAND_DQS, bidir, X, 232, 0, Z), " & "230 (BC_2, *, control, 0), " & "229 (BC_7, NAND_DATA01, bidir, X, 230, 0, Z), " & "228 (BC_2, *, control, 0), " & "227 (BC_7, NAND_DATA07, bidir, X, 228, 0, Z), " & "226 (BC_2, *, control, 0), " & "225 (BC_7, NAND_ALE, bidir, X, 226, 0, Z), " & "224 (BC_2, *, control, 0), " & "223 (BC_7, NAND_WE_B, bidir, X, 224, 0, Z), " & "222 (BC_2, CLKOUT2, input, X), " & "221 (BC_2, CLKOUT1, input, X), " & "220 (BC_2, CLKIN2, input, X), " & "219 (BC_2, CLKIN1, input, X), " & "218 (BC_2, *, control, 0), " & "217 (BC_7, UART4_RXD, bidir, X, 218, 0, Z), " & "216 (BC_2, *, control, 0), " & "215 (BC_7, UART3_RXD, bidir, X, 216, 0, Z), " & "214 (BC_2, *, control, 0), " & "213 (BC_7, UART2_RXD, bidir, X, 214, 0, Z), " & "212 (BC_2, *, control, 0), " & "211 (BC_7, UART1_RXD, bidir, X, 212, 0, Z), " & "210 (BC_2, *, control, 0), " & "209 (BC_7, UART4_TXD, bidir, X, 210, 0, Z), " & "208 (BC_2, *, control, 0), " & "207 (BC_7, UART3_TXD, bidir, X, 208, 0, Z), " & "206 (BC_2, *, control, 0), " & "205 (BC_7, UART2_TXD, bidir, X, 206, 0, Z), " & "204 (BC_2, *, control, 0), " & "203 (BC_7, UART1_TXD, bidir, X, 204, 0, Z), " & "202 (BC_2, *, control, 0), " & "201 (BC_7, I2C2_SCL, bidir, X, 202, 0, Z), " & "200 (BC_2, *, control, 0), " & "199 (BC_7, I2C1_SCL, bidir, X, 200, 0, Z), " & "198 (BC_2, *, control, 0), " & "197 (BC_7, I2C4_SDA, bidir, X, 198, 0, Z), " & "196 (BC_2, *, control, 0), " & "195 (BC_7, I2C3_SDA, bidir, X, 196, 0, Z), " & "194 (BC_2, *, control, 0), " & "193 (BC_7, I2C2_SDA, bidir, X, 194, 0, Z), " & "192 (BC_2, *, control, 0), " & "191 (BC_7, I2C1_SDA, bidir, X, 192, 0, Z), " & "190 (BC_2, *, control, 0), " & "189 (BC_7, I2C4_SCL, bidir, X, 190, 0, Z), " & "188 (BC_2, *, control, 0), " & "187 (BC_7, I2C3_SCL, bidir, X, 188, 0, Z), " & "186 (BC_2, *, control, 0), " & "185 (BC_7, ECSPI2_MOSI, bidir, X, 186, 0, Z), " & "184 (BC_2, *, control, 0), " & "183 (BC_7, ECSPI2_SS0, bidir, X, 184, 0, Z), " & "182 (BC_2, *, control, 0), " & "181 (BC_7, ECSPI1_SS0, bidir, X, 182, 0, Z), " & "180 (BC_2, *, control, 0), " & "179 (BC_7, ECSPI1_SCLK, bidir, X, 180, 0, Z), " & "178 (BC_2, *, control, 0), " & "177 (BC_7, ECSPI1_MISO, bidir, X, 178, 0, Z), " & "176 (BC_2, *, control, 0), " & "175 (BC_7, ECSPI1_MOSI, bidir, X, 176, 0, Z), " & "174 (BC_2, *, control, 0), " & "173 (BC_7, ECSPI2_MISO, bidir, X, 174, 0, Z), " & "172 (BC_2, *, control, 0), " & "171 (BC_7, ECSPI2_SCLK, bidir, X, 172, 0, Z), " & "170 (BC_2, *, control, 0), " & "169 (BC_7, DRAM_DQ00, bidir, X, 170, 0, Z), " & "168 (BC_2, *, control, 0), " & "167 (BC_7, DRAM_DQ01, bidir, X, 168, 0, Z), " & "166 (BC_2, *, control, 0), " & "165 (BC_7, DRAM_DQ02, bidir, X, 166, 0, Z), " & "164 (BC_2, *, control, 0), " & "163 (BC_7, DRAM_DQ03, bidir, X, 164, 0, Z), " & "162 (BC_2, *, control, 0), " & "161 (BC_7, DRAM_DQS0_P, bidir, X, 162, 0, Z), " & "160 (BC_2, *, control, 0), " & "159 (BC_7, DRAM_DQS0_N, bidir, X, 160, 0, Z), " & "158 (BC_2, *, control, 0), " & "157 (BC_7, DRAM_DM0, bidir, X, 158, 0, Z), " & "156 (BC_2, *, control, 0), " & "155 (BC_7, DRAM_DQ04, bidir, X, 156, 0, Z), " & "154 (BC_2, *, control, 0), " & "153 (BC_7, DRAM_DQ05, bidir, X, 154, 0, Z), " & "152 (BC_2, *, control, 0), " & "151 (BC_7, DRAM_DQ06, bidir, X, 152, 0, Z), " & "150 (BC_2, *, control, 0), " & "149 (BC_7, DRAM_DQ07, bidir, X, 150, 0, Z), " & "148 (BC_2, *, control, 0), " & "147 (BC_7, DRAM_DQ08, bidir, X, 148, 0, Z), " & "146 (BC_2, *, control, 0), " & "145 (BC_7, DRAM_DQ09, bidir, X, 146, 0, Z), " & "144 (BC_2, *, control, 0), " & "143 (BC_7, DRAM_DQ10, bidir, X, 144, 0, Z), " & "142 (BC_2, *, control, 0), " & "141 (BC_7, DRAM_DQ11, bidir, X, 142, 0, Z), " & "140 (BC_2, *, control, 0), " & "139 (BC_7, DRAM_DQS1_P, bidir, X, 140, 0, Z), " & "138 (BC_2, *, control, 0), " & "137 (BC_7, DRAM_DQS1_N, bidir, X, 138, 0, Z), " & "136 (BC_2, *, control, 0), " & "135 (BC_7, DRAM_DM1, bidir, X, 136, 0, Z), " & "134 (BC_2, *, control, 0), " & "133 (BC_7, DRAM_DQ12, bidir, X, 134, 0, Z), " & "132 (BC_2, *, control, 0), " & "131 (BC_7, DRAM_DQ13, bidir, X, 132, 0, Z), " & "130 (BC_2, *, control, 0), " & "129 (BC_7, DRAM_DQ14, bidir, X, 130, 0, Z), " & "128 (BC_2, *, control, 0), " & "127 (BC_7, DRAM_DQ15, bidir, X, 128, 0, Z), " & "126 (BC_2, *, control, 0), " & "125 (BC_7, DRAM_AC00, bidir, X, 126, 0, Z), " & "124 (BC_2, *, control, 0), " & "123 (BC_7, DRAM_AC01, bidir, X, 124, 0, Z), " & "122 (BC_2, *, control, 0), " & "121 (BC_7, DRAM_AC02, bidir, X, 122, 0, Z), " & "120 (BC_2, *, control, 0), " & "119 (BC_7, DRAM_AC03, bidir, X, 120, 0, Z), " & "118 (BC_2, *, control, 0), " & "117 (BC_7, DRAM_AC04, bidir, X, 118, 0, Z), " & "116 (BC_2, *, control, 0), " & "115 (BC_7, DRAM_AC05, bidir, X, 116, 0, Z), " & "114 (BC_2, *, control, 0), " & "113 (BC_7, DRAM_AC06, bidir, X, 114, 0, Z), " & "112 (BC_2, *, control, 0), " & "111 (BC_7, DRAM_AC07, bidir, X, 112, 0, Z), " & "110 (BC_2, *, control, 0), " & "109 (BC_7, DRAM_AC08, bidir, X, 110, 0, Z), " & "108 (BC_2, *, control, 0), " & "107 (BC_7, DRAM_AC09, bidir, X, 108, 0, Z), " & "106 (BC_2, *, control, 0), " & "105 (BC_7, DRAM_AC10, bidir, X, 106, 0, Z), " & "104 (BC_2, *, control, 0), " & "103 (BC_7, DRAM_AC11, bidir, X, 104, 0, Z), " & "102 (BC_2, *, control, 0), " & "101 (BC_7, DRAM_AC12, bidir, X, 102, 0, Z), " & "100 (BC_2, *, control, 0), " & "99 (BC_7, DRAM_AC13, bidir, X, 100, 0, Z), " & "98 (BC_2, *, control, 0), " & "97 (BC_7, DRAM_AC14, bidir, X, 98, 0, Z), " & "96 (BC_2, *, control, 0), " & "95 (BC_7, DRAM_AC15, bidir, X, 96, 0, Z), " & "94 (BC_2, *, control, 0), " & "93 (BC_7, DRAM_AC16, bidir, X, 94, 0, Z), " & "92 (BC_2, *, control, 0), " & "91 (BC_7, DRAM_AC17, bidir, X, 92, 0, Z), " & "90 (BC_0, *, internal, X), " & "89 (BC_0, *, internal, X), " & "88 (BC_2, *, control, 0), " & "87 (BC_7, DRAM_AC19, bidir, X, 88, 0, Z), " & "86 (BC_2, DRAM_RESET_N, output2, X), " & "85 (BC_2, *, control, 0), " & "84 (BC_7, DRAM_ALERT_N, bidir, X, 85, 0, Z), " & "83 (BC_2, *, control, 0), " & "82 (BC_7, DRAM_AC20, bidir, X, 83, 0, Z), " & "81 (BC_2, *, control, 0), " & "80 (BC_7, DRAM_AC21, bidir, X, 81, 0, Z), " & "79 (BC_2, *, control, 0), " & "78 (BC_7, DRAM_AC22, bidir, X, 79, 0, Z), " & "77 (BC_2, *, control, 0), " & "76 (BC_7, DRAM_AC23, bidir, X, 77, 0, Z), " & "75 (BC_2, *, control, 0), " & "74 (BC_7, DRAM_AC24, bidir, X, 75, 0, Z), " & "73 (BC_2, *, control, 0), " & "72 (BC_7, DRAM_AC25, bidir, X, 73, 0, Z), " & "71 (BC_2, *, control, 0), " & "70 (BC_7, DRAM_AC26, bidir, X, 71, 0, Z), " & "69 (BC_2, *, control, 0), " & "68 (BC_7, DRAM_AC27, bidir, X, 69, 0, Z), " & "67 (BC_2, *, control, 0), " & "66 (BC_7, DRAM_AC28, bidir, X, 67, 0, Z), " & "65 (BC_2, *, control, 0), " & "64 (BC_7, DRAM_AC29, bidir, X, 65, 0, Z), " & "63 (BC_2, *, control, 0), " & "62 (BC_7, DRAM_AC30, bidir, X, 63, 0, Z), " & "61 (BC_2, *, control, 0), " & "60 (BC_7, DRAM_AC31, bidir, X, 61, 0, Z), " & "59 (BC_2, *, control, 0), " & "58 (BC_7, DRAM_AC32, bidir, X, 59, 0, Z), " & "57 (BC_2, *, control, 0), " & "56 (BC_7, DRAM_AC33, bidir, X, 57, 0, Z), " & "55 (BC_2, *, control, 0), " & "54 (BC_7, DRAM_AC34, bidir, X, 55, 0, Z), " & "53 (BC_2, *, control, 0), " & "52 (BC_7, DRAM_AC35, bidir, X, 53, 0, Z), " & "51 (BC_2, *, control, 0), " & "50 (BC_7, DRAM_AC36, bidir, X, 51, 0, Z), " & "49 (BC_2, *, control, 0), " & "48 (BC_7, DRAM_AC37, bidir, X, 49, 0, Z), " & "47 (BC_2, *, control, 0), " & "46 (BC_7, DRAM_AC38, bidir, X, 47, 0, Z), " & "45 (BC_0, *, internal, X), " & "44 (BC_0, *, internal, X), " & "43 (BC_2, *, control, 0), " & "42 (BC_7, DRAM_DQ16, bidir, X, 43, 0, Z), " & "41 (BC_2, *, control, 0), " & "40 (BC_7, DRAM_DQ17, bidir, X, 41, 0, Z), " & "39 (BC_2, *, control, 0), " & "38 (BC_7, DRAM_DQ18, bidir, X, 39, 0, Z), " & "37 (BC_2, *, control, 0), " & "36 (BC_7, DRAM_DQ19, bidir, X, 37, 0, Z), " & "35 (BC_2, *, control, 0), " & "34 (BC_7, DRAM_DQS2_P, bidir, X, 35, 0, Z), " & "33 (BC_2, *, control, 0), " & "32 (BC_7, DRAM_DQS2_N, bidir, X, 33, 0, Z), " & "31 (BC_2, *, control, 0), " & "30 (BC_7, DRAM_DM2, bidir, X, 31, 0, Z), " & "29 (BC_2, *, control, 0), " & "28 (BC_7, DRAM_DQ20, bidir, X, 29, 0, Z), " & "27 (BC_2, *, control, 0), " & "26 (BC_7, DRAM_DQ21, bidir, X, 27, 0, Z), " & "25 (BC_2, *, control, 0), " & "24 (BC_7, DRAM_DQ22, bidir, X, 25, 0, Z), " & "23 (BC_2, *, control, 0), " & "22 (BC_7, DRAM_DQ23, bidir, X, 23, 0, Z), " & "21 (BC_2, *, control, 0), " & "20 (BC_7, DRAM_DQ24, bidir, X, 21, 0, Z), " & "19 (BC_2, *, control, 0), " & "18 (BC_7, DRAM_DQ25, bidir, X, 19, 0, Z), " & "17 (BC_2, *, control, 0), " & "16 (BC_7, DRAM_DQ26, bidir, X, 17, 0, Z), " & "15 (BC_2, *, control, 0), " & "14 (BC_7, DRAM_DQ27, bidir, X, 15, 0, Z), " & "13 (BC_2, *, control, 0), " & "12 (BC_7, DRAM_DQS3_P, bidir, X, 13, 0, Z), " & "11 (BC_2, *, control, 0), " & "10 (BC_7, DRAM_DQS3_N, bidir, X, 11, 0, Z), " & "9 (BC_2, *, control, 0), " & "8 (BC_7, DRAM_DM3, bidir, X, 9, 0, Z), " & "7 (BC_2, *, control, 0), " & "6 (BC_7, DRAM_DQ28, bidir, X, 7, 0, Z), " & "5 (BC_2, *, control, 0), " & "4 (BC_7, DRAM_DQ29, bidir, X, 5, 0, Z), " & "3 (BC_2, *, control, 0), " & "2 (BC_7, DRAM_DQ30, bidir, X, 3, 0, Z), " & "1 (BC_2, *, control, 0), " & "0 (BC_7, DRAM_DQ31, bidir, X, 1, 0, Z) "; end IMX8MM;