Register Definitions for Rc663

Register definitions for Rc663. More...

Collaboration diagram for Register Definitions for Rc663:

Modules
	Rc663 User Configuration
	Custom Configuration of hardware related settings.

Macros
#define	PHHAL_HW_SAMAV3_RC663_REG_COMMAND   0x00
	Command Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_HOSTCTRL   0x01
	Host-Control Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_ERROR   0x0A
	Error Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_STATUS   0x0B
	Status Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_RXBITCTRL   0x0C
	Rx-Bit-Control Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_RXCOLL   0x0D
	Rx-Coll Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_DRVMODE   0x28
	Driver Mode Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_TXAMP   0x29
	Tx Amplifier Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_DRVCON   0x2A
	Driver Control Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_TXI   0x2B
	TxI Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_TXCRCCON   0x2C
	Tx-CRC Control Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_RXCRCCON   0x2D
	Rx-CRC Control Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_TXDATANUM   0x2E
	Tx-DataNum Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_TXMODWIDTH   0x2F
	Tx-Modwidth Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_TXSYM10BURSTLEN   0x30
	Symbol 0 and 1 Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_TXWAITCTRL   0x31
	Tx-Wait Control Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_TXWAITLO   0x32
	TxWaitLo Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_FRAMECON   0x33
	Frame control register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_RXSOFD   0x34
	RxSOFD Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_RXCTRL   0x35
	Rx Control Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_RXWAIT   0x36
	Rx-Wait Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_RXTHRESHOLD   0x37
	Rx-Threshold Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_RCV   0x38
	Receiver Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_RXANA   0x39
	Rx-Analog Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_SERIALSPEED   0x3B
	Serial Speed Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_LPO_TRIMM   0x3C
	LPO_TRIMM Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_PLL_CTRL   0x3D
	PLL Control Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_PLL_DIV   0x3E
	PLL DivO Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_LPCD_QMIN   0x3F
	LPCD QMin Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_LPCD_QMAX   0x40
	LPCD QMax Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_LPCD_IMIN   0x41
	LPCD IMin Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_LPCD_RESULT_I   0x42
	LPCD Result(I) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_LPCD_RESULT_Q   0x43
	LPCD Result(Q) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_VERSION   0x7F
	Version Register. More...

Fifo Registers
#define	PHHAL_HW_SAMAV3_RC663_REG_FIFOCONTROL   0x02
	FIFO-Control Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_WATERLEVEL   0x03
	WaterLevel Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_FIFOLENGTH   0x04
	FIFO-Length Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_FIFODATA   0x05
	FIFO-Data Register. More...

IRQ Registers
#define	PHHAL_HW_SAMAV3_RC663_REG_IRQ0   0x06
	IRQ0 Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_IRQ1   0x07
	IRQ1 Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_IRQ0EN   0x08
	IRQ0EN Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_IRQ1EN   0x09
	IRQ1EN Register. More...

Timer Registers
#define	PHHAL_HW_SAMAV3_RC663_REG_TCONTROL   0x0E
	Timer Control Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T0CONTROL   0x0F
	Timer0 Control Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T0RELOADHI   0x10
	Timer0 Reload(High) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T0RELOADLO   0x11
	Timer0 Reload(Low) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T0COUNTERVALHI   0x12
	Timer0 Counter(High) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T0COUNTERVALLO   0x13
	Timer0 Counter(Low) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T1CONTROL   0x14
	Timer1 Control Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T1RELOADHI   0x15
	Timer1 Reload(High) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T1RELOADLO   0x16
	Timer1 Reload(Low) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T1COUNTERVALHI   0x17
	Timer1 Counter(High) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T1COUNTERVALLO   0x18
	Timer1 Counter(Low) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T2CONTROL   0x19
	Timer2 Control Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T2RELOADHI   0x1A
	Timer2 Reload(High) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T2RELOADLO   0x1B
	Timer2 Reload(Low) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T2COUNTERVALHI   0x1C
	Timer2 Counter(High) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T2COUNTERVALLO   0x1D
	Timer2 Counter(Low) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T3CONTROL   0x1E
	Timer3 Control Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T3RELOADHI   0x1F
	Timer3 Reload(High) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T3RELOADLO   0x20
	Timer3 Reload(Low) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T3COUNTERVALHI   0x21
	Timer3 Counter(High) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T3COUNTERVALLO   0x22
	Timer3 Counter(Low) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T4CONTROL   0x23
	Timer4 Control Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T4RELOADHI   0x24
	Timer4 Reload(High) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T4RELOADLO   0x25
	Timer4 Reload(Low) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T4COUNTERVALHI   0x26
	Timer4 Counter(High) Register. More...
#define	PHHAL_HW_SAMAV3_RC663_REG_T4COUNTERVALLO   0x27
	Timer4 Counter(Low) Register. More...

Command Register Contents (0x00)
#define	PHHAL_HW_SAMAV3_RC663_BIT_STANDBY   0x80U
	Standby bit; If set, the IC transits to standby mode.
#define	PHHAL_HW_SAMAV3_RC663_CMD_IDLE   0x00U
	No action; cancels current command execution.
#define	PHHAL_HW_SAMAV3_RC663_CMD_LPCD   0x01U
	Low Power Card Detection.
#define	PHHAL_HW_SAMAV3_RC663_CMD_LOADKEY   0x02U
	Reads a key from the FIFO buffer and puts it into the key buffer.
#define	PHHAL_HW_SAMAV3_RC663_CMD_MFAUTHENT   0x03U
	Performs the MIFARE standard authentication (in MIFARE Reader/Writer mode only).
#define	PHHAL_HW_SAMAV3_RC663_CMD_ACKREQ   0x04U
	Performs a Query, a Ack and a Req-Rn for EPC V2.
#define	PHHAL_HW_SAMAV3_RC663_CMD_RECEIVE   0x05U
	Activates the receiver circuitry.
#define	PHHAL_HW_SAMAV3_RC663_CMD_TRANSMIT   0x06U
	Transmits data from the FIFO buffer to Card.
#define	PHHAL_HW_SAMAV3_RC663_CMD_TRANSCEIVE   0x07U
	Like PHHAL_HW_SAMAV3_RC663_CMD_TRANSMIT but automatically activates the receiver after transmission is finished.
#define	PHHAL_HW_SAMAV3_RC663_CMD_WRITEE2   0x08U
	Gets one byte from FIFO buffer and writes it to the internal EEPROM.
#define	PHHAL_HW_SAMAV3_RC663_CMD_WRITEE2PAGE   0x09U
	Gets up to 64 Bytes from FIFO buffer and writes it to the EEPROM.
#define	PHHAL_HW_SAMAV3_RC663_CMD_READE2   0x0AU
	Reads data from EEPROM and puts it into the FIFO buffer.
#define	PHHAL_HW_SAMAV3_RC663_CMD_LOADREG   0x0CU
	Reads data from EEPROM and initializes the registers.
#define	PHHAL_HW_SAMAV3_RC663_CMD_LOADPROTOCOL   0x0DU
	Reads data from EEPROM and initializes the registers needed for a protocol change.
#define	PHHAL_HW_SAMAV3_RC663_CMD_LOADKEYE2   0x0EU
	Copies a MIFARE key from the EEPROM into the key buffer.
#define	PHHAL_HW_SAMAV3_RC663_CMD_STOREKEYE2   0x0FU
	Stores a MIFARE key into the EEPROM.
#define	PHHAL_HW_SAMAV3_RC663_CMD_SOFTRESET   0x1FU
	Resets the IC.
#define	PHHAL_HW_SAMAV3_RC663_MASK_COMMAND   0x1FU
	Mask for Command-bits.

Host-Control Register Contents (0x01)
#define	PHHAL_HW_SAMAV3_RC663_BIT_REGEN   0x80U
#define	PHHAL_HW_SAMAV3_RC663_BIT_BUSHOST   0x40U
#define	PHHAL_HW_SAMAV3_RC663_BIT_BUSSAM   0x20U
#define	PHHAL_HW_SAMAV3_RC663_MASK_SAMINTERFACE   0x0CU

FIFO-Control Register Contents (0x02)
#define	PHHAL_HW_SAMAV3_RC663_BIT_FIFOSIZE   0x80U
#define	PHHAL_HW_SAMAV3_RC663_BIT_HIALERT   0x40U
#define	PHHAL_HW_SAMAV3_RC663_BIT_LOALERT   0x20U
#define	PHHAL_HW_SAMAV3_RC663_BIT_FLUSHFIFO   0x10U
#define	PHHAL_HW_SAMAV3_RC663_BIT_WATERLEVEL_HI   0x04U
#define	PHHAL_HW_SAMAV3_RC663_MASK_FIFOLENGTH_HI   0x03U

IRQ0 Register(s) Contents (0x06/0x08)
#define	PHHAL_HW_SAMAV3_RC663_BIT_SET   0x80U
#define	PHHAL_HW_SAMAV3_RC663_BIT_IRQINV   0x80U
#define	PHHAL_HW_SAMAV3_RC663_BIT_HIALERTIRQ   0x40U
#define	PHHAL_HW_SAMAV3_RC663_BIT_LOALERTIRQ   0x20U
#define	PHHAL_HW_SAMAV3_RC663_BIT_IDLEIRQ   0x10U
#define	PHHAL_HW_SAMAV3_RC663_BIT_TXIRQ   0x08U
#define	PHHAL_HW_SAMAV3_RC663_BIT_RXIRQ   0x04U
#define	PHHAL_HW_SAMAV3_RC663_BIT_ERRIRQ   0x02U
#define	PHHAL_HW_SAMAV3_RC663_BIT_EMDIRQ   0x01U

IRQ1 Register(s) Contents (0x07/0x09)
#define	PHHAL_HW_SAMAV3_RC663_BIT_IRQPUSHPULL   0x80U
#define	PHHAL_HW_SAMAV3_RC663_BIT_GLOBALIRQ   0x40U
#define	PHHAL_HW_SAMAV3_RC663_BIT_IRQPINEN   0x40U
#define	PHHAL_HW_SAMAV3_RC663_BIT_LPCDIRQ   0x20U
#define	PHHAL_HW_SAMAV3_RC663_BIT_TIMER4IRQ   0x10U
#define	PHHAL_HW_SAMAV3_RC663_BIT_TIMER3IRQ   0x08U
#define	PHHAL_HW_SAMAV3_RC663_BIT_TIMER2IRQ   0x04U
#define	PHHAL_HW_SAMAV3_RC663_BIT_TIMER1IRQ   0x02U
#define	PHHAL_HW_SAMAV3_RC663_BIT_TIMER0IRQ   0x01U

Error Register Contents (0x0A)
#define	PHHAL_HW_SAMAV3_RC663_BIT_EE_ERR   0x80U
#define	PHHAL_HW_SAMAV3_RC663_BIT_FIFOWRERR   0x40U
#define	PHHAL_HW_SAMAV3_RC663_BIT_FIFOOVL   0x20U
#define	PHHAL_HW_SAMAV3_RC663_BIT_MINFRAMEERR   0x10U
#define	PHHAL_HW_SAMAV3_RC663_BIT_NODATAERR   0x08U
#define	PHHAL_HW_SAMAV3_RC663_BIT_COLLDET   0x04U
#define	PHHAL_HW_SAMAV3_RC663_BIT_PROTERR   0x02U
#define	PHHAL_HW_SAMAV3_RC663_BIT_INTEGERR   0x01U

Status Register Contents (0x0B)
#define	PHHAL_HW_SAMAV3_RC663_BIT_CRYPTO1ON   0x20U
#define	PHHAL_HW_SAMAV3_RC663_MASK_COMMSTATE   0x07U

Rx-Bit-Control Register Contents (0x0C)
#define	PHHAL_HW_SAMAV3_RC663_BIT_VALUESAFTERCOLL   0x80U
#define	PHHAL_HW_SAMAV3_RC663_BIT_NOCOLL   0x08U
#define	PHHAL_HW_SAMAV3_RC663_MASK_RXALIGN   0x70U
#define	PHHAL_HW_SAMAV3_RC663_MASK_RXLASTBITS   0x07U

Rx-Coll Register Contents (0x0D)
#define	PHHAL_HW_SAMAV3_RC663_BIT_COLLPOSVALID   0x80U
#define	PHHAL_HW_SAMAV3_RC663_MASK_COLLPOS   0x7FU

Timer-Control Register Contents (0x0E)
#define	PHHAL_HW_SAMAV3_RC663_BIT_T3RUNNING   0x80U
#define	PHHAL_HW_SAMAV3_RC663_BIT_T2RUNNING   0x40U
#define	PHHAL_HW_SAMAV3_RC663_BIT_T1RUNNING   0x20U
#define	PHHAL_HW_SAMAV3_RC663_BIT_T0RUNNING   0x10U
#define	PHHAL_HW_SAMAV3_RC663_BIT_T3STARTSTOPNOW   0x08U
#define	PHHAL_HW_SAMAV3_RC663_BIT_T2STARTSTOPNOW   0x04U
#define	PHHAL_HW_SAMAV3_RC663_BIT_T1STARTSTOPNOW   0x02U
#define	PHHAL_HW_SAMAV3_RC663_BIT_T0STARTSTOPNOW   0x01U

T[0-3]-Control Register Contents (0x0F/0x14/0x19/0x1E)
#define	PHHAL_HW_SAMAV3_RC663_BIT_TSTOP_RX   0x80U
	Stop timer on receive interrupt.
#define	PHHAL_HW_SAMAV3_RC663_BIT_TAUTORESTARTED   0x08U
	Auto-restart timer after underflow.
#define	PHHAL_HW_SAMAV3_RC663_BIT_TSTART_TX   0x10U
	Start timer on transmit interrupt.
#define	PHHAL_HW_SAMAV3_RC663_BIT_TSTART_LFO   0x20U
	Use this timer for LFO trimming.
#define	PHHAL_HW_SAMAV3_RC663_BIT_TSTART_LFO_UV   0x30U
	Use this timer for LFO trimming (generate UV at a trimming event).
#define	PHHAL_HW_SAMAV3_RC663_MASK_TSTART   0x30U
	Mask for TSTART bits.
#define	PHHAL_HW_SAMAV3_RC663_VALUE_TCLK_1356_MHZ   0x00U
	Use 13.56MHz as input clock.
#define	PHHAL_HW_SAMAV3_RC663_VALUE_TCLK_212_KHZ   0x01U
	Use 212KHz as input clock.
#define	PHHAL_HW_SAMAV3_RC663_VALUE_TCLK_T0   0x02U
	Use timer0 as input clock.
#define	PHHAL_HW_SAMAV3_RC663_VALUE_TCLK_T1   0x03U
	Use timer1 as input clock.

T4-Control Register Contents (0x23)
#define	PHHAL_HW_SAMAV3_RC663_BIT_T4RUNNING   0x80U
#define	PHHAL_HW_SAMAV3_RC663_BIT_T4STARTSTOPNOW   0x40U
#define	PHHAL_HW_SAMAV3_RC663_BIT_T4AUTOTRIMM   0x20U
#define	PHHAL_HW_SAMAV3_RC663_BIT_T4AUTOLPCD   0x10U
#define	PHHAL_HW_SAMAV3_RC663_BIT_T4AUTORESTARTED   0x08U
#define	PHHAL_HW_SAMAV3_RC663_BIT_T4AUTOWAKEUP   0x04U
#define	PHHAL_HW_SAMAV3_RC663_VALUE_TCLK_LFO_64_KHZ   0x00U
#define	PHHAL_HW_SAMAV3_RC663_VALUE_TCLK_LFO_8_KHZ   0x01U
#define	PHHAL_HW_SAMAV3_RC663_VALUE_TCLK_LFO_4_KHZ   0x02U
#define	PHHAL_HW_SAMAV3_RC663_VALUE_TCLK_LFO_2_KHZ   0x03U

Driver Mode Register Contents (0x28)
#define	PHHAL_HW_SAMAV3_RC663_BIT_TX2INV   0x80U
#define	PHHAL_HW_SAMAV3_RC663_BIT_TX1INV   0x40U
#define	PHHAL_HW_SAMAV3_RC663_BIT_TXEN   0x08U
#define	PHHAL_HW_SAMAV3_RC663_BIT_RFON   0x04U
#define	PHHAL_HW_SAMAV3_RC663_BIT_TPUSHON   0x02U
#define	PHHAL_HW_SAMAV3_RC663_BIT_TPULLON   0x01U

Tx Amplifier Register Contents (0x29)
#define	PHHAL_HW_SAMAV3_RC663_MASK_CW_AMPLITUDE   0xF0U
#define	PHHAL_HW_SAMAV3_RC663_MASK_RESIDUAL_CARRIER   0x0FU

Driver Control Register Contents (0x2A)
#define	PHHAL_HW_SAMAV3_RC663_BIT_CWMAX   0x10U
#define	PHHAL_HW_SAMAV3_RC663_BIT_DISOVSHTPREV   0x08U
#define	PHHAL_HW_SAMAV3_RC663_BIT_DRIVERINV   0x04U
#define	PHHAL_HW_SAMAV3_RC663_VALUE_DRIVERSEL_LOW   0x00U
#define	PHHAL_HW_SAMAV3_RC663_VALUE_DRIVERSEL_TXENV   0x01U
#define	PHHAL_HW_SAMAV3_RC663_VALUE_DRIVERSEL_SIGIN   0x02U

Tx-/Rx-CRC Control Register Contents (0x2C/0x2D)
#define	PHHAL_HW_SAMAV3_RC663_BIT_RXFORCECRCWRITE   0x80U
#define	PHHAL_HW_SAMAV3_RC663_BIT_CRCINVERT   0x02U
#define	PHHAL_HW_SAMAV3_RC663_BIT_CRCEN   0x01U
#define	PHHAL_HW_SAMAV3_RC663_MASK_CRCPRESETVAL   0x07U
#define	PHHAL_HW_SAMAV3_RC663_MASK_CRCTYPE   0x0CU

Tx-DataNum Register Contents (0x2E)
#define	PHHAL_HW_SAMAV3_RC663_BIT_KEEPBITGRID   0x10U
#define	PHHAL_HW_SAMAV3_RC663_BIT_DATAEN   0x08U
#define	PHHAL_HW_SAMAV3_RC663_MASK_TXLASTBITS   0x07U

Tx-Wait Control Register Contents (0x31)
#define	PHHAL_HW_SAMAV3_RC663_BIT_TXWAIT_START_RX   0x80U
#define	PHHAL_HW_SAMAV3_RC663_BIT_TXWAIT_DBFREQ   0x40U
#define	PHHAL_HW_SAMAV3_RC663_MASK_TXWAITHI   0x38U
#define	PHHAL_HW_SAMAV3_RC663_MASK_TXSTOPBITLEN   0x07U

Frame Control Register Contents (0x33)
#define	PHHAL_HW_SAMAV3_RC663_BIT_TXPARITYEN   0x80U
#define	PHHAL_HW_SAMAV3_RC663_BIT_RXPARITYEN   0x40U
#define	PHHAL_HW_SAMAV3_RC663_VALUE_STOP_SYM3   0x0CU
#define	PHHAL_HW_SAMAV3_RC663_VALUE_STOP_SYM2   0x08U
#define	PHHAL_HW_SAMAV3_RC663_VALUE_STOP_SYM1   0x04U
#define	PHHAL_HW_SAMAV3_RC663_VALUE_START_SYM2   0x03U
#define	PHHAL_HW_SAMAV3_RC663_VALUE_START_SYM1   0x02U
#define	PHHAL_HW_SAMAV3_RC663_VALUE_START_SYM0   0x01U
#define	PHHAL_HW_SAMAV3_RC663_MASK_STARTSYM   0x03U
#define	PHHAL_HW_SAMAV3_RC663_MASK_STOPSYM   0x0CU

Rx Control Register Contents (0x35)
#define	PHHAL_HW_SAMAV3_RC663_BIT_RXALLOWBITS   0x80U
#define	PHHAL_HW_SAMAV3_RC663_BIT_RXMULTIPLE   0x40U
#define	PHHAL_HW_SAMAV3_RC663_BIT_RXEOFTYPE   0x20U
#define	PHHAL_HW_SAMAV3_RC663_BIT_EGT_CHECK   0x10U
#define	PHHAL_HW_SAMAV3_RC663_BIT_EMD_SUPPRESSION   0x08U
#define	PHHAL_HW_SAMAV3_RC663_MASK_RXBAUDRATE   0x07U

Rx-Wait Register Contents (0x36)
#define	PHHAL_HW_SAMAV3_RC663_BIT_RXWAITDBFREQ   0x80U
#define	PHHAL_HW_SAMAV3_RC663_MASK_RXWAIT   0x7FU

Rx-Threshold Register Contents (0x37)
#define	PHHAL_HW_SAMAV3_RC663_MASK_MINLEVEL   0xF0U
#define	PHHAL_HW_SAMAV3_RC663_MASK_MINLEVELP   0x0FU

Rx-Receiver Register Contents (0x38)
#define	PHHAL_HW_SAMAV3_RC663_BIT_RX_SINGLE   0x80U
#define	PHHAL_HW_SAMAV3_RC663_BIT_RX_SHORT_MIX2ADC   0x40U
#define	PHHAL_HW_SAMAV3_RC663_BIT_USE_SMALL_EVAL   0x04U
#define	PHHAL_HW_SAMAV3_RC663_MASK_RX_SIGPRO_IN_SEL   0x30U
#define	PHHAL_HW_SAMAV3_RC663_MASK_COLLLEVEL   0x03U

Rx-Analog Register Contents (0x39)
#define	PHHAL_HW_SAMAV3_RC663_BIT_RX_OC_ENABLE   0x20U
#define	PHHAL_HW_SAMAV3_RC663_BIT_RX_HP_LOWF   0x10U
#define	PHHAL_HW_SAMAV3_RC663_MASK_VMID_R_SEL   0xC0U
#define	PHHAL_HW_SAMAV3_RC663_MASK_RCV_HPCF   0x0CU
#define	PHHAL_HW_SAMAV3_RC663_MASK_RCV_GAIN   0x03U

Serial-Speed Register Contents (0x3B)
#define	PHHAL_HW_SAMAV3_RC663_MASK_BR_T0   0xE0U
#define	PHHAL_HW_SAMAV3_RC663_MASK_BR_T1   0x1FU

LPCD Result(Q) Register Contents (0x43)
#define	PHHAL_HW_SAMAV3_RC663_BIT_LPCDIRQ_CLR   0x40U

Tx-BitMod Register Contents (0x48)
#define	PHHAL_HW_SAMAV3_RC663_BIT_TXMSBFIRST   0x80U
#define	PHHAL_HW_SAMAV3_RC663_BIT_TXPARITYTYPE   0x20U
#define	PHHAL_HW_SAMAV3_RC663_BIT_TXSTOPBITTYPE   0x08U
#define	PHHAL_HW_SAMAV3_RC663_BIT_TXSTARTBITTYPE   0x02U
#define	PHHAL_HW_SAMAV3_RC663_BIT_TXSTARTBITEN   0x01U

Rx-BitMod Register Contents (0x58)
#define	PHHAL_HW_SAMAV3_RC663_BIT_RXSTOPONINVPAR   0x20U
#define	PHHAL_HW_SAMAV3_RC663_BIT_RXSTOPONLEN   0x10U
#define	PHHAL_HW_SAMAV3_RC663_BIT_RXMSBFIRST   0x08U
#define	PHHAL_HW_SAMAV3_RC663_BIT_RXSTOPBITEN   0x04U
#define	PHHAL_HW_SAMAV3_RC663_BIT_RXPARITYTYPE   0x02U

Rx-Mod Register Contents (0x5D)
#define	PHHAL_HW_SAMAV3_RC663_BIT_PREFILTER   0x20U
#define	PHHAL_HW_SAMAV3_RC663_BIT_RECTFILTER   0x10U
#define	PHHAL_HW_SAMAV3_RC663_BIT_SYNCHIGH   0x08U
#define	PHHAL_HW_SAMAV3_RC663_BIT_CORRINV   0x04U
#define	PHHAL_HW_SAMAV3_RC663_BIT_FSK   0x02U
#define	PHHAL_HW_SAMAV3_RC663_BIT_BPSK   0x01U

Detailed Description

Register definitions for Rc663.

Macro Definition Documentation

PHHAL_HW_SAMAV3_RC663_REG_COMMAND

#define PHHAL_HW_SAMAV3_RC663_REG_COMMAND   0x00

Command Register.

Used for starting / stopping commands and for sending the IC into standby mode.

PHHAL_HW_SAMAV3_RC663_REG_HOSTCTRL

#define PHHAL_HW_SAMAV3_RC663_REG_HOSTCTRL   0x01

Host-Control Register.

Configure Host and SAM interfaces.

PHHAL_HW_SAMAV3_RC663_REG_FIFOCONTROL

#define PHHAL_HW_SAMAV3_RC663_REG_FIFOCONTROL   0x02

FIFO-Control Register.

Set FIFO size and retrieve FIFO parameters.
Note: Also contains 1 additional Water-Level bits (MSB) and 2 additional FIFO-Length bits (also MSB).

PHHAL_HW_SAMAV3_RC663_REG_WATERLEVEL

#define PHHAL_HW_SAMAV3_RC663_REG_WATERLEVEL   0x03

WaterLevel Register.

FIFO WaterLevel configuration.

PHHAL_HW_SAMAV3_RC663_REG_FIFOLENGTH

#define PHHAL_HW_SAMAV3_RC663_REG_FIFOLENGTH   0x04

FIFO-Length Register.

Retrieve the number of bytes within the FIFO.

PHHAL_HW_SAMAV3_RC663_REG_FIFODATA

#define PHHAL_HW_SAMAV3_RC663_REG_FIFODATA   0x05

FIFO-Data Register.

Writing to this register moves a byte into the FIFO while incrementing the FIFO length and raising the internal WaterLevel.

PHHAL_HW_SAMAV3_RC663_REG_IRQ0

#define PHHAL_HW_SAMAV3_RC663_REG_IRQ0   0x06

IRQ0 Register.

Read or modify the first 7 IRQ bits.

PHHAL_HW_SAMAV3_RC663_REG_IRQ1

#define PHHAL_HW_SAMAV3_RC663_REG_IRQ1   0x07

IRQ1 Register.

Read or modify the second 7 IRQ bits.

PHHAL_HW_SAMAV3_RC663_REG_IRQ0EN

#define PHHAL_HW_SAMAV3_RC663_REG_IRQ0EN   0x08

IRQ0EN Register.

Enable or disable the first IRQ bits or invert the IRQ propagation.

PHHAL_HW_SAMAV3_RC663_REG_IRQ1EN

#define PHHAL_HW_SAMAV3_RC663_REG_IRQ1EN   0x09

IRQ1EN Register.

Enable or disable the second IRQ bits or enable/disable PushPull mode.

PHHAL_HW_SAMAV3_RC663_REG_ERROR

#define PHHAL_HW_SAMAV3_RC663_REG_ERROR   0x0A

Error Register.

Contains bits for the occured errors.

PHHAL_HW_SAMAV3_RC663_REG_STATUS

#define PHHAL_HW_SAMAV3_RC663_REG_STATUS   0x0B

Status Register.

Contains the Crypto1 state and information about the ComState.

PHHAL_HW_SAMAV3_RC663_REG_RXBITCTRL

#define PHHAL_HW_SAMAV3_RC663_REG_RXBITCTRL   0x0C

Rx-Bit-Control Register.

Set/Get Bit-granularity and collision information.

PHHAL_HW_SAMAV3_RC663_REG_RXCOLL

#define PHHAL_HW_SAMAV3_RC663_REG_RXCOLL   0x0D

Rx-Coll Register.

Contains information about the collision position after a collision.

PHHAL_HW_SAMAV3_RC663_REG_TCONTROL

#define PHHAL_HW_SAMAV3_RC663_REG_TCONTROL   0x0E

Timer Control Register.

Provides timer control and status information for all timers.

PHHAL_HW_SAMAV3_RC663_REG_T0CONTROL

#define PHHAL_HW_SAMAV3_RC663_REG_T0CONTROL   0x0F

Timer0 Control Register.

Configure the timer.

PHHAL_HW_SAMAV3_RC663_REG_T0RELOADHI

#define PHHAL_HW_SAMAV3_RC663_REG_T0RELOADHI   0x10

Timer0 Reload(High) Register.

Set the most significant byte of the Reload-Value.

PHHAL_HW_SAMAV3_RC663_REG_T0RELOADLO

#define PHHAL_HW_SAMAV3_RC663_REG_T0RELOADLO   0x11

Timer0 Reload(Low) Register.

Set the least significant byte of the Reload-Value.

PHHAL_HW_SAMAV3_RC663_REG_T0COUNTERVALHI

#define PHHAL_HW_SAMAV3_RC663_REG_T0COUNTERVALHI   0x12

Timer0 Counter(High) Register.

Get the most significant byte of the Counter-Value.

PHHAL_HW_SAMAV3_RC663_REG_T0COUNTERVALLO

#define PHHAL_HW_SAMAV3_RC663_REG_T0COUNTERVALLO   0x13

Timer0 Counter(Low) Register.

Get the least significant byte of the Counter-Value.

PHHAL_HW_SAMAV3_RC663_REG_T1CONTROL

#define PHHAL_HW_SAMAV3_RC663_REG_T1CONTROL   0x14

Timer1 Control Register.

Configure the timer.

PHHAL_HW_SAMAV3_RC663_REG_T1RELOADHI

#define PHHAL_HW_SAMAV3_RC663_REG_T1RELOADHI   0x15

Timer1 Reload(High) Register.

Set the most significant byte of the Reload-Value.

PHHAL_HW_SAMAV3_RC663_REG_T1RELOADLO

#define PHHAL_HW_SAMAV3_RC663_REG_T1RELOADLO   0x16

Timer1 Reload(Low) Register.

Set the least significant byte of the Reload-Value.

PHHAL_HW_SAMAV3_RC663_REG_T1COUNTERVALHI

#define PHHAL_HW_SAMAV3_RC663_REG_T1COUNTERVALHI   0x17

Timer1 Counter(High) Register.

Get the most significant byte of the Counter-Value.

PHHAL_HW_SAMAV3_RC663_REG_T1COUNTERVALLO

#define PHHAL_HW_SAMAV3_RC663_REG_T1COUNTERVALLO   0x18

Timer1 Counter(Low) Register.

Get the least significant byte of the Counter-Value.

PHHAL_HW_SAMAV3_RC663_REG_T2CONTROL

#define PHHAL_HW_SAMAV3_RC663_REG_T2CONTROL   0x19

Timer2 Control Register.

Configure the timer.

PHHAL_HW_SAMAV3_RC663_REG_T2RELOADHI

#define PHHAL_HW_SAMAV3_RC663_REG_T2RELOADHI   0x1A

Timer2 Reload(High) Register.

Set the most significant byte of the Reload-Value.

PHHAL_HW_SAMAV3_RC663_REG_T2RELOADLO

#define PHHAL_HW_SAMAV3_RC663_REG_T2RELOADLO   0x1B

Timer2 Reload(Low) Register.

Set the least significant byte of the Reload-Value.

PHHAL_HW_SAMAV3_RC663_REG_T2COUNTERVALHI

#define PHHAL_HW_SAMAV3_RC663_REG_T2COUNTERVALHI   0x1C

Timer2 Counter(High) Register.

Get the most significant byte of the Counter-Value.

PHHAL_HW_SAMAV3_RC663_REG_T2COUNTERVALLO

#define PHHAL_HW_SAMAV3_RC663_REG_T2COUNTERVALLO   0x1D

Timer2 Counter(Low) Register.

Get the least significant byte of the Counter-Value.

PHHAL_HW_SAMAV3_RC663_REG_T3CONTROL

#define PHHAL_HW_SAMAV3_RC663_REG_T3CONTROL   0x1E

Timer3 Control Register.

Configure the timer.

PHHAL_HW_SAMAV3_RC663_REG_T3RELOADHI

#define PHHAL_HW_SAMAV3_RC663_REG_T3RELOADHI   0x1F

Timer3 Reload(High) Register.

Set the most significant byte of the Reload-Value.

PHHAL_HW_SAMAV3_RC663_REG_T3RELOADLO

#define PHHAL_HW_SAMAV3_RC663_REG_T3RELOADLO   0x20

Timer3 Reload(Low) Register.

Set the least significant byte of the Reload-Value.

PHHAL_HW_SAMAV3_RC663_REG_T3COUNTERVALHI

#define PHHAL_HW_SAMAV3_RC663_REG_T3COUNTERVALHI   0x21

Timer3 Counter(High) Register.

Get the most significant byte of the Counter-Value.

PHHAL_HW_SAMAV3_RC663_REG_T3COUNTERVALLO

#define PHHAL_HW_SAMAV3_RC663_REG_T3COUNTERVALLO   0x22

Timer3 Counter(Low) Register.

Get the least significant byte of the Counter-Value.

PHHAL_HW_SAMAV3_RC663_REG_T4CONTROL

#define PHHAL_HW_SAMAV3_RC663_REG_T4CONTROL   0x23

Timer4 Control Register.

Configure the timer.

PHHAL_HW_SAMAV3_RC663_REG_T4RELOADHI

#define PHHAL_HW_SAMAV3_RC663_REG_T4RELOADHI   0x24

Timer4 Reload(High) Register.

Set the most significant byte of the Reload-Value.

PHHAL_HW_SAMAV3_RC663_REG_T4RELOADLO

#define PHHAL_HW_SAMAV3_RC663_REG_T4RELOADLO   0x25

Timer4 Reload(Low) Register.

Set the least significant byte of the Reload-Value.

PHHAL_HW_SAMAV3_RC663_REG_T4COUNTERVALHI

#define PHHAL_HW_SAMAV3_RC663_REG_T4COUNTERVALHI   0x26

Timer4 Counter(High) Register.

Get the most significant byte of the Counter-Value.

PHHAL_HW_SAMAV3_RC663_REG_T4COUNTERVALLO

#define PHHAL_HW_SAMAV3_RC663_REG_T4COUNTERVALLO   0x27

Timer4 Counter(Low) Register.

Get the least significant byte of the Counter-Value.

PHHAL_HW_SAMAV3_RC663_REG_DRVMODE

#define PHHAL_HW_SAMAV3_RC663_REG_DRVMODE   0x28

Driver Mode Register.

Enable / Invert the Tx-Driver and set the Clock Mode.

PHHAL_HW_SAMAV3_RC663_REG_TXAMP

#define PHHAL_HW_SAMAV3_RC663_REG_TXAMP   0x29

Tx Amplifier Register.

Modify Amplitude and Carrier settings.

PHHAL_HW_SAMAV3_RC663_REG_DRVCON

#define PHHAL_HW_SAMAV3_RC663_REG_DRVCON   0x2A

Driver Control Register.

Select / Invert drivers.

PHHAL_HW_SAMAV3_RC663_REG_TXI

#define PHHAL_HW_SAMAV3_RC663_REG_TXI   0x2B

TxI Register.

Contains Overshoot prevention and current control settings.

PHHAL_HW_SAMAV3_RC663_REG_TXCRCCON

#define PHHAL_HW_SAMAV3_RC663_REG_TXCRCCON   0x2C

Tx-CRC Control Register.

Configure CRC parameters transmission.

PHHAL_HW_SAMAV3_RC663_REG_RXCRCCON

#define PHHAL_HW_SAMAV3_RC663_REG_RXCRCCON   0x2D

Rx-CRC Control Register.

Configure CRC parameters for reception.

PHHAL_HW_SAMAV3_RC663_REG_TXDATANUM

#define PHHAL_HW_SAMAV3_RC663_REG_TXDATANUM   0x2E

Tx-DataNum Register.

Set TxLastBits and configure KeepBitGrid functionality.

PHHAL_HW_SAMAV3_RC663_REG_TXMODWIDTH

#define PHHAL_HW_SAMAV3_RC663_REG_TXMODWIDTH   0x2F

Tx-Modwidth Register.

Set the modulation width.

PHHAL_HW_SAMAV3_RC663_REG_TXSYM10BURSTLEN

#define PHHAL_HW_SAMAV3_RC663_REG_TXSYM10BURSTLEN   0x30

Symbol 0 and 1 Register.

Configure Burst-lengths of both symbols.

PHHAL_HW_SAMAV3_RC663_REG_TXWAITCTRL

#define PHHAL_HW_SAMAV3_RC663_REG_TXWAITCTRL   0x31

Tx-Wait Control Register.

Enable / Configure Tx Waiting-Time.

PHHAL_HW_SAMAV3_RC663_REG_TXWAITLO

#define PHHAL_HW_SAMAV3_RC663_REG_TXWAITLO   0x32

TxWaitLo Register.

Contains the Least-Significant-Bits for the Tx Waiting-Time.

PHHAL_HW_SAMAV3_RC663_REG_FRAMECON

#define PHHAL_HW_SAMAV3_RC663_REG_FRAMECON   0x33

Frame control register.

Contains active Start/Stop symbol and Parity settings.

PHHAL_HW_SAMAV3_RC663_REG_RXSOFD

#define PHHAL_HW_SAMAV3_RC663_REG_RXSOFD   0x34

RxSOFD Register.

Contains Start-of-Frame and subcarrier detection bits.

PHHAL_HW_SAMAV3_RC663_REG_RXCTRL

#define PHHAL_HW_SAMAV3_RC663_REG_RXCTRL   0x35

Rx Control Register.

Configure Receiver settings such as baudrate and EMD-suppression feature.

PHHAL_HW_SAMAV3_RC663_REG_RXWAIT

#define PHHAL_HW_SAMAV3_RC663_REG_RXWAIT   0x36

Rx-Wait Register.

Configure Receiver Deaf-Time.

PHHAL_HW_SAMAV3_RC663_REG_RXTHRESHOLD

#define PHHAL_HW_SAMAV3_RC663_REG_RXTHRESHOLD   0x37

Rx-Threshold Register.

Configure Receiver Threshold.

PHHAL_HW_SAMAV3_RC663_REG_RCV

#define PHHAL_HW_SAMAV3_RC663_REG_RCV   0x38

Receiver Register.

Configure Collision-Level and other features.

PHHAL_HW_SAMAV3_RC663_REG_RXANA

#define PHHAL_HW_SAMAV3_RC663_REG_RXANA   0x39

Rx-Analog Register.

Configure analog settings and parameters for Receiver circuitry.

PHHAL_HW_SAMAV3_RC663_REG_SERIALSPEED

#define PHHAL_HW_SAMAV3_RC663_REG_SERIALSPEED   0x3B

Serial Speed Register.

Configure serial baudrates.

PHHAL_HW_SAMAV3_RC663_REG_LPO_TRIMM

#define PHHAL_HW_SAMAV3_RC663_REG_LPO_TRIMM   0x3C

LPO_TRIMM Register.

Trimm Control Input for Low Power Oscillator.

PHHAL_HW_SAMAV3_RC663_REG_PLL_CTRL

#define PHHAL_HW_SAMAV3_RC663_REG_PLL_CTRL   0x3D

PLL Control Register.

Configure PLL settings.

PHHAL_HW_SAMAV3_RC663_REG_PLL_DIV

#define PHHAL_HW_SAMAV3_RC663_REG_PLL_DIV   0x3E

PLL DivO Register.

Contains PLL output.

PHHAL_HW_SAMAV3_RC663_REG_LPCD_QMIN

#define PHHAL_HW_SAMAV3_RC663_REG_LPCD_QMIN   0x3F

LPCD QMin Register.

Configure IMax(2) and QMin values for LPCD.

PHHAL_HW_SAMAV3_RC663_REG_LPCD_QMAX

#define PHHAL_HW_SAMAV3_RC663_REG_LPCD_QMAX   0x40

LPCD QMax Register.

Configure IMax(1) and QMax values for LPCD.

PHHAL_HW_SAMAV3_RC663_REG_LPCD_IMIN

#define PHHAL_HW_SAMAV3_RC663_REG_LPCD_IMIN   0x41

LPCD IMin Register.

Configure IMax(0) and IMin values for LPCD.

PHHAL_HW_SAMAV3_RC663_REG_LPCD_RESULT_I

#define PHHAL_HW_SAMAV3_RC663_REG_LPCD_RESULT_I   0x42

LPCD Result(I) Register.

Contains I-Channel results of LPCD.

PHHAL_HW_SAMAV3_RC663_REG_LPCD_RESULT_Q

#define PHHAL_HW_SAMAV3_RC663_REG_LPCD_RESULT_Q   0x43

LPCD Result(Q) Register.

Contains Q-Channel results of LPCD.

PHHAL_HW_SAMAV3_RC663_REG_VERSION

#define PHHAL_HW_SAMAV3_RC663_REG_VERSION   0x7F

Version Register.

Contains IC Version and Subversion.