
T1024RDB CPLD history

revA board:
V1.0 first version

V1.1 Fix Vbanck switch and diff-clock switch together issue.
		 Fix issue of CCS cannot connect Empty NOR boot flash.
		 
V1.2 Update AQ2104 reset OC.

V1.3
     add 2.5G AQR105 reset
     Set 2.5G as default on MUX PCIE & 2.5G SGMII.
     
revB board:
V2.4  based on V1.3, add Serdes clock control

revC board:
V3.5  Add 2.5G AQR105 interrupt
      Change serdes clock control on both MUX PCIE & 2.5G SGMII and Serdes PLL1 & PLL2 input.
      
V3.6  Fix SATA card not recovery after deepsleep
      Delay PCIE power up time after deepslee, since SATA card require more power than 
      network card, which cause CPU halt after deepsleep to wake up.
      
V3.7  Fix 2.5G AQR105 interrupt cannot set in CPLD.             		  
      		  
      		  