/** ###################################################################
**     THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename  : IO_Map.H
**     Project   : sci_echo
**     Processor : MC56F8006_48_LQFP
**     Beantype  : IO_Map
**     Version   : Driver 01.00
**     Compiler  : Metrowerks DSP C Compiler
**     Date/Time : 11/14/2008, 4:27 PM
**     Abstract  :
**         IO_Map.h - implements an IO device's mapping. 
**         This module contains symbol definitions of all peripheral 
**         registers and bits. 
**     Settings  :
**
**     Contents  :
**         No public methods
**
**     (c) Copyright UNIS, a.s. 1997-2008
**     UNIS, a.s.
**     Jundrovska 33
**     624 00 Brno
**     Czech Republic
**     http      : www.processorexpert.com
**     mail      : info@processorexpert.com
** ###################################################################*/

#ifndef __IO_Map_H
#define __IO_Map_H

/* Based on CPU DB 56F8006_48_LQFP, version 3.00.177 (RegistersPrg V2.24) */
/* DataSheet : MC56F8006RM,Rev. 0 Draft B,09/2007 */

#include "PE_Types.h"

/******************************************
*** Peripheral TMR0
*******************************************/
typedef volatile struct {
  /*** TMR0_COMP1 - Timer Channel 0 Compare Register #1; 0x0000F000 ***/
  union {
    word Word;
  } TMR0_COMP1_STR;
  
  #define TMR0_COMP1                    *((volatile word *)0x0000F000)


  /*** TMR0_COMP2 - Timer Channel 0 Compare Register #2; 0x0000F001 ***/
  union {
    word Word;
  } TMR0_COMP2_STR;
  
  #define TMR0_COMP2                    *((volatile word *)0x0000F001)


  /*** TMR0_CAPT - Timer Channel 0 Capture Register; 0x0000F002 ***/
  union {
    word Word;
  } TMR0_CAPT_STR;
  
  #define TMR0_CAPT                     *((volatile word *)0x0000F002)


  /*** TMR0_LOAD - Timer Channel 0 Load Register; 0x0000F003 ***/
  union {
    word Word;
  } TMR0_LOAD_STR;
  
  #define TMR0_LOAD_LOAD0_MASK          0x01U
  #define TMR0_LOAD_LOAD1_MASK          0x02U
  #define TMR0_LOAD_LOAD2_MASK          0x04U
  #define TMR0_LOAD_LOAD3_MASK          0x08U
  #define TMR0_LOAD_LOAD4_MASK          0x10U
  #define TMR0_LOAD_LOAD5_MASK          0x20U
  #define TMR0_LOAD_LOAD6_MASK          0x40U
  #define TMR0_LOAD_LOAD7_MASK          0x80U
  #define TMR0_LOAD_LOAD8_MASK          0x0100U
  #define TMR0_LOAD_LOAD9_MASK          0x0200U
  #define TMR0_LOAD_LOAD10_MASK         0x0400U
  #define TMR0_LOAD_LOAD11_MASK         0x0800U
  #define TMR0_LOAD_LOAD12_MASK         0x1000U
  #define TMR0_LOAD_LOAD13_MASK         0x2000U
  #define TMR0_LOAD_LOAD14_MASK         0x4000U
  #define TMR0_LOAD_LOAD15_MASK         0x8000U
  #define TMR0_LOAD                     *((volatile word *)0x0000F003)


  /*** TMR0_HOLD - Timer Channel 0 Hold Register; 0x0000F004 ***/
  union {
    word Word;
  } TMR0_HOLD_STR;
  
  #define TMR0_HOLD_HOLD0_MASK          0x01U
  #define TMR0_HOLD_HOLD1_MASK          0x02U
  #define TMR0_HOLD_HOLD2_MASK          0x04U
  #define TMR0_HOLD_HOLD3_MASK          0x08U
  #define TMR0_HOLD_HOLD4_MASK          0x10U
  #define TMR0_HOLD_HOLD5_MASK          0x20U
  #define TMR0_HOLD_HOLD6_MASK          0x40U
  #define TMR0_HOLD_HOLD7_MASK          0x80U
  #define TMR0_HOLD_HOLD8_MASK          0x0100U
  #define TMR0_HOLD_HOLD9_MASK          0x0200U
  #define TMR0_HOLD_HOLD10_MASK         0x0400U
  #define TMR0_HOLD_HOLD11_MASK         0x0800U
  #define TMR0_HOLD_HOLD12_MASK         0x1000U
  #define TMR0_HOLD_HOLD13_MASK         0x2000U
  #define TMR0_HOLD_HOLD14_MASK         0x4000U
  #define TMR0_HOLD_HOLD15_MASK         0x8000U
  #define TMR0_HOLD                     *((volatile word *)0x0000F004)


  /*** TMR0_CNTR - Timer Channel 0 Counter Register; 0x0000F005 ***/
  union {
    word Word;
  } TMR0_CNTR_STR;
  
  #define TMR0_CNTR                     *((volatile word *)0x0000F005)


  /*** TMR0_CTRL - Timer Channel 0 Control Register; 0x0000F006 ***/
  union {
    word Word;
  } TMR0_CTRL_STR;
  
  #define TMR0_CTRL_OM0_MASK            0x01U
  #define TMR0_CTRL_OM1_MASK            0x02U
  #define TMR0_CTRL_OM2_MASK            0x04U
  #define TMR0_CTRL_Co_INIT_MASK        0x08U
  #define TMR0_CTRL_DIR_MASK            0x10U
  #define TMR0_CTRL_LENGTH_MASK         0x20U
  #define TMR0_CTRL_ONCE_MASK           0x40U
  #define TMR0_CTRL_SCS0_MASK           0x80U
  #define TMR0_CTRL_SCS1_MASK           0x0100U
  #define TMR0_CTRL_PCS0_MASK           0x0200U
  #define TMR0_CTRL_PCS1_MASK           0x0400U
  #define TMR0_CTRL_PCS2_MASK           0x0800U
  #define TMR0_CTRL_PCS3_MASK           0x1000U
  #define TMR0_CTRL_CM0_MASK            0x2000U
  #define TMR0_CTRL_CM1_MASK            0x4000U
  #define TMR0_CTRL_CM2_MASK            0x8000U
  #define TMR0_CTRL_OM_MASK             0x07U
  #define TMR0_CTRL_OM_BITNUM           0x00U
  #define TMR0_CTRL_SCS_MASK            0x0180U
  #define TMR0_CTRL_SCS_BITNUM          0x07U
  #define TMR0_CTRL_PCS_MASK            0x1E00U
  #define TMR0_CTRL_PCS_BITNUM          0x09U
  #define TMR0_CTRL_CM_MASK             0xE000U
  #define TMR0_CTRL_CM_BITNUM           0x0DU
  #define TMR0_CTRL                     *((volatile word *)0x0000F006)


  /*** TMR0_SCTRL - Timer Channel 0 Status and Control Register; 0x0000F007 ***/
  union {
    word Word;
  } TMR0_SCTRL_STR;
  
  #define TMR0_SCTRL_OEN_MASK           0x01U
  #define TMR0_SCTRL_OPS_MASK           0x02U
  #define TMR0_SCTRL_FORCE_MASK         0x04U
  #define TMR0_SCTRL_VAL_MASK           0x08U
  #define TMR0_SCTRL_EEOF_MASK          0x10U
  #define TMR0_SCTRL_MSTR_MASK          0x20U
  #define TMR0_SCTRL_CAPTURE_MODE0_MASK 0x40U
  #define TMR0_SCTRL_CAPTURE_MODE1_MASK 0x80U
  #define TMR0_SCTRL_INPUT_MASK         0x0100U
  #define TMR0_SCTRL_IPS_MASK           0x0200U
  #define TMR0_SCTRL_IEFIE_MASK         0x0400U
  #define TMR0_SCTRL_IEF_MASK           0x0800U
  #define TMR0_SCTRL_TOFIE_MASK         0x1000U
  #define TMR0_SCTRL_TOF_MASK           0x2000U
  #define TMR0_SCTRL_TCFIE_MASK         0x4000U
  #define TMR0_SCTRL_TCF_MASK           0x8000U
  #define TMR0_SCTRL_CAPTURE_MODE_MASK  0xC0U
  #define TMR0_SCTRL_CAPTURE_MODE_BITNUM 0x06U
  #define TMR0_SCTRL                    *((volatile word *)0x0000F007)


  /*** TMR0_CMPLD1 - Timer Channel 0 Comparator Load Register 1; 0x0000F008 ***/
  union {
    word Word;
  } TMR0_CMPLD1_STR;
  
  #define TMR0_CMPLD1_COMPARATOR_LOAD_10_MASK 0x01U
  #define TMR0_CMPLD1_COMPARATOR_LOAD_11_MASK 0x02U
  #define TMR0_CMPLD1_COMPARATOR_LOAD_12_MASK 0x04U
  #define TMR0_CMPLD1_COMPARATOR_LOAD_13_MASK 0x08U
  #define TMR0_CMPLD1_COMPARATOR_LOAD_14_MASK 0x10U
  #define TMR0_CMPLD1_COMPARATOR_LOAD_15_MASK 0x20U
  #define TMR0_CMPLD1_COMPARATOR_LOAD_16_MASK 0x40U
  #define TMR0_CMPLD1_COMPARATOR_LOAD_17_MASK 0x80U
  #define TMR0_CMPLD1_COMPARATOR_LOAD_18_MASK 0x0100U
  #define TMR0_CMPLD1_COMPARATOR_LOAD_19_MASK 0x0200U
  #define TMR0_CMPLD1_COMPARATOR_LOAD_110_MASK 0x0400U
  #define TMR0_CMPLD1_COMPARATOR_LOAD_111_MASK 0x0800U
  #define TMR0_CMPLD1_COMPARATOR_LOAD_112_MASK 0x1000U
  #define TMR0_CMPLD1_COMPARATOR_LOAD_113_MASK 0x2000U
  #define TMR0_CMPLD1_COMPARATOR_LOAD_114_MASK 0x4000U
  #define TMR0_CMPLD1_COMPARATOR_LOAD_115_MASK 0x8000U
  #define TMR0_CMPLD1                   *((volatile word *)0x0000F008)


  /*** TMR0_CMPLD2 - Timer Channel 0 Comparator Load Register 2; 0x0000F009 ***/
  union {
    word Word;
  } TMR0_CMPLD2_STR;
  
  #define TMR0_CMPLD2_COMPARATOR_LOAD_20_MASK 0x01U
  #define TMR0_CMPLD2_COMPARATOR_LOAD_21_MASK 0x02U
  #define TMR0_CMPLD2_COMPARATOR_LOAD_22_MASK 0x04U
  #define TMR0_CMPLD2_COMPARATOR_LOAD_23_MASK 0x08U
  #define TMR0_CMPLD2_COMPARATOR_LOAD_24_MASK 0x10U
  #define TMR0_CMPLD2_COMPARATOR_LOAD_25_MASK 0x20U
  #define TMR0_CMPLD2_COMPARATOR_LOAD_26_MASK 0x40U
  #define TMR0_CMPLD2_COMPARATOR_LOAD_27_MASK 0x80U
  #define TMR0_CMPLD2_COMPARATOR_LOAD_28_MASK 0x0100U
  #define TMR0_CMPLD2_COMPARATOR_LOAD_29_MASK 0x0200U
  #define TMR0_CMPLD2_COMPARATOR_LOAD_210_MASK 0x0400U
  #define TMR0_CMPLD2_COMPARATOR_LOAD_211_MASK 0x0800U
  #define TMR0_CMPLD2_COMPARATOR_LOAD_212_MASK 0x1000U
  #define TMR0_CMPLD2_COMPARATOR_LOAD_213_MASK 0x2000U
  #define TMR0_CMPLD2_COMPARATOR_LOAD_214_MASK 0x4000U
  #define TMR0_CMPLD2_COMPARATOR_LOAD_215_MASK 0x8000U
  #define TMR0_CMPLD2                   *((volatile word *)0x0000F009)


  /*** TMR0_CSCTRL - Timer Channel 0 Comparator Status and Control Register; 0x0000F00A ***/
  union {
    word Word;
  } TMR0_CSCTRL_STR;
  
  #define TMR0_CSCTRL_CL10_MASK         0x01U
  #define TMR0_CSCTRL_CL11_MASK         0x02U
  #define TMR0_CSCTRL_CL20_MASK         0x04U
  #define TMR0_CSCTRL_CL21_MASK         0x08U
  #define TMR0_CSCTRL_TCF1_MASK         0x10U
  #define TMR0_CSCTRL_TCF2_MASK         0x20U
  #define TMR0_CSCTRL_TCF1EN_MASK       0x40U
  #define TMR0_CSCTRL_TCF2EN_MASK       0x80U
  #define TMR0_CSCTRL_ALT_LOAD_MASK     0x1000U
  #define TMR0_CSCTRL_FAULT_MASK        0x2000U
  #define TMR0_CSCTRL_DBG_EN0_MASK      0x4000U
  #define TMR0_CSCTRL_DBG_EN1_MASK      0x8000U
  #define TMR0_CSCTRL_CL1_MASK          0x03U
  #define TMR0_CSCTRL_CL1_BITNUM        0x00U
  #define TMR0_CSCTRL_CL2_MASK          0x0CU
  #define TMR0_CSCTRL_CL2_BITNUM        0x02U
  #define TMR0_CSCTRL_TCF_1_MASK        0x30U
  #define TMR0_CSCTRL_TCF_1_BITNUM      0x04U
  #define TMR0_CSCTRL_DBG_EN_MASK       0xC000U
  #define TMR0_CSCTRL_DBG_EN_BITNUM     0x0EU
  #define TMR0_CSCTRL                   *((volatile word *)0x0000F00A)


  /*** TMR0_FILT - Timer  Channel 0 Input Filter Register; 0x0000F00B ***/
  union {
    word Word;
  } TMR0_FILT_STR;
  
  #define TMR0_FILT_FILT_PER0_MASK      0x01U
  #define TMR0_FILT_FILT_PER1_MASK      0x02U
  #define TMR0_FILT_FILT_PER2_MASK      0x04U
  #define TMR0_FILT_FILT_PER3_MASK      0x08U
  #define TMR0_FILT_FILT_PER4_MASK      0x10U
  #define TMR0_FILT_FILT_PER5_MASK      0x20U
  #define TMR0_FILT_FILT_PER6_MASK      0x40U
  #define TMR0_FILT_FILT_PER7_MASK      0x80U
  #define TMR0_FILT_FILT_CNT0_MASK      0x0100U
  #define TMR0_FILT_FILT_CNT1_MASK      0x0200U
  #define TMR0_FILT_FILT_CNT2_MASK      0x0400U
  #define TMR0_FILT_FILT_PER_MASK       0xFFU
  #define TMR0_FILT_FILT_PER_BITNUM     0x00U
  #define TMR0_FILT_FILT_CNT_MASK       0x0700U
  #define TMR0_FILT_FILT_CNT_BITNUM     0x08U
  #define TMR0_FILT                     *((volatile word *)0x0000F00B)


  word Reserved0[3];                   /* Reserved (unused) registers */
  
  /*** TMR_ENBL - Timer  Channel Enable Register; 0x0000F00F ***/
  union {
    word Word;
  } TMR_ENBL_STR;
  
  #define TMR_ENBL_ENBL0_MASK           0x01U
  #define TMR_ENBL_ENBL1_MASK           0x02U
  #define TMR_ENBL_ENBL2_MASK           0x04U
  #define TMR_ENBL_ENBL3_MASK           0x08U
  #define TMR_ENBL_ENBL_MASK            0x0FU
  #define TMR_ENBL_ENBL_BITNUM          0x00U
  #define TMR_ENBL                      *((volatile word *)0x0000F00F)


} TMR0_PRPH;

/******************************************
*** Peripheral TMR1
*******************************************/
typedef volatile struct {
  /*** TMR1_COMP1 - Timer Channel 1 Compare Register #1; 0x0000F010 ***/
  union {
    word Word;
  } TMR1_COMP1_STR;
  
  #define TMR1_COMP1                    *((volatile word *)0x0000F010)


  /*** TMR1_COMP2 - Timer Channel 1 Compare Register #2; 0x0000F011 ***/
  union {
    word Word;
  } TMR1_COMP2_STR;
  
  #define TMR1_COMP2                    *((volatile word *)0x0000F011)


  /*** TMR1_CAPT - Timer Channel 1 Capture Register; 0x0000F012 ***/
  union {
    word Word;
  } TMR1_CAPT_STR;
  
  #define TMR1_CAPT                     *((volatile word *)0x0000F012)


  /*** TMR1_LOAD - Timer Channel 1 Load Register; 0x0000F013 ***/
  union {
    word Word;
  } TMR1_LOAD_STR;
  
  #define TMR1_LOAD_LOAD0_MASK          0x01U
  #define TMR1_LOAD_LOAD1_MASK          0x02U
  #define TMR1_LOAD_LOAD2_MASK          0x04U
  #define TMR1_LOAD_LOAD3_MASK          0x08U
  #define TMR1_LOAD_LOAD4_MASK          0x10U
  #define TMR1_LOAD_LOAD5_MASK          0x20U
  #define TMR1_LOAD_LOAD6_MASK          0x40U
  #define TMR1_LOAD_LOAD7_MASK          0x80U
  #define TMR1_LOAD_LOAD8_MASK          0x0100U
  #define TMR1_LOAD_LOAD9_MASK          0x0200U
  #define TMR1_LOAD_LOAD10_MASK         0x0400U
  #define TMR1_LOAD_LOAD11_MASK         0x0800U
  #define TMR1_LOAD_LOAD12_MASK         0x1000U
  #define TMR1_LOAD_LOAD13_MASK         0x2000U
  #define TMR1_LOAD_LOAD14_MASK         0x4000U
  #define TMR1_LOAD_LOAD15_MASK         0x8000U
  #define TMR1_LOAD                     *((volatile word *)0x0000F013)


  /*** TMR1_HOLD - Timer Channel 1 Hold Register; 0x0000F014 ***/
  union {
    word Word;
  } TMR1_HOLD_STR;
  
  #define TMR1_HOLD_HOLD0_MASK          0x01U
  #define TMR1_HOLD_HOLD1_MASK          0x02U
  #define TMR1_HOLD_HOLD2_MASK          0x04U
  #define TMR1_HOLD_HOLD3_MASK          0x08U
  #define TMR1_HOLD_HOLD4_MASK          0x10U
  #define TMR1_HOLD_HOLD5_MASK          0x20U
  #define TMR1_HOLD_HOLD6_MASK          0x40U
  #define TMR1_HOLD_HOLD7_MASK          0x80U
  #define TMR1_HOLD_HOLD8_MASK          0x0100U
  #define TMR1_HOLD_HOLD9_MASK          0x0200U
  #define TMR1_HOLD_HOLD10_MASK         0x0400U
  #define TMR1_HOLD_HOLD11_MASK         0x0800U
  #define TMR1_HOLD_HOLD12_MASK         0x1000U
  #define TMR1_HOLD_HOLD13_MASK         0x2000U
  #define TMR1_HOLD_HOLD14_MASK         0x4000U
  #define TMR1_HOLD_HOLD15_MASK         0x8000U
  #define TMR1_HOLD                     *((volatile word *)0x0000F014)


  /*** TMR1_CNTR - Timer Channel 1 Counter Register; 0x0000F015 ***/
  union {
    word Word;
  } TMR1_CNTR_STR;
  
  #define TMR1_CNTR                     *((volatile word *)0x0000F015)


  /*** TMR1_CTRL - Timer Channel 1 Control Register; 0x0000F016 ***/
  union {
    word Word;
  } TMR1_CTRL_STR;
  
  #define TMR1_CTRL_OM0_MASK            0x01U
  #define TMR1_CTRL_OM1_MASK            0x02U
  #define TMR1_CTRL_OM2_MASK            0x04U
  #define TMR1_CTRL_Co_INIT_MASK        0x08U
  #define TMR1_CTRL_DIR_MASK            0x10U
  #define TMR1_CTRL_LENGTH_MASK         0x20U
  #define TMR1_CTRL_ONCE_MASK           0x40U
  #define TMR1_CTRL_SCS0_MASK           0x80U
  #define TMR1_CTRL_SCS1_MASK           0x0100U
  #define TMR1_CTRL_PCS0_MASK           0x0200U
  #define TMR1_CTRL_PCS1_MASK           0x0400U
  #define TMR1_CTRL_PCS2_MASK           0x0800U
  #define TMR1_CTRL_PCS3_MASK           0x1000U
  #define TMR1_CTRL_CM0_MASK            0x2000U
  #define TMR1_CTRL_CM1_MASK            0x4000U
  #define TMR1_CTRL_CM2_MASK            0x8000U
  #define TMR1_CTRL_OM_MASK             0x07U
  #define TMR1_CTRL_OM_BITNUM           0x00U
  #define TMR1_CTRL_SCS_MASK            0x0180U
  #define TMR1_CTRL_SCS_BITNUM          0x07U
  #define TMR1_CTRL_PCS_MASK            0x1E00U
  #define TMR1_CTRL_PCS_BITNUM          0x09U
  #define TMR1_CTRL_CM_MASK             0xE000U
  #define TMR1_CTRL_CM_BITNUM           0x0DU
  #define TMR1_CTRL                     *((volatile word *)0x0000F016)


  /*** TMR1_SCTRL - Timer Channel 1 Status and Control Register; 0x0000F017 ***/
  union {
    word Word;
  } TMR1_SCTRL_STR;
  
  #define TMR1_SCTRL_OEN_MASK           0x01U
  #define TMR1_SCTRL_OPS_MASK           0x02U
  #define TMR1_SCTRL_FORCE_MASK         0x04U
  #define TMR1_SCTRL_VAL_MASK           0x08U
  #define TMR1_SCTRL_EEOF_MASK          0x10U
  #define TMR1_SCTRL_MSTR_MASK          0x20U
  #define TMR1_SCTRL_CAPTURE_MODE0_MASK 0x40U
  #define TMR1_SCTRL_CAPTURE_MODE1_MASK 0x80U
  #define TMR1_SCTRL_INPUT_MASK         0x0100U
  #define TMR1_SCTRL_IPS_MASK           0x0200U
  #define TMR1_SCTRL_IEFIE_MASK         0x0400U
  #define TMR1_SCTRL_IEF_MASK           0x0800U
  #define TMR1_SCTRL_TOFIE_MASK         0x1000U
  #define TMR1_SCTRL_TOF_MASK           0x2000U
  #define TMR1_SCTRL_TCFIE_MASK         0x4000U
  #define TMR1_SCTRL_TCF_MASK           0x8000U
  #define TMR1_SCTRL_CAPTURE_MODE_MASK  0xC0U
  #define TMR1_SCTRL_CAPTURE_MODE_BITNUM 0x06U
  #define TMR1_SCTRL                    *((volatile word *)0x0000F017)


  /*** TMR1_CMPLD1 - Timer Channel 1 Comparator Load Register 1; 0x0000F018 ***/
  union {
    word Word;
  } TMR1_CMPLD1_STR;
  
  #define TMR1_CMPLD1_COMPARATOR_LOAD_10_MASK 0x01U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_11_MASK 0x02U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_12_MASK 0x04U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_13_MASK 0x08U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_14_MASK 0x10U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_15_MASK 0x20U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_16_MASK 0x40U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_17_MASK 0x80U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_18_MASK 0x0100U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_19_MASK 0x0200U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_110_MASK 0x0400U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_111_MASK 0x0800U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_112_MASK 0x1000U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_113_MASK 0x2000U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_114_MASK 0x4000U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_115_MASK 0x8000U
  #define TMR1_CMPLD1                   *((volatile word *)0x0000F018)


  /*** TMR1_CMPLD2 - Timer Channel 1 Comparator Load Register 2; 0x0000F019 ***/
  union {
    word Word;
  } TMR1_CMPLD2_STR;
  
  #define TMR1_CMPLD2_COMPARATOR_LOAD_20_MASK 0x01U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_21_MASK 0x02U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_22_MASK 0x04U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_23_MASK 0x08U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_24_MASK 0x10U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_25_MASK 0x20U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_26_MASK 0x40U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_27_MASK 0x80U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_28_MASK 0x0100U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_29_MASK 0x0200U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_210_MASK 0x0400U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_211_MASK 0x0800U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_212_MASK 0x1000U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_213_MASK 0x2000U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_214_MASK 0x4000U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_215_MASK 0x8000U
  #define TMR1_CMPLD2                   *((volatile word *)0x0000F019)


  /*** TMR1_CSCTRL - Timer Channel 1 Comparator Status and Control Register; 0x0000F01A ***/
  union {
    word Word;
  } TMR1_CSCTRL_STR;
  
  #define TMR1_CSCTRL_CL10_MASK         0x01U
  #define TMR1_CSCTRL_CL11_MASK         0x02U
  #define TMR1_CSCTRL_CL20_MASK         0x04U
  #define TMR1_CSCTRL_CL21_MASK         0x08U
  #define TMR1_CSCTRL_TCF1_MASK         0x10U
  #define TMR1_CSCTRL_TCF2_MASK         0x20U
  #define TMR1_CSCTRL_TCF1EN_MASK       0x40U
  #define TMR1_CSCTRL_TCF2EN_MASK       0x80U
  #define TMR1_CSCTRL_ALT_LOAD_MASK     0x1000U
  #define TMR1_CSCTRL_FAULT_MASK        0x2000U
  #define TMR1_CSCTRL_DBG_EN0_MASK      0x4000U
  #define TMR1_CSCTRL_DBG_EN1_MASK      0x8000U
  #define TMR1_CSCTRL_CL1_MASK          0x03U
  #define TMR1_CSCTRL_CL1_BITNUM        0x00U
  #define TMR1_CSCTRL_CL2_MASK          0x0CU
  #define TMR1_CSCTRL_CL2_BITNUM        0x02U
  #define TMR1_CSCTRL_TCF_1_MASK        0x30U
  #define TMR1_CSCTRL_TCF_1_BITNUM      0x04U
  #define TMR1_CSCTRL_DBG_EN_MASK       0xC000U
  #define TMR1_CSCTRL_DBG_EN_BITNUM     0x0EU
  #define TMR1_CSCTRL                   *((volatile word *)0x0000F01A)


  /*** TMR1_FILT - Timer  Channel 1 Input Filter Register; 0x0000F01B ***/
  union {
    word Word;
  } TMR1_FILT_STR;
  
  #define TMR1_FILT_FILT_PER0_MASK      0x01U
  #define TMR1_FILT_FILT_PER1_MASK      0x02U
  #define TMR1_FILT_FILT_PER2_MASK      0x04U
  #define TMR1_FILT_FILT_PER3_MASK      0x08U
  #define TMR1_FILT_FILT_PER4_MASK      0x10U
  #define TMR1_FILT_FILT_PER5_MASK      0x20U
  #define TMR1_FILT_FILT_PER6_MASK      0x40U
  #define TMR1_FILT_FILT_PER7_MASK      0x80U
  #define TMR1_FILT_FILT_CNT0_MASK      0x0100U
  #define TMR1_FILT_FILT_CNT1_MASK      0x0200U
  #define TMR1_FILT_FILT_CNT2_MASK      0x0400U
  #define TMR1_FILT_FILT_PER_MASK       0xFFU
  #define TMR1_FILT_FILT_PER_BITNUM     0x00U
  #define TMR1_FILT_FILT_CNT_MASK       0x0700U
  #define TMR1_FILT_FILT_CNT_BITNUM     0x08U
  #define TMR1_FILT                     *((volatile word *)0x0000F01B)


  word Reserved0[4];                   /* Reserved (unused) registers */

} TMR1_PRPH;

/******************************************
*** Peripheral PWM
*******************************************/
typedef volatile struct {
  /*** PWM_CTRL - PWM control register; 0x0000F020 ***/
  union {
    word Word;
  } PWM_CTRL_STR;
  
  #define PWM_CTRL_PWMEN_MASK           0x01U
  #define PWM_CTRL_LDOK_MASK            0x02U
  #define PWM_CTRL_ISENS0_MASK          0x04U
  #define PWM_CTRL_ISENS1_MASK          0x08U
  #define PWM_CTRL_PWMF_MASK            0x10U
  #define PWM_CTRL_PWMRIE_MASK          0x20U
  #define PWM_CTRL_PRSC0_MASK           0x40U
  #define PWM_CTRL_PRSC1_MASK           0x80U
  #define PWM_CTRL_IPOL0_MASK           0x0100U
  #define PWM_CTRL_IPOL1_MASK           0x0200U
  #define PWM_CTRL_IPOL2_MASK           0x0400U
  #define PWM_CTRL_HALF_MASK            0x0800U
  #define PWM_CTRL_LDFQ0_MASK           0x1000U
  #define PWM_CTRL_LDFQ1_MASK           0x2000U
  #define PWM_CTRL_LDFQ2_MASK           0x4000U
  #define PWM_CTRL_LDFQ3_MASK           0x8000U
  #define PWM_CTRL_ISENS_MASK           0x0CU
  #define PWM_CTRL_ISENS_BITNUM         0x02U
  #define PWM_CTRL_PRSC_MASK            0xC0U
  #define PWM_CTRL_PRSC_BITNUM          0x06U
  #define PWM_CTRL_IPOL_MASK            0x0700U
  #define PWM_CTRL_IPOL_BITNUM          0x08U
  #define PWM_CTRL_LDFQ_MASK            0xF000U
  #define PWM_CTRL_LDFQ_BITNUM          0x0CU
  #define PWM_CTRL                      *((volatile word *)0x0000F020)


  /*** PWM_FCTRL - PWM fault control register; 0x0000F021 ***/
  union {
    word Word;
  } PWM_FCTRL_STR;
  
  #define PWM_FCTRL_FMODE0_MASK         0x01U
  #define PWM_FCTRL_FIE0_MASK           0x02U
  #define PWM_FCTRL_FMODE1_MASK         0x04U
  #define PWM_FCTRL_FIE1_MASK           0x08U
  #define PWM_FCTRL_FMODE2_MASK         0x10U
  #define PWM_FCTRL_FIE2_MASK           0x20U
  #define PWM_FCTRL_FMODE3_MASK         0x40U
  #define PWM_FCTRL_FIE3_MASK           0x80U
  #define PWM_FCTRL_FPOL0_MASK          0x0100U
  #define PWM_FCTRL_FPOL1_MASK          0x0200U
  #define PWM_FCTRL_FPOL2_MASK          0x0400U
  #define PWM_FCTRL_FPOL3_MASK          0x0800U
  #define PWM_FCTRL_FPOL_MASK           0x0F00U
  #define PWM_FCTRL_FPOL_BITNUM         0x08U
  #define PWM_FCTRL                     *((volatile word *)0x0000F021)


  /*** PWM_FLTACK - PWM fault status acknowledge register; 0x0000F022 ***/
  union {
    word Word;
  } PWM_FLTACK_STR;
  
  #define PWM_FLTACK_DT0_FTACK0_MASK    0x01U
  #define PWM_FLTACK_DT1_MASK           0x02U
  #define PWM_FLTACK_DT2_FTACK1_MASK    0x04U
  #define PWM_FLTACK_DT3_MASK           0x08U
  #define PWM_FLTACK_DT4_FTACK2_MASK    0x10U
  #define PWM_FLTACK_DT5_MASK           0x20U
  #define PWM_FLTACK_FTACK3_MASK        0x40U
  #define PWM_FLTACK_FFLAG0_MASK        0x0100U
  #define PWM_FLTACK_FPIN0_MASK         0x0200U
  #define PWM_FLTACK_FFLAG1_MASK        0x0400U
  #define PWM_FLTACK_FPIN1_MASK         0x0800U
  #define PWM_FLTACK_FFLAG2_MASK        0x1000U
  #define PWM_FLTACK_FPIN2_MASK         0x2000U
  #define PWM_FLTACK_FFLAG3_MASK        0x4000U
  #define PWM_FLTACK_FPIN3_MASK         0x8000U
  #define PWM_FLTACK                    *((volatile word *)0x0000F022)


  /*** PWM_OUT - PWM output control register; 0x0000F023 ***/
  union {
    word Word;
  } PWM_OUT_STR;
  
  #define PWM_OUT_OUT0_MASK             0x01U
  #define PWM_OUT_OUT1_MASK             0x02U
  #define PWM_OUT_OUT2_MASK             0x04U
  #define PWM_OUT_OUT3_MASK             0x08U
  #define PWM_OUT_OUT4_MASK             0x10U
  #define PWM_OUT_OUT5_MASK             0x20U
  #define PWM_OUT_OUTCTL0_MASK          0x0100U
  #define PWM_OUT_OUTCTL1_MASK          0x0200U
  #define PWM_OUT_OUTCTL2_MASK          0x0400U
  #define PWM_OUT_OUTCTL3_MASK          0x0800U
  #define PWM_OUT_OUTCTL4_MASK          0x1000U
  #define PWM_OUT_OUTCTL5_MASK          0x2000U
  #define PWM_OUT_PAD_EN_MASK           0x8000U
  #define PWM_OUT_OUT_MASK              0x3FU
  #define PWM_OUT_OUT_BITNUM            0x00U
  #define PWM_OUT_OUTCTL_MASK           0x3F00U
  #define PWM_OUT_OUTCTL_BITNUM         0x08U
  #define PWM_OUT                       *((volatile word *)0x0000F023)


  /*** PWM_CNTR - PWM counter register; 0x0000F024 ***/
  union {
    word Word;
  } PWM_CNTR_STR;
  
  #define PWM_CNTR_CR0_MASK             0x01U
  #define PWM_CNTR_CR1_MASK             0x02U
  #define PWM_CNTR_CR2_MASK             0x04U
  #define PWM_CNTR_CR3_MASK             0x08U
  #define PWM_CNTR_CR4_MASK             0x10U
  #define PWM_CNTR_CR5_MASK             0x20U
  #define PWM_CNTR_CR6_MASK             0x40U
  #define PWM_CNTR_CR7_MASK             0x80U
  #define PWM_CNTR_CR8_MASK             0x0100U
  #define PWM_CNTR_CR9_MASK             0x0200U
  #define PWM_CNTR_CR10_MASK            0x0400U
  #define PWM_CNTR_CR11_MASK            0x0800U
  #define PWM_CNTR_CR12_MASK            0x1000U
  #define PWM_CNTR_CR13_MASK            0x2000U
  #define PWM_CNTR_CR14_MASK            0x4000U
  #define PWM_CNTR_CR_MASK              0x7FFFU
  #define PWM_CNTR_CR_BITNUM            0x00U
  #define PWM_CNTR                      *((volatile word *)0x0000F024)


  /*** PWM_CMOD - PWM counter modulo register; 0x0000F025 ***/
  union {
    word Word;
  } PWM_CMOD_STR;
  
  #define PWM_CMOD_PWMCM0_MASK          0x01U
  #define PWM_CMOD_PWMCM1_MASK          0x02U
  #define PWM_CMOD_PWMCM2_MASK          0x04U
  #define PWM_CMOD_PWMCM3_MASK          0x08U
  #define PWM_CMOD_PWMCM4_MASK          0x10U
  #define PWM_CMOD_PWMCM5_MASK          0x20U
  #define PWM_CMOD_PWMCM6_MASK          0x40U
  #define PWM_CMOD_PWMCM7_MASK          0x80U
  #define PWM_CMOD_PWMCM8_MASK          0x0100U
  #define PWM_CMOD_PWMCM9_MASK          0x0200U
  #define PWM_CMOD_PWMCM10_MASK         0x0400U
  #define PWM_CMOD_PWMCM11_MASK         0x0800U
  #define PWM_CMOD_PWMCM12_MASK         0x1000U
  #define PWM_CMOD_PWMCM13_MASK         0x2000U
  #define PWM_CMOD_PWMCM14_MASK         0x4000U
  #define PWM_CMOD_PWMCM_MASK           0x7FFFU
  #define PWM_CMOD_PWMCM_BITNUM         0x00U
  #define PWM_CMOD                      *((volatile word *)0x0000F025)


  /*** PWM_VAL0 - PWM value register 0; 0x0000F026 ***/
  union {
    word Word;
  } PWM_VAL0_STR;
  
  #define PWM_VAL0                      *((volatile word *)0x0000F026)


  /*** PWM_VAL1 - PWM value register 1; 0x0000F027 ***/
  union {
    word Word;
  } PWM_VAL1_STR;
  
  #define PWM_VAL1                      *((volatile word *)0x0000F027)


  /*** PWM_VAL2 - PWM value register 2; 0x0000F028 ***/
  union {
    word Word;
  } PWM_VAL2_STR;
  
  #define PWM_VAL2                      *((volatile word *)0x0000F028)


  /*** PWM_VAL3 - PWM value register 3; 0x0000F029 ***/
  union {
    word Word;
  } PWM_VAL3_STR;
  
  #define PWM_VAL3                      *((volatile word *)0x0000F029)


  /*** PWM_VAL4 - PWM value register 4; 0x0000F02A ***/
  union {
    word Word;
  } PWM_VAL4_STR;
  
  #define PWM_VAL4                      *((volatile word *)0x0000F02A)


  /*** PWM_VAL5 - PWM value register 5; 0x0000F02B ***/
  union {
    word Word;
  } PWM_VAL5_STR;
  
  #define PWM_VAL5                      *((volatile word *)0x0000F02B)


  /*** PWM_DTIM0 - PWM deadtime register 0; 0x0000F02C ***/
  union {
    word Word;
  } PWM_DTIM0_STR;
  
  #define PWM_DTIM0_PWMDT00_MASK        0x01U
  #define PWM_DTIM0_PWMDT01_MASK        0x02U
  #define PWM_DTIM0_PWMDT02_MASK        0x04U
  #define PWM_DTIM0_PWMDT03_MASK        0x08U
  #define PWM_DTIM0_PWMDT04_MASK        0x10U
  #define PWM_DTIM0_PWMDT05_MASK        0x20U
  #define PWM_DTIM0_PWMDT06_MASK        0x40U
  #define PWM_DTIM0_PWMDT07_MASK        0x80U
  #define PWM_DTIM0_PWMDT08_MASK        0x0100U
  #define PWM_DTIM0_PWMDT09_MASK        0x0200U
  #define PWM_DTIM0_PWMDT010_MASK       0x0400U
  #define PWM_DTIM0_PWMDT011_MASK       0x0800U
  #define PWM_DTIM0_PWMDT0_MASK         0x0FFFU
  #define PWM_DTIM0_PWMDT0_BITNUM       0x00U
  #define PWM_DTIM0                     *((volatile word *)0x0000F02C)


  /*** PWM_DTIM1 - PWM deadtime register 1; 0x0000F02D ***/
  union {
    word Word;
  } PWM_DTIM1_STR;
  
  #define PWM_DTIM1_PWMDT10_MASK        0x01U
  #define PWM_DTIM1_PWMDT11_MASK        0x02U
  #define PWM_DTIM1_PWMDT12_MASK        0x04U
  #define PWM_DTIM1_PWMDT13_MASK        0x08U
  #define PWM_DTIM1_PWMDT14_MASK        0x10U
  #define PWM_DTIM1_PWMDT15_MASK        0x20U
  #define PWM_DTIM1_PWMDT16_MASK        0x40U
  #define PWM_DTIM1_PWMDT17_MASK        0x80U
  #define PWM_DTIM1_PWMDT18_MASK        0x0100U
  #define PWM_DTIM1_PWMDT19_MASK        0x0200U
  #define PWM_DTIM1_PWMDT110_MASK       0x0400U
  #define PWM_DTIM1_PWMDT111_MASK       0x0800U
  #define PWM_DTIM1_PWMDT1_MASK         0x0FFFU
  #define PWM_DTIM1_PWMDT1_BITNUM       0x00U
  #define PWM_DTIM1                     *((volatile word *)0x0000F02D)


  /*** PWM_DMAP1 - PWM disable mapping register one; 0x0000F02E ***/
  union {
    word Word;
  } PWM_DMAP1_STR;
  
  #define PWM_DMAP1_DISMAP_15_00_MASK   0x01U
  #define PWM_DMAP1_DISMAP_15_01_MASK   0x02U
  #define PWM_DMAP1_DISMAP_15_02_MASK   0x04U
  #define PWM_DMAP1_DISMAP_15_03_MASK   0x08U
  #define PWM_DMAP1_DISMAP_15_04_MASK   0x10U
  #define PWM_DMAP1_DISMAP_15_05_MASK   0x20U
  #define PWM_DMAP1_DISMAP_15_06_MASK   0x40U
  #define PWM_DMAP1_DISMAP_15_07_MASK   0x80U
  #define PWM_DMAP1_DISMAP_15_08_MASK   0x0100U
  #define PWM_DMAP1_DISMAP_15_09_MASK   0x0200U
  #define PWM_DMAP1_DISMAP_15_010_MASK  0x0400U
  #define PWM_DMAP1_DISMAP_15_011_MASK  0x0800U
  #define PWM_DMAP1_DISMAP_15_012_MASK  0x1000U
  #define PWM_DMAP1_DISMAP_15_013_MASK  0x2000U
  #define PWM_DMAP1_DISMAP_15_014_MASK  0x4000U
  #define PWM_DMAP1_DISMAP_15_015_MASK  0x8000U
  #define PWM_DMAP1                     *((volatile word *)0x0000F02E)


  /*** PWM_DMAP2 - PWM disable mapping register two; 0x0000F02F ***/
  union {
    word Word;
  } PWM_DMAP2_STR;
  
  #define PWM_DMAP2_DISMAP_23_160_MASK  0x01U
  #define PWM_DMAP2_DISMAP_23_161_MASK  0x02U
  #define PWM_DMAP2_DISMAP_23_162_MASK  0x04U
  #define PWM_DMAP2_DISMAP_23_163_MASK  0x08U
  #define PWM_DMAP2_DISMAP_23_164_MASK  0x10U
  #define PWM_DMAP2_DISMAP_23_165_MASK  0x20U
  #define PWM_DMAP2_DISMAP_23_166_MASK  0x40U
  #define PWM_DMAP2_DISMAP_23_167_MASK  0x80U
  #define PWM_DMAP2_DISMAP_23_16_MASK   0xFFU
  #define PWM_DMAP2_DISMAP_23_16_BITNUM 0x00U
  #define PWM_DMAP2                     *((volatile word *)0x0000F02F)


  /*** PWM_CNFG - PWM config register; 0x0000F030 ***/
  union {
    word Word;
  } PWM_CNFG_STR;
  
  #define PWM_CNFG_WP_MASK              0x01U
  #define PWM_CNFG_INDEP01_MASK         0x02U
  #define PWM_CNFG_INDEP23_MASK         0x04U
  #define PWM_CNFG_INDEP45_MASK         0x08U
  #define PWM_CNFG_BOTNEG01_MASK        0x10U
  #define PWM_CNFG_BOTNEG23_MASK        0x20U
  #define PWM_CNFG_BOTNEG45_MASK        0x40U
  #define PWM_CNFG_TOPNEG01_MASK        0x0100U
  #define PWM_CNFG_TOPNEG23_MASK        0x0200U
  #define PWM_CNFG_TOPNEG45_MASK        0x0400U
  #define PWM_CNFG_EDG_MASK             0x1000U
  #define PWM_CNFG_WAIT_EN_MASK         0x2000U
  #define PWM_CNFG_DBG_EN_MASK          0x4000U
  #define PWM_CNFG                      *((volatile word *)0x0000F030)


  /*** PWM_CCTRL - PWM channel control register; 0x0000F031 ***/
  union {
    word Word;
  } PWM_CCTRL_STR;
  
  #define PWM_CCTRL_SWP01_MASK          0x01U
  #define PWM_CCTRL_SWP23_MASK          0x02U
  #define PWM_CCTRL_SWP45_MASK          0x04U
  #define PWM_CCTRL_VLMODE0_MASK        0x10U
  #define PWM_CCTRL_VLMODE1_MASK        0x20U
  #define PWM_CCTRL_MSK0_MASK           0x0100U
  #define PWM_CCTRL_MSK1_MASK           0x0200U
  #define PWM_CCTRL_MSK2_MASK           0x0400U
  #define PWM_CCTRL_MSK3_MASK           0x0800U
  #define PWM_CCTRL_MSK4_MASK           0x1000U
  #define PWM_CCTRL_MSK5_MASK           0x2000U
  #define PWM_CCTRL_nBX_MASK            0x4000U
  #define PWM_CCTRL_ENHA_MASK           0x8000U
  #define PWM_CCTRL_VLMODE_MASK         0x30U
  #define PWM_CCTRL_VLMODE_BITNUM       0x04U
  #define PWM_CCTRL_MSK_MASK            0x3F00U
  #define PWM_CCTRL_MSK_BITNUM          0x08U
  #define PWM_CCTRL                     *((volatile word *)0x0000F031)


  /*** PWM_PORT - PWM port register; 0x0000F032 ***/
  union {
    word Word;
  } PWM_PORT_STR;
  
  #define PWM_PORT_PORT0_MASK           0x01U
  #define PWM_PORT_PORT1_MASK           0x02U
  #define PWM_PORT_PORT2_MASK           0x04U
  #define PWM_PORT_PORT3_MASK           0x08U
  #define PWM_PORT_PORT4_MASK           0x10U
  #define PWM_PORT_PORT5_MASK           0x20U
  #define PWM_PORT_PORT6_MASK           0x40U
  #define PWM_PORT_PORT_MASK            0x7FU
  #define PWM_PORT_PORT_BITNUM          0x00U
  #define PWM_PORT                      *((volatile word *)0x0000F032)


  /*** PWM_ICCTRL - PWM Internal Correction Control Register; 0x0000F033 ***/
  union {
    word Word;
  } PWM_ICCTRL_STR;
  
  #define PWM_ICCTRL_ICC0_MASK          0x01U
  #define PWM_ICCTRL_ICC1_MASK          0x02U
  #define PWM_ICCTRL_ICC2_MASK          0x04U
  #define PWM_ICCTRL_PEC0_MASK          0x08U
  #define PWM_ICCTRL_PEC1_MASK          0x10U
  #define PWM_ICCTRL_PEC2_MASK          0x20U
  #define PWM_ICCTRL_ICC_MASK           0x07U
  #define PWM_ICCTRL_ICC_BITNUM         0x00U
  #define PWM_ICCTRL_PEC_MASK           0x38U
  #define PWM_ICCTRL_PEC_BITNUM         0x03U
  #define PWM_ICCTRL                    *((volatile word *)0x0000F033)


  /*** PWM_SCTRL - PWM Source Control Register; 0x0000F034 ***/
  union {
    word Word;
  } PWM_SCTRL_STR;
  
  #define PWM_SCTRL_SRC0_MASK           0x01U
  #define PWM_SCTRL_SRC10_MASK          0x04U
  #define PWM_SCTRL_SRC11_MASK          0x08U
  #define PWM_SCTRL_SRC20_MASK          0x20U
  #define PWM_SCTRL_SRC21_MASK          0x40U
  #define PWM_SCTRL_CINV0_MASK          0x0100U
  #define PWM_SCTRL_CINV1_MASK          0x0200U
  #define PWM_SCTRL_CINV2_MASK          0x0400U
  #define PWM_SCTRL_CINV3_MASK          0x0800U
  #define PWM_SCTRL_CINV4_MASK          0x1000U
  #define PWM_SCTRL_CINV5_MASK          0x2000U
  #define PWM_SCTRL_SRC1_MASK           0x0CU
  #define PWM_SCTRL_SRC1_BITNUM         0x02U
  #define PWM_SCTRL_SRC2_MASK           0x60U
  #define PWM_SCTRL_SRC2_BITNUM         0x05U
  #define PWM_SCTRL_CINV_MASK           0x3F00U
  #define PWM_SCTRL_CINV_BITNUM         0x08U
  #define PWM_SCTRL                     *((volatile word *)0x0000F034)


  /*** PWM_SYNC - PWM Synchronization Window Register; 0x0000F035 ***/
  union {
    word Word;
  } PWM_SYNC_STR;
  
  #define PWM_SYNC_SYNC_WINDOW0_MASK    0x01U
  #define PWM_SYNC_SYNC_WINDOW1_MASK    0x02U
  #define PWM_SYNC_SYNC_WINDOW2_MASK    0x04U
  #define PWM_SYNC_SYNC_WINDOW3_MASK    0x08U
  #define PWM_SYNC_SYNC_WINDOW4_MASK    0x10U
  #define PWM_SYNC_SYNC_WINDOW5_MASK    0x20U
  #define PWM_SYNC_SYNC_WINDOW6_MASK    0x40U
  #define PWM_SYNC_SYNC_WINDOW7_MASK    0x80U
  #define PWM_SYNC_SYNC_WINDOW8_MASK    0x0100U
  #define PWM_SYNC_SYNC_WINDOW9_MASK    0x0200U
  #define PWM_SYNC_SYNC_WINDOW10_MASK   0x0400U
  #define PWM_SYNC_SYNC_WINDOW11_MASK   0x0800U
  #define PWM_SYNC_SYNC_WINDOW12_MASK   0x1000U
  #define PWM_SYNC_SYNC_WINDOW13_MASK   0x2000U
  #define PWM_SYNC_SYNC_WINDOW14_MASK   0x4000U
  #define PWM_SYNC_SYNC_OUT_EN_MASK     0x8000U
  #define PWM_SYNC_SYNC_WINDOW_MASK     0x7FFFU
  #define PWM_SYNC_SYNC_WINDOW_BITNUM   0x00U
  #define PWM_SYNC                      *((volatile word *)0x0000F035)


  /*** PWM_FFILT0 - PWM Fault 0 Filter Register; 0x0000F036 ***/
  union {
    word Word;
  } PWM_FFILT0_STR;
  
  #define PWM_FFILT0_FILT0_PER0_MASK    0x01U
  #define PWM_FFILT0_FILT0_PER1_MASK    0x02U
  #define PWM_FFILT0_FILT0_PER2_MASK    0x04U
  #define PWM_FFILT0_FILT0_PER3_MASK    0x08U
  #define PWM_FFILT0_FILT0_PER4_MASK    0x10U
  #define PWM_FFILT0_FILT0_PER5_MASK    0x20U
  #define PWM_FFILT0_FILT0_PER6_MASK    0x40U
  #define PWM_FFILT0_FILT0_PER7_MASK    0x80U
  #define PWM_FFILT0_FILT0_CNT0_MASK    0x0100U
  #define PWM_FFILT0_FILT0_CNT1_MASK    0x0200U
  #define PWM_FFILT0_FILT0_CNT2_MASK    0x0400U
  #define PWM_FFILT0_GSTR0_MASK         0x8000U
  #define PWM_FFILT0_FILT0_PER_MASK     0xFFU
  #define PWM_FFILT0_FILT0_PER_BITNUM   0x00U
  #define PWM_FFILT0_FILT0_CNT_MASK     0x0700U
  #define PWM_FFILT0_FILT0_CNT_BITNUM   0x08U
  #define PWM_FFILT0                    *((volatile word *)0x0000F036)


  /*** PWM_FFILT1 - PWM Fault 1 Filter Register; 0x0000F037 ***/
  union {
    word Word;
  } PWM_FFILT1_STR;
  
  #define PWM_FFILT1_FILT1_PER0_MASK    0x01U
  #define PWM_FFILT1_FILT1_PER1_MASK    0x02U
  #define PWM_FFILT1_FILT1_PER2_MASK    0x04U
  #define PWM_FFILT1_FILT1_PER3_MASK    0x08U
  #define PWM_FFILT1_FILT1_PER4_MASK    0x10U
  #define PWM_FFILT1_FILT1_PER5_MASK    0x20U
  #define PWM_FFILT1_FILT1_PER6_MASK    0x40U
  #define PWM_FFILT1_FILT1_PER7_MASK    0x80U
  #define PWM_FFILT1_FILT1_CNT0_MASK    0x0100U
  #define PWM_FFILT1_FILT1_CNT1_MASK    0x0200U
  #define PWM_FFILT1_FILT1_CNT2_MASK    0x0400U
  #define PWM_FFILT1_GSTR1_MASK         0x8000U
  #define PWM_FFILT1_FILT1_PER_MASK     0xFFU
  #define PWM_FFILT1_FILT1_PER_BITNUM   0x00U
  #define PWM_FFILT1_FILT1_CNT_MASK     0x0700U
  #define PWM_FFILT1_FILT1_CNT_BITNUM   0x08U
  #define PWM_FFILT1                    *((volatile word *)0x0000F037)


  /*** PWM_FFILT2 - PWM Fault 2 Filter Register; 0x0000F038 ***/
  union {
    word Word;
  } PWM_FFILT2_STR;
  
  #define PWM_FFILT2_FILT2_PER0_MASK    0x01U
  #define PWM_FFILT2_FILT2_PER1_MASK    0x02U
  #define PWM_FFILT2_FILT2_PER2_MASK    0x04U
  #define PWM_FFILT2_FILT2_PER3_MASK    0x08U
  #define PWM_FFILT2_FILT2_PER4_MASK    0x10U
  #define PWM_FFILT2_FILT2_PER5_MASK    0x20U
  #define PWM_FFILT2_FILT2_PER6_MASK    0x40U
  #define PWM_FFILT2_FILT2_PER7_MASK    0x80U
  #define PWM_FFILT2_FILT2_CNT0_MASK    0x0100U
  #define PWM_FFILT2_FILT2_CNT1_MASK    0x0200U
  #define PWM_FFILT2_FILT2_CNT2_MASK    0x0400U
  #define PWM_FFILT2_GSTR2_MASK         0x8000U
  #define PWM_FFILT2_FILT2_PER_MASK     0xFFU
  #define PWM_FFILT2_FILT2_PER_BITNUM   0x00U
  #define PWM_FFILT2_FILT2_CNT_MASK     0x0700U
  #define PWM_FFILT2_FILT2_CNT_BITNUM   0x08U
  #define PWM_FFILT2                    *((volatile word *)0x0000F038)


  /*** PWM_FFILT3 - PWM Fault 3 Filter Register; 0x0000F039 ***/
  union {
    word Word;
  } PWM_FFILT3_STR;
  
  #define PWM_FFILT3_FILT3_PER0_MASK    0x01U
  #define PWM_FFILT3_FILT3_PER1_MASK    0x02U
  #define PWM_FFILT3_FILT3_PER2_MASK    0x04U
  #define PWM_FFILT3_FILT3_PER3_MASK    0x08U
  #define PWM_FFILT3_FILT3_PER4_MASK    0x10U
  #define PWM_FFILT3_FILT3_PER5_MASK    0x20U
  #define PWM_FFILT3_FILT3_PER6_MASK    0x40U
  #define PWM_FFILT3_FILT3_PER7_MASK    0x80U
  #define PWM_FFILT3_FILT3_CNT0_MASK    0x0100U
  #define PWM_FFILT3_FILT3_CNT1_MASK    0x0200U
  #define PWM_FFILT3_FILT3_CNT2_MASK    0x0400U
  #define PWM_FFILT3_GSTR3_MASK         0x8000U
  #define PWM_FFILT3_FILT3_PER_MASK     0xFFU
  #define PWM_FFILT3_FILT3_PER_BITNUM   0x00U
  #define PWM_FFILT3_FILT3_CNT_MASK     0x0700U
  #define PWM_FFILT3_FILT3_CNT_BITNUM   0x08U
  #define PWM_FFILT3                    *((volatile word *)0x0000F039)


  word Reserved0[6];                   /* Reserved (unused) registers */

} PWM_PRPH;

/******************************************
*** Peripheral INTC
*******************************************/
typedef volatile struct {
  /*** INTC_ICSR - Interrupt Control & Status Register; 0x0000F040 ***/
  union {
    word Word;
  } INTC_ICSR_STR;
  
  #define INTC_ICSR_STPCNT_MASK         0x01U
  #define INTC_ICSR_BKPT_MASK           0x02U
  #define INTC_ICSR_TRBUF_MASK          0x04U
  #define INTC_ICSR_ETRE_MASK           0x08U
  #define INTC_ICSR_ERRF_MASK           0x10U
  #define INTC_ICSR_INT_DIS_MASK        0x20U
  #define INTC_ICSR_VAB0_MASK           0x40U
  #define INTC_ICSR_VAB1_MASK           0x80U
  #define INTC_ICSR_VAB2_MASK           0x0100U
  #define INTC_ICSR_VAB3_MASK           0x0200U
  #define INTC_ICSR_VAB4_MASK           0x0400U
  #define INTC_ICSR_VAB5_MASK           0x0800U
  #define INTC_ICSR_VAB6_MASK           0x1000U
  #define INTC_ICSR_IPIC0_MASK          0x2000U
  #define INTC_ICSR_IPIC1_MASK          0x4000U
  #define INTC_ICSR_INT_MASK            0x8000U
  #define INTC_ICSR_VAB_MASK            0x1FC0U
  #define INTC_ICSR_VAB_BITNUM          0x06U
  #define INTC_ICSR_IPIC_MASK           0x6000U
  #define INTC_ICSR_IPIC_BITNUM         0x0DU
  #define INTC_ICSR                     *((volatile word *)0x0000F040)


  /*** INTC_VBA - Vector Base Address Register; 0x0000F041 ***/
  union {
    word Word;
  } INTC_VBA_STR;
  
  #define INTC_VBA_VECTOR_BASE_ADDRESS0_MASK 0x01U
  #define INTC_VBA_VECTOR_BASE_ADDRESS1_MASK 0x02U
  #define INTC_VBA_VECTOR_BASE_ADDRESS2_MASK 0x04U
  #define INTC_VBA_VECTOR_BASE_ADDRESS3_MASK 0x08U
  #define INTC_VBA_VECTOR_BASE_ADDRESS4_MASK 0x10U
  #define INTC_VBA_VECTOR_BASE_ADDRESS5_MASK 0x20U
  #define INTC_VBA_VECTOR_BASE_ADDRESS6_MASK 0x40U
  #define INTC_VBA_VECTOR_BASE_ADDRESS7_MASK 0x80U
  #define INTC_VBA_VECTOR_BASE_ADDRESS8_MASK 0x0100U
  #define INTC_VBA_VECTOR_BASE_ADDRESS9_MASK 0x0200U
  #define INTC_VBA_VECTOR_BASE_ADDRESS10_MASK 0x0400U
  #define INTC_VBA_VECTOR_BASE_ADDRESS11_MASK 0x0800U
  #define INTC_VBA_VECTOR_BASE_ADDRESS12_MASK 0x1000U
  #define INTC_VBA_VECTOR_BASE_ADDRESS13_MASK 0x2000U
  #define INTC_VBA_VECTOR_BASE_ADDRESS_MASK 0x3FFFU
  #define INTC_VBA_VECTOR_BASE_ADDRESS_BITNUM 0x00U
  #define INTC_VBA                      *((volatile word *)0x0000F041)


  /*** INTC_IAR0 - Interrupt Assignment Register 0; 0x0000F042 ***/
  union {
    word Word;
  } INTC_IAR0_STR;
  
  #define INTC_IAR0_USER10_MASK         0x01U
  #define INTC_IAR0_USER11_MASK         0x02U
  #define INTC_IAR0_USER12_MASK         0x04U
  #define INTC_IAR0_USER13_MASK         0x08U
  #define INTC_IAR0_USER14_MASK         0x10U
  #define INTC_IAR0_USER15_MASK         0x20U
  #define INTC_IAR0_USER20_MASK         0x0100U
  #define INTC_IAR0_USER21_MASK         0x0200U
  #define INTC_IAR0_USER22_MASK         0x0400U
  #define INTC_IAR0_USER23_MASK         0x0800U
  #define INTC_IAR0_USER24_MASK         0x1000U
  #define INTC_IAR0_USER25_MASK         0x2000U
  #define INTC_IAR0_USER1_MASK          0x3FU
  #define INTC_IAR0_USER1_BITNUM        0x00U
  #define INTC_IAR0_USER2_MASK          0x3F00U
  #define INTC_IAR0_USER2_BITNUM        0x08U
  #define INTC_IAR0                     *((volatile word *)0x0000F042)


  /*** INTC_IAR1 - Interrupt Assignment Register 1; 0x0000F043 ***/
  union {
    word Word;
  } INTC_IAR1_STR;
  
  #define INTC_IAR1_USER30_MASK         0x01U
  #define INTC_IAR1_USER31_MASK         0x02U
  #define INTC_IAR1_USER32_MASK         0x04U
  #define INTC_IAR1_USER33_MASK         0x08U
  #define INTC_IAR1_USER34_MASK         0x10U
  #define INTC_IAR1_USER35_MASK         0x20U
  #define INTC_IAR1_USER40_MASK         0x0100U
  #define INTC_IAR1_USER41_MASK         0x0200U
  #define INTC_IAR1_USER42_MASK         0x0400U
  #define INTC_IAR1_USER43_MASK         0x0800U
  #define INTC_IAR1_USER44_MASK         0x1000U
  #define INTC_IAR1_USER45_MASK         0x2000U
  #define INTC_IAR1_USER3_MASK          0x3FU
  #define INTC_IAR1_USER3_BITNUM        0x00U
  #define INTC_IAR1_USER4_MASK          0x3F00U
  #define INTC_IAR1_USER4_BITNUM        0x08U
  #define INTC_IAR1                     *((volatile word *)0x0000F043)


  /*** INTC_IAR2 - Interrupt Assignment Register 2; 0x0000F044 ***/
  union {
    word Word;
  } INTC_IAR2_STR;
  
  #define INTC_IAR2_USER50_MASK         0x01U
  #define INTC_IAR2_USER51_MASK         0x02U
  #define INTC_IAR2_USER52_MASK         0x04U
  #define INTC_IAR2_USER53_MASK         0x08U
  #define INTC_IAR2_USER54_MASK         0x10U
  #define INTC_IAR2_USER55_MASK         0x20U
  #define INTC_IAR2_USER60_MASK         0x0100U
  #define INTC_IAR2_USER61_MASK         0x0200U
  #define INTC_IAR2_USER62_MASK         0x0400U
  #define INTC_IAR2_USER63_MASK         0x0800U
  #define INTC_IAR2_USER64_MASK         0x1000U
  #define INTC_IAR2_USER65_MASK         0x2000U
  #define INTC_IAR2_USER5_MASK          0x3FU
  #define INTC_IAR2_USER5_BITNUM        0x00U
  #define INTC_IAR2_USER6_MASK          0x3F00U
  #define INTC_IAR2_USER6_BITNUM        0x08U
  #define INTC_IAR2                     *((volatile word *)0x0000F044)


  word Reserved0[27];                  /* Reserved (unused) registers */

} INTC_PRPH;

/******************************************
*** Peripheral ADC0
*******************************************/
typedef volatile struct {
  /*** ADC0_ADCSC1A - ADC0 Status and control register 1A; 0x0000F060 ***/
  union {
    word Word;
  } ADC0_ADCSC1A_STR;
  
  #define ADC0_ADCSC1A_ADCH0_MASK       0x01U
  #define ADC0_ADCSC1A_ADCH1_MASK       0x02U
  #define ADC0_ADCSC1A_ADCH2_MASK       0x04U
  #define ADC0_ADCSC1A_ADCH3_MASK       0x08U
  #define ADC0_ADCSC1A_ADCH4_MASK       0x10U
  #define ADC0_ADCSC1A_ADCO_MASK        0x20U
  #define ADC0_ADCSC1A_AIEN_MASK        0x40U
  #define ADC0_ADCSC1A_COCO_MASK        0x80U
  #define ADC0_ADCSC1A_ADCH_MASK        0x1FU
  #define ADC0_ADCSC1A_ADCH_BITNUM      0x00U
  #define ADC0_ADCSC1A                  *((volatile word *)0x0000F060)


  /*** ADC0_ADCSC2 - ADC0 Status and control register; 0x0000F061 ***/
  union {
    word Word;
  } ADC0_ADCSC2_STR;
  
  #define ADC0_ADCSC2_REFSEL0_MASK      0x01U
  #define ADC0_ADCSC2_REFSEL1_MASK      0x02U
  #define ADC0_ADCSC2_ECC_MASK          0x04U
  #define ADC0_ADCSC2_ADTRG_MASK        0x40U
  #define ADC0_ADCSC2_ADACT_MASK        0x80U
  #define ADC0_ADCSC2_REFSEL_MASK       0x03U
  #define ADC0_ADCSC2_REFSEL_BITNUM     0x00U
  #define ADC0_ADCSC2                   *((volatile word *)0x0000F061)


  word Reserved0[4];                   /* Reserved (unused) registers */
  
  /*** ADC0_ADCCFG - ADC0 Configuration register; 0x0000F066 ***/
  union {
    word Word;
  } ADC0_ADCCFG_STR;
  
  #define ADC0_ADCCFG_ADICLK0_MASK      0x01U
  #define ADC0_ADCCFG_ADICLK1_MASK      0x02U
  #define ADC0_ADCCFG_MODE0_MASK        0x04U
  #define ADC0_ADCCFG_MODE1_MASK        0x08U
  #define ADC0_ADCCFG_ADLSMP_MASK       0x10U
  #define ADC0_ADCCFG_ADIV0_MASK        0x20U
  #define ADC0_ADCCFG_ADIV1_MASK        0x40U
  #define ADC0_ADCCFG_ADLPC_MASK        0x80U
  #define ADC0_ADCCFG_ADICLK_MASK       0x03U
  #define ADC0_ADCCFG_ADICLK_BITNUM     0x00U
  #define ADC0_ADCCFG_MODE_MASK         0x0CU
  #define ADC0_ADCCFG_MODE_BITNUM       0x02U
  #define ADC0_ADCCFG_ADIV_MASK         0x60U
  #define ADC0_ADCCFG_ADIV_BITNUM       0x05U
  #define ADC0_ADCCFG                   *((volatile word *)0x0000F066)


  word Reserved1[3];                   /* Reserved (unused) registers */
  
  /*** ADC0_ADCSC1B - ADC0 Status and control register 1B; 0x0000F06A ***/
  union {
    word Word;
  } ADC0_ADCSC1B_STR;
  
  #define ADC0_ADCSC1B_ADCH0_MASK       0x01U
  #define ADC0_ADCSC1B_ADCH1_MASK       0x02U
  #define ADC0_ADCSC1B_ADCH2_MASK       0x04U
  #define ADC0_ADCSC1B_ADCH3_MASK       0x08U
  #define ADC0_ADCSC1B_ADCH4_MASK       0x10U
  #define ADC0_ADCSC1B_ADCO_MASK        0x20U
  #define ADC0_ADCSC1B_AIEN_MASK        0x40U
  #define ADC0_ADCSC1B_COCO_MASK        0x80U
  #define ADC0_ADCSC1B_ADCH_MASK        0x1FU
  #define ADC0_ADCSC1B_ADCH_BITNUM      0x00U
  #define ADC0_ADCSC1B                  *((volatile word *)0x0000F06A)


  /*** ADC0_ADCRA - ADC0 Data Result Registers A; 0x0000F06B ***/
  union {
    word Word;
  } ADC0_ADCRA_STR;
  
  #define ADC0_ADCRA_ADR0_MASK          0x08U
  #define ADC0_ADCRA_ADR1_MASK          0x10U
  #define ADC0_ADCRA_ADR2_MASK          0x20U
  #define ADC0_ADCRA_ADR3_MASK          0x40U
  #define ADC0_ADCRA_ADR4_MASK          0x80U
  #define ADC0_ADCRA_ADR5_MASK          0x0100U
  #define ADC0_ADCRA_ADR6_MASK          0x0200U
  #define ADC0_ADCRA_ADR7_MASK          0x0400U
  #define ADC0_ADCRA_ADR8_MASK          0x0800U
  #define ADC0_ADCRA_ADR9_MASK          0x1000U
  #define ADC0_ADCRA_ADR10_MASK         0x2000U
  #define ADC0_ADCRA_ADR11_MASK         0x4000U
  #define ADC0_ADCRA_ADR_MASK           0x7FF8U
  #define ADC0_ADCRA_ADR_BITNUM         0x03U
  #define ADC0_ADCRA                    *((volatile word *)0x0000F06B)


  /*** ADC0_ADCRB - ADC0 Data Result Registers B; 0x0000F06C ***/
  union {
    word Word;
  } ADC0_ADCRB_STR;
  
  #define ADC0_ADCRB_ADR0_MASK          0x08U
  #define ADC0_ADCRB_ADR1_MASK          0x10U
  #define ADC0_ADCRB_ADR2_MASK          0x20U
  #define ADC0_ADCRB_ADR3_MASK          0x40U
  #define ADC0_ADCRB_ADR4_MASK          0x80U
  #define ADC0_ADCRB_ADR5_MASK          0x0100U
  #define ADC0_ADCRB_ADR6_MASK          0x0200U
  #define ADC0_ADCRB_ADR7_MASK          0x0400U
  #define ADC0_ADCRB_ADR8_MASK          0x0800U
  #define ADC0_ADCRB_ADR9_MASK          0x1000U
  #define ADC0_ADCRB_ADR10_MASK         0x2000U
  #define ADC0_ADCRB_ADR11_MASK         0x4000U
  #define ADC0_ADCRB_ADR_MASK           0x7FF8U
  #define ADC0_ADCRB_ADR_BITNUM         0x03U
  #define ADC0_ADCRB                    *((volatile word *)0x0000F06C)


  word Reserved2[19];                  /* Reserved (unused) registers */

} ADC0_PRPH;

/******************************************
*** Peripheral ADC1
*******************************************/
typedef volatile struct {
  /*** ADC1_ADCSC1A - ADC1 Status and control register 1A; 0x0000F080 ***/
  union {
    word Word;
  } ADC1_ADCSC1A_STR;
  
  #define ADC1_ADCSC1A_ADCH0_MASK       0x01U
  #define ADC1_ADCSC1A_ADCH1_MASK       0x02U
  #define ADC1_ADCSC1A_ADCH2_MASK       0x04U
  #define ADC1_ADCSC1A_ADCH3_MASK       0x08U
  #define ADC1_ADCSC1A_ADCH4_MASK       0x10U
  #define ADC1_ADCSC1A_ADCO_MASK        0x20U
  #define ADC1_ADCSC1A_AIEN_MASK        0x40U
  #define ADC1_ADCSC1A_COCO_MASK        0x80U
  #define ADC1_ADCSC1A_ADCH_MASK        0x1FU
  #define ADC1_ADCSC1A_ADCH_BITNUM      0x00U
  #define ADC1_ADCSC1A                  *((volatile word *)0x0000F080)


  /*** ADC1_ADCSC2 - ADC1 Status and control register; 0x0000F081 ***/
  union {
    word Word;
  } ADC1_ADCSC2_STR;
  
  #define ADC1_ADCSC2_REFSEL0_MASK      0x01U
  #define ADC1_ADCSC2_REFSEL1_MASK      0x02U
  #define ADC1_ADCSC2_ECC_MASK          0x04U
  #define ADC1_ADCSC2_ADTRG_MASK        0x40U
  #define ADC1_ADCSC2_ADACT_MASK        0x80U
  #define ADC1_ADCSC2_REFSEL_MASK       0x03U
  #define ADC1_ADCSC2_REFSEL_BITNUM     0x00U
  #define ADC1_ADCSC2                   *((volatile word *)0x0000F081)


  word Reserved0[4];                   /* Reserved (unused) registers */
  
  /*** ADC1_ADCCFG - ADC1 Configuration register; 0x0000F086 ***/
  union {
    word Word;
  } ADC1_ADCCFG_STR;
  
  #define ADC1_ADCCFG_ADICLK0_MASK      0x01U
  #define ADC1_ADCCFG_ADICLK1_MASK      0x02U
  #define ADC1_ADCCFG_MODE0_MASK        0x04U
  #define ADC1_ADCCFG_MODE1_MASK        0x08U
  #define ADC1_ADCCFG_ADLSMP_MASK       0x10U
  #define ADC1_ADCCFG_ADIV0_MASK        0x20U
  #define ADC1_ADCCFG_ADIV1_MASK        0x40U
  #define ADC1_ADCCFG_ADLPC_MASK        0x80U
  #define ADC1_ADCCFG_ADICLK_MASK       0x03U
  #define ADC1_ADCCFG_ADICLK_BITNUM     0x00U
  #define ADC1_ADCCFG_MODE_MASK         0x0CU
  #define ADC1_ADCCFG_MODE_BITNUM       0x02U
  #define ADC1_ADCCFG_ADIV_MASK         0x60U
  #define ADC1_ADCCFG_ADIV_BITNUM       0x05U
  #define ADC1_ADCCFG                   *((volatile word *)0x0000F086)


  word Reserved1[3];                   /* Reserved (unused) registers */
  
  /*** ADC1_ADCSC1B - ADC1 Status and control register 1B; 0x0000F08A ***/
  union {
    word Word;
  } ADC1_ADCSC1B_STR;
  
  #define ADC1_ADCSC1B_ADCH0_MASK       0x01U
  #define ADC1_ADCSC1B_ADCH1_MASK       0x02U
  #define ADC1_ADCSC1B_ADCH2_MASK       0x04U
  #define ADC1_ADCSC1B_ADCH3_MASK       0x08U
  #define ADC1_ADCSC1B_ADCH4_MASK       0x10U
  #define ADC1_ADCSC1B_ADCO_MASK        0x20U
  #define ADC1_ADCSC1B_AIEN_MASK        0x40U
  #define ADC1_ADCSC1B_COCO_MASK        0x80U
  #define ADC1_ADCSC1B_ADCH_MASK        0x1FU
  #define ADC1_ADCSC1B_ADCH_BITNUM      0x00U
  #define ADC1_ADCSC1B                  *((volatile word *)0x0000F08A)


  /*** ADC1_ADCRA - ADC1 Data Result Registers A; 0x0000F08B ***/
  union {
    word Word;
  } ADC1_ADCRA_STR;
  
  #define ADC1_ADCRA_ADR0_MASK          0x08U
  #define ADC1_ADCRA_ADR1_MASK          0x10U
  #define ADC1_ADCRA_ADR2_MASK          0x20U
  #define ADC1_ADCRA_ADR3_MASK          0x40U
  #define ADC1_ADCRA_ADR4_MASK          0x80U
  #define ADC1_ADCRA_ADR5_MASK          0x0100U
  #define ADC1_ADCRA_ADR6_MASK          0x0200U
  #define ADC1_ADCRA_ADR7_MASK          0x0400U
  #define ADC1_ADCRA_ADR8_MASK          0x0800U
  #define ADC1_ADCRA_ADR9_MASK          0x1000U
  #define ADC1_ADCRA_ADR10_MASK         0x2000U
  #define ADC1_ADCRA_ADR11_MASK         0x4000U
  #define ADC1_ADCRA_ADR_MASK           0x7FF8U
  #define ADC1_ADCRA_ADR_BITNUM         0x03U
  #define ADC1_ADCRA                    *((volatile word *)0x0000F08B)


  /*** ADC1_ADCRB - ADC1 Data Result Registers B; 0x0000F08C ***/
  union {
    word Word;
  } ADC1_ADCRB_STR;
  
  #define ADC1_ADCRB_ADR0_MASK          0x08U
  #define ADC1_ADCRB_ADR1_MASK          0x10U
  #define ADC1_ADCRB_ADR2_MASK          0x20U
  #define ADC1_ADCRB_ADR3_MASK          0x40U
  #define ADC1_ADCRB_ADR4_MASK          0x80U
  #define ADC1_ADCRB_ADR5_MASK          0x0100U
  #define ADC1_ADCRB_ADR6_MASK          0x0200U
  #define ADC1_ADCRB_ADR7_MASK          0x0400U
  #define ADC1_ADCRB_ADR8_MASK          0x0800U
  #define ADC1_ADCRB_ADR9_MASK          0x1000U
  #define ADC1_ADCRB_ADR10_MASK         0x2000U
  #define ADC1_ADCRB_ADR11_MASK         0x4000U
  #define ADC1_ADCRB_ADR_MASK           0x7FF8U
  #define ADC1_ADCRB_ADR_BITNUM         0x03U
  #define ADC1_ADCRB                    *((volatile word *)0x0000F08C)


  word Reserved2[19];                  /* Reserved (unused) registers */

} ADC1_PRPH;

/******************************************
*** Peripheral PGA0
*******************************************/
typedef volatile struct {
  /*** PGA0_CNTL0 - PGA0 Control Register 0; 0x0000F0A0 ***/
  union {
    word Word;
  } PGA0_CNTL0_STR;
  
  #define PGA0_CNTL0_EN_MASK            0x01U
  #define PGA0_CNTL0_LP_MASK            0x02U
  #define PGA0_CNTL0_GAINSEL0_MASK      0x04U
  #define PGA0_CNTL0_GAINSEL1_MASK      0x08U
  #define PGA0_CNTL0_GAINSEL2_MASK      0x10U
  #define PGA0_CNTL0_GAINSEL3_MASK      0x20U
  #define PGA0_CNTL0_GAINSEL4_MASK      0x40U
  #define PGA0_CNTL0_TM_MASK            0x80U
  #define PGA0_CNTL0_GAINSEL_MASK       0x7CU
  #define PGA0_CNTL0_GAINSEL_BITNUM     0x02U
  #define PGA0_CNTL0                    *((volatile word *)0x0000F0A0)


  /*** PGA0_CNTL1 - PGA0 Control Register 1; 0x0000F0A1 ***/
  union {
    word Word;
  } PGA0_CNTL1_STR;
  
  #define PGA0_CNTL1_CPD0_MASK          0x01U
  #define PGA0_CNTL1_CPD1_MASK          0x02U
  #define PGA0_CNTL1_CPD2_MASK          0x04U
  #define PGA0_CNTL1_CALMODE0_MASK      0x08U
  #define PGA0_CNTL1_CALMODE1_MASK      0x10U
  #define PGA0_CNTL1_BP_MASK            0x20U
  #define PGA0_CNTL1_CPD_MASK           0x07U
  #define PGA0_CNTL1_CPD_BITNUM         0x00U
  #define PGA0_CNTL1_CALMODE_MASK       0x18U
  #define PGA0_CNTL1_CALMODE_BITNUM     0x03U
  #define PGA0_CNTL1                    *((volatile word *)0x0000F0A1)


  /*** PGA0_CNTL2 - PGA0 Control Register 2; 0x0000F0A2 ***/
  union {
    word Word;
  } PGA0_CNTL2_STR;
  
  #define PGA0_CNTL2_ADIV0_MASK         0x01U
  #define PGA0_CNTL2_ADIV1_MASK         0x02U
  #define PGA0_CNTL2_NUM_CLK_GS0_MASK   0x04U
  #define PGA0_CNTL2_NUM_CLK_GS1_MASK   0x08U
  #define PGA0_CNTL2_NUM_CLK_GS2_MASK   0x10U
  #define PGA0_CNTL2_SWTRIG_MASK        0x20U
  #define PGA0_CNTL2_ADIV_MASK          0x03U
  #define PGA0_CNTL2_ADIV_BITNUM        0x00U
  #define PGA0_CNTL2_NUM_CLK_GS_MASK    0x1CU
  #define PGA0_CNTL2_NUM_CLK_GS_BITNUM  0x02U
  #define PGA0_CNTL2                    *((volatile word *)0x0000F0A2)


  /*** PGA0_STS - PGA0 Status Register; 0x0000F0A3 ***/
  union {
    word Word;
  } PGA0_STS_STR;
  
  #define PGA0_STS_STCOMP_MASK          0x01U
  #define PGA0_STS_RUNNING_MASK         0x02U
  #define PGA0_STS                      *((volatile word *)0x0000F0A3)


  word Reserved0[28];                  /* Reserved (unused) registers */

} PGA0_PRPH;

/******************************************
*** Peripheral PGA1
*******************************************/
typedef volatile struct {
  /*** PGA1_CNTL0 - PGA1 Control Register 0; 0x0000F0C0 ***/
  union {
    word Word;
  } PGA1_CNTL0_STR;
  
  #define PGA1_CNTL0_EN_MASK            0x01U
  #define PGA1_CNTL0_LP_MASK            0x02U
  #define PGA1_CNTL0_GAINSEL0_MASK      0x04U
  #define PGA1_CNTL0_GAINSEL1_MASK      0x08U
  #define PGA1_CNTL0_GAINSEL2_MASK      0x10U
  #define PGA1_CNTL0_GAINSEL3_MASK      0x20U
  #define PGA1_CNTL0_GAINSEL4_MASK      0x40U
  #define PGA1_CNTL0_TM_MASK            0x80U
  #define PGA1_CNTL0_GAINSEL_MASK       0x7CU
  #define PGA1_CNTL0_GAINSEL_BITNUM     0x02U
  #define PGA1_CNTL0                    *((volatile word *)0x0000F0C0)


  /*** PGA1_CNTL1 - PGA1 Control Register 1; 0x0000F0C1 ***/
  union {
    word Word;
  } PGA1_CNTL1_STR;
  
  #define PGA1_CNTL1_CPD0_MASK          0x01U
  #define PGA1_CNTL1_CPD1_MASK          0x02U
  #define PGA1_CNTL1_CPD2_MASK          0x04U
  #define PGA1_CNTL1_CALMODE0_MASK      0x08U
  #define PGA1_CNTL1_CALMODE1_MASK      0x10U
  #define PGA1_CNTL1_BP_MASK            0x20U
  #define PGA1_CNTL1_CPD_MASK           0x07U
  #define PGA1_CNTL1_CPD_BITNUM         0x00U
  #define PGA1_CNTL1_CALMODE_MASK       0x18U
  #define PGA1_CNTL1_CALMODE_BITNUM     0x03U
  #define PGA1_CNTL1                    *((volatile word *)0x0000F0C1)


  /*** PGA1_CNTL2 - PGA1 Control Register 2; 0x0000F0C2 ***/
  union {
    word Word;
  } PGA1_CNTL2_STR;
  
  #define PGA1_CNTL2_ADIV0_MASK         0x01U
  #define PGA1_CNTL2_ADIV1_MASK         0x02U
  #define PGA1_CNTL2_NUM_CLK_GS0_MASK   0x04U
  #define PGA1_CNTL2_NUM_CLK_GS1_MASK   0x08U
  #define PGA1_CNTL2_NUM_CLK_GS2_MASK   0x10U
  #define PGA1_CNTL2_SWTRIG_MASK        0x20U
  #define PGA1_CNTL2_ADIV_MASK          0x03U
  #define PGA1_CNTL2_ADIV_BITNUM        0x00U
  #define PGA1_CNTL2_NUM_CLK_GS_MASK    0x1CU
  #define PGA1_CNTL2_NUM_CLK_GS_BITNUM  0x02U
  #define PGA1_CNTL2                    *((volatile word *)0x0000F0C2)


  /*** PGA1_STS - PGA1 Status Register; 0x0000F0C3 ***/
  union {
    word Word;
  } PGA1_STS_STR;
  
  #define PGA1_STS_STCOMP_MASK          0x01U
  #define PGA1_STS_RUNNING_MASK         0x02U
  #define PGA1_STS                      *((volatile word *)0x0000F0C3)


  word Reserved0[28];                  /* Reserved (unused) registers */

} PGA1_PRPH;

/******************************************
*** Peripheral SCI
*******************************************/
typedef volatile struct {
  /*** SCI_RATE - QSCI 0 Baud Rate Register; 0x0000F0E0 ***/
  union {
    word Word;
  } SCI_RATE_STR;
  
  #define SCI_RATE_FRAC_SBR0_MASK       0x01U
  #define SCI_RATE_FRAC_SBR1_MASK       0x02U
  #define SCI_RATE_FRAC_SBR2_MASK       0x04U
  #define SCI_RATE_SBR0_MASK            0x08U
  #define SCI_RATE_SBR1_MASK            0x10U
  #define SCI_RATE_SBR2_MASK            0x20U
  #define SCI_RATE_SBR3_MASK            0x40U
  #define SCI_RATE_SBR4_MASK            0x80U
  #define SCI_RATE_SBR5_MASK            0x0100U
  #define SCI_RATE_SBR6_MASK            0x0200U
  #define SCI_RATE_SBR7_MASK            0x0400U
  #define SCI_RATE_SBR8_MASK            0x0800U
  #define SCI_RATE_SBR9_MASK            0x1000U
  #define SCI_RATE_SBR10_MASK           0x2000U
  #define SCI_RATE_SBR11_MASK           0x4000U
  #define SCI_RATE_SBR12_MASK           0x8000U
  #define SCI_RATE_FRAC_SBR_MASK        0x07U
  #define SCI_RATE_FRAC_SBR_BITNUM      0x00U
  #define SCI_RATE_SBR_MASK             0xFFF8U
  #define SCI_RATE_SBR_BITNUM           0x03U
  #define SCI_RATE                      *((volatile word *)0x0000F0E0)


  /*** SCI_CTRL1 - QSCI 0 Control Register; 0x0000F0E1 ***/
  union {
    word Word;
  } SCI_CTRL1_STR;
  
  #define SCI_CTRL1_SBK_MASK            0x01U
  #define SCI_CTRL1_RWU_MASK            0x02U
  #define SCI_CTRL1_RE_MASK             0x04U
  #define SCI_CTRL1_TE_MASK             0x08U
  #define SCI_CTRL1_REIE_MASK           0x10U
  #define SCI_CTRL1_RFIE_MASK           0x20U
  #define SCI_CTRL1_TIIE_MASK           0x40U
  #define SCI_CTRL1_TEIE_MASK           0x80U
  #define SCI_CTRL1_PT_MASK             0x0100U
  #define SCI_CTRL1_PE_MASK             0x0200U
  #define SCI_CTRL1_POL_MASK            0x0400U
  #define SCI_CTRL1_WAKE_MASK           0x0800U
  #define SCI_CTRL1_M_MASK              0x1000U
  #define SCI_CTRL1_RSRC_MASK           0x2000U
  #define SCI_CTRL1_SWAI_MASK           0x4000U
  #define SCI_CTRL1_LOOP_MASK           0x8000U
  #define SCI_CTRL1                     *((volatile word *)0x0000F0E1)


  /*** SCI_CTRL2 - QSCI 0 Control Register 2; 0x0000F0E2 ***/
  union {
    word Word;
  } SCI_CTRL2_STR;
  
  #define SCI_CTRL2_LIN_MODE_MASK       0x08U
  #define SCI_CTRL2_FIFO_EN_MASK        0x20U
  #define SCI_CTRL2_RFWM0_MASK          0x40U
  #define SCI_CTRL2_RFWM1_MASK          0x80U
  #define SCI_CTRL2_RFCNT0_MASK         0x0100U
  #define SCI_CTRL2_RFCNT1_MASK         0x0200U
  #define SCI_CTRL2_RFCNT2_MASK         0x0400U
  #define SCI_CTRL2_TFWM0_MASK          0x0800U
  #define SCI_CTRL2_TFWM1_MASK          0x1000U
  #define SCI_CTRL2_TFCNT0_MASK         0x2000U
  #define SCI_CTRL2_TFCNT1_MASK         0x4000U
  #define SCI_CTRL2_TFCNT2_MASK         0x8000U
  #define SCI_CTRL2_RFWM_MASK           0xC0U
  #define SCI_CTRL2_RFWM_BITNUM         0x06U
  #define SCI_CTRL2_RFCNT_MASK          0x0700U
  #define SCI_CTRL2_RFCNT_BITNUM        0x08U
  #define SCI_CTRL2_TFWM_MASK           0x1800U
  #define SCI_CTRL2_TFWM_BITNUM         0x0BU
  #define SCI_CTRL2_TFCNT_MASK          0xE000U
  #define SCI_CTRL2_TFCNT_BITNUM        0x0DU
  #define SCI_CTRL2                     *((volatile word *)0x0000F0E2)


  /*** SCI_STAT - QSCI 0 Status Register; 0x0000F0E3 ***/
  union {
    word Word;
  } SCI_STAT_STR;
  
  #define SCI_STAT_RAF_MASK             0x01U
  #define SCI_STAT_LSE_MASK             0x08U
  #define SCI_STAT_PF_MASK              0x0100U
  #define SCI_STAT_FE_MASK              0x0200U
  #define SCI_STAT_NF_MASK              0x0400U
  #define SCI_STAT_OR_MASK              0x0800U
  #define SCI_STAT_RIDLE_MASK           0x1000U
  #define SCI_STAT_RDRF_MASK            0x2000U
  #define SCI_STAT_TIDLE_MASK           0x4000U
  #define SCI_STAT_TDRE_MASK            0x8000U
  #define SCI_STAT                      *((volatile word *)0x0000F0E3)


  /*** SCI_DATA - QSCI 0 Data Register; 0x0000F0E4 ***/
  union {
    word Word;
  } SCI_DATA_STR;
  
  #define SCI_DATA_RECEIVE_TRANSMIT_DATA0_MASK 0x01U
  #define SCI_DATA_RECEIVE_TRANSMIT_DATA1_MASK 0x02U
  #define SCI_DATA_RECEIVE_TRANSMIT_DATA2_MASK 0x04U
  #define SCI_DATA_RECEIVE_TRANSMIT_DATA3_MASK 0x08U
  #define SCI_DATA_RECEIVE_TRANSMIT_DATA4_MASK 0x10U
  #define SCI_DATA_RECEIVE_TRANSMIT_DATA5_MASK 0x20U
  #define SCI_DATA_RECEIVE_TRANSMIT_DATA6_MASK 0x40U
  #define SCI_DATA_RECEIVE_TRANSMIT_DATA7_MASK 0x80U
  #define SCI_DATA_RECEIVE_TRANSMIT_DATA8_MASK 0x0100U
  #define SCI_DATA_RECEIVE_TRANSMIT_DATA_MASK 0x01FFU
  #define SCI_DATA_RECEIVE_TRANSMIT_DATA_BITNUM 0x00U
  #define SCI_DATA                      *((volatile word *)0x0000F0E4)


  word Reserved0[27];                  /* Reserved (unused) registers */

} SCI_PRPH;

/******************************************
*** Peripheral SPI
*******************************************/
typedef volatile struct {
  /*** SPI_SCTRL - QSPI 0 Status and Control Register; 0x0000F100 ***/
  union {
    word Word;
  } SPI_SCTRL_STR;
  
  #define SPI_SCTRL_SPTE_MASK           0x01U
  #define SPI_SCTRL_MODF_MASK           0x02U
  #define SPI_SCTRL_OVRF_MASK           0x04U
  #define SPI_SCTRL_SPRF_MASK           0x08U
  #define SPI_SCTRL_SPTIE_MASK          0x10U
  #define SPI_SCTRL_SPE_MASK            0x20U
  #define SPI_SCTRL_CPHA_MASK           0x40U
  #define SPI_SCTRL_CPOL_MASK           0x80U
  #define SPI_SCTRL_SPMSTR_MASK         0x0100U
  #define SPI_SCTRL_SPRIE_MASK          0x0200U
  #define SPI_SCTRL_MODFEN_MASK         0x0400U
  #define SPI_SCTRL_ERRIE_MASK          0x0800U
  #define SPI_SCTRL_DSO_MASK            0x1000U
  #define SPI_SCTRL_SPR0_MASK           0x2000U
  #define SPI_SCTRL_SPR1_MASK           0x4000U
  #define SPI_SCTRL_SPR2_MASK           0x8000U
  #define SPI_SCTRL_SPR_MASK            0xE000U
  #define SPI_SCTRL_SPR_BITNUM          0x0DU
  #define SPI_SCTRL                     *((volatile word *)0x0000F100)


  /*** SPI_DSCTRL - QSPI 0 Data Size and Control Register; 0x0000F101 ***/
  union {
    word Word;
  } SPI_DSCTRL_STR;
  
  #define SPI_DSCTRL_DS0_MASK           0x01U
  #define SPI_DSCTRL_DS1_MASK           0x02U
  #define SPI_DSCTRL_DS2_MASK           0x04U
  #define SPI_DSCTRL_DS3_MASK           0x08U
  #define SPI_DSCTRL_SPR3_MASK          0x10U
  #define SPI_DSCTRL_SSB_OVER_MASK      0x20U
  #define SPI_DSCTRL_SSB_STRB_MASK      0x40U
  #define SPI_DSCTRL_SSB_DDR_MASK       0x80U
  #define SPI_DSCTRL_SSB_AUTO_MASK      0x0100U
  #define SPI_DSCTRL_SSB_ODM_MASK       0x0200U
  #define SPI_DSCTRL_SSB_DATA_MASK      0x0400U
  #define SPI_DSCTRL_SSB_IN_MASK        0x0800U
  #define SPI_DSCTRL_BD2X_MASK          0x1000U
  #define SPI_DSCTRL_WOM_MASK           0x8000U
  #define SPI_DSCTRL_DS_MASK            0x0FU
  #define SPI_DSCTRL_DS_BITNUM          0x00U
  #define SPI_DSCTRL                    *((volatile word *)0x0000F101)


  /*** SPI_DRCV - QSPI 0 Data Receive Register; 0x0000F102 ***/
  union {
    word Word;
  } SPI_DRCV_STR;
  
  #define SPI_DRCV                      *((volatile word *)0x0000F102)


  /*** SPI_DXMIT - QSPI 0 Data Transmit Register; 0x0000F103 ***/
  union {
    word Word;
  } SPI_DXMIT_STR;
  
  #define SPI_DXMIT                     *((volatile word *)0x0000F103)


  word Reserved0[28];                  /* Reserved (unused) registers */

} SPI_PRPH;

/******************************************
*** Peripheral I2C
*******************************************/
typedef volatile struct {
  /*** I2C_ADDR - I2C Bus Address Register; 0x0000F120 ***/
  union {
    word Word;
  } I2C_ADDR_STR;
  
  #define I2C_ADDR_AD0_MASK             0x02U
  #define I2C_ADDR_AD1_MASK             0x04U
  #define I2C_ADDR_AD2_MASK             0x08U
  #define I2C_ADDR_AD3_MASK             0x10U
  #define I2C_ADDR_AD4_MASK             0x20U
  #define I2C_ADDR_AD5_MASK             0x40U
  #define I2C_ADDR_AD6_MASK             0x80U
  #define I2C_ADDR_AD_MASK              0xFEU
  #define I2C_ADDR_AD_BITNUM            0x01U
  #define I2C_ADDR                      *((volatile word *)0x0000F120)


  /*** I2C_FREQDIV - I2C Bus Frequency Divider Register; 0x0000F121 ***/
  union {
    word Word;
  } I2C_FREQDIV_STR;
  
  #define I2C_FREQDIV_ICR0_MASK         0x01U
  #define I2C_FREQDIV_ICR1_MASK         0x02U
  #define I2C_FREQDIV_ICR2_MASK         0x04U
  #define I2C_FREQDIV_ICR3_MASK         0x08U
  #define I2C_FREQDIV_ICR4_MASK         0x10U
  #define I2C_FREQDIV_ICR5_MASK         0x20U
  #define I2C_FREQDIV_MULT0_MASK        0x40U
  #define I2C_FREQDIV_MULT1_MASK        0x80U
  #define I2C_FREQDIV_ICR_MASK          0x3FU
  #define I2C_FREQDIV_ICR_BITNUM        0x00U
  #define I2C_FREQDIV_MULT_MASK         0xC0U
  #define I2C_FREQDIV_MULT_BITNUM       0x06U
  #define I2C_FREQDIV                   *((volatile word *)0x0000F121)


  /*** I2C_CR1 - I2C-Bus Control Register; 0x0000F122 ***/
  union {
    word Word;
  } I2C_CR1_STR;
  
  #define I2C_CR1_RSTA_MASK             0x04U
  #define I2C_CR1_TXAK_MASK             0x08U
  #define I2C_CR1_TX_MASK               0x10U
  #define I2C_CR1_MST_MASK              0x20U
  #define I2C_CR1_IICIE_MASK            0x40U
  #define I2C_CR1_IICEN_MASK            0x80U
  #define I2C_CR1                       *((volatile word *)0x0000F122)


  /*** I2C_SR - I2C Bus Status Register; 0x0000F123 ***/
  union {
    word Word;
  } I2C_SR_STR;
  
  #define I2C_SR_RXAK_MASK              0x01U
  #define I2C_SR_IICIF_MASK             0x02U
  #define I2C_SR_SRW_MASK               0x04U
  #define I2C_SR_ARBL_MASK              0x10U
  #define I2C_SR_BUSY_MASK              0x20U
  #define I2C_SR_IAAS_MASK              0x40U
  #define I2C_SR_TCF_MASK               0x80U
  #define I2C_SR                        *((volatile word *)0x0000F123)


  /*** I2C_DATA - I2C Bus Data I/O Register; 0x0000F124 ***/
  union {
    word Word;
  } I2C_DATA_STR;
  
  #define I2C_DATA_DATA0_MASK           0x01U
  #define I2C_DATA_DATA1_MASK           0x02U
  #define I2C_DATA_DATA2_MASK           0x04U
  #define I2C_DATA_DATA3_MASK           0x08U
  #define I2C_DATA_DATA4_MASK           0x10U
  #define I2C_DATA_DATA5_MASK           0x20U
  #define I2C_DATA_DATA6_MASK           0x40U
  #define I2C_DATA_DATA7_MASK           0x80U
  #define I2C_DATA_DATA_MASK            0xFFU
  #define I2C_DATA_DATA_BITNUM          0x00U
  #define I2C_DATA                      *((volatile word *)0x0000F124)


  /*** I2C_CR2 - I2C Control Register; 0x0000F125 ***/
  union {
    word Word;
  } I2C_CR2_STR;
  
  #define I2C_CR2_AD8_MASK              0x01U
  #define I2C_CR2_AD9_MASK              0x02U
  #define I2C_CR2_AD10_MASK             0x04U
  #define I2C_CR2_ADEXT_MASK            0x40U
  #define I2C_CR2_GCAEN_MASK            0x80U
  #define I2C_CR2_AD_8_MASK             0x07U
  #define I2C_CR2_AD_8_BITNUM           0x00U
  #define I2C_CR2                       *((volatile word *)0x0000F125)


  /*** I2C_SMB_CSR - I2C SMBus Control and Status Register; 0x0000F126 ***/
  union {
    word Word;
  } I2C_SMB_CSR_STR;
  
  #define I2C_SMB_CSR_SHTF_MASK         0x04U
  #define I2C_SMB_CSR_SLTF_MASK         0x08U
  #define I2C_SMB_CSR_TCKSEL_MASK       0x10U
  #define I2C_SMB_CSR_SIICAEN_MASK      0x20U
  #define I2C_SMB_CSR_ALERTEN_MASK      0x40U
  #define I2C_SMB_CSR_FACK_MASK         0x80U
  #define I2C_SMB_CSR                   *((volatile word *)0x0000F126)


  /*** I2C_ADDR2 - I2C Bus Address Register 2; 0x0000F127 ***/
  union {
    word Word;
  } I2C_ADDR2_STR;
  
  #define I2C_ADDR2_SAD0_MASK           0x02U
  #define I2C_ADDR2_SAD1_MASK           0x04U
  #define I2C_ADDR2_SAD2_MASK           0x08U
  #define I2C_ADDR2_SAD3_MASK           0x10U
  #define I2C_ADDR2_SAD4_MASK           0x20U
  #define I2C_ADDR2_SAD5_MASK           0x40U
  #define I2C_ADDR2_SAD6_MASK           0x80U
  #define I2C_ADDR2_SAD_MASK            0xFEU
  #define I2C_ADDR2_SAD_BITNUM          0x01U
  #define I2C_ADDR2                     *((volatile word *)0x0000F127)


  /*** I2C_SLT1 - I2C SCL Low Time Out Register High; 0x0000F128 ***/
  union {
    word Word;
  } I2C_SLT1_STR;
  
  #define I2C_SLT1_SSLT8_MASK           0x01U
  #define I2C_SLT1_SSLT9_MASK           0x02U
  #define I2C_SLT1_SSLT10_MASK          0x04U
  #define I2C_SLT1_SSLT11_MASK          0x08U
  #define I2C_SLT1_SSLT12_MASK          0x10U
  #define I2C_SLT1_SSLT13_MASK          0x20U
  #define I2C_SLT1_SSLT14_MASK          0x40U
  #define I2C_SLT1_SSLT15_MASK          0x80U
  #define I2C_SLT1_SSLT_8_MASK          0xFFU
  #define I2C_SLT1_SSLT_8_BITNUM        0x00U
  #define I2C_SLT1                      *((volatile word *)0x0000F128)


  /*** I2C_SLT2 - I2C SCL Low Time Out Register Low; 0x0000F129 ***/
  union {
    word Word;
  } I2C_SLT2_STR;
  
  #define I2C_SLT2_SSLT0_MASK           0x01U
  #define I2C_SLT2_SSLT1_MASK           0x02U
  #define I2C_SLT2_SSLT2_MASK           0x04U
  #define I2C_SLT2_SSLT3_MASK           0x08U
  #define I2C_SLT2_SSLT4_MASK           0x10U
  #define I2C_SLT2_SSLT5_MASK           0x20U
  #define I2C_SLT2_SSLT6_MASK           0x40U
  #define I2C_SLT2_SSLT7_MASK           0x80U
  #define I2C_SLT2_SSLT_MASK            0xFFU
  #define I2C_SLT2_SSLT_BITNUM          0x00U
  #define I2C_SLT2                      *((volatile word *)0x0000F129)


  word Reserved0[22];                  /* Reserved (unused) registers */

} I2C_PRPH;

/******************************************
*** Peripheral COP
*******************************************/
typedef volatile struct {
  /*** COP_CTRL - COP Control Register; 0x0000F140 ***/
  union {
    word Word;
  } COP_CTRL_STR;
  
  #define COP_CTRL_CWP_MASK             0x01U
  #define COP_CTRL_CEN_MASK             0x02U
  #define COP_CTRL_CWEN_MASK            0x04U
  #define COP_CTRL_CSEN_MASK            0x08U
  #define COP_CTRL_CLOREN_MASK          0x10U
  #define COP_CTRL_CLKSEL0_MASK         0x20U
  #define COP_CTRL_CLKSEL1_MASK         0x40U
  #define COP_CTRL_PSS0_MASK            0x0100U
  #define COP_CTRL_PSS1_MASK            0x0200U
  #define COP_CTRL_CLKSEL_MASK          0x60U
  #define COP_CTRL_CLKSEL_BITNUM        0x05U
  #define COP_CTRL_PSS_MASK             0x0300U
  #define COP_CTRL_PSS_BITNUM           0x08U
  #define COP_CTRL                      *((volatile word *)0x0000F140)


  /*** COP_TOUT - Timeout Register; 0x0000F141 ***/
  union {
    word Word;
  } COP_TOUT_STR;
  
  #define COP_TOUT_TIMEOUT0_MASK        0x01U
  #define COP_TOUT_TIMEOUT1_MASK        0x02U
  #define COP_TOUT_TIMEOUT2_MASK        0x04U
  #define COP_TOUT_TIMEOUT3_MASK        0x08U
  #define COP_TOUT_TIMEOUT4_MASK        0x10U
  #define COP_TOUT_TIMEOUT5_MASK        0x20U
  #define COP_TOUT_TIMEOUT6_MASK        0x40U
  #define COP_TOUT_TIMEOUT7_MASK        0x80U
  #define COP_TOUT_TIMEOUT8_MASK        0x0100U
  #define COP_TOUT_TIMEOUT9_MASK        0x0200U
  #define COP_TOUT_TIMEOUT10_MASK       0x0400U
  #define COP_TOUT_TIMEOUT11_MASK       0x0800U
  #define COP_TOUT_TIMEOUT12_MASK       0x1000U
  #define COP_TOUT_TIMEOUT13_MASK       0x2000U
  #define COP_TOUT_TIMEOUT14_MASK       0x4000U
  #define COP_TOUT_TIMEOUT15_MASK       0x8000U
  #define COP_TOUT                      *((volatile word *)0x0000F141)


  /*** COP_CNTR - Counter Register; 0x0000F142 ***/
  union {
    word Word;
  } COP_CNTR_STR;
  
  #define COP_CNTR                      *((volatile word *)0x0000F142)


  word Reserved0[29];                  /* Reserved (unused) registers */

} COP_PRPH;

/******************************************
*** Peripheral OCCS
*******************************************/
typedef volatile struct {
  /*** OCCS_CTRL - PLL Control Register; 0x0000F160 ***/
  union {
    word Word;
  } OCCS_CTRL_STR;
  
  #define OCCS_CTRL_ZSRC0_MASK          0x01U
  #define OCCS_CTRL_ZSRC1_MASK          0x02U
  #define OCCS_CTRL_PRECS_MASK          0x04U
  #define OCCS_CTRL_PLLPD_MASK          0x10U
  #define OCCS_CTRL_LCKON_MASK          0x80U
  #define OCCS_CTRL_LOCIE_MASK          0x0800U
  #define OCCS_CTRL_PLLIE00_MASK        0x1000U
  #define OCCS_CTRL_PLLIE01_MASK        0x2000U
  #define OCCS_CTRL_PLLIE10_MASK        0x4000U
  #define OCCS_CTRL_PLLIE11_MASK        0x8000U
  #define OCCS_CTRL_ZSRC_MASK           0x03U
  #define OCCS_CTRL_ZSRC_BITNUM         0x00U
  #define OCCS_CTRL_PLLIE0_MASK         0x3000U
  #define OCCS_CTRL_PLLIE0_BITNUM       0x0CU
  #define OCCS_CTRL_PLLIE1_MASK         0xC000U
  #define OCCS_CTRL_PLLIE1_BITNUM       0x0EU
  #define OCCS_CTRL                     *((volatile word *)0x0000F160)


  /*** OCCS_DIVBY - PLL Divide- by Register; 0x0000F161 ***/
  union {
    word Word;
  } OCCS_DIVBY_STR;
  
  #define OCCS_DIVBY_COD0_MASK          0x0100U
  #define OCCS_DIVBY_COD1_MASK          0x0200U
  #define OCCS_DIVBY_COD2_MASK          0x0400U
  #define OCCS_DIVBY_COD3_MASK          0x0800U
  #define OCCS_DIVBY_LORTP0_MASK        0x1000U
  #define OCCS_DIVBY_LORTP1_MASK        0x2000U
  #define OCCS_DIVBY_LORTP2_MASK        0x4000U
  #define OCCS_DIVBY_LORTP3_MASK        0x8000U
  #define OCCS_DIVBY_COD_MASK           0x0F00U
  #define OCCS_DIVBY_COD_BITNUM         0x08U
  #define OCCS_DIVBY_LORTP_MASK         0xF000U
  #define OCCS_DIVBY_LORTP_BITNUM       0x0CU
  #define OCCS_DIVBY                    *((volatile word *)0x0000F161)


  /*** OCCS_STAT - PLL Status Register; 0x0000F162 ***/
  union {
    word Word;
  } OCCS_STAT_STR;
  
  #define OCCS_STAT_ZSRC0_MASK          0x01U
  #define OCCS_STAT_ZSRC1_MASK          0x02U
  #define OCCS_STAT_COSC_RDY_MASK       0x04U
  #define OCCS_STAT_PLLPDN_MASK         0x10U
  #define OCCS_STAT_LCK0_MASK           0x20U
  #define OCCS_STAT_LCK1_MASK           0x40U
  #define OCCS_STAT_LOCI_MASK           0x2000U
  #define OCCS_STAT_LOLI0_MASK          0x4000U
  #define OCCS_STAT_LOLI1_MASK          0x8000U
  #define OCCS_STAT_ZSRC_MASK           0x03U
  #define OCCS_STAT_ZSRC_BITNUM         0x00U
  #define OCCS_STAT_LCK_MASK            0x60U
  #define OCCS_STAT_LCK_BITNUM          0x05U
  #define OCCS_STAT_LOLI_MASK           0xC000U
  #define OCCS_STAT_LOLI_BITNUM         0x0EU
  #define OCCS_STAT                     *((volatile word *)0x0000F162)


  word Reserved0[1];                   /* Reserved (unused) registers */
  
  /*** OCCS_OCTRL - Oscillator Control Register; 0x0000F164 ***/
  union {
    word Word;
  } OCCS_OCTRL_STR;
  
  #define OCCS_OCTRL_TRIM0_MASK         0x01U
  #define OCCS_OCTRL_TRIM1_MASK         0x02U
  #define OCCS_OCTRL_TRIM2_MASK         0x04U
  #define OCCS_OCTRL_TRIM3_MASK         0x08U
  #define OCCS_OCTRL_TRIM4_MASK         0x10U
  #define OCCS_OCTRL_TRIM5_MASK         0x20U
  #define OCCS_OCTRL_TRIM6_MASK         0x40U
  #define OCCS_OCTRL_TRIM7_MASK         0x80U
  #define OCCS_OCTRL_TRIM8_MASK         0x0100U
  #define OCCS_OCTRL_TRIM9_MASK         0x0200U
  #define OCCS_OCTRL_EXT_SEL_MASK       0x0400U
  #define OCCS_OCTRL_RANGE_MASK         0x0800U
  #define OCCS_OCTRL_CLK_MODE_MASK      0x1000U
  #define OCCS_OCTRL_COHL_MASK          0x2000U
  #define OCCS_OCTRL_ROSB_MASK          0x4000U
  #define OCCS_OCTRL_ROPD_MASK          0x8000U
  #define OCCS_OCTRL_TRIM_MASK          0x03FFU
  #define OCCS_OCTRL_TRIM_BITNUM        0x00U
  #define OCCS_OCTRL                    *((volatile word *)0x0000F164)


  /*** OCCS_CLKCHKR - External Clock Check Reference Register; 0x0000F165 ***/
  union {
    word Word;
  } OCCS_CLKCHKR_STR;
  
  #define OCCS_CLKCHKR_REFERENCE_CNT0_MASK 0x01U
  #define OCCS_CLKCHKR_REFERENCE_CNT1_MASK 0x02U
  #define OCCS_CLKCHKR_REFERENCE_CNT2_MASK 0x04U
  #define OCCS_CLKCHKR_REFERENCE_CNT3_MASK 0x08U
  #define OCCS_CLKCHKR_REFERENCE_CNT4_MASK 0x10U
  #define OCCS_CLKCHKR_REFERENCE_CNT5_MASK 0x20U
  #define OCCS_CLKCHKR_REFERENCE_CNT6_MASK 0x40U
  #define OCCS_CLKCHKR_REFERENCE_CNT7_MASK 0x80U
  #define OCCS_CLKCHKR_REFERENCE_CNT8_MASK 0x0100U
  #define OCCS_CLKCHKR_REFERENCE_CNT9_MASK 0x0200U
  #define OCCS_CLKCHKR_REFERENCE_CNT10_MASK 0x0400U
  #define OCCS_CLKCHKR_REFERENCE_CNT11_MASK 0x0800U
  #define OCCS_CLKCHKR_REFERENCE_CNT12_MASK 0x1000U
  #define OCCS_CLKCHKR_REFERENCE_CNT13_MASK 0x2000U
  #define OCCS_CLKCHKR_REFERENCE_CNT14_MASK 0x4000U
  #define OCCS_CLKCHKR_CHK_ENA_MASK     0x8000U
  #define OCCS_CLKCHKR_REFERENCE_CNT_MASK 0x7FFFU
  #define OCCS_CLKCHKR_REFERENCE_CNT_BITNUM 0x00U
  #define OCCS_CLKCHKR                  *((volatile word *)0x0000F165)


  /*** OCCS_CLKCHKT - External Clock Check Target Register; 0x0000F166 ***/
  union {
    word Word;
  } OCCS_CLKCHKT_STR;
  
  #define OCCS_CLKCHKT_TARGET_CNT0_MASK 0x01U
  #define OCCS_CLKCHKT_TARGET_CNT1_MASK 0x02U
  #define OCCS_CLKCHKT_TARGET_CNT2_MASK 0x04U
  #define OCCS_CLKCHKT_TARGET_CNT3_MASK 0x08U
  #define OCCS_CLKCHKT_TARGET_CNT4_MASK 0x10U
  #define OCCS_CLKCHKT_TARGET_CNT5_MASK 0x20U
  #define OCCS_CLKCHKT_TARGET_CNT6_MASK 0x40U
  #define OCCS_CLKCHKT_TARGET_CNT_MASK  0x7FU
  #define OCCS_CLKCHKT_TARGET_CNT_BITNUM 0x00U
  #define OCCS_CLKCHKT                  *((volatile word *)0x0000F166)


  /*** OCCS_PROT - Protection Register; 0x0000F167 ***/
  union {
    word Word;
  } OCCS_PROT_STR;
  
  #define OCCS_PROT_PLLEP0_MASK         0x01U
  #define OCCS_PROT_PLLEP1_MASK         0x02U
  #define OCCS_PROT_OSCEP0_MASK         0x04U
  #define OCCS_PROT_OSCEP1_MASK         0x08U
  #define OCCS_PROT_FRQEP0_MASK         0x10U
  #define OCCS_PROT_FRQEP1_MASK         0x20U
  #define OCCS_PROT_PLLEP_MASK          0x03U
  #define OCCS_PROT_PLLEP_BITNUM        0x00U
  #define OCCS_PROT_OSCEP_MASK          0x0CU
  #define OCCS_PROT_OSCEP_BITNUM        0x02U
  #define OCCS_PROT_FRQEP_MASK          0x30U
  #define OCCS_PROT_FRQEP_BITNUM        0x04U
  #define OCCS_PROT                     *((volatile word *)0x0000F167)


  word Reserved1[24];                  /* Reserved (unused) registers */

} OCCS_PRPH;

/******************************************
*** Peripheral GPIOA
*******************************************/
typedef volatile struct {
  /*** GPIO_A_PUR - GPIO A Pull-up Enable Register; 0x0000F180 ***/
  union {
    word Word;
  } GPIO_A_PUR_STR;
  
  #define GPIO_A_PUR_PU0_MASK           0x01U
  #define GPIO_A_PUR_PU1_MASK           0x02U
  #define GPIO_A_PUR_PU2_MASK           0x04U
  #define GPIO_A_PUR_PU3_MASK           0x08U
  #define GPIO_A_PUR_PU4_MASK           0x10U
  #define GPIO_A_PUR_PU5_MASK           0x20U
  #define GPIO_A_PUR_PU6_MASK           0x40U
  #define GPIO_A_PUR_PU7_MASK           0x80U
  #define GPIO_A_PUR_PU_MASK            0xFFU
  #define GPIO_A_PUR_PU_BITNUM          0x00U
  #define GPIO_A_PUR                    *((volatile word *)0x0000F180)


  /*** GPIO_A_DR - GPIO A Data Register; 0x0000F181 ***/
  union {
    word Word;
  } GPIO_A_DR_STR;
  
  #define GPIO_A_DR_D0_MASK             0x01U
  #define GPIO_A_DR_D1_MASK             0x02U
  #define GPIO_A_DR_D2_MASK             0x04U
  #define GPIO_A_DR_D3_MASK             0x08U
  #define GPIO_A_DR_D4_MASK             0x10U
  #define GPIO_A_DR_D5_MASK             0x20U
  #define GPIO_A_DR_D6_MASK             0x40U
  #define GPIO_A_DR_D7_MASK             0x80U
  #define GPIO_A_DR_D_MASK              0xFFU
  #define GPIO_A_DR_D_BITNUM            0x00U
  #define GPIO_A_DR                     *((volatile word *)0x0000F181)


  /*** GPIO_A_DDR - GPIO A Data Direction Register; 0x0000F182 ***/
  union {
    word Word;
  } GPIO_A_DDR_STR;
  
  #define GPIO_A_DDR_DD0_MASK           0x01U
  #define GPIO_A_DDR_DD1_MASK           0x02U
  #define GPIO_A_DDR_DD2_MASK           0x04U
  #define GPIO_A_DDR_DD3_MASK           0x08U
  #define GPIO_A_DDR_DD4_MASK           0x10U
  #define GPIO_A_DDR_DD5_MASK           0x20U
  #define GPIO_A_DDR_DD6_MASK           0x40U
  #define GPIO_A_DDR_DD7_MASK           0x80U
  #define GPIO_A_DDR_DD_MASK            0xFFU
  #define GPIO_A_DDR_DD_BITNUM          0x00U
  #define GPIO_A_DDR                    *((volatile word *)0x0000F182)


  /*** GPIO_A_PER - GPIO A Peripheral Enable Registers; 0x0000F183 ***/
  union {
    word Word;
  } GPIO_A_PER_STR;
  
  #define GPIO_A_PER_PE0_MASK           0x01U
  #define GPIO_A_PER_PE1_MASK           0x02U
  #define GPIO_A_PER_PE2_MASK           0x04U
  #define GPIO_A_PER_PE3_MASK           0x08U
  #define GPIO_A_PER_PE4_MASK           0x10U
  #define GPIO_A_PER_PE5_MASK           0x20U
  #define GPIO_A_PER_PE6_MASK           0x40U
  #define GPIO_A_PER_PE7_MASK           0x80U
  #define GPIO_A_PER_PE_MASK            0xFFU
  #define GPIO_A_PER_PE_BITNUM          0x00U
  #define GPIO_A_PER                    *((volatile word *)0x0000F183)


  word Reserved0[1];                   /* Reserved (unused) registers */
  
  /*** GPIO_A_IENR - GPIO A Interrupt Enable Register; 0x0000F185 ***/
  union {
    word Word;
  } GPIO_A_IENR_STR;
  
  #define GPIO_A_IENR_IEN0_MASK         0x01U
  #define GPIO_A_IENR_IEN1_MASK         0x02U
  #define GPIO_A_IENR_IEN2_MASK         0x04U
  #define GPIO_A_IENR_IEN3_MASK         0x08U
  #define GPIO_A_IENR_IEN4_MASK         0x10U
  #define GPIO_A_IENR_IEN5_MASK         0x20U
  #define GPIO_A_IENR_IEN6_MASK         0x40U
  #define GPIO_A_IENR_IEN7_MASK         0x80U
  #define GPIO_A_IENR_IEN_MASK          0xFFU
  #define GPIO_A_IENR_IEN_BITNUM        0x00U
  #define GPIO_A_IENR                   *((volatile word *)0x0000F185)


  /*** GPIO_A_IPOLR - GPIO A Interrupt Polarity Register; 0x0000F186 ***/
  union {
    word Word;
  } GPIO_A_IPOLR_STR;
  
  #define GPIO_A_IPOLR_IPOL0_MASK       0x01U
  #define GPIO_A_IPOLR_IPOL1_MASK       0x02U
  #define GPIO_A_IPOLR_IPOL2_MASK       0x04U
  #define GPIO_A_IPOLR_IPOL3_MASK       0x08U
  #define GPIO_A_IPOLR_IPOL4_MASK       0x10U
  #define GPIO_A_IPOLR_IPOL5_MASK       0x20U
  #define GPIO_A_IPOLR_IPOL6_MASK       0x40U
  #define GPIO_A_IPOLR_IPOL7_MASK       0x80U
  #define GPIO_A_IPOLR_IPOL_MASK        0xFFU
  #define GPIO_A_IPOLR_IPOL_BITNUM      0x00U
  #define GPIO_A_IPOLR                  *((volatile word *)0x0000F186)


  /*** GPIO_A_IPR - GPIO A Interrupt Pending Register; 0x0000F187 ***/
  union {
    word Word;
  } GPIO_A_IPR_STR;
  
  #define GPIO_A_IPR_IP0_MASK           0x01U
  #define GPIO_A_IPR_IP1_MASK           0x02U
  #define GPIO_A_IPR_IP2_MASK           0x04U
  #define GPIO_A_IPR_IP3_MASK           0x08U
  #define GPIO_A_IPR_IP4_MASK           0x10U
  #define GPIO_A_IPR_IP5_MASK           0x20U
  #define GPIO_A_IPR_IP6_MASK           0x40U
  #define GPIO_A_IPR_IP7_MASK           0x80U
  #define GPIO_A_IPR_IP_MASK            0xFFU
  #define GPIO_A_IPR_IP_BITNUM          0x00U
  #define GPIO_A_IPR                    *((volatile word *)0x0000F187)


  /*** GPIO_A_IESR - GPIO A Interrupt Edge Sensitive Register; 0x0000F188 ***/
  union {
    word Word;
  } GPIO_A_IESR_STR;
  
  #define GPIO_A_IESR_IES0_MASK         0x01U
  #define GPIO_A_IESR_IES1_MASK         0x02U
  #define GPIO_A_IESR_IES2_MASK         0x04U
  #define GPIO_A_IESR_IES3_MASK         0x08U
  #define GPIO_A_IESR_IES4_MASK         0x10U
  #define GPIO_A_IESR_IES5_MASK         0x20U
  #define GPIO_A_IESR_IES6_MASK         0x40U
  #define GPIO_A_IESR_IES7_MASK         0x80U
  #define GPIO_A_IESR_IES_MASK          0xFFU
  #define GPIO_A_IESR_IES_BITNUM        0x00U
  #define GPIO_A_IESR                   *((volatile word *)0x0000F188)


  word Reserved1[1];                   /* Reserved (unused) registers */
  
  /*** GPIO_A_RAWDATA - GPIO A Raw Data Register; 0x0000F18A ***/
  union {
    word Word;
  } GPIO_A_RAWDATA_STR;
  
  #define GPIO_A_RAWDATA_RAW_DATA0_MASK 0x01U
  #define GPIO_A_RAWDATA_RAW_DATA1_MASK 0x02U
  #define GPIO_A_RAWDATA_RAW_DATA2_MASK 0x04U
  #define GPIO_A_RAWDATA_RAW_DATA3_MASK 0x08U
  #define GPIO_A_RAWDATA_RAW_DATA4_MASK 0x10U
  #define GPIO_A_RAWDATA_RAW_DATA5_MASK 0x20U
  #define GPIO_A_RAWDATA_RAW_DATA6_MASK 0x40U
  #define GPIO_A_RAWDATA_RAW_DATA7_MASK 0x80U
  #define GPIO_A_RAWDATA_RAW_DATA_MASK  0xFFU
  #define GPIO_A_RAWDATA_RAW_DATA_BITNUM 0x00U
  #define GPIO_A_RAWDATA                *((volatile word *)0x0000F18A)


  /*** GPIO_A_DRIVE - GPIO A Drive Strength Control Register; 0x0000F18B ***/
  union {
    word Word;
  } GPIO_A_DRIVE_STR;
  
  #define GPIO_A_DRIVE_DRIVE0_MASK      0x01U
  #define GPIO_A_DRIVE_DRIVE1_MASK      0x02U
  #define GPIO_A_DRIVE_DRIVE2_MASK      0x04U
  #define GPIO_A_DRIVE_DRIVE3_MASK      0x08U
  #define GPIO_A_DRIVE_DRIVE4_MASK      0x10U
  #define GPIO_A_DRIVE_DRIVE5_MASK      0x20U
  #define GPIO_A_DRIVE_DRIVE6_MASK      0x40U
  #define GPIO_A_DRIVE_DRIVE7_MASK      0x80U
  #define GPIO_A_DRIVE_DRIVE_MASK       0xFFU
  #define GPIO_A_DRIVE_DRIVE_BITNUM     0x00U
  #define GPIO_A_DRIVE                  *((volatile word *)0x0000F18B)


  /*** GPIO_A_IFE - GPIO A Input Filter Control Register; 0x0000F18C ***/
  union {
    word Word;
  } GPIO_A_IFE_STR;
  
  #define GPIO_A_IFE_IFE0_MASK          0x01U
  #define GPIO_A_IFE_IFE1_MASK          0x02U
  #define GPIO_A_IFE_IFE2_MASK          0x04U
  #define GPIO_A_IFE_IFE3_MASK          0x08U
  #define GPIO_A_IFE_IFE4_MASK          0x10U
  #define GPIO_A_IFE_IFE5_MASK          0x20U
  #define GPIO_A_IFE_IFE6_MASK          0x40U
  #define GPIO_A_IFE_IFE7_MASK          0x80U
  #define GPIO_A_IFE_IFE_MASK           0xFFU
  #define GPIO_A_IFE_IFE_BITNUM         0x00U
  #define GPIO_A_IFE                    *((volatile word *)0x0000F18C)


  /*** GPIO_A_SLEW - GPIO A Slew Rate Control Register; 0x0000F18D ***/
  union {
    word Word;
  } GPIO_A_SLEW_STR;
  
  #define GPIO_A_SLEW_SLEW0_MASK        0x01U
  #define GPIO_A_SLEW_SLEW1_MASK        0x02U
  #define GPIO_A_SLEW_SLEW2_MASK        0x04U
  #define GPIO_A_SLEW_SLEW3_MASK        0x08U
  #define GPIO_A_SLEW_SLEW4_MASK        0x10U
  #define GPIO_A_SLEW_SLEW5_MASK        0x20U
  #define GPIO_A_SLEW_SLEW6_MASK        0x40U
  #define GPIO_A_SLEW_SLEW7_MASK        0x80U
  #define GPIO_A_SLEW_SLEW_MASK         0xFFU
  #define GPIO_A_SLEW_SLEW_BITNUM       0x00U
  #define GPIO_A_SLEW                   *((volatile word *)0x0000F18D)


  word Reserved2[18];                  /* Reserved (unused) registers */

} GPIOA_PRPH;

/******************************************
*** Peripheral GPIOB
*******************************************/
typedef volatile struct {
  /*** GPIO_B_PUR - GPIO B Pull-up Enable Register; 0x0000F1A0 ***/
  union {
    word Word;
  } GPIO_B_PUR_STR;
  
  #define GPIO_B_PUR_PU0_MASK           0x01U
  #define GPIO_B_PUR_PU1_MASK           0x02U
  #define GPIO_B_PUR_PU2_MASK           0x04U
  #define GPIO_B_PUR_PU3_MASK           0x08U
  #define GPIO_B_PUR_PU4_MASK           0x10U
  #define GPIO_B_PUR_PU5_MASK           0x20U
  #define GPIO_B_PUR_PU6_MASK           0x40U
  #define GPIO_B_PUR_PU7_MASK           0x80U
  #define GPIO_B_PUR_PU_MASK            0xFFU
  #define GPIO_B_PUR_PU_BITNUM          0x00U
  #define GPIO_B_PUR                    *((volatile word *)0x0000F1A0)


  /*** GPIO_B_DR - GPIO B Data Register; 0x0000F1A1 ***/
  union {
    word Word;
  } GPIO_B_DR_STR;
  
  #define GPIO_B_DR_D0_MASK             0x01U
  #define GPIO_B_DR_D1_MASK             0x02U
  #define GPIO_B_DR_D2_MASK             0x04U
  #define GPIO_B_DR_D3_MASK             0x08U
  #define GPIO_B_DR_D4_MASK             0x10U
  #define GPIO_B_DR_D5_MASK             0x20U
  #define GPIO_B_DR_D6_MASK             0x40U
  #define GPIO_B_DR_D7_MASK             0x80U
  #define GPIO_B_DR_D_MASK              0xFFU
  #define GPIO_B_DR_D_BITNUM            0x00U
  #define GPIO_B_DR                     *((volatile word *)0x0000F1A1)


  /*** GPIO_B_DDR - GPIO B Data Direction Register; 0x0000F1A2 ***/
  union {
    word Word;
  } GPIO_B_DDR_STR;
  
  #define GPIO_B_DDR_DD0_MASK           0x01U
  #define GPIO_B_DDR_DD1_MASK           0x02U
  #define GPIO_B_DDR_DD2_MASK           0x04U
  #define GPIO_B_DDR_DD3_MASK           0x08U
  #define GPIO_B_DDR_DD4_MASK           0x10U
  #define GPIO_B_DDR_DD5_MASK           0x20U
  #define GPIO_B_DDR_DD6_MASK           0x40U
  #define GPIO_B_DDR_DD7_MASK           0x80U
  #define GPIO_B_DDR_DD_MASK            0xFFU
  #define GPIO_B_DDR_DD_BITNUM          0x00U
  #define GPIO_B_DDR                    *((volatile word *)0x0000F1A2)


  /*** GPIO_B_PER - GPIO B Peripheral Enable Registers; 0x0000F1A3 ***/
  union {
    word Word;
  } GPIO_B_PER_STR;
  
  #define GPIO_B_PER_PE0_MASK           0x01U
  #define GPIO_B_PER_PE1_MASK           0x02U
  #define GPIO_B_PER_PE2_MASK           0x04U
  #define GPIO_B_PER_PE3_MASK           0x08U
  #define GPIO_B_PER_PE4_MASK           0x10U
  #define GPIO_B_PER_PE5_MASK           0x20U
  #define GPIO_B_PER_PE6_MASK           0x40U
  #define GPIO_B_PER_PE7_MASK           0x80U
  #define GPIO_B_PER_PE_MASK            0xFFU
  #define GPIO_B_PER_PE_BITNUM          0x00U
  #define GPIO_B_PER                    *((volatile word *)0x0000F1A3)


  word Reserved0[1];                   /* Reserved (unused) registers */
  
  /*** GPIO_B_IENR - GPIO B Interrupt Enable Register; 0x0000F1A5 ***/
  union {
    word Word;
  } GPIO_B_IENR_STR;
  
  #define GPIO_B_IENR_IEN0_MASK         0x01U
  #define GPIO_B_IENR_IEN1_MASK         0x02U
  #define GPIO_B_IENR_IEN2_MASK         0x04U
  #define GPIO_B_IENR_IEN3_MASK         0x08U
  #define GPIO_B_IENR_IEN4_MASK         0x10U
  #define GPIO_B_IENR_IEN5_MASK         0x20U
  #define GPIO_B_IENR_IEN6_MASK         0x40U
  #define GPIO_B_IENR_IEN7_MASK         0x80U
  #define GPIO_B_IENR_IEN_MASK          0xFFU
  #define GPIO_B_IENR_IEN_BITNUM        0x00U
  #define GPIO_B_IENR                   *((volatile word *)0x0000F1A5)


  /*** GPIO_B_IPOLR - GPIO B Interrupt Polarity Register; 0x0000F1A6 ***/
  union {
    word Word;
  } GPIO_B_IPOLR_STR;
  
  #define GPIO_B_IPOLR_IPOL0_MASK       0x01U
  #define GPIO_B_IPOLR_IPOL1_MASK       0x02U
  #define GPIO_B_IPOLR_IPOL2_MASK       0x04U
  #define GPIO_B_IPOLR_IPOL3_MASK       0x08U
  #define GPIO_B_IPOLR_IPOL4_MASK       0x10U
  #define GPIO_B_IPOLR_IPOL5_MASK       0x20U
  #define GPIO_B_IPOLR_IPOL6_MASK       0x40U
  #define GPIO_B_IPOLR_IPOL7_MASK       0x80U
  #define GPIO_B_IPOLR_IPOL_MASK        0xFFU
  #define GPIO_B_IPOLR_IPOL_BITNUM      0x00U
  #define GPIO_B_IPOLR                  *((volatile word *)0x0000F1A6)


  /*** GPIO_B_IPR - GPIO B Interrupt Pending Register; 0x0000F1A7 ***/
  union {
    word Word;
  } GPIO_B_IPR_STR;
  
  #define GPIO_B_IPR_IP0_MASK           0x01U
  #define GPIO_B_IPR_IP1_MASK           0x02U
  #define GPIO_B_IPR_IP2_MASK           0x04U
  #define GPIO_B_IPR_IP3_MASK           0x08U
  #define GPIO_B_IPR_IP4_MASK           0x10U
  #define GPIO_B_IPR_IP5_MASK           0x20U
  #define GPIO_B_IPR_IP6_MASK           0x40U
  #define GPIO_B_IPR_IP7_MASK           0x80U
  #define GPIO_B_IPR_IP_MASK            0xFFU
  #define GPIO_B_IPR_IP_BITNUM          0x00U
  #define GPIO_B_IPR                    *((volatile word *)0x0000F1A7)


  /*** GPIO_B_IESR - GPIO B Interrupt Edge Sensitive Register; 0x0000F1A8 ***/
  union {
    word Word;
  } GPIO_B_IESR_STR;
  
  #define GPIO_B_IESR_IES0_MASK         0x01U
  #define GPIO_B_IESR_IES1_MASK         0x02U
  #define GPIO_B_IESR_IES2_MASK         0x04U
  #define GPIO_B_IESR_IES3_MASK         0x08U
  #define GPIO_B_IESR_IES4_MASK         0x10U
  #define GPIO_B_IESR_IES5_MASK         0x20U
  #define GPIO_B_IESR_IES6_MASK         0x40U
  #define GPIO_B_IESR_IES7_MASK         0x80U
  #define GPIO_B_IESR_IES_MASK          0xFFU
  #define GPIO_B_IESR_IES_BITNUM        0x00U
  #define GPIO_B_IESR                   *((volatile word *)0x0000F1A8)


  word Reserved1[1];                   /* Reserved (unused) registers */
  
  /*** GPIO_B_RAWDATA - GPIO B Raw Data Register; 0x0000F1AA ***/
  union {
    word Word;
  } GPIO_B_RAWDATA_STR;
  
  #define GPIO_B_RAWDATA_RAW_DATA0_MASK 0x01U
  #define GPIO_B_RAWDATA_RAW_DATA1_MASK 0x02U
  #define GPIO_B_RAWDATA_RAW_DATA2_MASK 0x04U
  #define GPIO_B_RAWDATA_RAW_DATA3_MASK 0x08U
  #define GPIO_B_RAWDATA_RAW_DATA4_MASK 0x10U
  #define GPIO_B_RAWDATA_RAW_DATA5_MASK 0x20U
  #define GPIO_B_RAWDATA_RAW_DATA6_MASK 0x40U
  #define GPIO_B_RAWDATA_RAW_DATA7_MASK 0x80U
  #define GPIO_B_RAWDATA_RAW_DATA_MASK  0xFFU
  #define GPIO_B_RAWDATA_RAW_DATA_BITNUM 0x00U
  #define GPIO_B_RAWDATA                *((volatile word *)0x0000F1AA)


  /*** GPIO_B_DRIVE - GPIO B Drive Strength Control Register; 0x0000F1AB ***/
  union {
    word Word;
  } GPIO_B_DRIVE_STR;
  
  #define GPIO_B_DRIVE_DRIVE0_MASK      0x01U
  #define GPIO_B_DRIVE_DRIVE1_MASK      0x02U
  #define GPIO_B_DRIVE_DRIVE2_MASK      0x04U
  #define GPIO_B_DRIVE_DRIVE3_MASK      0x08U
  #define GPIO_B_DRIVE_DRIVE4_MASK      0x10U
  #define GPIO_B_DRIVE_DRIVE5_MASK      0x20U
  #define GPIO_B_DRIVE_DRIVE6_MASK      0x40U
  #define GPIO_B_DRIVE_DRIVE7_MASK      0x80U
  #define GPIO_B_DRIVE_DRIVE_MASK       0xFFU
  #define GPIO_B_DRIVE_DRIVE_BITNUM     0x00U
  #define GPIO_B_DRIVE                  *((volatile word *)0x0000F1AB)


  /*** GPIO_B_IFE - GPIO B Input Filter Control Register; 0x0000F1AC ***/
  union {
    word Word;
  } GPIO_B_IFE_STR;
  
  #define GPIO_B_IFE_IFE0_MASK          0x01U
  #define GPIO_B_IFE_IFE1_MASK          0x02U
  #define GPIO_B_IFE_IFE2_MASK          0x04U
  #define GPIO_B_IFE_IFE3_MASK          0x08U
  #define GPIO_B_IFE_IFE4_MASK          0x10U
  #define GPIO_B_IFE_IFE5_MASK          0x20U
  #define GPIO_B_IFE_IFE6_MASK          0x40U
  #define GPIO_B_IFE_IFE7_MASK          0x80U
  #define GPIO_B_IFE_IFE_MASK           0xFFU
  #define GPIO_B_IFE_IFE_BITNUM         0x00U
  #define GPIO_B_IFE                    *((volatile word *)0x0000F1AC)


  /*** GPIO_B_SLEW - GPIO B Slew Rate Control Register; 0x0000F1AD ***/
  union {
    word Word;
  } GPIO_B_SLEW_STR;
  
  #define GPIO_B_SLEW_SLEW0_MASK        0x01U
  #define GPIO_B_SLEW_SLEW1_MASK        0x02U
  #define GPIO_B_SLEW_SLEW2_MASK        0x04U
  #define GPIO_B_SLEW_SLEW3_MASK        0x08U
  #define GPIO_B_SLEW_SLEW4_MASK        0x10U
  #define GPIO_B_SLEW_SLEW5_MASK        0x20U
  #define GPIO_B_SLEW_SLEW6_MASK        0x40U
  #define GPIO_B_SLEW_SLEW7_MASK        0x80U
  #define GPIO_B_SLEW_SLEW_MASK         0xFFU
  #define GPIO_B_SLEW_SLEW_BITNUM       0x00U
  #define GPIO_B_SLEW                   *((volatile word *)0x0000F1AD)


  word Reserved2[18];                  /* Reserved (unused) registers */

} GPIOB_PRPH;

/******************************************
*** Peripheral GPIOC
*******************************************/
typedef volatile struct {
  /*** GPIO_C_PUR - GPIO C Pull-up Enable Register; 0x0000F1C0 ***/
  union {
    word Word;
  } GPIO_C_PUR_STR;
  
  #define GPIO_C_PUR_PU0_MASK           0x01U
  #define GPIO_C_PUR_PU1_MASK           0x02U
  #define GPIO_C_PUR_PU2_MASK           0x04U
  #define GPIO_C_PUR_PU3_MASK           0x08U
  #define GPIO_C_PUR_PU4_MASK           0x10U
  #define GPIO_C_PUR_PU5_MASK           0x20U
  #define GPIO_C_PUR_PU6_MASK           0x40U
  #define GPIO_C_PUR_PU7_MASK           0x80U
  #define GPIO_C_PUR_PU_MASK            0xFFU
  #define GPIO_C_PUR_PU_BITNUM          0x00U
  #define GPIO_C_PUR                    *((volatile word *)0x0000F1C0)


  /*** GPIO_C_DR - GPIO C Data Register; 0x0000F1C1 ***/
  union {
    word Word;
  } GPIO_C_DR_STR;
  
  #define GPIO_C_DR_D0_MASK             0x01U
  #define GPIO_C_DR_D1_MASK             0x02U
  #define GPIO_C_DR_D2_MASK             0x04U
  #define GPIO_C_DR_D3_MASK             0x08U
  #define GPIO_C_DR_D4_MASK             0x10U
  #define GPIO_C_DR_D5_MASK             0x20U
  #define GPIO_C_DR_D6_MASK             0x40U
  #define GPIO_C_DR_D7_MASK             0x80U
  #define GPIO_C_DR_D_MASK              0xFFU
  #define GPIO_C_DR_D_BITNUM            0x00U
  #define GPIO_C_DR                     *((volatile word *)0x0000F1C1)


  /*** GPIO_C_DDR - GPIO C Data Direction Register; 0x0000F1C2 ***/
  union {
    word Word;
  } GPIO_C_DDR_STR;
  
  #define GPIO_C_DDR_DD0_MASK           0x01U
  #define GPIO_C_DDR_DD1_MASK           0x02U
  #define GPIO_C_DDR_DD2_MASK           0x04U
  #define GPIO_C_DDR_DD3_MASK           0x08U
  #define GPIO_C_DDR_DD4_MASK           0x10U
  #define GPIO_C_DDR_DD5_MASK           0x20U
  #define GPIO_C_DDR_DD6_MASK           0x40U
  #define GPIO_C_DDR_DD7_MASK           0x80U
  #define GPIO_C_DDR_DD_MASK            0xFFU
  #define GPIO_C_DDR_DD_BITNUM          0x00U
  #define GPIO_C_DDR                    *((volatile word *)0x0000F1C2)


  /*** GPIO_C_PER - GPIO C Peripheral Enable Registers; 0x0000F1C3 ***/
  union {
    word Word;
  } GPIO_C_PER_STR;
  
  #define GPIO_C_PER_PE0_MASK           0x01U
  #define GPIO_C_PER_PE1_MASK           0x02U
  #define GPIO_C_PER_PE2_MASK           0x04U
  #define GPIO_C_PER_PE3_MASK           0x08U
  #define GPIO_C_PER_PE4_MASK           0x10U
  #define GPIO_C_PER_PE5_MASK           0x20U
  #define GPIO_C_PER_PE6_MASK           0x40U
  #define GPIO_C_PER_PE7_MASK           0x80U
  #define GPIO_C_PER_PE_MASK            0xFFU
  #define GPIO_C_PER_PE_BITNUM          0x00U
  #define GPIO_C_PER                    *((volatile word *)0x0000F1C3)


  word Reserved0[1];                   /* Reserved (unused) registers */
  
  /*** GPIO_C_IENR - GPIO C Interrupt Enable Register; 0x0000F1C5 ***/
  union {
    word Word;
  } GPIO_C_IENR_STR;
  
  #define GPIO_C_IENR_IEN0_MASK         0x01U
  #define GPIO_C_IENR_IEN1_MASK         0x02U
  #define GPIO_C_IENR_IEN2_MASK         0x04U
  #define GPIO_C_IENR_IEN3_MASK         0x08U
  #define GPIO_C_IENR_IEN4_MASK         0x10U
  #define GPIO_C_IENR_IEN5_MASK         0x20U
  #define GPIO_C_IENR_IEN6_MASK         0x40U
  #define GPIO_C_IENR_IEN7_MASK         0x80U
  #define GPIO_C_IENR_IEN_MASK          0xFFU
  #define GPIO_C_IENR_IEN_BITNUM        0x00U
  #define GPIO_C_IENR                   *((volatile word *)0x0000F1C5)


  /*** GPIO_C_IPOLR - GPIO C Interrupt Polarity Register; 0x0000F1C6 ***/
  union {
    word Word;
  } GPIO_C_IPOLR_STR;
  
  #define GPIO_C_IPOLR_IPOL0_MASK       0x01U
  #define GPIO_C_IPOLR_IPOL1_MASK       0x02U
  #define GPIO_C_IPOLR_IPOL2_MASK       0x04U
  #define GPIO_C_IPOLR_IPOL3_MASK       0x08U
  #define GPIO_C_IPOLR_IPOL4_MASK       0x10U
  #define GPIO_C_IPOLR_IPOL5_MASK       0x20U
  #define GPIO_C_IPOLR_IPOL6_MASK       0x40U
  #define GPIO_C_IPOLR_IPOL7_MASK       0x80U
  #define GPIO_C_IPOLR_IPOL_MASK        0xFFU
  #define GPIO_C_IPOLR_IPOL_BITNUM      0x00U
  #define GPIO_C_IPOLR                  *((volatile word *)0x0000F1C6)


  /*** GPIO_C_IPR - GPIO C Interrupt Pending Register; 0x0000F1C7 ***/
  union {
    word Word;
  } GPIO_C_IPR_STR;
  
  #define GPIO_C_IPR_IP0_MASK           0x01U
  #define GPIO_C_IPR_IP1_MASK           0x02U
  #define GPIO_C_IPR_IP2_MASK           0x04U
  #define GPIO_C_IPR_IP3_MASK           0x08U
  #define GPIO_C_IPR_IP4_MASK           0x10U
  #define GPIO_C_IPR_IP5_MASK           0x20U
  #define GPIO_C_IPR_IP6_MASK           0x40U
  #define GPIO_C_IPR_IP7_MASK           0x80U
  #define GPIO_C_IPR_IP_MASK            0xFFU
  #define GPIO_C_IPR_IP_BITNUM          0x00U
  #define GPIO_C_IPR                    *((volatile word *)0x0000F1C7)


  /*** GPIO_C_IESR - GPIO C Interrupt Edge Sensitive Register; 0x0000F1C8 ***/
  union {
    word Word;
  } GPIO_C_IESR_STR;
  
  #define GPIO_C_IESR_IES0_MASK         0x01U
  #define GPIO_C_IESR_IES1_MASK         0x02U
  #define GPIO_C_IESR_IES2_MASK         0x04U
  #define GPIO_C_IESR_IES3_MASK         0x08U
  #define GPIO_C_IESR_IES4_MASK         0x10U
  #define GPIO_C_IESR_IES5_MASK         0x20U
  #define GPIO_C_IESR_IES6_MASK         0x40U
  #define GPIO_C_IESR_IES7_MASK         0x80U
  #define GPIO_C_IESR_IES_MASK          0xFFU
  #define GPIO_C_IESR_IES_BITNUM        0x00U
  #define GPIO_C_IESR                   *((volatile word *)0x0000F1C8)


  word Reserved1[1];                   /* Reserved (unused) registers */
  
  /*** GPIO_C_RAWDATA - GPIO C Raw Data Register; 0x0000F1CA ***/
  union {
    word Word;
  } GPIO_C_RAWDATA_STR;
  
  #define GPIO_C_RAWDATA_RAW_DATA0_MASK 0x01U
  #define GPIO_C_RAWDATA_RAW_DATA1_MASK 0x02U
  #define GPIO_C_RAWDATA_RAW_DATA2_MASK 0x04U
  #define GPIO_C_RAWDATA_RAW_DATA3_MASK 0x08U
  #define GPIO_C_RAWDATA_RAW_DATA4_MASK 0x10U
  #define GPIO_C_RAWDATA_RAW_DATA5_MASK 0x20U
  #define GPIO_C_RAWDATA_RAW_DATA6_MASK 0x40U
  #define GPIO_C_RAWDATA_RAW_DATA7_MASK 0x80U
  #define GPIO_C_RAWDATA_RAW_DATA_MASK  0xFFU
  #define GPIO_C_RAWDATA_RAW_DATA_BITNUM 0x00U
  #define GPIO_C_RAWDATA                *((volatile word *)0x0000F1CA)


  /*** GPIO_C_DRIVE - GPIO C Drive Strength Control Register; 0x0000F1CB ***/
  union {
    word Word;
  } GPIO_C_DRIVE_STR;
  
  #define GPIO_C_DRIVE_DRIVE0_MASK      0x01U
  #define GPIO_C_DRIVE_DRIVE1_MASK      0x02U
  #define GPIO_C_DRIVE_DRIVE2_MASK      0x04U
  #define GPIO_C_DRIVE_DRIVE3_MASK      0x08U
  #define GPIO_C_DRIVE_DRIVE4_MASK      0x10U
  #define GPIO_C_DRIVE_DRIVE5_MASK      0x20U
  #define GPIO_C_DRIVE_DRIVE6_MASK      0x40U
  #define GPIO_C_DRIVE_DRIVE7_MASK      0x80U
  #define GPIO_C_DRIVE_DRIVE_MASK       0xFFU
  #define GPIO_C_DRIVE_DRIVE_BITNUM     0x00U
  #define GPIO_C_DRIVE                  *((volatile word *)0x0000F1CB)


  /*** GPIO_C_IFE - GPIO C Input Filter Control Register; 0x0000F1CC ***/
  union {
    word Word;
  } GPIO_C_IFE_STR;
  
  #define GPIO_C_IFE_IFE0_MASK          0x01U
  #define GPIO_C_IFE_IFE1_MASK          0x02U
  #define GPIO_C_IFE_IFE2_MASK          0x04U
  #define GPIO_C_IFE_IFE3_MASK          0x08U
  #define GPIO_C_IFE_IFE4_MASK          0x10U
  #define GPIO_C_IFE_IFE5_MASK          0x20U
  #define GPIO_C_IFE_IFE6_MASK          0x40U
  #define GPIO_C_IFE_IFE7_MASK          0x80U
  #define GPIO_C_IFE_IFE_MASK           0xFFU
  #define GPIO_C_IFE_IFE_BITNUM         0x00U
  #define GPIO_C_IFE                    *((volatile word *)0x0000F1CC)


  /*** GPIO_C_SLEW - GPIO C Slew Rate Control Register; 0x0000F1CD ***/
  union {
    word Word;
  } GPIO_C_SLEW_STR;
  
  #define GPIO_C_SLEW_SLEW0_MASK        0x01U
  #define GPIO_C_SLEW_SLEW1_MASK        0x02U
  #define GPIO_C_SLEW_SLEW2_MASK        0x04U
  #define GPIO_C_SLEW_SLEW3_MASK        0x08U
  #define GPIO_C_SLEW_SLEW4_MASK        0x10U
  #define GPIO_C_SLEW_SLEW5_MASK        0x20U
  #define GPIO_C_SLEW_SLEW6_MASK        0x40U
  #define GPIO_C_SLEW_SLEW7_MASK        0x80U
  #define GPIO_C_SLEW_SLEW_MASK         0xFFU
  #define GPIO_C_SLEW_SLEW_BITNUM       0x00U
  #define GPIO_C_SLEW                   *((volatile word *)0x0000F1CD)


  word Reserved2[18];                  /* Reserved (unused) registers */

} GPIOC_PRPH;

/******************************************
*** Peripheral GPIOD
*******************************************/
typedef volatile struct {
  /*** GPIO_D_PUR - GPIO D Pull-up Enable Register; 0x0000F1E0 ***/
  union {
    word Word;
  } GPIO_D_PUR_STR;
  
  #define GPIO_D_PUR_PU0_MASK           0x01U
  #define GPIO_D_PUR_PU1_MASK           0x02U
  #define GPIO_D_PUR_PU2_MASK           0x04U
  #define GPIO_D_PUR_PU3_MASK           0x08U
  #define GPIO_D_PUR_PU_MASK            0x0FU
  #define GPIO_D_PUR_PU_BITNUM          0x00U
  #define GPIO_D_PUR                    *((volatile word *)0x0000F1E0)


  /*** GPIO_D_DR - GPIO D Data Register; 0x0000F1E1 ***/
  union {
    word Word;
  } GPIO_D_DR_STR;
  
  #define GPIO_D_DR_D0_MASK             0x01U
  #define GPIO_D_DR_D1_MASK             0x02U
  #define GPIO_D_DR_D2_MASK             0x04U
  #define GPIO_D_DR_D3_MASK             0x08U
  #define GPIO_D_DR_D_MASK              0x0FU
  #define GPIO_D_DR_D_BITNUM            0x00U
  #define GPIO_D_DR                     *((volatile word *)0x0000F1E1)


  /*** GPIO_D_DDR - GPIO D Data Direction Register; 0x0000F1E2 ***/
  union {
    word Word;
  } GPIO_D_DDR_STR;
  
  #define GPIO_D_DDR_DD0_MASK           0x01U
  #define GPIO_D_DDR_DD1_MASK           0x02U
  #define GPIO_D_DDR_DD2_MASK           0x04U
  #define GPIO_D_DDR_DD3_MASK           0x08U
  #define GPIO_D_DDR_DD_MASK            0x0FU
  #define GPIO_D_DDR_DD_BITNUM          0x00U
  #define GPIO_D_DDR                    *((volatile word *)0x0000F1E2)


  /*** GPIO_D_PER - GPIO D Peripheral Enable Registers; 0x0000F1E3 ***/
  union {
    word Word;
  } GPIO_D_PER_STR;
  
  #define GPIO_D_PER_PE0_MASK           0x01U
  #define GPIO_D_PER_PE1_MASK           0x02U
  #define GPIO_D_PER_PE2_MASK           0x04U
  #define GPIO_D_PER_PE3_MASK           0x08U
  #define GPIO_D_PER_PE_MASK            0x0FU
  #define GPIO_D_PER_PE_BITNUM          0x00U
  #define GPIO_D_PER                    *((volatile word *)0x0000F1E3)


  word Reserved0[1];                   /* Reserved (unused) registers */
  
  /*** GPIO_D_IENR - GPIO D Interrupt Enable Register; 0x0000F1E5 ***/
  union {
    word Word;
  } GPIO_D_IENR_STR;
  
  #define GPIO_D_IENR_IEN0_MASK         0x01U
  #define GPIO_D_IENR_IEN1_MASK         0x02U
  #define GPIO_D_IENR_IEN2_MASK         0x04U
  #define GPIO_D_IENR_IEN3_MASK         0x08U
  #define GPIO_D_IENR_IEN_MASK          0x0FU
  #define GPIO_D_IENR_IEN_BITNUM        0x00U
  #define GPIO_D_IENR                   *((volatile word *)0x0000F1E5)


  /*** GPIO_D_IPOLR - GPIO D Interrupt Polarity Register; 0x0000F1E6 ***/
  union {
    word Word;
  } GPIO_D_IPOLR_STR;
  
  #define GPIO_D_IPOLR_IPOL0_MASK       0x01U
  #define GPIO_D_IPOLR_IPOL1_MASK       0x02U
  #define GPIO_D_IPOLR_IPOL2_MASK       0x04U
  #define GPIO_D_IPOLR_IPOL3_MASK       0x08U
  #define GPIO_D_IPOLR_IPOL_MASK        0x0FU
  #define GPIO_D_IPOLR_IPOL_BITNUM      0x00U
  #define GPIO_D_IPOLR                  *((volatile word *)0x0000F1E6)


  /*** GPIO_D_IPR - GPIO D Interrupt Pending Register; 0x0000F1E7 ***/
  union {
    word Word;
  } GPIO_D_IPR_STR;
  
  #define GPIO_D_IPR_IP0_MASK           0x01U
  #define GPIO_D_IPR_IP1_MASK           0x02U
  #define GPIO_D_IPR_IP2_MASK           0x04U
  #define GPIO_D_IPR_IP3_MASK           0x08U
  #define GPIO_D_IPR_IP_MASK            0x0FU
  #define GPIO_D_IPR_IP_BITNUM          0x00U
  #define GPIO_D_IPR                    *((volatile word *)0x0000F1E7)


  /*** GPIO_D_IESR - GPIO D Interrupt Edge Sensitive Register; 0x0000F1E8 ***/
  union {
    word Word;
  } GPIO_D_IESR_STR;
  
  #define GPIO_D_IESR_IES0_MASK         0x01U
  #define GPIO_D_IESR_IES1_MASK         0x02U
  #define GPIO_D_IESR_IES2_MASK         0x04U
  #define GPIO_D_IESR_IES3_MASK         0x08U
  #define GPIO_D_IESR_IES_MASK          0x0FU
  #define GPIO_D_IESR_IES_BITNUM        0x00U
  #define GPIO_D_IESR                   *((volatile word *)0x0000F1E8)


  word Reserved1[1];                   /* Reserved (unused) registers */
  
  /*** GPIO_D_RAWDATA - GPIO D Raw Data Register; 0x0000F1EA ***/
  union {
    word Word;
  } GPIO_D_RAWDATA_STR;
  
  #define GPIO_D_RAWDATA_RAW_DATA0_MASK 0x01U
  #define GPIO_D_RAWDATA_RAW_DATA1_MASK 0x02U
  #define GPIO_D_RAWDATA_RAW_DATA2_MASK 0x04U
  #define GPIO_D_RAWDATA_RAW_DATA3_MASK 0x08U
  #define GPIO_D_RAWDATA_RAW_DATA_MASK  0x0FU
  #define GPIO_D_RAWDATA_RAW_DATA_BITNUM 0x00U
  #define GPIO_D_RAWDATA                *((volatile word *)0x0000F1EA)


  /*** GPIO_D_DRIVE - GPIO D Drive Strength Control Register; 0x0000F1EB ***/
  union {
    word Word;
  } GPIO_D_DRIVE_STR;
  
  #define GPIO_D_DRIVE_DRIVE0_MASK      0x01U
  #define GPIO_D_DRIVE_DRIVE1_MASK      0x02U
  #define GPIO_D_DRIVE_DRIVE2_MASK      0x04U
  #define GPIO_D_DRIVE_DRIVE3_MASK      0x08U
  #define GPIO_D_DRIVE_DRIVE_MASK       0x0FU
  #define GPIO_D_DRIVE_DRIVE_BITNUM     0x00U
  #define GPIO_D_DRIVE                  *((volatile word *)0x0000F1EB)


  /*** GPIO_D_IFE - GPIO D Input Filter Control Register; 0x0000F1EC ***/
  union {
    word Word;
  } GPIO_D_IFE_STR;
  
  #define GPIO_D_IFE_IFE0_MASK          0x01U
  #define GPIO_D_IFE_IFE1_MASK          0x02U
  #define GPIO_D_IFE_IFE2_MASK          0x04U
  #define GPIO_D_IFE_IFE3_MASK          0x08U
  #define GPIO_D_IFE_IFE_MASK           0x0FU
  #define GPIO_D_IFE_IFE_BITNUM         0x00U
  #define GPIO_D_IFE                    *((volatile word *)0x0000F1EC)


  /*** GPIO_D_SLEW - GPIO D Slew Rate Control Register; 0x0000F1ED ***/
  union {
    word Word;
  } GPIO_D_SLEW_STR;
  
  #define GPIO_D_SLEW_SLEW0_MASK        0x01U
  #define GPIO_D_SLEW_SLEW1_MASK        0x02U
  #define GPIO_D_SLEW_SLEW2_MASK        0x04U
  #define GPIO_D_SLEW_SLEW3_MASK        0x08U
  #define GPIO_D_SLEW_SLEW_MASK         0x0FU
  #define GPIO_D_SLEW_SLEW_BITNUM       0x00U
  #define GPIO_D_SLEW                   *((volatile word *)0x0000F1ED)


  word Reserved2[18];                  /* Reserved (unused) registers */

} GPIOD_PRPH;

/******************************************
*** Peripheral GPIOE
*******************************************/
typedef volatile struct {
  /*** GPIO_E_PUR - GPIO E Pull-up Enable Register; 0x0000F200 ***/
  union {
    word Word;
  } GPIO_E_PUR_STR;
  
  #define GPIO_E_PUR_PU0_MASK           0x01U
  #define GPIO_E_PUR_PU1_MASK           0x02U
  #define GPIO_E_PUR_PU2_MASK           0x04U
  #define GPIO_E_PUR_PU3_MASK           0x08U
  #define GPIO_E_PUR_PU4_MASK           0x10U
  #define GPIO_E_PUR_PU5_MASK           0x20U
  #define GPIO_E_PUR_PU6_MASK           0x40U
  #define GPIO_E_PUR_PU7_MASK           0x80U
  #define GPIO_E_PUR_PU_MASK            0xFFU
  #define GPIO_E_PUR_PU_BITNUM          0x00U
  #define GPIO_E_PUR                    *((volatile word *)0x0000F200)


  /*** GPIO_E_DR - GPIO E Data Register; 0x0000F201 ***/
  union {
    word Word;
  } GPIO_E_DR_STR;
  
  #define GPIO_E_DR_D0_MASK             0x01U
  #define GPIO_E_DR_D1_MASK             0x02U
  #define GPIO_E_DR_D2_MASK             0x04U
  #define GPIO_E_DR_D3_MASK             0x08U
  #define GPIO_E_DR_D4_MASK             0x10U
  #define GPIO_E_DR_D5_MASK             0x20U
  #define GPIO_E_DR_D6_MASK             0x40U
  #define GPIO_E_DR_D7_MASK             0x80U
  #define GPIO_E_DR_D_MASK              0xFFU
  #define GPIO_E_DR_D_BITNUM            0x00U
  #define GPIO_E_DR                     *((volatile word *)0x0000F201)


  /*** GPIO_E_DDR - GPIO E Data Direction Register; 0x0000F202 ***/
  union {
    word Word;
  } GPIO_E_DDR_STR;
  
  #define GPIO_E_DDR_DD0_MASK           0x01U
  #define GPIO_E_DDR_DD1_MASK           0x02U
  #define GPIO_E_DDR_DD2_MASK           0x04U
  #define GPIO_E_DDR_DD3_MASK           0x08U
  #define GPIO_E_DDR_DD4_MASK           0x10U
  #define GPIO_E_DDR_DD5_MASK           0x20U
  #define GPIO_E_DDR_DD6_MASK           0x40U
  #define GPIO_E_DDR_DD7_MASK           0x80U
  #define GPIO_E_DDR_DD_MASK            0xFFU
  #define GPIO_E_DDR_DD_BITNUM          0x00U
  #define GPIO_E_DDR                    *((volatile word *)0x0000F202)


  /*** GPIO_E_PER - GPIO E Peripheral Enable Registers; 0x0000F203 ***/
  union {
    word Word;
  } GPIO_E_PER_STR;
  
  #define GPIO_E_PER_PE0_MASK           0x01U
  #define GPIO_E_PER_PE1_MASK           0x02U
  #define GPIO_E_PER_PE2_MASK           0x04U
  #define GPIO_E_PER_PE3_MASK           0x08U
  #define GPIO_E_PER_PE4_MASK           0x10U
  #define GPIO_E_PER_PE5_MASK           0x20U
  #define GPIO_E_PER_PE6_MASK           0x40U
  #define GPIO_E_PER_PE7_MASK           0x80U
  #define GPIO_E_PER_PE_MASK            0xFFU
  #define GPIO_E_PER_PE_BITNUM          0x00U
  #define GPIO_E_PER                    *((volatile word *)0x0000F203)


  word Reserved0[1];                   /* Reserved (unused) registers */
  
  /*** GPIO_E_IENR - GPIO E Interrupt Enable Register; 0x0000F205 ***/
  union {
    word Word;
  } GPIO_E_IENR_STR;
  
  #define GPIO_E_IENR_IEN0_MASK         0x01U
  #define GPIO_E_IENR_IEN1_MASK         0x02U
  #define GPIO_E_IENR_IEN2_MASK         0x04U
  #define GPIO_E_IENR_IEN3_MASK         0x08U
  #define GPIO_E_IENR_IEN4_MASK         0x10U
  #define GPIO_E_IENR_IEN5_MASK         0x20U
  #define GPIO_E_IENR_IEN6_MASK         0x40U
  #define GPIO_E_IENR_IEN7_MASK         0x80U
  #define GPIO_E_IENR_IEN_MASK          0xFFU
  #define GPIO_E_IENR_IEN_BITNUM        0x00U
  #define GPIO_E_IENR                   *((volatile word *)0x0000F205)


  /*** GPIO_E_IPOLR - GPIO E Interrupt Polarity Register; 0x0000F206 ***/
  union {
    word Word;
  } GPIO_E_IPOLR_STR;
  
  #define GPIO_E_IPOLR_IPOL0_MASK       0x01U
  #define GPIO_E_IPOLR_IPOL1_MASK       0x02U
  #define GPIO_E_IPOLR_IPOL2_MASK       0x04U
  #define GPIO_E_IPOLR_IPOL3_MASK       0x08U
  #define GPIO_E_IPOLR_IPOL4_MASK       0x10U
  #define GPIO_E_IPOLR_IPOL5_MASK       0x20U
  #define GPIO_E_IPOLR_IPOL6_MASK       0x40U
  #define GPIO_E_IPOLR_IPOL7_MASK       0x80U
  #define GPIO_E_IPOLR_IPOL_MASK        0xFFU
  #define GPIO_E_IPOLR_IPOL_BITNUM      0x00U
  #define GPIO_E_IPOLR                  *((volatile word *)0x0000F206)


  /*** GPIO_E_IPR - GPIO E Interrupt Pending Register; 0x0000F207 ***/
  union {
    word Word;
  } GPIO_E_IPR_STR;
  
  #define GPIO_E_IPR_IP0_MASK           0x01U
  #define GPIO_E_IPR_IP1_MASK           0x02U
  #define GPIO_E_IPR_IP2_MASK           0x04U
  #define GPIO_E_IPR_IP3_MASK           0x08U
  #define GPIO_E_IPR_IP4_MASK           0x10U
  #define GPIO_E_IPR_IP5_MASK           0x20U
  #define GPIO_E_IPR_IP6_MASK           0x40U
  #define GPIO_E_IPR_IP7_MASK           0x80U
  #define GPIO_E_IPR_IP_MASK            0xFFU
  #define GPIO_E_IPR_IP_BITNUM          0x00U
  #define GPIO_E_IPR                    *((volatile word *)0x0000F207)


  /*** GPIO_E_IESR - GPIO E Interrupt Edge Sensitive Register; 0x0000F208 ***/
  union {
    word Word;
  } GPIO_E_IESR_STR;
  
  #define GPIO_E_IESR_IES0_MASK         0x01U
  #define GPIO_E_IESR_IES1_MASK         0x02U
  #define GPIO_E_IESR_IES2_MASK         0x04U
  #define GPIO_E_IESR_IES3_MASK         0x08U
  #define GPIO_E_IESR_IES4_MASK         0x10U
  #define GPIO_E_IESR_IES5_MASK         0x20U
  #define GPIO_E_IESR_IES6_MASK         0x40U
  #define GPIO_E_IESR_IES7_MASK         0x80U
  #define GPIO_E_IESR_IES_MASK          0xFFU
  #define GPIO_E_IESR_IES_BITNUM        0x00U
  #define GPIO_E_IESR                   *((volatile word *)0x0000F208)


  word Reserved1[1];                   /* Reserved (unused) registers */
  
  /*** GPIO_E_RAWDATA - GPIO E Raw Data Register; 0x0000F20A ***/
  union {
    word Word;
  } GPIO_E_RAWDATA_STR;
  
  #define GPIO_E_RAWDATA_RAW_DATA0_MASK 0x01U
  #define GPIO_E_RAWDATA_RAW_DATA1_MASK 0x02U
  #define GPIO_E_RAWDATA_RAW_DATA2_MASK 0x04U
  #define GPIO_E_RAWDATA_RAW_DATA3_MASK 0x08U
  #define GPIO_E_RAWDATA_RAW_DATA4_MASK 0x10U
  #define GPIO_E_RAWDATA_RAW_DATA5_MASK 0x20U
  #define GPIO_E_RAWDATA_RAW_DATA6_MASK 0x40U
  #define GPIO_E_RAWDATA_RAW_DATA7_MASK 0x80U
  #define GPIO_E_RAWDATA_RAW_DATA_MASK  0xFFU
  #define GPIO_E_RAWDATA_RAW_DATA_BITNUM 0x00U
  #define GPIO_E_RAWDATA                *((volatile word *)0x0000F20A)


  /*** GPIO_E_DRIVE - GPIO E Drive Strength Control Register; 0x0000F20B ***/
  union {
    word Word;
  } GPIO_E_DRIVE_STR;
  
  #define GPIO_E_DRIVE_DRIVE0_MASK      0x01U
  #define GPIO_E_DRIVE_DRIVE1_MASK      0x02U
  #define GPIO_E_DRIVE_DRIVE2_MASK      0x04U
  #define GPIO_E_DRIVE_DRIVE3_MASK      0x08U
  #define GPIO_E_DRIVE_DRIVE4_MASK      0x10U
  #define GPIO_E_DRIVE_DRIVE5_MASK      0x20U
  #define GPIO_E_DRIVE_DRIVE6_MASK      0x40U
  #define GPIO_E_DRIVE_DRIVE7_MASK      0x80U
  #define GPIO_E_DRIVE_DRIVE_MASK       0xFFU
  #define GPIO_E_DRIVE_DRIVE_BITNUM     0x00U
  #define GPIO_E_DRIVE                  *((volatile word *)0x0000F20B)


  /*** GPIO_E_IFE - GPIO E Input Filter Control Register; 0x0000F20C ***/
  union {
    word Word;
  } GPIO_E_IFE_STR;
  
  #define GPIO_E_IFE_IFE0_MASK          0x01U
  #define GPIO_E_IFE_IFE1_MASK          0x02U
  #define GPIO_E_IFE_IFE2_MASK          0x04U
  #define GPIO_E_IFE_IFE3_MASK          0x08U
  #define GPIO_E_IFE_IFE4_MASK          0x10U
  #define GPIO_E_IFE_IFE5_MASK          0x20U
  #define GPIO_E_IFE_IFE6_MASK          0x40U
  #define GPIO_E_IFE_IFE7_MASK          0x80U
  #define GPIO_E_IFE_IFE_MASK           0xFFU
  #define GPIO_E_IFE_IFE_BITNUM         0x00U
  #define GPIO_E_IFE                    *((volatile word *)0x0000F20C)


  /*** GPIO_E_SLEW - GPIO E Slew Rate Control Register; 0x0000F20D ***/
  union {
    word Word;
  } GPIO_E_SLEW_STR;
  
  #define GPIO_E_SLEW_SLEW0_MASK        0x01U
  #define GPIO_E_SLEW_SLEW1_MASK        0x02U
  #define GPIO_E_SLEW_SLEW2_MASK        0x04U
  #define GPIO_E_SLEW_SLEW3_MASK        0x08U
  #define GPIO_E_SLEW_SLEW4_MASK        0x10U
  #define GPIO_E_SLEW_SLEW5_MASK        0x20U
  #define GPIO_E_SLEW_SLEW6_MASK        0x40U
  #define GPIO_E_SLEW_SLEW7_MASK        0x80U
  #define GPIO_E_SLEW_SLEW_MASK         0xFFU
  #define GPIO_E_SLEW_SLEW_BITNUM       0x00U
  #define GPIO_E_SLEW                   *((volatile word *)0x0000F20D)


  word Reserved2[18];                  /* Reserved (unused) registers */

} GPIOE_PRPH;

/******************************************
*** Peripheral GPIOF
*******************************************/
typedef volatile struct {
  /*** GPIO_F_PUR - GPIO F Pull-up Enable Register; 0x0000F220 ***/
  union {
    word Word;
  } GPIO_F_PUR_STR;
  
  #define GPIO_F_PUR_PU0_MASK           0x01U
  #define GPIO_F_PUR_PU1_MASK           0x02U
  #define GPIO_F_PUR_PU2_MASK           0x04U
  #define GPIO_F_PUR_PU3_MASK           0x08U
  #define GPIO_F_PUR_PU_MASK            0x0FU
  #define GPIO_F_PUR_PU_BITNUM          0x00U
  #define GPIO_F_PUR                    *((volatile word *)0x0000F220)


  /*** GPIO_F_DR - GPIO F Data Register; 0x0000F221 ***/
  union {
    word Word;
  } GPIO_F_DR_STR;
  
  #define GPIO_F_DR_D0_MASK             0x01U
  #define GPIO_F_DR_D1_MASK             0x02U
  #define GPIO_F_DR_D2_MASK             0x04U
  #define GPIO_F_DR_D3_MASK             0x08U
  #define GPIO_F_DR_D_MASK              0x0FU
  #define GPIO_F_DR_D_BITNUM            0x00U
  #define GPIO_F_DR                     *((volatile word *)0x0000F221)


  /*** GPIO_F_DDR - GPIO F Data Direction Register; 0x0000F222 ***/
  union {
    word Word;
  } GPIO_F_DDR_STR;
  
  #define GPIO_F_DDR_DD0_MASK           0x01U
  #define GPIO_F_DDR_DD1_MASK           0x02U
  #define GPIO_F_DDR_DD2_MASK           0x04U
  #define GPIO_F_DDR_DD3_MASK           0x08U
  #define GPIO_F_DDR_DD_MASK            0x0FU
  #define GPIO_F_DDR_DD_BITNUM          0x00U
  #define GPIO_F_DDR                    *((volatile word *)0x0000F222)


  /*** GPIO_F_PER - GPIO F Peripheral Enable Registers; 0x0000F223 ***/
  union {
    word Word;
  } GPIO_F_PER_STR;
  
  #define GPIO_F_PER_PE0_MASK           0x01U
  #define GPIO_F_PER_PE1_MASK           0x02U
  #define GPIO_F_PER_PE2_MASK           0x04U
  #define GPIO_F_PER_PE3_MASK           0x08U
  #define GPIO_F_PER_PE_MASK            0x0FU
  #define GPIO_F_PER_PE_BITNUM          0x00U
  #define GPIO_F_PER                    *((volatile word *)0x0000F223)


  word Reserved0[1];                   /* Reserved (unused) registers */
  
  /*** GPIO_F_IENR - GPIO F Interrupt Enable Register; 0x0000F225 ***/
  union {
    word Word;
  } GPIO_F_IENR_STR;
  
  #define GPIO_F_IENR_IEN0_MASK         0x01U
  #define GPIO_F_IENR_IEN1_MASK         0x02U
  #define GPIO_F_IENR_IEN2_MASK         0x04U
  #define GPIO_F_IENR_IEN3_MASK         0x08U
  #define GPIO_F_IENR_IEN_MASK          0x0FU
  #define GPIO_F_IENR_IEN_BITNUM        0x00U
  #define GPIO_F_IENR                   *((volatile word *)0x0000F225)


  /*** GPIO_F_IPOLR - GPIO F Interrupt Polarity Register; 0x0000F226 ***/
  union {
    word Word;
  } GPIO_F_IPOLR_STR;
  
  #define GPIO_F_IPOLR_IPOL0_MASK       0x01U
  #define GPIO_F_IPOLR_IPOL1_MASK       0x02U
  #define GPIO_F_IPOLR_IPOL2_MASK       0x04U
  #define GPIO_F_IPOLR_IPOL3_MASK       0x08U
  #define GPIO_F_IPOLR_IPOL_MASK        0x0FU
  #define GPIO_F_IPOLR_IPOL_BITNUM      0x00U
  #define GPIO_F_IPOLR                  *((volatile word *)0x0000F226)


  /*** GPIO_F_IPR - GPIO F Interrupt Pending Register; 0x0000F227 ***/
  union {
    word Word;
  } GPIO_F_IPR_STR;
  
  #define GPIO_F_IPR_IP0_MASK           0x01U
  #define GPIO_F_IPR_IP1_MASK           0x02U
  #define GPIO_F_IPR_IP2_MASK           0x04U
  #define GPIO_F_IPR_IP3_MASK           0x08U
  #define GPIO_F_IPR_IP_MASK            0x0FU
  #define GPIO_F_IPR_IP_BITNUM          0x00U
  #define GPIO_F_IPR                    *((volatile word *)0x0000F227)


  /*** GPIO_F_IESR - GPIO F Interrupt Edge Sensitive Register; 0x0000F228 ***/
  union {
    word Word;
  } GPIO_F_IESR_STR;
  
  #define GPIO_F_IESR_IES0_MASK         0x01U
  #define GPIO_F_IESR_IES1_MASK         0x02U
  #define GPIO_F_IESR_IES2_MASK         0x04U
  #define GPIO_F_IESR_IES3_MASK         0x08U
  #define GPIO_F_IESR_IES_MASK          0x0FU
  #define GPIO_F_IESR_IES_BITNUM        0x00U
  #define GPIO_F_IESR                   *((volatile word *)0x0000F228)


  word Reserved1[1];                   /* Reserved (unused) registers */
  
  /*** GPIO_F_RAWDATA - GPIO F Raw Data Register; 0x0000F22A ***/
  union {
    word Word;
  } GPIO_F_RAWDATA_STR;
  
  #define GPIO_F_RAWDATA_RAW_DATA0_MASK 0x01U
  #define GPIO_F_RAWDATA_RAW_DATA1_MASK 0x02U
  #define GPIO_F_RAWDATA_RAW_DATA2_MASK 0x04U
  #define GPIO_F_RAWDATA_RAW_DATA3_MASK 0x08U
  #define GPIO_F_RAWDATA_RAW_DATA_MASK  0x0FU
  #define GPIO_F_RAWDATA_RAW_DATA_BITNUM 0x00U
  #define GPIO_F_RAWDATA                *((volatile word *)0x0000F22A)


  /*** GPIO_F_DRIVE - GPIO F Drive Strength Control Register; 0x0000F22B ***/
  union {
    word Word;
  } GPIO_F_DRIVE_STR;
  
  #define GPIO_F_DRIVE_DRIVE0_MASK      0x01U
  #define GPIO_F_DRIVE_DRIVE1_MASK      0x02U
  #define GPIO_F_DRIVE_DRIVE2_MASK      0x04U
  #define GPIO_F_DRIVE_DRIVE3_MASK      0x08U
  #define GPIO_F_DRIVE_DRIVE_MASK       0x0FU
  #define GPIO_F_DRIVE_DRIVE_BITNUM     0x00U
  #define GPIO_F_DRIVE                  *((volatile word *)0x0000F22B)


  /*** GPIO_F_IFE - GPIO F Input Filter Control Register; 0x0000F22C ***/
  union {
    word Word;
  } GPIO_F_IFE_STR;
  
  #define GPIO_F_IFE_IFE0_MASK          0x01U
  #define GPIO_F_IFE_IFE1_MASK          0x02U
  #define GPIO_F_IFE_IFE2_MASK          0x04U
  #define GPIO_F_IFE_IFE3_MASK          0x08U
  #define GPIO_F_IFE_IFE_MASK           0x0FU
  #define GPIO_F_IFE_IFE_BITNUM         0x00U
  #define GPIO_F_IFE                    *((volatile word *)0x0000F22C)


  /*** GPIO_F_SLEW - GPIO F Slew Rate Control Register; 0x0000F22D ***/
  union {
    word Word;
  } GPIO_F_SLEW_STR;
  
  #define GPIO_F_SLEW_SLEW0_MASK        0x01U
  #define GPIO_F_SLEW_SLEW1_MASK        0x02U
  #define GPIO_F_SLEW_SLEW2_MASK        0x04U
  #define GPIO_F_SLEW_SLEW3_MASK        0x08U
  #define GPIO_F_SLEW_SLEW_MASK         0x0FU
  #define GPIO_F_SLEW_SLEW_BITNUM       0x00U
  #define GPIO_F_SLEW                   *((volatile word *)0x0000F22D)


  word Reserved2[18];                  /* Reserved (unused) registers */

} GPIOF_PRPH;

/******************************************
*** Peripheral SIM
*******************************************/
typedef volatile struct {
  /*** SIM_CTRL - SIM Control Register; 0x0000F240 ***/
  union {
    word Word;
  } SIM_CTRL_STR;
  
  #define SIM_CTRL_WAIT_DISABLE0_MASK   0x01U
  #define SIM_CTRL_WAIT_DISABLE1_MASK   0x02U
  #define SIM_CTRL_STOP_DISABLE0_MASK   0x04U
  #define SIM_CTRL_STOP_DISABLE1_MASK   0x08U
  #define SIM_CTRL_SWRST_MASK           0x10U
  #define SIM_CTRL_ONCEEBL_MASK         0x20U
  #define SIM_CTRL_WAIT_DISABLE_MASK    0x03U
  #define SIM_CTRL_WAIT_DISABLE_BITNUM  0x00U
  #define SIM_CTRL_STOP_DISABLE_MASK    0x0CU
  #define SIM_CTRL_STOP_DISABLE_BITNUM  0x02U
  #define SIM_CTRL                      *((volatile word *)0x0000F240)


  /*** SIM_RSTAT - SIM Reset Status Register; 0x0000F241 ***/
  union {
    word Word;
  } SIM_RSTAT_STR;
  
  #define SIM_RSTAT_POR_MASK            0x01U
  #define SIM_RSTAT_PPD_MASK            0x02U
  #define SIM_RSTAT_LVDR_MASK           0x04U
  #define SIM_RSTAT_EXTR_MASK           0x08U
  #define SIM_RSTAT_COP_LOR_MASK        0x10U
  #define SIM_RSTAT_COP_CPU_MASK        0x20U
  #define SIM_RSTAT_SWR_MASK            0x40U
  #define SIM_RSTAT                     *((volatile word *)0x0000F241)


  /*** SIM_MSHID - SIM Most Significant Half JTAG ID; 0x0000F242 ***/
  union {
    word Word;
  } SIM_MSHID_STR;
  
  #define SIM_MSHID_SIM_MSH_ID0_MASK    0x01U
  #define SIM_MSHID_SIM_MSH_ID1_MASK    0x02U
  #define SIM_MSHID_SIM_MSH_ID2_MASK    0x04U
  #define SIM_MSHID_SIM_MSH_ID3_MASK    0x08U
  #define SIM_MSHID_SIM_MSH_ID4_MASK    0x10U
  #define SIM_MSHID_SIM_MSH_ID5_MASK    0x20U
  #define SIM_MSHID_SIM_MSH_ID6_MASK    0x40U
  #define SIM_MSHID_SIM_MSH_ID7_MASK    0x80U
  #define SIM_MSHID_SIM_MSH_ID8_MASK    0x0100U
  #define SIM_MSHID_SIM_MSH_ID9_MASK    0x0200U
  #define SIM_MSHID_SIM_MSH_ID10_MASK   0x0400U
  #define SIM_MSHID_SIM_MSH_ID11_MASK   0x0800U
  #define SIM_MSHID_SIM_MSH_ID12_MASK   0x1000U
  #define SIM_MSHID_SIM_MSH_ID13_MASK   0x2000U
  #define SIM_MSHID_SIM_MSH_ID14_MASK   0x4000U
  #define SIM_MSHID_SIM_MSH_ID15_MASK   0x8000U
  #define SIM_MSHID                     *((volatile word *)0x0000F242)


  /*** SIM_LSHID - SIM Least Significant Half JTAG ID; 0x0000F243 ***/
  union {
    word Word;
  } SIM_LSHID_STR;
  
  #define SIM_LSHID_SIM_LSH_ID0_MASK    0x01U
  #define SIM_LSHID_SIM_LSH_ID1_MASK    0x02U
  #define SIM_LSHID_SIM_LSH_ID2_MASK    0x04U
  #define SIM_LSHID_SIM_LSH_ID3_MASK    0x08U
  #define SIM_LSHID_SIM_LSH_ID4_MASK    0x10U
  #define SIM_LSHID_SIM_LSH_ID5_MASK    0x20U
  #define SIM_LSHID_SIM_LSH_ID6_MASK    0x40U
  #define SIM_LSHID_SIM_LSH_ID7_MASK    0x80U
  #define SIM_LSHID_SIM_LSH_ID8_MASK    0x0100U
  #define SIM_LSHID_SIM_LSH_ID9_MASK    0x0200U
  #define SIM_LSHID_SIM_LSH_ID10_MASK   0x0400U
  #define SIM_LSHID_SIM_LSH_ID11_MASK   0x0800U
  #define SIM_LSHID_SIM_LSH_ID12_MASK   0x1000U
  #define SIM_LSHID_SIM_LSH_ID13_MASK   0x2000U
  #define SIM_LSHID_SIM_LSH_ID14_MASK   0x4000U
  #define SIM_LSHID_SIM_LSH_ID15_MASK   0x8000U
  #define SIM_LSHID                     *((volatile word *)0x0000F243)


  word Reserved0[1];                   /* Reserved (unused) registers */
  
  /*** SIM_CLKOUT - SIM Clock Output Select Register; 0x0000F245 ***/
  union {
    word Word;
  } SIM_CLKOUT_STR;
  
  #define SIM_CLKOUT_CLKOSEL00_MASK     0x01U
  #define SIM_CLKOUT_CLKOSEL01_MASK     0x02U
  #define SIM_CLKOUT_CLKOSEL02_MASK     0x04U
  #define SIM_CLKOUT_CLKOSEL03_MASK     0x08U
  #define SIM_CLKOUT_CLKOSEL04_MASK     0x10U
  #define SIM_CLKOUT_CLKDIS0_MASK       0x20U
  #define SIM_CLKOUT_CLKOSEL10_MASK     0x0100U
  #define SIM_CLKOUT_CLKOSEL11_MASK     0x0200U
  #define SIM_CLKOUT_CLKOSEL12_MASK     0x0400U
  #define SIM_CLKOUT_CLKDIS1_MASK       0x2000U
  #define SIM_CLKOUT_CLKOSEL0_MASK      0x1FU
  #define SIM_CLKOUT_CLKOSEL0_BITNUM    0x00U
  #define SIM_CLKOUT_CLKOSEL1_MASK      0x0700U
  #define SIM_CLKOUT_CLKOSEL1_BITNUM    0x08U
  #define SIM_CLKOUT                    *((volatile word *)0x0000F245)


  /*** SIM_PCR - SIM Peripheral Clock Rate Register; 0x0000F246 ***/
  union {
    word Word;
  } SIM_PCR_STR;
  
  #define SIM_PCR_SCI_CR_MASK           0x1000U
  #define SIM_PCR_PWM_CR_MASK           0x2000U
  #define SIM_PCR_TMR_CR_MASK           0x8000U
  #define SIM_PCR                       *((volatile word *)0x0000F246)


  /*** SIM_PCE - SIM Peripheral Clock Enable Register; 0x0000F247 ***/
  union {
    word Word;
  } SIM_PCE_STR;
  
  #define SIM_PCE_TA0_MASK              0x01U
  #define SIM_PCE_TA1_MASK              0x02U
  #define SIM_PCE_PIT_MASK              0x04U
  #define SIM_PCE_PDB_MASK              0x08U
  #define SIM_PCE_COP_MASK              0x10U
  #define SIM_PCE_PWM_MASK              0x20U
  #define SIM_PCE_SPI_MASK              0x40U
  #define SIM_PCE_SCI_MASK              0x80U
  #define SIM_PCE_I2C_MASK              0x0100U
  #define SIM_PCE_PGA0_MASK             0x0200U
  #define SIM_PCE_PGA1_MASK             0x0400U
  #define SIM_PCE_ADC0_MASK             0x0800U
  #define SIM_PCE_ADC1_MASK             0x1000U
  #define SIM_PCE_CMP0_MASK             0x2000U
  #define SIM_PCE_CMP1_MASK             0x4000U
  #define SIM_PCE_CMP2_MASK             0x8000U
  #define SIM_PCE_TA_MASK               0x03U
  #define SIM_PCE_TA_BITNUM             0x00U
  #define SIM_PCE_PGA_MASK              0x0600U
  #define SIM_PCE_PGA_BITNUM            0x09U
  #define SIM_PCE_ADC_MASK              0x1800U
  #define SIM_PCE_ADC_BITNUM            0x0BU
  #define SIM_PCE_CMP_MASK              0xE000U
  #define SIM_PCE_CMP_BITNUM            0x0DU
  #define SIM_PCE                       *((volatile word *)0x0000F247)


  /*** SIM_SDR - SIM STOP Disable Register; 0x0000F248 ***/
  union {
    word Word;
  } SIM_SDR_STR;
  
  #define SIM_SDR_TA0_MASK              0x01U
  #define SIM_SDR_TA1_MASK              0x02U
  #define SIM_SDR_PIT_MASK              0x04U
  #define SIM_SDR_PDB_MASK              0x08U
  #define SIM_SDR_COP_MASK              0x10U
  #define SIM_SDR_PWM_MASK              0x20U
  #define SIM_SDR_SPI_MASK              0x40U
  #define SIM_SDR_SCI_MASK              0x80U
  #define SIM_SDR_I2C_MASK              0x0100U
  #define SIM_SDR_PGA0_MASK             0x0200U
  #define SIM_SDR_PGA1_MASK             0x0400U
  #define SIM_SDR_ADC0_MASK             0x0800U
  #define SIM_SDR_ADC1_MASK             0x1000U
  #define SIM_SDR_CMP0_MASK             0x2000U
  #define SIM_SDR_CMP1_MASK             0x4000U
  #define SIM_SDR_CMP2_MASK             0x8000U
  #define SIM_SDR_TA_MASK               0x03U
  #define SIM_SDR_TA_BITNUM             0x00U
  #define SIM_SDR_PGA_MASK              0x0600U
  #define SIM_SDR_PGA_BITNUM            0x09U
  #define SIM_SDR_ADC_MASK              0x1800U
  #define SIM_SDR_ADC_BITNUM            0x0BU
  #define SIM_SDR_CMP_MASK              0xE000U
  #define SIM_SDR_CMP_BITNUM            0x0DU
  #define SIM_SDR                       *((volatile word *)0x0000F248)


  /*** SIM_ISAL - SIM I/O Short Address Location register; 0x0000F249 ***/
  union {
    word Word;
  } SIM_ISAL_STR;
  
  #define SIM_ISAL_ADDR_15_60_MASK      0x40U
  #define SIM_ISAL_ADDR_15_61_MASK      0x80U
  #define SIM_ISAL_ADDR_15_62_MASK      0x0100U
  #define SIM_ISAL_ADDR_15_63_MASK      0x0200U
  #define SIM_ISAL_ADDR_15_64_MASK      0x0400U
  #define SIM_ISAL_ADDR_15_65_MASK      0x0800U
  #define SIM_ISAL_ADDR_15_66_MASK      0x1000U
  #define SIM_ISAL_ADDR_15_67_MASK      0x2000U
  #define SIM_ISAL_ADDR_15_68_MASK      0x4000U
  #define SIM_ISAL_ADDR_15_69_MASK      0x8000U
  #define SIM_ISAL_ADDR_15_6_MASK       0xFFC0U
  #define SIM_ISAL_ADDR_15_6_BITNUM     0x06U
  #define SIM_ISAL                      *((volatile word *)0x0000F249)


  /*** SIM_PROT - SIM Protection Register; 0x0000F24A ***/
  union {
    word Word;
  } SIM_PROT_STR;
  
  #define SIM_PROT_GIPSP0_MASK          0x01U
  #define SIM_PROT_GIPSP1_MASK          0x02U
  #define SIM_PROT_PCEP0_MASK           0x04U
  #define SIM_PROT_PCEP1_MASK           0x08U
  #define SIM_PROT_GIPSP_MASK           0x03U
  #define SIM_PROT_GIPSP_BITNUM         0x00U
  #define SIM_PROT_PCEP_MASK            0x0CU
  #define SIM_PROT_PCEP_BITNUM          0x02U
  #define SIM_PROT                      *((volatile word *)0x0000F24A)


  /*** SIM_GPSA - SIM GPIO Peripheral Select Register for GPIOA; 0x0000F24B ***/
  union {
    word Word;
  } SIM_GPSA_STR;
  
  #define SIM_GPSA_GPS_A30_MASK         0x01U
  #define SIM_GPSA_GPS_A31_MASK         0x02U
  #define SIM_GPSA_GPS_A40_MASK         0x04U
  #define SIM_GPSA_GPS_A41_MASK         0x08U
  #define SIM_GPSA_GPS_A50_MASK         0x10U
  #define SIM_GPSA_GPS_A51_MASK         0x20U
  #define SIM_GPSA_GPS_A60_MASK         0x40U
  #define SIM_GPSA_GPS_A61_MASK         0x80U
  #define SIM_GPSA_GPS_A62_MASK         0x0100U
  #define SIM_GPSA_GPS_A3_MASK          0x03U
  #define SIM_GPSA_GPS_A3_BITNUM        0x00U
  #define SIM_GPSA_GPS_A4_MASK          0x0CU
  #define SIM_GPSA_GPS_A4_BITNUM        0x02U
  #define SIM_GPSA_GPS_A5_MASK          0x30U
  #define SIM_GPSA_GPS_A5_BITNUM        0x04U
  #define SIM_GPSA_GPS_A6_MASK          0x01C0U
  #define SIM_GPSA_GPS_A6_BITNUM        0x06U
  #define SIM_GPSA                      *((volatile word *)0x0000F24B)


  /*** SIM_GPSB0 - SIM GPIO Peripheral Select Register 0 for GPIOB; 0x0000F24C ***/
  union {
    word Word;
  } SIM_GPSB0_STR;
  
  #define SIM_GPSB0_GPS_B00_MASK        0x01U
  #define SIM_GPSB0_GPS_B01_MASK        0x02U
  #define SIM_GPSB0_GPS_B02_MASK        0x04U
  #define SIM_GPSB0_GPS_B10_MASK        0x08U
  #define SIM_GPSB0_GPS_B11_MASK        0x10U
  #define SIM_GPSB0_GPS_B20_MASK        0x40U
  #define SIM_GPSB0_GPS_B21_MASK        0x80U
  #define SIM_GPSB0_GPS_B30_MASK        0x0100U
  #define SIM_GPSB0_GPS_B31_MASK        0x0200U
  #define SIM_GPSB0_GPS_B32_MASK        0x0400U
  #define SIM_GPSB0_GPS_B40_MASK        0x0800U
  #define SIM_GPSB0_GPS_B41_MASK        0x1000U
  #define SIM_GPSB0_GPS_B42_MASK        0x2000U
  #define SIM_GPSB0_GPS_B50_MASK        0x4000U
  #define SIM_GPSB0_GPS_B51_MASK        0x8000U
  #define SIM_GPSB0_GPS_B0_MASK         0x07U
  #define SIM_GPSB0_GPS_B0_BITNUM       0x00U
  #define SIM_GPSB0_GPS_B1_MASK         0x18U
  #define SIM_GPSB0_GPS_B1_BITNUM       0x03U
  #define SIM_GPSB0_GPS_B2_MASK         0xC0U
  #define SIM_GPSB0_GPS_B2_BITNUM       0x06U
  #define SIM_GPSB0_GPS_B3_MASK         0x0700U
  #define SIM_GPSB0_GPS_B3_BITNUM       0x08U
  #define SIM_GPSB0_GPS_B4_MASK         0x3800U
  #define SIM_GPSB0_GPS_B4_BITNUM       0x0BU
  #define SIM_GPSB0_GPS_B5_MASK         0xC000U
  #define SIM_GPSB0_GPS_B5_BITNUM       0x0EU
  #define SIM_GPSB0                     *((volatile word *)0x0000F24C)


  /*** SIM_GPSB1 - SIM GPIO Peripheral Select Register 1 for GPIOB; 0x0000F24D ***/
  union {
    word Word;
  } SIM_GPSB1_STR;
  
  #define SIM_GPSB1_GPS_B60_MASK        0x01U
  #define SIM_GPSB1_GPS_B61_MASK        0x02U
  #define SIM_GPSB1_GPS_B70_MASK        0x04U
  #define SIM_GPSB1_GPS_B71_MASK        0x08U
  #define SIM_GPSB1_GPS_B6_MASK         0x03U
  #define SIM_GPSB1_GPS_B6_BITNUM       0x00U
  #define SIM_GPSB1_GPS_B7_MASK         0x0CU
  #define SIM_GPSB1_GPS_B7_BITNUM       0x02U
  #define SIM_GPSB1                     *((volatile word *)0x0000F24D)


  /*** SIM_GPSC - SIM GPIO Peripheral Select Register for GPIOC; 0x0000F24E ***/
  union {
    word Word;
  } SIM_GPSC_STR;
  
  #define SIM_GPSC_GPS_C0_MASK          0x01U
  #define SIM_GPSC_GPS_C6_MASK          0x02U
  #define SIM_GPSC                      *((volatile word *)0x0000F24E)


  /*** SIM_GPSD - SIM GPIO Peripheral Select Register for GPIOD; 0x0000F24F ***/
  union {
    word Word;
  } SIM_GPSD_STR;
  
  #define SIM_GPSD_GPS_D00_MASK         0x01U
  #define SIM_GPSD_GPS_D01_MASK         0x02U
  #define SIM_GPSD_GPS_D02_MASK         0x04U
  #define SIM_GPSD_GPS_D10_MASK         0x08U
  #define SIM_GPSD_GPS_D11_MASK         0x10U
  #define SIM_GPSD_GPS_D20_MASK         0x20U
  #define SIM_GPSD_GPS_D21_MASK         0x40U
  #define SIM_GPSD_GPS_D30_MASK         0x80U
  #define SIM_GPSD_GPS_D31_MASK         0x0100U
  #define SIM_GPSD_GPS_D0_MASK          0x07U
  #define SIM_GPSD_GPS_D0_BITNUM        0x00U
  #define SIM_GPSD_GPS_D1_MASK          0x18U
  #define SIM_GPSD_GPS_D1_BITNUM        0x03U
  #define SIM_GPSD_GPS_D2_MASK          0x60U
  #define SIM_GPSD_GPS_D2_BITNUM        0x05U
  #define SIM_GPSD_GPS_D3_MASK          0x0180U
  #define SIM_GPSD_GPS_D3_BITNUM        0x07U
  #define SIM_GPSD                      *((volatile word *)0x0000F24F)


  /*** SIM_IPS0 - SIM Internal Peripheral Select Register 0; 0x0000F250 ***/
  union {
    word Word;
  } SIM_IPS0_STR;
  
  #define SIM_IPS0_IPS_PSRC00_MASK      0x01U
  #define SIM_IPS0_IPS_PSRC01_MASK      0x02U
  #define SIM_IPS0_IPS_PSRC02_MASK      0x04U
  #define SIM_IPS0_IPS_PSRC10_MASK      0x08U
  #define SIM_IPS0_IPS_PSRC11_MASK      0x10U
  #define SIM_IPS0_IPS_PSRC12_MASK      0x20U
  #define SIM_IPS0_IPS_PSRC20_MASK      0x40U
  #define SIM_IPS0_IPS_PSRC21_MASK      0x80U
  #define SIM_IPS0_IPS_PSRC22_MASK      0x0100U
  #define SIM_IPS0_IPS_FAULT1_MASK      0x0200U
  #define SIM_IPS0_IPS_FAULT2_MASK      0x0400U
  #define SIM_IPS0_IPS_FAULT3_MASK      0x0800U
  #define SIM_IPS0_IPS_PSRC0_MASK       0x07U
  #define SIM_IPS0_IPS_PSRC0_BITNUM     0x00U
  #define SIM_IPS0_IPS_PSRC1_MASK       0x38U
  #define SIM_IPS0_IPS_PSRC1_BITNUM     0x03U
  #define SIM_IPS0_IPS_PSRC2_MASK       0x01C0U
  #define SIM_IPS0_IPS_PSRC2_BITNUM     0x06U
  #define SIM_IPS0_IPS_FAULT_1_MASK     0x0E00U
  #define SIM_IPS0_IPS_FAULT_1_BITNUM   0x09U
  #define SIM_IPS0                      *((volatile word *)0x0000F250)


  /*** SIM_IPS1 - SIM Internal Peripheral Select Register 1; 0x0000F251 ***/
  union {
    word Word;
  } SIM_IPS1_STR;
  
  #define SIM_IPS1_IPS_T00_MASK         0x01U
  #define SIM_IPS1_IPS_T01_MASK         0x02U
  #define SIM_IPS1_IPS_T02_MASK         0x04U
  #define SIM_IPS1_IPS_T10_MASK         0x08U
  #define SIM_IPS1_IPS_T11_MASK         0x10U
  #define SIM_IPS1_IPS_T12_MASK         0x20U
  #define SIM_IPS1_IPS_C0_WS0_MASK      0x40U
  #define SIM_IPS1_IPS_C0_WS1_MASK      0x80U
  #define SIM_IPS1_IPS_C0_WS2_MASK      0x0100U
  #define SIM_IPS1_IPS_C1_WS0_MASK      0x0200U
  #define SIM_IPS1_IPS_C1_WS1_MASK      0x0400U
  #define SIM_IPS1_IPS_C1_WS2_MASK      0x0800U
  #define SIM_IPS1_IPS_C2_WS0_MASK      0x1000U
  #define SIM_IPS1_IPS_C2_WS1_MASK      0x2000U
  #define SIM_IPS1_IPS_C2_WS2_MASK      0x4000U
  #define SIM_IPS1_IPS_T0_MASK          0x07U
  #define SIM_IPS1_IPS_T0_BITNUM        0x00U
  #define SIM_IPS1_IPS_T1_MASK          0x38U
  #define SIM_IPS1_IPS_T1_BITNUM        0x03U
  #define SIM_IPS1_IPS_C0_WS_MASK       0x01C0U
  #define SIM_IPS1_IPS_C0_WS_BITNUM     0x06U
  #define SIM_IPS1_IPS_C1_WS_MASK       0x0E00U
  #define SIM_IPS1_IPS_C1_WS_BITNUM     0x09U
  #define SIM_IPS1_IPS_C2_WS_MASK       0x7000U
  #define SIM_IPS1_IPS_C2_WS_BITNUM     0x0CU
  #define SIM_IPS1                      *((volatile word *)0x0000F251)


  word Reserved1[14];                  /* Reserved (unused) registers */

} SIM_PRPH;

/******************************************
*** Peripheral PMC
*******************************************/
typedef volatile struct {
  /*** PMC_SCR - PMC Status and Control Register; 0x0000F260 ***/
  union {
    word Word;
  } PMC_SCR_STR;
  
  #define PMC_SCR_PROT0_MASK            0x01U
  #define PMC_SCR_PROT1_MASK            0x02U
  #define PMC_SCR_LVLS_MASK             0x04U
  #define PMC_SCR_LVDE_MASK             0x08U
  #define PMC_SCR_BGBE_MASK             0x10U
  #define PMC_SCR_LPWUI_MASK            0x20U
  #define PMC_SCR_LPRS_MASK             0x40U
  #define PMC_SCR_LPR_MASK              0x80U
  #define PMC_SCR_PPDE_MASK             0x0100U
  #define PMC_SCR_LVDRE_MASK            0x0200U
  #define PMC_SCR_LVDIE_MASK            0x0400U
  #define PMC_SCR_OORIE_MASK            0x0800U
  #define PMC_SCR_PORF_MASK             0x1000U
  #define PMC_SCR_PPDF_MASK             0x2000U
  #define PMC_SCR_LVDF_MASK             0x4000U
  #define PMC_SCR_OORF_MASK             0x8000U
  #define PMC_SCR_PROT_MASK             0x03U
  #define PMC_SCR_PROT_BITNUM           0x00U
  #define PMC_SCR                       *((volatile word *)0x0000F260)


  /*** PMC_CR2 - PMC Control Register 2; 0x0000F261 ***/
  union {
    word Word;
  } PMC_CR2_STR;
  
  #define PMC_CR2_TRIM0_MASK            0x01U
  #define PMC_CR2_TRIM1_MASK            0x02U
  #define PMC_CR2_TRIM2_MASK            0x04U
  #define PMC_CR2_TRIM3_MASK            0x08U
  #define PMC_CR2_TRIM4_MASK            0x10U
  #define PMC_CR2_LPO_TRIM0_MASK        0x20U
  #define PMC_CR2_LPO_TRIM1_MASK        0x40U
  #define PMC_CR2_LPO_TRIM2_MASK        0x80U
  #define PMC_CR2_LPO_EN_MASK           0x0100U
  #define PMC_CR2_TRIM_MASK             0x1FU
  #define PMC_CR2_TRIM_BITNUM           0x00U
  #define PMC_CR2_LPO_TRIM_MASK         0xE0U
  #define PMC_CR2_LPO_TRIM_BITNUM       0x05U
  #define PMC_CR2                       *((volatile word *)0x0000F261)


  word Reserved0[30];                  /* Reserved (unused) registers */

} PMC_PRPH;

/******************************************
*** Peripheral HSCMP0
*******************************************/
typedef volatile struct {
  /*** CMP0_CR0 - CMP0 Control Register 0; 0x0000F280 ***/
  union {
    word Word;
  } CMP0_CR0_STR;
  
  #define CMP0_CR0_MMC0_MASK            0x01U
  #define CMP0_CR0_MMC1_MASK            0x02U
  #define CMP0_CR0_PMC0_MASK            0x04U
  #define CMP0_CR0_PMC1_MASK            0x08U
  #define CMP0_CR0_FILTER_CNT0_MASK     0x10U
  #define CMP0_CR0_FILTER_CNT1_MASK     0x20U
  #define CMP0_CR0_FILTER_CNT2_MASK     0x40U
  #define CMP0_CR0_MMC_MASK             0x03U
  #define CMP0_CR0_MMC_BITNUM           0x00U
  #define CMP0_CR0_PMC_MASK             0x0CU
  #define CMP0_CR0_PMC_BITNUM           0x02U
  #define CMP0_CR0_FILTER_CNT_MASK      0x70U
  #define CMP0_CR0_FILTER_CNT_BITNUM    0x04U
  #define CMP0_CR0                      *((volatile word *)0x0000F280)


  /*** CMP0_CR1 - CMP0 Control Register 1; 0x0000F281 ***/
  union {
    word Word;
  } CMP0_CR1_STR;
  
  #define CMP0_CR1_EN_MASK              0x01U
  #define CMP0_CR1_OPE_MASK             0x02U
  #define CMP0_CR1_COS_MASK             0x04U
  #define CMP0_CR1_INV_MASK             0x08U
  #define CMP0_CR1_PMODE_MASK           0x10U
  #define CMP0_CR1_WE_MASK              0x40U
  #define CMP0_CR1_SE_MASK              0x80U
  #define CMP0_CR1                      *((volatile word *)0x0000F281)


  /*** CMP0_FPR - CMP0 Filter Period Register; 0x0000F282 ***/
  union {
    word Word;
  } CMP0_FPR_STR;
  
  #define CMP0_FPR_FILT_PER0_MASK       0x01U
  #define CMP0_FPR_FILT_PER1_MASK       0x02U
  #define CMP0_FPR_FILT_PER2_MASK       0x04U
  #define CMP0_FPR_FILT_PER3_MASK       0x08U
  #define CMP0_FPR_FILT_PER4_MASK       0x10U
  #define CMP0_FPR_FILT_PER5_MASK       0x20U
  #define CMP0_FPR_FILT_PER6_MASK       0x40U
  #define CMP0_FPR_FILT_PER7_MASK       0x80U
  #define CMP0_FPR_FILT_PER_MASK        0xFFU
  #define CMP0_FPR_FILT_PER_BITNUM      0x00U
  #define CMP0_FPR                      *((volatile word *)0x0000F282)


  /*** CMP0_SCR - CMP0 Status & Control Register; 0x0000F283 ***/
  union {
    word Word;
  } CMP0_SCR_STR;
  
  #define CMP0_SCR_COUT_MASK            0x01U
  #define CMP0_SCR_CFF_MASK             0x02U
  #define CMP0_SCR_CFR_MASK             0x04U
  #define CMP0_SCR_IEF_MASK             0x08U
  #define CMP0_SCR_IER_MASK             0x10U
  #define CMP0_SCR                      *((volatile word *)0x0000F283)


  word Reserved0[28];                  /* Reserved (unused) registers */

} HSCMP0_PRPH;

/******************************************
*** Peripheral HSCMP1
*******************************************/
typedef volatile struct {
  /*** CMP1_CR0 - CMP1 Control Register 0; 0x0000F2A0 ***/
  union {
    word Word;
  } CMP1_CR0_STR;
  
  #define CMP1_CR0_MMC0_MASK            0x01U
  #define CMP1_CR0_MMC1_MASK            0x02U
  #define CMP1_CR0_PMC0_MASK            0x04U
  #define CMP1_CR0_PMC1_MASK            0x08U
  #define CMP1_CR0_FILTER_CNT0_MASK     0x10U
  #define CMP1_CR0_FILTER_CNT1_MASK     0x20U
  #define CMP1_CR0_FILTER_CNT2_MASK     0x40U
  #define CMP1_CR0_MMC_MASK             0x03U
  #define CMP1_CR0_MMC_BITNUM           0x00U
  #define CMP1_CR0_PMC_MASK             0x0CU
  #define CMP1_CR0_PMC_BITNUM           0x02U
  #define CMP1_CR0_FILTER_CNT_MASK      0x70U
  #define CMP1_CR0_FILTER_CNT_BITNUM    0x04U
  #define CMP1_CR0                      *((volatile word *)0x0000F2A0)


  /*** CMP1_CR1 - CMP1 Control Register 1; 0x0000F2A1 ***/
  union {
    word Word;
  } CMP1_CR1_STR;
  
  #define CMP1_CR1_EN_MASK              0x01U
  #define CMP1_CR1_OPE_MASK             0x02U
  #define CMP1_CR1_COS_MASK             0x04U
  #define CMP1_CR1_INV_MASK             0x08U
  #define CMP1_CR1_PMODE_MASK           0x10U
  #define CMP1_CR1_WE_MASK              0x40U
  #define CMP1_CR1_SE_MASK              0x80U
  #define CMP1_CR1                      *((volatile word *)0x0000F2A1)


  /*** CMP1_FPR - CMP1 Filter Period Register; 0x0000F2A2 ***/
  union {
    word Word;
  } CMP1_FPR_STR;
  
  #define CMP1_FPR_FILT_PER0_MASK       0x01U
  #define CMP1_FPR_FILT_PER1_MASK       0x02U
  #define CMP1_FPR_FILT_PER2_MASK       0x04U
  #define CMP1_FPR_FILT_PER3_MASK       0x08U
  #define CMP1_FPR_FILT_PER4_MASK       0x10U
  #define CMP1_FPR_FILT_PER5_MASK       0x20U
  #define CMP1_FPR_FILT_PER6_MASK       0x40U
  #define CMP1_FPR_FILT_PER7_MASK       0x80U
  #define CMP1_FPR_FILT_PER_MASK        0xFFU
  #define CMP1_FPR_FILT_PER_BITNUM      0x00U
  #define CMP1_FPR                      *((volatile word *)0x0000F2A2)


  /*** CMP1_SCR - CMP1 Status & Control Register; 0x0000F2A3 ***/
  union {
    word Word;
  } CMP1_SCR_STR;
  
  #define CMP1_SCR_COUT_MASK            0x01U
  #define CMP1_SCR_CFF_MASK             0x02U
  #define CMP1_SCR_CFR_MASK             0x04U
  #define CMP1_SCR_IEF_MASK             0x08U
  #define CMP1_SCR_IER_MASK             0x10U
  #define CMP1_SCR                      *((volatile word *)0x0000F2A3)


  word Reserved0[28];                  /* Reserved (unused) registers */

} HSCMP1_PRPH;

/******************************************
*** Peripheral HSCMP2
*******************************************/
typedef volatile struct {
  /*** CMP2_CR0 - CMP2 Control Register 0; 0x0000F2C0 ***/
  union {
    word Word;
  } CMP2_CR0_STR;
  
  #define CMP2_CR0_MMC0_MASK            0x01U
  #define CMP2_CR0_MMC1_MASK            0x02U
  #define CMP2_CR0_PMC0_MASK            0x04U
  #define CMP2_CR0_PMC1_MASK            0x08U
  #define CMP2_CR0_FILTER_CNT0_MASK     0x10U
  #define CMP2_CR0_FILTER_CNT1_MASK     0x20U
  #define CMP2_CR0_FILTER_CNT2_MASK     0x40U
  #define CMP2_CR0_MMC_MASK             0x03U
  #define CMP2_CR0_MMC_BITNUM           0x00U
  #define CMP2_CR0_PMC_MASK             0x0CU
  #define CMP2_CR0_PMC_BITNUM           0x02U
  #define CMP2_CR0_FILTER_CNT_MASK      0x70U
  #define CMP2_CR0_FILTER_CNT_BITNUM    0x04U
  #define CMP2_CR0                      *((volatile word *)0x0000F2C0)


  /*** CMP2_CR1 - CMP2 Control Register 1; 0x0000F2C1 ***/
  union {
    word Word;
  } CMP2_CR1_STR;
  
  #define CMP2_CR1_EN_MASK              0x01U
  #define CMP2_CR1_OPE_MASK             0x02U
  #define CMP2_CR1_COS_MASK             0x04U
  #define CMP2_CR1_INV_MASK             0x08U
  #define CMP2_CR1_PMODE_MASK           0x10U
  #define CMP2_CR1_WE_MASK              0x40U
  #define CMP2_CR1_SE_MASK              0x80U
  #define CMP2_CR1                      *((volatile word *)0x0000F2C1)


  /*** CMP2_FPR - CMP2 Filter Period Register; 0x0000F2C2 ***/
  union {
    word Word;
  } CMP2_FPR_STR;
  
  #define CMP2_FPR_FILT_PER0_MASK       0x01U
  #define CMP2_FPR_FILT_PER1_MASK       0x02U
  #define CMP2_FPR_FILT_PER2_MASK       0x04U
  #define CMP2_FPR_FILT_PER3_MASK       0x08U
  #define CMP2_FPR_FILT_PER4_MASK       0x10U
  #define CMP2_FPR_FILT_PER5_MASK       0x20U
  #define CMP2_FPR_FILT_PER6_MASK       0x40U
  #define CMP2_FPR_FILT_PER7_MASK       0x80U
  #define CMP2_FPR_FILT_PER_MASK        0xFFU
  #define CMP2_FPR_FILT_PER_BITNUM      0x00U
  #define CMP2_FPR                      *((volatile word *)0x0000F2C2)


  /*** CMP2_SCR - CMP2 Status & Control Register; 0x0000F2C3 ***/
  union {
    word Word;
  } CMP2_SCR_STR;
  
  #define CMP2_SCR_COUT_MASK            0x01U
  #define CMP2_SCR_CFF_MASK             0x02U
  #define CMP2_SCR_CFR_MASK             0x04U
  #define CMP2_SCR_IEF_MASK             0x08U
  #define CMP2_SCR_IER_MASK             0x10U
  #define CMP2_SCR                      *((volatile word *)0x0000F2C3)


  word Reserved0[28];                  /* Reserved (unused) registers */

} HSCMP2_PRPH;

/******************************************
*** Peripheral PIT
*******************************************/
typedef volatile struct {
  /*** PIT_CTRL - PIT 0 Control Register; 0x0000F2E0 ***/
  union {
    word Word;
  } PIT_CTRL_STR;
  
  #define PIT_CTRL_CNT_EN_MASK          0x01U
  #define PIT_CTRL_PRIE_MASK            0x02U
  #define PIT_CTRL_PRF_MASK             0x04U
  #define PIT_CTRL_PRESCALER0_MASK      0x08U
  #define PIT_CTRL_PRESCALER1_MASK      0x10U
  #define PIT_CTRL_PRESCALER2_MASK      0x20U
  #define PIT_CTRL_PRESCALER3_MASK      0x40U
  #define PIT_CTRL_PRESCALER_MASK       0x78U
  #define PIT_CTRL_PRESCALER_BITNUM     0x03U
  #define PIT_CTRL                      *((volatile word *)0x0000F2E0)


  /*** PIT_MOD - PIT 0 Modulo Register; 0x0000F2E1 ***/
  union {
    word Word;
  } PIT_MOD_STR;
  
  #define PIT_MOD                       *((volatile word *)0x0000F2E1)


  /*** PIT_CNTR - PIT 0 Counter Register; 0x0000F2E2 ***/
  union {
    word Word;
  } PIT_CNTR_STR;
  
  #define PIT_CNTR                      *((volatile word *)0x0000F2E2)


  word Reserved0[29];                  /* Reserved (unused) registers */

} PIT_PRPH;

/******************************************
*** Peripheral PDB
*******************************************/
typedef volatile struct {
  /*** PDB_SCR - PDB Status and Control Register; 0x0000F300 ***/
  union {
    word Word;
  } PDB_SCR_STR;
  
  #define PDB_SCR_ENB_MASK              0x01U
  #define PDB_SCR_ENA_MASK              0x02U
  #define PDB_SCR_TRIGSEL0_MASK         0x04U
  #define PDB_SCR_TRIGSEL1_MASK         0x08U
  #define PDB_SCR_TRIGSEL2_MASK         0x10U
  #define PDB_SCR_SWTRIG_MASK           0x20U
  #define PDB_SCR_CONT_MASK             0x40U
  #define PDB_SCR_BOS0_MASK             0x80U
  #define PDB_SCR_BOS1_MASK             0x0100U
  #define PDB_SCR_AOS0_MASK             0x0400U
  #define PDB_SCR_AOS1_MASK             0x0800U
  #define PDB_SCR_PRESCALER0_MASK       0x2000U
  #define PDB_SCR_PRESCALER1_MASK       0x4000U
  #define PDB_SCR_PRESCALER2_MASK       0x8000U
  #define PDB_SCR_TRIGSEL_MASK          0x1CU
  #define PDB_SCR_TRIGSEL_BITNUM        0x02U
  #define PDB_SCR_BOS_MASK              0x0180U
  #define PDB_SCR_BOS_BITNUM            0x07U
  #define PDB_SCR_AOS_MASK              0x0C00U
  #define PDB_SCR_AOS_BITNUM            0x0AU
  #define PDB_SCR_PRESCALER_MASK        0xE000U
  #define PDB_SCR_PRESCALER_BITNUM      0x0DU
  #define PDB_SCR                       *((volatile word *)0x0000F300)


  /*** PDB_DELAYA - PDB Delay A Register; 0x0000F301 ***/
  union {
    word Word;
  } PDB_DELAYA_STR;
  
  #define PDB_DELAYA                    *((volatile word *)0x0000F301)


  /*** PDB_DELAYB - PDB Delay B Register; 0x0000F302 ***/
  union {
    word Word;
  } PDB_DELAYB_STR;
  
  #define PDB_DELAYB                    *((volatile word *)0x0000F302)


  /*** PDB_MOD - PDB Counter Modulus Register; 0x0000F303 ***/
  union {
    word Word;
  } PDB_MOD_STR;
  
  #define PDB_MOD_MOD0_MASK             0x01U
  #define PDB_MOD_MOD1_MASK             0x02U
  #define PDB_MOD_MOD2_MASK             0x04U
  #define PDB_MOD_MOD3_MASK             0x08U
  #define PDB_MOD_MOD4_MASK             0x10U
  #define PDB_MOD_MOD5_MASK             0x20U
  #define PDB_MOD_MOD6_MASK             0x40U
  #define PDB_MOD_MOD7_MASK             0x80U
  #define PDB_MOD_MOD8_MASK             0x0100U
  #define PDB_MOD_MOD9_MASK             0x0200U
  #define PDB_MOD_MOD10_MASK            0x0400U
  #define PDB_MOD_MOD11_MASK            0x0800U
  #define PDB_MOD_MOD12_MASK            0x1000U
  #define PDB_MOD_MOD13_MASK            0x2000U
  #define PDB_MOD_MOD14_MASK            0x4000U
  #define PDB_MOD_MOD15_MASK            0x8000U
  #define PDB_MOD                       *((volatile word *)0x0000F303)


  /*** PDB_COUNT - PDB Counter Value Register; 0x0000F304 ***/
  union {
    word Word;
  } PDB_COUNT_STR;
  
  #define PDB_COUNT                     *((volatile word *)0x0000F304)


  word Reserved0[27];                  /* Reserved (unused) registers */

} PDB_PRPH;

/******************************************
*** Peripheral RTC
*******************************************/
typedef volatile struct {
  /*** RTC_SC - RTC Status and Control Register; 0x0000F320 ***/
  union {
    word Word;
  } RTC_SC_STR;
  
  #define RTC_SC_RTCPS0_MASK            0x01U
  #define RTC_SC_RTCPS1_MASK            0x02U
  #define RTC_SC_RTCPS2_MASK            0x04U
  #define RTC_SC_RTCPS3_MASK            0x08U
  #define RTC_SC_RTIE_MASK              0x10U
  #define RTC_SC_RTCLKS0_MASK           0x20U
  #define RTC_SC_RTCLKS1_MASK           0x40U
  #define RTC_SC_RTIF_MASK              0x80U
  #define RTC_SC_RTCPS_MASK             0x0FU
  #define RTC_SC_RTCPS_BITNUM           0x00U
  #define RTC_SC_RTCLKS_MASK            0x60U
  #define RTC_SC_RTCLKS_BITNUM          0x05U
  #define RTC_SC                        *((volatile word *)0x0000F320)


  /*** RTC_CNT - RTC Counter Register; 0x0000F321 ***/
  union {
    word Word;
  } RTC_CNT_STR;
  
  #define RTC_CNT_RTCCNT0_MASK          0x01U
  #define RTC_CNT_RTCCNT1_MASK          0x02U
  #define RTC_CNT_RTCCNT2_MASK          0x04U
  #define RTC_CNT_RTCCNT3_MASK          0x08U
  #define RTC_CNT_RTCCNT4_MASK          0x10U
  #define RTC_CNT_RTCCNT5_MASK          0x20U
  #define RTC_CNT_RTCCNT6_MASK          0x40U
  #define RTC_CNT_RTCCNT7_MASK          0x80U
  #define RTC_CNT_RTCCNT_MASK           0xFFU
  #define RTC_CNT_RTCCNT_BITNUM         0x00U
  #define RTC_CNT                       *((volatile word *)0x0000F321)


  /*** RTC_MOD - RTC Modulo Register; 0x0000F322 ***/
  union {
    word Word;
  } RTC_MOD_STR;
  
  #define RTC_MOD_RTCMOD0_MASK          0x01U
  #define RTC_MOD_RTCMOD1_MASK          0x02U
  #define RTC_MOD_RTCMOD2_MASK          0x04U
  #define RTC_MOD_RTCMOD3_MASK          0x08U
  #define RTC_MOD_RTCMOD4_MASK          0x10U
  #define RTC_MOD_RTCMOD5_MASK          0x20U
  #define RTC_MOD_RTCMOD6_MASK          0x40U
  #define RTC_MOD_RTCMOD7_MASK          0x80U
  #define RTC_MOD_RTCMOD_MASK           0xFFU
  #define RTC_MOD_RTCMOD_BITNUM         0x00U
  #define RTC_MOD                       *((volatile word *)0x0000F322)


  word Reserved0[221];                 /* Reserved (unused) registers */

} RTC_PRPH;

/******************************************
*** Peripheral HFM
*******************************************/
typedef volatile struct {
  /*** FM_CLKDIV - Flash Memory Clock Divider Register; 0x0000F400 ***/
  union {
    word Word;
  } FM_CLKDIV_STR;
  
  #define FM_CLKDIV_DIV0_MASK           0x01U
  #define FM_CLKDIV_DIV1_MASK           0x02U
  #define FM_CLKDIV_DIV2_MASK           0x04U
  #define FM_CLKDIV_DIV3_MASK           0x08U
  #define FM_CLKDIV_DIV4_MASK           0x10U
  #define FM_CLKDIV_DIV5_MASK           0x20U
  #define FM_CLKDIV_PRDIV8_MASK         0x40U
  #define FM_CLKDIV_DIVLD_MASK          0x80U
  #define FM_CLKDIV_DIV_MASK            0x3FU
  #define FM_CLKDIV_DIV_BITNUM          0x00U
  #define FM_CLKDIV                     *((volatile word *)0x0000F400)


  /*** FM_CNFG - Flash Memory Configuration Register; 0x0000F401 ***/
  union {
    word Word;
  } FM_CNFG_STR;
  
  #define FM_CNFG_BTS_MASK              0x01U
  #define FM_CNFG_LBTS_MASK             0x02U
  #define FM_CNFG_KEYACC_MASK           0x20U
  #define FM_CNFG_CCIE_MASK             0x40U
  #define FM_CNFG_CBEIE_MASK            0x80U
  #define FM_CNFG_AEIE_MASK             0x0100U
  #define FM_CNFG_LOCK_MASK             0x0400U
  #define FM_CNFG                       *((volatile word *)0x0000F401)


  word Reserved0[1];                   /* Reserved (unused) registers */
  
  /*** FM_SECHI - Flash Memory Security High Half Register; 0x0000F403 ***/
  union {
    word Word;
  } FM_SECHI_STR;
  
  #define FM_SECHI_SECSTAT_MASK         0x4000U
  #define FM_SECHI_KEYEN_MASK           0x8000U
  #define FM_SECHI                      *((volatile word *)0x0000F403)


  /*** FM_SECLO - Flash Memory Security Low Half Register; 0x0000F404 ***/
  union {
    word Word;
  } FM_SECLO_STR;
  
  #define FM_SECLO_SEC0_MASK            0x01U
  #define FM_SECLO_SEC1_MASK            0x02U
  #define FM_SECLO_SEC_MASK             0x03U
  #define FM_SECLO_SEC_BITNUM           0x00U
  #define FM_SECLO                      *((volatile word *)0x0000F404)


  word Reserved1[11];                  /* Reserved (unused) registers */
  
  /*** FM_PROT - Flash Memory Protection Register; 0x0000F410 ***/
  union {
    word Word;
  } FM_PROT_STR;
  
  #define FM_PROT_PROTECT0_MASK         0x01U
  #define FM_PROT_PROTECT1_MASK         0x02U
  #define FM_PROT_PROTECT2_MASK         0x04U
  #define FM_PROT_PROTECT3_MASK         0x08U
  #define FM_PROT_PROTECT4_MASK         0x10U
  #define FM_PROT_PROTECT5_MASK         0x20U
  #define FM_PROT_PROTECT6_MASK         0x40U
  #define FM_PROT_PROTECT7_MASK         0x80U
  #define FM_PROT_PROTECT8_MASK         0x0100U
  #define FM_PROT_PROTECT9_MASK         0x0200U
  #define FM_PROT_PROTECT10_MASK        0x0400U
  #define FM_PROT_PROTECT11_MASK        0x0800U
  #define FM_PROT_PROTECT12_MASK        0x1000U
  #define FM_PROT_PROTECT13_MASK        0x2000U
  #define FM_PROT_PROTECT14_MASK        0x4000U
  #define FM_PROT_PROTECT15_MASK        0x8000U
  #define FM_PROT                       *((volatile word *)0x0000F410)


  word Reserved2[2];                   /* Reserved (unused) registers */
  
  /*** FM_USTAT - Flash Memory User Status Register; 0x0000F413 ***/
  union {
    word Word;
  } FM_USTAT_STR;
  
  #define FM_USTAT_BLANK_MASK           0x04U
  #define FM_USTAT_ACCERR_MASK          0x10U
  #define FM_USTAT_PVIOL_MASK           0x20U
  #define FM_USTAT_CCIF_MASK            0x40U
  #define FM_USTAT_CBEIF_MASK           0x80U
  #define FM_USTAT                      *((volatile word *)0x0000F413)


  /*** FM_CMD - Flash Memory Command and Buffer Register; 0x0000F414 ***/
  union {
    word Word;
  } FM_CMD_STR;
  
  #define FM_CMD_CMD0_MASK              0x01U
  #define FM_CMD_CMD1_MASK              0x02U
  #define FM_CMD_CMD2_MASK              0x04U
  #define FM_CMD_CMD3_MASK              0x08U
  #define FM_CMD_CMD4_MASK              0x10U
  #define FM_CMD_CMD5_MASK              0x20U
  #define FM_CMD_CMD6_MASK              0x40U
  #define FM_CMD_CMD_MASK               0x7FU
  #define FM_CMD_CMD_BITNUM             0x00U
  #define FM_CMD                        *((volatile word *)0x0000F414)


  word Reserved3[3];                   /* Reserved (unused) registers */
  
  /*** FM_DATA - Flash Memory Data Register; 0x0000F418 ***/
  union {
    word Word;
  } FM_DATA_STR;
  
  #define FM_DATA_FMDATA0_MASK          0x01U
  #define FM_DATA_FMDATA1_MASK          0x02U
  #define FM_DATA_FMDATA2_MASK          0x04U
  #define FM_DATA_FMDATA3_MASK          0x08U
  #define FM_DATA_FMDATA4_MASK          0x10U
  #define FM_DATA_FMDATA5_MASK          0x20U
  #define FM_DATA_FMDATA6_MASK          0x40U
  #define FM_DATA_FMDATA7_MASK          0x80U
  #define FM_DATA_FMDATA8_MASK          0x0100U
  #define FM_DATA_FMDATA9_MASK          0x0200U
  #define FM_DATA_FMDATA10_MASK         0x0400U
  #define FM_DATA_FMDATA11_MASK         0x0800U
  #define FM_DATA_FMDATA12_MASK         0x1000U
  #define FM_DATA_FMDATA13_MASK         0x2000U
  #define FM_DATA_FMDATA14_MASK         0x4000U
  #define FM_DATA_FMDATA15_MASK         0x8000U
  #define FM_DATA                       *((volatile word *)0x0000F418)


  word Reserved4[1];                   /* Reserved (unused) registers */
  
  /*** FM_OPT0 - Flash Optional Data Register 0; 0x0000F41A ***/
  union {
    word Word;
  } FM_OPT0_STR;
  
  #define FM_OPT0_IFR_OPT00_MASK        0x01U
  #define FM_OPT0_IFR_OPT01_MASK        0x02U
  #define FM_OPT0_IFR_OPT02_MASK        0x04U
  #define FM_OPT0_IFR_OPT03_MASK        0x08U
  #define FM_OPT0_IFR_OPT04_MASK        0x10U
  #define FM_OPT0_IFR_OPT05_MASK        0x20U
  #define FM_OPT0_IFR_OPT06_MASK        0x40U
  #define FM_OPT0_IFR_OPT07_MASK        0x80U
  #define FM_OPT0_IFR_OPT08_MASK        0x0100U
  #define FM_OPT0_IFR_OPT09_MASK        0x0200U
  #define FM_OPT0_IFR_OPT010_MASK       0x0400U
  #define FM_OPT0_IFR_OPT011_MASK       0x0800U
  #define FM_OPT0_IFR_OPT012_MASK       0x1000U
  #define FM_OPT0_IFR_OPT013_MASK       0x2000U
  #define FM_OPT0_IFR_OPT014_MASK       0x4000U
  #define FM_OPT0_IFR_OPT015_MASK       0x8000U
  #define FM_OPT0                       *((volatile word *)0x0000F41A)


  /*** FM_OPT1 - Flash Optional Data Register 1; 0x0000F41B ***/
  union {
    word Word;
  } FM_OPT1_STR;
  
  #define FM_OPT1_IFR_OPT10_MASK        0x01U
  #define FM_OPT1_IFR_OPT11_MASK        0x02U
  #define FM_OPT1_IFR_OPT12_MASK        0x04U
  #define FM_OPT1_IFR_OPT13_MASK        0x08U
  #define FM_OPT1_IFR_OPT14_MASK        0x10U
  #define FM_OPT1_IFR_OPT15_MASK        0x20U
  #define FM_OPT1_IFR_OPT16_MASK        0x40U
  #define FM_OPT1_IFR_OPT17_MASK        0x80U
  #define FM_OPT1_IFR_OPT18_MASK        0x0100U
  #define FM_OPT1_IFR_OPT19_MASK        0x0200U
  #define FM_OPT1_IFR_OPT110_MASK       0x0400U
  #define FM_OPT1_IFR_OPT111_MASK       0x0800U
  #define FM_OPT1_IFR_OPT112_MASK       0x1000U
  #define FM_OPT1_IFR_OPT113_MASK       0x2000U
  #define FM_OPT1_IFR_OPT114_MASK       0x4000U
  #define FM_OPT1_IFR_OPT115_MASK       0x8000U
  #define FM_OPT1                       *((volatile word *)0x0000F41B)


  word Reserved5[1];                   /* Reserved (unused) registers */
  
  /*** FM_TSTSIG - Flash Memory Test Array Signature Register; 0x0000F41D ***/
  union {
    word Word;
  } FM_TSTSIG_STR;
  
  #define FM_TSTSIG_TST_AREA_SIG0_MASK  0x01U
  #define FM_TSTSIG_TST_AREA_SIG1_MASK  0x02U
  #define FM_TSTSIG_TST_AREA_SIG2_MASK  0x04U
  #define FM_TSTSIG_TST_AREA_SIG3_MASK  0x08U
  #define FM_TSTSIG_TST_AREA_SIG4_MASK  0x10U
  #define FM_TSTSIG_TST_AREA_SIG5_MASK  0x20U
  #define FM_TSTSIG_TST_AREA_SIG6_MASK  0x40U
  #define FM_TSTSIG_TST_AREA_SIG7_MASK  0x80U
  #define FM_TSTSIG_TST_AREA_SIG8_MASK  0x0100U
  #define FM_TSTSIG_TST_AREA_SIG9_MASK  0x0200U
  #define FM_TSTSIG_TST_AREA_SIG10_MASK 0x0400U
  #define FM_TSTSIG_TST_AREA_SIG11_MASK 0x0800U
  #define FM_TSTSIG_TST_AREA_SIG12_MASK 0x1000U
  #define FM_TSTSIG_TST_AREA_SIG13_MASK 0x2000U
  #define FM_TSTSIG_TST_AREA_SIG14_MASK 0x4000U
  #define FM_TSTSIG_TST_AREA_SIG15_MASK 0x8000U
  #define FM_TSTSIG                     *((volatile word *)0x0000F41D)


} HFM_PRPH;




#endif
/* __IO_Map_H */

/*
** ###################################################################
**
**     This file was created by UNIS Processor Expert 2.99 [04.17]
**     for the Freescale 56800 series of microcontrollers.
**
** ###################################################################
*/
