LPCOpen Platform for LPC112X microcontrollers  112X
LPCOpen Platform for the NXP LPC112X family of Microcontrollers
chip.h
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1 /*
2  * @brief LPC11xx basic chip inclusion file
3  *
4  * Copyright(C) NXP Semiconductors, 2012
5  * All rights reserved.
6  *
7  * Software that is described herein is for illustrative purposes only
8  * which provides customers with programming information regarding the
9  * LPC products. This software is supplied "AS IS" without any warranties of
10  * any kind, and NXP Semiconductors and its licensor disclaim any and
11  * all warranties, express or implied, including all implied warranties of
12  * merchantability, fitness for a particular purpose and non-infringement of
13  * intellectual property rights. NXP Semiconductors assumes no responsibility
14  * or liability for the use of the software, conveys no license or rights under any
15  * patent, copyright, mask work right, or any other intellectual property rights in
16  * or to any products. NXP Semiconductors reserves the right to make changes
17  * in the software without notification. NXP Semiconductors also makes no
18  * representation or warranty that such application will be suitable for the
19  * specified use without further testing or modification.
20  *
21  * Permission to use, copy, modify, and distribute this software and its
22  * documentation is hereby granted, under NXP Semiconductors' and its
23  * licensor's relevant copyrights in the software, without fee, provided that it
24  * is used in conjunction with NXP Semiconductors microcontrollers. This
25  * copyright, permission, and disclaimer notice must appear in all copies of
26  * this code.
27  */
28 
29 #ifndef __CHIP_H_
30 #define __CHIP_H_
31 
32 #include "lpc_types.h"
33 #include "sys_config.h"
34 #include "cmsis.h"
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
40 #ifndef CORE_M0
41 #error CORE_M0 is not defined for the LPC1125 architecture
42 #error CORE_M0 should be defined as part of your compiler define list
43 #endif
44 
45 /* Peripheral mapping per device
46  Peripheral Address
47  ---------- ------------
48  I2C 0x40000000
49  WDT 0x40004000
50  UART0 0x40008000
51  UART1 0x40020000
52  UART2 0x40024000
53  TIMER0_16 0x4000C000
54  TIMER1_16 0x40010000
55  TIMER0_32 0x40014000
56  TIMER1_32 0x40018000
57  ADC 0x4001C000
58  PMU 0x40038000
59  FLASH_CTRL 0x4003C000
60  SSP0 0x40040000
61  IOCONF 0x40044000
62  SYSCON 0x40048000
63  SSP1 0x40058000
64  GPIO_PIO0 0x50000000
65  GPIO_PIO1 0x50010000
66  GPIO_PIO2 0x50020000
67  GPIO_PIO3 0x50030000
68  */
69 
75 #define LPC_I2C_BASE 0x40000000
76 #define LPC_WWDT_BASE 0x40004000
77 #define LPC_UART0_BASE 0x40008000
78 #define LPC_UART1_BASE 0x40020000
79 #define LPC_UART2_BASE 0x40024000
80 #define LPC_TIMER16_0_BASE 0x4000C000
81 #define LPC_TIMER16_1_BASE 0x40010000
82 #define LPC_TIMER32_0_BASE 0x40014000
83 #define LPC_TIMER32_1_BASE 0x40018000
84 #define LPC_ADC_BASE 0x4001C000
85 #define LPC_PMU_BASE 0x40038000
86 #define LPC_FLASH_BASE 0x4003C000
87 #define LPC_SSP0_BASE 0x40040000
88 #define LPC_IOCON_BASE 0x40044000
89 #define LPC_SYSCON_BASE 0x40048000
90 #define LPC_SSP1_BASE 0x40058000
91 #define LPC_GPIO_PORT0_BASE 0x50000000
92 #define LPC_GPIO_PORT1_BASE 0x50010000
93 #define LPC_GPIO_PORT2_BASE 0x50020000
94 #define LPC_GPIO_PORT3_BASE 0x50030000
95 
96 #define LPC_I2C ((LPC_I2C_T *) LPC_I2C_BASE)
97 #define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
98 #define LPC_UART0 ((LPC_UART_T *) LPC_UART0_BASE)
99 #define LPC_UART1 ((LPC_UART_T *) LPC_UART1_BASE)
100 #define LPC_UART2 ((LPC_UART_T *) LPC_UART2_BASE)
101 #define LPC_TIMER16_0 ((LPC_TIMER_T *) LPC_TIMER16_0_BASE)
102 #define LPC_TIMER16_1 ((LPC_TIMER_T *) LPC_TIMER16_1_BASE)
103 #define LPC_TIMER32_0 ((LPC_TIMER_T *) LPC_TIMER32_0_BASE)
104 #define LPC_TIMER32_1 ((LPC_TIMER_T *) LPC_TIMER32_1_BASE)
105 #define LPC_ADC ((LPC_ADC_T *) LPC_ADC_BASE)
106 #define LPC_PMU ((LPC_PMU_T *) LPC_PMU_BASE)
107 #define LPC_FMC ((LPC_FMC_T *) LPC_FLASH_BASE)
108 #define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
109 #define LPC_IOCON ((LPC_IOCON_T *) LPC_IOCON_BASE)
110 #define LPC_SYSCON ((LPC_SYSCON_T*) LPC_SYSCON_BASE)
111 #define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
112 #define LPC_GPIO ((LPC_GPIO_T *) LPC_GPIO_PORT0_BASE)
113 
128 extern const uint32_t OscRateIn;
129 
136 extern const uint32_t ExtRateIn;
137 
142 #include "i2c_112x.h"
143 #include "i2cm_112x.h"
144 #include "wwdt_112x.h"
145 #include "uart_112x.h"
146 #include "timer_112x.h"
147 #include "adc_112x.h"
148 #include "pmu_112x.h"
149 #include "fmc_112x.h"
150 #include "ssp_112x.h"
151 #include "iocon_112x.h"
152 #include "syscon_112x.h"
153 #include "clock_112x.h"
154 #include "gpio_112x.h"
155 #include "romapi_112x.h"
156 
157 
158 /* Common IRQ Handler Alias list */
159 #define UART0_IRQHanlder UART_IRQHandler
160 #define I2C0_IRQHandler I2C_IRQHandler
161 #define CMP_IRQHandler ACMP_IRQHandler
162 #define WWDT_IRQHandler WDT_IRQHandler
163 
172 extern uint32_t SystemCoreClock;
173 
179 void SystemCoreClockUpdate(void);
180 
187 void Chip_SystemInit(void);
188 
195 void Chip_SetupXtalClocking(void);
196 
201 void Chip_SetupIrcClocking(void);
202 
207 #ifdef __cplusplus
208 }
209 #endif
210 
211 #endif /* __CHIP_H_ */