LPCOpen Platform for LPC112X microcontrollers  112X
LPCOpen Platform for the NXP LPC112X family of Microcontrollers
adc_112x.h
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1 /*
2  * @brief LPC1125 A/D conversion driver
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __ADC_1125_H_
33 #define __ADC_1125_H_
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
49 typedef enum {
53 
57 typedef struct {
58  __IO uint32_t CTRL;
59  __I uint32_t RESERVED0;
60  __IO uint32_t SEQ_CTRL[ADC_SEQB_IDX + 1];
61  __IO uint32_t SEQ_GDAT[ADC_SEQB_IDX + 1];
62  __I uint32_t RESERVED1[2];
63  __I uint32_t DR[9];
64  __I uint32_t RESERVED2[3];
65  __IO uint32_t THR_LOW[2];
66  __IO uint32_t THR_HIGH[2];
67  __IO uint32_t CHAN_THRSEL;
68  __IO uint32_t INTEN;
69  __IO uint32_t FLAGS;
70  __IO uint32_t TRM;
71 } LPC_ADC_T;
72 
74 #define ADC_MAX_SAMPLE_RATE 2000000
75 
80 #define ADC_CR_CLKDIV_MASK (0xFF << 0)
81 #define ADC_CR_CLKDIV_BITPOS (0)
82 #define ADC_CR_ASYNC_MODE (1 << 8)
83 #define ADC_CR_MODE10BIT (1 << 9)
84 #define ADC_CR_LPWRMODEBIT (1 << 10)
85 #define ADC_CR_CALMODEBIT (1 << 30)
86 #define ADC_CR_BITACC(n) ((((n) & 0x1) << 9))
87 #define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 0))
88 #define ADC_SAMPLE_RATE_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x01))
89 
91 #define ADC_SEQ_CTRL_CHANSEL(n) (1 << (n))
92 #define ADC_SEQ_CTRL_CHANSEL_MASK (0xFFF)
95 #define ADC_SEQ_CTRL_HWTRIG_ARM_TXEV (0 << 12)
96 #define ADC_SEQ_CTRL_HWTRIG_CT16B1_MAT3 (1 << 12)
97 #define ADC_SEQ_CTRL_HWTRIG_CT16B1_MAT2 (2 << 12)
98 #define ADC_SEQ_CTRL_HWTRIG_PIO0_2 (3 << 12)
99 #define ADC_SEQ_CTRL_HWTRIG_PIO0_7 (4 << 12)
100 #define ADC_SEQ_CTRL_HWTRIG_PIO0_8 (5 << 12)
101 #define ADC_SEQ_CTRL_HWTRIG_PIO0_9 (6 << 12)
102 #define ADC_SEQ_CTRL_HWTRIG_PIO2_0 (7 << 12)
103 #define ADC_SEQ_CTRL_HWTRIG_MASK (0x3F << 12)
106 #define ADC_SEQ_CTRL_HWTRIG_POLPOS (1 << 18)
107 #define ADC_SEQ_CTRL_HWTRIG_SYNCBYPASS (1 << 19)
108 #define ADC_SEQ_CTRL_START (1 << 26)
109 #define ADC_SEQ_CTRL_BURST (1 << 27)
110 #define ADC_SEQ_CTRL_SINGLESTEP (1 << 28)
111 #define ADC_SEQ_CTRL_LOWPRIO (1 << 29)
112 #define ADC_SEQ_CTRL_MODE_EOS (1 << 30)
113 #define ADC_SEQ_CTRL_SEQ_ENA (1UL << 31)
116 #define ADC_SEQ_GDAT_RESULT_MASK (0xFFF << 4)
117 #define ADC_SEQ_GDAT_RESULT_BITPOS (4)
118 #define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x3 << 16)
119 #define ADC_SEQ_GDAT_THCMPRANGE_BITPOS (16)
120 #define ADC_SEQ_GDAT_THCMPCROSS_MASK (0x3 << 18)
121 #define ADC_SEQ_GDAT_THCMPCROSS_BITPOS (18)
122 #define ADC_SEQ_GDAT_CHAN_MASK (0xF << 26)
123 #define ADC_SEQ_GDAT_CHAN_BITPOS (26)
124 #define ADC_SEQ_GDAT_OVERRUN (1 << 30)
125 #define ADC_SEQ_GDAT_DATAVALID (1UL << 31)
128 #define ADC_DR_RESULT(n) ((((n) >> 4) & 0xFFF))
129 #define ADC_DR_THCMPRANGE_MASK (0x3 << 16)
130 #define ADC_DR_THCMPRANGE_BITPOS (16)
131 #define ADC_DR_THCMPRANGE(n) (((n) >> ADC_DR_THCMPRANGE_BITPOS) & 0x3)
132 #define ADC_DR_THCMPCROSS_MASK (0x3 << 18)
133 #define ADC_DR_THCMPCROSS_BITPOS (18)
134 #define ADC_DR_THCMPCROSS(n) (((n) >> ADC_DR_THCMPCROSS_BITPOS) & 0x3)
135 #define ADC_DR_CHAN_MASK (0xF << 26)
136 #define ADC_DR_CHAN_BITPOS (26)
137 #define ADC_DR_CHANNEL(n) (((n) >> ADC_DR_CHAN_BITPOS) & 0xF)
138 #define ADC_DR_OVERRUN (1 << 30)
139 #define ADC_DR_DATAVALID (1UL << 31)
140 #define ADC_DR_DONE(n) (((n) >> 31))
141 
143 #define ADC_THR_VAL_MASK (0xFFF << 4)
144 #define ADC_THR_VAL_POS (4)
147 #define ADC_THRSEL_CHAN_SEL_THR1(n) (1 << (n))
150 #define ADC_INTEN_SEQA_ENABLE (1 << 0)
151 #define ADC_INTEN_SEQB_ENABLE (1 << 1)
152 #define ADC_INTEN_SEQN_ENABLE(seq) (1 << (seq))
153 #define ADC_INTEN_OVRRUN_ENABLE (1 << 2)
154 #define ADC_INTEN_CMP_DISBALE (0)
155 #define ADC_INTEN_CMP_OUTSIDETH (1)
156 #define ADC_INTEN_CMP_CROSSTH (2)
157 #define ADC_INTEN_CMP_MASK (3)
158 #define ADC_INTEN_CMP_ENABLE(isel, ch) (((isel) & ADC_INTEN_CMP_MASK) << ((2 * (ch)) + 3))
161 #define ADC_FLAGS_THCMP_MASK(ch) (1 << (ch))
162 #define ADC_FLAGS_OVRRUN_MASK(ch) (1 << (12 + (ch)))
163 #define ADC_FLAGS_SEQA_OVRRUN_MASK (1 << 24)
164 #define ADC_FLAGS_SEQB_OVRRUN_MASK (1 << 25)
165 #define ADC_FLAGS_SEQN_OVRRUN_MASK(seq) (1 << (24 + (seq)))
166 #define ADC_FLAGS_SEQA_INT_MASK (1 << 28)
167 #define ADC_FLAGS_SEQB_INT_MASK (1 << 29)
168 #define ADC_FLAGS_SEQN_INT_MASK(seq) (1 << (28 + (seq)))
169 #define ADC_FLAGS_THCMP_INT_MASK (1 << 30)
170 #define ADC_FLAGS_OVRRUN_INT_MASK (1UL << 31)
173 #define ADC_TRIM_VRANGE_HIGHV (0 << 5)
174 #define ADC_TRIM_VRANGE_LOWV (1 << 5)
185 void Chip_ADC_Init(LPC_ADC_T *pADC, uint32_t flags);
186 
193 void Chip_ADC_DeInit(LPC_ADC_T *pADC);
194 
208 STATIC INLINE void Chip_ADC_SetDivider(LPC_ADC_T *pADC, uint8_t div)
209 {
210  uint32_t temp;
211 
212  temp = pADC->CTRL & ~(ADC_CR_CLKDIV_MASK);
213  pADC->CTRL = temp | (uint32_t) div;
214 }
215 
222 void Chip_ADC_SetClockRate(LPC_ADC_T *pADC, uint32_t rate);
223 
234 {
235  return pADC->CTRL & ADC_CR_CLKDIV_MASK;
236 }
237 
247 
254 {
255  return (bool) ((pADC->CTRL & ADC_CR_CALMODEBIT) == 0);
256 }
257 
267 void Chip_ADC_SetSequencerBits(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex, uint32_t bits);
268 
278 void Chip_ADC_ClearSequencerBits(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex, uint32_t bits);
279 
303 STATIC INLINE void Chip_ADC_SetupSequencer(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex, uint32_t options)
304 {
305  pADC->SEQ_CTRL[seqIndex] = options;
306 }
307 
315 {
317 }
318 
326 {
328 }
329 
339 {
341 }
342 
353 {
355 }
356 
364 {
366 }
367 
369 typedef enum {
375 
377 typedef enum {
383 
401 {
402  return pADC->SEQ_GDAT[seqIndex];
403 }
404 
421 STATIC INLINE uint32_t Chip_ADC_GetDataReg(LPC_ADC_T *pADC, uint8_t index)
422 {
423  return pADC->DR[index];
424 }
425 
433 STATIC INLINE void Chip_ADC_SetThrLowValue(LPC_ADC_T *pADC, uint8_t thrnum, uint16_t value)
434 {
435  pADC->THR_LOW[thrnum] = (((uint32_t) value) << ADC_THR_VAL_POS);
436 }
437 
445 STATIC INLINE void Chip_ADC_SetThrHighValue(LPC_ADC_T *pADC, uint8_t thrnum, uint16_t value)
446 {
447  pADC->THR_HIGH[thrnum] = (((uint32_t) value) << ADC_THR_VAL_POS);
448 }
449 
459 void Chip_ADC_SelectTH0Channels(LPC_ADC_T *pADC, uint32_t channels);
460 
470 void Chip_ADC_SelectTH1Channels(LPC_ADC_T *pADC, uint32_t channels);
471 
481 void Chip_ADC_EnableInt(LPC_ADC_T *pADC, uint32_t intMask);
482 
492 void Chip_ADC_DisableInt(LPC_ADC_T *pADC, uint32_t intMask);
493 
495 typedef enum {
500 
508 void Chip_ADC_SetThresholdInt(LPC_ADC_T *pADC, uint8_t ch, ADC_INTEN_THCMP_T thInt);
509 
520 {
521  return pADC->FLAGS;
522 }
523 
530 STATIC INLINE void Chip_ADC_ClearFlags(LPC_ADC_T *pADC, uint32_t flags)
531 {
532  pADC->FLAGS = flags;
533 }
534 
541 STATIC INLINE void Chip_ADC_SetTrim(LPC_ADC_T *pADC, uint32_t trim)
542 {
543  pADC->TRM = trim;
544 }
545 
550 #ifdef __cplusplus
551 }
552 #endif
553 
554 #endif /* __ADC_1125_H_ */