62 __I uint32_t RESERVED1[2];
64 __I uint32_t RESERVED2[3];
65 __IO uint32_t THR_LOW[2];
66 __IO uint32_t THR_HIGH[2];
74 #define ADC_MAX_SAMPLE_RATE 2000000
80 #define ADC_CR_CLKDIV_MASK (0xFF << 0)
81 #define ADC_CR_CLKDIV_BITPOS (0)
82 #define ADC_CR_ASYNC_MODE (1 << 8)
83 #define ADC_CR_MODE10BIT (1 << 9)
84 #define ADC_CR_LPWRMODEBIT (1 << 10)
85 #define ADC_CR_CALMODEBIT (1 << 30)
86 #define ADC_CR_BITACC(n) ((((n) & 0x1) << 9))
87 #define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 0))
88 #define ADC_SAMPLE_RATE_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x01))
91 #define ADC_SEQ_CTRL_CHANSEL(n) (1 << (n))
92 #define ADC_SEQ_CTRL_CHANSEL_MASK (0xFFF)
95 #define ADC_SEQ_CTRL_HWTRIG_ARM_TXEV (0 << 12)
96 #define ADC_SEQ_CTRL_HWTRIG_CT16B1_MAT3 (1 << 12)
97 #define ADC_SEQ_CTRL_HWTRIG_CT16B1_MAT2 (2 << 12)
98 #define ADC_SEQ_CTRL_HWTRIG_PIO0_2 (3 << 12)
99 #define ADC_SEQ_CTRL_HWTRIG_PIO0_7 (4 << 12)
100 #define ADC_SEQ_CTRL_HWTRIG_PIO0_8 (5 << 12)
101 #define ADC_SEQ_CTRL_HWTRIG_PIO0_9 (6 << 12)
102 #define ADC_SEQ_CTRL_HWTRIG_PIO2_0 (7 << 12)
103 #define ADC_SEQ_CTRL_HWTRIG_MASK (0x3F << 12)
106 #define ADC_SEQ_CTRL_HWTRIG_POLPOS (1 << 18)
107 #define ADC_SEQ_CTRL_HWTRIG_SYNCBYPASS (1 << 19)
108 #define ADC_SEQ_CTRL_START (1 << 26)
109 #define ADC_SEQ_CTRL_BURST (1 << 27)
110 #define ADC_SEQ_CTRL_SINGLESTEP (1 << 28)
111 #define ADC_SEQ_CTRL_LOWPRIO (1 << 29)
112 #define ADC_SEQ_CTRL_MODE_EOS (1 << 30)
113 #define ADC_SEQ_CTRL_SEQ_ENA (1UL << 31)
116 #define ADC_SEQ_GDAT_RESULT_MASK (0xFFF << 4)
117 #define ADC_SEQ_GDAT_RESULT_BITPOS (4)
118 #define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x3 << 16)
119 #define ADC_SEQ_GDAT_THCMPRANGE_BITPOS (16)
120 #define ADC_SEQ_GDAT_THCMPCROSS_MASK (0x3 << 18)
121 #define ADC_SEQ_GDAT_THCMPCROSS_BITPOS (18)
122 #define ADC_SEQ_GDAT_CHAN_MASK (0xF << 26)
123 #define ADC_SEQ_GDAT_CHAN_BITPOS (26)
124 #define ADC_SEQ_GDAT_OVERRUN (1 << 30)
125 #define ADC_SEQ_GDAT_DATAVALID (1UL << 31)
128 #define ADC_DR_RESULT(n) ((((n) >> 4) & 0xFFF))
129 #define ADC_DR_THCMPRANGE_MASK (0x3 << 16)
130 #define ADC_DR_THCMPRANGE_BITPOS (16)
131 #define ADC_DR_THCMPRANGE(n) (((n) >> ADC_DR_THCMPRANGE_BITPOS) & 0x3)
132 #define ADC_DR_THCMPCROSS_MASK (0x3 << 18)
133 #define ADC_DR_THCMPCROSS_BITPOS (18)
134 #define ADC_DR_THCMPCROSS(n) (((n) >> ADC_DR_THCMPCROSS_BITPOS) & 0x3)
135 #define ADC_DR_CHAN_MASK (0xF << 26)
136 #define ADC_DR_CHAN_BITPOS (26)
137 #define ADC_DR_CHANNEL(n) (((n) >> ADC_DR_CHAN_BITPOS) & 0xF)
138 #define ADC_DR_OVERRUN (1 << 30)
139 #define ADC_DR_DATAVALID (1UL << 31)
140 #define ADC_DR_DONE(n) (((n) >> 31))
143 #define ADC_THR_VAL_MASK (0xFFF << 4)
144 #define ADC_THR_VAL_POS (4)
147 #define ADC_THRSEL_CHAN_SEL_THR1(n) (1 << (n))
150 #define ADC_INTEN_SEQA_ENABLE (1 << 0)
151 #define ADC_INTEN_SEQB_ENABLE (1 << 1)
152 #define ADC_INTEN_SEQN_ENABLE(seq) (1 << (seq))
153 #define ADC_INTEN_OVRRUN_ENABLE (1 << 2)
154 #define ADC_INTEN_CMP_DISBALE (0)
155 #define ADC_INTEN_CMP_OUTSIDETH (1)
156 #define ADC_INTEN_CMP_CROSSTH (2)
157 #define ADC_INTEN_CMP_MASK (3)
158 #define ADC_INTEN_CMP_ENABLE(isel, ch) (((isel) & ADC_INTEN_CMP_MASK) << ((2 * (ch)) + 3))
161 #define ADC_FLAGS_THCMP_MASK(ch) (1 << (ch))
162 #define ADC_FLAGS_OVRRUN_MASK(ch) (1 << (12 + (ch)))
163 #define ADC_FLAGS_SEQA_OVRRUN_MASK (1 << 24)
164 #define ADC_FLAGS_SEQB_OVRRUN_MASK (1 << 25)
165 #define ADC_FLAGS_SEQN_OVRRUN_MASK(seq) (1 << (24 + (seq)))
166 #define ADC_FLAGS_SEQA_INT_MASK (1 << 28)
167 #define ADC_FLAGS_SEQB_INT_MASK (1 << 29)
168 #define ADC_FLAGS_SEQN_INT_MASK(seq) (1 << (28 + (seq)))
169 #define ADC_FLAGS_THCMP_INT_MASK (1 << 30)
170 #define ADC_FLAGS_OVRRUN_INT_MASK (1UL << 31)
173 #define ADC_TRIM_VRANGE_HIGHV (0 << 5)
174 #define ADC_TRIM_VRANGE_LOWV (1 << 5)
185 void Chip_ADC_Init(LPC_ADC_T *pADC, uint32_t flags);
213 pADC->
CTRL = temp | (uint32_t) div;
423 return pADC->
DR[index];