LPCOpen Platform for LPC112X microcontrollers  112X
LPCOpen Platform for the NXP LPC112X family of Microcontrollers
i2c_common_112x.h
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1 /*
2  * @brief LPC11xx I2C driver
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2013
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __I2C_COMMON_1125_H_
33 #define __I2C_COMMON_1125_H_
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
47 typedef struct { /* I2C0 Structure */
48  __IO uint32_t CONSET;
49  __I uint32_t STAT;
50  __IO uint32_t DAT;
51  __IO uint32_t ADR0;
52  __IO uint32_t SCLH;
53  __IO uint32_t SCLL;
54  __O uint32_t CONCLR;
55  __IO uint32_t MMCTRL;
56  __IO uint32_t ADR1;
57  __IO uint32_t ADR2;
58  __IO uint32_t ADR3;
59  __I uint32_t DATA_BUFFER;
60  __IO uint32_t MASK[4];
61 } LPC_I2C_T;
62 
63 /*
64  * @brief I2C Control Set register description
65  */
66 #define I2C_I2CONSET_AA ((0x04))
67 #define I2C_I2CONSET_SI ((0x08))
68 #define I2C_I2CONSET_STO ((0x10))
69 #define I2C_I2CONSET_STA ((0x20))
70 #define I2C_I2CONSET_I2EN ((0x40))
72 /*
73  * @brief I2C Control Clear register description
74  */
75 #define I2C_I2CONCLR_AAC ((1 << 2))
76 #define I2C_I2CONCLR_SIC ((1 << 3))
77 #define I2C_I2CONCLR_STOC ((1 << 4))
78 #define I2C_I2CONCLR_STAC ((1 << 5))
79 #define I2C_I2CONCLR_I2ENC ((1 << 6))
81 /*
82  * @brief I2C Common Control register description
83  */
84 #define I2C_CON_AA (1UL << 2)
85 #define I2C_CON_SI (1UL << 3)
86 #define I2C_CON_STO (1UL << 4)
87 #define I2C_CON_STA (1UL << 5)
88 #define I2C_CON_I2EN (1UL << 6)
90 /*
91  * @brief I2C Status Code definition (I2C Status register)
92  */
93 #define I2C_STAT_CODE_BITMASK ((0xF8))
94 #define I2C_STAT_CODE_ERROR ((0xFF))
96 /*
97  * @brief I2C Master transmit mode
98  */
99 #define I2C_I2STAT_M_TX_START ((0x08))
100 #define I2C_I2STAT_M_TX_RESTART ((0x10))
101 #define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))
102 #define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))
103 #define I2C_I2STAT_M_TX_DAT_ACK ((0x28))
104 #define I2C_I2STAT_M_TX_DAT_NACK ((0x30))
105 #define I2C_I2STAT_M_TX_ARB_LOST ((0x38))
107 /*
108  * @brief I2C Master receive mode
109  */
110 #define I2C_I2STAT_M_RX_START ((0x08))
111 #define I2C_I2STAT_M_RX_RESTART ((0x10))
112 #define I2C_I2STAT_M_RX_ARB_LOST ((0x38))
113 #define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))
114 #define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))
115 #define I2C_I2STAT_M_RX_DAT_ACK ((0x50))
116 #define I2C_I2STAT_M_RX_DAT_NACK ((0x58))
118 /*
119  * @brief I2C Slave receive mode
120  */
121 #define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))
122 #define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))
123 // #define I2C_I2STAT_S_RX_SLAW_ACK ((0x68))
124 #define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))
125 #define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))
126 // #define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78))
127 #define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))
128 #define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))
129 #define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))
130 #define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))
131 #define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))
134 /*
135  * @brief I2C Slave transmit mode
136  */
137 #define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))
138 #define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))
139 // #define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0))
140 #define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))
141 #define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))
142 #define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))
143 #define I2C_SLAVE_TIME_OUT 0x10000000UL
145 /*
146  * @brief I2C Data register definition
147  */
148 #define I2C_I2DAT_BITMASK ((0xFF))
149 #define I2C_I2DAT_IDLE_CHAR (0xFF)
152 /*
153  * @brief I2C Monitor mode control register description
154  */
155 #define I2C_I2MMCTRL_MM_ENA ((1 << 0))
156 #define I2C_I2MMCTRL_ENA_SCL ((1 << 1))
157 #define I2C_I2MMCTRL_MATCH_ALL ((1 << 2))
158 #define I2C_I2MMCTRL_BITMASK ((0x07))
160 /*
161  * @brief I2C Data buffer register description
162  */
163 #define I2DATA_BUFFER_BITMASK ((0xFF))
165 /*
166  * @brief I2C Slave Address registers definition
167  */
168 #define I2C_I2ADR_GC ((1 << 0))
169 #define I2C_I2ADR_BITMASK ((0xFF))
171 /*
172  * @brief I2C Mask Register definition
173  */
174 #define I2C_I2MASK_MASK(n) ((n & 0xFE))
176 /*
177  * @brief I2C SCL HIGH duty cycle Register definition
178  */
179 #define I2C_I2SCLH_BITMASK ((0xFFFF))
181 /*
182  * @brief I2C SCL LOW duty cycle Register definition
183  */
184 #define I2C_I2SCLL_BITMASK ((0xFFFF))
186 /*
187  * @brief I2C monitor control configuration defines
188  */
189 #define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL
190 #define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL
196  #ifdef __cplusplus
197 }
198 #endif
199 
200 #endif /* __I2C_COMMON_1125_H_ */