LPCOpen Platform for LPC112X microcontrollers  112X
LPCOpen Platform for the NXP LPC112X family of Microcontrollers
pmu_112x.h
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1 /*
2  * @brief LPC11xx PMU chip driver
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2013
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __PMU_1125_H_
33 #define __PMU_1125_H_
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
50 typedef struct {
51  __IO uint32_t PCON;
52  __IO uint32_t GPREG[5];
53 } LPC_PMU_T;
54 
58 typedef enum CHIP_PMU_MCUPOWER {
63 
67 #define PMU_PCON_PM_SLEEP (0x0)
68 #define PMU_PCON_PM_DEEPSLEEP (0x0)
69 #define PMU_PCON_PM_DEEPPOWERDOWN (0x2)
71 #define PMU_PCON_DPDEN (0x02)
72 #define PMU_PCON_SLEEPFLAG (1 << 8)
73 #define PMU_PCON_DPDFLAG (1 << 11)
74 #define PMU_GPREG4_DATA ((uint32_t) 0x1fffff << 11)
75 #define PMU_GPREG4_WAKEHYSENABLE (1 << 10)
84 STATIC INLINE void Chip_PMU_WriteGPREG(LPC_PMU_T *pPMU, uint8_t regIndex, uint32_t value)
85 {
86  pPMU->GPREG[regIndex] = value;
87 }
88 
89 STATIC INLINE void Chip_PMU_WriteGPREG4(LPC_PMU_T *pPMU, uint32_t value)
90 {
91  uint32_t reg;
92 
93  reg = pPMU->GPREG[4] & ~PMU_GPREG4_DATA;
94  pPMU->GPREG[4] = reg | (value << 11);
95 }
96 
103 STATIC INLINE uint32_t Chip_PMU_ReadGPREG(LPC_PMU_T *pPMU, uint8_t regIndex)
104 {
105  return pPMU->GPREG[regIndex];
106 }
107 
115 void Chip_PMU_SleepState(LPC_PMU_T *pPMU);
116 
127 
141 
148 void Chip_PMU_Sleep(LPC_PMU_T *pPMU, CHIP_PMU_MCUPOWER_T SleepMode);
149 
158 {
159  return pPMU->PCON & (PMU_PCON_SLEEPFLAG | PMU_PCON_DPDFLAG);
160 }
161 
170 STATIC INLINE void Chip_PMU_ClearSleepFlags(LPC_PMU_T *pPMU, uint32_t flags)
171 {
172  pPMU->PCON |= flags;
173 }
174 
183 {
184  return pPMU->GPREG[4] & PMU_GPREG4_WAKEHYSENABLE;
185 }
186 
197 {
198  pPMU->GPREG[4] |= PMU_GPREG4_WAKEHYSENABLE;
199 }
200 
205 #ifdef __cplusplus
206 }
207 #endif
208 
209 #endif /* __PMU_1125_H_ */