LPCOpen Platform for LPC112X microcontrollers  112X
LPCOpen Platform for the NXP LPC112X family of Microcontrollers
syscon_112x.h
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1 /*
2  * @brief LPC1125 System Control registers and control functions
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2015
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __SYSCON_1125_H_
33 #define __SYSCON_1125_H_
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
47 typedef struct {
48  __IO uint32_t SYSMEMREMAP;
49  __IO uint32_t PRESETCTRL;
50  __IO uint32_t SYSPLLCTRL;
51  __I uint32_t SYSPLLSTAT;
52  __I uint32_t RESERVED1[4];
53  __IO uint32_t SYSOSCCTRL;
54  __IO uint32_t WDTOSCCTRL;
55  __IO uint32_t IRCCTRL;
56  __IO uint32_t RESERVED2;
57  __IO uint32_t SYSRSTSTAT;
58  __I uint32_t RESERVED3[3];
59  __IO uint32_t SYSPLLCLKSEL;
60  __IO uint32_t SYSPLLCLKUEN;
61  __I uint32_t RESERVED4[10];
62  __IO uint32_t MAINCLKSEL;
63  __IO uint32_t MAINCLKUEN;
64  __IO uint32_t SYSAHBCLKDIV;
65  __I uint32_t RESERVED5;
66  __IO uint32_t SYSAHBCLKCTRL;
67  __I uint32_t RESERVED6[4];
68  __IO uint32_t SSP0CLKDIV;
69  __IO uint32_t UART0CLKDIV;
70  __IO uint32_t SSP1CLKDIV;
71  __IO uint32_t UART1CLKDIV;
72  __IO uint32_t UART2CLKDIV;
73  __I uint32_t RESERVED7[10];
74  __IO uint32_t WDTCLKSEL;
75  __IO uint32_t WDTCLKUEN;
76  __IO uint32_t WDTCLKDIV;
77  __I uint32_t RESERVED8;
78  __IO uint32_t CLKOUTSEL;
79  __IO uint32_t CLKOUTUEN;
80  __IO uint32_t CLKOUTDIV;
81  __I uint32_t RESERVED9[5];
82  __I uint32_t PIOPORCAP[2];
83  __I uint32_t RESERVED10[18];
84  __IO uint32_t BODCTRL;
85  __IO uint32_t SYSTCKCAL;
86  __I uint32_t RESERVED11[6];
87  __IO uint32_t IRQLATENCY;
88  __IO uint32_t NMISRC;
89  __IO uint32_t RESERVED12[34];
90  __IO uint32_t STARTAPRP0;
91  __IO uint32_t STARTERP0;
92  __IO uint32_t STARTRSRP0CLR;
93  __IO uint32_t STARTSRP0;
94  __I uint32_t RESERVED13[8];
95  __IO uint32_t PDSLEEPCFG;
96  __IO uint32_t PDWAKECFG;
97  __IO uint32_t PDRUNCFG;
98 } LPC_SYSCON_T;
99 
103 typedef enum CHIP_SYSCON_BOOT_MODE_REMAP {
108 
115 {
116  LPC_SYSCON->SYSMEMREMAP = (uint32_t) remap;
117 }
118 
122 typedef enum {
127 
136 {
137  LPC_SYSCON->PRESETCTRL &= ~(1 << (uint32_t) periph);
138 }
139 
146 {
147  LPC_SYSCON->PRESETCTRL |= (1 << (uint32_t) periph);
148 }
149 
156 {
159 }
160 
164 #define SYSCON_RST_POR (1 << 0)
165 #define SYSCON_RST_EXTRST (1 << 1)
166 #define SYSCON_RST_WDT (1 << 2)
167 #define SYSCON_RST_BOD (1 << 3)
168 #define SYSCON_RST_SYSRST (1 << 4)
173 #define SYSCON_NMISRC_ENABLE ((uint32_t) 1 << 31)
180 STATIC INLINE uint32_t Chip_SYSCON_GetSystemRSTStatus(void)
181 {
182  return LPC_SYSCON->SYSRSTSTAT;
183 }
184 
192 {
193  LPC_SYSCON->SYSRSTSTAT = reset;
194 }
195 
203 {
204  return LPC_SYSCON->PIOPORCAP[index];
205 }
206 
210 typedef enum CHIP_SYSCON_BODRSTLVL {
216 
220 typedef enum CHIP_SYSCON_BODRINTVAL {
226 
237 {
238  LPC_SYSCON->BODCTRL = ((uint32_t) rstlvl) | (((uint32_t) intlvl) << 2);
239 }
240 
246 {
247  LPC_SYSCON->BODCTRL |= (1 << 4);
248 }
249 
255 {
256  LPC_SYSCON->BODCTRL &= ~(1 << 4);
257 }
258 
259 
265 STATIC INLINE void Chip_SYSCON_SetSYSTCKCAL(uint32_t sysCalVal)
266 {
267  LPC_SYSCON->SYSTCKCAL = sysCalVal;
268 }
269 
278 {
279  LPC_SYSCON->IRQLATENCY = latency;
280 }
281 
287 {
288  return LPC_SYSCON->IRQLATENCY;
289 }
290 
299 {
300  LPC_SYSCON->NMISRC = intsrc;
301 }
302 
308 {
309  LPC_SYSCON->NMISRC |= SYSCON_NMISRC_ENABLE;
310 }
311 
317 {
318  LPC_SYSCON->NMISRC &= ~(SYSCON_NMISRC_ENABLE);
319 }
320 
328 STATIC INLINE void Chip_SYSCON_SetStartPin(uint32_t pin, uint32_t edge)
329 {
330  if (edge) {
331  LPC_SYSCON->STARTAPRP0 |= (1 << pin);
332  }
333  else {
334  LPC_SYSCON->STARTAPRP0 &= ~(1 << pin);
335  }
336 }
337 
345 {
346  LPC_SYSCON->STARTERP0 |= (1 << pin);
347 }
348 
356 {
357  LPC_SYSCON->STARTERP0 &= ~(1 << pin);
358 }
359 
367 {
368  LPC_SYSCON->STARTRSRP0CLR = (1 << pin);
369 }
370 
378 {
379  return (bool) ((LPC_SYSCON->STARTSRP0 & (1 << pin)) != 0);
380 }
381 
385 #define SYSCON_DEEPSLP_BOD_PD (1 << 3)
386 #define SYSCON_DEEPSLP_WDTOSC_PD (1 << 6)
398 void Chip_SYSCON_SetDeepSleepPD(uint32_t sleepmask);
399 
406 {
407  return LPC_SYSCON->PDSLEEPCFG;
408 }
409 
413 #define SYSCON_SLPWAKE_IRCOUT_PD (1 << 0)
414 #define SYSCON_SLPWAKE_IRC_PD (1 << 1)
415 #define SYSCON_SLPWAKE_FLASH_PD (1 << 2)
416 #define SYSCON_SLPWAKE_BOD_PD (1 << 3)
417 #define SYSCON_SLPWAKE_ADC_PD (1 << 4)
418 #define SYSCON_SLPWAKE_SYSOSC_PD (1 << 5)
419 #define SYSCON_SLPWAKE_WDTOSC_PD (1 << 6)
420 #define SYSCON_SLPWAKE_SYSPLL_PD (1 << 7)
432 void Chip_SYSCON_SetWakeup(uint32_t wakeupmask);
433 
440 {
441  return LPC_SYSCON->PDWAKECFG;
442 }
443 
447 #define SYSCON_POWERDOWN_IRCOUT_PD (1 << 0)
448 #define SYSCON_POWERDOWN_IRC_PD (1 << 1)
449 #define SYSCON_POWERDOWN_FLASH_PD (1 << 2)
450 #define SYSCON_POWERDOWN_BOD_PD (1 << 3)
451 #define SYSCON_POWERDOWN_ADC_PD (1 << 4)
452 #define SYSCON_POWERDOWN_SYSOSC_PD (1 << 5)
453 #define SYSCON_POWERDOWN_WDTOSC_PD (1 << 6)
454 #define SYSCON_POWERDOWN_SYSPLL_PD (1 << 7)
461 void Chip_SYSCON_PowerDown(uint32_t powerdownmask);
462 
468 void Chip_SYSCON_PowerUp(uint32_t powerupmask);
469 
476 {
477  return LPC_SYSCON->PDRUNCFG;
478 }
479 
484 #ifdef __cplusplus
485 }
486 #endif
487 
488 #endif