LPCOpen Platform for LPC112X microcontrollers  112X
LPCOpen Platform for the NXP LPC112X family of Microcontrollers
Macros | Enumerations | Functions
CHIP: LPC11xx Clock Control block driver

Detailed Description

Macros

#define SYSCON_IRC_FREQ   (12000000)
 

Enumerations

enum  CHIP_SYSCON_PLLCLKSRC_T { SYSCON_PLLCLKSRC_IRC = 0, SYSCON_PLLCLKSRC_MAINOSC, SYSCON_PLLCLKSRC_RESERVED1, SYSCON_PLLCLKSRC_RESERVED2 }
 
enum  CHIP_WDTLFO_OSC_T {
  WDTLFO_OSC_ILLEGAL, WDTLFO_OSC_0_60, WDTLFO_OSC_1_05, WDTLFO_OSC_1_40,
  WDTLFO_OSC_1_75, WDTLFO_OSC_2_10, WDTLFO_OSC_2_40, WDTLFO_OSC_2_70,
  WDTLFO_OSC_3_00, WDTLFO_OSC_3_25, WDTLFO_OSC_3_50, WDTLFO_OSC_3_75,
  WDTLFO_OSC_4_00, WDTLFO_OSC_4_20, WDTLFO_OSC_4_40, WDTLFO_OSC_4_60
}
 
enum  CHIP_SYSCON_MAINCLKSRC_T {
  SYSCON_MAINCLKSRC_IRC = 0, SYSCON_MAINCLKSRC_PLLIN, SYSCON_MAINCLKSRC_LFOSC, SYSCON_MAINCLKSRC_WDTOSC = SYSCON_MAINCLKSRC_LFOSC,
  SYSCON_MAINCLKSRC_PLLOUT
}
 
enum  CHIP_SYSCON_CLOCK_T {
  SYSCON_CLOCK_SYS = 0, SYSCON_CLOCK_ROM, SYSCON_CLOCK_RAM, SYSCON_CLOCK_FLASHREG,
  SYSCON_CLOCK_FLASHARRAY, SYSCON_CLOCK_I2C, SYSCON_CLOCK_GPIO, SYSCON_CLOCK_CT16B0,
  SYSCON_CLOCK_CT16B1, SYSCON_CLOCK_CT32B0, SYSCON_CLOCK_CT32B1, SYSCON_CLOCK_SSP0,
  SYSCON_CLOCK_UART0, SYSCON_CLOCK_ADC, SYSCON_CLOCK_RESERVED14, SYSCON_CLOCK_WDT,
  SYSCON_CLOCK_IOCON, SYSCON_CLOCK_RESERVED17, SYSCON_CLOCK_SSP1
}
 
enum  CHIP_SYSCON_WDTCLKSRC_T { SYSCON_WDTCLKSRC_IRC = 0, SYSCON_WDTCLKSRC_MAINSYSCLK, SYSCON_WDTCLKSRC_WDTOSC }
 
enum  CHIP_SYSCON_CLKOUTSRC_T {
  SYSCON_CLKOUTSRC_IRC = 0, SYSCON_CLKOUTSRC_MAINOSC, SYSCON_CLKOUTSRC_WDTOSC, SYSCON_CLKOUTSRC_LFOSC = SYSCON_CLKOUTSRC_WDTOSC,
  SYSCON_CLKOUTSRC_MAINSYSCLK
}
 

Functions

STATIC INLINE void Chip_Clock_SetupSystemPLL (uint8_t msel, uint8_t psel)
 Set System PLL divider values. More...
 
STATIC INLINE bool Chip_Clock_IsSystemPLLLocked (void)
 Read System PLL lock status. More...
 
void Chip_Clock_SetSystemPLLSource (CHIP_SYSCON_PLLCLKSRC_T src)
 Set System PLL clock source. More...
 
void Chip_Clock_SetPLLBypass (bool bypass, bool highfr)
 Bypass System Oscillator and set oscillator frequency range. More...
 
STATIC INLINE void Chip_Clock_SetWDTOSC (CHIP_WDTLFO_OSC_T wdtclk, uint8_t div)
 Setup Watchdog oscillator rate and divider. More...
 
void Chip_Clock_SetMainClockSource (CHIP_SYSCON_MAINCLKSRC_T src)
 Set main system clock source. More...
 
STATIC INLINE
CHIP_SYSCON_MAINCLKSRC_T 
Chip_Clock_GetMainClockSource (void)
 Returns the main clock source. More...
 
STATIC INLINE void Chip_Clock_SetSysClockDiv (uint32_t div)
 Set system clock divider. More...
 
STATIC INLINE void Chip_Clock_EnablePeriphClock (CHIP_SYSCON_CLOCK_T clk)
 Enable a system or peripheral clock. More...
 
STATIC INLINE void Chip_Clock_DisablePeriphClock (CHIP_SYSCON_CLOCK_T clk)
 Disable a system or peripheral clock. More...
 
STATIC INLINE void Chip_Clock_SetSSP0ClockDiv (uint32_t div)
 Set SSP0 divider. More...
 
STATIC INLINE uint32_t Chip_Clock_GetSSP0ClockDiv (void)
 Return SSP0 divider. More...
 
STATIC INLINE void Chip_Clock_SetUARTClockDiv (uint32_t div)
 Set UART divider clock. More...
 
STATIC INLINE uint32_t Chip_Clock_GetUARTClockDiv (void)
 Return UART divider. More...
 
STATIC INLINE void Chip_Clock_SetSSP1ClockDiv (uint32_t div)
 Set SSP1 divider clock. More...
 
STATIC INLINE uint32_t Chip_Clock_GetSSP1ClockDiv (void)
 Return SSP1 divider. More...
 
void Chip_Clock_SetWDTClockSource (CHIP_SYSCON_WDTCLKSRC_T src, uint32_t div)
 Set WDT clock source and divider. More...
 
void Chip_Clock_SetCLKOUTSource (CHIP_SYSCON_CLKOUTSRC_T src, uint32_t div)
 Set CLKOUT clock source and divider. More...
 
STATIC INLINE uint32_t Chip_Clock_GetMainOscRate (void)
 Returns the main oscillator clock rate. More...
 
STATIC INLINE uint32_t Chip_Clock_GetIntOscRate (void)
 Returns the internal oscillator (IRC) clock rate. More...
 
uint32_t Chip_Clock_GetWDTOSCRate (void)
 Return estimated watchdog oscillator rate. More...
 
uint32_t Chip_Clock_GetSystemPLLInClockRate (void)
 Return System PLL input clock rate. More...
 
uint32_t Chip_Clock_GetSystemPLLOutClockRate (void)
 Return System PLL output clock rate. More...
 
uint32_t Chip_Clock_GetMainClockRate (void)
 Return main clock rate. More...
 
uint32_t Chip_Clock_GetSystemClockRate (void)
 Return system clock rate. More...
 

Macro Definition Documentation

#define SYSCON_IRC_FREQ   (12000000)

Internal oscillator frequency

Definition at line 45 of file clock_112x.h.

Enumeration Type Documentation

Clock sources for CLKOUT

Enumerator
SYSCON_CLKOUTSRC_IRC 

Internal oscillator for CLKOUT

SYSCON_CLKOUTSRC_MAINOSC 

Main oscillator for CLKOUT

SYSCON_CLKOUTSRC_WDTOSC 

Watchdog oscillator for CLKOUT

SYSCON_CLKOUTSRC_LFOSC 

LF oscillator rate (LPC11A/Exx only) for CLKOUT

SYSCON_CLKOUTSRC_MAINSYSCLK 

Main system clock for CLKOUT

Definition at line 308 of file clock_112x.h.

System and peripheral clocks

Enumerator
SYSCON_CLOCK_SYS 

0: System clock

SYSCON_CLOCK_ROM 

1: ROM clock

SYSCON_CLOCK_RAM 

2: RAM clock

SYSCON_CLOCK_FLASHREG 

3: FLASH register interface clock

SYSCON_CLOCK_FLASHARRAY 

4: FLASH array access clock

SYSCON_CLOCK_I2C 

5: I2C clock, not on LPC110x

SYSCON_CLOCK_GPIO 

6: GPIO clock

SYSCON_CLOCK_CT16B0 

7: 16-bit Counter/timer 0 clock

SYSCON_CLOCK_CT16B1 

8: 16-bit Counter/timer 1 clock

SYSCON_CLOCK_CT32B0 

9: 32-bit Counter/timer 0 clock

SYSCON_CLOCK_CT32B1 

10: 32-bit Counter/timer 1 clock

SYSCON_CLOCK_SSP0 

11: SSP0 clock

SYSCON_CLOCK_UART0 

12: UART0 clock

SYSCON_CLOCK_ADC 

13: ADC clock

SYSCON_CLOCK_RESERVED14 

14: Reserved

SYSCON_CLOCK_WDT 

15: Watchdog timer clock

SYSCON_CLOCK_IOCON 

16: IOCON block clock

SYSCON_CLOCK_RESERVED17 

17: Reserved

SYSCON_CLOCK_SSP1 

18: SSP1 clock, LPC11A/C/E/Uxx//1125 only

Definition at line 176 of file clock_112x.h.

Clock sources for main system clock

Enumerator
SYSCON_MAINCLKSRC_IRC 

Internal oscillator

SYSCON_MAINCLKSRC_PLLIN 

System PLL input

SYSCON_MAINCLKSRC_LFOSC 

LF oscillator rate (11Axx only)

SYSCON_MAINCLKSRC_WDTOSC 

Watchdog oscillator rate

SYSCON_MAINCLKSRC_PLLOUT 

System PLL output

Definition at line 135 of file clock_112x.h.

Clock sources for system and USB PLLs

Enumerator
SYSCON_PLLCLKSRC_IRC 

Internal oscillator in

SYSCON_PLLCLKSRC_MAINOSC 

Crystal (main) oscillator in

SYSCON_PLLCLKSRC_RESERVED1 

Reserved

SYSCON_PLLCLKSRC_RESERVED2 

Reserved

Definition at line 71 of file clock_112x.h.

Clock sources for WDT

Enumerator
SYSCON_WDTCLKSRC_IRC 

Internal oscillator for watchdog clock

SYSCON_WDTCLKSRC_MAINSYSCLK 

Main system clock for watchdog clock

SYSCON_WDTCLKSRC_WDTOSC 

Watchdog oscillator for watchdog clock

Definition at line 287 of file clock_112x.h.

Watchdog and low frequency oscillator frequencies plus or minus 40%

Enumerator
WDTLFO_OSC_ILLEGAL 
WDTLFO_OSC_0_60 

0.6 MHz watchdog/LFO rate

WDTLFO_OSC_1_05 

1.05 MHz watchdog/LFO rate

WDTLFO_OSC_1_40 

1.4 MHz watchdog/LFO rate

WDTLFO_OSC_1_75 

1.75 MHz watchdog/LFO rate

WDTLFO_OSC_2_10 

2.1 MHz watchdog/LFO rate

WDTLFO_OSC_2_40 

2.4 MHz watchdog/LFO rate

WDTLFO_OSC_2_70 

2.7 MHz watchdog/LFO rate

WDTLFO_OSC_3_00 

3.0 MHz watchdog/LFO rate

WDTLFO_OSC_3_25 

3.25 MHz watchdog/LFO rate

WDTLFO_OSC_3_50 

3.5 MHz watchdog/LFO rate

WDTLFO_OSC_3_75 

3.75 MHz watchdog/LFO rate

WDTLFO_OSC_4_00 

4.0 MHz watchdog/LFO rate

WDTLFO_OSC_4_20 

4.2 MHz watchdog/LFO rate

WDTLFO_OSC_4_40 

4.4 MHz watchdog/LFO rate

WDTLFO_OSC_4_60 

4.6 MHz watchdog/LFO rate

Definition at line 101 of file clock_112x.h.

Function Documentation

STATIC INLINE void Chip_Clock_DisablePeriphClock ( CHIP_SYSCON_CLOCK_T  clk)

Disable a system or peripheral clock.

Parameters
clk: Clock to disable
Returns
Nothing

Definition at line 213 of file clock_112x.h.

STATIC INLINE void Chip_Clock_EnablePeriphClock ( CHIP_SYSCON_CLOCK_T  clk)

Enable a system or peripheral clock.

Parameters
clk: Clock to enable
Returns
Nothing

Definition at line 203 of file clock_112x.h.

STATIC INLINE uint32_t Chip_Clock_GetIntOscRate ( void  )

Returns the internal oscillator (IRC) clock rate.

Returns
internal oscillator (IRC) clock rate

Definition at line 341 of file clock_112x.h.

uint32_t Chip_Clock_GetMainClockRate ( void  )

Return main clock rate.

Returns
main clock rate

Definition at line 174 of file clock_112x.c.

STATIC INLINE CHIP_SYSCON_MAINCLKSRC_T Chip_Clock_GetMainClockSource ( void  )

Returns the main clock source.

Returns
Which clock is used for the core clock source?

Definition at line 156 of file clock_112x.h.

STATIC INLINE uint32_t Chip_Clock_GetMainOscRate ( void  )

Returns the main oscillator clock rate.

Returns
main oscillator clock rate

Definition at line 332 of file clock_112x.h.

STATIC INLINE uint32_t Chip_Clock_GetSSP0ClockDiv ( void  )

Return SSP0 divider.

Returns
divider for SSP0 clock
Note
A value of 0 means the clock is disabled.

Definition at line 235 of file clock_112x.h.

STATIC INLINE uint32_t Chip_Clock_GetSSP1ClockDiv ( void  )

Return SSP1 divider.

Returns
divider for SSP1 clock
Note
A value of 0 means the clock is disabled.

Definition at line 279 of file clock_112x.h.

uint32_t Chip_Clock_GetSystemClockRate ( void  )

Return system clock rate.

Returns
system clock rate

Definition at line 200 of file clock_112x.c.

uint32_t Chip_Clock_GetSystemPLLInClockRate ( void  )

Return System PLL input clock rate.

Returns
System PLL input clock rate

Definition at line 146 of file clock_112x.c.

uint32_t Chip_Clock_GetSystemPLLOutClockRate ( void  )

Return System PLL output clock rate.

Returns
System PLL output clock rate

Definition at line 167 of file clock_112x.c.

STATIC INLINE uint32_t Chip_Clock_GetUARTClockDiv ( void  )

Return UART divider.

Returns
divider for UART clock
Note
A value of 0 means the clock is disabled.

Definition at line 257 of file clock_112x.h.

uint32_t Chip_Clock_GetWDTOSCRate ( void  )

Return estimated watchdog oscillator rate.

Returns
Estimated watchdog oscillator rate
Note
This rate is accurate to plus or minus 40%.

Definition at line 140 of file clock_112x.c.

STATIC INLINE bool Chip_Clock_IsSystemPLLLocked ( void  )

Read System PLL lock status.

Returns
true of the PLL is locked. false if not locked

Definition at line 63 of file clock_112x.h.

void Chip_Clock_SetCLKOUTSource ( CHIP_SYSCON_CLKOUTSRC_T  src,
uint32_t  div 
)

Set CLKOUT clock source and divider.

Parameters
src: Clock source for CLKOUT
div: divider for CLKOUT clock
Returns
Nothing
Note
Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock rate is the clock source divided by the divider. This function will also toggle the clock source update register to update the clock source.

Definition at line 130 of file clock_112x.c.

void Chip_Clock_SetMainClockSource ( CHIP_SYSCON_MAINCLKSRC_T  src)

Set main system clock source.

Parameters
src: Clock source for main system
Returns
Nothing
Note
This function will also toggle the clock source update register to update the clock source.

Definition at line 113 of file clock_112x.c.

void Chip_Clock_SetPLLBypass ( bool  bypass,
bool  highfr 
)

Bypass System Oscillator and set oscillator frequency range.

Parameters
bypass: Flag to bypass oscillator
highfr: Flag to set oscillator range from 15-25 MHz
Returns
Nothing
Note
Sets the PLL input to bypass the oscillator. This would be used if an external clock that is not an oscillator is attached to the XTALIN pin.

Definition at line 98 of file clock_112x.c.

STATIC INLINE void Chip_Clock_SetSSP0ClockDiv ( uint32_t  div)

Set SSP0 divider.

Parameters
div: divider for SSP0 clock
Returns
Nothing
Note
Use 0 to disable, or a divider value of 1 to 255. The SSP0 clock rate is the main system clock divided by this value.

Definition at line 225 of file clock_112x.h.

STATIC INLINE void Chip_Clock_SetSSP1ClockDiv ( uint32_t  div)

Set SSP1 divider clock.

Parameters
div: divider for SSP1 clock
Returns
Nothing
Note
Use 0 to disable, or a divider value of 1 to 255. The SSP1 clock rate is the main system clock divided by this value.

Definition at line 269 of file clock_112x.h.

STATIC INLINE void Chip_Clock_SetSysClockDiv ( uint32_t  div)

Set system clock divider.

Parameters
div: divider for system clock
Returns
Nothing
Note
Use 0 to disable, or a divider value of 1 to 255. The system clock rate is the main system clock divided by this value.

Definition at line 168 of file clock_112x.h.

void Chip_Clock_SetSystemPLLSource ( CHIP_SYSCON_PLLCLKSRC_T  src)

Set System PLL clock source.

Parameters
src: Clock source for system PLL
Returns
Nothing
Note
This function will also toggle the clock source update register to update the clock source.

Definition at line 90 of file clock_112x.c.

STATIC INLINE void Chip_Clock_SetUARTClockDiv ( uint32_t  div)

Set UART divider clock.

Parameters
div: divider for UART clock
Returns
Nothing
Note
Use 0 to disable, or a divider value of 1 to 255. The UART clock rate is the main system clock divided by this value.

Definition at line 247 of file clock_112x.h.

STATIC INLINE void Chip_Clock_SetupSystemPLL ( uint8_t  msel,
uint8_t  psel 
)

Set System PLL divider values.

Parameters
msel: PLL feedback divider value. M = msel + 1.
psel: PLL post divider value. P = (1<<psel).
Returns
Nothing
Note
See the user manual for how to setup the PLL.

Definition at line 54 of file clock_112x.h.

void Chip_Clock_SetWDTClockSource ( CHIP_SYSCON_WDTCLKSRC_T  src,
uint32_t  div 
)

Set WDT clock source and divider.

Parameters
src: Clock source for WDT
div: divider for WDT clock
Returns
Nothing
Note
Use 0 to disable, or a divider value of 1 to 255. The WDT clock rate is the clock source divided by the divider. This function will also toggle the clock source update register to update the clock source.

Definition at line 121 of file clock_112x.c.

STATIC INLINE void Chip_Clock_SetWDTOSC ( CHIP_WDTLFO_OSC_T  wdtclk,
uint8_t  div 
)

Setup Watchdog oscillator rate and divider.

Parameters
wdtclk: Selected watchdog clock rate
div: Watchdog divider value, even value between 2 and 64
Returns
Nothing
Note
Watchdog rate = selected rate divided by divider rate

Definition at line 127 of file clock_112x.h.