LPCOpen Platform for LPC112X microcontrollers  112X
LPCOpen Platform for the NXP LPC112X family of Microcontrollers
error.h
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1 /*
2  * @brief Error code returned by Boot ROM drivers/library functions
3  *
4  * This file contains unified error codes to be used across driver,
5  * middleware, applications, hal and demo software.
6  *
7  *
8  * @note
9  * Copyright(C) NXP Semiconductors, 2012
10  * All rights reserved.
11  *
12  * @par
13  * Software that is described herein is for illustrative purposes only
14  * which provides customers with programming information regarding the
15  * LPC products. This software is supplied "AS IS" without any warranties of
16  * any kind, and NXP Semiconductors and its licensor disclaim any and
17  * all warranties, express or implied, including all implied warranties of
18  * merchantability, fitness for a particular purpose and non-infringement of
19  * intellectual property rights. NXP Semiconductors assumes no responsibility
20  * or liability for the use of the software, conveys no license or rights under any
21  * patent, copyright, mask work right, or any other intellectual property rights in
22  * or to any products. NXP Semiconductors reserves the right to make changes
23  * in the software without notification. NXP Semiconductors also makes no
24  * representation or warranty that such application will be suitable for the
25  * specified use without further testing or modification.
26  *
27  * @par
28  * Permission to use, copy, modify, and distribute this software and its
29  * documentation is hereby granted, under NXP Semiconductors' and its
30  * licensor's relevant copyrights in the software, without fee, provided that it
31  * is used in conjunction with NXP Semiconductors microcontrollers. This
32  * copyright, permission, and disclaimer notice must appear in all copies of
33  * this code.
34  */
35 
36 #ifndef __LPC_ERROR_H__
37 #define __LPC_ERROR_H__
38 
46 typedef enum
47 { LPC_OK=0, ERR_FAILED = -1, ERR_TIME_OUT = -2, ERR_BUSY = -3,
53  /* ISP related errors */
54  ERR_ISP_BASE = 0x00000000,
55  /*0x00000001*/ ERR_ISP_INVALID_COMMAND = ERR_ISP_BASE + 1,
56  /*0x00000002*/ ERR_ISP_SRC_ADDR_ERROR, /* Source address not on word boundary */
57  /*0x00000003*/ ERR_ISP_DST_ADDR_ERROR, /* Destination address not on word or 256 byte boundary */
60  /*0x00000006*/ ERR_ISP_COUNT_ERROR, /* Byte count is not multiple of 4 or is not a permitted value */
61  /*0x00000007*/ ERR_ISP_INVALID_SECTOR,
62  /*0x00000008*/ ERR_ISP_SECTOR_NOT_BLANK,
64  /*0x0000000A*/ ERR_ISP_COMPARE_ERROR,
65  /*0x0000000B*/ ERR_ISP_BUSY, /* Flash programming hardware interface is busy */
66  /*0x0000000C*/ ERR_ISP_PARAM_ERROR, /* Insufficient number of parameters */
67  /*0x0000000D*/ ERR_ISP_ADDR_ERROR, /* Address not on word boundary */
68  /*0x0000000E*/ ERR_ISP_ADDR_NOT_MAPPED,
69  /*0x0000000F*/ ERR_ISP_CMD_LOCKED, /* Command is locked */
70  /*0x00000010*/ ERR_ISP_INVALID_CODE, /* Unlock code is invalid */
71  /*0x00000011*/ ERR_ISP_INVALID_BAUD_RATE,
72  /*0x00000012*/ ERR_ISP_INVALID_STOP_BIT,
77  /*0x00000017*/ ERR_ISP_IRC_NO_POWER,
78  /*0x00000018*/ ERR_ISP_FLASH_NO_POWER,
79  /*0x00000019*/ ERR_ISP_EEPROM_NO_POWER,
80  /*0x0000001A*/ ERR_ISP_EEPROM_NO_CLOCK,
81  /*0x0000001B*/ ERR_ISP_FLASH_NO_CLOCK,
83 
84  /* ROM API related errors */
92  /* SPIFI API related errors */
93  ERR_SPIFI_BASE = 0x00020000,
95  /*0x00020002*/ ERR_SPIFI_INTERNAL_ERROR,
96  /*0x00020003*/ ERR_SPIFI_TIMEOUT,
97  /*0x00020004*/ ERR_SPIFI_OPERAND_ERROR,
98  /*0x00020005*/ ERR_SPIFI_STATUS_PROBLEM,
99  /*0x00020006*/ ERR_SPIFI_UNKNOWN_EXT,
100  /*0x00020007*/ ERR_SPIFI_UNKNOWN_ID,
101  /*0x00020008*/ ERR_SPIFI_UNKNOWN_TYPE,
102  /*0x00020009*/ ERR_SPIFI_UNKNOWN_MFG,
103  /*0x0002000A*/ ERR_SPIFI_NO_DEVICE,
104  /*0x0002000B*/ ERR_SPIFI_ERASE_NEEDED,
105 
107  /* Security API related errors */
108  ERR_SEC_AES_BASE = 0x00030000,
113  /*0x00030005*/ ERR_SEC_AES_DMA_MUX_CFG,
114  /*0x00030006*/ SEC_AES_DMA_BUSY,
115 
116  /* USB device stack related errors */
130  /* CGU related errors */
131  ERR_CGU_BASE = 0x00050000,
132  /*0x00050001*/ ERR_CGU_NOT_IMPL=ERR_CGU_BASE+1,
133  /*0x00050002*/ ERR_CGU_INVALID_PARAM,
134  /*0x00050003*/ ERR_CGU_INVALID_SLICE,
135  /*0x00050004*/ ERR_CGU_OUTPUT_GEN,
136  /*0x00050005*/ ERR_CGU_DIV_SRC,
137  /*0x00050006*/ ERR_CGU_DIV_VAL,
138  /*0x00050007*/ ERR_CGU_SRC,
139 
140  /* I2C related errors */
141  ERR_I2C_BASE = 0x00060000,
142  /*0x00060000*/ ERR_I2C_BUSY = ERR_I2C_BASE,
143  /*0x00060001*/ ERR_I2C_NAK,
144  /*0x00060002*/ ERR_I2C_BUFFER_OVERFLOW,
145  /*0x00060003*/ ERR_I2C_BYTE_COUNT_ERR,
149  /*0x00060007*/ ERR_I2C_GENERAL_FAILURE,
151  /*0x00060009*/ ERR_I2C_TIMEOUT,
152  /*0x0006000A*/ ERR_I2C_BUFFER_UNDERFLOW,
153  /*0x0006000B*/ ERR_I2C_PARAM,
154 
155  /* OTP related errors */
156  ERR_OTP_BASE = 0x00070000,
162  /*0x00070006*/ ERR_OTP_USB_ID_ENABLED,
163  /*0x00070007*/ ERR_OTP_ETH_MAC_ENABLED,
164  /*0x00070008*/ ERR_OTP_AES_KEYS_ENABLED,
165  /*0x00070009*/ ERR_OTP_ILLEGAL_BANK,
166 
167  /* UART related errors */
168  ERR_UART_BASE = 0x00080000,
169  /*0x00080001*/ ERR_UART_RXD_BUSY = ERR_UART_BASE+1, //UART rxd is busy
170  /*0x00080002*/ ERR_UART_TXD_BUSY, //UART txd is busy
171  /*0x00080003*/ ERR_UART_OVERRUN_FRAME_PARITY_NOISE, //overrun err, frame err, parity err, RxNoise err
172  /*0x00080004*/ ERR_UART_UNDERRUN, //underrun err
173  /*0x00080005*/ ERR_UART_PARAM, //parameter is error
174  /*0x00080006*/ ERR_UART_BAUDRATE, //baudrate setting is error
175 
176  /* CAN related errors */
177  ERR_CAN_BASE = 0x00090000,
178  /*0x00090001*/ ERR_CAN_BAD_MEM_BUF = ERR_CAN_BASE+1,
179  /*0x00090002*/ ERR_CAN_INIT_FAIL,
180  /*0x00090003*/ ERR_CANOPEN_INIT_FAIL,
181 
182  /* SPIFI Lite API related errors */
183  ERR_SPIFI_LITE_BASE = 0x000A0000,
185  /*0x000A0002*/ ERR_SPIFI_LITE_BUSY,
188  /*0x000A0005*/ ERR_SPIFI_LITE_IN_DMA,
190  /*0x000A0100*/ PENDING_SPIFI_LITE,
191 
192  /* CLK related errors */
193  ERR_CLK_BASE = 0x000B0000,
194  /*0x000B0001*/ ERR_CLK_NOT_IMPL=ERR_CLK_BASE+1,
195  /*0x000B0002*/ ERR_CLK_INVALID_PARAM,
196  /*0x000B0003*/ ERR_CLK_INVALID_SLICE,
197  /*0x000B0004*/ ERR_CLK_OUTPUT_GEN,
198  /*0x000B0005*/ ERR_CLK_DIV_SRC,
199  /*0x000B0006*/ ERR_CLK_DIV_VAL,
200  /*0x000B0007*/ ERR_CLK_SRC,
205  /*0x000B000C*/ ERR_CLK_PLL_NO_SOLUTION,
206  /*0x000B000D*/ ERR_CLK_PLL_MIN_PCT,
207  /*0x000B000E*/ ERR_CLK_PLL_MAX_PCT,
208  /*0x000B000F*/ ERR_CLK_OSC_FREQ,
209  /*0x000B0010*/ ERR_CLK_CFG,
210  /*0x000B0011*/ ERR_CLK_TIMEOUT,
211  /*0x000B0012*/ ERR_CLK_BASE_OFF,
212  /*0x000B0013*/ ERR_CLK_OFF_DEADLOCK,
213 
214  /*Power API*/
215  ERR_PWR_BASE = 0x000C0000,
218  /*0x000C0003*/ PWR_ERROR_INVALID_STATE,
219  /*0x000C0004*/ PWR_ERROR_INVALID_CFG,
220  /*0x000C0005*/ PWR_ERROR_PVT_DETECT,
221 
222  /* DMA related errors */
223  ERR_DMA_BASE = 0x000D0000,
224  /*0x000D0001*/ ERR_DMA_ERROR_INT=ERR_DMA_BASE+1,
225  /*0x000D0002*/ ERR_DMA_CHANNEL_NUMBER,
226  /*0x000D0003*/ ERR_DMA_CHANNEL_DISABLED,
227  /*0x000D0004*/ ERR_DMA_BUSY,
228  /*0x000D0005*/ ERR_DMA_NOT_ALIGNMENT,
229  /*0x000D0006*/ ERR_DMA_PING_PONG_EN,
231  /*0x000D0008*/ ERR_DMA_PARAM,
232  /*0x000D0009*/ ERR_DMA_QUEUE_EMPTY,
233  /*0x000D000A*/ ERR_DMA_GENERAL,
234 
235  /* SPI related errors */
236  ERR_SPI_BASE = 0x000E0000,
237  /*0x000E0000*/ ERR_SPI_BUSY=ERR_SPI_BASE,
238  /*0x000E0001*/ ERR_SPI_RXOVERRUN,
239  /*0x000E0002*/ ERR_SPI_TXUNDERRUN,
240  /*0x000E0003*/ ERR_SPI_SELNASSERT,
241  /*0x000E0004*/ ERR_SPI_SELNDEASSERT,
242  /*0x000E0005*/ ERR_SPI_CLKSTALL,
243  /*0x000E0006*/ ERR_SPI_PARAM,
244  /*0x000E0007*/ ERR_SPI_INVALID_LENGTH,
245 
246  /* ADC related errors */
247  ERR_ADC_BASE = 0x000F0000,
248  /*0x000F0001*/ ERR_ADC_OVERRUN=ERR_ADC_BASE+1,
249  /*0x000F0002*/ ERR_ADC_INVALID_CHANNEL,
250  /*0x000F0003*/ ERR_ADC_INVALID_SEQUENCE,
251  /*0x000F0004*/ ERR_ADC_INVALID_SETUP,
252  /*0x000F0005*/ ERR_ADC_PARAM,
253  /*0x000F0006*/ ERR_ADC_INVALID_LENGTH,
254  /*0x000F0007*/ ERR_ADC_NO_POWER,
255 
256  /* Debugger Mailbox related errors */
257  ERR_DM_BASE = 0x00100000,
258  /*0x00100001*/ ERR_DM_NOT_ENTERED=ERR_DM_BASE+1,
259  /*0x00100002*/ ERR_DM_UNKNOWN_CMD,
260  /*0x00100003*/ ERR_DM_COMM_FAIL
261 
262 } ErrorCode_t;
263 
264 #ifndef offsetof
265 #define offsetof(s, m) (int) &(((s *) 0)->m)
266 #endif
267 
268 #define COMPILE_TIME_ASSERT(pred) switch (0) { \
269  case 0: \
270  case pred:; }
271 
272 #endif /* __LPC_ERROR_H__ */