I.MX6Q

I.MX6Q_BDC

  1. Quad ARM Cortex A9 Core

      • Efficient and high-performance code execution
      • Operating System and user applications (including control over hardware accelerators and non-accelerated functions)
      • up to 1.2Ghz (consumer version), 1Ghz (automotive) and 800Mhz (Industrial)
      • Trustzone Enabled
      • For full information visit: Cortex-A9 Processor
  2. Cache

      • 32 Kbyte L1 Instruction Cache
      • 32 Kbyte L1 Data Cache
  3. NEON/VFP per Core

      • Neon Coprocessor
      • SIMD Media Processing Architecture
      • NEON register file with 32, 64-bit general-purpose registers
      • NEON integer execution pipeline (ALU, Shift, MAC)
      • Vector Floating Point (VFP) co-processor
      • VFP engine for full execution of the VFPv3 data-processing instruction set
  4. PTM per Core

      • Embedded Trace Macrocell
      • For tracing CPU activity
      • Filtering and triggering resources
  5. 1MB L2-Cache

      • 1MB unified L2 Cache with coherency across all cores
  6. Secure JTAG

      • JTAG Controller (SJC)
      • Protects JTAG from debug port attacks by regulating or blocking access to the system debug features
      • Provides four different JTAG security modes that can be selected via e-fuse configuration
  7. PLL, Osc.

      • Four (x4) PLLs used to generate three source clocks
  8. Clock Reset

      • System Reset Controller (SRC)
      • Clock Control Module (CCM)
      • Crystal oscillator source support
      • Frequency Pre-multiplier (FPM)
  9. Smart DMA

      • Smart DMA enables data transfer between non-mastering peripherals and external or internal memories
      • Burst-capable port for direct external memory access
      • Trace buffer and context dump
  10. IOMUX

      • Significant number of muxable GPIOs and alternate function pins
  11. Timer x 3

      • GPT is a 32 bit up-counter whose value can be captured in a register using an event on an external pin triggered on rising and/or falling edge.
      • 2x Enhanced Periodic Interrupt Timer (EPIT)
        • 32-bit set-and-forget timer which begins counting after the EPIT is enabled by software
        • Capable of providing precise interrupts at regular intervals with minimal processor intervention
  12. PWM x4

      • 4x Pulse Width Modulators (PWM) with a 16-bit counter.
  13. Watch Dog x 2

      • Watch Dog timer (WDOG) supports two comparison points during each counting period.
      • Each comparison point is configurable to evoke an interrupt to the ARM core, and a second point evokes an external event on the WDOG line.
  14. Power Management

      • On-chip, high efficiency power distribution network
      • Enables option of minimizing external voltage sources for more efficient board designs
      • Fully capable of dynamic voltage and frequency scaling
      • Multiple low power modes for reduced power consumption
  15. Power Supplies

      • Choice of using onboard LDOs or use in bypass mode with an external PMIC
  16. Temperature Monitor

      • On-chip temperature sensor with high, low and mid watermark capabilities
      • Ability to generate interuppt to system upon reaching a high temperature mark and take appropriate action
  17. ROM

      • Boot ROM including HAB memory
  18. RAM

      • Unified Internal RAM (256 KB)
  19. RNG

      • On-chip Random Number Generator
  20. TrustZone

      • ARM TrustZone (TZ) Trusted Execution environment including the TZ architecture (separation of interrupts, memory mapping, etc.)
      • TrustZone Watchdog (TZ WDOG)
  21. Ciphers

  22. Security Control

      • Advanced High Assurance Boot (A-HAB) System (HAB with embedded enhancements)
      • SHA-256, 2048-bit RSA key
      • Version control mechanism
      • Warm boot
      • CSU and TZ initialization
      • IC Identification Module (IIM) and Central Security Unit (CSU)
      • CSU enhanced for the IIM
      • Configured during boot and by e-fuses
      • Determines the security level operation mode and the TZ policy
      • Tamper Detection
  23. SRTC

      • Secure Real Time Clock (SRTC)
      • Tamper-resistant RTC with its own power domain and mechanism to detect voltage and clock glitches
  24. eFuses

      • On-chip One-Time programmable electrical fuse array (E-Fusebox)
  25. Multimedia

      • Up to four simultaneous displays
        • Two parallel ports - up to 24-bit interfaces
      • 2x LVDS controllers
      • 1x HDMI 1.4 output
      • 1x MIPI DSI output (2 lanes, 1Ghz each)
      • MIPI CSI input (4 lanes, 1 Ghz each)
      • Audio
        • Audio codecs are provided by software, which runs on ARM core
        • 4x SSIs
        • SPDIF Tx
  26. 3D

      • 3D Graphics Processing Unit (GPU)
      • OpenGL ES Common Profile v1.0
      • OpenGL ES Common Profile v1.1/Direct3D Mobile
      • OpenGL ES Profile v2.0
      • OpenGL ES Profile v3.0
      • OpenCL v1.0
  27. 2D

      • 2D Graphics Processing Unit (GPU2D) provides hardware acceleration for 2D graphic algorithms with sufficient processor power to run desk-top quality interactive graphics applications
  28. Vector Graphics

      • Vector graphics acceleration via separate OpenVG unit
  29. Video Codecs 1080p30 enc/Dec

      • Video Processing Unit (VPU) (HW-implemented video codecs unless mentioned otherwise):
        • MPEG-4 decode: 1080p, 30 fps, Simple Profile and Advanced Simple Profile
        • MPEG-4 encode: 1080p, Simple Profile
        • H.263 decode: 1080p, Profile P0/P3
        • H.263 encode: 1080p, Profile P0/P3
        • H.264 decode: 1080p60, Baseline, Main, and High Profile
        • H.264 encode:1080p, Baseline
      • H.264 MVC SHP Decode: 1080p30fps
        • MPEG-2 decode: 1080p, MP/HP-ML
        • VC-1 decode: 1080p, Simple, Main, and Advanced Profile-L3
        • DivX decode: 1080p, Versions 3, 4, 5 and 6
        • MJPEG® decode: 8k x 8k, 120MPel/s
        • MJPEG encode: 8k x 8k, 160MPel/s
      • VP8 Decode: 720p
      • AVS: 1080p, Jizhun Profile
      • h.264 MVC SHP Decode: 1080p30fps
  30. Audio ASRC

  31. Image Processing Unit

      • Image Processing Unit-IPU
      • Connectivity to displays, display controllers, and auxiliary graphics co-processors
      • Display Processing: video/graphics combining, image enhancement
      • Image conversions: resizing, rotation/inversion, color conversion
      • Synchronization and control capabilities, allowing autonomous operation
  32. Resizing and Blending

      • Fully flexible higher/lower resizing ratio
      • Independent horizontal and vertical resizing ratios
  33. Inversion and Rotation

      • Performs any combination of:
        • 90-degree rotation
        • Horizontal mirroring
        • Vertical mirroring
  34. Image Enhancement

      • Contrast and brightness adjustment
      • Color adjustment and gamut mapping
      • Gamma correction
      • Contrast enhancement, sharpening and noise reduction
  35. HDMI and PHY

      • HDMI 1.4 output
      • Integrated PHY
      • CEC ready
      • HDCP ready (specific SKU, contact FSE)
  36. Display & Camera Interface

      • Up to 4 displays with independent content
      • Two independent Camera Sensor ports
      • Camera ports supporting parallel interface or video in supporting BT.656/BT.1120 formats
      • Camera Preview (displaying the input from an image sensor) can be performed completely autonomously
      • Provides support for time-sensitive control signals to the camera
      • 1x HDMI 1.4 output
      • 1x MIPI DSI output (2 lanes/1Ghz)
      • 1x MIP CSI output (4 lanes/1Ghz)
      • 2x LVDS outputs
      • 2x Parallel RGB outputs (24-bit)
  37. MIPI DSI

      • MIPI DSI output (2 lanes, 1Ghz each)
  38. MIPI CSI2

      • MIPI CSI input (4 lanes, 1 Ghz each)
  39. 24-Bit RGB, LVDS (x2)

      • RGB Data of 18 or 24 bits
      • two parallel display ports, each up-to 24-bits
      • Connectivity to displays with LVDS interface
      • used to connect IPU to external LVDS displays
      • two LVDS channels
  40. 20-bit CSI

  41. Connectivity

      • 3.3V IO voltage for seamless integration
  42. MMC 4.4/SD 3.0 x 3

      • 4 MMC/SD3.0/SDIO ports
      • MMC supports up to 8-bit mode (up to 416 Mbps)
  43. eMMC 4.4 SDXC

      • one enhanced port - support 832 Mbps, (8-bit, eMMC 4.4)
  44. UART x 5, 5 Mbps

      • 5x UART - 1 supports 8-bit and 2 support 4-bit (up to 4.0 Mbps each)
      • Each UART supports serial RS-232 NRZ format, and IrDA
      • Each of the UART modules supports the following serial data transmit/receive protocols and configurations:
        • 7 or 8 bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none)
        • Programmable baud rates up to 4 MHz. This is a higher max baud rate relative to the 1.875 MHz, which is stated by the TIA/EIA-232-F standard and previous NXP® UART modules.
        • 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud
        • IrDA 1.0 support (up to SIR speed of 115200 bps)
        • Option to operate as 8-pins full UART, DCE, or DTE
  45. I2C x 3, SPI x5

      • 3x Inter IC Modules (I2C) up to 400 kbps
      • Provides functionality of a standard I2C slave and master
      • Designed to be compatible with the standard Philips I2C bus protocol
  46. ESAI, SSI/I2S x 3

      • Enhanced Serial Audio Interface (ESAI), up to 1.4 Mbps each channel
      • AC97 support
      • Up to 6 transmitters and 4 receivers
      • 3x I2S/SSI/AC97 (up to 1.4 Mbps each)
      • SSI provides:
        • Full-duplex synchronous interface
        • Connectivity with off-chip audio peripherals
        • Supports SSI normal, SSI network, I2S, and AC-97, bit depths up to 24 bits per word
        • Clock/frame sync options
        • Two pairs of 8x24 FIFOs per SSI
        • Hardware support for an external DMA controller to minimize impact on system performance
        • Second pair of FIFOs provides hardware interleaving of a second audio stream
  47. 3.3V GPIO

      • GPIO with interrupt capabilities
      • Most non-analog and non-DDR pins configurable as GPIO (bidirectional, general-purpose input and output signals)
  48. Keypad

      • Key Pad Port (KPP)
      • Supports up to an 8 x 8 external key pad matrix
  49. SATA and PHY 3 Gbps

      • serial-ATA to interface with hard disk drives
      • SATA II, 1.5 Gbps
      • SATA controller and PHY
      • Integrated PHY/Transceiver, Serial FS (requires external transceiver)
  50. USB2 OTG and PHY, USB2 Host and PHY

      • USB 2.0
      • USB 2.0 OTG with support for overcurrent and PM signals (up to 480 Mbps)
      • Integrated PHY/Transceiver, Serial FS (requires external transceiver)
      • Supports external HS/FS transceivers (ULPI / Serial)
      • USB 2.0
      • 1x USB 2.0 HOST
  51. USB2 HSIC Host x2

      • 2x USB 2.0 HSIC (up to 480 Mbps each)
  52. MIPI HSI

      • 1x MIPI HSI
      • Compatible with the MIPI_HSI specification version1.0 & MIPI_HSI Physical Layer v1.01.00 specification
  53. S/PDIF Tx/Rx

      • 1x SPDIF Transmitter
      • 1x SPDIF Receiver
      • IEC60958 standard, consumer format
      • SPDIF channel status (CS) and User (U) data support
  54. PCIe 2.0 (1-Lane)

      • 1x PCIe 2.0, 1-lane port up to 5Gbps
      • Supports Dual Mode (DM), Root Complex (RC), and Express Endpoint (EP)
  55. Flex CAN x2 / MLB150 + DTCP

      • 2x FlexCAN supporting CAN 2.0B specification
      • 1x MLB150 (150Mbps), 3-pin or 6-pin support with Digital Transmission Content Protection (DTCP) support (specific SKU)
  56. 1 GB Ethernet + IEEE 1588

      • 10/100 Ethernet Support
      • 1Gb Ethernet support with IEEE 1588 support via 3rd party driver
      • Support SNI, MII, RMII and RGMII interfaces to an external PHY.
  57. NAND Cntrl. (BCH40)

      • SLC/MLC support
      • Up to 40 bit ECC support (MLC)
      • 1.65 … 3.6V supply range
      • Boot able
  58. LP-DDR2/DDR3/LV-DDR3x32/64, 533 MHz

      • 64-bit DDR3-533Mhz (1066MTPS)
      • 64-bit DDR3L-533Mhz (1066MTPS)
      • 2x 32bit LPDDR2 533Mhz (1066MTPS) with channel interleaving