Use the Program MATT page ( Figure 1) to define and display program memory-space mappings (virtual-to-physical address mappings) for the StarCore DSP. The MMU configurator generates the appropriate descriptors for the program memory-address translation table (MATT).
Each memory-space mapping has a corresponding entry in the list on the left-hand side of the Program MATT page. Each entry shows an abbreviated expression which summarizes the settings on the right-hand side of the page. A plus sign to the left of an entry indicates an enabled mapping, and a minus sign indicates a disabled mapping.
To change an entry, select it from the left-hand side of the page, then use the Address, Size, and Properties settings to specify options that the MMU configurator verifies as a group. Click the Change button to assign the specified options to the selected entry. To cancel your changes, select another entry from the left-hand side of the page, without clicking the Change button.
The following table explains each option on the Program MATT page.
| Option | Explanation |
|---|---|
| Virtual | Enter the virtual base address of the program segment. This option corresponds to the Program Segment Virtual Base Address and Size (PSVBAS) bits of the Program Segment Descriptor Registers A (M_PSDAx) that configure the virtual base address. |
| Physical | Enter the most-significant part of the physical address to use for translation. This option corresponds to the Data Segment Physical Base Address (DSPBA) bits of the Data Segment Descriptor Registers B (M_DSDBx)." |
| Size | Specify the PMATT Units number in Number box. Select the PMATT Units type from the Type pop-up menu: B, KB, MB, GB |
| Permissions | Specify whether to share the program segment. This option corresponds to the System/Shared Virtual Program Memory (SSVPM) bit of the Program Segment Descriptor Registers A (M_PSDAx). |
| Burst | Specify the number of transactions (beats) on the bus that the bus controller cannot interrupt. This burst size applies in the region to a cacheable segment. This option corresponds to the Program Burst Size (PBS) bits of the Program Segment Descriptor Registers B (M_PSDBx). |
| L2 Cache Policy | Determines the cache policy for the L2 cache for accesses from the core through L1 Instruction cache: Cacheable, NonCacheable, and Reserved. The pop-up menu has two Reserved values.This is because the L2 Cache Policy Values is stored on 2 bits so they are 4 possible values (2 valid and 2 reserved). Every entry in the combo box corresponds to a combination of bits. |
| Cacheable | Selected - Allows caching of the segment in instruction cache. Deselected - Disables caching of the segment in instruction cache. This checkbox corresponds to the Instruction Cacheability (IC) bit of the Program Segment Descriptor Registers A (M_PSDAx). |
| PAPS | Selected-The segment has supervisor-level fetch permission for program accesses. If you select the PAPU checkboxas well, you disable program-protection checks for this segment. Deselected - The segment does not have supervisor-level fetch permission for program accesses. This checkbox corresponds to the Program Access Permission in Supervisor Level (PAPS) bit of the Program Segment Descriptor Registers A (M_PSDAx). |
| Entry Enabled | Selected - The MMU enables this mapping entry. Deselected - The MMU disables this mapping entry. |
| PAPU | Selected - The segment has user-level fetch permission for program accesses. If you select the PAPS checkbox as well, you disable program-protection checks for this segment. Deselected - The segment does not have user-level fetch permission for program accesses. This checkbox corresponds to the Program Access Permission in User Level (PAPU) bit of the Program Segment Descriptor Registers A (M_PSDAx). |
| Prefetch Line | Selected - Allows the fetch unit's program-line pre-fetch to a segment cacheable in instruction cache. Deselected - Disables the fetch unit's program-line prefetch to a segment cacheable in instruction cache. This checkbox corresponds to the Program Pre-fetch Line Enable (PPFE) bit of the Program Segment Descriptor Registers B (M_PSDBx). |
| Program Next Line Prefetch | Selected - Allows the fetch unit's program next line pre-fetch mechanism to an ICache cacheable segment. Deselected - Enables the fetch unit's program next line pre-fetch mechanism to an ICache cacheable segment. |
The PMATT Table page ( Figure 2) shows an alternate, tabular rendering of the settings that you specify on the Program MATT page. Use this page to view the configuration of all Program MATT mappings. The MMU configurator uses the settings that you specify on the Program MATT page to generate the column headers of this page. The table data shows the validated records for each Program MATT entry. You can resize the table columns to hide columns or view the larger data fields. A plus sign ( + ) in a table cell represents a selected checkbox in the associated Program MATT configuration page.
