Controls optimization for e500 and e200 cores that support SPE vectors.
#pragma spill_to_spe on | off | reset
In complex functions, sometimes the compiler is not able to color all registers without spilling to the stack. The new optimization takes advantage of the unused high half of the gpr vectors as storage and therefore avoids loading and storing to the stack.
The optimization is off by default, unless the optimization level is 3 and higher.