Variable Length Encoding

The Variable Length Encoding (VLE) instruction set architecture is an extension to the instruction set specified in Freescale Semiconductor's Book E Implementation Standard (EIS) for Power Architecture processors. This instruction set adds a few identically operating counterparts to the regular EIS instruction set. But where regular EIS instructions occupy 32 bits and must be aligned to 32-bit boundaries, VLE instructions are either 16 or 32 bits long and can be aligned to 16-bit boundaries. This extra flexibility in instruction encoding and alignment allows the compiler and linker to greatly compress the size of runtime object code with only a small penalty in execution performance.

These topics describe how and when to configure the build tools to generate VLE object code:

• Processors With VLE Capability
  Not all Power Architecture processors have VLE capability.
• Compiling VLE Instructions
  Controlling VLE (Variable Length Encoding) code generation.
• Assembling VLE Instructions
  Assembling VLE instructions
• Linking VLE Object Code
  A processor capable of executing VLE (Variable Length Encoding) instructions must use separate memory pages for VLE and regular instructions.