Support of clock configurations in embedded components

As described in Clock configuration topic, particular system timing scheme, which is defined as reference clock source selection and settings, clock processing settings (for example, configuration of a PLL circuit) and value of main system clocks (such as internal peripherals bus clock), is in Processor Expert represented as a clock configuration and is configured in CPU (processor) component. In case of embedded components that encapsulate timing features derived from the system timing, Processor Expert also ensures that component timing settings are valid and consistent with the clock configuration.Unlike other clock configurations, Clock Configuration 0 has some specific features:

Note: As mentioned in Clock Configuration 0 topic, the Peripheral Initialization Components (see Levels of abstraction topic) support only Clock Configuration 0. Therefore, following part of documentation generally applies to Logical Device Driver (LDD) components and High Level Components (although implementation of described features slightly differs in case of high-level components as they operate with legacy speed modes conventions).

The following table shows number of supported clock configurations for each category of embedded component.

Component category	Clock configurations	Note
Peripheral Initialization	1	Clock configuration 0
High-level	3	Speed modes
LDD	8

There are two main clock configuration features available in embedded components: