The write-through operation inculdes:
- A write-through read miss on the input bus causes a line read on the output bus of a 16-byte-aligned memory address containing the desired address. This data is loaded into the cache and is marked as valid and not modified.
- A write-through read hit to a valid cache location returns data from the cache with no output bus access.
- A write-through write miss bypasses the cache and writes to the output bus without allocating and fetching the corresponding line into the cache (no allocate on write miss policy)
- A write-through write hit updates the cache hit data and writes to the output bus.