Target Processor

Use the Target Processor panel to specify the processor family for the project. The properties specified on this page are also used by the build tools (compiler, linker, and assembler).

The table below lists and describes the various options available on the Target Processor panel.

Table 1. Tool Settings - Target Processor
Option Description
Processor Use to specify the target processor architecture. The debugger configures the appropriate register views according to the target processor that you specify.
Thumb (-mthumb) Check to have the processor generate Thumb code instructions.
Thumb interwork (-mthumb-interwork) Check this option if you are writing ARM code that you want to interwork with Thumb code, or Thumb code that you want to interwork with ARM code. The only functions that need to be compiled for interworking are the functions that are called from the other state. The linker generates suitable interworking veneers when the compiler output is linked.
Endiannes Use to specify the byte order of the target hardware architecture:
  • Big - Select if the target processor uses big-endian (BE) byte order (leftmost bytes are most significant: B3 B2 B1 B0).
  • Little - Select if the target processor uses little-endian (LE) byte order (rightmost bytes are most significant: B0 B1 B2 B3).
Float ABI Specify the floating-point options. The options avaialable are: Toolchain Default, Library (-mfloat -abi=soft), Library with FP (-mfloat-ai=softfp), and FP instructions (-mfloat-abi=hard).
FPU Type From the list box, select the architecture or processor that corresponds to your target hardware.
  • Software-software-based FPU library.
  • FPA-Floating Point Accelerator format and instructions
  • VFP-hardware vector FPU format and instructions compatible with the VFPv1 architecture
  • VFPV2-hardware vector FPU format and instructions compatible with the VFPv2 architecture
The compiler might display error messages or warnings if the selected FPU architecture is not compatible with the target architecture.