The following table presents an overview of the instructions available for HCS12Z. The operands are described in the chapter Symbols and Notation.
| Instruction | Addressing modes | Descriptions |
|---|---|---|
| ABS Di | Inherent | Absolute Value |
ADC Di,#oprimmsz ADC Di,oprmemreg |
IMM 1/2/4 OPR 1/2/3 |
Add with Carry |
ADD Di,#oprimmsz ADD Di,oprmemreg |
IMM 1/2/4 OPR 1/2/3 |
Add without Carry |
ADD Di,#oprimmsz ADD Di, oprmemreg |
IMM 1/2/4 OPR 1/2/3 |
Bitwise AND |
| ANDCC #opr8i | IMM1 | Bitwise AND CCL with Immediate |
ASL Dd,Ds,Dn ASL Dd,Ds,#opr5i ASL Dd,Ds,oprmemreg ASL.bwpl Dd,oprmemreg,#opr5i ASL.bwpl Dd,oprmemreg,oprmemreg ASL Di,#opr1i ASL.bwpl oprmemreg,#opr1i |
REG-REG REG-IMM (1-bit, or 5-bit) REG-OPR/1/2/3 OPR/1/2/3-IMM (1-bit, or 5-bit) OPR/1/2/3-OPR/1/2/3 REG-IMM (2-operand) OPR/1/2/3-IMM (2-operand) |
Arithmetic Shift Left |
ASR Dd,Ds,Dn ASR Dd,Ds,#opr5i ASR.bwpl Dd,oprmemreg,#opr5i ASR.bwpl Dd,oprmemreg,oprmemreg ASR.bwpl oprmemreg,#opr1i |
REG-REG REG-IMM OPR/1/2/3-IMM OPR/1/2/3-OPR/1/2/3 OPR/1/2/3-IMM |
Arithmetic Shift Right |
| BCC oprdest | REL | Branch if Carry Clear |
| BCLR Di,#opr5iBCLR Di,DnBCLR.bwl oprmemreg,#opr5iBCLR.bwl oprmemreg,Dn | REG-IMM REG-REG OPR/1/2/3-IMM OPR/1/2/3-REG |
Test and Clear Bit |
| BCS oprdest | REL | Branch if Carry Set |
| BEQ oprdest | REL | Branch if Equal |
| BFEXT Dd,Ds,DpBFEXT Dd,Ds,#width:offset BFEXT.bwplDd,oprmemreg,Dp BFEXT.bwploprmemreg,Ds,Dp BFEXT.bwplDd,oprmemreg,#width:offset BFEXT.bwploprmemreg,Ds,#width:offset | REG-REG-REG REG-REG-IMM REG-OPR/1/2/3-REG OPR/1/2/3-REG-REG REG-OPR/1/2/3-IMM OPR/1/2/3-REG-IMM |
Bit Field Extract |
| BFINS Dd,Ds,DpBFINS Dd,Ds,#width:offset BFINS.bwplDd,oprmemreg,Dp BFINS.bwploprmemreg,Ds,Dp BFINS.bwplDd,oprmemreg,#width:offset BFINS.bwploprmemreg,Ds,#width:offset | REG-REG-REG REG-REG-IMM REG-OPR/1/2/3-REG OPR/1/2/3-REG-REG REG-OPR/1/2/3-IMM OPR/1/2/3-REG-IMM |
Bit Field Insert |
| BGE oprdest | REL | Branch if greater than or equal to |
| BGND | INH | Enter background debug mode |
| BGT oprdest | REL | Branch if greater than |
| BHI oprdest | REL | Branch if higher |
| BHS oprdest | REL | Branch if higher or same |
| BIT Di,#oprimmszBIT Di,oprmemreg | IMM1/2/4 OPR/1/2/3 |
Bit Test |
| BLE oprdest | REL | Branch if less than or equal to |
| BLO oprdest | REL | Branch if lower |
| BLSoprdest | REL | Branch if lower or same |
| BLT oprdest | REL | Branch if less than |
| BMI oprdest | REL | Branch if Minus |
| BNE oprdest | REL | Branch if Not Equal |
| BPL oprdest | REL | Branch if Plus |
| BRA oprdest | REL | Branch always |
BRCLR Di,#opr5i,oprdest BRCLR Di,Dn,oprdest BRCLR.bwloprmemreg,#opr5i, oprdest BRCLR.bwloprmemreg,Dn,oprdest |
REG-IMM-REL REG-REG-REL OPR/1/2/3-IMM-REL OPR/1/2/3-REG-REL |
Test Bit and Branch if Clear |
BRSET Di,#opr5i,oprdest BRSET Di,Dn,oprdest BRSET.bwloprmemreg,#opr5i,oprdest BRSET.bwloprmemreg,Dn,oprdest |
REG-IMM-REL REG-REG-REL OPR/1/2/3-IMM-REL OPR/1/2/3-REG-REL |
Test Bit and Branch if set |
BSET Di,#opr5i BSET Di,Dn BSET.bwl oprmemreg,#opr5i BSET.bwl oprmemreg,Dn |
REG-IMM REG-REG OPR/1/2/3-IMM OPR/1/2/3-REG |
Test and Set Bit |
| BSR oprdest | REL | Branch to subroutine |
BTGL Di,#opr5i BTGL Di,Dn BTGL.bwploprmemreg,#opr5i BTGL.bwploprmemreg,Dn |
REG-IMM REG-REG OPR/1/2/3-IMM OPR/1/2/3-REG |
Test and Toggle Bit |
| BVC oprdest | REL | Branch if overflow clear |
| BVS oprdest | REL | Branch if overflow set |
| CLB cpureg-cpureg | REG-REG | Count leading bits |
| CLC | IMM1 | Clear Carry (Translates to ANDCC #$FE) |
| CLI | IMM1 | Clear Interrupt Mask (Translates to ANDCC #$EF) |
| CLR.bwpl oprmemreg CLR Di CLR X CLR Y | OPR/1/2/3 INH INH INH |
Clear Memory, Register, or Index Register |
| CLV | IMM1 | Clear Overflow (Translates to ANDCC #$FD) |
| CMP Di,#oprimmszCMP Di,oprmemreg CMP xy,#opr24i CMP xy,oprmemreg CMP S,#opr24i CMP S,oprmemreg CMP X,Y | IMM1/2/4 OPR/1/2/3 IMM3 OPR/1/2/3 IMM3 OPR/1/2/3 INH |
Compare |
| COM.bwl oprmemreg | OPR/1/2/3 | Complement memory |
DBcc Di,oprdest DBcc X,oprdest DBcc Y,oprdest DBcc.bwploprmemreg,oprdest |
REG-REL REG-REL REG-REL OPR/1/2/3-REL |
Decrement and Branch |
DEC Di DEC.bwl oprmemreg |
INH OPR/1/2/3 |
Decrement |
| DIVS Dd,Dj,Dk DIVS.B Dd,Dj,#opr8i DIVS.W Dd,Dj,#opr16i DIVS.L Dd,Dj,#opr32i DIVS.bwl Dd,Dj,oprmemreg DIVS.bwplbwplDd,oprmemreg,oprmemreg | REG-REG REG-IMM1 REG-IMM2 REG-IMM4 REG-OPR/1/2/3 OPR/1/2/3-OPR/1/2/3 |
Signed Divide |
DIVU Dd,Dj,Dk DIVU.B Dd,Dj,#opr8i DIVU.W Dd,Dj,#opr16i DIVU.L Dd,Dj,#opr32i DIVU.bwl Dd,Dj,oprmemreg DIVU.bwplbwplDd,oprmemreg,oprmemreg |
REG-REG REG-IMM1 REG-IMM2 REG-IMM4 REG-OPR/1/2/3 OPR/1/2/3-OPR/1/2/3 |
Unsigned divide |
EOR Di,#oprimmsz EOR Di,oprmemreg |
IMM1/2/4 OPR/1/2/3 |
Exclusive OR |
| EXG cpureg,cpureg | INH | Exchange register contents |
INC Di INC.bwl oprmemreg |
INH OPR/1/2/3 |
Increment |
JMP opr24a JMP oprmemreg |
EXT3 OPR/1/2/3 |
Jump |
JSR opr24a JSR oprmemreg |
EXT3 OPR/1/2/3 |
Jump to subroutine |
LD Di,#oprimmsz LD Di,opr24a LD Di,oprmemreg LD xy,#opr18i LD xy,#opr24i LD xy,opr24a LD xy,oprmemreg LD S,#opr24i LD S,oprmemreg |
IMM1/2/4 (same size as Di) EXT3 (24-bit address) OPR/1/2/3 IMM2 (efficient 18-bit) IMM3 (same size as X or Y) EXT3 (24-bit address) OPR/1/2/3 IMM3 (same size as SP) OPR/1/2/3 |
Load (Di, X,Y, or SP) |
LEA D67,oprmemreg LEA S,oprmemreg LEA xy,oprmemreg LEA S,(#opr8i,S) LEA xy,(#opr8i,xy) |
OPR/1/2/3 OPR/1/2/3 OPR/1/2/3 IMM1 (8-bit signed offset) IMM1 (8-bit signed offset) |
Load Effective Address |
LSL Dd,Ds,Dn LSL Dd,Ds,#opr5i LSL.bwpl Dd,oprmemreg,#opr5i LSL.bwpl Dd,oprmemreg,oprmemreg LSL.bwpl oprmemreg,#opr1i |
REG-REG REG-IMM OPR/1/2/3-IMM OPR/1/2/3-OPR/1/2/3 OPR/1/2/3-IMM |
Logical Shift Left |
LSR Dd,Ds,Dn LSR Dd,Ds,#opr5i LSR.bwpl Dd,oprmemreg,#opr5i LSR.bwpl Dd,oprmemreg,oprmemreg LSR.bwpl oprmemreg,#opr1i |
REG-REG REG-IMM OPR/1/2/3-IMM OPR/1/2/3-OPR/1/2/3 OPR/1/2/3-IMM |
Logical Shift Right |
MACS Dd,Dj,Dk MACS.B Dd,Dj,#opr8i MACS.W Dd,Dj,#opr16i MACS.L Dd,Dj,#opr32i MACS.bwl Dd,Dj,oprmemreg MACS.bwplbwplDd,oprmemreg,oprmemreg |
REG-REG REG-IMM1 REG-IMM2 REG-IMM4 REG-OPR/1/2/3 OPR/1/2/3-OPR/1/2/3 |
Signed Multiply and Accumulate |
MACU Dd,Dj,Dk MACU.B Dd,Dj,#opr8i MACU.W Dd,Dj,#opr16i MACU.L Dd,Dj,#opr32i MACU.bwl Dd,Dj,oprmemreg MACU.bwplbwplDd,oprmemreg,oprmemreg |
REG-REG REG-IMM1 REG-IMM2 REG-IMM4 REG-OPR/1/2/3 OPR/1/2/3-OPR/1/2/3 |
Unsigned multiply and accumulate |
| MAXS Di,oprmemreg | OPR/1/2/3 | Maximum of two signed values to Di |
| MAXU Di,oprmemreg | OPR/1/2/3 | Maximum of two unsigned values to Di |
| MINS Di,oprmemreg | OPR/1/2/3 | Minimum of two signed values to Di |
| MINU Di,oprmemreg | OPR/1/2/3 | Minimum of two unsigned values to Di |
MODS Dd,Dj,Dk MODS.B Dd,Dj,#opr8i MODS.W Dd,Dj,#opr16i MODS.L Dd,Dj,#opr32i MODS.bwl Dd,Dj,oprmemreg MODS.bwplbwplDd,oprmemreg,oprmemreg |
REG-REG REG-IMM1 REG-IMM2 REG-IMM4 REG-OPR/1/2/3 OPR/1/2/3-OPR/1/2/3 |
Signed Modulo |
MODU Dd,Dj,Dk MODU.B Dd,Dj,#opr8i MODU.W Dd,Dj,#opr16i MODU.L Dd,Dj,#opr32i MODU.bwl Dd,Dj,oprmemreg MODU.bwplbwplDd,oprmemreg,oprmemreg |
REG-REG REG-IMM1 REG-IMM2 REG-IMM4 REG-OPR/1/2/3 OPR/1/2/3-OPR/1/2/3 |
Unsigned Modulo |
MOV.B #opr8i,oprmemreg MOV.W #opr16i,oprmemreg MOV.P #opr24i,oprmemreg MOV.L #opr32i,oprmemreg MOV.bwpl oprmemreg,oprmemreg |
IMM1-OPR/1/2/3 IMM2-OPR/1/2/3 IMM3-OPR/1/2/3 IMM4-OPR/1/2/3 OPR/1/2/3-OPR/1/2/3 |
Move Data (8, 16, 24, or 32-bits; IMM-OPR or OPR-OPR) |
MULS Dd,Dj,Dk MULS.B Dd,Dj,#opr8i MULS.W Dd,Dj,#opr16i MULS.L Dd,Dj,#opr32i MULS.bwl Dd,Dj,oprmemreg MULS.bwplbwplDd , oprmemreg,oprmemreg |
REG-REG REG-IMM1 REG-IMM2 REG-IMM4 REG-OPR/1/2/3 OPR/1/2/3-OPR/1/2/3 |
Signed Multiply |
MULU Dd,Dj,Dk MULU.B Dd,Dj,#opr8i MULU.W Dd,Dj,#opr16i MULU.L Dd,Dj,#opr32i MULU.bwl Dd,Dj,oprmemreg MULU.bwplbwplDd,oprmemreg,oprmemreg |
REG-REG REG-IMM1 REG-IMM2 REG-IMM4 REG-OPR/1/2/3 OPR/1/2/3-OPR/1/2/3 |
Unsigned multiply |
| NEG.bwl oprmemreg | OPR/1/2/3 | Two's complement negate |
| NOP | INH | Null operation |
OR Di,#oprimmsz OR Di,oprmemreg |
IMM1/2/4 OPR/1/2/3 |
Bitwise OR |
| ORCC #opr8i | IMM1 | Bitwise OR with CCL Immediate |
PSH oprregs1 PSH oprregs2 PSH ALL PSH ALL16b |
INH INH INH INH |
Push registers onto stack |
PUL oprregs1 PUL oprregs2 PUL ALL PUL ALL16b |
INH INH INH INH |
Pull registers from stack |
QMULS Dd,Dj,Dk QMULS.B Dd,Dj,#opr8i QMULS.W Dd,Dj,#opr16i QMULS.L Dd,Dj,#opr32i QMULS.bwl Dd,Dj,oprmemreg QMULS.bwplbwpl Dd,oprmemreg,oprmemreg |
REG-REG REG-IMM1 REG-IMM2 REG-IMM4 REG-OPR/1/2/3 OPR/1/2/3-OPR/1/2/3 |
Signed Fractional multiply |
QMULU Dd,Dj,Dk QMULU.B Dd,Dj,#opr8i QMULU.W Dd,Dj,#opr16i QMULU.L Dd,Dj,#opr32i QMULU.bwl Dd,Dj,oprmemreg QMULU.bwplbwpl Dd,oprmemreg,oprmemreg |
REG-REG REG-IMM1 REG-IMM2 REG-IMM4 REG-OPR/1/2/3 OPR/1/2/3-OPR/1/2/3 |
Unsigned Fractional multiply |
| ROL.bwpl oprmemreg | OPR/1/2/3 | Rotate left through carry |
| ROR.bwpl oprmemreg | OPR/1/2/3 | Rotate right through carry |
| RTI | INH | Return from Interrupt |
| RTS | INH | Return from subroutine |
| SAT Di | INH | Saturate |
SBC Di,#oprimmsz SBC Di,oprmemreg |
IMM1/2/4 OPR/1/2/3 |
Subtract with Borrow |
| SEV | IMM1 | Set Carry Flag (Translates to ORCC #$01) |
| SEI | IMM1 | Set Interrupt Mask (Translates to ORCC #$10) |
| SEV | IMM1 | Set Overflow flag (Translates to ORCC #$02) |
| SEX cpureg,cpureg | INH | Sign extend (smaller CPU register to a larger CPU register) |
ST Di,opr24a ST Di,oprmemreg ST xy,opr24a ST xy,oprmemreg ST S,oprmemreg |
EXT (24-bit address) OPR/1/2/3 EXT (24-bit address) OPR/1/2/3 OPR/1/2/3 |
Store (Di,X,Y or SP) |
| STOP | INH | Stop processing |
SUB Di,#oprimmsz SUB Di,oprmemreg SUB D6,X,Y SUB D6,Y,X |
IMM1/2/4 OPR/1/2/3 INH INH |
Subtract without borrow |
| SWI | INH | Software interrupt |
| SYS | INH | System call software interrupt |
TBcc Di,oprdest TBcc X,oprdest TBcc Y,oprdest TBcc.bwploprmemreg,oprdest |
REG-REL REG-REL REG-REL OPR/1/2/3-REL |
Test and branch |
| TFR cpureg,cpureg | INH | Transfer register contents |
| TRAP #num | INH | Unimplemented Page2 Opcode Trap |
| WAI | INH | Wait for interrupt |
| ZEX cpureg,cpureg | INH | Zero-extend (smaller CPU register to a larger CPU register) |