QuadSPI General Parameters
- Flash Port Connection
Figure 1. Flash Port Connection 
Selects the QuadSPI port on which external flash memory is connected (port A or B). DLLCR, SFLASH_1_SIZE and SFLASH_2_SIZE configured registers are dependent on the port selection (e.g. DLLCRA/DLLCRB).
- DLL Modes
Figure 2. DLL Modes 
- DLL Bypass Mode - Enable DLL Bypass mode based operation in
Phase 2 if above configurations correspond to this phase.
0: Disable
1: Enable
- DLL Auto Update Mode - Enable DLL Auto Update mode based operation in
Phase 2 if above configurations corresponds to this phase.
0: Disable
1: Enable
The two DLL Modes cannot be selected at the same time.
- DLL Bypass Mode - Enable DLL Bypass mode based operation in
Phase 2 if above configurations correspond to this phase.
- IPCR Trigger
Figure 3. IPCR Enable Mode 
Enables the IPCR register in the QuadSPI Registers Table.
- SFLASH Clock Frequency
Figure 4. SFLASH Clock Frequency 
User-provided frequency (in MHz) for Phase 2 QuadSPI configuration. This frequency corresponds to the QSPI_1X_CLK clock.
- Import/Export button
Figure 5. Import/Export buttons 
User can select to import a .bin file that will be applied over the current configuration. User can select to export a .bin or .c file.