Configuration parameters

Following options are available:

  • DDR type - Select between memory types available for selected platform.
  • Clock Cycle Frequency - Predefined frequencies available for current memory type.
    Table 1. DDR mapping
    Clock Cycle Frequency (MHz) Data Transfer Rate (MT/s)
    2400 4800
    3000 6000
    3200 6400
  • Board DDR data rate – Data transfer rate for the clock cycle frequency.
  • Number of ranks - The number of ranks supported by the controller.
  • Number of channels - Can be extracted from DDR memory datasheet. In example is mentioned as 2 channels.
  • DRAM Configuration - The configuration of the memory.
  • PHY ODT Impedance - Select On Die Termination impedance value used by PHY during reads.
  • PHY Drive Strength - Select the driver impedance value used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
  • DRAM ODT Impedance - Select On Die Termination impedance value used by DRAM during writes.
  • DRAM Drive Strength - Select the driver impedance value used by DRAM during reads.
  • Starting location for CS0 - Select the start address of the memory. The value should be in HEX format between "0" and "FF".
  • Enable Inline ECC - Error Correction Code: mechanism to detect (and even correct) errors in data when reading from and writing to DDR memory. When Inline ECC is enabled, for each byte of data 1 additional bit is reserved for the error checking code. This means that only 7/8 of the total DDR memory will be available.
  • PHY log level - controls the verbosity of the log messages provided by PHY which may contain additional information during training: MR register values, CA training, etc.
  • Pin Swizzling - due to various possibilities of routing of DDR memory, CA and DQ lines can be swapped.
    • General rules that apply to DQ swapping:
      1. All values must be unique.
      2. Bit swapping inside a byte (e.g map lines 1 and 4 on a different position inside [8:0])
      3. Byte swapping inside a channel (e.g. lines 1 and 4 can be mapped inside [17:9] lane but cannot be mapped inside [26:18] or [35:27] lanes)
    To mention here that mapping is done from memory perspective, i.e. upper line represents the DDR memory and the lower line represents the MCU.
    • General rules that apply to CA swapping:
      1. All values must be unique.
      2. Bit swapping inside a byte (e.g map lines 1 and 4 on a different position inside [6:0])
    To mention here that mapping is done from memory perspective, i.e. upper line represents the DDR memory CA lines whereas and the lower line represents the corresponding lanes from DFI adress.
  • Save debug messages – Controls whether the generated code will save PHY debug messages at the specified address. Memory dump can be consumed by the tool for decoding the messages received during training.
    Figure 1. Save debug messages