The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage
register and 3-state outputs. Both the shift and storage register have separate clocks.
The device features a serial input (DS) and a serial output (Q7S) to enable cascading
and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the
LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred
to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks
are connected together, the shift register will always be one clock pulse ahead of the
storage register. Data in the storage register appears at the output whenever the output
enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance
OFF-state. Operation of the OE input does not affect the
state of the registers. Inputs include clamp diodes. This enables the use of current
limiting resistors to interface inputs to voltages in excess of VCC.