AltiVec® Execution Unit and Instruction Set Overview


NXP's AltiVec technology expands Power Architecture technology with the addition of a 128-bit vector execution unit, which operates concurrently with the existing integer and floating point units. This engine enables highly parallel operations, allowing for the simultaneous execution of up to 16 operations in a single clock cycle.

AltiVec technology is a short vector parallel architecture. Depending on data size, vectors are 4, 8 or 16 elements long. This can be contrasted with the long vector architectures of supercomputers that were popular in the 1980s. Vector sizes for those machines ranged to hundreds of elements. The long vector approach of supercomputers, while useful for scientific calculations, is not optimal for the communications, multimedia and other performance-driven applications targeted by NXP with AltiVec technology.

AltiVec technology operations are performed on multiple data elements by a single instruction. This is often referred to as SIMD (single instructions, multiple data) parallel processing. AltiVec technology offers support for:

  • 16-way parallelism for 8-bit signed and unsigned integers and characters
  • 8-way parallelism for 16-bit signed and unsigned integers
  • 4-way parallelism for 32-bit signed and unsigned integers and IEEE floating-point numbers

AltiVec technology also includes a separate register file containing 32-entries, each 128 bits wide. These 128-bit wide registers hold the data sources for the AltiVec technology execution units. Registers are loaded and unloaded through vector store and vector load instructions that transfer the contents of a single 128-bit register to and from memory.

AltiVec technology can be most accurately thought of as a set of registers and execution units added to the Power Architecture in an analogous manner to the addition of floating point units. Floating point units were added to most mainstream microprocessor architectures to provide better support for high-precision scientific calculations. AltiVec technology is being added to the Power Architecture to dramatically accelerate the next level of performance-driven, high-bandwidth communications and computing applications.

Each AltiVec instruction specifies up to three source operands and a single destination operand.

Way parallelism for 8-bit signed and unsigned integers and characters

All operands are vector registers, with the exception of the load and store instructions and a few instruction types that provide operands from immediate fields within the instruction. Over 160 instructions are defined for the AltiVec technology featured in e600 core devices and QorIQ T Series processors.