AltiVec addresses high-bandwidth data processing and algorithmic-intensive computations, delivering DSP-level performance for control and data path processing tasks. Benchmarks conducted by the Embedded Microprocessor Benchmark Consortium (EEMBC) have demonstrated 10x performance improvements with AltiVec technology.
QorIQ T Series processors, featuring AltiVec technology, will deliver dramatic performance and energy efficiency boosts for a wide range of applications including the wireless infrastructure, networking, aerospace, military, industrial, robotics, storage, medical, video systems and printing markets.
Traditionally, many high-performance applications have contained a combination of a single microprocessor performing the system control function and off-chip devices based on one or more other architectures, such as a DSP farm or custom ASICs, to perform specialized computations. AltiVec technology enables a class of processors that drives the convergence of these technologies. AltiVec technology provides embedded and computing system designers with a “one part-one code base” approach to product design. Because this integrated solution is still 100% compatible with the industry-standard Power Architecture technology, design and support are simplified, and the development barriers inherent to multiple architecture designs are eliminated. System designers and their customers will benefit through faster time-to-market and lower total system development cost while simultaneously enjoying a tremendous jump in performance.
Announcing the Mentor® Embedded Performance Library for NXP's AltiVec technology. Engineered to help NXP's customers achieve maximum performance benefits of the newest AltiVec engine on the QorIQ T Series processors, while simultaneously boosting the software developer's productivity.
|AltiVec Libraries||Downloadable libraries of AltiVec technology-enabled functions.||zip||54|
|AltiVec Libraries Readme||Readme file||zip||13|
|AltiVec Code Samples||Description||Format||Size|
|AltiVec Complex FIR||Describes an implementation of a complex finite impulse response (FIR) filter for 16-bit data using the AltiVec C/C++ Programming Model.||zip||126|
|AltiVec Real FIR||Describes possible implementations of a real finite impulse response (FIR) filter for 16-bit data using the AltiVec C/C++ Programming Model.||zip||282|
|AltiVec Real Delayed LMS FIR||Describes an implementation of a real delayed least mean squared (LMS) FIR filter. It is coded for 16-bit input data and a 24 tap filter.||zip||104|
|AltiVec and Fixed-Point FFT||Compares the performance of fixed-point Fast Fourier Transform (FFT) with and without AltiVec technology to demonstrate how mathematically-intensive code can be adapted for use with AltiVec and how AltiVec increases code performance.||557|
|AltiVec and Floating-Point FFT||Compares the performance of fast Fourier transform (FFT) with and without AltiVec™ technology to demonstrate how mathematically-intensive code can be adapted for use with AltiVec and how AltiVec increases code performance.||308|
|RGB to YCbCr Color Translation||Describes how to convert 8-bit pixels from the RGB color space to the YCbCr color space using the AltiVec C/C++ Programming Model. It implements the conversion standard as specified in CCIR recommendation 601-2.||zip||138|
|GSM Soft-Decision Viterbi Decoder||Describes an implementation of a Soft-Decision Viterbi decoder for GSM CC(2,1,5) TCH frames. A Soft Decision Viterbi Decoder is used to provide maximum likelihood of decoding a convolutional encoded signal in the presence of noise.||zip||217|
|GSM Convolutional Encoder||Describes a method of encoding a signal to improve its redundancy for transmission purposes using the AltiVec C/C++ Programming Model. The CC(2,1,5) convolutional encoder encodes a binary, half-rate code with a constraint length of five.||zip||219|
|Vectorized Common Math Subroutines||A collection of exemplary implementations of several common math functions (sin/cos, exp/log, sqrt) using AltiVec technology. The current implementation covers only the single-precision floating point version of each function and is intended as a coding example for similar algorithms.||zip||214|
|Sum Of Absolute Differences||Describes an implementation of a Sum of Absolute Differences (SAD) kernel using the AltiVec C/C++ Programming Model. This kernel is used extensively in motion estimation algorithms in the video standards.||zip||134|
|2D Discrete Cosine Transform||Describes an implementation of two dimensional Discrete Cosine Transform using the AltiVec C/C++ Programming Model for 8x8 16-bit input. It is used in video image compression algorithms.||zip||241|
|2D Inverse Discrete Cosine Transform||Describes an implementation of two dimensional Inverse Discrete Cosine Transform using the AltiVec C/C++ Programming Model for 8x8 16-bit input. It is used in video image compression algorithms.||zip||126|
|Quantization||Describes a method of scaling values in the range -2040..2040 into the range -127..127 using the AltiVec C/C++ Programming Model. This places the data in a suitable form for variable length encoding and further compression.||zip||124|
|Dequantization||Describes a method of transforming values from the range -127..127 to -2048..2047 using the AltiVec C/C++ Programming Model. This places data in a suitable form for applying an Inverse Discrete Cosine Transform to translate images back to the spatial domain.||zip||13|
|AltiVec Technology Programming Environments Manual||Reference guide for assembler programmers||2511|
|AltiVec Technology Programming Interface Manual||Reference guide for high-level programmers||9377|