Diesel Engine Management


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Block Diagram

Diesel Engine Management

Diesel Engine Management BD1

MCU General Features

  • Two independent Power Architecture z7 cores with up to 300 MHz operation
  • Single z7 core in Lockstep with one of the main cores
  • 8M Flash
  • 512 kB total SRAM
  • 3 eTPU2 timers with 96 channels
  • eMIOS timer with 32 channels
  • Ethernet 10/100
  • Four Sigma Delta and four eQADC converters
  • Built to support functional safety (ISO 26262/ASIL-D)
  • 416 and 516 BGA
  • -40 to 125C Ta Operation


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