201905005I : i.MXRT1050 Errata Rev2 Updates
NXP Semiconductors announces an errata update for the i.MXRT1050 to revision 2. The revision history included in the updated documents provides a detailed description of the changes. Changes are summarized belowAdded following 5 errata:ERR011572: Cortex-M7: Write-Trough stores and loads may return incorrect dataERR050130: PIT: Temporary incorrect value reported in LMTR64H register in lifetimer modeERR050144: SAI: Setting FCONT = 1 when TMR > 0 may not function correctlyERR050101: USB: Endpoint conflict issue in device modeERR050194: QTMR: overflow flag and interrupt can't be generated while configured as counter up mode The i.MXRT1050 errata revision 2 is attached to this notice and can be found at:https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1050-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1050?tab=Documentation_Tab&linkline=Errata
PCN Type | Change Category | Issue Date | Effective Date |
---|---|---|---|
Customer Information Notification | Errata | 18-Jul-2019 | 19-Jul-2019 |
Reason of Change
The errata were added for additional technical clarification on some device features.
Identification of Affected Products
Product identification does not change
Anticipated Impact
No impact on form fit function reliability or quality.
Affected Parts
Part Number / 12NC | Last Time Buy Date | Last Time Delivery Date | Replacement Part |
---|---|---|---|
MIMXRT1051CVL5B (935365838557) |
- | - | - |
MIMXRT1051DVJ6B (935376003557) |
- | - | - |
MIMXRT1051DVL6B (935365839557) |
- | - | - |
MIMXRT1052CVJ5B (935376004557) |
- | - | - |
MIMXRT1052CVL5B (935365841557) |
- | - | - |
MIMXRT1052CVL5BR (935365841518) |
- | - | - |
MIMXRT1052DVJ6B (935376005557) |
- | - | - |
MIMXRT1052DVL6B (935365842557) |
- | - | - |
MIMXRT1052DVL6BR (935365842518) |
- | - | - |