202102037I : PCA8561 Datasheet 9 Clock Pulses after Power-On Requirement

Updated sections 7.3 "Starting and Resetting the PCA8561" 7.3.3 "Hardware Reset: RST Pin" and 15.1 "Power-on Reset" as follows: 7.3 Starting and Resetting the PCA8561 Added "See also application information" comment. 7.3.3 Hardware Reset: RST pin Removed "The bus interface is initialized" comment. 15.1 Power-on Reset The built-in POR block acts on the rising edge of the VDD supply voltage. Depending on the VDD rising edge in the application the POR may not work properly. Therefore to ensure proper device operation it is required to send nine clock pulses immediately after power-on (see also UM10204).

Reason of Change

The intend of these updates is to ensure that the customers send nine clock pulses immediately after power-on (see also UM10204) for the proper device operation; if the POR does not work properly.

Anticipated Impact

Data sheet revision: A new datasheet will be issued

Affected Parts