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Design Files
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2-Bit I3C-Bus Buffer with Bidirectional Voltage Level Translation
The P3B1602DP is a 2‑bit I3C buffer with integrated auto direction sensing and bidirectional voltage level translation, enabling seamless communication across mixed‑voltage systems. Optimized for I3C, I²C, and other serial buses, it supports capacitive loads up to 100 pF. Its extended one‑shot ON duration ensures strong signal drive and reliable edge performance, even across large capacitive loads and large round trip delay caused by long traces.
Product Details
Block Diagram
Features
Key Features
- Auto-direction sensing and bidirectional voltage-level translation
- Longer one-shot pulse for driving larger capacitive loads with reduced ringing and overshoot
- No power sequencing required
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Maximum frequency, Single Data Rate (SDR) data rate:
- Open-drain: 3.4MHz (6.8 Mbps)
- Push-pull: 12.5MHz (25 Mbps)
- Support I3C/I²C/SMBus interfaces (does not support clock stretching)
- Output Enable (OE) pin tolerant up to 3.63 V
- Input/output (I/O) latch-up current: 100 mA per JESD 78
Electrostatic Discharge (ESD) Protection
- Human Body Model (HBM), JEDEC standard JESD22-A114E Class 2: exceeds 2000 V
- Charged Device Model (CDM), JEDEC standard JESD22-C101E: exceeds 500 V
Packages
- TSSOP8 (3 x 3 x 1.1 mm)
Temperature Range
- Specified from -40 °C to +125 °C
Buy/Parametrics
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