8-Bit I²C-Bus and SMBus I/O Port with 2-Kbit EEPROM

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Block Diagram

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PCA9500 Block Diagram

PCA9500 Block Diagram

Block diagram: PCA9500BS, PCA9500D, PCA9500PW

Features

  • 8 general purpose input/output expander/collector
  • Drop-in replacement for PCF8574 with integrated 2-kbit EEPROM
  • Internal 256 x 8 EEPROM
  • Self timed write cycle
  • 4 byte page write operation
  • I²C-bus and SMBus interface logic
  • Internal power-on reset
  • Noise filter on SCL/SDA inputs
  • 3 address pins allowing up to 8 devices on the I²C-bus/SMBus
  • No glitch on power-up
  • Supports hot insertion
  • Power-up with all channels configured as inputs
  • Low standby current
  • Operating power supply voltage range of 2.5 V to 3.6 V
  • 5 V tolerant inputs/outputs
  • 0 Hz to 400 kHz clock frequency
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Packages offered: SO16, TSSOP16, HVQFN16

Target Applications

  • Board version tracking and configuration
  • Board health monitoring and status reporting
  • Multi-card systems in telecommunications, networking, and base station infrastructure equipment
  • Field recall and troubleshooting functions for installed boards
  • General-purpose integrated I/O with memory
  • Drop-in replacement for PCF8574 with integrated 2-kbit EEPROM
  • Bus leader sees GPIO and EEPROM as two separate devices
  • Three hardware address pins allow up to 8 PCA9500s to be located in the same I²C-bus/SMBus

Design Resources

Documentation

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