Low-Power Level Translating I²C-bus/SMBus Repeater

PCA9509A

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Block Diagram

PCA9509A Block Diagram

PCA9509A Block Diagram

Features

  • Bidirectional buffer isolates capacitance and allows 400 pF on port B of the device
  • Voltage level translation from port A (0.8 V to 1.5 V) to port B (2.3 V to 5.5 V)
  • Requires no external pull-up resistors on lower voltage port A
  • Active HIGH repeater enable input disables current mirrors and current source to reduce standby power
  • Open-drain port B inputs/outputs
  • Lock-up free operation
  • Supports arbitration and clock stretching across the repeater
  • Accommodates Standard-mode and Fast-mode I²C-bus devices and multiple controllers
  • Powered-off high-impedance I²C-bus pins
  • Operating supply voltage range of 0.8 V to 1.5 V on port A, 2.3 V to 5.5 V on port B
  • All pins are 5 V tolerant with respect to ground pin
  • 0 Hz to 400 kHz clock frequency

    Remark: The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.

  • ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Packages offered: TSSOP8, XQFN8

Design Resources

Documentation

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4 documents

Design Files

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Hardware

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